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| author | José Roberto de Souza <jose.souza@intel.com> | 2021-01-28 19:43:11 +0300 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-01-29 16:50:49 +0300 |
| commit | 5d0c938ec9cc96fc7b8abcff0ca8b2a084e9c90c (patch) | |
| tree | 9ceb126b2e31958960b566e6597c1cc372808fa6 /drivers/gpu/drm/i915/i915_drv.h | |
| parent | f0b29707baa9e6f3d7b90090fcce62d2f1023fa1 (diff) | |
| download | linux-5d0c938ec9cc96fc7b8abcff0ca8b2a084e9c90c.tar.xz | |
drm/i915/gen11+: Only load DRAM information from pcode
Up to now we were reading some DRAM information from MCHBAR register
and from pcode what is already not good but some GEN12(TGL-H and ADL-S)
platforms have MCHBAR DRAM information in different offsets.
This was notified to HW team that decided that the best alternative is
always apply the 16gb_dimm watermark adjustment for GEN12+ platforms
and read the remaning DRAM information needed to other display
programming from pcode.
So here moving the DRAM pcode function to intel_dram.c, removing
the duplicated fields from intel_qgv_info, setting and using
information from dram_info.
v2:
- bring back num_points to intel_qgv_info as num_qgv_point can be
overwritten in icl_get_qgv_points()
- add gen12_get_dram_info() and simplify gen11_get_dram_info()
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210128164312.91160-2-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 01e11ed7cf9d..eccaf2a58ef3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1135,6 +1135,7 @@ struct drm_i915_private { INTEL_DRAM_LPDDR3, INTEL_DRAM_LPDDR4 } type; + u8 num_qgv_points; } dram_info; struct intel_bw_info { |