diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-04-16 20:10:06 +0300 |
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committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-04-21 01:26:17 +0300 |
commit | 578e6edec45cf883681ae4e0b0d53ec62460af93 (patch) | |
tree | 09efe9bfaf5c81072b6cfee9b002d143efc9bad0 /drivers/gpu/drm/i915/intel_pm.c | |
parent | 77531b0ef621b62e5164d33411106a3415eb7b67 (diff) | |
download | linux-578e6edec45cf883681ae4e0b0d53ec62460af93.tar.xz |
drm/i915: Store dbuf slice mask in device info
Let's just store the dbuf slice information as a bitmask
in the device info. Makes life a little easier later.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210416171011.19012-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ad3344ec6284..ca4710a211c9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3637,7 +3637,7 @@ bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv) u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv) { int i; - int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; + int num_slices = intel_dbuf_num_slices(dev_priv); u8 enabled_slices_mask = 0; for (i = 0; i < num_slices; i++) { @@ -4033,10 +4033,15 @@ static int intel_dbuf_size(struct drm_i915_private *dev_priv) return INTEL_INFO(dev_priv)->dbuf.size; } +int intel_dbuf_num_slices(struct drm_i915_private *dev_priv) +{ + return hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask); +} + static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv) { return intel_dbuf_size(dev_priv) / - INTEL_INFO(dev_priv)->dbuf.num_slices; + intel_dbuf_num_slices(dev_priv); } static void @@ -4063,7 +4068,7 @@ u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv, { u32 slice_mask = 0; u16 ddb_size = intel_dbuf_size(dev_priv); - int num_slices = INTEL_INFO(dev_priv)->dbuf.num_slices; + int num_slices = intel_dbuf_num_slices(dev_priv); u16 slice_size = ddb_size / num_slices; u16 start_slice; u16 end_slice; @@ -5821,7 +5826,7 @@ skl_compute_ddb(struct intel_atomic_state *state) "Enabled dbuf slices 0x%x -> 0x%x (out of %d dbuf slices)\n", old_dbuf_state->enabled_slices, new_dbuf_state->enabled_slices, - INTEL_INFO(dev_priv)->dbuf.num_slices); + intel_dbuf_num_slices(dev_priv)); } for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { |