diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2021-05-14 18:37:09 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-05-15 05:48:38 +0300 |
| commit | a8a56da71a13358528446f4903f6c939dd1d6a1d (patch) | |
| tree | e05cb30d45fb1e7dca7f2646784fe697180aca9d /drivers/gpu/drm/i915/intel_pm.c | |
| parent | b2c6eaf27b508ce5f63e59e3cfb6ae0231685eee (diff) | |
| download | linux-a8a56da71a13358528446f4903f6c939dd1d6a1d.tar.xz | |
drm/i915/adl_p: Implement Wa_22011091694
Adding a new hook to ADL-P just to avoid another platform check in
gen12lp_init_clock_gating() but also open to it.
BSpec: 54369
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514153711.2359617-18-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ef2d1fa60f04..32f7806ea12c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7141,6 +7141,14 @@ static void gen12lp_init_clock_gating(struct drm_i915_private *dev_priv) CLKREQ_POLICY_MEM_UP_OVRD, 0); } +static void adlp_init_clock_gating(struct drm_i915_private *dev_priv) +{ + gen12lp_init_clock_gating(dev_priv); + + /* Wa_22011091694:adlp */ + intel_de_rmw(dev_priv, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); +} + static void dg1_init_clock_gating(struct drm_i915_private *dev_priv) { gen12lp_init_clock_gating(dev_priv); @@ -7618,7 +7626,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) */ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { - if (IS_DG1(dev_priv)) + if (IS_ALDERLAKE_P(dev_priv)) + dev_priv->display.init_clock_gating = adlp_init_clock_gating; + else if (IS_DG1(dev_priv)) dev_priv->display.init_clock_gating = dg1_init_clock_gating; else if (IS_GEN(dev_priv, 12)) dev_priv->display.init_clock_gating = gen12lp_init_clock_gating; |