diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-05-03 22:31:42 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-05-06 17:53:28 +0300 |
| commit | 8f91cfd2e7ff7714887ab7bbb0319268e8c92bcf (patch) | |
| tree | 01e0bb73512333223847da85482c3a23fd050b13 /drivers/gpu/drm/i915/intel_runtime_pm.c | |
| parent | c91a45f421e358c1d7899e0ba4e00638c06111af (diff) | |
| download | linux-8f91cfd2e7ff7714887ab7bbb0319268e8c92bcf.tar.xz | |
drm/i915: Replace intel_ddi_pll_init()
intel_ddi_pll_init() is an anachronism. Rename it to
hsw_assert_cdclk() and move it to the power domain init code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190503193143.28240-1-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_runtime_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_runtime_pm.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 1b7ea6bab613..b1fd2ae99199 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3625,6 +3625,23 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv) I915_WRITE(MBUS_ABOX_CTL, val); } +static void hsw_assert_cdclk(struct drm_i915_private *dev_priv) +{ + u32 val = I915_READ(LCPLL_CTL); + + /* + * The LCPLL register should be turned on by the BIOS. For now + * let's just check its state and print errors in case + * something is wrong. Don't even try to turn it on. + */ + + if (val & LCPLL_CD_SOURCE_FCLK) + DRM_ERROR("CDCLK source is not LCPLL\n"); + + if (val & LCPLL_PLL_DISABLE) + DRM_ERROR("LCPLL is disabled\n"); +} + static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, bool enable) { @@ -4085,7 +4102,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *i915, bool resume) mutex_unlock(&power_domains->lock); assert_ved_power_gated(i915); assert_isp_power_gated(i915); - } else if (IS_IVYBRIDGE(i915) || INTEL_GEN(i915) >= 7) { + } else if (IS_BROADWELL(i915) || IS_HASWELL(i915)) { + hsw_assert_cdclk(i915); + intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); + } else if (IS_IVYBRIDGE(i915)) { intel_pch_reset_handshake(i915, !HAS_PCH_NOP(i915)); } |