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| author | Tanmay Shah <tanmay@codeaurora.org> | 2020-09-26 07:50:48 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2020-11-04 19:26:25 +0300 |
| commit | 6625e2637d93d2f52ef0d17656f21bfa2cb4983a (patch) | |
| tree | 228c177671bd2a16534188cc1d1da2bd435c8477 /drivers/gpu/drm/msm/dp/dp_ctrl.c | |
| parent | c7314613226a05758bb8c5a350521959c7db4ea9 (diff) | |
| download | linux-6625e2637d93d2f52ef0d17656f21bfa2cb4983a.tar.xz | |
drm/msm/dp: DisplayPort PHY compliance tests fixup
Bandwidth code was being used as test link rate. Fix this by converting
bandwidth code to test link rate
Do not reset voltage and pre-emphasis level during IRQ HPD attention
interrupt. Also fix pre-emphasis parsing during test link status process
Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets")
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dp/dp_ctrl.c')
| -rw-r--r-- | drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index 2e3e1917351f..872b12689e31 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -1643,9 +1643,6 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) if (rc) return rc; - ctrl->link->phy_params.p_level = 0; - ctrl->link->phy_params.v_level = 0; - while (--link_train_max_retries && !atomic_read(&ctrl->dp_ctrl.aborted)) { rc = dp_ctrl_reinitialize_mainlink(ctrl); |