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authorStephen Boyd <swboyd@chromium.org>2020-09-10 03:49:02 +0300
committerRob Clark <robdclark@chromium.org>2020-09-15 20:54:35 +0300
commit937f941ca06f2f3ab64baebf31be2c16d57ae7b8 (patch)
tree3e1729d78c6584d60f47280bdec910af16ff9ce5 /drivers/gpu/drm/msm/dp/dp_ctrl.c
parentab205927592be25ddef5db10344925b389fd4344 (diff)
downloadlinux-937f941ca06f2f3ab64baebf31be2c16d57ae7b8.tar.xz
drm/msm/dp: Use qmp phy for DP PLL and PHY
Make the necessary changes to the DP driver to use the qmp phy from the common phy framework instead of rolling our own in the drm subsystem. This also removes the PLL code and adds proper includes so things build. Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Cc: Chandan Uddaraju <chandanu@codeaurora.org> Cc: Vara Reddy <varar@codeaurora.org> Cc: Tanmay Shah <tanmay@codeaurora.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Manu Gautam <mgautam@codeaurora.org> Cc: Sandeep Maheswaram <sanm@codeaurora.org> Cc: Douglas Anderson <dianders@chromium.org> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jonathan Marek <jonathan@marek.ca> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Cc: Rob Clark <robdclark@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dp/dp_ctrl.c')
-rw-r--r--drivers/gpu/drm/msm/dp/dp_ctrl.c48
1 files changed, 34 insertions, 14 deletions
diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 70b0e06953f6..2e3e1917351f 100644
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -8,8 +8,11 @@
#include <linux/types.h>
#include <linux/completion.h>
#include <linux/delay.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-dp.h>
#include <drm/drm_fixed.h>
#include <drm/drm_dp_helper.h>
+#include <drm/drm_print.h>
#include "dp_reg.h"
#include "dp_ctrl.h"
@@ -1302,7 +1305,7 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,
}
static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
- enum dp_pm_type module, char *name, u32 rate)
+ enum dp_pm_type module, char *name, unsigned long rate)
{
u32 num = ctrl->parser->mp[module].num_clk;
struct dss_clk *cfg = ctrl->parser->mp[module].clk_config;
@@ -1312,23 +1315,29 @@ static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl,
cfg++;
}
- DRM_DEBUG_DP("setting rate=%d on clk=%s\n", rate, name);
+ DRM_DEBUG_DP("setting rate=%lu on clk=%s\n", rate, name);
if (num)
cfg->rate = rate;
else
- DRM_ERROR("%s clock doesn't exit to set rate %d\n",
+ DRM_ERROR("%s clock doesn't exit to set rate %lu\n",
name, rate);
}
static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
{
int ret = 0;
+ struct dp_io *dp_io = &ctrl->parser->io;
+ struct phy *phy = dp_io->phy;
+ struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
- dp_power_set_link_clk_parent(ctrl->power);
-
+ opts_dp->lanes = ctrl->link->link_params.num_lanes;
+ opts_dp->link_rate = ctrl->link->link_params.rate / 100;
dp_ctrl_set_clock_rate(ctrl, DP_CTRL_PM, "ctrl_link",
- ctrl->link->link_params.rate);
+ ctrl->link->link_params.rate * 1000);
+
+ phy_configure(phy, &dp_io->phy_opts);
+ phy_power_on(phy);
ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true);
if (ret)
@@ -1345,7 +1354,7 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
int ret = 0;
dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
- ctrl->dp_ctrl.pixel_rate);
+ ctrl->dp_ctrl.pixel_rate * 1000);
ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
if (ret)
@@ -1360,6 +1369,8 @@ static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip)
{
struct dp_ctrl_private *ctrl;
+ struct dp_io *dp_io;
+ struct phy *phy;
if (!dp_ctrl) {
DRM_ERROR("Invalid input data\n");
@@ -1367,11 +1378,13 @@ int dp_ctrl_host_init(struct dp_ctrl *dp_ctrl, bool flip)
}
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+ dp_io = &ctrl->parser->io;
+ phy = dp_io->phy;
ctrl->dp_ctrl.orientation = flip;
- dp_catalog_ctrl_usb_reset(ctrl->catalog, flip);
dp_catalog_ctrl_phy_reset(ctrl->catalog);
+ phy_init(phy);
dp_catalog_ctrl_enable_irq(ctrl->catalog, true);
return 0;
@@ -1420,10 +1433,13 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl)
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
{
int ret = 0;
+ struct dp_io *dp_io = &ctrl->parser->io;
+ struct phy *phy = dp_io->phy;
+ struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
- dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog,
- ctrl->dp_ctrl.orientation, ctrl->link->link_params.num_lanes);
+ opts_dp->lanes = ctrl->link->link_params.num_lanes;
+ phy_configure(phy, &dp_io->phy_opts);
/*
* Disable and re-enable the mainlink clock since the
* link clock might have been adjusted as part of the
@@ -1434,6 +1450,7 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
DRM_ERROR("Failed to disable clocks. ret=%d\n", ret);
return ret;
}
+ phy_power_off(phy);
/* hw recommended delay before re-enabling clocks */
msleep(20);
@@ -1622,10 +1639,6 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
ctrl->link->link_params.rate,
ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
- dp_catalog_ctrl_phy_lane_cfg(ctrl->catalog,
- ctrl->dp_ctrl.orientation,
- ctrl->link->link_params.num_lanes);
-
rc = dp_ctrl_enable_mainlink_clocks(ctrl);
if (rc)
return rc;
@@ -1763,12 +1776,16 @@ end:
int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
+ struct dp_io *dp_io;
+ struct phy *phy;
int ret = 0;
if (!dp_ctrl)
return -EINVAL;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
+ dp_io = &ctrl->parser->io;
+ phy = dp_io->phy;
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
@@ -1783,6 +1800,9 @@ int dp_ctrl_off(struct dp_ctrl *dp_ctrl)
DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret);
}
+ phy_power_off(phy);
+ phy_exit(phy);
+
DRM_DEBUG_DP("DP off done\n");
return ret;
}