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| author | Tanmay Shah <tanmay@codeaurora.org> | 2020-09-26 07:50:48 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2020-11-04 19:26:25 +0300 |
| commit | 6625e2637d93d2f52ef0d17656f21bfa2cb4983a (patch) | |
| tree | 228c177671bd2a16534188cc1d1da2bd435c8477 /drivers/gpu/drm/msm/dp/dp_link.h | |
| parent | c7314613226a05758bb8c5a350521959c7db4ea9 (diff) | |
| download | linux-6625e2637d93d2f52ef0d17656f21bfa2cb4983a.tar.xz | |
drm/msm/dp: DisplayPort PHY compliance tests fixup
Bandwidth code was being used as test link rate. Fix this by converting
bandwidth code to test link rate
Do not reset voltage and pre-emphasis level during IRQ HPD attention
interrupt. Also fix pre-emphasis parsing during test link status process
Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Fixes: 8ede2ecc3e5e ("drm/msm/dp: Add DP compliance tests on Snapdragon Chipsets")
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dp/dp_link.h')
| -rw-r--r-- | drivers/gpu/drm/msm/dp/dp_link.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_link.h index 49811b6221e5..9dd4dd926530 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.h +++ b/drivers/gpu/drm/msm/dp/dp_link.h @@ -135,6 +135,7 @@ static inline u32 dp_link_bit_depth_to_bpc(u32 tbd) } } +void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link); u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp); int dp_link_process_request(struct dp_link *dp_link); int dp_link_get_colorimetry_config(struct dp_link *dp_link); |