diff options
| author | Stephen Boyd <swboyd@chromium.org> | 2020-09-10 03:49:02 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@chromium.org> | 2020-09-15 20:54:35 +0300 |
| commit | 937f941ca06f2f3ab64baebf31be2c16d57ae7b8 (patch) | |
| tree | 3e1729d78c6584d60f47280bdec910af16ff9ce5 /drivers/gpu/drm/msm/dp/dp_reg.h | |
| parent | ab205927592be25ddef5db10344925b389fd4344 (diff) | |
| download | linux-937f941ca06f2f3ab64baebf31be2c16d57ae7b8.tar.xz | |
drm/msm/dp: Use qmp phy for DP PLL and PHY
Make the necessary changes to the DP driver to use the qmp phy from the
common phy framework instead of rolling our own in the drm subsystem.
This also removes the PLL code and adds proper includes so things build.
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm/msm/dp/dp_reg.h')
| -rw-r--r-- | drivers/gpu/drm/msm/dp/dp_reg.h | 213 |
1 files changed, 0 insertions, 213 deletions
diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index de32f6204a50..43042ff90a19 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -6,22 +6,6 @@ #ifndef _DP_REG_H_ #define _DP_REG_H_ -/* DP PHY Register Regions */ -#define REG_DP_PHY_REGION_BASE (0x088ea000) -#define REG_DP_PHY_REGION_SIZE (0x00000C00) - -#define REG_USB3_DP_COM_REGION_BASE (0x088e8000) -#define REG_USB3_DP_COM_REGION_SIZE (0x00000020) - -#define DP_PHY_PLL_OFFSET (0x00000000) -#define DP_PHY_PLL_SIZE (0x00000200) -#define DP_PHY_REG_OFFSET (0x00000A00) -#define DP_PHY_REG_SIZE (0x00000200) -#define DP_PHY_LN_TX0_OFFSET (0x00000200) -#define DP_PHY_LN_TX0_SIZE (0x00000200) -#define DP_PHY_LN_TX1_OFFSET (0x00000600) -#define DP_PHY_LN_TX1_SIZE (0x00000200) - /* DP_TX Registers */ #define REG_DP_HW_VERSION (0x00000000) @@ -290,183 +274,10 @@ #define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) -/*DP PHY Register offsets */ -#define REG_DP_PHY_REVISION_ID0 (0x00000000) -#define REG_DP_PHY_REVISION_ID1 (0x00000004) -#define REG_DP_PHY_REVISION_ID2 (0x00000008) -#define REG_DP_PHY_REVISION_ID3 (0x0000000C) - -#define REG_DP_PHY_CFG (0x00000010) - -#define REG_DP_PHY_PD_CTL (0x00000018) -#define DP_PHY_PD_CTL_PWRDN (0x00000001) -#define DP_PHY_PD_CTL_PSR_PWRDN (0x00000002) -#define DP_PHY_PD_CTL_AUX_PWRDN (0x00000004) -#define DP_PHY_PD_CTL_LANE_0_1_PWRDN (0x00000008) -#define DP_PHY_PD_CTL_LANE_2_3_PWRDN (0x00000010) -#define DP_PHY_PD_CTL_PLL_PWRDN (0x00000020) -#define DP_PHY_PD_CTL_DP_CLAMP_EN (0x00000040) - -#define REG_DP_PHY_MODE (0x0000001C) - -#define REG_DP_PHY_AUX_CFG0 (0x00000020) -#define REG_DP_PHY_AUX_CFG1 (0x00000024) -#define REG_DP_PHY_AUX_CFG2 (0x00000028) -#define REG_DP_PHY_AUX_CFG3 (0x0000002C) -#define REG_DP_PHY_AUX_CFG4 (0x00000030) -#define REG_DP_PHY_AUX_CFG5 (0x00000034) -#define REG_DP_PHY_AUX_CFG6 (0x00000038) -#define REG_DP_PHY_AUX_CFG7 (0x0000003C) -#define REG_DP_PHY_AUX_CFG8 (0x00000040) -#define REG_DP_PHY_AUX_CFG9 (0x00000044) - -#define REG_DP_PHY_AUX_INTERRUPT_MASK (0x00000048) -#define PHY_AUX_STOP_ERR_MASK (0x00000001) -#define PHY_AUX_DEC_ERR_MASK (0x00000002) -#define PHY_AUX_SYNC_ERR_MASK (0x00000004) -#define PHY_AUX_ALIGN_ERR_MASK (0x00000008) -#define PHY_AUX_REQ_ERR_MASK (0x00000010) - - #define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) #define REG_DP_PHY_AUX_BIST_CFG (0x00000050) #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) -#define REG_DP_PHY_VCO_DIV 0x0064 -#define REG_DP_PHY_TX0_TX1_LANE_CTL 0x006C -#define REG_DP_PHY_TX2_TX3_LANE_CTL 0x0088 - -#define REG_DP_PHY_SPARE0 (0x00AC) -#define DP_PHY_SPARE0_MASK (0x000F) -#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT (0x0004) - -#define REG_DP_PHY_STATUS (0x00C0) - -/* Tx registers */ -#define REG_DP_PHY_TXn_BIST_MODE_LANENO 0x0000 -#define REG_DP_PHY_TXn_CLKBUF_ENABLE 0x0008 - -#define REG_DP_PHY_TXn_TX_EMP_POST1_LVL 0x000C -#define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001F -#define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 - -#define REG_DP_PHY_TXn_TX_DRV_LVL 0x001C -#define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001F -#define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 - -#define REG_DP_PHY_TXn_RESET_TSYNC_EN 0x0024 -#define REG_DP_PHY_TXn_PRE_STALL_LDO_BOOST_EN 0x0028 -#define REG_DP_PHY_TXn_TX_BAND 0x002C -#define REG_DP_PHY_TXn_SLEW_CNTL 0x0030 -#define REG_DP_PHY_TXn_INTERFACE_SELECT 0x0034 - -#define REG_DP_PHY_TXn_RES_CODE_LANE_TX 0x003C -#define REG_DP_PHY_TXn_RES_CODE_LANE_RX 0x0040 -#define REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_TX 0x0044 -#define REG_DP_PHY_TXn_RES_CODE_LANE_OFFSET_RX 0x0048 - -#define REG_DP_PHY_TXn_DEBUG_BUS_SEL 0x0058 -#define REG_DP_PHY_TXn_TRANSCEIVER_BIAS_EN 0x005C -#define REG_DP_PHY_TXn_HIGHZ_DRVR_EN 0x0060 -#define REG_DP_PHY_TXn_TX_POL_INV 0x0064 -#define REG_DP_PHY_TXn_PARRATE_REC_DETECT_IDLE_EN 0x0068 - -#define REG_DP_PHY_TXn_LANE_MODE_1 0x008C - -#define REG_DP_PHY_TXn_TRAN_DRVR_EMP_EN 0x00C0 -#define REG_DP_PHY_TXn_TX_INTERFACE_MODE 0x00C4 - -#define REG_DP_PHY_TXn_VMODE_CTRL1 0x00F0 - -/* PLL register offset */ -#define QSERDES_COM_ATB_SEL1 0x0000 -#define QSERDES_COM_ATB_SEL2 0x0004 -#define QSERDES_COM_FREQ_UPDATE 0x0008 -#define QSERDES_COM_BG_TIMER 0x000C -#define QSERDES_COM_SSC_EN_CENTER 0x0010 -#define QSERDES_COM_SSC_ADJ_PER1 0x0014 -#define QSERDES_COM_SSC_ADJ_PER2 0x0018 -#define QSERDES_COM_SSC_PER1 0x001C -#define QSERDES_COM_SSC_PER2 0x0020 -#define QSERDES_COM_SSC_STEP_SIZE1 0x0024 -#define QSERDES_COM_SSC_STEP_SIZE2 0x0028 -#define QSERDES_COM_POST_DIV 0x002C -#define QSERDES_COM_POST_DIV_MUX 0x0030 - -#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0034 -#define QSERDES_COM_BIAS_EN 0x0001 -#define QSERDES_COM_BIAS_EN_MUX 0x0002 -#define QSERDES_COM_CLKBUF_R_EN 0x0004 -#define QSERDES_COM_CLKBUF_L_EN 0x0008 -#define QSERDES_COM_EN_SYSCLK_TX_SEL 0x0010 -#define QSERDES_COM_CLKBUF_RX_DRIVE_L 0x0020 -#define QSERDES_COM_CLKBUF_RX_DRIVE_R 0x0040 - -#define QSERDES_COM_CLK_ENABLE1 0x0038 -#define QSERDES_COM_SYS_CLK_CTRL 0x003C -#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x0040 -#define QSERDES_COM_PLL_EN 0x0044 -#define QSERDES_COM_PLL_IVCO 0x0048 -#define QSERDES_COM_CMN_IETRIM 0x004C -#define QSERDES_COM_CMN_IPTRIM 0x0050 - -#define QSERDES_COM_CP_CTRL_MODE0 0x0060 -#define QSERDES_COM_CP_CTRL_MODE1 0x0064 -#define QSERDES_COM_PLL_RCTRL_MODE0 0x0068 -#define QSERDES_COM_PLL_RCTRL_MODE1 0x006C -#define QSERDES_COM_PLL_CCTRL_MODE0 0x0070 -#define QSERDES_COM_PLL_CCTRL_MODE1 0x0074 -#define QSERDES_COM_PLL_CNTRL 0x0078 -#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x007C -#define QSERDES_COM_SYSCLK_EN_SEL 0x0080 -#define QSERDES_COM_CML_SYSCLK_SEL 0x0084 -#define QSERDES_COM_RESETSM_CNTRL 0x0088 -#define QSERDES_COM_RESETSM_CNTRL2 0x008C -#define QSERDES_COM_LOCK_CMP_EN 0x0090 -#define QSERDES_COM_LOCK_CMP_CFG 0x0094 -#define QSERDES_COM_LOCK_CMP1_MODE0 0x0098 -#define QSERDES_COM_LOCK_CMP2_MODE0 0x009C -#define QSERDES_COM_LOCK_CMP3_MODE0 0x00A0 - -#define QSERDES_COM_DEC_START_MODE0 0x00B0 -#define QSERDES_COM_DEC_START_MODE1 0x00B4 -#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x00B8 -#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x00BC -#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x00C0 -#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x00C4 -#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x00C8 -#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x00CC -#define QSERDES_COM_INTEGLOOP_INITVAL 0x00D0 -#define QSERDES_COM_INTEGLOOP_EN 0x00D4 -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x00D8 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00DC -#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x00E0 -#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x00E4 -#define QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x00E8 -#define QSERDES_COM_VCO_TUNE_CTRL 0x00EC -#define QSERDES_COM_VCO_TUNE_MAP 0x00F0 - -#define QSERDES_COM_CMN_STATUS 0x0124 -#define QSERDES_COM_RESET_SM_STATUS 0x0128 - -#define QSERDES_COM_CLK_SEL 0x0138 -#define QSERDES_COM_HSCLK_SEL 0x013C - -#define QSERDES_COM_CORECLK_DIV_MODE0 0x0148 - -#define QSERDES_COM_SW_RESET 0x0150 -#define QSERDES_COM_CORE_CLK_EN 0x0154 -#define QSERDES_COM_C_READY_STATUS 0x0158 -#define QSERDES_COM_CMN_CONFIG 0x015C - -#define QSERDES_COM_SVS_MODE_CLK_SEL 0x0164 - -/* DP MMSS_CC registers */ -#define MMSS_DP_LINK_CMD_RCGR (0x0138) -#define MMSS_DP_LINK_CFG_RCGR (0x013C) -#define MMSS_DP_PIXEL_M (0x01B4) -#define MMSS_DP_PIXEL_N (0x01B8) - /* DP HDCP 1.3 registers */ #define DP_HDCP_CTRL (0x0A0) #define DP_HDCP_STATUS (0x0A4) @@ -492,28 +303,4 @@ #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) -/* USB3 DP COM registers */ -#define REG_USB3_DP_COM_RESET_OVRD_CTRL (0x1C) -#define USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET (0x01) -#define USB3_DP_COM_OVRD_CTRL_SW_DPPHY_RESET_MUX (0x02) -#define USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET (0x04) -#define USB3_DP_COM_OVRD_CTRL_SW_USB3PHY_RESET_MUX (0x08) - -#define REG_USB3_DP_COM_PHY_MODE_CTRL (0x00) -#define USB3_DP_COM_PHY_MODE_DP (0x03) - -#define REG_USB3_DP_COM_SW_RESET (0x04) -#define USB3_DP_COM_SW_RESET_SET (0x01) - -#define REG_USB3_DP_COM_TYPEC_CTRL (0x10) -#define USB3_DP_COM_TYPEC_CTRL_PORTSEL (0x01) -#define USB3_DP_COM_TYPEC_CTRL_PORTSEL_MUX (0x02) - -#define REG_USB3_DP_COM_SWI_CTRL (0x0c) - -#define REG_USB3_DP_COM_POWER_DOWN_CTRL (0x08) -#define USB3_DP_COM_POWER_DOWN_CTRL_SW_PWRDN (0x01) - - - #endif /* _DP_REG_H_ */ |