summaryrefslogtreecommitdiff
path: root/drivers/irqchip/Makefile
diff options
context:
space:
mode:
authorMinghuan Lian <Minghuan.Lian@nxp.com>2016-03-23 14:08:20 +0300
committerMarc Zyngier <marc.zyngier@arm.com>2016-05-04 11:58:04 +0300
commitb8f3ebe630a4f1b4ff9340103d3b565ad5d78d43 (patch)
tree9072b01dd90206a5908274e8d91337c1ca41badf /drivers/irqchip/Makefile
parent5e79cb29ddbd1d354398308309337ba013245469 (diff)
downloadlinux-b8f3ebe630a4f1b4ff9340103d3b565ad5d78d43.tar.xz
irqchip: Add Layerscape SCFG MSI controller support
Some kind of Freescale Layerscape SoC provides a MSI implementation which uses two SCFG registers MSIIR and MSIR to support 32 MSI interrupts for each PCIe controller. The patch is to support it. Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Tested-by: Alexander Stein <alexander.stein@systec-electronic.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/Makefile')
-rw-r--r--drivers/irqchip/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e354b00c173d..8cedf9060565 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -66,3 +66,4 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
+obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o