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authorSakari Ailus <sakari.ailus@linux.intel.com>2020-08-07 12:00:59 +0300
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>2020-12-07 17:57:07 +0300
commitc4c0b222720d413cc866275a0200019eb3c58f33 (patch)
tree9b3469ff28633d2ef2fcdd1df09ba8794e18ba51 /drivers/media
parent4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3c (diff)
downloadlinux-c4c0b222720d413cc866275a0200019eb3c58f33.tar.xz
media: ccs-pll: Support two cycles per pixel on OP domain
The l parameter defines the number of clock cycles to process a single pixel per OP lane. It is calculated based on a new register op_bits_per_lane. Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/i2c/ccs-pll.c19
-rw-r--r--drivers/media/i2c/ccs-pll.h2
-rw-r--r--drivers/media/i2c/ccs/ccs-core.c1
3 files changed, 16 insertions, 6 deletions
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 62939ca5b8e2..60ab0c043c7a 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -162,7 +162,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
const struct ccs_pll_branch_limits_bk *op_lim_bk,
struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul,
- uint32_t div)
+ uint32_t div, uint32_t l)
{
uint32_t sys_div;
uint32_t best_pix_div = INT_MAX >> 1;
@@ -252,10 +252,15 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
* op_pll_fr->pll_multiplier;
- op_pll_bk->pix_clk_div = pll->bits_per_pixel
- * pll->op_lanes / pll->csi2.lanes;
+ if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)
+ op_pll_bk->pix_clk_div = pll->bits_per_pixel
+ * pll->op_lanes / pll->csi2.lanes / l;
+ else
+ op_pll_bk->pix_clk_div = pll->bits_per_pixel / l;
+
op_pll_bk->pix_clk_freq_hz =
op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
+
dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
@@ -291,7 +296,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div
* op_pll_bk->sys_clk_div * pll->scale_n
- * pll->vt_lanes,
+ * pll->vt_lanes * l,
pll->op_lanes * vt_op_binning_div
* pll->scale_m);
@@ -406,6 +411,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
uint16_t min_op_pre_pll_clk_div;
uint16_t max_op_pre_pll_clk_div;
uint32_t mul, div;
+ uint32_t l = (!pll->op_bits_per_lane ||
+ pll->op_bits_per_lane >= pll->bits_per_pixel) ? 1 : 2;
uint32_t i;
int rval = -EINVAL;
@@ -444,7 +451,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
pll->pixel_rate_csi =
op_pll_bk->pix_clk_freq_hz
* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
- pll->csi2.lanes : 1);
+ pll->csi2.lanes : 1) / l;
/* Figure out limits for OP pre-pll divider based on extclk */
dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
@@ -482,7 +489,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
(pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 :
2 - (op_pll_fr->pre_pll_clk_div & 1)) {
rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll,
- op_pll_fr, op_pll_bk, mul, div);
+ op_pll_fr, op_pll_bk, mul, div, l);
if (rval)
continue;
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index 807ae7250aa2..207822cf2324 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -76,6 +76,7 @@ struct ccs_pll_branch_bk {
* @scale_m: Downscaling factor, M component, [16, max] (input)
* @scale_n: Downscaling factor, N component, typically 16 (input)
* @bits_per_pixel: Bits per pixel on the output data bus (input)
+ * @op_bits_per_lane: Number of bits per OP lane (input)
* @flags: CCS_PLL_FLAG_* (input)
* @link_freq: Chosen link frequency (input)
* @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock
@@ -100,6 +101,7 @@ struct ccs_pll {
uint8_t scale_m;
uint8_t scale_n;
uint8_t bits_per_pixel;
+ uint8_t op_bits_per_lane;
uint16_t flags;
uint32_t link_freq;
uint32_t ext_clk_freq_hz;
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 6c2b8a4259fd..d39da0f31d90 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -3222,6 +3222,7 @@ static int ccs_probe(struct i2c_client *client)
if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
+ sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);