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authorThierry Reding <treding@nvidia.com>2021-06-02 19:32:51 +0300
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-06-03 22:49:40 +0300
commit4f1ac76e5ed9436ff3cd72e308527fd1e90b193a (patch)
treeb088cc04ad067a71bd684ee5bc16b9f3ddb2193b /drivers/memory
parenteeafcdea46936d84e2016e7d965f0b79e75ffd9e (diff)
downloadlinux-4f1ac76e5ed9436ff3cd72e308527fd1e90b193a.tar.xz
memory: tegra: Consolidate register fields
Subsequent patches will add more register fields to the tegra_mc_client structure, so consolidate all register field definitions into a common sub-structure for coherency. Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/tegra/mc.c10
-rw-r--r--drivers/memory/tegra/tegra114.c1244
-rw-r--r--drivers/memory/tegra/tegra124.c1304
-rw-r--r--drivers/memory/tegra/tegra210.c1432
-rw-r--r--drivers/memory/tegra/tegra30.c1291
5 files changed, 2910 insertions, 2371 deletions
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index e58c3e5baea0..b7e104bf6614 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -316,13 +316,13 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
/* write latency allowance defaults */
for (i = 0; i < mc->soc->num_clients; i++) {
- const struct tegra_mc_la *la = &mc->soc->clients[i].la;
+ const struct tegra_mc_client *client = &mc->soc->clients[i];
u32 value;
- value = mc_readl(mc, la->reg);
- value &= ~(la->mask << la->shift);
- value |= (la->def & la->mask) << la->shift;
- mc_writel(mc, value, la->reg);
+ value = mc_readl(mc, client->regs.la.reg);
+ value &= ~(client->regs.la.mask << client->regs.la.shift);
+ value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift;
+ mc_writel(mc, value, client->regs.la.reg);
}
/* latch new values */
diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c
index ed376ba2d2fe..1f2054d34bf5 100644
--- a/drivers/memory/tegra/tegra114.c
+++ b/drivers/memory/tegra/tegra114.c
@@ -15,883 +15,1013 @@ static const struct tegra_mc_client tegra114_mc_clients[] = {
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
- .la = {
- .reg = 0x34c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0,
+ .regs = {
+ .la = {
+ .reg = 0x34c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0,
+ },
},
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
}, {
.id = 0x09,
.name = "eppup",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x228,
- .bit = 9,
- },
- .la = {
- .reg = 0x300,
- .shift = 0,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
}, {
.id = 0x0a,
.name = "g2pr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 10,
- },
- .la = {
- .reg = 0x308,
- .shift = 0,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
}, {
.id = 0x0b,
.name = "g2sr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 11,
- },
- .la = {
- .reg = 0x308,
- .shift = 16,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x68,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x68,
+ },
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x68,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x68,
+ },
},
}, {
.id = 0x12,
.name = "fdcdrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 18,
- },
- .la = {
- .reg = 0x334,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x13,
.name = "fdcdrd2",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 19,
- },
- .la = {
- .reg = 0x33c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x33c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x14,
.name = "g2dr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 20,
- },
- .la = {
- .reg = 0x30c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x18,
.name = "idxsrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 24,
- },
- .la = {
- .reg = 0x334,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0b,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0b,
+ },
},
}, {
.id = 0x1c,
.name = "msencsrd",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0xe8,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xe8,
+ },
},
}, {
.id = 0x20,
.name = "texl2srd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 0,
- },
- .la = {
- .reg = 0x338,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 2,
- },
- .la = {
- .reg = 0x354,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 3,
- },
- .la = {
- .reg = 0x354,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 4,
- },
- .la = {
- .reg = 0x358,
- .shift = 0,
- .mask = 0xff,
- .def = 0xb8,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xb8,
+ },
},
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 5,
- },
- .la = {
- .reg = 0x358,
- .shift = 16,
- .mask = 0xff,
- .def = 0xee,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xee,
+ },
},
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x28,
.name = "eppu",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 8,
- },
- .la = {
- .reg = 0x300,
- .shift = 16,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
}, {
.id = 0x29,
.name = "eppv",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 9,
- },
- .la = {
- .reg = 0x304,
- .shift = 0,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
}, {
.id = 0x2a,
.name = "eppy",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 10,
- },
- .la = {
- .reg = 0x304,
- .shift = 16,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
}, {
.id = 0x2b,
.name = "msencswr",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x2c,
.name = "viwsb",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 12,
- },
- .la = {
- .reg = 0x364,
- .shift = 0,
- .mask = 0xff,
- .def = 0x47,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x364,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x47,
+ },
},
}, {
.id = 0x2d,
.name = "viwu",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 13,
- },
- .la = {
- .reg = 0x368,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x2e,
.name = "viwv",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 14,
- },
- .la = {
- .reg = 0x368,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x2f,
.name = "viwy",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 15,
- },
- .la = {
- .reg = 0x36c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x47,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x36c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x47,
+ },
},
}, {
.id = 0x30,
.name = "g2dw",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x22c,
- .bit = 16,
- },
- .la = {
- .reg = 0x30c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x9,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x9,
+ },
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
}, {
.id = 0x33,
.name = "fdcdwr",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 19,
- },
- .la = {
- .reg = 0x338,
- .shift = 16,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x34,
.name = "fdcdwr2",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 20,
- },
- .la = {
- .reg = 0x340,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x340,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x25,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x25,
+ },
},
}, {
.id = 0x37,
.name = "ispw",
.swgroup = TEGRA_SWGROUP_ISP,
- .smmu = {
- .reg = 0x22c,
- .bit = 23,
- },
- .la = {
- .reg = 0x31c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x31c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0xe8,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xe8,
+ },
},
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 30,
- },
- .la = {
- .reg = 0x35c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 31,
- },
- .la = {
- .reg = 0x35c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 0,
- },
- .la = {
- .reg = 0x360,
- .shift = 0,
- .mask = 0xff,
- .def = 0x89,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x89,
+ },
},
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 1,
- },
- .la = {
- .reg = 0x360,
- .shift = 16,
- .mask = 0xff,
- .def = 0x59,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x59,
+ },
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 10,
- },
- .la = {
- .reg = 0x37c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 11,
- },
- .la = {
- .reg = 0x37c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 12,
- },
- .la = {
- .reg = 0x380,
- .shift = 0,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 13,
- },
- .la = {
- .reg = 0x380,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x4e,
.name = "fdcdwr3",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 14,
- },
- .la = {
- .reg = 0x388,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x4f,
.name = "fdcdrd3",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 15,
- },
- .la = {
- .reg = 0x384,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x50,
.name = "fdcwr4",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 16,
- },
- .la = {
- .reg = 0x388,
- .shift = 16,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
}, {
.id = 0x51,
.name = "fdcrd4",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x230,
- .bit = 17,
- },
- .la = {
- .reg = 0x384,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
}, {
.id = 0x52,
.name = "emucifr",
.swgroup = TEGRA_SWGROUP_EMUCIF,
- .la = {
- .reg = 0x38c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x38c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x53,
.name = "emucifw",
.swgroup = TEGRA_SWGROUP_EMUCIF,
- .la = {
- .reg = 0x38c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x38c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 20,
- },
- .la = {
- .reg = 0x390,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 21,
- },
- .la = {
- .reg = 0x390,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
},
};
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 459211f50c08..8a8485ceb789 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -16,921 +16,1055 @@ static const struct tegra_mc_client tegra124_mc_clients[] = {
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
- .la = {
- .reg = 0x34c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0,
+ .regs = {
+ .la = {
+ .reg = 0x34c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0,
+ },
},
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0xc2,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xc2,
+ },
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0xc6,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xc6,
+ },
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x228,
- .bit = 14,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0x24,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x24,
+ },
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x1c,
.name = "msencsrd",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x228,
- .bit = 31,
- },
- .la = {
- .reg = 0x350,
- .shift = 0,
- .mask = 0xff,
- .def = 0x65,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x65,
+ },
},
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 2,
- },
- .la = {
- .reg = 0x354,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4f,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4f,
+ },
},
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 3,
- },
- .la = {
- .reg = 0x354,
- .shift = 16,
- .mask = 0xff,
- .def = 0x3d,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x3d,
+ },
},
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 4,
- },
- .la = {
- .reg = 0x358,
- .shift = 0,
- .mask = 0xff,
- .def = 0x66,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x66,
+ },
},
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 5,
- },
- .la = {
- .reg = 0x358,
- .shift = 16,
- .mask = 0xff,
- .def = 0xa5,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xa5,
+ },
},
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x2b,
.name = "msencswr",
.swgroup = TEGRA_SWGROUP_MSENC,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x22c,
- .bit = 17,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x22c,
- .bit = 29,
- },
- .la = {
- .reg = 0x350,
- .shift = 16,
- .mask = 0xff,
- .def = 0x65,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x65,
+ },
},
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 30,
- },
- .la = {
- .reg = 0x35c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 31,
- },
- .la = {
- .reg = 0x35c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 0,
- },
- .la = {
- .reg = 0x360,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 1,
- },
- .la = {
- .reg = 0x360,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x44,
.name = "ispra",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 4,
- },
- .la = {
- .reg = 0x370,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x370,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x46,
.name = "ispwa",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 6,
- },
- .la = {
- .reg = 0x374,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x47,
.name = "ispwb",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 7,
- },
- .la = {
- .reg = 0x374,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 10,
- },
- .la = {
- .reg = 0x37c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x39,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x39,
+ },
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 11,
- },
- .la = {
- .reg = 0x37c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 12,
- },
- .la = {
- .reg = 0x380,
- .shift = 0,
- .mask = 0xff,
- .def = 0x39,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x39,
+ },
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 13,
- },
- .la = {
- .reg = 0x380,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4e,
.name = "isprab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 14,
- },
- .la = {
- .reg = 0x384,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x50,
.name = "ispwab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 16,
- },
- .la = {
- .reg = 0x388,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x51,
.name = "ispwbb",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 17,
- },
- .la = {
- .reg = 0x388,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 20,
- },
- .la = {
- .reg = 0x390,
- .shift = 0,
- .mask = 0xff,
- .def = 0x9b,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x9b,
+ },
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 21,
- },
- .la = {
- .reg = 0x390,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x56,
.name = "a9avpscr",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 22,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x57,
.name = "a9avpscw",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 23,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x58,
.name = "gpusrd",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 24,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x59,
.name = "gpuswr",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 25,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x5a,
.name = "displayt",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x230,
- .bit = 26,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x60,
.name = "sdmmcra",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 0,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x61,
.name = "sdmmcraa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 1,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x62,
.name = "sdmmcr",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 2,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x63,
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.name = "sdmmcrab",
- .smmu = {
- .reg = 0x234,
- .bit = 3,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x64,
.name = "sdmmcwa",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 4,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x65,
.name = "sdmmcwaa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 5,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x66,
.name = "sdmmcw",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 6,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x67,
.name = "sdmmcwab",
.swgroup = TEGRA_SWGROUP_SDMMC4A,
- .smmu = {
- .reg = 0x234,
- .bit = 7,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x6c,
.name = "vicsrd",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 12,
- },
- .la = {
- .reg = 0x394,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x6d,
.name = "vicswr",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 13,
- },
- .la = {
- .reg = 0x394,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x72,
.name = "viw",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x234,
- .bit = 18,
- },
- .la = {
- .reg = 0x398,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x398,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x73,
.name = "displayd",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x234,
- .bit = 19,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
},
};
diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c
index b3bbc5a05ba1..08f3a08cd743 100644
--- a/drivers/memory/tegra/tegra210.c
+++ b/drivers/memory/tegra/tegra210.c
@@ -16,1005 +16,1149 @@ static const struct tegra_mc_client tegra210_mc_clients[] = {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x228,
- .bit = 14,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2e,
+ },
},
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0x24,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x24,
+ },
},
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x1c,
.name = "nvencsrd",
.swgroup = TEGRA_SWGROUP_NVENC,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x228,
- .bit = 31,
- },
- .la = {
- .reg = 0x350,
- .shift = 0,
- .mask = 0xff,
- .def = 0x65,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x65,
+ },
},
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x2b,
.name = "nvencswr",
.swgroup = TEGRA_SWGROUP_NVENC,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x22c,
- .bit = 17,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x22c,
- .bit = 29,
- },
- .la = {
- .reg = 0x350,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x44,
.name = "ispra",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 4,
- },
- .la = {
- .reg = 0x370,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x370,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x46,
.name = "ispwa",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 6,
- },
- .la = {
- .reg = 0x374,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x47,
.name = "ispwb",
.swgroup = TEGRA_SWGROUP_ISP2,
- .smmu = {
- .reg = 0x230,
- .bit = 7,
- },
- .la = {
- .reg = 0x374,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x374,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4a,
.name = "xusb_hostr",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 10,
- },
- .la = {
- .reg = 0x37c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x7a,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x7a,
+ },
},
}, {
.id = 0x4b,
.name = "xusb_hostw",
.swgroup = TEGRA_SWGROUP_XUSB_HOST,
- .smmu = {
- .reg = 0x230,
- .bit = 11,
- },
- .la = {
- .reg = 0x37c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x37c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4c,
.name = "xusb_devr",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 12,
- },
- .la = {
- .reg = 0x380,
- .shift = 0,
- .mask = 0xff,
- .def = 0x39,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x39,
+ },
},
}, {
.id = 0x4d,
.name = "xusb_devw",
.swgroup = TEGRA_SWGROUP_XUSB_DEV,
- .smmu = {
- .reg = 0x230,
- .bit = 13,
- },
- .la = {
- .reg = 0x380,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x380,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x4e,
.name = "isprab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 14,
- },
- .la = {
- .reg = 0x384,
- .shift = 0,
- .mask = 0xff,
- .def = 0x18,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x384,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x18,
+ },
},
}, {
.id = 0x50,
.name = "ispwab",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 16,
- },
- .la = {
- .reg = 0x388,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x51,
.name = "ispwbb",
.swgroup = TEGRA_SWGROUP_ISP2B,
- .smmu = {
- .reg = 0x230,
- .bit = 17,
- },
- .la = {
- .reg = 0x388,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x388,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x54,
.name = "tsecsrd",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 20,
- },
- .la = {
- .reg = 0x390,
- .shift = 0,
- .mask = 0xff,
- .def = 0x9b,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x9b,
+ },
},
}, {
.id = 0x55,
.name = "tsecswr",
.swgroup = TEGRA_SWGROUP_TSEC,
- .smmu = {
- .reg = 0x230,
- .bit = 21,
- },
- .la = {
- .reg = 0x390,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x390,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x56,
.name = "a9avpscr",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 22,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
}, {
.id = 0x57,
.name = "a9avpscw",
.swgroup = TEGRA_SWGROUP_A9AVP,
- .smmu = {
- .reg = 0x230,
- .bit = 23,
- },
- .la = {
- .reg = 0x3a4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x3a4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x58,
.name = "gpusrd",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 24,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x59,
.name = "gpuswr",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0x230,
- .bit = 25,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0x230,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x5a,
.name = "displayt",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x230,
- .bit = 26,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x1e,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x1e,
+ },
},
}, {
.id = 0x60,
.name = "sdmmcra",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 0,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x61,
.name = "sdmmcraa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 1,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 0,
- .mask = 0xff,
- .def = 0x5a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x5a,
+ },
},
}, {
.id = 0x62,
.name = "sdmmcr",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 2,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x49,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x49,
+ },
},
}, {
.id = 0x63,
.swgroup = TEGRA_SWGROUP_SDMMC4A,
.name = "sdmmcrab",
- .smmu = {
- .reg = 0x234,
- .bit = 3,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x5a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x5a,
+ },
},
}, {
.id = 0x64,
.name = "sdmmcwa",
.swgroup = TEGRA_SWGROUP_SDMMC1A,
- .smmu = {
- .reg = 0x234,
- .bit = 4,
- },
- .la = {
- .reg = 0x3b8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x3b8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x65,
.name = "sdmmcwaa",
.swgroup = TEGRA_SWGROUP_SDMMC2A,
- .smmu = {
- .reg = 0x234,
- .bit = 5,
- },
- .la = {
- .reg = 0x3bc,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x3bc,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x66,
.name = "sdmmcw",
.swgroup = TEGRA_SWGROUP_SDMMC3A,
- .smmu = {
- .reg = 0x234,
- .bit = 6,
- },
- .la = {
- .reg = 0x3c0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x3c0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x67,
.name = "sdmmcwab",
.swgroup = TEGRA_SWGROUP_SDMMC4A,
- .smmu = {
- .reg = 0x234,
- .bit = 7,
- },
- .la = {
- .reg = 0x3c4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x3c4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x6c,
.name = "vicsrd",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 12,
- },
- .la = {
- .reg = 0x394,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x6d,
.name = "vicswr",
.swgroup = TEGRA_SWGROUP_VIC,
- .smmu = {
- .reg = 0x234,
- .bit = 13,
- },
- .la = {
- .reg = 0x394,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x394,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x72,
.name = "viw",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x234,
- .bit = 18,
- },
- .la = {
- .reg = 0x398,
- .shift = 0,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x398,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x73,
.name = "displayd",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x234,
- .bit = 19,
- },
- .la = {
- .reg = 0x3c8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x3c8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
}, {
.id = 0x78,
.name = "nvdecsrd",
.swgroup = TEGRA_SWGROUP_NVDEC,
- .smmu = {
- .reg = 0x234,
- .bit = 24,
- },
- .la = {
- .reg = 0x3d8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x3d8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x79,
.name = "nvdecswr",
.swgroup = TEGRA_SWGROUP_NVDEC,
- .smmu = {
- .reg = 0x234,
- .bit = 25,
- },
- .la = {
- .reg = 0x3d8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x3d8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x7a,
.name = "aper",
.swgroup = TEGRA_SWGROUP_APE,
- .smmu = {
- .reg = 0x234,
- .bit = 26,
- },
- .la = {
- .reg = 0x3dc,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x3dc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x7b,
.name = "apew",
.swgroup = TEGRA_SWGROUP_APE,
- .smmu = {
- .reg = 0x234,
- .bit = 27,
- },
- .la = {
- .reg = 0x3dc,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x3dc,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x7e,
.name = "nvjpgsrd",
.swgroup = TEGRA_SWGROUP_NVJPG,
- .smmu = {
- .reg = 0x234,
- .bit = 30,
- },
- .la = {
- .reg = 0x3e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x23,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x3e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x23,
+ },
},
}, {
.id = 0x7f,
.name = "nvjpgswr",
.swgroup = TEGRA_SWGROUP_NVJPG,
- .smmu = {
- .reg = 0x234,
- .bit = 31,
- },
- .la = {
- .reg = 0x3e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x234,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x3e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x80,
.name = "sesrd",
.swgroup = TEGRA_SWGROUP_SE,
- .smmu = {
- .reg = 0xb98,
- .bit = 0,
- },
- .la = {
- .reg = 0x3e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2e,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x3e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2e,
+ },
},
}, {
.id = 0x81,
.name = "seswr",
.swgroup = TEGRA_SWGROUP_SE,
- .smmu = {
- .reg = 0xb98,
- .bit = 1,
- },
- .la = {
- .reg = 0x3e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x3e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x82,
.name = "axiapr",
.swgroup = TEGRA_SWGROUP_AXIAP,
- .smmu = {
- .reg = 0xb98,
- .bit = 2,
- },
- .la = {
- .reg = 0x3a0,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x3a0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x83,
.name = "axiapw",
.swgroup = TEGRA_SWGROUP_AXIAP,
- .smmu = {
- .reg = 0xb98,
- .bit = 3,
- },
- .la = {
- .reg = 0x3a0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x3a0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x84,
.name = "etrr",
.swgroup = TEGRA_SWGROUP_ETR,
- .smmu = {
- .reg = 0xb98,
- .bit = 4,
- },
- .la = {
- .reg = 0x3ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x3ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
}, {
.id = 0x85,
.name = "etrw",
.swgroup = TEGRA_SWGROUP_ETR,
- .smmu = {
- .reg = 0xb98,
- .bit = 5,
- },
- .la = {
- .reg = 0x3ec,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x3ec,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x86,
.name = "tsecsrdb",
.swgroup = TEGRA_SWGROUP_TSECB,
- .smmu = {
- .reg = 0xb98,
- .bit = 6,
- },
- .la = {
- .reg = 0x3f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x9b,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x3f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x9b,
+ },
},
}, {
.id = 0x87,
.name = "tsecswrb",
.swgroup = TEGRA_SWGROUP_TSECB,
- .smmu = {
- .reg = 0xb98,
- .bit = 7,
- },
- .la = {
- .reg = 0x3f0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0xb98,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x3f0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
}, {
.id = 0x88,
.name = "gpusrd2",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0xb98,
- .bit = 8,
- },
- .la = {
- .reg = 0x3e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x1a,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0xb98,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x3e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x1a,
+ },
},
}, {
.id = 0x89,
.name = "gpuswr2",
.swgroup = TEGRA_SWGROUP_GPU,
- .smmu = {
- /* read-only */
- .reg = 0xb98,
- .bit = 9,
- },
- .la = {
- .reg = 0x3e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ /* read-only */
+ .reg = 0xb98,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x3e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
},
};
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index ea849003014b..1922ab64e686 100644
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -37,970 +37,1102 @@ static const struct tegra_mc_client tegra30_mc_clients[] = {
.id = 0x00,
.name = "ptcr",
.swgroup = TEGRA_SWGROUP_PTC,
- .la = {
- .reg = 0x34c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0,
+ .regs = {
+ .la = {
+ .reg = 0x34c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x01,
.name = "display0a",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 1,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x02,
.name = "display0ab",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 2,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x03,
.name = "display0b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 3,
- },
- .la = {
- .reg = 0x2e8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x2e8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x04,
.name = "display0bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 4,
- },
- .la = {
- .reg = 0x2f4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x2f4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x05,
.name = "display0c",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 5,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x06,
.name = "display0cb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 6,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 0,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 6,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x07,
.name = "display1b",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 7,
- },
- .la = {
- .reg = 0x2ec,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 7,
+ },
+ .la = {
+ .reg = 0x2ec,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x08,
.name = "display1bb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 8,
- },
- .la = {
- .reg = 0x2f8,
- .shift = 16,
- .mask = 0xff,
- .def = 0x4e,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x2f8,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x4e,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x09,
.name = "eppup",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x228,
- .bit = 9,
- },
- .la = {
- .reg = 0x300,
- .shift = 0,
- .mask = 0xff,
- .def = 0x17,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x17,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x0a,
.name = "g2pr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 10,
- },
- .la = {
- .reg = 0x308,
- .shift = 0,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x0b,
.name = "g2sr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 11,
- },
- .la = {
- .reg = 0x308,
- .shift = 16,
- .mask = 0xff,
- .def = 0x09,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x308,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x09,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x0c,
.name = "mpeunifbr",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 12,
- },
- .la = {
- .reg = 0x328,
- .shift = 0,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x0d,
.name = "viruv",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x228,
- .bit = 13,
- },
- .la = {
- .reg = 0x364,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2c,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x364,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2c,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x0e,
.name = "afir",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x228,
- .bit = 14,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x0f,
.name = "avpcarm7r",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x228,
- .bit = 15,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x10,
.name = "displayhc",
.swgroup = TEGRA_SWGROUP_DC,
- .smmu = {
- .reg = 0x228,
- .bit = 16,
- },
- .la = {
- .reg = 0x2f0,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x2f0,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x11,
.name = "displayhcb",
.swgroup = TEGRA_SWGROUP_DCB,
- .smmu = {
- .reg = 0x228,
- .bit = 17,
- },
- .la = {
- .reg = 0x2fc,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2fc,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x12,
.name = "fdcdrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 18,
- },
- .la = {
- .reg = 0x334,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x13,
.name = "fdcdrd2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x228,
- .bit = 19,
- },
- .la = {
- .reg = 0x33c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x33c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x14,
.name = "g2dr",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x228,
- .bit = 20,
- },
- .la = {
- .reg = 0x30c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x15,
.name = "hdar",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x228,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x16,
.name = "host1xdmar",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 22,
- },
- .la = {
- .reg = 0x310,
- .shift = 0,
- .mask = 0xff,
- .def = 0x05,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x05,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x17,
.name = "host1xr",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x228,
- .bit = 23,
- },
- .la = {
- .reg = 0x310,
- .shift = 16,
- .mask = 0xff,
- .def = 0x50,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x310,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x50,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x18,
.name = "idxsrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x228,
- .bit = 24,
- },
- .la = {
- .reg = 0x334,
- .shift = 16,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 24,
+ },
+ .la = {
+ .reg = 0x334,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x19,
.name = "idxsrd2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x228,
- .bit = 25,
- },
- .la = {
- .reg = 0x33c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 25,
+ },
+ .la = {
+ .reg = 0x33c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x1a,
.name = "mpe_ipred",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 26,
- },
- .la = {
- .reg = 0x328,
- .shift = 16,
- .mask = 0xff,
- .def = 0x80,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x328,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x80,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x1b,
.name = "mpeamemrd",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 27,
- },
- .la = {
- .reg = 0x32c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x42,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x32c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x42,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x1c,
.name = "mpecsrd",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x228,
- .bit = 28,
- },
- .la = {
- .reg = 0x32c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x32c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x1d,
.name = "ppcsahbdmar",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 29,
- },
- .la = {
- .reg = 0x344,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x1e,
.name = "ppcsahbslvr",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x228,
- .bit = 30,
- },
- .la = {
- .reg = 0x344,
- .shift = 16,
- .mask = 0xff,
- .def = 0x12,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x344,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x12,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x1f,
.name = "satar",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x228,
- .bit = 31,
- },
- .la = {
- .reg = 0x350,
- .shift = 0,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x228,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x20,
.name = "texsrd",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 0,
- },
- .la = {
- .reg = 0x338,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x21,
.name = "texsrd2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x22c,
- .bit = 1,
- },
- .la = {
- .reg = 0x340,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x340,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x22,
.name = "vdebsevr",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 2,
- },
- .la = {
- .reg = 0x354,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 2,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x23,
.name = "vdember",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 3,
- },
- .la = {
- .reg = 0x354,
- .shift = 16,
- .mask = 0xff,
- .def = 0xd0,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 3,
+ },
+ .la = {
+ .reg = 0x354,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xd0,
+ },
},
.fifo_size = 16 * 4,
}, {
.id = 0x24,
.name = "vdemcer",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 4,
- },
- .la = {
- .reg = 0x358,
- .shift = 0,
- .mask = 0xff,
- .def = 0x2a,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 4,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x2a,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x25,
.name = "vdetper",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 5,
- },
- .la = {
- .reg = 0x358,
- .shift = 16,
- .mask = 0xff,
- .def = 0x74,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 5,
+ },
+ .la = {
+ .reg = 0x358,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x74,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x26,
.name = "mpcorelpr",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
.fifo_size = 16 * 14,
}, {
.id = 0x27,
.name = "mpcorer",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 0,
- .mask = 0xff,
- .def = 0x04,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x04,
+ },
},
.fifo_size = 16 * 14,
}, {
.id = 0x28,
.name = "eppu",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 8,
- },
- .la = {
- .reg = 0x300,
- .shift = 16,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 8,
+ },
+ .la = {
+ .reg = 0x300,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x29,
.name = "eppv",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 9,
- },
- .la = {
- .reg = 0x304,
- .shift = 0,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 9,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2a,
.name = "eppy",
.swgroup = TEGRA_SWGROUP_EPP,
- .smmu = {
- .reg = 0x22c,
- .bit = 10,
- },
- .la = {
- .reg = 0x304,
- .shift = 16,
- .mask = 0xff,
- .def = 0x6c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 10,
+ },
+ .la = {
+ .reg = 0x304,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x6c,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2b,
.name = "mpeunifbw",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x22c,
- .bit = 11,
- },
- .la = {
- .reg = 0x330,
- .shift = 0,
- .mask = 0xff,
- .def = 0x13,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 11,
+ },
+ .la = {
+ .reg = 0x330,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x13,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x2c,
.name = "viwsb",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 12,
- },
- .la = {
- .reg = 0x364,
- .shift = 16,
- .mask = 0xff,
- .def = 0x12,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 12,
+ },
+ .la = {
+ .reg = 0x364,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x12,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2d,
.name = "viwu",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 13,
- },
- .la = {
- .reg = 0x368,
- .shift = 0,
- .mask = 0xff,
- .def = 0xb2,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 13,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xb2,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2e,
.name = "viwv",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 14,
- },
- .la = {
- .reg = 0x368,
- .shift = 16,
- .mask = 0xff,
- .def = 0xb2,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 14,
+ },
+ .la = {
+ .reg = 0x368,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xb2,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x2f,
.name = "viwy",
.swgroup = TEGRA_SWGROUP_VI,
- .smmu = {
- .reg = 0x22c,
- .bit = 15,
- },
- .la = {
- .reg = 0x36c,
- .shift = 0,
- .mask = 0xff,
- .def = 0x12,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 15,
+ },
+ .la = {
+ .reg = 0x36c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x12,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x30,
.name = "g2dw",
.swgroup = TEGRA_SWGROUP_G2,
- .smmu = {
- .reg = 0x22c,
- .bit = 16,
- },
- .la = {
- .reg = 0x30c,
- .shift = 16,
- .mask = 0xff,
- .def = 0x9,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 16,
+ },
+ .la = {
+ .reg = 0x30c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x9,
+ },
},
.fifo_size = 16 * 128,
}, {
.id = 0x31,
.name = "afiw",
.swgroup = TEGRA_SWGROUP_AFI,
- .smmu = {
- .reg = 0x22c,
- .bit = 17,
- },
- .la = {
- .reg = 0x2e0,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0c,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 17,
+ },
+ .la = {
+ .reg = 0x2e0,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0c,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x32,
.name = "avpcarm7w",
.swgroup = TEGRA_SWGROUP_AVPC,
- .smmu = {
- .reg = 0x22c,
- .bit = 18,
- },
- .la = {
- .reg = 0x2e4,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 18,
+ },
+ .la = {
+ .reg = 0x2e4,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x33,
.name = "fdcdwr",
.swgroup = TEGRA_SWGROUP_NV,
- .smmu = {
- .reg = 0x22c,
- .bit = 19,
- },
- .la = {
- .reg = 0x338,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 19,
+ },
+ .la = {
+ .reg = 0x338,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x34,
.name = "fdcdwr2",
.swgroup = TEGRA_SWGROUP_NV2,
- .smmu = {
- .reg = 0x22c,
- .bit = 20,
- },
- .la = {
- .reg = 0x340,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0a,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 20,
+ },
+ .la = {
+ .reg = 0x340,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0a,
+ },
},
.fifo_size = 16 * 48,
}, {
.id = 0x35,
.name = "hdaw",
.swgroup = TEGRA_SWGROUP_HDA,
- .smmu = {
- .reg = 0x22c,
- .bit = 21,
- },
- .la = {
- .reg = 0x318,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 21,
+ },
+ .la = {
+ .reg = 0x318,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x36,
.name = "host1xw",
.swgroup = TEGRA_SWGROUP_HC,
- .smmu = {
- .reg = 0x22c,
- .bit = 22,
- },
- .la = {
- .reg = 0x314,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 22,
+ },
+ .la = {
+ .reg = 0x314,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x37,
.name = "ispw",
.swgroup = TEGRA_SWGROUP_ISP,
- .smmu = {
- .reg = 0x22c,
- .bit = 23,
- },
- .la = {
- .reg = 0x31c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 23,
+ },
+ .la = {
+ .reg = 0x31c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 64,
}, {
.id = 0x38,
.name = "mpcorelpw",
.swgroup = TEGRA_SWGROUP_MPCORELP,
- .la = {
- .reg = 0x324,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x324,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
.fifo_size = 16 * 24,
}, {
.id = 0x39,
.name = "mpcorew",
.swgroup = TEGRA_SWGROUP_MPCORE,
- .la = {
- .reg = 0x320,
- .shift = 16,
- .mask = 0xff,
- .def = 0x0e,
+ .regs = {
+ .la = {
+ .reg = 0x320,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x0e,
+ },
},
.fifo_size = 16 * 24,
}, {
.id = 0x3a,
.name = "mpecswr",
.swgroup = TEGRA_SWGROUP_MPE,
- .smmu = {
- .reg = 0x22c,
- .bit = 26,
- },
- .la = {
- .reg = 0x330,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 26,
+ },
+ .la = {
+ .reg = 0x330,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 8,
}, {
.id = 0x3b,
.name = "ppcsahbdmaw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 27,
- },
- .la = {
- .reg = 0x348,
- .shift = 0,
- .mask = 0xff,
- .def = 0x10,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 27,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x10,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x3c,
.name = "ppcsahbslvw",
.swgroup = TEGRA_SWGROUP_PPCS,
- .smmu = {
- .reg = 0x22c,
- .bit = 28,
- },
- .la = {
- .reg = 0x348,
- .shift = 16,
- .mask = 0xff,
- .def = 0x06,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 28,
+ },
+ .la = {
+ .reg = 0x348,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x06,
+ },
},
.fifo_size = 16 * 4,
}, {
.id = 0x3d,
.name = "sataw",
.swgroup = TEGRA_SWGROUP_SATA,
- .smmu = {
- .reg = 0x22c,
- .bit = 29,
- },
- .la = {
- .reg = 0x350,
- .shift = 16,
- .mask = 0xff,
- .def = 0x33,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 29,
+ },
+ .la = {
+ .reg = 0x350,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x33,
+ },
},
.fifo_size = 16 * 32,
}, {
.id = 0x3e,
.name = "vdebsevw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 30,
- },
- .la = {
- .reg = 0x35c,
- .shift = 0,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 30,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 4,
}, {
.id = 0x3f,
.name = "vdedbgw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x22c,
- .bit = 31,
- },
- .la = {
- .reg = 0x35c,
- .shift = 16,
- .mask = 0xff,
- .def = 0xff,
+ .regs = {
+ .smmu = {
+ .reg = 0x22c,
+ .bit = 31,
+ },
+ .la = {
+ .reg = 0x35c,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0xff,
+ },
},
.fifo_size = 16 * 16,
}, {
.id = 0x40,
.name = "vdembew",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 0,
- },
- .la = {
- .reg = 0x360,
- .shift = 0,
- .mask = 0xff,
- .def = 0x42,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 0,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 0,
+ .mask = 0xff,
+ .def = 0x42,
+ },
},
.fifo_size = 16 * 2,
}, {
.id = 0x41,
.name = "vdetpmw",
.swgroup = TEGRA_SWGROUP_VDE,
- .smmu = {
- .reg = 0x230,
- .bit = 1,
- },
- .la = {
- .reg = 0x360,
- .shift = 16,
- .mask = 0xff,
- .def = 0x2a,
+ .regs = {
+ .smmu = {
+ .reg = 0x230,
+ .bit = 1,
+ },
+ .la = {
+ .reg = 0x360,
+ .shift = 16,
+ .mask = 0xff,
+ .def = 0x2a,
+ },
},
.fifo_size = 16 * 16,
},
@@ -1089,7 +1221,6 @@ static void tegra30_mc_tune_client_latency(struct tegra_mc *mc,
unsigned int bandwidth_mbytes_sec)
{
u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;
- const struct tegra_mc_la *la = &client->la;
unsigned int fifo_size = client->fifo_size;
u32 arb_nsec, la_ticks, value;
@@ -1149,12 +1280,12 @@ static void tegra30_mc_tune_client_latency(struct tegra_mc *mc,
* request.
*/
la_ticks = arb_nsec / mc->tick;
- la_ticks = min(la_ticks, la->mask);
+ la_ticks = min(la_ticks, client->regs.la.mask);
- value = mc_readl(mc, la->reg);
- value &= ~(la->mask << la->shift);
- value |= la_ticks << la->shift;
- mc_writel(mc, value, la->reg);
+ value = mc_readl(mc, client->regs.la.reg);
+ value &= ~(client->regs.la.mask << client->regs.la.shift);
+ value |= la_ticks << client->regs.la.shift;
+ mc_writel(mc, value, client->regs.la.reg);
}
static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst)
generated by cgit v1.2.3 (git 2.39.0) at 2024-06-11 13:07:48 +0300