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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2019-08-16 20:33:42 +0300
committerLee Jones <lee.jones@linaro.org>2019-09-02 13:09:03 +0300
commitcbd1c5c4d443c4a83c9c7eecc0561b9aeafddf50 (patch)
treebea4cfa5673aaa43ef0fcd753ead66865f0f5969 /drivers/mfd/intel-lpss.c
parentb9a801dfa59163dc2db8147a98af406eb79e51de (diff)
downloadlinux-cbd1c5c4d443c4a83c9c7eecc0561b9aeafddf50.tar.xz
mfd: intel-lpss: Consistently use GENMASK()
Since we already are using BIT() macro, use GENMASK() as well for sake of consistency. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
Diffstat (limited to 'drivers/mfd/intel-lpss.c')
-rw-r--r--drivers/mfd/intel-lpss.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c
index 277f48f1cc1c..3e16a1765142 100644
--- a/drivers/mfd/intel-lpss.c
+++ b/drivers/mfd/intel-lpss.c
@@ -47,10 +47,10 @@
#define LPSS_PRIV_IDLELTR 0x14
#define LPSS_PRIV_LTR_REQ BIT(15)
-#define LPSS_PRIV_LTR_SCALE_MASK 0xc00
-#define LPSS_PRIV_LTR_SCALE_1US 0x800
-#define LPSS_PRIV_LTR_SCALE_32US 0xc00
-#define LPSS_PRIV_LTR_VALUE_MASK 0x3ff
+#define LPSS_PRIV_LTR_SCALE_MASK GENMASK(11, 10)
+#define LPSS_PRIV_LTR_SCALE_1US (2 << 10)
+#define LPSS_PRIV_LTR_SCALE_32US (3 << 10)
+#define LPSS_PRIV_LTR_VALUE_MASK GENMASK(9, 0)
#define LPSS_PRIV_SSP_REG 0x20
#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN BIT(0)
@@ -59,8 +59,8 @@
#define LPSS_PRIV_CAPS 0xfc
#define LPSS_PRIV_CAPS_NO_IDMA BIT(8)
+#define LPSS_PRIV_CAPS_TYPE_MASK GENMASK(7, 4)
#define LPSS_PRIV_CAPS_TYPE_SHIFT 4
-#define LPSS_PRIV_CAPS_TYPE_MASK (0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
/* This matches the type field in CAPS register */
enum intel_lpss_dev_type {