diff options
| author | Pavan Chebbi <pavan.chebbi@broadcom.com> | 2021-07-28 21:11:42 +0300 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2021-07-28 22:23:33 +0300 |
| commit | caf3eedbcd8d326c9b789cc270b9ddcce254e0ce (patch) | |
| tree | 97a871c4184989fd688fec6401a592338495a85c /drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h | |
| parent | 30e96f487f64c60b2884e37b9dabf287c9d048aa (diff) | |
| download | linux-caf3eedbcd8d326c9b789cc270b9ddcce254e0ce.tar.xz | |
bnxt_en: 1PPS support for 5750X family chips
1PPS (One Pulse Per Second) is a signal generated either
by the NIC PHC or an external timing source.
Integrating the support to configure and use 1PPS using
the TSIO pins along with PTP timestamps will add Grand
Master capability to the 5750X family chipsets.
This patch initializes the driver data structures and
registers the 1PPS with kernel, based on the TSIO pins'
capability in the hardware. This will create a /dev/ppsX
device which applications can use to receive PPS events.
Later patches will define functions to configure and use
the pins.
Reviewed-by: Edwin Peer <edwin.peer@broadcom.com>
Signed-off-by: Pavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h')
| -rw-r--r-- | drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h b/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h index 4135ea3ec788..619a6a1bf9fa 100644 --- a/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h +++ b/drivers/net/ethernet/broadcom/bnxt/bnxt_ptp.h @@ -21,11 +21,33 @@ #define BNXT_PTP_QTS_TX_ENABLES (PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID | \ PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT) +struct pps_pin { + u8 usage; +}; + +#define BNXT_PPS_PIN_DISABLE 0 +#define BNXT_PPS_PIN_ENABLE 1 +#define BNXT_PPS_PIN_NONE 0 +#define BNXT_PPS_PIN_PPS_IN 1 +#define BNXT_PPS_PIN_PPS_OUT 2 +#define BNXT_PPS_PIN_SYNC_IN 3 +#define BNXT_PPS_PIN_SYNC_OUT 4 + +#define BNXT_PPS_EVENT_INTERNAL 1 +#define BNXT_PPS_EVENT_EXTERNAL 2 + +struct bnxt_pps { + u8 num_pins; +#define BNXT_MAX_TSIO_PINS 4 + struct pps_pin pins[BNXT_MAX_TSIO_PINS]; +}; + struct bnxt_ptp_cfg { struct ptp_clock_info ptp_info; struct ptp_clock *ptp_clock; struct cyclecounter cc; struct timecounter tc; + struct bnxt_pps pps_info; /* serialize timecounter access */ spinlock_t ptp_lock; struct sk_buff *tx_skb; |