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authorHolger Brunck <holger.brunck@keymile.com>2017-05-17 18:24:38 +0300
committerDavid S. Miller <davem@davemloft.net>2017-05-18 17:28:39 +0300
commit067bb938dad61e58fc3d6a0e090b72ec011851cd (patch)
tree617e9b79f94dfe0cdff171fae024b7f13353b657 /drivers/net/wan
parentc7f235a7c2d09b1b83671ba2d93ebee981554467 (diff)
downloadlinux-067bb938dad61e58fc3d6a0e090b72ec011851cd.tar.xz
net/wan/fsl_ucc_hdlc: add hdlc-bus support
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can be enabled with the "fsl,hdlc-bus" property in the DTS node of the corresponding ucc. This aligns the configuration of the UPSMR and GUMR registers to what is done in our ucc_hdlc driver (that only support hdlc-bus mode) and with the QuickEngine's documentation for hdlc-bus mode. GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal is ignored. The brkpt_support is enabled to set the HBM1 bit in the CMXUCR register to configure an open-drain connected HDLC bus. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Cc: Zhao Qiang <qiang.zhao@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/wan')
-rw-r--r--drivers/net/wan/fsl_ucc_hdlc.c32
-rw-r--r--drivers/net/wan/fsl_ucc_hdlc.h1
2 files changed, 33 insertions, 0 deletions
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index 4c93d561b18a..e9b2d687f150 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -98,6 +98,13 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
uf_info->tsa = 1;
uf_info->ctsp = 1;
}
+
+ /* This sets HPM register in CMXUCR register which configures a
+ * open drain connected HDLC bus
+ */
+ if (priv->hdlc_bus)
+ uf_info->brkpt_support = 1;
+
uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
UCC_HDLC_UCCE_TXB) << 16);
@@ -135,6 +142,28 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
/* Set UPSMR normal mode (need fixed)*/
iowrite32be(0, &priv->uf_regs->upsmr);
+ /* hdlc_bus mode */
+ if (priv->hdlc_bus) {
+ u32 upsmr;
+
+ dev_info(priv->dev, "HDLC bus Mode\n");
+ upsmr = ioread32be(&priv->uf_regs->upsmr);
+
+ /* bus mode and retransmit enable, with collision window
+ * set to 8 bytes
+ */
+ upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
+ UCC_HDLC_UPSMR_CW8;
+ iowrite32be(upsmr, &priv->uf_regs->upsmr);
+
+ /* explicitly disable CDS & CTSP */
+ gumr = ioread32be(&priv->uf_regs->gumr);
+ gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
+ /* set automatic sync to explicitly ignore CD signal */
+ gumr |= UCC_FAST_GUMR_SYNL_AUTO;
+ iowrite32be(gumr, &priv->uf_regs->gumr);
+ }
+
priv->rx_ring_size = RX_BD_RING_LEN;
priv->tx_ring_size = TX_BD_RING_LEN;
/* Alloc Rx BD */
@@ -1046,6 +1075,9 @@ static int ucc_hdlc_probe(struct platform_device *pdev)
if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
uhdlc_priv->loopback = 1;
+ if (of_get_property(np, "fsl,hdlc-bus", NULL))
+ uhdlc_priv->hdlc_bus = 1;
+
if (uhdlc_priv->tsa == 1) {
utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
if (!utdm) {
diff --git a/drivers/net/wan/fsl_ucc_hdlc.h b/drivers/net/wan/fsl_ucc_hdlc.h
index 881ecdeef076..c21134c1f180 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.h
+++ b/drivers/net/wan/fsl_ucc_hdlc.h
@@ -78,6 +78,7 @@ struct ucc_hdlc_private {
u16 tsa;
bool hdlc_busy;
bool loopback;
+ bool hdlc_bus;
u8 *tx_buffer;
u8 *rx_buffer;