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authorPali Rohár <pali@kernel.org>2021-11-24 18:59:44 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2022-01-27 13:05:14 +0300
commit9473abe5b5bff6c34e8cda352c4b5ce6a7bc82aa (patch)
treee606c33bc7b74d5f4a7d568d73758c0c4f1d1d96 /drivers/pci
parentd4e0d674b42dfb87f556c2a7caf2e9b3defb1477 (diff)
downloadlinux-9473abe5b5bff6c34e8cda352c4b5ce6a7bc82aa.tar.xz
PCI: pci-bridge-emul: Set PCI_STATUS_CAP_LIST for PCIe device
commit 3be9d243b21724d49b65043d4520d688b6040b36 upstream. Since all PCI Express device Functions are required to implement the PCI Express Capability structure, Capabilities List bit in PCI Status Register must be hardwired to 1b. Capabilities Pointer register (which is already set by pci-bride-emul.c driver) is valid only when Capabilities List is set to 1b. Link: https://lore.kernel.org/r/20211124155944.1290-7-pali@kernel.org Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic") Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci-bridge-emul.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 867159562d07..37504c2cce9b 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -296,6 +296,7 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
if (bridge->has_pcie) {
bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
+ bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
bridge->pcie_cap_regs_behavior =