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authorWilliam wu <wulf@rock-chips.com>2018-02-16 15:09:53 +0300
committerKishon Vijay Abraham I <kishon@ti.com>2018-03-16 14:25:33 +0300
commitf293f7409f6b2850d45a9fb8689003d8fa6fe453 (patch)
treef623af5e3826a1d254250aef9fd7f7441076103b /drivers/phy
parent6912d4f40bc7b8a40604f2fa02bb5545e39d1a35 (diff)
downloadlinux-f293f7409f6b2850d45a9fb8689003d8fa6fe453.tar.xz
phy: rockchip-typec: enable usb3 host during usb3 phy power on
We have forced usb3 to work in usb2 only mode in firmware by setting usb3tousb2_en (bit3 of GRF_USB3PHY0/1_CON0) to 1, and setting host_u3_port_disable (bit0 of GRF_USB3OTG0/1_CON1) to 1 and host_u3_port (bit15~12 of GRF_USB3OTG0/1_CON1) to 0. So we need to re-enable usb3 host. Note that the RK3399 TRM suggests that we should keep the whole usb3 controller in reset for the duration of the Type-C PHY initialization. However, it's hard to assert the reset in the current framework of reset. And according to the TRM, it doesn't require that we should clear the usb3tousb2 bit before pipe ready. So let's enable the usb3 host after pipe ready to avoid the Type-C PHY initialization failure. Signed-off-by: William wu <wulf@rock-chips.com> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/rockchip/phy-rockchip-typec.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index 5f660f6b9f95..54dc52a948ef 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -362,6 +362,8 @@ struct usb3phy_reg {
* @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
* @external_psm: the register of type-c phy external psm clock.
* @pipe_status: the register of type-c phy pipe status.
+ * @usb3_host_disable: the register of type-c usb3 host disable.
+ * @usb3_host_port: the register of type-c usb3 host port.
*/
struct rockchip_usb3phy_port_cfg {
unsigned int reg;
@@ -369,6 +371,8 @@ struct rockchip_usb3phy_port_cfg {
struct usb3phy_reg usb3tousb2_en;
struct usb3phy_reg external_psm;
struct usb3phy_reg pipe_status;
+ struct usb3phy_reg usb3_host_disable;
+ struct usb3phy_reg usb3_host_port;
};
struct rockchip_typec_phy {
@@ -440,6 +444,8 @@ static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
.usb3tousb2_en = { 0xe580, 3, 19 },
.external_psm = { 0xe588, 14, 30 },
.pipe_status = { 0xe5c0, 0, 0 },
+ .usb3_host_disable = { 0x2434, 0, 16 },
+ .usb3_host_port = { 0x2434, 12, 28 },
},
{
.reg = 0xff800000,
@@ -447,6 +453,8 @@ static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
.usb3tousb2_en = { 0xe58c, 3, 19 },
.external_psm = { 0xe594, 14, 30 },
.pipe_status = { 0xe5c0, 16, 16 },
+ .usb3_host_disable = { 0x2444, 0, 16 },
+ .usb3_host_port = { 0x2444, 12, 28 },
},
{ /* sentinel */ }
};
@@ -879,6 +887,9 @@ static int rockchip_usb3_phy_power_on(struct phy *phy)
regmap_read(tcphy->grf_regs, reg->offset, &val);
if (!(val & BIT(reg->enable_bit))) {
tcphy->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB);
+ /* enable usb3 host */
+ property_enable(tcphy, &cfg->usb3_host_disable, 0);
+ property_enable(tcphy, &cfg->usb3_host_port, 1);
goto unlock_ret;
}
usleep_range(10, 20);