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| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-04-05 09:59:21 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-04-05 09:59:21 +0300 |
| commit | 9594408763d439287742d5582842db6a476bbd71 (patch) | |
| tree | 2a0787dae55a3372108837cc8ce3261beac6ff46 /drivers/platform/x86/Kconfig | |
| parent | 202680c7a93713283207dedfbc4b550ad6836a43 (diff) | |
| parent | e49d033bddf5b565044e2abe4241353959bc9120 (diff) | |
| download | linux-9594408763d439287742d5582842db6a476bbd71.tar.xz | |
Merge 5.12-rc6 into tty-next
We need the serial/tty fixes in here as well.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/platform/x86/Kconfig')
| -rw-r--r-- | drivers/platform/x86/Kconfig | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index ad4e630e73e2..461ec61530eb 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig @@ -1173,15 +1173,20 @@ config INTEL_PMC_CORE depends on PCI help The Intel Platform Controller Hub for Intel Core SoCs provides access - to Power Management Controller registers via a PCI interface. This + to Power Management Controller registers via various interfaces. This driver can utilize debugging capabilities and supported features as - exposed by the Power Management Controller. + exposed by the Power Management Controller. It also may perform some + tasks in the PMC in order to enable transition into the SLPS0 state. + It should be selected on all Intel platforms supported by the driver. Supported features: - SLP_S0_RESIDENCY counter - PCH IP Power Gating status - - LTR Ignore + - LTR Ignore / LTR Show - MPHY/PLL gating status (Sunrisepoint PCH only) + - SLPS0 Debug registers (Cannonlake/Icelake PCH) + - Low Power Mode registers (Tigerlake and beyond) + - PMC quirks as needed to enable SLPS0/S0ix config INTEL_PMT_CLASS tristate |