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| author | Mario Limonciello <mario.limonciello@amd.com> | 2021-09-14 05:01:14 +0300 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2021-09-14 13:26:00 +0300 |
| commit | 3c3c8e88c8712bfe06cd10d7ca77a94a33610cd6 (patch) | |
| tree | 0562c2d55f5c9d47136e0ccb1e1a3e58b7bfbde2 /drivers/platform | |
| parent | 196159d278ae3b49e7bbb7c76822e6008fd89b97 (diff) | |
| download | linux-3c3c8e88c8712bfe06cd10d7ca77a94a33610cd6.tar.xz | |
platform/x86: amd-pmc: Increase the response register timeout
There have been reports of approximately a 0.9%-1.7% failure rate in SMU
communication timeouts with s0i3 entry on some OEM designs. Currently
the design in amd-pmc is to try every 100us for up to 20ms.
However the GPU driver which also communicates with the SMU using a
mailbox register which the driver polls every 1us for up to 2000ms.
In the GPU driver this was increased by commit 055162645a40 ("drm/amd/pm:
increase time out value when sending msg to SMU")
Increase the maximum timeout used by amd-pmc to 2000ms to match this
behavior. This has been shown to improve the stability for machines
that randomly have failures.
Cc: stable@kernel.org
Reported-by: Julian Sikorski <belegdol@gmail.com>
BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1629
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20210914020115.655-1-mario.limonciello@amd.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Diffstat (limited to 'drivers/platform')
| -rw-r--r-- | drivers/platform/x86/amd-pmc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c index 3481479a2942..d6a7c896ac86 100644 --- a/drivers/platform/x86/amd-pmc.c +++ b/drivers/platform/x86/amd-pmc.c @@ -71,7 +71,7 @@ #define AMD_CPU_ID_YC 0x14B5 #define PMC_MSG_DELAY_MIN_US 100 -#define RESPONSE_REGISTER_LOOP_MAX 200 +#define RESPONSE_REGISTER_LOOP_MAX 20000 #define SOC_SUBSYSTEM_IP_MAX 12 #define DELAY_MIN_US 2000 |