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authorRajat Jain <rajatja@google.com>2019-02-16 03:19:20 +0300
committerDarren Hart (VMware) <dvhart@infradead.org>2019-02-23 20:21:02 +0300
commit4a5861f714293767980e4948c9a7c9e5e09c9b94 (patch)
tree0a40c8f76e60c0c1d61dd05dbfbfb8e5ae250147 /drivers/platform
parentf27e1d1826d0392c0841e6f098b88e2da166163a (diff)
downloadlinux-4a5861f714293767980e4948c9a7c9e5e09c9b94.tar.xz
platform/x86: intel_pmc_core: Avoid a u32 overflow
The register (SLP_S0_RES) at offset slp_s0_offset is a 32 bit register. The pmc_core_adjust_slp_s0_step() could overflow the u32 value while returning it after adjusting the step. Thus change to u64, this is already accounted for in debugfs attribute (that wants to output a 64 bit value). Signed-off-by: Rajat Jain <rajatja@google.com> Acked-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Darren Hart (VMware) <dvhart@infradead.org>
Diffstat (limited to 'drivers/platform')
-rw-r--r--drivers/platform/x86/intel_pmc_core.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 835ed6d333bf..08d8b45303db 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -330,9 +330,9 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
writel(val, pmcdev->regbase + reg_offset);
}
-static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
+static inline u64 pmc_core_adjust_slp_s0_step(u32 value)
{
- return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
+ return (u64)value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
}
static int pmc_core_dev_state_get(void *data, u64 *val)