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authorLinus Torvalds <torvalds@linux-foundation.org>2021-09-01 20:29:29 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2021-09-01 20:29:29 +0300
commit0d290223a6c77107b1c3988959e49279a8dafaba (patch)
tree2b250c9e698b84a38d17920c0712558226c93c78 /drivers/soundwire
parentea7b4244b3656ca33b19a950f092b5bbc718b40c (diff)
parenta8729efbbb847f6ea9b06e73491ec8ddb560465e (diff)
downloadlinux-0d290223a6c77107b1c3988959e49279a8dafaba.tar.xz
Merge tag 'sound-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
Pull sound updates from Takashi Iwai: "There are a few intensive changes in ALSA core side at this time that helped with significant code reduction. Meanwhile we keep getting new stuff, so the total size still grows... Anyway, the below are some highlights in this development cycle. ALSA core: - New helpers to manage page allocations and card object with devres - Refactoring for memory allocation with wc-pages - A new PCM hardware flag SNDRV_PCM_INFO_EXPLICIT_SYNC for controlling the explicit sync of the stream control; it'll be used for ASoC SOF and non-coherent memory in future ASoC: - Lots of cleanups and improvements to the Intel drivers, including some new systems support - New support for AMD Vangoh, CUI CMM-4030D-261, Mediatek Mt8195, Renesas RZ/G2L Mediatek Mt8195, RealTek RT101P, Renesas RZ/G2L, Rockchip RK3568 S/PDIF USB-audio: - Re-organized the quirk handling and a new option quirk_flags - Fix for a regression in 5.14 code change for JACK - Quirks for Sony WALKMAN, Digidesign mbox HD-audio: - Enhanced support for CS8409 codec - More consistent shutdown behavior with the runtime PM - The model option can accept the PCI or codec SSID as an alias - Quirks for ASUS ROG, HP Spectre x360 Others: - Lots of code reduction in legacy drivers with devres helpers - FireWire MOTU 896HD support" * tag 'sound-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (421 commits) ASoC: Revert PCM trigger changes ALSA: usb-audio: Add lowlatency module option ALSA: hda/cs8409: Initialize Codec only in init fixup. ALSA: hda/cs8409: Ensure Type Detection is only run on startup when necessary ALSA: usb-audio: Work around for XRUN with low latency playback ALSA: pcm: fix divide error in snd_pcm_lib_ioctl ASoC: soc-pcm: test refcount before triggering ASoC: soc-pcm: protect BE dailink state changes in trigger ASoC: wcd9335: Disable irq on slave ports in the remove function ASoC: wcd9335: Fix a memory leak in the error handling path of the probe function ASoC: wcd9335: Fix a double irq free in the remove function ALSA: hda: Disable runtime resume at shutdown ASoC: rockchip: i2s: Add support for frame inversion ASoC: dt-bindings: rockchip: Add compatible strings for more SoCs ASoC: rockchip: i2s: Add compatible for more SoCs ASoC: rockchip: i2s: Make playback/capture optional ASoC: rockchip: i2s: Fixup config for DAIFMT_DSP_A/B ASoC: dt-bindings: rockchip: Document reset property for i2s ASoC: rockchip: i2s: Fix regmap_ops hang ASoC: rockchip: i2s: Improve dma data transfer efficiency ...
Diffstat (limited to 'drivers/soundwire')
-rw-r--r--drivers/soundwire/intel.c74
-rw-r--r--drivers/soundwire/intel_init.c14
2 files changed, 5 insertions, 83 deletions
diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
index f66fcbc33a2f..78037ffdb09b 100644
--- a/drivers/soundwire/intel.c
+++ b/drivers/soundwire/intel.c
@@ -41,80 +41,6 @@ static int md_flags;
module_param_named(sdw_md_flags, md_flags, int, 0444);
MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
-/* Intel SHIM Registers Definition */
-#define SDW_SHIM_LCAP 0x0
-#define SDW_SHIM_LCTL 0x4
-#define SDW_SHIM_IPPTR 0x8
-#define SDW_SHIM_SYNC 0xC
-
-#define SDW_SHIM_CTLSCAP(x) (0x010 + 0x60 * (x))
-#define SDW_SHIM_CTLS0CM(x) (0x012 + 0x60 * (x))
-#define SDW_SHIM_CTLS1CM(x) (0x014 + 0x60 * (x))
-#define SDW_SHIM_CTLS2CM(x) (0x016 + 0x60 * (x))
-#define SDW_SHIM_CTLS3CM(x) (0x018 + 0x60 * (x))
-#define SDW_SHIM_PCMSCAP(x) (0x020 + 0x60 * (x))
-
-#define SDW_SHIM_PCMSYCHM(x, y) (0x022 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PCMSYCHC(x, y) (0x042 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PDMSCAP(x) (0x062 + 0x60 * (x))
-#define SDW_SHIM_IOCTL(x) (0x06C + 0x60 * (x))
-#define SDW_SHIM_CTMCTL(x) (0x06E + 0x60 * (x))
-
-#define SDW_SHIM_WAKEEN 0x190
-#define SDW_SHIM_WAKESTS 0x192
-
-#define SDW_SHIM_LCTL_SPA BIT(0)
-#define SDW_SHIM_LCTL_SPA_MASK GENMASK(3, 0)
-#define SDW_SHIM_LCTL_CPA BIT(8)
-#define SDW_SHIM_LCTL_CPA_MASK GENMASK(11, 8)
-
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_24 (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD GENMASK(14, 0)
-#define SDW_SHIM_SYNC_SYNCCPU BIT(15)
-#define SDW_SHIM_SYNC_CMDSYNC_MASK GENMASK(19, 16)
-#define SDW_SHIM_SYNC_CMDSYNC BIT(16)
-#define SDW_SHIM_SYNC_SYNCGO BIT(24)
-
-#define SDW_SHIM_PCMSCAP_ISS GENMASK(3, 0)
-#define SDW_SHIM_PCMSCAP_OSS GENMASK(7, 4)
-#define SDW_SHIM_PCMSCAP_BSS GENMASK(12, 8)
-
-#define SDW_SHIM_PCMSYCM_LCHN GENMASK(3, 0)
-#define SDW_SHIM_PCMSYCM_HCHN GENMASK(7, 4)
-#define SDW_SHIM_PCMSYCM_STREAM GENMASK(13, 8)
-#define SDW_SHIM_PCMSYCM_DIR BIT(15)
-
-#define SDW_SHIM_PDMSCAP_ISS GENMASK(3, 0)
-#define SDW_SHIM_PDMSCAP_OSS GENMASK(7, 4)
-#define SDW_SHIM_PDMSCAP_BSS GENMASK(12, 8)
-#define SDW_SHIM_PDMSCAP_CPSS GENMASK(15, 13)
-
-#define SDW_SHIM_IOCTL_MIF BIT(0)
-#define SDW_SHIM_IOCTL_CO BIT(1)
-#define SDW_SHIM_IOCTL_COE BIT(2)
-#define SDW_SHIM_IOCTL_DO BIT(3)
-#define SDW_SHIM_IOCTL_DOE BIT(4)
-#define SDW_SHIM_IOCTL_BKE BIT(5)
-#define SDW_SHIM_IOCTL_WPDD BIT(6)
-#define SDW_SHIM_IOCTL_CIBD BIT(8)
-#define SDW_SHIM_IOCTL_DIBD BIT(9)
-
-#define SDW_SHIM_CTMCTL_DACTQE BIT(0)
-#define SDW_SHIM_CTMCTL_DODS BIT(1)
-#define SDW_SHIM_CTMCTL_DOAIS GENMASK(4, 3)
-
-#define SDW_SHIM_WAKEEN_ENABLE BIT(0)
-#define SDW_SHIM_WAKESTS_STATUS BIT(0)
-
-/* Intel ALH Register definitions */
-#define SDW_ALH_STRMZCFG(x) (0x000 + (0x4 * (x)))
-#define SDW_ALH_NUM_STREAMS 64
-
-#define SDW_ALH_STRMZCFG_DMAT_VAL 0x3
-#define SDW_ALH_STRMZCFG_DMAT GENMASK(7, 0)
-#define SDW_ALH_STRMZCFG_CHN GENMASK(19, 16)
-
enum intel_pdi_type {
INTEL_PDI_IN = 0,
INTEL_PDI_OUT = 1,
diff --git a/drivers/soundwire/intel_init.c b/drivers/soundwire/intel_init.c
index 9e283bef53d2..e329022e1669 100644
--- a/drivers/soundwire/intel_init.c
+++ b/drivers/soundwire/intel_init.c
@@ -18,12 +18,6 @@
#include "cadence_master.h"
#include "intel.h"
-#define SDW_SHIM_LCAP 0x0
-#define SDW_SHIM_BASE 0x2C000
-#define SDW_ALH_BASE 0x2C800
-#define SDW_LINK_BASE 0x30000
-#define SDW_LINK_SIZE 0x10000
-
static void intel_link_dev_release(struct device *dev)
{
struct auxiliary_device *auxdev = to_auxiliary_dev(dev);
@@ -69,8 +63,8 @@ static struct sdw_intel_link_dev *intel_link_dev_register(struct sdw_intel_res *
link->mmio_base = res->mmio_base;
link->registers = res->mmio_base + SDW_LINK_BASE
+ (SDW_LINK_SIZE * link_id);
- link->shim = res->mmio_base + SDW_SHIM_BASE;
- link->alh = res->mmio_base + SDW_ALH_BASE;
+ link->shim = res->mmio_base + res->shim_base;
+ link->alh = res->mmio_base + res->alh_base;
link->ops = res->ops;
link->dev = res->dev;
@@ -220,6 +214,8 @@ static struct sdw_intel_ctx
}
ctx->mmio_base = res->mmio_base;
+ ctx->shim_base = res->shim_base;
+ ctx->alh_base = res->alh_base;
ctx->link_mask = res->link_mask;
ctx->handle = res->handle;
mutex_init(&ctx->shim_lock);
@@ -308,7 +304,7 @@ sdw_intel_startup_controller(struct sdw_intel_ctx *ctx)
return -EINVAL;
/* Check SNDWLCAP.LCOUNT */
- caps = ioread32(ctx->mmio_base + SDW_SHIM_BASE + SDW_SHIM_LCAP);
+ caps = ioread32(ctx->mmio_base + ctx->shim_base + SDW_SHIM_LCAP);
caps &= GENMASK(2, 0);
/* Check HW supported vs property value */