diff options
| author | Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> | 2020-05-21 09:05:44 +0300 |
|---|---|---|
| committer | Felipe Balbi <balbi@kernel.org> | 2020-05-25 11:09:44 +0300 |
| commit | 65dc2e725286106f99c6f6b78e3d9c52c15f3a9c (patch) | |
| tree | 267a2f9b4db38c3354448e3ad17a5774896b188b /drivers/usb/dwc2/core.h | |
| parent | 4cda340a455b425f7df9657aaaa78a75757d940d (diff) | |
| download | linux-65dc2e725286106f99c6f6b78e3d9c52c15f3a9c.tar.xz | |
usb: dwc2: Update Core Reset programming flow.
Starting from core version 4.20a Core Reset flow is changed.
Introduced new bit in GRSTCTL register - GRSTCTL_CSFTRST_DONE.
Core Reset new programming flow steps are follow:
1. Set GRSTCTL_CSFTRST bit.
2. Wait for bit GRSTCTL_CSFTRST_DONE is set.
3. Clear GRSTCTL_CSFTRST and GRSTCTL_CSFTRST_DONE bits.
Check core version functionality separated from dwc2_get_hwparams() to
new dwc2_check_core_version() function because Core Reset flow depend
on SNPSID.
Signed-off-by: Minas Harutyunyan <hminas@synopsys.com>
Signed-off-by: Felipe Balbi <balbi@kernel.org>
Diffstat (limited to 'drivers/usb/dwc2/core.h')
| -rw-r--r-- | drivers/usb/dwc2/core.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h index 668d1ad646a4..132d687f1590 100644 --- a/drivers/usb/dwc2/core.h +++ b/drivers/usb/dwc2/core.h @@ -1103,8 +1103,10 @@ struct dwc2_hsotg { #define DWC2_CORE_REV_3_00a 0x4f54300a #define DWC2_CORE_REV_3_10a 0x4f54310a #define DWC2_CORE_REV_4_00a 0x4f54400a +#define DWC2_CORE_REV_4_20a 0x4f54420a #define DWC2_FS_IOT_REV_1_00a 0x5531100a #define DWC2_HS_IOT_REV_1_00a 0x5532100a +#define DWC2_CORE_REV_MASK 0x0000ffff /* DWC OTG HW Core ID */ #define DWC2_OTG_ID 0x4f540000 @@ -1309,6 +1311,8 @@ void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg); bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg); +int dwc2_check_core_version(struct dwc2_hsotg *hsotg); + /* * Common core Functions. * The following functions support managing the DWC_otg controller in either |