diff options
| author | Cédric Le Goater <clg@kaod.org> | 2019-09-25 15:42:37 +0300 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2021-11-01 09:42:41 +0300 |
| commit | 87c56608f11d1ac43dd8067474f3d799d30d6b47 (patch) | |
| tree | a0a3f0465aecb6c507d8171026d2a74981711210 /drivers | |
| parent | 59b049dc3a89e496819dd7faed582cf49a3553ab (diff) | |
| download | linux-87c56608f11d1ac43dd8067474f3d799d30d6b47.tar.xz | |
mtd: spi-nor: aspeed: Introduce a HCLK mask for training
The AST2600 handles more HCLK divisors than its predecessors.
OpenBMC-Staging-Count: 7
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mtd/spi-nor/controllers/aspeed-smc.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/drivers/mtd/spi-nor/controllers/aspeed-smc.c b/drivers/mtd/spi-nor/controllers/aspeed-smc.c index 58c7ad96e811..74b5a9a89350 100644 --- a/drivers/mtd/spi-nor/controllers/aspeed-smc.c +++ b/drivers/mtd/spi-nor/controllers/aspeed-smc.c @@ -41,6 +41,7 @@ struct aspeed_smc_info { u8 we0; /* shift for write enable bit for CE0 */ u8 ctl0; /* offset in regs of ctl for CE0 */ u8 timing; /* offset in regs of timing */ + u32 hclk_mask; /* clock frequency mask in CEx Control reg */ u32 hdiv_max; /* Max HCLK divisor on read timing reg */ void (*set_4b)(struct aspeed_smc_chip *chip); @@ -75,6 +76,7 @@ static const struct aspeed_smc_info fmc_2400_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, @@ -91,6 +93,7 @@ static const struct aspeed_smc_info spi_2400_info = { .we0 = 0, .ctl0 = 0x04, .timing = 0x14, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b_spi_2400, .optimize_read = aspeed_smc_optimize_read, @@ -105,6 +108,7 @@ static const struct aspeed_smc_info fmc_2500_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, @@ -121,6 +125,7 @@ static const struct aspeed_smc_info spi_2500_info = { .we0 = 16, .ctl0 = 0x10, .timing = 0x94, + .hclk_mask = 0xfffff0ff, .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, .optimize_read = aspeed_smc_optimize_read, @@ -1058,7 +1063,7 @@ static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); /* Establish our read mode with freq field set to 0 (HCLK/16) */ - chip->ctl_val[smc_read] = save_read_val & 0xfffff0ff; + chip->ctl_val[smc_read] = save_read_val & info->hclk_mask; /* Check if calibration data is suitable */ if (!aspeed_smc_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) { |