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authorThierry Reding <treding@nvidia.com>2017-08-30 13:05:26 +0300
committerThierry Reding <treding@nvidia.com>2017-10-17 14:31:10 +0300
commit4d1dc40185735e285576d7ed865b065c5cabe40c (patch)
tree6acfc12559ef2ff39678fd3fb8416ed1643e7f35 /include/dt-bindings
parent2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff)
downloadlinux-4d1dc40185735e285576d7ed865b065c5cabe40c.tar.xz
dt-bindings: clock: tegra: Add sor1_out clock
The sor1_src clock implemented on Tegra210 is modelled the wrong way around, which causes some issues with HDMI and DP support. This clock implementation is provided by BPMP on Tegra186, which models this in a more correct way. Since this introduces incompatibilities between the two SoC generations which we want to avoid, the Tegra210 will be fixed in subsequent patches. This change adds sor1_out as an alias for sor1_src. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/tegra210-car.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index 46689cd3750b..43c4a8407333 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -309,6 +309,7 @@
#define TEGRA210_CLK_BLINK 280
/* 281 */
#define TEGRA210_CLK_SOR1_SRC 282
+#define TEGRA210_CLK_SOR1_OUT 282
/* 283 */
#define TEGRA210_CLK_XUSB_HOST_SRC 284
#define TEGRA210_CLK_XUSB_FALCON_SRC 285