summaryrefslogtreecommitdiff
path: root/include/linux/edac.h
diff options
context:
space:
mode:
authorYazen Ghannam <Yazen.Ghannam@amd.com>2016-11-18 01:57:28 +0300
committerBorislav Petkov <bp@suse.de>2016-11-21 11:31:59 +0300
commit1e8096bb2031c53b6bf3adc7667b4b2bdf2a1ac6 (patch)
tree68e40ab29b0fa5931d1d35749a7b00333a2114dc /include/linux/edac.h
parent27bda205ba93c02d8b5dcd1d5c2acc84d889ca6a (diff)
downloadlinux-1e8096bb2031c53b6bf3adc7667b4b2bdf2a1ac6.tar.xz
EDAC: Add LRDDR4 DRAM type
AMD Fam17h systems can support Load-Reduced DDR4 DIMMs. So add this new type to edac.h in preparation for the Fam17h EDAC update. Also, let's fix a format issue with the LRDDR3 line while we're here. Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com> Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1479423463-8536-3-git-send-email-Yazen.Ghannam@amd.com Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'include/linux/edac.h')
-rw-r--r--include/linux/edac.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/linux/edac.h b/include/linux/edac.h
index 9e0d78966552..bf2bf87bb2f9 100644
--- a/include/linux/edac.h
+++ b/include/linux/edac.h
@@ -192,10 +192,11 @@ static inline char *mc_event_error_type(const unsigned int err_type)
* @MEM_DDR3: DDR3 RAM
* @MEM_RDDR3: Registered DDR3 RAM
* This is a variant of the DDR3 memories.
- * @MEM_LRDDR3 Load-Reduced DDR3 memory.
+ * @MEM_LRDDR3: Load-Reduced DDR3 memory.
* @MEM_DDR4: Unbuffered DDR4 RAM
* @MEM_RDDR4: Registered DDR4 RAM
* This is a variant of the DDR4 memories.
+ * @MEM_LRDDR4: Load-Reduced DDR4 memory.
*/
enum mem_type {
MEM_EMPTY = 0,
@@ -218,6 +219,7 @@ enum mem_type {
MEM_LRDDR3,
MEM_DDR4,
MEM_RDDR4,
+ MEM_LRDDR4,
};
#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
@@ -239,6 +241,7 @@ enum mem_type {
#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
#define MEM_FLAG_DDR4 BIT(MEM_DDR4)
#define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
+#define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
/**
* enum edac-type - Error Detection and Correction capabilities and mode