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authorSaeed Mahameed <saeedm@mellanox.com>2015-06-11 14:47:28 +0300
committerDavid S. Miller <davem@davemloft.net>2015-06-12 01:55:25 +0300
commitfc11fbf9a785b25c5d07f05a30d4169ec39818da (patch)
treea4f8e88672f5c4b302493f89746854a34438b074 /include/linux/mlx5
parentfacc9699f0fe7d65a92cc09e175662659306066d (diff)
downloadlinux-fc11fbf9a785b25c5d07f05a30d4169ec39818da.tar.xz
net/mlx5e: Add HW cacheline start padding
Enable HW cacheline start padding and align RX WQE size to cacheline while considering HW start padding. Also, fix dma_unmap call to use the correct SKB data buffer size. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/mlx5')
-rw-r--r--include/linux/mlx5/device.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index b2c43508a737..b943cd9e2097 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -132,6 +132,10 @@ enum {
};
enum {
+ MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
+};
+
+enum {
MLX5_MIN_PKEY_TABLE_SIZE = 128,
MLX5_MAX_LOG_PKEY_TABLE = 5,
};