diff options
153 files changed, 34000 insertions, 2559 deletions
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index c4894b716fbe..ba465b6fa8e5 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2579,6 +2579,9 @@ deep - Suspend-To-RAM or equivalent (if supported) See Documentation/admin-guide/pm/sleep-states.rst. + mem.devmem= Activate the /dev/mem device + Format: <bool> (1/Y/y=enable, 0/N/n=disable) + meye.*= [HW] Set MotionEye Camera parameters See Documentation/media/v4l-drivers/meye.rst. diff --git a/Documentation/devicetree/bindings/bmc/npcm7xx-lpc-bpc.txt b/Documentation/devicetree/bindings/bmc/npcm7xx-lpc-bpc.txt new file mode 100644 index 000000000000..0832c9cbea32 --- /dev/null +++ b/Documentation/devicetree/bindings/bmc/npcm7xx-lpc-bpc.txt @@ -0,0 +1,26 @@ +Nuvoton NPCM7xx LPC BPC interface + +Nuvoton BMC NPCM7xx BIOS Post Code (BPC) monitoring two +configurable I/O addresses written by the host on the +Low Pin Count (LPC) bus, the capure data stored in 128-word FIFO. + +NPCM7xx BPC supports capture double words, when using capture +double word only I/O address 1 is monitored. + +Required properties for lpc_bpc node +- compatible : "nuvoton,npcm750-lpc-bpc" for Poleg NPCM7XX. +- reg : specifies physical base address and size of the registers. +- interrupts : contain the LPC BPC with flags for falling edge. +- monitor-ports : contain monitor I/O addresses, at least one monitor I/O + address required + +Optional property for lpc_bpc node +- bpc-en-dwcapture : enable capture double words support. + +Example: + lpc_bpc: lpc-bpc@f0007040 { + compatible = "nuvoton,npcm7xx-lpc-bpc"; + reg = <0xf0007040 0x14>; + monitor-ports = <0x80>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/bmc/npcm7xx-pci-mbox.txt b/Documentation/devicetree/bindings/bmc/npcm7xx-pci-mbox.txt new file mode 100644 index 000000000000..e5585f38041b --- /dev/null +++ b/Documentation/devicetree/bindings/bmc/npcm7xx-pci-mbox.txt @@ -0,0 +1,19 @@ +Nuvoton NPCM7xx PCI mail box interface + +Nuvoton BMC NPCM7xx PCI mail box, The mailbox is a high-bandwidth +communication module between the BMC CPU and host CPU. + +Required properties for lpc_bpc node +- compatible : "nuvoton,npcm750-pci-mbox" for Poleg NPCM7XX. +- reg : specifies two address space + 1. physical base address and size of the registers. + 2. physical base address and size of the dual-ported RAM. +- interrupts : contain the PCI mail box interrupt with flags for falling edge. + +Example: + pcimbox: pcimbox@f0848000 { + compatible = "nuvoton,npcm750-pci-mbox", "simple-mfd", "syscon"; + reg = <0xf084C000 0x8 + 0xf0848000 0x3F00>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt new file mode 100644 index 000000000000..dd4dac59a5bd --- /dev/null +++ b/Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt @@ -0,0 +1,17 @@ +Nuvoton NPCM7xx SoC EDAC device driver + +The Nuvoton NPCM7xx SoC supports DDR4 memory with/without ECC and the driver +uses the EDAC framework to implement the ECC detection and corrtection. + +Required properties: +- compatible: should be "nuvoton,npcm7xx-sdram-edac" +- reg: Memory controller register set should be <0xf0824000 0x1000> +- interrupts: should be MC interrupt #25 + +Example: + + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm7xx-sdram-edac"; + reg = <0xf0824000 0x1000>; + interrupts = <0 25 4>; + }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/max31785.txt b/Documentation/devicetree/bindings/hwmon/pmbus/max31785.txt new file mode 100644 index 000000000000..af9578e7742c --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/max31785.txt @@ -0,0 +1,158 @@ +Bindings for the Maxim MAX31785 Intelligent Fan Controller +========================================================== + +Reference: + +https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf + +Required properties: +- compatible : One of "maxim,max31785" or "maxim,max31785a" +- reg : I2C address, one of 0x52, 0x53, 0x54, 0x55. +- #address-cells : Must be 1 +- #size-cells : Must be 0 +- #thermal-sensor-cells : Should be 1. The device supports: + - One internal sensor + - Four external I2C digital sensors + - Six external thermal diodes + +Optional properties: +- use-stored-presence : Do not treat the devicetree description as canon for + fan presence (the 'installed' bit of FAN_CONFIG_*). + Instead, rely on the on the default value store of + the device to populate it. + +Capabilities are configured through subnodes of the controller's node. + +Fans +---- + +Only fans with subnodes present will be considered as installed. If +use-stored-presence is present in the parent node, then only fans that are both +defined in the devicetree and have their installed bit set are considered +installed. + +Required subnode properties: +- compatible : Must be "pmbus-fan" +- reg : The PMBus page the properties apply to. +- #cooling-cells : Should be 2. See the thermal bindings at [1]. +- maxim,fan-rotor-input : The type of rotor measurement provided to the + controller. Must be either "tach" for tachometer + pulses or "lock" for a locked-rotor signal. +- maxim,fan-lock-polarity: Required iff maxim,fan-rotor-input is "lock". Valid + values are "low" for active low, "high" for active + high. + +Optional subnode properties: +- fan-mode : "rpm" or "pwm". Default value is "pwm". +- tach-pulses : Tachometer pulses per revolution. Valid values are + 1, 2, 3 or 4. The default is 1. +- cooling-min-level : Smallest cooling state accepted. See [1]. +- cooling-max-level : Largest cooling state accepted. See [1]. +- maxim,fan-no-fault-ramp: Do not ramp the fan to 100% PWM duty on detecting a + fan fault +- maxim,fan-startup : The number of rotations required before taking + emergency action for an unresponsive fan and driving + it with 100% or 0% PWM duty, depending on the state + of maxim,fan-no-fault-ramp. Valid values are 0 + (automatic spin-up disabled), 2, 4, or 8. Default + value is 0. +- maxim,fan-health : Enable automated fan health check +- maxim,fan-ramp : Configures how fast the device ramps the PWM duty + cycle from one value to another. Valid values are 0 + to 7 inclusive, with values 0 - 2 configuring a + 1000ms update rate and 1 - 3% duty respective duty + increase, and 3 - 7 a 200ms update rate with a 1 - + 5% respective duty increase. Default value is 0. +- maxim,fan-no-watchdog : Do not ramp fan to 100% PWM duty on failure to + update desired fan rate inside 10s. This implies + maxim,tmp-no-fault-ramp +- maxim,tmp-no-fault-ramp: Do not ramp fan to 100% PWM duty on temperature + sensor fault detection. This implies + maxim,fan-no-watchdog +- maxim,tmp-hysteresis : The temperature hysteresis used to determine + transitions to lower fan speed bands in the + temperature/fan rate lookup table. Valid values are + 2, 4, 6 or 8 (degrees celcius). Default value is 2. +- maxim,fan-dual-tach : Enable dual tachometer functionality +- maxim,fan-pwm-freq : The PWM frequency. Valid values are 30, 50, 100, 150 + and 25000 (Hz). Default value is 30Hz. +- maxim,fan-lookup-table : A 16-element cell array of alternating temperature + and rate values representing the look up table. The + rate units are set through the fan-mode property. +- maxim,fan-fault-pin-mon: Ramp fans to 100% PWM duty when the FAULT pin is + asserted + +Temperature +----------- + +Required subnode properties: +- compatible : Must be "pmbus-temperature" +- reg : The PMBus page the properties apply to. + +Optional subnode properties: +- maxim,tmp-offset : Valid values are 0 - 30 (degrees celcius) inclusive. + Default value is 0. +- maxim,tmp-fans : An array of phandles to fans controlled by the + current temperature sensor. + +[1] Documentation/devicetree/bindings/thermal/thermal.txt + +Example: + fan-max31785: max31785@52 { + reg = <0x52>; + compatible = "maxim,max31785"; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + mode = "rpm"; + tach-pulses = <1>; + + #cooling-cells = <2>; + cooling-min-level = <0>; + cooling-max-level = <9>; + + maxim,fan-rotor-input = "tach"; + maxim,fan-dual-tach; + }; + + /* + * Hardware controlled fan: Fan speed is controlled by a + * temperature sensor feeding values into the lookup table. The + * fan association is done in the temperature sensor node. One + * sensor can drive multiple fans. + */ + cpu_fan: fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + mode = "rpm"; + tach-pulses = <1>; + + #cooling-cells = <2>; + + maxim,fan-rotor-input = "tach"; + maxim,tmp-hysteresis = <2>; + maxim,fan-lookup-table = < + /* Temperature RPM */ + 0 1000 + 10 2000 + 20 3000 + 30 4000 + 40 5000 + 50 6000 + 60 7000 + 70 8000 + >; + }; + + cpu_temp: sensor@6 { + compatible = "pmbus-temperature"; + reg = <6>; + + maxim,tmp-offset = <0>; + maxim,tmp-fans = <&cpu_fan>; + }; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-npcm7xx.txt b/Documentation/devicetree/bindings/i2c/i2c-npcm7xx.txt new file mode 100644 index 000000000000..0ecae950748b --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-npcm7xx.txt @@ -0,0 +1,29 @@ +Nuvoton NPCM7XX I2C bus + +The NPCM750x includes sixteen I2C bus controllers. All Controllers support +both master and slave mode. Each controller has two 16 byte HW FIFO for TX and +RX. + +Required properties: +- compatible : must be "nuvoton,npcm750-i2c" +- reg : Offset and length of the register set for the device. +- interrupts : Contain the I2C interrupt with flags for falling edge. +- clocks : phandle of I2C reference clock. + +Optional: +- bus-frequency : Contain the I2C bus frequency, + the default I2C bus frequency is 100000. +- pinctrl-0 : must be <&smbX_pins>, X is module number + (on NPCM7XX it's 0 to 15) +- pinctrl-names : should be set to "default" +Example: + + i2c0: i2c@80000 { + compatible = "nuvoton,npcm750-i2c"; + reg = <0x80000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + }; diff --git a/Documentation/devicetree/bindings/mfd/intel-peci-client.txt b/Documentation/devicetree/bindings/mfd/intel-peci-client.txt new file mode 100644 index 000000000000..5d1d5d0a552f --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/intel-peci-client.txt @@ -0,0 +1,34 @@ +* Intel PECI client bindings + +PECI (Platform Environment Control Interface) is a one-wire bus interface that +provides a communication channel from PECI clients in Intel processors and +chipset components to external monitoring or control devices. PECI is designed +to support the following sideband functions: + +- Processor and DRAM thermal management +- Platform Manageability +- Processor Interface Tuning and Diagnostics +- Failure Analysis + +Required properties: +- compatible : Should be "intel,peci-client". +- reg : Should contain address of a client CPU. According to the PECI + specification, client addresses start from 0x30. + +Example: + peci-bus@0 { + compatible = "vendor,soc-peci"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + peci-client@30 { + compatible = "intel,peci-client"; + reg = <0x30>; + }; + + peci-client@31 { + compatible = "intel,peci-client"; + reg = <0x31>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/nuvoton,npcm7xx-emc.txt b/Documentation/devicetree/bindings/net/nuvoton,npcm7xx-emc.txt new file mode 100644 index 000000000000..4227597401f5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/nuvoton,npcm7xx-emc.txt @@ -0,0 +1,36 @@ +Nuvoton NPCM7XX 10/100 Ethernet MAC Controller (EMC) + +The NPCM750x provides two identical Ethernet MAC Controllers +for WAN/LAN applications + +Required properties: +- device_type : Should be "network" +- compatible : "nuvoton,npcm750-emc" for Poleg NPCM750. +- reg : Offset and length of the register set for the device. +- interrupts : Contain the emc interrupts with flags for falling edge. + first interrupt dedicated to Txirq + second interrupt dedicated to Rxirq +- phy-mode : Should be "rmii" (see ethernet.txt in the same directory) +- clocks : phandle of emc reference clock. +- use-ncsi : Use the NC-SI stack instead of an MDIO PHY + +Example: + +emc0: eth@f0825000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0825000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + phy-mode = "rmii"; + clocks = <&clk NPCM7XX_CLK_AHB>; + + #use-ncsi; /* add this to support ncsi */ + + clock-names = "clk_emc"; + pinctrl-names = "default"; + pinctrl-0 = <&r1_pins + &r1err_pins + &r1md_pins>; + status = "okay"; +};
\ No newline at end of file diff --git a/Documentation/devicetree/bindings/peci/peci-aspeed.txt b/Documentation/devicetree/bindings/peci/peci-aspeed.txt new file mode 100644 index 000000000000..cdca73a3b7d8 --- /dev/null +++ b/Documentation/devicetree/bindings/peci/peci-aspeed.txt @@ -0,0 +1,55 @@ +Device tree configuration for PECI buses on the AST24XX and AST25XX SoCs. + +Required properties: +- compatible : Should be one of: + "aspeed,ast2400-peci" + "aspeed,ast2500-peci" +- reg : Should contain PECI controller registers location and + length. +- #address-cells : Should be <1> required to define a client address. +- #size-cells : Should be <0> required to define a client address. +- interrupts : Should contain PECI controller interrupt. +- clocks : Should contain clock source for PECI controller. Should + reference the external oscillator clock in the second + cell. +- resets : Should contain phandle to reset controller with the reset + number in the second cell. +- clock-frequency : Should contain the operation frequency of PECI controller + in units of Hz. + 187500 ~ 24000000 + +Optional properties: +- msg-timing : Message timing negotiation period. This value will + determine the period of message timing negotiation to be + issued by PECI controller. The unit of the programmed + value is four times of PECI clock period. + 0 ~ 255 (default: 1) +- addr-timing : Address timing negotiation period. This value will + determine the period of address timing negotiation to be + issued by PECI controller. The unit of the programmed + value is four times of PECI clock period. + 0 ~ 255 (default: 1) +- rd-sampling-point : Read sampling point selection. The whole period of a bit + time will be divided into 16 time frames. This value will + determine the time frame in which the controller will + sample PECI signal for data read back. Usually in the + middle of a bit time is the best. + 0 ~ 15 (default: 8) +- cmd-timeout-ms : Command timeout in units of ms. + 1 ~ 60000 (default: 1000) + +Example: + peci0: peci-bus@0 { + compatible = "aspeed,ast2500-peci"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + msg-timing = <1>; + addr-timing = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + }; diff --git a/Documentation/devicetree/bindings/peci/peci-npcm.txt b/Documentation/devicetree/bindings/peci/peci-npcm.txt new file mode 100644 index 000000000000..ea5bead7e76a --- /dev/null +++ b/Documentation/devicetree/bindings/peci/peci-npcm.txt @@ -0,0 +1,38 @@ +Nuvoton NPCM Platform Environment Control Interface (PECI) bus + +Required properties: +- compatible : "nuvoton,npcm750-peci" for the NPCM7XX BMC. +- reg : specifies PECI physical base address and size of the registers. +- #address-cells : Should be <1> required to define a client address. +- #size-cells : Should be <0> required to define a client address. +- interrupts : Contain the PECI interrupt with flags for falling edge. +- clocks : phandle of PECI reference clock. + +Optional properties: +- cmd-timeout-ms : Command timeout in units of ms. + 1 ~ 60000 (default: 1000) +- pull-down : Defines the PECI I/O internal pull down operation. + 0 - pull down always enable (default) + 1 - pull down only during transactions. + 2 - pull down always disable. +- host-neg-bit-rate : Define host negotiation bit rate divider. + the host negotiation bit rate calculate with formula: + clock frequency[Hz] / [4 x {host-neg-bit-rate + 1}] + 7 ~ 31 (default: 15) +- high-volt-range : Adapts PECI I/O interface to voltage range, the property + is a boolean parameter define as follow: + false - PECI I/O interface voltage range of 0.8-1.06V. (default) + true - PECI I/O interface voltage range of 0.95-1.26V. + +Example: + peci: peci-bus@100000 { + compatible = "nuvoton,npcm750-peci"; + reg = <0x100000 0x200>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_APB3>; + cmd-timeout-ms = <1000>; + pull-down = <0>; + host-neg-bit-rate = <15>; + }; diff --git a/Documentation/devicetree/bindings/peci/peci.txt b/Documentation/devicetree/bindings/peci/peci.txt new file mode 100644 index 000000000000..71f26c7c6e58 --- /dev/null +++ b/Documentation/devicetree/bindings/peci/peci.txt @@ -0,0 +1,43 @@ +Generic device tree configuration for PECI adapters +=================================================== + +Required properties: +- #address-cells : Should be <1>. Read more about client addresses below. +- #size-cells : Should be <0>. Read more about client addresses below. + +The cells properties above define that an address of CPU clients of a PECI bus +are described by a single value. + +Example: + peci0: peci-bus@0 { + compatible = "vendor,soc-peci"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + }; + +Generic device tree configuration for PECI clients +================================================== + +Required properties: +- compatible : Should contain name of PECI client. +- reg : Should contain address of a client CPU. According to the PECI + specification, client addresses start from 0x30. + +Example: + peci-bus@0 { + compatible = "vendor,soc-peci"; + reg = <0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + peci-client@30 { + compatible = "intel,peci-client"; + reg = <0x30>; + }; + + peci-client@31 { + compatible = "intel,peci-client"; + reg = <0x31>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt new file mode 100644 index 000000000000..a388005842ad --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt @@ -0,0 +1,47 @@ +* Nuvoton FLASH Interface Unit (FIU) SPI Controller + +NPCM FIU supports single, dual and quad communication interface. + +The NPCM7XX supports three FIU modules, +FIU0 and FIUx supports two chip selects, +FIU3 support four chip select. + +Required properties: + - compatible : "nuvoton,npcm750-fiu" for the NPCM7XX BMC + - #address-cells : should be 1. + - #size-cells : should be 0. + - reg : the first contains the register location and length, + the second contains the memory mapping address and length + - reg-names: Should contain the reg names "control" and "memory" + - clocks : phandle of FIU reference clock. + +Required properties in case the pins can be muxed: + - pinctrl-names : a pinctrl state named "default" must be defined. + - pinctrl-0 : phandle referencing pin configuration of the device. + +Optional property: + - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. + +Aliases: +- All the FIU controller nodes should be represented in the aliases node using + the following format 'fiu{n}' where n is a unique number for the alias. + In the NPCM7XX BMC: + fiu0 represent fiu 0 controller + fiu1 represent fiu 3 controller + fiu2 represent fiu x controller + +Example: +fiu3: spi@c00000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_AHB>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + spi-nor@0 { + ... + }; +}; + diff --git a/Documentation/hwmon/peci-cputemp b/Documentation/hwmon/peci-cputemp new file mode 100644 index 000000000000..821a9258f2e6 --- /dev/null +++ b/Documentation/hwmon/peci-cputemp @@ -0,0 +1,78 @@ +Kernel driver peci-cputemp +========================== + +Supported chips: + One of Intel server CPUs listed below which is connected to a PECI bus. + * Intel Xeon E5/E7 v3 server processors + Intel Xeon E5-14xx v3 family + Intel Xeon E5-24xx v3 family + Intel Xeon E5-16xx v3 family + Intel Xeon E5-26xx v3 family + Intel Xeon E5-46xx v3 family + Intel Xeon E7-48xx v3 family + Intel Xeon E7-88xx v3 family + * Intel Xeon E5/E7 v4 server processors + Intel Xeon E5-16xx v4 family + Intel Xeon E5-26xx v4 family + Intel Xeon E5-46xx v4 family + Intel Xeon E7-48xx v4 family + Intel Xeon E7-88xx v4 family + * Intel Xeon Scalable server processors + Intel Xeon Bronze family + Intel Xeon Silver family + Intel Xeon Gold family + Intel Xeon Platinum family + Addresses scanned: PECI client address 0x30 - 0x37 + Datasheet: Available from http://www.intel.com/design/literature.htm + +Author: + Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +Description +----------- + +This driver implements a generic PECI hwmon feature which provides Digital +Thermal Sensor (DTS) thermal readings of the CPU package and CPU cores that are +accessible using the PECI Client Command Suite via the processor PECI client. + +All temperature values are given in millidegree Celsius and will be measurable +only when the target CPU is powered on. + +sysfs attributes +---------------- + +temp1_label "Die" +temp1_input Provides current die temperature of the CPU package. +temp1_max Provides thermal control temperature of the CPU package + which is also known as Tcontrol. +temp1_crit Provides shutdown temperature of the CPU package which + is also known as the maximum processor junction + temperature, Tjmax or Tprochot. +temp1_crit_hyst Provides the hysteresis value from Tcontrol to Tjmax of + the CPU package. + +temp2_label "Tcontrol" +temp2_input Provides current Tcontrol temperature of the CPU + package which is also known as Fan Temperature target. + Indicates the relative value from thermal monitor trip + temperature at which fans should be engaged. +temp2_crit Provides Tcontrol critical value of the CPU package + which is same to Tjmax. + +temp3_label "Tthrottle" +temp3_input Provides current Tthrottle temperature of the CPU + package. Used for throttling temperature. If this value + is allowed and lower than Tjmax - the throttle will + occur and reported at lower than Tjmax. + +temp4_label "Tjmax" +temp4_input Provides the maximum junction temperature, Tjmax of the + CPU package. + +temp[5-*]_label Provides string "Core X", where X is resolved core + number. +temp[5-*]_input Provides current temperature of each core. +temp[5-*]_max Provides thermal control temperature of the core. +temp[5-*]_crit Provides shutdown temperature of the core. +temp[5-*]_crit_hyst Provides the hysteresis value from Tcontrol to Tjmax of + the core. diff --git a/Documentation/hwmon/peci-dimmtemp b/Documentation/hwmon/peci-dimmtemp new file mode 100644 index 000000000000..c54f2526188c --- /dev/null +++ b/Documentation/hwmon/peci-dimmtemp @@ -0,0 +1,50 @@ +Kernel driver peci-dimmtemp +=========================== + +Supported chips: + One of Intel server CPUs listed below which is connected to a PECI bus. + * Intel Xeon E5/E7 v3 server processors + Intel Xeon E5-14xx v3 family + Intel Xeon E5-24xx v3 family + Intel Xeon E5-16xx v3 family + Intel Xeon E5-26xx v3 family + Intel Xeon E5-46xx v3 family + Intel Xeon E7-48xx v3 family + Intel Xeon E7-88xx v3 family + * Intel Xeon E5/E7 v4 server processors + Intel Xeon E5-16xx v4 family + Intel Xeon E5-26xx v4 family + Intel Xeon E5-46xx v4 family + Intel Xeon E7-48xx v4 family + Intel Xeon E7-88xx v4 family + * Intel Xeon Scalable server processors + Intel Xeon Bronze family + Intel Xeon Silver family + Intel Xeon Gold family + Intel Xeon Platinum family + Addresses scanned: PECI client address 0x30 - 0x37 + Datasheet: Available from http://www.intel.com/design/literature.htm + +Author: + Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +Description +----------- + +This driver implements a generic PECI hwmon feature which provides Digital +Thermal Sensor (DTS) thermal readings of DIMM components that are accessible +using the PECI Client Command Suite via the processor PECI client. + +All temperature values are given in millidegree Celsius and will be measurable +only when the target CPU is powered on. + +sysfs attributes +---------------- + +temp[N]_label Provides string "DIMM CI", where C is DIMM channel and + I is DIMM index of the populated DIMM. +temp[N]_input Provides current temperature of the populated DIMM. + +Note: + DIMM temperature attributes will appear when the client CPU's BIOS + completes memory training and testing. diff --git a/MAINTAINERS b/MAINTAINERS index 1d235c674be8..a8aec3e5a21f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1498,6 +1498,14 @@ F: arch/arm/mach-aspeed/ F: arch/arm/boot/dts/aspeed-* N: aspeed +ARM/ASPEED PECI DRIVER +M: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> +M: Jason M Biils <jason.m.bills@linux.intel.com> +L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/peci/peci-aspeed.txt +F: drivers/peci/peci-aspeed.c + ARM/BITMAIN ARCHITECTURE M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -5876,6 +5884,12 @@ L: linux-edac@vger.kernel.org S: Maintained F: drivers/edac/mpc85xx_edac.[ch] +EDAC-NPCM7XX +M: George Hung <george.hung@quantatw.com> +S: Maintained +F: drivers/edac/npcm7xx_edac.c +F: Documentation/devicetree/bindings/edac/npcm7xx-sdram-edac.txt + EDAC-PASEMI M: Egor Martovetsky <egor@pasemi.com> L: linux-edac@vger.kernel.org @@ -12593,6 +12607,20 @@ L: platform-driver-x86@vger.kernel.org S: Maintained F: drivers/platform/x86/peaq-wmi.c +PECI SUBSYSTEM +M: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> +M: Jason M Biils <jason.m.bills@linux.intel.com> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/peci/ +F: drivers/mfd/intel-peci-client.c +F: drivers/peci/ +F: drivers/hwmon/peci-*.c +F: drivers/hwmon/peci-hwmon.h +F: include/linux/mfd/intel-peci-client.h +F: include/linux/peci.h +F: include/uapi/linux/peci-ioctl.h + PER-CPU MEMORY ALLOCATOR M: Dennis Zhou <dennis@kernel.org> M: Tejun Heo <tj@kernel.org> diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 9b3d4deca9e4..44c34174fa55 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -159,6 +159,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000 machine-$(CONFIG_ARCH_ACTIONS) += actions machine-$(CONFIG_ARCH_ALPINE) += alpine machine-$(CONFIG_ARCH_ARTPEC) += artpec +machine-$(CONFIG_ARCH_ASPEED) += aspeed machine-$(CONFIG_ARCH_AT91) += at91 machine-$(CONFIG_ARCH_AXXIA) += axxia machine-$(CONFIG_ARCH_BCM) += bcm diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 9159fa2cea90..3ad9706337a2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -324,7 +324,8 @@ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb dtb-$(CONFIG_ARCH_NPCM7XX) += \ - nuvoton-npcm750-evb.dtb + nuvoton-npcm750-evb.dtb \ + nuvoton-npcm730-gsj.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ @@ -1268,19 +1269,27 @@ dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ + aspeed-ast2600-evb.dtb \ aspeed-bmc-arm-centriq2400-rep.dtb \ aspeed-bmc-arm-stardragon4800-rep2.dtb \ aspeed-bmc-facebook-cmm.dtb \ + aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ + aspeed-bmc-facebook-wedge40.dtb \ + aspeed-bmc-facebook-wedge100.dtb \ aspeed-bmc-facebook-yamp.dtb \ + aspeed-bmc-ibm-rainier.dtb \ aspeed-bmc-intel-s2600wf.dtb \ aspeed-bmc-inspur-fp5280g2.dtb \ aspeed-bmc-lenovo-hr630.dtb \ + aspeed-bmc-lenovo-hr855xg2.dtb \ aspeed-bmc-microsoft-olympus.dtb \ aspeed-bmc-opp-lanyang.dtb \ + aspeed-bmc-opp-mihawk.dtb \ aspeed-bmc-opp-palmetto.dtb \ aspeed-bmc-opp-romulus.dtb \ aspeed-bmc-opp-swift.dtb \ + aspeed-bmc-opp-tacoma.dtb \ aspeed-bmc-opp-vesnin.dtb \ aspeed-bmc-opp-witherspoon.dtb \ aspeed-bmc-opp-zaius.dtb \ diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts index 556ed469830c..8bec21ed0de5 100644 --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -40,6 +40,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -50,6 +51,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-max-frequency = <100000000>; }; }; @@ -94,6 +96,17 @@ }; }; +&sdmmc { + status = "okay"; +}; + +&sdhci0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_default>; +}; + /* * Enable port A as device (via the virtual hub) and port B as * host by default on the eval board. This can be easily changed diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts new file mode 100644 index 000000000000..b5121f2bdae8 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. + +/dts-v1/; + +#include "aspeed-g6.dtsi" + +/ { + model = "AST2600 EVB"; + compatible = "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; +}; + +&mdio1 { + status = "okay"; + + ethphy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mdio2 { + status = "okay"; + + ethphy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mdio3 { + status = "okay"; + + ethphy3: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + +&mac1 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default>; +}; + +&mac2 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; +}; + +&mac3 { + status = "okay"; + + phy-mode = "rgmii"; + phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + non-removable; + bus-width = <4>; + max-frequency = <52000000>; +}; + +&rtc { + status = "okay"; +}; + +&fsim0 { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x2000000>; // 32MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x2a00000 0x1600000>; // 22MB + label = "rwfs"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&uart5 { + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + +&i2c0 { + status = "okay"; + + temp@2e { + compatible = "adi,adt7490"; + reg = <0x2e>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts index 521afbea2c5b..f82dba54aa77 100644 --- a/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-arm-stardragon4800-rep2.dts @@ -92,6 +92,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii2_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, + <&syscon ASPEED_CLK_GATE_MAC2RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts new file mode 100644 index 000000000000..c05478296446 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-minipack.dts @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + model = "Facebook Minipack 100 BMC"; + compatible = "facebook,minipack-bmc", "aspeed,ast2500"; + + aliases { + /* + * Override the default serial aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + + /* + * i2c switch 2-0070, pca9548, 8 child channels assigned + * with bus number 16-23. + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + + /* + * i2c switch 8-0070, pca9548, 8 child channels assigned + * with bus number 24-31. + */ + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; + + /* + * i2c switch 9-0070, pca9548, 8 child channels assigned + * with bus number 32-39. + */ + i2c32 = &imux32; + i2c33 = &imux33; + i2c34 = &imux34; + i2c35 = &imux35; + i2c36 = &imux36; + i2c37 = &imux37; + i2c38 = &imux38; + i2c39 = &imux39; + + /* + * i2c switch 11-0070, pca9548, 8 child channels assigned + * with bus number 40-47. + */ + i2c40 = &imux40; + i2c41 = &imux41; + i2c42 = &imux42; + i2c43 = &imux43; + i2c44 = &imux44; + i2c45 = &imux45; + i2c46 = &imux46; + i2c47 = &imux47; + }; + + chosen { + stdout-path = &uart1; + bootargs = "debug console=ttyS1,9600n8 root=/dev/ram rw"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; +}; + +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&wdt2 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_ncts1_default + &pinctrl_ndsr1_default + &pinctrl_ndtr1_default + &pinctrl_nrts1_default>; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + no-hw-checksum; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; + bus-frequency = <400000>; + multi-master; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + multi-master; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux28: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux29: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux30: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux31: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c9 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + imux32: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux33: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux34: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux35: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux36: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux37: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux38: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux39: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + imux40: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux41: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux42: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux43: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + imux44: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + imux45: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + imux46: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + imux47: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts index c4521eda787c..0f30919fde3d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-tiogapass.dts @@ -12,6 +12,27 @@ aliases { serial0 = &uart1; serial4 = &uart5; + + /* + * Hardcode the bus number of i2c switches' channels to + * avoid breaking the legacy applications. + */ + i2c16 = &imux16; + i2c17 = &imux17; + i2c18 = &imux18; + i2c19 = &imux19; + i2c20 = &imux20; + i2c21 = &imux21; + i2c22 = &imux22; + i2c23 = &imux23; + i2c24 = &imux24; + i2c25 = &imux25; + i2c26 = &imux26; + i2c27 = &imux27; + i2c28 = &imux28; + i2c29 = &imux29; + i2c30 = &imux30; + i2c31 = &imux31; }; chosen { stdout-path = &uart5; @@ -25,13 +46,9 @@ iio-hwmon { compatible = "iio-hwmon"; io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, - <&adc 4>, <&adc 5>, <&adc 6>; + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; }; - iio-hwmon-battery { - compatible = "iio-hwmon"; - io-channels = <&adc 7>; - }; }; &fmc { @@ -109,6 +126,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; @@ -124,6 +144,215 @@ &i2c1 { status = "okay"; //X24 Riser + i2c-switch@71 { + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + imux16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + tmp75@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + tmp421@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-switch@73 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + + imux20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + }; + + }; + + imux17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + tmp421@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + tmp421@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-switch@73 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + + imux24: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux25: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux26: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux27: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + }; + + }; + + imux18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + ina230@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + tmp421@48 { + compatible = "ti,tmp75"; + reg = <0x48>; + }; + + tmp421@49 { + compatible = "ti,tmp75"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c-switch@73 { + compatible = "nxp,pca9546"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x73>; + + imux28: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + imux29: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + imux30: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + imux31: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + }; + + }; + + imux19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + i2c-switch@40 { + compatible = "ti,ina230"; + reg = <0x40>; + }; + + i2c-switch@41 { + compatible = "ti,ina230"; + reg = <0x41>; + }; + + i2c-switch@45 { + compatible = "ti,ina230"; + reg = <0x45>; + }; + + }; + + }; }; &i2c2 { @@ -144,6 +373,42 @@ &i2c5 { status = "okay"; // CPU Voltage regulators + regulator@48 { + compatible = "infineon,pxe1610"; + reg = <0x48>; + }; + regulator@4a { + compatible = "infineon,pxe1610"; + reg = <0x4a>; + }; + regulator@50 { + compatible = "infineon,pxe1610"; + reg = <0x50>; + }; + regulator@52 { + compatible = "infineon,pxe1610"; + reg = <0x52>; + }; + regulator@58 { + compatible = "infineon,pxe1610"; + reg = <0x58>; + }; + regulator@5a { + compatible = "infineon,pxe1610"; + reg = <0x5a>; + }; + regulator@68 { + compatible = "infineon,pxe1610"; + reg = <0x68>; + }; + regulator@70 { + compatible = "infineon,pxe1610"; + reg = <0x70>; + }; + regulator@72 { + compatible = "infineon,pxe1610"; + reg = <0x72>; + }; }; &i2c6 { diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts new file mode 100644 index 000000000000..b1e10f0c85c9 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge100.dts @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "aspeed-g4.dtsi" + +/ { + model = "Facebook Wedge 100 BMC"; + compatible = "facebook,wedge100-bmc", "aspeed,ast2400"; + + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; +}; + +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&wdt2 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "fmc0"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + no-hw-checksum; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts new file mode 100644 index 000000000000..aaa77a597d1a --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-wedge40.dts @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (c) 2018 Facebook Inc. +/dts-v1/; + +#include "aspeed-g4.dtsi" + +/ { + model = "Facebook Wedge 40 BMC"; + compatible = "facebook,wedge40-bmc", "aspeed,ast2400"; + + aliases { + /* + * Override the default uart aliases to avoid breaking + * the legacy applications. + */ + serial0 = &uart5; + serial1 = &uart1; + serial2 = &uart3; + serial3 = &uart4; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS2,9600n8 root=/dev/ram rw"; + }; + + memory@40000000 { + reg = <0x40000000 0x20000000>; + }; +}; + +&wdt1 { + status = "okay"; + aspeed,reset-type = "system"; +}; + +&wdt2 { + status = "disabled"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "fmc0"; +#include "facebook-bmc-flash-layout.dtsi" + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default + &pinctrl_rxd3_default>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default + &pinctrl_rxd4_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac1 { + status = "okay"; + no-hw-checksum; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts index 4e09a9cf32b7..32f7ef9db0a1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-yamp.dts @@ -90,6 +90,9 @@ no-hw-checksum; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &i2c0 { diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts new file mode 100644 index 000000000000..08e1db0ac672 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -0,0 +1,611 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "Rainier"; + compatible = "ibm,rainier-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@B8000000 { + no-map; + reg = <0xB8000000 0x04000000>; /* 64M */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(S, 0)>; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 1) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(S, 1)>; + }; + + ps2-presence { + label = "ps2-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(S, 2)>; + }; + + ps3-presence { + label = "ps3-presence"; + gpios = <&gpio0 ASPEED_GPIO(S, 3) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(S, 3)>; + }; + }; + +}; + +&emmc_controller { + status = "okay"; +}; + +&emmc { + status = "okay"; +}; + +&fsim0 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + power-supply@68 { + compatible = "ibm,cffps"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps"; + reg = <0x69>; + }; + + power-supply@6a { + compatible = "ibm,cffps"; + reg = <0x6a>; + }; + + power-supply@6b { + compatible = "ibm,cffps"; + reg = <0x6b>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; +}; + +&i2c5 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c6 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + tmp275@4b { + compatible = "ti,tmp275"; + reg = <0x4b>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + eeprom@52 { + compatible = "atmel,24c64"; + reg = <0x52>; + }; + + eeprom@53 { + compatible = "atmel,24c64"; + reg = <0x53>; + }; +}; + +&i2c7 { + status = "okay"; + + si7021-a20@20 { + compatible = "silabs,si7020"; + reg = <0x20>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + }; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + }; + + gpio@1 { + reg = <1>; + }; + + gpio@2 { + reg = <2>; + }; + + gpio@3 { + reg = <3>; + }; + + gpio@4 { + reg = <4>; + }; + + gpio@5 { + reg = <5>; + }; + + gpio@6 { + reg = <6>; + }; + + gpio@7 { + reg = <7>; + }; + + gpio@8 { + reg = <8>; + }; + + gpio@9 { + reg = <9>; + }; + + gpio@10 { + reg = <10>; + }; + + gpio@11 { + reg = <11>; + }; + + gpio@12 { + reg = <12>; + }; + + gpio@13 { + reg = <13>; + }; + + gpio@14 { + reg = <14>; + }; + + gpio@15 { + reg = <15>; + }; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c8 { + status = "okay"; + + ucd90320@b { + compatible = "ti,ucd90160"; + reg = <0x0b>; + }; + + ucd90320@c { + compatible = "ti,ucd90160"; + reg = <0x0c>; + }; + + ucd90320@11 { + compatible = "ti,ucd90160"; + reg = <0x11>; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c9 { + status = "okay"; + + ir35221@42 { + compatible = "infineon,ir35221"; + reg = <0x42>; + }; + + ir35221@43 { + compatible = "infineon,ir35221"; + reg = <0x43>; + }; + + ir35221@44 { + compatible = "infineon,ir35221"; + reg = <0x44>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + ir35221@73 { + compatible = "infineon,ir35221"; + reg = <0x73>; + }; + + ir35221@74 { + compatible = "infineon,ir35221"; + reg = <0x74>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c10 { + status = "okay"; + + ir35221@42 { + compatible = "infineon,ir35221"; + reg = <0x42>; + }; + + ir35221@43 { + compatible = "infineon,ir35221"; + reg = <0x43>; + }; + + ir35221@44 { + compatible = "infineon,ir35221"; + reg = <0x44>; + }; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + tmp423b@4d { + compatible = "ti,tmp423"; + reg = <0x4d>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + + ir35221@73 { + compatible = "infineon,ir35221"; + reg = <0x73>; + }; + + ir35221@74 { + compatible = "infineon,ir35221"; + reg = <0x74>; + }; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; +}; + +&i2c11 { + status = "okay"; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c14 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c15 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&vuart1 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_GATE_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>, + <&syscon ASPEED_CLK_GATE_MAC4RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts index 628195b66d46..e65207b938f8 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts @@ -148,14 +148,48 @@ }; leds { - compatible = "gpio-leds"; + compatible = "gpio-leds"; - power { - label = "power"; - /* TODO: dummy gpio */ - gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; - }; + power { + label = "power"; + /* TODO: dummy gpio */ + gpios = <&gpio ASPEED_GPIO(R, 1) GPIO_ACTIVE_LOW>; + }; + + init-ok { + label = "init-ok"; + gpios = <&gpio ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>; + }; + + front-memory { + label = "front-memory"; + gpios = <&gpio ASPEED_GPIO(F, 4) GPIO_ACTIVE_LOW>; + }; + + front-syshot { + label = "front-syshot"; + gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>; + }; + + front-syshealth { + label = "front-syshealth"; + gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>; + }; + front-fan { + label = "front-fan"; + gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>; + }; + + front-psu { + label = "front-psu"; + gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>; + }; + + identify { + label = "identify"; + gpios = <&gpio ASPEED_GPIO(Z, 7) GPIO_ACTIVE_LOW>; + }; }; iio-hwmon-battery { @@ -239,6 +273,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; @@ -725,9 +762,9 @@ reg = <0x58>; }; - power-supply@5a { + power-supply@59 { compatible = "pmbus"; - reg = <0x5a>; + reg = <0x59>; }; }; @@ -749,15 +786,6 @@ aspeed,external-nodes = <&gfx &lhc>; }; -&gpio { - pin_gpio_b7 { - gpio-hog; - gpios = <ASPEED_GPIO(B,7) GPIO_ACTIVE_LOW>; - output-high; - line-name = "BMC_INIT_OK"; - }; -}; - &wdt1 { aspeed,reset-type = "none"; aspeed,external-signal; diff --git a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts index 2337ee23f5c4..58a746b72d98 100644 --- a/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts +++ b/arch/arm/boot/dts/aspeed-bmc-inspur-on5263m5.dts @@ -77,6 +77,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts index 22dade6393d0..ae571129b6ec 100644 --- a/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts +++ b/arch/arm/boot/dts/aspeed-bmc-intel-s2600wf.dts @@ -69,6 +69,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts index d3695a32e8e0..d966616fb34a 100644 --- a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr630.dts @@ -133,6 +133,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts new file mode 100644 index 000000000000..8193fadeaec1 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-lenovo-hr855xg2.dts @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Device Tree file for Lenovo Hr855xg2 platform + * + * Copyright (C) 2019-present Lenovo + */ + +/dts-v1/; + +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> + +/ { + model = "HR855XG2 BMC"; + compatible = "lenovo,hr855xg2-bmc", "aspeed,ast2500"; + + aliases { + i2c14 = &i2c_riser1; + i2c15 = &i2c_riser2; + i2c16 = &i2c_riser3; + i2c17 = &i2c_M2; + i2c18 = &channel_0; + i2c19 = &channel_1; + i2c20 = &channel_2; + i2c21 = &channel_3; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=tty0 console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x00100000>; /* 1M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + gpios = <&gpio ASPEED_GPIO(C, 7) GPIO_ACTIVE_LOW>; + }; + + fault { + gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>, + <&adc 8>, <&adc 9>, <&adc 10>,<&adc 11>, + <&adc 12>,<&adc 13>,<&adc 14>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; + +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout.dtsi" + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&lpc_snoop { + status = "okay"; + snoop-ports = <0x80>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default>; +}; + +&uart2 { + /* Rear RS-232 connector */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default + &pinctrl_rxd2_default + &pinctrl_nrts2_default + &pinctrl_ndtr2_default + &pinctrl_ndsr2_default + &pinctrl_ncts2_default + &pinctrl_ndcd2_default + &pinctrl_nri2_default>; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&mac0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&adc{ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&i2c0 { + status = "okay"; + + i2c-switch@70 { + compatible = "nxp,pca9545"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c_riser1: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_riser2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_riser3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_M2: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c1 { + status = "okay"; + bus-frequency = <90000>; + HotSwap@10 { + compatible = "adm1272"; + reg = <0x10>; + }; + + VR@45 { + compatible = "pmbus"; + reg = <0x45>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + channel_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + channel_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + channel_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + channel_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + /* temp1 */ + tmp75@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + /* temp2 */ + tmp75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; + + eeprom@54 { + compatible = "atmel,24c256"; + reg = <0x54>; + pagesize = <16>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default + &pinctrl_pwm1_default + &pinctrl_pwm2_default + &pinctrl_pwm3_default + &pinctrl_pwm4_default + &pinctrl_pwm5_default + &pinctrl_pwm6_default + &pinctrl_pwm7_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; + + fan@12 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0c>; + }; + + fan@13 { + reg = <0x06>; + aspeed,fan-tach-ch = /bits/ 8 <0x0d>; + }; + + fan@14 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0e>; + }; + + fan@15 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; + + fan@16 { + reg = <0x07>; + aspeed,fan-tach-ch = /bits/ 8 <0x0f>; + }; +}; + +&gpio { + + pin_gpio_a1 { + gpio-hog; + gpios = <ASPEED_GPIO(A, 1) GPIO_ACTIVE_LOW>; + output-high; + line-name = "BMC_EMMC_RST_N"; + }; + + pin_gpio_a3 { + gpio-hog; + gpios = <ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>; + output-high; + line-name = "PCH_PWROK_BMC_FPGA"; + }; + + pin_gpio_b5 { + gpio-hog; + gpios = <ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + + pin_gpio_b7 { + gpio-hog; + gpios = <ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>; + output-low; + line-name = "CPU_SM_WP"; + }; + + pin_gpio_e0 { + gpio-hog; + gpios = <ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + input; + line-name = "PDB_PSU_SEL"; + }; + + pin_gpio_e2 { + gpio-hog; + gpios = <ASPEED_GPIO(E, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "LOCATOR_LED_N"; + }; + + pin_gpio_e5 { + gpio-hog; + gpios = <ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FM_BMC_DBP_PRESENT_R1_N"; + }; + + pin_gpio_e6 { + gpio-hog; + gpios = <ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_ME_SECURITY_OVERRIDE_N"; + }; + + pin_gpio_f0 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 0) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "IRQ_BMC_PCH_NMI_R"; + }; + + pin_gpio_f1 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 1) GPIO_ACTIVE_HIGH>; + input; + line-name = "CPU2_PROCDIS_BMC_N"; + }; + + pin_gpio_f2 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "RM_THROTTLE_EN_N"; + }; + + pin_gpio_f3 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 3) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "FM_PMBUS_ALERT_B_EN"; + }; + + pin_gpio_f4 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_FORCE_NM_THROTTLE_N"; + }; + + pin_gpio_f6 { + gpio-hog; + gpios = <ASPEED_GPIO(F, 6) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FM_BMC_CPU_PWR_DEBUG_N"; + }; + + pin_gpio_g7 { + gpio-hog; + gpios = <ASPEED_GPIO(G, 7) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_PCIE_I2C_MUX_RST_N"; + }; + + pin_gpio_h6 { + gpio-hog; + gpios = <ASPEED_GPIO(H, 6) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FM_BMC_DBP_PRESENT_R2_N"; + }; + + pin_gpio_i3 { + gpio-hog; + gpios = <ASPEED_GPIO(I, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SPI_BMC_BIOS_WP_N"; + }; + + pin_gpio_j1 { + gpio-hog; + gpios = <ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_USB_SEL"; + }; + + pin_gpio_j2 { + gpio-hog; + gpios = <ASPEED_GPIO(J, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PDB_SMB_RST_N"; + }; + + pin_gpio_j3 { + gpio-hog; + gpios = <ASPEED_GPIO(J, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SPI_BMC_BIOS_HOLD_N"; + }; + + pin_gpio_l0 { + gpio-hog; + gpios = <ASPEED_GPIO(L, 0) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PDB_FAN_TACH_SEL"; + }; + + pin_gpio_l1 { + gpio-hog; + gpios = <ASPEED_GPIO(L, 1) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "SYS_RESET_BMC_FPGA_N"; + }; + + pin_gpio_l4 { + gpio-hog; + gpios = <ASPEED_GPIO(L, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FM_EFUSE_FAN_G1_EN"; + }; + + pin_gpio_l5 { + gpio-hog; + gpios = <ASPEED_GPIO(L, 5) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FM_EFUSE_FAN_G2_EN"; + }; + + pin_gpio_r6 { + gpio-hog; + gpios = <ASPEED_GPIO(R, 6) GPIO_ACTIVE_HIGH>; + input; + line-name = "CPU3_PROCDIS_BMC_N"; + }; + + pin_gpio_r7 { + gpio-hog; + gpios = <ASPEED_GPIO(R, 7) GPIO_ACTIVE_HIGH>; + input; + line-name = "CPU4_PROCDIS_BMC_N"; + }; + + pin_gpio_s1 { + gpio-hog; + gpios = <ASPEED_GPIO(S, 1) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "DBP_SYSPWROK_BMC"; + }; + + pin_gpio_s2 { + gpio-hog; + gpios = <ASPEED_GPIO(S, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "PCH_RST_RSMRST_N"; + }; + + pin_gpio_s6 { + gpio-hog; + gpios = <ASPEED_GPIO(S, 6) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_HW_STRAP_5"; + }; + + pin_gpio_z3 { + gpio-hog; + gpios = <ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "FM_BMC_PCH_SCI_LPC_N"; + }; + + pin_gpio_aa0 { + gpio-hog; + gpios = <ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "FW_PSU_ALERT_EN_N"; + }; + + pin_gpio_aa4 { + gpio-hog; + gpios = <ASPEED_GPIO(AA, 4) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "DBP_CPU_PREQ_N"; + }; + + pin_gpio_ab3 { + gpio-hog; + gpios = <ASPEED_GPIO(AB, 3) GPIO_ACTIVE_HIGH>; + output-low; + line-name = "BMC_WDTRST"; + }; + + pin_gpio_ac6 { + gpio-hog; + gpios = <ASPEED_GPIO(AC, 6) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "ESPI_BMC_ALERT_N"; + }; + +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts index de95112e2a04..89dedaa920c5 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-lanyang.dts @@ -178,6 +178,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts new file mode 100644 index 000000000000..52e88b09c08b --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts @@ -0,0 +1,921 @@ +// SPDX-License-Identifier: GPL-2.0+ +/dts-v1/; +#include "aspeed-g5.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> + +/ { + model = "Mihawk BMC"; + compatible = "ibm,mihawk-bmc", "aspeed,ast2500"; + + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory@80000000 { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@98000000 { + no-map; + reg = <0x98000000 0x04000000>; /* 64M */ + }; + + gfx_memory: framebuffer { + size = <0x01000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + + video_engine_memory: jpegbuffer { + size = <0x02000000>; + alignment = <0x01000000>; + compatible = "shared-dma-pool"; + reusable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + air-water { + label = "air-water"; + gpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(F, 6)>; + }; + + checkstop { + label = "checkstop"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(J, 2)>; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(Z, 2)>; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(Z, 0)>; + }; + id-button { + label = "id-button"; + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(F, 1)>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca9552 9 GPIO_ACTIVE_LOW>; + linux,code = <9>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca9552 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca9552 11 GPIO_ACTIVE_LOW>; + linux,code = <11>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca9552 12 GPIO_ACTIVE_LOW>; + linux,code = <12>; + }; + + fan4-presence { + label = "fan4-presence"; + gpios = <&pca9552 13 GPIO_ACTIVE_LOW>; + linux,code = <13>; + }; + + fan5-presence { + label = "fan5-presence"; + gpios = <&pca9552 14 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + }; + + leds { + compatible = "gpio-leds"; + + fault { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>; + }; + + power { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>; + }; + + rear-id { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>; + }; + + rear-g { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>; + }; + + rear-ok { + retain-state-shutdown; + default-state = "keep"; + gpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>; + }; + + fan0 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 0 GPIO_ACTIVE_LOW>; + }; + + fan1 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 1 GPIO_ACTIVE_LOW>; + }; + + fan2 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 2 GPIO_ACTIVE_LOW>; + }; + + fan3 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 3 GPIO_ACTIVE_LOW>; + }; + + fan4 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 4 GPIO_ACTIVE_LOW>; + }; + + fan5 { + retain-state-shutdown; + default-state = "keep"; + gpios = <&pca9552 5 GPIO_ACTIVE_LOW>; + }; + }; + + fsi: gpio-fsi { + compatible = "fsi-master-gpio", "fsi-master"; + #address-cells = <2>; + #size-cells = <0>; + no-gpio-delays; + + clock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>; + mux-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>; + trans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>; + }; + iio-hwmon-12v { + compatible = "iio-hwmon"; + io-channels = <&adc 0>; + }; + + iio-hwmon-5v { + compatible = "iio-hwmon"; + io-channels = <&adc 1>; + }; + + iio-hwmon-3v { + compatible = "iio-hwmon"; + io-channels = <&adc 2>; + }; + + iio-hwmon-vdd0 { + compatible = "iio-hwmon"; + io-channels = <&adc 3>; + }; + + iio-hwmon-vdd1 { + compatible = "iio-hwmon"; + io-channels = <&adc 4>; + }; + + iio-hwmon-vcs0 { + compatible = "iio-hwmon"; + io-channels = <&adc 5>; + }; + + iio-hwmon-vcs1 { + compatible = "iio-hwmon"; + io-channels = <&adc 6>; + }; + + iio-hwmon-vdn0 { + compatible = "iio-hwmon"; + io-channels = <&adc 7>; + }; + + iio-hwmon-vdn1 { + compatible = "iio-hwmon"; + io-channels = <&adc 8>; + }; + + iio-hwmon-vio0 { + compatible = "iio-hwmon"; + io-channels = <&adc 9>; + }; + + iio-hwmon-vio1 { + compatible = "iio-hwmon"; + io-channels = <&adc 10>; + }; + + iio-hwmon-vddra { + compatible = "iio-hwmon"; + io-channels = <&adc 11>; + }; + + iio-hwmon-battery { + compatible = "iio-hwmon"; + io-channels = <&adc 12>; + }; + + iio-hwmon-vddrb { + compatible = "iio-hwmon"; + io-channels = <&adc 13>; + }; + + iio-hwmon-vddrc { + compatible = "iio-hwmon"; + io-channels = <&adc 14>; + }; + + iio-hwmon-vddrd { + compatible = "iio-hwmon"; + io-channels = <&adc 15>; + }; +}; + +&pwm_tacho { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default + &pinctrl_pwm2_default &pinctrl_pwm3_default + &pinctrl_pwm4_default &pinctrl_pwm5_default>; + + fan@0 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x00>; + }; + + fan@1 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x01>; + }; + + fan@2 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x02>; + }; + + fan@3 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x03>; + }; + + fan@4 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x04>; + }; + + fan@5 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x05>; + }; + + fan@6 { + reg = <0x00>; + aspeed,fan-tach-ch = /bits/ 8 <0x06>; + }; + + fan@7 { + reg = <0x01>; + aspeed,fan-tach-ch = /bits/ 8 <0x07>; + }; + + fan@8 { + reg = <0x02>; + aspeed,fan-tach-ch = /bits/ 8 <0x08>; + }; + + fan@9 { + reg = <0x03>; + aspeed,fan-tach-ch = /bits/ 8 <0x09>; + }; + + fan@10 { + reg = <0x04>; + aspeed,fan-tach-ch = /bits/ 8 <0x0a>; + }; + + fan@11 { + reg = <0x05>; + aspeed,fan-tach-ch = /bits/ 8 <0x0b>; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + label = "bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "obmc-ubi"; + }; + }; + }; + flash@1 { + status = "okay"; + label = "alt-bmc"; + m25p,fast-read; + spi-max-frequency = <50000000>; + partitions { + #address-cells = < 1 >; + #size-cells = < 1 >; + compatible = "fixed-partitions"; + u-boot@0 { + reg = < 0 0x60000 >; + label = "alt-u-boot"; + }; + u-boot-env@60000 { + reg = < 0x60000 0x20000 >; + label = "alt-u-boot-env"; + }; + obmc-ubi@80000 { + reg = < 0x80000 0x1F80000 >; + label = "alt-obmc-ubi"; + }; + }; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + label = "pnor"; + m25p,fast-read; + spi-max-frequency = <100000000>; + }; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&uart1 { + /* Rear RS-232 connector */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ndtr1_default + &pinctrl_ndsr1_default + &pinctrl_ncts1_default + &pinctrl_ndcd1_default + &pinctrl_nri1_default>; +}; + +&uart2 { + /* APSS */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; +}; + +&uart5 { + status = "okay"; +}; + +&mac0 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&mac1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + /* SAMTEC P0 */ + /* SAMTEC P1 */ + +}; + +&i2c3 { + status = "okay"; + + /* APSS */ + /* CPLD */ + + /* PCA9516 (repeater) -> + * CLK Buffer 9FGS9092 + * CLK Buffer 9DBL0651BKILFT + * CLK Buffer 9DBL0651BKILFT + * Power Supply 0 + * Power Supply 1 + * PCA 9552 LED + */ + + power-supply@58 { + compatible = "ibm,cffps1"; + reg = <0x58>; + }; + + power-supply@5b { + compatible = "ibm,cffps1"; + reg = <0x5b>; + }; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + + }; + +}; + +&i2c4 { + status = "okay"; + + /* CP0 VDD & VCS : IR35221 */ + /* CP0 VDN : IR35221 */ + /* CP0 VIO : IR38064 */ + /* CP0 VDDR : PXM1330 */ + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + +}; + +&i2c5 { + status = "okay"; + + /* CP0 VDD & VCS : IR35221 */ + /* CP0 VDN : IR35221 */ + /* CP0 VIO : IR38064 */ + /* CP0 VDDR : PXM1330 */ + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@72 { + compatible = "infineon,ir35221"; + reg = <0x72>; + }; + +}; + +&i2c6 { + status = "okay"; + + /* pca9548 -> NVMe1 to 8 */ + + pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + +}; + +&i2c7 { + status = "okay"; + + /* pca9548 -> NVMe9 to 16 */ + + pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + +}; + +&i2c8 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; +}; + +&i2c9 { + status = "okay"; + + /* pca9545 Riser -> + * PCIe x8 Slot3 + * PCIe x16 slot4 + * PCIe x8 slot5 + * I2C BMC RISER PCA9554 + * BMC SCL/SDA PCA9554 + * PCA9554 + */ + + /* pca9545 -> + * PCIe x16 Slot1 + * PCIe x8 slot2 + * PEX8748 + */ + + pca9545riser@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c-mux-idle-disconnect; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pca9545@71 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c-mux-idle-disconnect; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c10 { + status = "okay"; + + /* pca9545 Riser -> + * PCIe x8 Slot8 + * PCIe x16 slot9 + * PCIe x8 slot10 + * I2C BMC RISER PCA9554 + * BMC SCL/SDA PCA9554 + * PCA9554 + */ + + /* pca9545 -> + * PCIe x16 Slot1 + * PCIe x8 slot2 + * PEX8748 + */ + + pca9545riser@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c-mux-idle-disconnect; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pca9545@71 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + + i2c-mux-idle-disconnect; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c11 { + status = "okay"; + + /* TPM */ + /* RTC RX8900CE */ + /* FPGA for power sequence */ + /* TMP275A */ + /* TMP275A */ + /* EMC1462 */ + + tpm@57 { + compatible = "infineon,slb9645tt"; + reg = <0x57>; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + + tmp275@49 { + compatible = "ti,tmp275"; + reg = <0x49>; + }; + + /* chip emc1462 use emc1403 driver */ + emc1403@4c { + compatible = "smsc,emc1403"; + reg = <0x4c>; + }; + +}; + +&i2c12 { + status = "okay"; + + /* pca9545 -> + * SAS BP1 + * SAS BP2 + * NVMe BP + * M.2 riser + */ + + pca9545@70 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + interrupt-controller; + #interrupt-cells = <2>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + tmp275@48 { + compatible = "ti,tmp275"; + reg = <0x48>; + }; + }; + + }; + +}; + +&i2c13 { + status = "okay"; + + /* pca9548 -> + * NVMe BP + * NVMe HDD17 to 24 + */ + + pca9548@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; +}; + +&vuart { + status = "okay"; +}; + +&gfx { + status = "okay"; + memory-region = <&gfx_memory>; +}; + +&adc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default + &pinctrl_adc1_default + &pinctrl_adc2_default + &pinctrl_adc3_default + &pinctrl_adc4_default + &pinctrl_adc5_default + &pinctrl_adc6_default + &pinctrl_adc7_default + &pinctrl_adc8_default + &pinctrl_adc9_default + &pinctrl_adc10_default + &pinctrl_adc11_default + &pinctrl_adc12_default + &pinctrl_adc13_default + &pinctrl_adc14_default + &pinctrl_adc15_default>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + aspeed,alt-boot; +}; + +&ibt { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + status = "okay"; + memory-region = <&video_engine_memory>; +}; + +#include "ibm-power9-dual.dtsi" + diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts index b0cb34ccb135..eb4e93a57ff4 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -87,6 +87,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -99,6 +100,7 @@ flash@0 { status = "okay"; m25p,fast-read; + spi-max-frequency = <50000000>; label = "pnor"; }; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts index 9628ecb879cf..a2eef507ffbb 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts @@ -112,6 +112,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -125,6 +126,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-max-frequency = <100000000>; }; }; @@ -160,6 +162,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &i2c1 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts index caac895c60b4..f6197c70c231 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-swift.dts @@ -207,8 +207,8 @@ #size-cells = <0>; no-gpio-delays; - clock-gpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_HIGH>; - data-gpios = <&gpio ASPEED_GPIO(E, 0) GPIO_ACTIVE_HIGH>; + clock-gpios = <&gpio ASPEED_GPIO(P, 1) GPIO_ACTIVE_HIGH>; + data-gpios = <&gpio ASPEED_GPIO(P, 2) GPIO_ACTIVE_HIGH>; mux-gpios = <&gpio ASPEED_GPIO(P, 4) GPIO_ACTIVE_HIGH>; enable-gpios = <&gpio ASPEED_GPIO(P, 0) GPIO_ACTIVE_HIGH>; trans-gpios = <&gpio ASPEED_GPIO(P, 3) GPIO_ACTIVE_HIGH>; @@ -322,6 +322,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; use-ncsi; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &i2c2 { @@ -494,7 +497,7 @@ }; power-supply@68 { - compatible = "ibm,cffps1"; + compatible = "ibm,cffps2"; reg = <0x68>; }; @@ -504,7 +507,7 @@ }; power-supply@69 { - compatible = "ibm,cffps1"; + compatible = "ibm,cffps2"; reg = <0x69>; }; @@ -963,4 +966,15 @@ status = "okay"; }; +&sdmmc { + status = "okay"; +}; + +&sdhci1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_default>; +}; + #include "ibm-power9-dual.dtsi" diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts new file mode 100644 index 000000000000..e51e8839bd56 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts @@ -0,0 +1,801 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> + +/ { + model = "Tacoma"; + compatible = "ibm,tacoma-bmc", "aspeed,ast2600"; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + flash_memory: region@ba000000 { + no-map; + reg = <0xb8000000 0x4000000>; /* 64M */ + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + air-water { + label = "air-water"; + gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(Q, 7)>; + }; + + checkstop { + label = "checkstop"; + gpios = <&gpio0 ASPEED_GPIO(E, 3) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(E, 3)>; + }; + + ps0-presence { + label = "ps0-presence"; + gpios = <&gpio0 ASPEED_GPIO(H, 3) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(H, 3)>; + }; + + ps1-presence { + label = "ps1-presence"; + gpios = <&gpio0 ASPEED_GPIO(E, 5) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(E, 5)>; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&pca0 4 GPIO_ACTIVE_LOW>; + linux,code = <4>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&pca0 5 GPIO_ACTIVE_LOW>; + linux,code = <5>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&pca0 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&pca0 7 GPIO_ACTIVE_LOW>; + linux,code = <7>; + }; + }; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + + flash@0 { + status = "okay"; + m25p,fast-read; + label = "pnor"; + spi-max-frequency = <100000000>; + }; +}; + +&mac2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_GATE_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; + use-ncsi; +}; + +&emmc { + status = "okay"; +}; + +&fsim0 { + status = "okay"; + #address-cells = <2>; + #size-cells = <0>; + + cfam@0,0 { + reg = <0 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <0>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam0_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam0_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam0_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam0_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam0_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam0_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam0_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam0_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam0_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam0_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam0_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam0_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam0_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam0_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam0_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ0: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub0: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +&fsi_hub0 { + cfam@1,0 { + reg = <1 0>; + #address-cells = <1>; + #size-cells = <1>; + chip-id = <1>; + + scom@1000 { + compatible = "ibm,fsi2pib"; + reg = <0x1000 0x400>; + }; + + i2c@1800 { + compatible = "ibm,fsi-i2c-master"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + cfam1_i2c0: i2c-bus@0 { + reg = <0>; + }; + + cfam1_i2c1: i2c-bus@1 { + reg = <1>; + }; + + cfam1_i2c2: i2c-bus@2 { + reg = <2>; + }; + + cfam1_i2c3: i2c-bus@3 { + reg = <3>; + }; + + cfam1_i2c4: i2c-bus@4 { + reg = <4>; + }; + + cfam1_i2c5: i2c-bus@5 { + reg = <5>; + }; + + cfam1_i2c6: i2c-bus@6 { + reg = <6>; + }; + + cfam1_i2c7: i2c-bus@7 { + reg = <7>; + }; + + cfam1_i2c8: i2c-bus@8 { + reg = <8>; + }; + + cfam1_i2c9: i2c-bus@9 { + reg = <9>; + }; + + cfam1_i2c10: i2c-bus@a { + reg = <10>; + }; + + cfam1_i2c11: i2c-bus@b { + reg = <11>; + }; + + cfam1_i2c12: i2c-bus@c { + reg = <12>; + }; + + cfam1_i2c13: i2c-bus@d { + reg = <13>; + }; + + cfam1_i2c14: i2c-bus@e { + reg = <14>; + }; + }; + + sbefifo@2400 { + compatible = "ibm,p9-sbefifo"; + reg = <0x2400 0x400>; + #address-cells = <1>; + #size-cells = <0>; + + fsi_occ1: occ { + compatible = "ibm,p9-occ"; + }; + }; + + fsi_hub1: hub@3400 { + compatible = "fsi-master-hub"; + reg = <0x3400 0x400>; + #address-cells = <2>; + #size-cells = <0>; + + no-scan-on-init; + }; + }; +}; + +/* Legacy OCC numbering (to get rid of when userspace is fixed) */ +&fsi_occ0 { + reg = <1>; +}; + +&fsi_occ1 { + reg = <2>; +}; + +/ { + aliases { + i2c100 = &cfam0_i2c0; + i2c101 = &cfam0_i2c1; + i2c102 = &cfam0_i2c2; + i2c103 = &cfam0_i2c3; + i2c104 = &cfam0_i2c4; + i2c105 = &cfam0_i2c5; + i2c106 = &cfam0_i2c6; + i2c107 = &cfam0_i2c7; + i2c108 = &cfam0_i2c8; + i2c109 = &cfam0_i2c9; + i2c110 = &cfam0_i2c10; + i2c111 = &cfam0_i2c11; + i2c112 = &cfam0_i2c12; + i2c113 = &cfam0_i2c13; + i2c114 = &cfam0_i2c14; + i2c200 = &cfam1_i2c0; + i2c201 = &cfam1_i2c1; + i2c202 = &cfam1_i2c2; + i2c203 = &cfam1_i2c3; + i2c204 = &cfam1_i2c4; + i2c205 = &cfam1_i2c5; + i2c206 = &cfam1_i2c6; + i2c207 = &cfam1_i2c7; + i2c208 = &cfam1_i2c8; + i2c209 = &cfam1_i2c9; + i2c210 = &cfam1_i2c10; + i2c211 = &cfam1_i2c11; + i2c212 = &cfam1_i2c12; + i2c213 = &cfam1_i2c13; + i2c214 = &cfam1_i2c14; + }; + +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + bmp: bmp280@77 { + compatible = "bosch,bmp280"; + reg = <0x77>; + #io-channel-cells = <1>; + }; + + max31785@52 { + compatible = "maxim,max31785a"; + reg = <0x52>; + #address-cells = <1>; + #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + }; + + dps: dps310@76 { + compatible = "infineon,dps310"; + reg = <0x76>; + #io-channel-cells = <0>; + }; + + pca0: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + + gpio-controller; + #gpio-cells = <2>; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + power-supply@68 { + compatible = "ibm,cffps1"; + reg = <0x68>; + }; + + power-supply@69 { + compatible = "ibm,cffps1"; + reg = <0x69>; + }; +}; + +&i2c4 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c5 { + status = "okay"; + + tmp423a@4c { + compatible = "ti,tmp423"; + reg = <0x4c>; + }; + + ir35221@70 { + compatible = "infineon,ir35221"; + reg = <0x70>; + }; + + ir35221@71 { + compatible = "infineon,ir35221"; + reg = <0x71>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c9 { + status = "okay"; + + tmp275@4a { + compatible = "ti,tmp275"; + reg = <0x4a>; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + + pca9552: pca9552@60 { + compatible = "nxp,pca9552"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = "PS_SMBUS_RESET_N", "APSS_RESET_N", + "GPU0_TH_OVERT_N_BUFF", "GPU1_TH_OVERT_N_BUFF", + "GPU2_TH_OVERT_N_BUFF", "GPU3_TH_OVERT_N_BUFF", + "GPU4_TH_OVERT_N_BUFF", "GPU5_TH_OVERT_N_BUFF", + "GPU0_PWR_GOOD_BUFF", "GPU1_PWR_GOOD_BUFF", + "GPU2_PWR_GOOD_BUFF", "GPU3_PWR_GOOD_BUFF", + "GPU4_PWR_GOOD_BUFF", "GPU5_PWR_GOOD_BUFF", + "12V_BREAKER_FLT_N", "THROTTLE_UNLATCHED_N"; + + gpio@0 { + reg = <0>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@1 { + reg = <1>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@2 { + reg = <2>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@3 { + reg = <3>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@4 { + reg = <4>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@5 { + reg = <5>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@6 { + reg = <6>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@7 { + reg = <7>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@8 { + reg = <8>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@9 { + reg = <9>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@10 { + reg = <10>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@11 { + reg = <11>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@12 { + reg = <12>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@13 { + reg = <13>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@14 { + reg = <14>; + type = <PCA955X_TYPE_GPIO>; + }; + + gpio@15 { + reg = <15>; + type = <PCA955X_TYPE_GPIO>; + }; + }; + + rtc@32 { + compatible = "epson,rx8900"; + reg = <0x32>; + }; + + eeprom@51 { + compatible = "atmel,24c64"; + reg = <0x51>; + }; + + ucd90160@64 { + compatible = "ti,ucd90160"; + reg = <0x64>; + }; +}; + +&i2c12 { + status = "okay"; +}; + +&i2c13 { + status = "okay"; +}; + +&ibt { + status = "okay"; +}; + +&uart1 { + status = "okay"; + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + +&uart5 { + // Workaround for A0 + compatible = "snps,dw-apb-uart"; +}; + +&vuart1 { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; + memory-region = <&flash_memory>; + flash = <&spi1>; +}; + +&wdt1 { + aspeed,reset-type = "none"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; +}; + +&wdt2 { + status = "okay"; +}; + +&pinctrl { + /* Hog these as no driver is probed for the entire LPC block */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpc_default>, + <&pinctrl_lsirq_default>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts index 0b9e29c3212e..affd2c8743b1 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts @@ -43,6 +43,10 @@ gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>; }; + power_green { + gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>; + }; + id_blue { gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>; }; @@ -81,6 +85,12 @@ label = "bmc"; #include "openbmc-flash-layout.dtsi" }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt"; + }; }; &spi { @@ -222,3 +232,7 @@ &vuart { status = "okay"; }; + +&wdt2 { + aspeed,alt-boot; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts index 31ea34e14c79..c677b7f0fee3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts @@ -200,6 +200,7 @@ status = "okay"; label = "bmc"; m25p,fast-read; + spi-max-frequency = <50000000>; partitions { #address-cells = < 1 >; @@ -224,6 +225,7 @@ status = "okay"; label = "alt-bmc"; m25p,fast-read; + spi-max-frequency = <50000000>; partitions { #address-cells = < 1 >; @@ -242,7 +244,6 @@ label = "alt-obmc-ubi"; }; }; - }; }; @@ -255,6 +256,7 @@ status = "okay"; label = "pnor"; m25p,fast-read; + spi-max-frequency = <100000000>; }; }; @@ -293,6 +295,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; @@ -319,6 +324,58 @@ reg = <0x52>; #address-cells = <1>; #size-cells = <0>; + + fan@0 { + compatible = "pmbus-fan"; + reg = <0>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@1 { + compatible = "pmbus-fan"; + reg = <1>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@2 { + compatible = "pmbus-fan"; + reg = <2>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; + + fan@3 { + compatible = "pmbus-fan"; + reg = <3>; + tach-pulses = <2>; + maxim,fan-rotor-input = "tach"; + maxim,fan-pwm-freq = <25000>; + maxim,fan-dual-tach; + maxim,fan-no-watchdog; + maxim,fan-no-fault-ramp; + maxim,fan-ramp = <2>; + maxim,fan-fault-pin-mon; + }; }; dps: dps310@76 { diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts index 30624378316d..51e749b33fd3 100644 --- a/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts +++ b/arch/arm/boot/dts/aspeed-bmc-opp-zaius.dts @@ -130,6 +130,7 @@ status = "okay"; label = "bmc"; m25p,fast-read; + spi-max-frequency = <50000000>; #include "openbmc-flash-layout.dtsi" }; }; @@ -143,6 +144,7 @@ status = "okay"; label = "pnor"; m25p,fast-read; + spi-max-frequency = <100000000>; }; }; @@ -187,6 +189,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts index 33d704541de6..7cac89c7aca6 100644 --- a/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts +++ b/arch/arm/boot/dts/aspeed-bmc-portwell-neptune.dts @@ -80,12 +80,18 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii1_default &pinctrl_mdio1_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>, + <&syscon ASPEED_CLK_GATE_MAC1RCLK>; + clock-names = "MACCLK", "RCLK"; }; &mac1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_rmii2_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>, + <&syscon ASPEED_CLK_GATE_MAC2RCLK>; + clock-names = "MACCLK", "RCLK"; use-ncsi; }; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index dd4b0b15afcf..7984ff406d85 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -29,6 +29,7 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + peci0 = &peci0; }; cpus { @@ -65,6 +66,27 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@3 { + reg = < 3 >; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + flash@4 { + reg = < 4 >; + compatible = "jedec,spi-nor"; status = "disabled"; }; }; @@ -80,6 +102,7 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; @@ -162,7 +185,7 @@ #reset-cells = <1>; pinctrl: pinctrl { - compatible = "aspeed,g4-pinctrl"; + compatible = "aspeed,ast2400-pinctrl"; }; p2a: p2a-control { @@ -192,6 +215,34 @@ reg = <0x1e720000 0x8000>; // 32K }; + sdmmc: sd-controller@1e740000 { + compatible = "aspeed,ast2400-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@100 { + compatible = "aspeed,ast2400-sdhci"; + reg = <0x100 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@200 { + compatible = "aspeed,ast2400-sdhci"; + reg = <0x200 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + gpio: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; @@ -325,9 +376,20 @@ interrupts = <8>; status = "disabled"; }; + + sio_regs: regs { + compatible = "aspeed,bmc-misc"; + }; }; }; + peci: bus@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; @@ -371,6 +433,24 @@ }; }; +&peci { + peci0: peci-bus@0 { + compatible = "aspeed,ast2400-peci"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + msg-timing = <1>; + addr-timing = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + status = "disabled"; + }; +}; + &i2c { i2c_ic: interrupt-controller@0 { #interrupt-cells = <1>; @@ -1368,3 +1448,86 @@ groups = "WDTRST2"; }; }; + +&sio_regs { + sio_2b { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_2a { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_29 { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_28 { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <0>; + }; + sio_2f { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_2e { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_2d { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_2c { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <0>; + }; + sio_23 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_22 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_21 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_20 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <0>; + }; + sio_27 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_26 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_25 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_24 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <0>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 5b1ca265c2ce..8c843429319e 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -29,6 +29,7 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &vuart; + peci0 = &peci0; }; cpus { @@ -72,16 +73,19 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@2 { reg = < 2 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; @@ -97,11 +101,13 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; @@ -117,11 +123,13 @@ flash@0 { reg = < 0 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; flash@1 { reg = < 1 >; compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; status = "disabled"; }; }; @@ -215,7 +223,7 @@ #reset-cells = <1>; pinctrl: pinctrl { - compatible = "aspeed,g5-pinctrl"; + compatible = "aspeed,ast2500-pinctrl"; aspeed,external-nodes = <&gfx &lhc>; }; @@ -224,6 +232,10 @@ compatible = "aspeed,ast2500-p2a-ctrl"; status = "disabled"; }; + + vga_scratch: scratch { + compatible = "aspeed,bmc-misc"; + }; }; rng: hwrng@1e6e2078 { @@ -267,13 +279,41 @@ reg = <0x1e720000 0x9000>; // 36K }; + sdmmc: sd-controller@1e740000 { + compatible = "aspeed,ast2500-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@100 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x100 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@200 { + compatible = "aspeed,ast2500-sdhci"; + reg = <0x200 0x100>; + interrupts = <26>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + gpio: gpio@1e780000 { #gpio-cells = <2>; gpio-controller; compatible = "aspeed,ast2500-gpio"; reg = <0x1e780000 0x1000>; interrupts = <20>; - gpio-ranges = <&pinctrl 0 0 220>; + gpio-ranges = <&pinctrl 0 0 232>; clocks = <&syscon ASPEED_CLK_APB>; interrupt-controller; #interrupt-cells = <2>; @@ -438,9 +478,20 @@ interrupts = <8>; status = "disabled"; }; + + sio_regs: regs { + compatible = "aspeed,bmc-misc"; + }; }; }; + peci: bus@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + }; + uart2: serial@1e78d000 { compatible = "ns16550a"; reg = <0x1e78d000 0x20>; @@ -484,6 +535,24 @@ }; }; +&peci { + peci0: peci-bus@0 { + compatible = "aspeed,ast2500-peci"; + reg = <0x0 0x60>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <15>; + clocks = <&syscon ASPEED_CLK_GATE_REFCLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + msg-timing = <1>; + addr-timing = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + status = "disabled"; + }; +}; + &i2c { i2c_ic: interrupt-controller@0 { #interrupt-cells = <1>; @@ -1346,6 +1415,11 @@ groups = "SDA2"; }; + pinctrl_sgpm_default: sgpm_default { + function = "SGPM"; + groups = "SGPM"; + }; + pinctrl_sgps1_default: sgps1_default { function = "SGPS1"; groups = "SGPS1"; @@ -1556,3 +1630,134 @@ groups = "WDTRST2"; }; }; + +&vga_scratch { + dac_mux { + offset = <0x2c>; + bit-mask = <0x3>; + bit-shift = <16>; + }; + vga0 { + offset = <0x50>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; + vga1 { + offset = <0x54>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; + vga2 { + offset = <0x58>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; + vga3 { + offset = <0x5c>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; + vga4 { + offset = <0x60>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; + vga5 { + offset = <0x64>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; + vga6 { + offset = <0x68>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; + vga7 { + offset = <0x6c>; + bit-mask = <0xffffffff>; + bit-shift = <0>; + }; +}; + +&sio_regs { + sio_2b { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_2a { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_29 { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_28 { + offset = <0xf0>; + bit-mask = <0xff>; + bit-shift = <0>; + }; + sio_2f { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_2e { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_2d { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_2c { + offset = <0xf4>; + bit-mask = <0xff>; + bit-shift = <0>; + }; + sio_23 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_22 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_21 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_20 { + offset = <0xf8>; + bit-mask = <0xff>; + bit-shift = <0>; + }; + sio_27 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <24>; + }; + sio_26 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <16>; + }; + sio_25 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <8>; + }; + sio_24 { + offset = <0xfc>; + bit-mask = <0xff>; + bit-shift = <0>; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi new file mode 100644 index 000000000000..045ce66ca876 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -0,0 +1,1149 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. + +&pinctrl { + pinctrl_adc0_default: adc0_default { + function = "ADC0"; + groups = "ADC0"; + }; + + pinctrl_adc1_default: adc1_default { + function = "ADC1"; + groups = "ADC1"; + }; + + pinctrl_adc10_default: adc10_default { + function = "ADC10"; + groups = "ADC10"; + }; + + pinctrl_adc11_default: adc11_default { + function = "ADC11"; + groups = "ADC11"; + }; + + pinctrl_adc12_default: adc12_default { + function = "ADC12"; + groups = "ADC12"; + }; + + pinctrl_adc13_default: adc13_default { + function = "ADC13"; + groups = "ADC13"; + }; + + pinctrl_adc14_default: adc14_default { + function = "ADC14"; + groups = "ADC14"; + }; + + pinctrl_adc15_default: adc15_default { + function = "ADC15"; + groups = "ADC15"; + }; + + pinctrl_adc2_default: adc2_default { + function = "ADC2"; + groups = "ADC2"; + }; + + pinctrl_adc3_default: adc3_default { + function = "ADC3"; + groups = "ADC3"; + }; + + pinctrl_adc4_default: adc4_default { + function = "ADC4"; + groups = "ADC4"; + }; + + pinctrl_adc5_default: adc5_default { + function = "ADC5"; + groups = "ADC5"; + }; + + pinctrl_adc6_default: adc6_default { + function = "ADC6"; + groups = "ADC6"; + }; + + pinctrl_adc7_default: adc7_default { + function = "ADC7"; + groups = "ADC7"; + }; + + pinctrl_adc8_default: adc8_default { + function = "ADC8"; + groups = "ADC8"; + }; + + pinctrl_adc9_default: adc9_default { + function = "ADC9"; + groups = "ADC9"; + }; + + pinctrl_bmcint_default: bmcint_default { + function = "BMCINT"; + groups = "BMCINT"; + }; + + pinctrl_espi_default: espi_default { + function = "ESPI"; + groups = "ESPI"; + }; + + pinctrl_espialt_default: espialt_default { + function = "ESPIALT"; + groups = "ESPIALT"; + }; + + pinctrl_fsi1_default: fsi1_default { + function = "FSI1"; + groups = "FSI1"; + }; + + pinctrl_fsi2_default: fsi2_default { + function = "FSI2"; + groups = "FSI2"; + }; + + pinctrl_fwspiabr_default: fwspiabr_default { + function = "FWSPIABR"; + groups = "FWSPIABR"; + }; + + pinctrl_fwspid_default: fwspid_default { + function = "FWSPID"; + groups = "FWSPID"; + }; + + pinctrl_fwqspid_default: fwqspid_default { + function = "FWQSPID"; + groups = "FWQSPID"; + }; + + pinctrl_fwspiwp_default: fwspiwp_default { + function = "FWSPIWP"; + groups = "FWSPIWP"; + }; + + pinctrl_gpit0_default: gpit0_default { + function = "GPIT0"; + groups = "GPIT0"; + }; + + pinctrl_gpit1_default: gpit1_default { + function = "GPIT1"; + groups = "GPIT1"; + }; + + pinctrl_gpit2_default: gpit2_default { + function = "GPIT2"; + groups = "GPIT2"; + }; + + pinctrl_gpit3_default: gpit3_default { + function = "GPIT3"; + groups = "GPIT3"; + }; + + pinctrl_gpit4_default: gpit4_default { + function = "GPIT4"; + groups = "GPIT4"; + }; + + pinctrl_gpit5_default: gpit5_default { + function = "GPIT5"; + groups = "GPIT5"; + }; + + pinctrl_gpit6_default: gpit6_default { + function = "GPIT6"; + groups = "GPIT6"; + }; + + pinctrl_gpit7_default: gpit7_default { + function = "GPIT7"; + groups = "GPIT7"; + }; + + pinctrl_gpiu0_default: gpiu0_default { + function = "GPIU0"; + groups = "GPIU0"; + }; + + pinctrl_gpiu1_default: gpiu1_default { + function = "GPIU1"; + groups = "GPIU1"; + }; + + pinctrl_gpiu2_default: gpiu2_default { + function = "GPIU2"; + groups = "GPIU2"; + }; + + pinctrl_gpiu3_default: gpiu3_default { + function = "GPIU3"; + groups = "GPIU3"; + }; + + pinctrl_gpiu4_default: gpiu4_default { + function = "GPIU4"; + groups = "GPIU4"; + }; + + pinctrl_gpiu5_default: gpiu5_default { + function = "GPIU5"; + groups = "GPIU5"; + }; + + pinctrl_gpiu6_default: gpiu6_default { + function = "GPIU6"; + groups = "GPIU6"; + }; + + pinctrl_gpiu7_default: gpiu7_default { + function = "GPIU7"; + groups = "GPIU7"; + }; + + pinctrl_hvi3c3_default: hvi3c3_default { + function = "HVI3C3"; + groups = "HVI3C3"; + }; + + pinctrl_hvi3c4_default: hvi3c4_default { + function = "HVI3C4"; + groups = "HVI3C4"; + }; + + pinctrl_i2c1_default: i2c1_default { + function = "I2C1"; + groups = "I2C1"; + }; + + pinctrl_i2c10_default: i2c10_default { + function = "I2C10"; + groups = "I2C10"; + }; + + pinctrl_i2c11_default: i2c11_default { + function = "I2C11"; + groups = "I2C11"; + }; + + pinctrl_i2c12_default: i2c12_default { + function = "I2C12"; + groups = "I2C12"; + }; + + pinctrl_i2c13_default: i2c13_default { + function = "I2C13"; + groups = "I2C13"; + }; + + pinctrl_i2c14_default: i2c14_default { + function = "I2C14"; + groups = "I2C14"; + }; + + pinctrl_i2c15_default: i2c15_default { + function = "I2C15"; + groups = "I2C15"; + }; + + pinctrl_i2c16_default: i2c16_default { + function = "I2C16"; + groups = "I2C16"; + }; + + pinctrl_i2c2_default: i2c2_default { + function = "I2C2"; + groups = "I2C2"; + }; + + pinctrl_i2c3_default: i2c3_default { + function = "I2C3"; + groups = "I2C3"; + }; + + pinctrl_i2c4_default: i2c4_default { + function = "I2C4"; + groups = "I2C4"; + }; + + pinctrl_i2c5_default: i2c5_default { + function = "I2C5"; + groups = "I2C5"; + }; + + pinctrl_i2c6_default: i2c6_default { + function = "I2C6"; + groups = "I2C6"; + }; + + pinctrl_i2c7_default: i2c7_default { + function = "I2C7"; + groups = "I2C7"; + }; + + pinctrl_i2c8_default: i2c8_default { + function = "I2C8"; + groups = "I2C8"; + }; + + pinctrl_i2c9_default: i2c9_default { + function = "I2C9"; + groups = "I2C9"; + }; + + pinctrl_i3c3_default: i3c3_default { + function = "I3C3"; + groups = "I3C3"; + }; + + pinctrl_i3c4_default: i3c4_default { + function = "I3C4"; + groups = "I3C4"; + }; + + pinctrl_i3c5_default: i3c5_default { + function = "I3C5"; + groups = "I3C5"; + }; + + pinctrl_i3c6_default: i3c6_default { + function = "I3C6"; + groups = "I3C6"; + }; + + pinctrl_jtagm_default: jtagm_default { + function = "JTAGM"; + groups = "JTAGM"; + }; + + pinctrl_lhpd_default: lhpd_default { + function = "LHPD"; + groups = "LHPD"; + }; + + pinctrl_lhsirq_default: lhsirq_default { + function = "LHSIRQ"; + groups = "LHSIRQ"; + }; + + pinctrl_lpc_default: lpc_default { + function = "LPC"; + groups = "LPC"; + }; + + pinctrl_lpchc_default: lpchc_default { + function = "LPCHC"; + groups = "LPCHC"; + }; + + pinctrl_lpcpd_default: lpcpd_default { + function = "LPCPD"; + groups = "LPCPD"; + }; + + pinctrl_lpcpme_default: lpcpme_default { + function = "LPCPME"; + groups = "LPCPME"; + }; + + pinctrl_lpcsmi_default: lpcsmi_default { + function = "LPCSMI"; + groups = "LPCSMI"; + }; + + pinctrl_lsirq_default: lsirq_default { + function = "LSIRQ"; + groups = "LSIRQ"; + }; + + pinctrl_maclink1_default: maclink1_default { + function = "MACLINK1"; + groups = "MACLINK1"; + }; + + pinctrl_maclink2_default: maclink2_default { + function = "MACLINK2"; + groups = "MACLINK2"; + }; + + pinctrl_maclink3_default: maclink3_default { + function = "MACLINK3"; + groups = "MACLINK3"; + }; + + pinctrl_maclink4_default: maclink4_default { + function = "MACLINK4"; + groups = "MACLINK4"; + }; + + pinctrl_mdio1_default: mdio1_default { + function = "MDIO1"; + groups = "MDIO1"; + }; + + pinctrl_mdio2_default: mdio2_default { + function = "MDIO2"; + groups = "MDIO2"; + }; + + pinctrl_mdio3_default: mdio3_default { + function = "MDIO3"; + groups = "MDIO3"; + }; + + pinctrl_mdio4_default: mdio4_default { + function = "MDIO4"; + groups = "MDIO4"; + }; + + pinctrl_ncts1_default: ncts1_default { + function = "NCTS1"; + groups = "NCTS1"; + }; + + pinctrl_ncts2_default: ncts2_default { + function = "NCTS2"; + groups = "NCTS2"; + }; + + pinctrl_ncts3_default: ncts3_default { + function = "NCTS3"; + groups = "NCTS3"; + }; + + pinctrl_ncts4_default: ncts4_default { + function = "NCTS4"; + groups = "NCTS4"; + }; + + pinctrl_ndcd1_default: ndcd1_default { + function = "NDCD1"; + groups = "NDCD1"; + }; + + pinctrl_ndcd2_default: ndcd2_default { + function = "NDCD2"; + groups = "NDCD2"; + }; + + pinctrl_ndcd3_default: ndcd3_default { + function = "NDCD3"; + groups = "NDCD3"; + }; + + pinctrl_ndcd4_default: ndcd4_default { + function = "NDCD4"; + groups = "NDCD4"; + }; + + pinctrl_ndsr1_default: ndsr1_default { + function = "NDSR1"; + groups = "NDSR1"; + }; + + pinctrl_ndsr2_default: ndsr2_default { + function = "NDSR2"; + groups = "NDSR2"; + }; + + pinctrl_ndsr3_default: ndsr3_default { + function = "NDSR3"; + groups = "NDSR3"; + }; + + pinctrl_ndsr4_default: ndsr4_default { + function = "NDSR4"; + groups = "NDSR4"; + }; + + pinctrl_ndtr1_default: ndtr1_default { + function = "NDTR1"; + groups = "NDTR1"; + }; + + pinctrl_ndtr2_default: ndtr2_default { + function = "NDTR2"; + groups = "NDTR2"; + }; + + pinctrl_ndtr3_default: ndtr3_default { + function = "NDTR3"; + groups = "NDTR3"; + }; + + pinctrl_ndtr4_default: ndtr4_default { + function = "NDTR4"; + groups = "NDTR4"; + }; + + pinctrl_nri1_default: nri1_default { + function = "NRI1"; + groups = "NRI1"; + }; + + pinctrl_nri2_default: nri2_default { + function = "NRI2"; + groups = "NRI2"; + }; + + pinctrl_nri3_default: nri3_default { + function = "NRI3"; + groups = "NRI3"; + }; + + pinctrl_nri4_default: nri4_default { + function = "NRI4"; + groups = "NRI4"; + }; + + pinctrl_nrts1_default: nrts1_default { + function = "NRTS1"; + groups = "NRTS1"; + }; + + pinctrl_nrts2_default: nrts2_default { + function = "NRTS2"; + groups = "NRTS2"; + }; + + pinctrl_nrts3_default: nrts3_default { + function = "NRTS3"; + groups = "NRTS3"; + }; + + pinctrl_nrts4_default: nrts4_default { + function = "NRTS4"; + groups = "NRTS4"; + }; + + pinctrl_oscclk_default: oscclk_default { + function = "OSCCLK"; + groups = "OSCCLK"; + }; + + pinctrl_pewake_default: pewake_default { + function = "PEWAKE"; + groups = "PEWAKE"; + }; + + pinctrl_pwm0_default: pwm0_default { + function = "PWM0"; + groups = "PWM0"; + }; + + pinctrl_pwm1_default: pwm1_default { + function = "PWM1"; + groups = "PWM1"; + }; + + pinctrl_pwm10g0_default: pwm10g0_default { + function = "PWM10"; + groups = "PWM10G0"; + }; + + pinctrl_pwm10g1_default: pwm10g1_default { + function = "PWM10"; + groups = "PWM10G1"; + }; + + pinctrl_pwm11g0_default: pwm11g0_default { + function = "PWM11"; + groups = "PWM11G0"; + }; + + pinctrl_pwm11g1_default: pwm11g1_default { + function = "PWM11"; + groups = "PWM11G1"; + }; + + pinctrl_pwm12g0_default: pwm12g0_default { + function = "PWM12"; + groups = "PWM12G0"; + }; + + pinctrl_pwm12g1_default: pwm12g1_default { + function = "PWM12"; + groups = "PWM12G1"; + }; + + pinctrl_pwm13g0_default: pwm13g0_default { + function = "PWM13"; + groups = "PWM13G0"; + }; + + pinctrl_pwm13g1_default: pwm13g1_default { + function = "PWM13"; + groups = "PWM13G1"; + }; + + pinctrl_pwm14g0_default: pwm14g0_default { + function = "PWM14"; + groups = "PWM14G0"; + }; + + pinctrl_pwm14g1_default: pwm14g1_default { + function = "PWM14"; + groups = "PWM14G1"; + }; + + pinctrl_pwm15g0_default: pwm15g0_default { + function = "PWM15"; + groups = "PWM15G0"; + }; + + pinctrl_pwm15g1_default: pwm15g1_default { + function = "PWM15"; + groups = "PWM15G1"; + }; + + pinctrl_pwm2_default: pwm2_default { + function = "PWM2"; + groups = "PWM2"; + }; + + pinctrl_pwm3_default: pwm3_default { + function = "PWM3"; + groups = "PWM3"; + }; + + pinctrl_pwm4_default: pwm4_default { + function = "PWM4"; + groups = "PWM4"; + }; + + pinctrl_pwm5_default: pwm5_default { + function = "PWM5"; + groups = "PWM5"; + }; + + pinctrl_pwm6_default: pwm6_default { + function = "PWM6"; + groups = "PWM6"; + }; + + pinctrl_pwm7_default: pwm7_default { + function = "PWM7"; + groups = "PWM7"; + }; + + pinctrl_pwm8g0_default: pwm8g0_default { + function = "PWM8"; + groups = "PWM8G0"; + }; + + pinctrl_pwm8g1_default: pwm8g1_default { + function = "PWM8"; + groups = "PWM8G1"; + }; + + pinctrl_pwm9g0_default: pwm9g0_default { + function = "PWM9"; + groups = "PWM9G0"; + }; + + pinctrl_pwm9g1_default: pwm9g1_default { + function = "PWM9"; + groups = "PWM9G1"; + }; + + pinctrl_qspi1_default: qspi1_default { + function = "QSPI1"; + groups = "QSPI1"; + }; + + pinctrl_qspi2_default: qspi2_default { + function = "QSPI2"; + groups = "QSPI2"; + }; + + pinctrl_rgmii1_default: rgmii1_default { + function = "RGMII1"; + groups = "RGMII1"; + }; + + pinctrl_rgmii2_default: rgmii2_default { + function = "RGMII2"; + groups = "RGMII2"; + }; + + pinctrl_rgmii3_default: rgmii3_default { + function = "RGMII3"; + groups = "RGMII3"; + }; + + pinctrl_rgmii4_default: rgmii4_default { + function = "RGMII4"; + groups = "RGMII4"; + }; + + pinctrl_rmii1_default: rmii1_default { + function = "RMII1"; + groups = "RMII1"; + }; + + pinctrl_rmii2_default: rmii2_default { + function = "RMII2"; + groups = "RMII2"; + }; + + pinctrl_rmii3_default: rmii3_default { + function = "RMII3"; + groups = "RMII3"; + }; + + pinctrl_rmii4_default: rmii4_default { + function = "RMII4"; + groups = "RMII4"; + }; + + pinctrl_rxd1_default: rxd1_default { + function = "RXD1"; + groups = "RXD1"; + }; + + pinctrl_rxd2_default: rxd2_default { + function = "RXD2"; + groups = "RXD2"; + }; + + pinctrl_rxd3_default: rxd3_default { + function = "RXD3"; + groups = "RXD3"; + }; + + pinctrl_rxd4_default: rxd4_default { + function = "RXD4"; + groups = "RXD4"; + }; + + pinctrl_salt1_default: salt1_default { + function = "SALT1"; + groups = "SALT1"; + }; + + pinctrl_salt10g0_default: salt10g0_default { + function = "SALT10"; + groups = "SALT10G0"; + }; + + pinctrl_salt10g1_default: salt10g1_default { + function = "SALT10"; + groups = "SALT10G1"; + }; + + pinctrl_salt11g0_default: salt11g0_default { + function = "SALT11"; + groups = "SALT11G0"; + }; + + pinctrl_salt11g1_default: salt11g1_default { + function = "SALT11"; + groups = "SALT11G1"; + }; + + pinctrl_salt12g0_default: salt12g0_default { + function = "SALT12"; + groups = "SALT12G0"; + }; + + pinctrl_salt12g1_default: salt12g1_default { + function = "SALT12"; + groups = "SALT12G1"; + }; + + pinctrl_salt13g0_default: salt13g0_default { + function = "SALT13"; + groups = "SALT13G0"; + }; + + pinctrl_salt13g1_default: salt13g1_default { + function = "SALT13"; + groups = "SALT13G1"; + }; + + pinctrl_salt14g0_default: salt14g0_default { + function = "SALT14"; + groups = "SALT14G0"; + }; + + pinctrl_salt14g1_default: salt14g1_default { + function = "SALT14"; + groups = "SALT14G1"; + }; + + pinctrl_salt15g0_default: salt15g0_default { + function = "SALT15"; + groups = "SALT15G0"; + }; + + pinctrl_salt15g1_default: salt15g1_default { + function = "SALT15"; + groups = "SALT15G1"; + }; + + pinctrl_salt16g0_default: salt16g0_default { + function = "SALT16"; + groups = "SALT16G0"; + }; + + pinctrl_salt16g1_default: salt16g1_default { + function = "SALT16"; + groups = "SALT16G1"; + }; + + pinctrl_salt2_default: salt2_default { + function = "SALT2"; + groups = "SALT2"; + }; + + pinctrl_salt3_default: salt3_default { + function = "SALT3"; + groups = "SALT3"; + }; + + pinctrl_salt4_default: salt4_default { + function = "SALT4"; + groups = "SALT4"; + }; + + pinctrl_salt5_default: salt5_default { + function = "SALT5"; + groups = "SALT5"; + }; + + pinctrl_salt6_default: salt6_default { + function = "SALT6"; + groups = "SALT6"; + }; + + pinctrl_salt7_default: salt7_default { + function = "SALT7"; + groups = "SALT7"; + }; + + pinctrl_salt8_default: salt8_default { + function = "SALT8"; + groups = "SALT8"; + }; + + pinctrl_salt9g0_default: salt9g0_default { + function = "SALT9"; + groups = "SALT9G0"; + }; + + pinctrl_salt9g1_default: salt9g1_default { + function = "SALT9"; + groups = "SALT9G1"; + }; + + pinctrl_sd1_default: sd1_default { + function = "SD1"; + groups = "SD1"; + }; + + pinctrl_sd2_default: sd2_default { + function = "SD2"; + groups = "SD2"; + }; + + pinctrl_emmc_default: emmc_default { + function = "EMMC"; + groups = "EMMCG4"; + }; + + pinctrl_sgpm1_default: sgpm1_default { + function = "SGPM1"; + groups = "SGPM1"; + }; + + pinctrl_sgps1_default: sgps1_default { + function = "SGPS1"; + groups = "SGPS1"; + }; + + pinctrl_sioonctrl_default: sioonctrl_default { + function = "SIOONCTRL"; + groups = "SIOONCTRL"; + }; + + pinctrl_siopbi_default: siopbi_default { + function = "SIOPBI"; + groups = "SIOPBI"; + }; + + pinctrl_siopbo_default: siopbo_default { + function = "SIOPBO"; + groups = "SIOPBO"; + }; + + pinctrl_siopwreq_default: siopwreq_default { + function = "SIOPWREQ"; + groups = "SIOPWREQ"; + }; + + pinctrl_siopwrgd_default: siopwrgd_default { + function = "SIOPWRGD"; + groups = "SIOPWRGD"; + }; + + pinctrl_sios3_default: sios3_default { + function = "SIOS3"; + groups = "SIOS3"; + }; + + pinctrl_sios5_default: sios5_default { + function = "SIOS5"; + groups = "SIOS5"; + }; + + pinctrl_siosci_default: siosci_default { + function = "SIOSCI"; + groups = "SIOSCI"; + }; + + pinctrl_spi1_default: spi1_default { + function = "SPI1"; + groups = "SPI1"; + }; + + pinctrl_spi1abr_default: spi1abr_default { + function = "SPI1ABR"; + groups = "SPI1ABR"; + }; + + pinctrl_spi1cs1_default: spi1cs1_default { + function = "SPI1CS1"; + groups = "SPI1CS1"; + }; + + pinctrl_spi1wp_default: spi1wp_default { + function = "SPI1WP"; + groups = "SPI1WP"; + }; + + pinctrl_spi2_default: spi2_default { + function = "SPI2"; + groups = "SPI2"; + }; + + pinctrl_spi2cs1_default: spi2cs1_default { + function = "SPI2CS1"; + groups = "SPI2CS1"; + }; + + pinctrl_spi2cs2_default: spi2cs2_default { + function = "SPI2CS2"; + groups = "SPI2CS2"; + }; + + pinctrl_tach0_default: tach0_default { + function = "TACH0"; + groups = "TACH0"; + }; + + pinctrl_tach1_default: tach1_default { + function = "TACH1"; + groups = "TACH1"; + }; + + pinctrl_tach10_default: tach10_default { + function = "TACH10"; + groups = "TACH10"; + }; + + pinctrl_tach11_default: tach11_default { + function = "TACH11"; + groups = "TACH11"; + }; + + pinctrl_tach12_default: tach12_default { + function = "TACH12"; + groups = "TACH12"; + }; + + pinctrl_tach13_default: tach13_default { + function = "TACH13"; + groups = "TACH13"; + }; + + pinctrl_tach14_default: tach14_default { + function = "TACH14"; + groups = "TACH14"; + }; + + pinctrl_tach15_default: tach15_default { + function = "TACH15"; + groups = "TACH15"; + }; + + pinctrl_tach2_default: tach2_default { + function = "TACH2"; + groups = "TACH2"; + }; + + pinctrl_tach3_default: tach3_default { + function = "TACH3"; + groups = "TACH3"; + }; + + pinctrl_tach4_default: tach4_default { + function = "TACH4"; + groups = "TACH4"; + }; + + pinctrl_tach5_default: tach5_default { + function = "TACH5"; + groups = "TACH5"; + }; + + pinctrl_tach6_default: tach6_default { + function = "TACH6"; + groups = "TACH6"; + }; + + pinctrl_tach7_default: tach7_default { + function = "TACH7"; + groups = "TACH7"; + }; + + pinctrl_tach8_default: tach8_default { + function = "TACH8"; + groups = "TACH8"; + }; + + pinctrl_tach9_default: tach9_default { + function = "TACH9"; + groups = "TACH9"; + }; + + pinctrl_thru0_default: thru0_default { + function = "THRU0"; + groups = "THRU0"; + }; + + pinctrl_thru1_default: thru1_default { + function = "THRU1"; + groups = "THRU1"; + }; + + pinctrl_thru2_default: thru2_default { + function = "THRU2"; + groups = "THRU2"; + }; + + pinctrl_thru3_default: thru3_default { + function = "THRU3"; + groups = "THRU3"; + }; + + pinctrl_txd1_default: txd1_default { + function = "TXD1"; + groups = "TXD1"; + }; + + pinctrl_txd2_default: txd2_default { + function = "TXD2"; + groups = "TXD2"; + }; + + pinctrl_txd3_default: txd3_default { + function = "TXD3"; + groups = "TXD3"; + }; + + pinctrl_txd4_default: txd4_default { + function = "TXD4"; + groups = "TXD4"; + }; + + pinctrl_uart10_default: uart10_default { + function = "UART10"; + groups = "UART10"; + }; + + pinctrl_uart11_default: uart11_default { + function = "UART11"; + groups = "UART11"; + }; + + pinctrl_uart12g0_default: uart12g0_default { + function = "UART12"; + groups = "UART12G0"; + }; + + pinctrl_uart12g1_default: uart12g1_default { + function = "UART12"; + groups = "UART12G1"; + }; + + pinctrl_uart13g0_default: uart13g0_default { + function = "UART13"; + groups = "UART13G0"; + }; + + pinctrl_uart13g1_default: uart13g1_default { + function = "UART13"; + groups = "UART13G1"; + }; + + pinctrl_uart6_default: uart6_default { + function = "UART6"; + groups = "UART6"; + }; + + pinctrl_uart7_default: uart7_default { + function = "UART7"; + groups = "UART7"; + }; + + pinctrl_uart8_default: uart8_default { + function = "UART8"; + groups = "UART8"; + }; + + pinctrl_uart9_default: uart9_default { + function = "UART9"; + groups = "UART9"; + }; + + pinctrl_vb_default: vb_default { + function = "VB"; + groups = "VB"; + }; + + pinctrl_vgahs_default: vgahs_default { + function = "VGAHS"; + groups = "VGAHS"; + }; + + pinctrl_vgavs_default: vgavs_default { + function = "VGAVS"; + groups = "VGAVS"; + }; + + pinctrl_wdtrst1_default: wdtrst1_default { + function = "WDTRST1"; + groups = "WDTRST1"; + }; + + pinctrl_wdtrst2_default: wdtrst2_default { + function = "WDTRST2"; + groups = "WDTRST2"; + }; + + pinctrl_wdtrst3_default: wdtrst3_default { + function = "WDTRST3"; + groups = "WDTRST3"; + }; + + pinctrl_wdtrst4_default: wdtrst4_default { + function = "WDTRST4"; + groups = "WDTRST4"; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi new file mode 100644 index 000000000000..e574254f298d --- /dev/null +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -0,0 +1,847 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2019 IBM Corp. + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/ast2600-clock.h> + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2600"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &vuart1; + serial6 = &vuart2; + }; + + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "aspeed,ast2600-smp"; + + cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + }; + + cpu@f01 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + clocks = <&syscon ASPEED_CLK_HPLL>; + arm,cpu-registers-not-fw-configured; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + ranges; + + gic: interrupt-controller@40461000 { + compatible = "arm,cortex-a7-gic"; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&gic>; + reg = <0x40461000 0x1000>, + <0x40462000 0x1000>, + <0x40464000 0x2000>, + <0x40466000 0x2000>; + }; + + fmc: spi@1e620000 { + reg = < 0x1e620000 0xc4 + 0x20000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-fmc"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + spi1: spi@1e630000 { + reg = < 0x1e630000 0xc4 + 0x30000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + spi2: spi@1e631000 { + reg = < 0x1e631000 0xc4 + 0x50000000 0x10000000 >; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2600-spi"; + clocks = <&syscon ASPEED_CLK_AHB>; + status = "disabled"; + flash@0 { + reg = < 0 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@1 { + reg = < 1 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + flash@2 { + reg = < 2 >; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + }; + + mdio0: mdio@1e650000 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650000 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1_default>; + }; + + mdio1: mdio@1e650008 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650008 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio2_default>; + }; + + mdio2: mdio@1e650010 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650010 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio3_default>; + }; + + mdio3: mdio@1e650018 { + compatible = "aspeed,ast2600-mdio"; + reg = <0x1e650018 0x8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; + }; + + mac0: ftgmac@1e660000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e660000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; + status = "disabled"; + }; + + mac1: ftgmac@1e680000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e680000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; + status = "disabled"; + }; + + mac2: ftgmac@1e670000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e670000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; + status = "disabled"; + }; + + mac3: ftgmac@1e690000 { + compatible = "aspeed,ast2600-mac", "faraday,ftgmac100"; + reg = <0x1e690000 0x180>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + syscon: syscon@1e6e2000 { + compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0x1000>; + ranges = <0 0x1e6e2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + pinctrl: pinctrl { + compatible = "aspeed,ast2600-pinctrl"; + }; + + smp-memram@180 { + compatible = "aspeed,ast2600-smpmem"; + reg = <0x180 0x40>; + }; + }; + + rng: hwrng@1e6e2524 { + compatible = "timeriomem_rng"; + reg = <0x1e6e2524 0x4>; + period = <1>; + quality = <100>; + }; + + gpio0: gpio@1e780000 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780000 0x800>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 0 208>; + ngpios = <208>; + clocks = <&syscon ASPEED_CLK_APB2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@1e780800 { + #gpio-cells = <2>; + gpio-controller; + compatible = "aspeed,ast2600-gpio"; + reg = <0x1e780800 0x800>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 208 36>; + ngpios = <36>; + clocks = <&syscon ASPEED_CLK_APB1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rtc: rtc@1e781000 { + compatible = "aspeed,ast2600-rtc"; + reg = <0x1e781000 0x18>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2600-timer"; + reg = <0x1e782000 0x90>; + interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB1>; + clock-names = "PCLK"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>; + no-loopback-test; + }; + + wdt1: watchdog@1e785000 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785000 0x40>; + }; + + wdt2: watchdog@1e785040 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785040 0x40>; + status = "disabled"; + }; + + wdt3: watchdog@1e785080 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e785080 0x40>; + status = "disabled"; + }; + + wdt4: watchdog@1e7850C0 { + compatible = "aspeed,ast2600-wdt"; + reg = <0x1e7850C0 0x40>; + status = "disabled"; + }; + + lpc: lpc@1e789000 { + compatible = "aspeed,ast2600-lpc", "simple-mfd"; + reg = <0x1e789000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e789000 0x1000>; + + lpc_bmc: lpc-bmc@0 { + compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon"; + reg = <0x0 0x80>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x80>; + + kcs1: kcs1@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + kcs_chan = <1>; + status = "disabled"; + }; + kcs2: kcs2@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + kcs_chan = <2>; + status = "disabled"; + }; + kcs3: kcs3@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + kcs_chan = <3>; + status = "disabled"; + }; + }; + + lpc_host: lpc-host@80 { + compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon"; + reg = <0x80 0x1e0>; + reg-io-width = <4>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x80 0x1e0>; + + kcs4: kcs4@0 { + compatible = "aspeed,ast2600-kcs-bmc"; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + kcs_chan = <4>; + status = "disabled"; + }; + + lpc_ctrl: lpc-ctrl@0 { + compatible = "aspeed,ast2600-lpc-ctrl"; + reg = <0x0 0x80>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; + }; + + lpc_snoop: lpc-snoop@0 { + compatible = "aspeed,ast2600-lpc-snoop"; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + lhc: lhc@20 { + compatible = "aspeed,ast2600-lhc"; + reg = <0x20 0x24 0x48 0x8>; + }; + + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2600-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + + ibt: ibt@c0 { + compatible = "aspeed,ast2600-ibt-bmc"; + reg = <0xc0 0x18>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sio_regs: regs { + compatible = "aspeed,bmc-misc"; + }; + }; + }; + + sdc: sdc@1e740000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e740000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e740000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_SDCLK>; + status = "disabled"; + + sdhci0: sdhci@1e740100 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; + reg = <0x100 0x100>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + + sdhci1: sdhci@1e740200 { + compatible = "aspeed,ast2600-sdhci", "sdhci"; + reg = <0x200 0x100>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + sdhci,auto-cmd12; + clocks = <&syscon ASPEED_CLK_SDIO>; + status = "disabled"; + }; + }; + + emmc_controller: sdc@1e750000 { + compatible = "aspeed,ast2600-sd-controller"; + reg = <0x1e750000 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e750000 0x10000>; + clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>; + status = "disabled"; + + emmc: sdhci@1e750100 { + compatible = "aspeed,ast2600-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_EMMC>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emmc_default>; + }; + }; + + vuart1: serial@1e787000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e787000 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB1>; + no-loopback-test; + status = "disabled"; + }; + + vuart2: serial@1e788000 { + compatible = "aspeed,ast2500-vuart"; + reg = <0x1e788000 0x40>; + reg-shift = <2>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_APB1>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; + no-loopback-test; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>; + status = "disabled"; + }; + + i2c: bus@1e78a000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1e78a000 0x1000>; + }; + + fsim0: fsi@1e79b000 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b000 0x94>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; + + fsim1: fsi@1e79b100 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b100 0x94>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi2_default>; + clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; + }; + }; +}; + +#include "aspeed-g6-pinctrl.dtsi" + +&i2c { + i2c0: i2c-bus@80 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "disabled"; + }; + + i2c1: i2c-bus@100 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x100 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2_default>; + status = "disabled"; + }; + + i2c2: i2c-bus@180 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x180 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_default>; + status = "disabled"; + }; + + i2c3: i2c-bus@200 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x200 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4_default>; + status = "disabled"; + }; + + i2c4: i2c-bus@280 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x280 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c5_default>; + status = "disabled"; + }; + + i2c5: i2c-bus@300 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x300 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c6_default>; + status = "disabled"; + }; + + i2c6: i2c-bus@380 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x380 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c7_default>; + status = "disabled"; + }; + + i2c7: i2c-bus@400 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x400 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c8_default>; + status = "disabled"; + }; + + i2c8: i2c-bus@480 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x480 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c9_default>; + status = "disabled"; + }; + + i2c9: i2c-bus@500 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x500 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "disabled"; + }; + + i2c10: i2c-bus@580 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x580 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c11_default>; + status = "disabled"; + }; + + i2c11: i2c-bus@600 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x600 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c12_default>; + status = "disabled"; + }; + + i2c12: i2c-bus@680 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x680 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c13_default>; + status = "disabled"; + }; + + i2c13: i2c-bus@700 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x700 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c14_default>; + status = "disabled"; + }; + + i2c14: i2c-bus@780 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x780 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c15_default>; + status = "disabled"; + }; + + i2c15: i2c-bus@800 { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + reg = <0x800 0x80>; + compatible = "aspeed,ast2600-i2c-bus"; + clocks = <&syscon ASPEED_CLK_APB2>; + resets = <&syscon ASPEED_RESET_I2C>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; + bus-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c16_default>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi index d2d0761295a4..da02aa70df06 100644 --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi @@ -3,14 +3,21 @@ // Copyright 2018 Google, Inc. #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> +#include <dt-bindings/gpio/gpio.h> / { #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&gic>; + memory { + device_type = "memory"; + reg = <0 0>; + }; + /* external reference clock */ - clk_refclk: clk_refclk { + clk_refclk: clk-refclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; @@ -18,7 +25,7 @@ }; /* external reference clock for cpu. float in normal operation */ - clk_sysbypck: clk_sysbypck { + clk_sysbypck: clk-sysbypck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <800000000>; @@ -26,7 +33,7 @@ }; /* external reference clock for MC. float in normal operation */ - clk_mcbypck: clk_mcbypck { + clk_mcbypck: clk-mcbypck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <800000000>; @@ -34,7 +41,7 @@ }; /* external clock signal rg1refck, supplied by the phy */ - clk_rg1refck: clk_rg1refck { + clk_rg1refck: clk-rg1refck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; @@ -42,14 +49,14 @@ }; /* external clock signal rg2refck, supplied by the phy */ - clk_rg2refck: clk_rg2refck { + clk_rg2refck: clk-rg2refck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <125000000>; clock-output-names = "clk_rg2refck"; }; - clk_xin: clk_xin { + clk_xin: clk-xin { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; @@ -69,6 +76,12 @@ reg = <0x800000 0x1000>; }; + rst: rst@f0801000 { + compatible = "nuvoton,npcm750-rst", "syscon", + "simple-mfd"; + reg = <0x801000 0x6C>; + }; + scu: scu@3fe000 { compatible = "arm,cortex-a9-scu"; reg = <0x3fe000 0x1000>; @@ -80,7 +93,7 @@ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; - clocks = <&clk 10>; + clocks = <&clk NPCM7XX_CLK_AXI>; arm,shared-override; }; @@ -109,6 +122,170 @@ clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>; }; + gmac0: eth@f0802000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0802000 0x2000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + ethernet = <0>; + clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg1_pins + &rg1mdio_pins>; + status = "disabled"; + }; + + emc0: eth@f0825000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0825000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + pinctrl-names = "default"; + pinctrl-0 = <&r1_pins + &r1err_pins + &r1md_pins>; + status = "disabled"; + }; + + ehci1:usb@f0806000 { + compatible = "nuvoton,npcm750-ehci"; + reg = <0xf0806000 0x1000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ohci1: ohci@f0807000 { + compatible = "nuvoton,npcm750-ohci"; + reg = <0xf0807000 0x1000>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhci0: sdhci@f0842000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0842000 0x200>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_mmc"; /* ,"clk_xin"; */ + pinctrl-names = "default"; + pinctrl-0 = <&mmc8_pins + &mmc_pins>; + }; + + sdhci1: sdhci@f0840000 { + compatible = "nuvoton,npcm750-sdhci"; + status = "disabled"; + reg = <0xf0840000 0x200>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_AHB>; /*, <&clk_xin>;*/ + clock-names = "clk_sdhc"; /* ,"clk_xin"; */ + pinctrl-names = "default"; + pinctrl-0 = <&sd1_pins>; + }; + + aes:aes@f0858000 { + compatible = "nuvoton,npcm750-aes"; + reg = <0xf0858000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + sha:sha@f085a000 { + compatible = "nuvoton,npcm750-sha"; + reg = <0xf085a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + copr: copr@0 { + compatible = "nuvoton,npcm750-copr"; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + }; + + vdma: vdma@e0800000 { + compatible = "nuvoton,npcm750-vdm"; + reg = <0xe0800000 0x1000 + 0xf0822000 0x1000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + }; + + fiu0: fiu@fb000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + status = "disabled"; + }; + + fiu3: fiu@c0000000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc0000000 0x1000>, <0xA0000000 0x20000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_pins>; + status = "disabled"; + }; + + fiux: fiu@fb001000 { + compatible = "nuvoton,npcm750-fiu"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfb001000 0x1000>, <0xf8000000 0x2000000>; + reg-names = "control", "memory"; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_ahb"; + status = "disabled"; + }; + + dvc: dvc@f0808000 { + compatible = "nuvoton,npcm750-dvc"; + reg = <0xf0808000 0x1000>; + interrupts = <0 23 4>; + }; + + vcd: vcd@f0810000 { + compatible = "nuvoton,npcm750-vcd"; + reg = <0xf0810000 0x10000>; + mem-addr = <0x3e200000>; + mem-size = <0x600000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ece: ece@f0820000 { + compatible = "nuvoton,npcm750-ece"; + reg = <0xf0820000 0x2000>; + mem-addr = <0x3e800000>; + mem-size = <0x600000>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pcimbox: pcimbox@f0848000 { + compatible = "nuvoton,npcm750-pci-mbox", + "simple-mfd", "syscon"; + reg = <0xf084C000 0x8 + 0xf0848000 0x3F00>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + }; + apb { #address-cells = <1>; #size-cells = <1>; @@ -116,11 +293,99 @@ interrupt-parent = <&gic>; ranges = <0x0 0xf0000000 0x00300000>; + lpc_kcs: lpc_kcs@7000 { + compatible = "nuvoton,npcm750-lpc-kcs", + "simple-mfd", "syscon"; + reg = <0x7000 0x40>; + reg-io-width = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x40>; + + kcs1: kcs1@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + kcs_chan = <1>; + status = "disabled"; + }; + + kcs2: kcs2@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + kcs_chan = <2>; + status = "disabled"; + }; + + kcs3: kcs3@0 { + compatible = "nuvoton,npcm750-kcs-bmc"; + reg = <0x0 0x40>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + kcs_chan = <3>; + status = "disabled"; + }; + }; + + lpc_host: lpc_host@7000 { + compatible = "nuvoton,npcm750-lpc-host", + "simple-mfd", "syscon"; + reg = <0x7000 0x60>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x7000 0x60>; + + lpc_bpc: lpc_bpc@40 { + compatible = "nuvoton,npcm750-lpc-bpc"; + reg = <0x40 0x20>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + + peci: peci-bus@100000 { + compatible = "nuvoton,npcm750-peci"; + reg = <0x100000 0x200>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_APB3>; + status = "disabled"; + }; + + spi0: spi@200000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x200000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi1_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + status = "disabled"; + }; + + spi1: spi@201000 { + compatible = "nuvoton,npcm750-pspi"; + reg = <0x201000 0x1000>; + pinctrl-names = "default"; + pinctrl-0 = <&pspi2_pins>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_APB5>; + clock-names = "clk_apb5"; + status = "disabled"; + }; + timer0: timer@8000 { compatible = "nuvoton,npcm750-timer"; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x8000 0x50>; - clocks = <&clk 5>; + reg = <0x8000 0x1C>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog0: watchdog@801C { @@ -128,7 +393,7 @@ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; reg = <0x801C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog1: watchdog@901C { @@ -136,7 +401,7 @@ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; reg = <0x901C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; watchdog2: watchdog@a01C { @@ -144,13 +409,13 @@ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; reg = <0xa01C 0x4>; status = "disabled"; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_TIMER>; }; serial0: serial@1000 { compatible = "nuvoton,npcm750-uart"; reg = <0x1000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; status = "disabled"; @@ -159,7 +424,7 @@ serial1: serial@2000 { compatible = "nuvoton,npcm750-uart"; reg = <0x2000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; status = "disabled"; @@ -168,7 +433,7 @@ serial2: serial@3000 { compatible = "nuvoton,npcm750-uart"; reg = <0x3000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; status = "disabled"; @@ -177,11 +442,818 @@ serial3: serial@4000 { compatible = "nuvoton,npcm750-uart"; reg = <0x4000 0x1000>; - clocks = <&clk 6>; + clocks = <&clk NPCM7XX_CLK_UART>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; reg-shift = <2>; status = "disabled"; }; + + rng: rng@b000 { + compatible = "nuvoton,npcm750-rng"; + reg = <0xb000 0x1000>; + clocks = <&clk NPCM7XX_CLK_APB1>; + clock-names = "clk_apb1"; + status = "disabled"; + }; + + adc: adc@c000 { + compatible = "nuvoton,npcm750-adc"; + reg = <0xc000 0x8>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_ADC>; + status = "disabled"; + }; + + otp:otp@189000 { + compatible = "nuvoton,npcm750-otp"; + reg = <0x189000 0x1000 + 0x18a000 0x1000>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_APB4>; + clock-names = "clk_apb4"; + }; + + pwm_fan:pwm-fan-controller@103000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nuvoton,npcm750-pwm-fan"; + reg = <0x103000 0x2000>, + <0x180000 0x8000>; + reg-names = "pwm", "fan"; + clocks = <&clk NPCM7XX_CLK_APB3>, + <&clk NPCM7XX_CLK_APB4>; + clock-names = "pwm","fan"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins + &pwm2_pins &pwm3_pins + &pwm4_pins &pwm5_pins + &pwm6_pins &pwm7_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins + &fanin12_pins &fanin13_pins + &fanin14_pins &fanin15_pins>; + status = "disabled"; + }; + + i2c0: i2c@80000 { + reg = <0x80000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb0_pins>; + status = "disabled"; + }; + + i2c1: i2c@81000 { + reg = <0x81000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb1_pins>; + status = "disabled"; + }; + + i2c2: i2c@82000 { + reg = <0x82000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb2_pins>; + status = "disabled"; + }; + + i2c3: i2c@83000 { + reg = <0x83000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb3_pins>; + status = "disabled"; + }; + + i2c4: i2c@84000 { + reg = <0x84000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb4_pins>; + status = "disabled"; + }; + + i2c5: i2c@85000 { + reg = <0x85000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb5_pins>; + status = "disabled"; + }; + + i2c6: i2c@86000 { + reg = <0x86000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb6_pins>; + status = "disabled"; + }; + + i2c7: i2c@87000 { + reg = <0x87000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb7_pins>; + status = "disabled"; + }; + + i2c8: i2c@88000 { + reg = <0x88000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb8_pins>; + status = "disabled"; + }; + + i2c9: i2c@89000 { + reg = <0x89000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb9_pins>; + status = "disabled"; + }; + + i2c10: i2c@8a000 { + reg = <0x8a000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb10_pins>; + status = "disabled"; + }; + + i2c11: i2c@8b000 { + reg = <0x8b000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb11_pins>; + status = "disabled"; + }; + + i2c12: i2c@8c000 { + reg = <0x8c000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb12_pins>; + status = "disabled"; + }; + + i2c13: i2c@8d000 { + reg = <0x8d000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb13_pins>; + status = "disabled"; + }; + + i2c14: i2c@8e000 { + reg = <0x8e000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb14_pins>; + status = "disabled"; + }; + + i2c15: i2c@8f000 { + reg = <0x8f000 0x1000>; + compatible = "nuvoton,npcm750-i2c"; + clocks = <&clk NPCM7XX_CLK_APB2>; + bus-frequency = <100000>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&smb15_pins>; + status = "disabled"; + }; + + gfxi: gfxi@f000e000 { + compatible = "nuvoton,npcm750-gfxi", "syscon", + "simple-mfd"; + reg = <0xf000e000 0x100>; + }; + + }; + }; + + pinctrl: pinctrl@f0800000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd"; + ranges = <0 0xf0010000 0x8000>; + status = "okay"; + gpio0: gpio@f0010000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x80>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + gpio1: gpio@f0011000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x1000 0x80>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 32 32>; + }; + gpio2: gpio@f0012000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x2000 0x80>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 64 32>; + }; + gpio3: gpio@f0013000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x3000 0x80>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 96 32>; + }; + gpio4: gpio@f0014000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x4000 0x80>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 128 32>; + }; + gpio5: gpio@f0015000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x5000 0x80>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 160 32>; + }; + gpio6: gpio@f0016000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x6000 0x80>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 192 32>; + }; + gpio7: gpio@f0017000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x7000 0x80>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + gpio-ranges = <&pinctrl 0 224 32>; + }; + + iox1_pins: iox1-pins { + groups = "iox1"; + function = "iox1"; + }; + iox2_pins: iox2-pins { + groups = "iox2"; + function = "iox2"; + }; + smb1d_pins: smb1d-pins { + groups = "smb1d"; + function = "smb1d"; + }; + smb2d_pins: smb2d-pins { + groups = "smb2d"; + function = "smb2d"; + }; + lkgpo1_pins: lkgpo1-pins { + groups = "lkgpo1"; + function = "lkgpo1"; + }; + lkgpo2_pins: lkgpo2-pins { + groups = "lkgpo2"; + function = "lkgpo2"; + }; + ioxh_pins: ioxh-pins { + groups = "ioxh"; + function = "ioxh"; + }; + gspi_pins: gspi-pins { + groups = "gspi"; + function = "gspi"; + }; + smb5b_pins: smb5b-pins { + groups = "smb5b"; + function = "smb5b"; + }; + smb5c_pins: smb5c-pins { + groups = "smb5c"; + function = "smb5c"; + }; + lkgpo0_pins: lkgpo0-pins { + groups = "lkgpo0"; + function = "lkgpo0"; + }; + pspi2_pins: pspi2-pins { + groups = "pspi2"; + function = "pspi2"; + }; + smb4den_pins: smb4den-pins { + groups = "smb4den"; + function = "smb4den"; + }; + smb4b_pins: smb4b-pins { + groups = "smb4b"; + function = "smb4b"; + }; + smb4c_pins: smb4c-pins { + groups = "smb4c"; + function = "smb4c"; + }; + smb15_pins: smb15-pins { + groups = "smb15"; + function = "smb15"; + }; + smb4d_pins: smb4d-pins { + groups = "smb4d"; + function = "smb4d"; + }; + smb14_pins: smb14-pins { + groups = "smb14"; + function = "smb14"; + }; + smb5_pins: smb5-pins { + groups = "smb5"; + function = "smb5"; + }; + smb4_pins: smb4-pins { + groups = "smb4"; + function = "smb4"; + }; + smb3_pins: smb3-pins { + groups = "smb3"; + function = "smb3"; + }; + spi0cs1_pins: spi0cs1-pins { + groups = "spi0cs1"; + function = "spi0cs1"; + }; + spi0cs2_pins: spi0cs2-pins { + groups = "spi0cs2"; + function = "spi0cs2"; + }; + spi0cs3_pins: spi0cs3-pins { + groups = "spi0cs3"; + function = "spi0cs3"; + }; + smb3c_pins: smb3c-pins { + groups = "smb3c"; + function = "smb3c"; + }; + smb3b_pins: smb3b-pins { + groups = "smb3b"; + function = "smb3b"; + }; + bmcuart0a_pins: bmcuart0a-pins { + groups = "bmcuart0a"; + function = "bmcuart0a"; + }; + uart1_pins: uart1-pins { + groups = "uart1"; + function = "uart1"; + }; + jtag2_pins: jtag2-pins { + groups = "jtag2"; + function = "jtag2"; + }; + bmcuart1_pins: bmcuart1-pins { + groups = "bmcuart1"; + function = "bmcuart1"; + }; + uart2_pins: uart2-pins { + groups = "uart2"; + function = "uart2"; + }; + bmcuart0b_pins: bmcuart0b-pins { + groups = "bmcuart0b"; + function = "bmcuart0b"; + }; + r1err_pins: r1err-pins { + groups = "r1err"; + function = "r1err"; + }; + r1md_pins: r1md-pins { + groups = "r1md"; + function = "r1md"; + }; + smb3d_pins: smb3d-pins { + groups = "smb3d"; + function = "smb3d"; + }; + fanin0_pins: fanin0-pins { + groups = "fanin0"; + function = "fanin0"; + }; + fanin1_pins: fanin1-pins { + groups = "fanin1"; + function = "fanin1"; + }; + fanin2_pins: fanin2-pins { + groups = "fanin2"; + function = "fanin2"; + }; + fanin3_pins: fanin3-pins { + groups = "fanin3"; + function = "fanin3"; + }; + fanin4_pins: fanin4-pins { + groups = "fanin4"; + function = "fanin4"; + }; + fanin5_pins: fanin5-pins { + groups = "fanin5"; + function = "fanin5"; + }; + fanin6_pins: fanin6-pins { + groups = "fanin6"; + function = "fanin6"; + }; + fanin7_pins: fanin7-pins { + groups = "fanin7"; + function = "fanin7"; + }; + fanin8_pins: fanin8-pins { + groups = "fanin8"; + function = "fanin8"; + }; + fanin9_pins: fanin9-pins { + groups = "fanin9"; + function = "fanin9"; + }; + fanin10_pins: fanin10-pins { + groups = "fanin10"; + function = "fanin10"; + }; + fanin11_pins: fanin11-pins { + groups = "fanin11"; + function = "fanin11"; + }; + fanin12_pins: fanin12-pins { + groups = "fanin12"; + function = "fanin12"; + }; + fanin13_pins: fanin13-pins { + groups = "fanin13"; + function = "fanin13"; + }; + fanin14_pins: fanin14-pins { + groups = "fanin14"; + function = "fanin14"; + }; + fanin15_pins: fanin15-pins { + groups = "fanin15"; + function = "fanin15"; + }; + pwm0_pins: pwm0-pins { + groups = "pwm0"; + function = "pwm0"; + }; + pwm1_pins: pwm1-pins { + groups = "pwm1"; + function = "pwm1"; + }; + pwm2_pins: pwm2-pins { + groups = "pwm2"; + function = "pwm2"; + }; + pwm3_pins: pwm3-pins { + groups = "pwm3"; + function = "pwm3"; + }; + r2_pins: r2-pins { + groups = "r2"; + function = "r2"; + }; + r2err_pins: r2err-pins { + groups = "r2err"; + function = "r2err"; + }; + r2md_pins: r2md-pins { + groups = "r2md"; + function = "r2md"; + }; + ga20kbc_pins: ga20kbc-pins { + groups = "ga20kbc"; + function = "ga20kbc"; + }; + smb5d_pins: smb5d-pins { + groups = "smb5d"; + function = "smb5d"; + }; + lpc_pins: lpc-pins { + groups = "lpc"; + function = "lpc"; + }; + espi_pins: espi-pins { + groups = "espi"; + function = "espi"; + }; + rg1_pins: rg1-pins { + groups = "rg1"; + function = "rg1"; + }; + rg1mdio_pins: rg1mdio-pins { + groups = "rg1mdio"; + function = "rg1mdio"; + }; + rg2_pins: rg2-pins { + groups = "rg2"; + function = "rg2"; + }; + ddr_pins: ddr-pins { + groups = "ddr"; + function = "ddr"; + }; + smb0_pins: smb0-pins { + groups = "smb0"; + function = "smb0"; + }; + smb1_pins: smb1-pins { + groups = "smb1"; + function = "smb1"; + }; + smb2_pins: smb2-pins { + groups = "smb2"; + function = "smb2"; + }; + smb2c_pins: smb2c-pins { + groups = "smb2c"; + function = "smb2c"; + }; + smb2b_pins: smb2b-pins { + groups = "smb2b"; + function = "smb2b"; + }; + smb1c_pins: smb1c-pins { + groups = "smb1c"; + function = "smb1c"; + }; + smb1b_pins: smb1b-pins { + groups = "smb1b"; + function = "smb1b"; + }; + smb8_pins: smb8-pins { + groups = "smb8"; + function = "smb8"; + }; + smb9_pins: smb9-pins { + groups = "smb9"; + function = "smb9"; + }; + smb10_pins: smb10-pins { + groups = "smb10"; + function = "smb10"; + }; + smb11_pins: smb11-pins { + groups = "smb11"; + function = "smb11"; + }; + sd1_pins: sd1-pins { + groups = "sd1"; + function = "sd1"; + }; + sd1pwr_pins: sd1pwr-pins { + groups = "sd1pwr"; + function = "sd1pwr"; + }; + pwm4_pins: pwm4-pins { + groups = "pwm4"; + function = "pwm4"; + }; + pwm5_pins: pwm5-pins { + groups = "pwm5"; + function = "pwm5"; + }; + pwm6_pins: pwm6-pins { + groups = "pwm6"; + function = "pwm6"; + }; + pwm7_pins: pwm7-pins { + groups = "pwm7"; + function = "pwm7"; + }; + mmc8_pins: mmc8-pins { + groups = "mmc8"; + function = "mmc8"; + }; + mmc_pins: mmc-pins { + groups = "mmc"; + function = "mmc"; + }; + mmcwp_pins: mmcwp-pins { + groups = "mmcwp"; + function = "mmcwp"; + }; + mmccd_pins: mmccd-pins { + groups = "mmccd"; + function = "mmccd"; + }; + mmcrst_pins: mmcrst-pins { + groups = "mmcrst"; + function = "mmcrst"; + }; + clkout_pins: clkout-pins { + groups = "clkout"; + function = "clkout"; + }; + serirq_pins: serirq-pins { + groups = "serirq"; + function = "serirq"; + }; + lpcclk_pins: lpcclk-pins { + groups = "lpcclk"; + function = "lpcclk"; + }; + scipme_pins: scipme-pins { + groups = "scipme"; + function = "scipme"; + }; + sci_pins: sci-pins { + groups = "sci"; + function = "sci"; + }; + smb6_pins: smb6-pins { + groups = "smb6"; + function = "smb6"; + }; + smb7_pins: smb7-pins { + groups = "smb7"; + function = "smb7"; + }; + pspi1_pins: pspi1-pins { + groups = "pspi1"; + function = "pspi1"; + }; + faninx_pins: faninx-pins { + groups = "faninx"; + function = "faninx"; + }; + r1_pins: r1-pins { + groups = "r1"; + function = "r1"; + }; + spi3_pins: spi3-pins { + groups = "spi3"; + function = "spi3"; + }; + spi3cs1_pins: spi3cs1-pins { + groups = "spi3cs1"; + function = "spi3cs1"; + }; + spi3quad_pins: spi3quad-pins { + groups = "spi3quad"; + function = "spi3quad"; + }; + spi3cs2_pins: spi3cs2-pins { + groups = "spi3cs2"; + function = "spi3cs2"; + }; + spi3cs3_pins: spi3cs3-pins { + groups = "spi3cs3"; + function = "spi3cs3"; + }; + nprd_smi_pins: nprd-smi-pins { + groups = "nprd_smi"; + function = "nprd_smi"; + }; + smb0b_pins: smb0b-pins { + groups = "smb0b"; + function = "smb0b"; + }; + smb0c_pins: smb0c-pins { + groups = "smb0c"; + function = "smb0c"; + }; + smb0den_pins: smb0den-pins { + groups = "smb0den"; + function = "smb0den"; + }; + smb0d_pins: smb0d-pins { + groups = "smb0d"; + function = "smb0d"; + }; + ddc_pins: ddc-pins { + groups = "ddc"; + function = "ddc"; + }; + rg2mdio_pins: rg2mdio-pins { + groups = "rg2mdio"; + function = "rg2mdio"; + }; + wdog1_pins: wdog1-pins { + groups = "wdog1"; + function = "wdog1"; + }; + wdog2_pins: wdog2-pins { + groups = "wdog2"; + function = "wdog2"; + }; + smb12_pins: smb12-pins { + groups = "smb12"; + function = "smb12"; + }; + smb13_pins: smb13-pins { + groups = "smb13"; + function = "smb13"; + }; + spix_pins: spix-pins { + groups = "spix"; + function = "spix"; + }; + spixcs1_pins: spixcs1-pins { + groups = "spixcs1"; + function = "spixcs1"; + }; + clkreq_pins: clkreq-pins { + groups = "clkreq"; + function = "clkreq"; + }; + hgpio0_pins: hgpio0-pins { + groups = "hgpio0"; + function = "hgpio0"; + }; + hgpio1_pins: hgpio1-pins { + groups = "hgpio1"; + function = "hgpio1"; + }; + hgpio2_pins: hgpio2-pins { + groups = "hgpio2"; + function = "hgpio2"; + }; + hgpio3_pins: hgpio3-pins { + groups = "hgpio3"; + function = "hgpio3"; + }; + hgpio4_pins: hgpio4-pins { + groups = "hgpio4"; + function = "hgpio4"; + }; + hgpio5_pins: hgpio5-pins { + groups = "hgpio5"; + function = "hgpio5"; + }; + hgpio6_pins: hgpio6-pins { + groups = "hgpio6"; + function = "hgpio6"; + }; + hgpio7_pins: hgpio7-pins { + groups = "hgpio7"; + function = "hgpio7"; }; }; }; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi new file mode 100644 index 000000000000..53cfd15fa03f --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj-gpio.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0pp_pins: gpio0pp-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + drive-push-pull; + }; + gpio1pp_pins: gpio1pp-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + drive-push-pull; + }; + gpio2pp_pins: gpio2pp-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + drive-push-pull; + }; + gpio3pp_pins: gpio3pp-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + drive-push-pull; + }; + gpio4pp_pins: gpio4pp-pins { + pins = "GPIO4/IOX2DI/SMB1DSDA"; + bias-disable; + drive-push-pull; + }; + gpio5pp_pins: gpio5pp-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + drive-push-pull; + }; + gpio6pp_pins: gpio6pp-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + drive-push-pull; + }; + gpio7pp_pins: gpio7pp-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + drive-push-pull; + }; + gpio8_pins: gpio8-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + gpio9_pins: gpio9-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + input-enable; + }; + gpio10pp_pins: gpio10pp-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + drive-push-pull; + }; + gpio11pp_pins: gpio11pp-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + drive-push-pull; + }; + gpio12_pins: gpio12-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + input-enable; + }; + gpio13_pins: gpio13-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + input-enable; + }; + gpio14_pins: gpio14-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + input-enable; + }; + gpio15od_pins: gpio15od-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + drive-open-drain; + }; + gpio17pp_pins: gpio17pp-pins { + pins = "GPIO17/PSPI2DI/SMB4DEN"; + bias-disable; + drive-push-pull; + }; + gpio18pp_pins: gpio18pp-pins { + pins = "GPIO18/PSPI2D0/SMB4BSDA"; + bias-disable; + drive-push-pull; + }; + gpio19pp_pins: gpio19pp-pins { + pins = "GPIO19/PSPI2CK/SMB4BSCL"; + bias-disable; + drive-push-pull; + }; + gpio24pp_pins: gpio24pp-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + drive-push-pull; + }; + gpio25pp_pins: gpio25pp-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + drive-push-pull; + }; + gpio37od_pins: gpio37od-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + drive-open-drain; + }; + gpio59pp_pins: gpio59pp-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + drive-push-pull; + }; + gpio60_pins: gpio60-pins { + pins = "GPIO60/SMB3DSCL"; + bias-disable; + input-enable; + }; + gpio72od_pins: gpio72od-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + drive-open-drain; + }; + gpio73od_pins: gpio73od-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + drive-open-drain; + }; + gpio74od_pins: gpio74od-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + drive-open-drain; + }; + gpio75od_pins: gpio75od-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + drive-open-drain; + }; + gpio76od_pins: gpio76od-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + drive-open-drain; + }; + gpio77od_pins: gpio77od-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + drive-open-drain; + }; + gpio78od_pins: gpio78od-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + drive-open-drain; + }; + gpio79od_pins: gpio79od-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + drive-open-drain; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84pp_pins: gpio84pp-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + drive-push-pull; + }; + gpio85pp_pins: gpio85pp-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + drive-push-pull; + }; + gpio86pp_pins: gpio86pp-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + drive-push-pull; + }; + gpio87pp_pins: gpio87pp-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + drive-push-pull; + }; + gpio88pp_pins: gpio88pp-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + drive-push-pull; + }; + gpio89pp_pins: gpio89pp-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + drive-push-pull; + }; + gpio90pp_pins: gpio90pp-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + drive-push-pull; + }; + gpio91_pins: gpio91-pins { + pins = "GPIO91/R2MDC"; + bias-disable; + input-enable; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2MDIO"; + bias-disable; + input-enable; + }; + gpio93pp_pins: gpio93pp-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + drive-push-pull; + }; + gpio94pp_pins: gpio94pp-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + drive-push-pull; + }; + gpio95_pins: gpio95-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio125pp_pins: gpio125pp-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + drive-push-pull; + }; + gpio126od_pins: gpio126od-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + drive-open-drain; + }; + gpio127od_pins: gpio127od-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + drive-open-drain; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142od_pins: gpio142od-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + drive-open-drain; + }; + gpio143ol_pins: gpio143ol-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + output-low; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio148_pins: gpio148-pins { + pins = "GPIO148/MMCDT4"; + bias-disable; + input-enable; + }; + gpio149_pins: gpio149-pins { + pins = "GPIO149/MMCDT5"; + bias-disable; + input-enable; + }; + gpio150_pins: gpio150-pins { + pins = "GPIO150/MMCDT6"; + bias-disable; + input-enable; + }; + gpio151_pins: gpio151-pins { + pins = "GPIO151/MMCDT7"; + bias-disable; + input-enable; + }; + gpio152_pins: gpio152-pins { + pins = "GPIO152/MMCCLK"; + bias-disable; + input-enable; + }; + gpio153_pins: gpio153-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + input-enable; + }; + gpio154_pins: gpio154-pins { + pins = "GPIO154/MMCCMD"; + bias-disable; + input-enable; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio156_pins: gpio156-pins { + pins = "GPIO156/MMCDT0"; + bias-disable; + input-enable; + }; + gpio157_pins: gpio157-pins { + pins = "GPIO157/MMCDT1"; + bias-disable; + input-enable; + }; + gpio158_pins: gpio158-pins { + pins = "GPIO158/MMCDT2"; + bias-disable; + input-enable; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMCDT3"; + bias-disable; + input-enable; + }; + gpio161_pins: gpio161-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + input-enable; + }; + gpio162_pins: gpio162-pins { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + gpio163_pins: gpio163-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio164_pins: gpio164-pins { + pins = "GPIO164/LAD0/ESPI_IO0"; + bias-disable; + input-enable; + }; + gpio165_pins: gpio165-pins { + pins = "GPIO165/LAD1/ESPI_IO1"; + bias-disable; + input-enable; + }; + gpio166_pins: gpio166-pins { + pins = "GPIO166/LAD2/ESPI_IO2"; + bias-disable; + input-enable; + }; + gpio167_pins: gpio167-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + input-enable; + }; + gpio168_pins: gpio168-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + gpio169_pins: gpio169-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + gpio170_pins: gpio170-pins { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + gpio175od_pins: gpio175od-pins { + pins = "GPIO175/PSPI1CK/FANIN19"; + bias-disable; + drive-open-drain; + }; + gpio176od_pins: gpio176od-pins { + pins = "GPIO176/PSPI1DO/FANIN18"; + bias-disable; + drive-open-drain; + }; + gpio177_pins: gpio177-pins { + pins = "GPIO177/PSPI1DI/FANIN17"; + bias-disable; + input-enable; + }; + gpio190od_pins: gpio190od-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + drive-open-drain; + }; + gpio191_pins: gpio191-pins { + pins = "GPIO191"; + bias-disable; + input-enable; + }; + gpio192_pins: gpio192-pins { + pins = "GPIO192"; + bias-disable; + input-enable; + }; + gpio194pp_pins: gpio194pp-pins { + pins = "GPIO194/SMB0BSCL"; + bias-disable; + drive-push-pull; + }; + gpio195od_pins: gpio195od-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + drive-open-drain; + }; + gpio196od_pins: gpio196od-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + drive-open-drain; + }; + gpio197od_pins: gpio197od-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + drive-open-drain; + }; + gpio198od_pins: gpio198od-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + drive-open-drain; + }; + gpio199od_pins: gpio199od-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + drive-open-drain; + }; + gpio200pp_pins: gpio200pp-pins { + pins = "GPIO200/R2CK"; + bias-disable; + drive-push-pull; + }; + gpio202od_pins: gpio202od-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + drive-open-drain; + }; + gpio203_pins: gpio203-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + input-enable; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts new file mode 100644 index 000000000000..801ed73d962c --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730-gsj.dts @@ -0,0 +1,553 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer lnc. Fran.Hsu@quantatw.com + +/dts-v1/; +#include "nuvoton-npcm730.dtsi" +#include "nuvoton-npcm730-gsj-gpio.dtsi" +/ { + model = "Quanta GSJ Board (Device Tree v12)"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet0 = &emc0; + ethernet1 = &gmac0; + serial3 = &serial3; + udc9 = &udc9; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c15 = &i2c15; + fiu0 = &fiu0; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + ahb { + gmac0: eth@f0802000 { + phy-mode = "rgmii-id"; + status = "okay"; + }; + + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm7xx-sdram-edac"; + reg = <0xf0824000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + }; + + emc0: eth@f0825000 { + phy-mode = "rmii"; + use-ncsi; + status = "okay"; + }; + + ehci1: usb@f0806000 { + status = "okay"; + }; + + ohci1: ohci@f0807000 { + status = "okay"; + }; + + udc9:udc@f0839000 { + status = "okay"; + }; + + aes:aes@f0858000 { + status = "okay"; + }; + + sha:sha@f085a000 { + status = "okay"; + }; + + fiu0: fiu@fb000000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1400000>; + }; + rwfs@1c00000 { + label = "rwfs"; + reg = <0x1c00000 0x300000>; + }; + reserved@1f00000 { + label = "reserved"; + reg = <0x1f00000 0x100000>; + }; + }; + }; + }; + + pcimbox: pcimbox@f0848000 { + status = "okay"; + }; + + apb { + + watchdog1: watchdog@901C { + status = "okay"; + }; + + rng: rng@b000 { + status = "okay"; + }; + + serial0: serial@1000 { + status = "okay"; + }; + + serial1: serial@2000 { + status = "okay"; + }; + + serial2: serial@3000 { + status = "okay"; + }; + + serial3: serial@4000 { + status = "okay"; + }; + + adc: adc@c000 { + status = "okay"; + }; + otp:otp@189000 { + status = "okay"; + }; + + i2c1: i2c@81000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; + }; + + i2c2: i2c@82000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; + }; + + i2c3: i2c@83000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; + }; + + i2c4: i2c@84000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + lm75@5c { + compatible = "maxim,max31725"; + reg = <0x5c>; + status = "okay"; + }; + }; + + i2c8: i2c@88000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c9: i2c@89000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; + }; + + i2c10: i2c@8a000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + eeprom@55 { + compatible = "atmel,24c64"; + reg = <0x55>; + }; + }; + + i2c11: i2c@8b000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + + /* P12V Quarter Brick DC/DC Power Module Q54SH12050 @60 */ + power-brick@36 { + compatible = "delta,dps800"; + reg = <0x36>; + }; + + hotswap@15 { + compatible = "ti,lm5066i"; + reg = <0x15>; + }; + }; + + i2c12: i2c@8c000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + ucd90160@6b { + compatible = "ti,ucd90160"; + reg = <0x6b>; + }; + }; + + i2c15: i2c@8f000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + + i2c-switch@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + i2c_u20: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_u21: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_u22: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_u23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_u24: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_u25: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_u26: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + + i2c_u27: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + }; + }; + }; + + pwm_fan:pwm-fan-controller@103000 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins &pwm1_pins &pwm2_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins>; + status = "okay"; + + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + }; + + }; + }; + + pinctrl: pinctrl@f0800000 { + pinctrl-names = "default"; + pinctrl-0 = < + /* GPI pins*/ + &gpio8_pins + &gpio9_pins + &gpio12_pins + &gpio13_pins + &gpio14_pins + &gpio60_pins + &gpio83_pins + &gpio91_pins + &gpio92_pins + &gpio95_pins + &gpio136_pins + &gpio137_pins + &gpio141_pins + &gpio144_pins + &gpio145_pins + &gpio146_pins + &gpio147_pins + &gpio148_pins + &gpio149_pins + &gpio150_pins + &gpio151_pins + &gpio152_pins + &gpio153_pins + &gpio154_pins + &gpio155_pins + &gpio156_pins + &gpio157_pins + &gpio158_pins + &gpio159_pins + &gpio161_pins + &gpio162_pins + &gpio163_pins + &gpio164_pins + &gpio165_pins + &gpio166_pins + &gpio167_pins + &gpio168_pins + &gpio169_pins + &gpio170_pins + &gpio177_pins + &gpio191_pins + &gpio192_pins + &gpio203_pins + /* GPO pins*/ + &gpio0pp_pins + &gpio1pp_pins + &gpio2pp_pins + &gpio3pp_pins + &gpio4pp_pins + &gpio5pp_pins + &gpio6pp_pins + &gpio7pp_pins + &gpio10pp_pins + &gpio11pp_pins + &gpio15od_pins + &gpio17pp_pins + &gpio18pp_pins + &gpio19pp_pins + &gpio24pp_pins + &gpio25pp_pins + &gpio37od_pins + &gpio59pp_pins + &gpio72od_pins + &gpio73od_pins + &gpio74od_pins + &gpio75od_pins + &gpio76od_pins + &gpio77od_pins + &gpio78od_pins + &gpio79od_pins + &gpio84pp_pins + &gpio85pp_pins + &gpio86pp_pins + &gpio87pp_pins + &gpio88pp_pins + &gpio89pp_pins + &gpio90pp_pins + &gpio93pp_pins + &gpio94pp_pins + &gpio125pp_pins + &gpio126od_pins + &gpio127od_pins + &gpio142od_pins + &gpio143ol_pins + &gpio175od_pins + &gpio176od_pins + &gpio190od_pins + &gpio194pp_pins + &gpio195od_pins + &gpio196od_pins + &gpio197od_pins + &gpio198od_pins + &gpio199od_pins + &gpio200pp_pins + &gpio202od_pins + >; + }; + + leds { + compatible = "gpio-leds"; + + led-bmc-live { + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + LED_U2_0_LOCATE { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_LOCATE { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_LOCATE { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_LOCATE { + gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_LOCATE { + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_LOCATE { + gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_BMC_TRAY_PWRGD { + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_FAULT { + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_LOCATE { + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_7_LOCATE { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_0_FAULT { + gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_1_FAULT { + gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_2_FAULT { + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_3_FAULT { + gpios = <&gpio2 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_4_FAULT { + gpios = <&gpio2 24 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_5_FAULT { + gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + LED_U2_6_FAULT { + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm730.dtsi b/arch/arm/boot/dts/nuvoton-npcm730.dtsi new file mode 100644 index 000000000000..20e13489b993 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm730.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com +// Copyright 2018 Google, Inc. + +#include "nuvoton-common-npcm7xx.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + soc { + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; + + ahb { + udc9:udc@f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd0000 0x800>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts index 15f744f1beea..de9c668c6e9a 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -9,6 +9,50 @@ model = "Nuvoton npcm750 Development Board (Device Tree)"; compatible = "nuvoton,npcm750"; + aliases { + ethernet0 = &emc0; + ethernet1 = &emc1; + ethernet2 = &gmac0; + ethernet3 = &gmac1; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + udc0 = &udc0; + udc1 = &udc1; + udc2 = &udc2; + udc3 = &udc3; + udc4 = &udc4; + udc5 = &udc5; + udc6 = &udc6; + udc7 = &udc7; + udc8 = &udc8; + udc9 = &udc9; + emmc0 = &sdhci0; + emmc1 = &sdhci1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + fiu2 = &fiux; + }; + chosen { stdout-path = &serial3; }; @@ -16,24 +60,553 @@ memory { reg = <0 0x40000000>; }; -}; -&watchdog1 { - status = "okay"; -}; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; -&serial0 { - status = "okay"; -}; + reg_vref1_2: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vref_1_2v"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + reg_vref3_3: regulator@1 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vref_3_3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; -&serial1 { - status = "okay"; -}; + ahb { + gmac0: eth@f0802000 { + phy-mode = "rgmii-id"; + status = "okay"; + }; + + gmac1: eth@f0804000 { + phy-mode = "rgmii-id"; + status = "okay"; + }; + + emc0: eth@f0825000 { + phy-mode = "rmii"; + #use-ncsi; /* add this to support ncsi */ + status = "okay"; + }; + + emc1: eth@f0826000 { + phy-mode = "rmii"; + #use-ncsi; /* add this to support ncsi */ + status = "okay"; + }; + + ehci1: usb@f0806000 { + status = "okay"; + }; + + ohci1: ohci@f0807000 { + status = "okay"; + }; + + udc0:udc@f0830000 { + status = "okay"; + }; + + udc1:udc@f0831000 { + status = "okay"; + }; + + udc2:udc@f0832000 { + status = "okay"; + }; + + udc3:udc@f0833000 { + status = "okay"; + }; + + udc4:udc@f0834000 { + status = "okay"; + }; + + udc5:udc@f0835000 { + status = "okay"; + }; + + udc6:udc@f0836000 { + status = "okay"; + }; + + udc7:udc@f0837000 { + status = "okay"; + }; + + udc8:udc@f0838000 { + status = "okay"; + }; + + udc9:udc@f0839000 { + status = "okay"; + }; + + aes:aes@f0858000 { + status = "okay"; + }; + + sha:sha@f085a000 { + status = "okay"; + }; + + fiu0: fiu@fb000000 { + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bbuboot1@0 { + label = "bb-uboot-1"; + reg = <0x0000000 0x80000>; + read-only; + }; + bbuboot2@80000 { + label = "bb-uboot-2"; + reg = <0x0080000 0x80000>; + read-only; + }; + envparam@100000 { + label = "env-param"; + reg = <0x0100000 0x40000>; + read-only; + }; + spare@140000 { + label = "spare"; + reg = <0x0140000 0xC0000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x400000>; + }; + rootfs@600000 { + label = "rootfs"; + reg = <0x0600000 0x700000>; + }; + spare1@D00000 { + label = "spare1"; + reg = <0x0D00000 0x200000>; + }; + spare2@0F00000 { + label = "spare2"; + reg = <0x0F00000 0x200000>; + }; + spare3@1100000 { + label = "spare3"; + reg = <0x1100000 0x200000>; + }; + spare4@1300000 { + label = "spare4"; + reg = <0x1300000 0x0>; + }; + }; + }; + }; + + fiu3: fiu@c0000000 { + pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-rx-bus-width = <2>; + reg = <0>; + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x0>; + }; + }; + }; + }; + + fiux: fiu@fb001000 { + spix-mode; + }; + + sdhci0: sdhci@f0842000 { + status = "okay"; + }; + + sdhci1: sdhci@f0840000 { + status = "okay"; + }; + + pcimbox: pcimbox@f0848000 { + status = "okay"; + }; + + vcd: vcd@f0810000 { + status = "okay"; + }; + + ece: ece@f0820000 { + status = "okay"; + }; + + apb { + + watchdog1: watchdog@901C { + status = "okay"; + }; + + rng: rng@b000 { + status = "okay"; + }; -&serial2 { - status = "okay"; + serial0: serial@1000 { + status = "okay"; + }; + + serial1: serial@2000 { + status = "okay"; + }; + + serial2: serial@3000 { + status = "okay"; + }; + + serial3: serial@4000 { + status = "okay"; + }; + + adc: adc@c000 { + /* enable external vref */ + /*vref-supply = <®_vref1_2>;*/ + status = "okay"; + }; + + otp:otp@189000 { + status = "okay"; + }; + + lpc_kcs: lpc_kcs@7000 { + kcs1: kcs1@0 { + status = "okay"; + }; + + kcs2: kcs2@0 { + status = "okay"; + }; + + kcs3: kcs3@0 { + status = "okay"; + }; + }; + + lpc_host: lpc_host@7000 { + lpc_bpc: lpc_bpc@40 { + monitor-ports = <0x80>; + status = "okay"; + }; + }; + + /* lm75 on SVB */ + i2c0: i2c@80000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; + }; + + /* lm75 on EB */ + i2c1: i2c@81000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + + lm75@48 { + compatible = "lm75"; + reg = <0x48>; + status = "okay"; + }; + }; + + /* tmp100 on EB */ + i2c2: i2c@82000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; + }; + + /* tmp100 on SVB */ + i2c6: i2c@86000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + + tmp100@48 { + compatible = "tmp100"; + reg = <0x48>; + status = "okay"; + }; + }; + i2c3: i2c@83000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c4: i2c@84000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "disabled"; + }; + + i2c5: i2c@85000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c7: i2c@87000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c8: i2c@88000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c9: i2c@89000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c10: i2c@8a000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c11: i2c@8b000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c14: i2c@8e000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c15: i2c@8f000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + /* SVB conflict with pspi2 cs gpio20o_pins */ + status = "disabled"; + }; + + pwm_fan:pwm-fan-controller@103000 { + status = "okay"; + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; + }; + + peci: peci-bus@100000 { + cmd-timeout-ms = <1000>; + pull-down = <0>; + host-neg-bit-rate = <15>; + status = "okay"; + intel-peci-dimmtemp@30 { + compatible = "intel,peci-client"; + reg = <0x30>; + status = "okay"; + }; + }; + + spi0: spi@200000 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; + Flash@0 { + compatible = "winbond,w25q128", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi0_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi0_spare2"; + reg = <0x800000 0x0>; + }; + }; + }; + + spi1: spi@201000 { + cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + status = "okay"; + Flash@0 { + compatible = "winbond,w25q128fw", + "jedec,spi-nor"; + reg = <0x0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + partition@0 { + label = "spi1_spare1"; + reg = <0x0000000 0x800000>; + }; + partition@1 { + label = "spi1_spare2"; + reg = <0x800000 0x0>; + }; + }; + }; + }; + }; + + pinctrl: pinctrl@f0800000 { + pinctrl-names = "default"; + pinctrl-0 = < &iox1_pins + &gpio8_pins + &gpio9o_pins + &gpio10_pins + &gpio11o_pins + &gpio16_pins + &gpio24o_pins + &gpio25ol_pins + &gpio32o_pins + &jtag2_pins + &gpio61o_pins + &gpio62o_pins + &gpio63o_pins + &gpio64o_pins /* SVB pspi1 enable */ + &gpio80_pins + &gpio81_pins + &gpio82_pins + &gpio83_pins + &lpc_pins + &gpio132_pins + &gpio133_pins + &gpio134_pins + &gpio135_pins + &gpio144_pins + &gpio145_pins + &gpio146_pins + &gpio147_pins + &gpio160_pins + &gpio162_pins + &gpio168_pins + &gpio169_pins + &gpio170_pins + &gpio187o_pins + &gpio190_pins + &gpio191o_pins + &gpio192o_pins + &gpio197ol_pins + &ddc_pins + &gpio218_pins + &gpio219ol_pins + &gpio220ol_pins + &gpio221o_pins + &gpio222_pins + &gpio223ol_pins + &spix_pins + &gpio228ol_pins + &gpio231o_pins + &gpio255_pins>; + }; }; -&serial3 { - status = "okay"; +&gcr { + serial_port_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <2>; /* Serial port mode 3 (takeover) */ + }; }; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi new file mode 100644 index 000000000000..a912910bc7ec --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-gpio.dtsi @@ -0,0 +1,2021 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0o_pins: gpio0o-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + output-high; + }; + gpio1_pins: gpio1-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + input-enable; + }; + gpio2_pins: gpio2-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + input-enable; + }; + gpio2o_pins: gpio2o-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + output_high; + }; + gpio3_pins: gpio3-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + input-enable; + }; + gpio3o_pins: gpio3o-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + output-high; + }; + gpio4_pins: gpio4-pins { + pins = "GPIO4/IOX2DI/SMB1DSDA"; + bias-disable; + input-enable; + }; + gpio5_pins: gpio5-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + input-enable; + }; + gpio6_pins: gpio6-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + input-enable; + }; + gpio6o_pins: gpio6o-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + output-high; + }; + gpio6ol_pins: gpio6ol-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + output-low; + }; + gpio7_pins: gpio7-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + input-enable; + }; + gpio7o_pins: gpio7o-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + output-high; + }; + gpio7ol_pins: gpio7ol-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + output-low; + }; + gpio8_pins: gpio8-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + input-enable; + }; + gpio8ol_pins: gpio8ol-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + output-low; + }; + gpio9_pins: gpio9-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + input-enable; + }; + gpio9o_pins: gpio9o-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-high; + }; + gpio9ol_pins: gpio9ol-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-low; + }; + gpio10_pins: gpio10-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + gpio10ol_pins: gpio10ol-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + output-low; + }; + gpio11_pins: gpio11-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + input-enable; + }; + gpio11o_pins: gpio11o-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + output-high; + }; + gpio11ol_pins: gpio11ol-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + output-low; + }; + gpio12_pins: gpio12-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + input-enable; + }; + gpio12o_pins: gpio12o-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + output-high; + }; + gpio12ol_pins: gpio12ol-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + output-low; + }; + gpio13_pins: gpio13-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + input-enable; + }; + gpio13ol_pins: gpio13ol-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + output-low; + }; + gpio14_pins: gpio14-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + input-enable; + }; + gpio14ol_pins: gpio14ol-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + output-low; + }; + gpio15_pins: gpio15-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + input-enable; + }; + gpio15o_pins: gpio15o-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + output-high; + }; + gpio16_pins: gpio16-pins { + pins = "GPIO16/LKGPO0"; + bias-disable; + input-enable; + }; + gpio16o_pins: gpio16o-pins { + pins = "GPIO16/LKGPO0"; + bias-disable; + output-high; + }; + gpio16ol_pins: gpio16ol-pins { + pins = "GPIO16/LKGPO0"; + bias-disable; + output-low; + }; + gpio17_pins: gpio17-pins { + pins = "GPIO17/PSPI2DI/SMB4DEN"; + bias-disable; + input-enable; + }; + gpio17o_pins: gpio17o-pins { + pins = "GPIO17/PSPI2DI/SMB4DEN"; + bias-disable; + output-high; + }; + gpio17ol_pins: gpio17ol-pins { + pins = "GPIO17/PSPI2DI/SMB4DEN"; + bias-disable; + output-low; + }; + gpio18_pins: gpio18-pins { + pins = "GPIO18/PSPI2D0/SMB4BSDA"; + bias-disable; + input-enable; + }; + gpio18ol_pins: gpio18ol-pins { + pins = "GPIO18/PSPI2D0/SMB4BSDA"; + bias-disable; + output-low; + }; + gpio19_pins: gpio19-pins { + pins = "GPIO19/PSPI2CK/SMB4BSCL"; + bias-disable; + input-enable; + }; + gpio19ol_pins: gpio19ol-pins { + pins = "GPIO19/PSPI2CK/SMB4BSCL"; + bias-disable; + output-low; + }; + gpio20_pins: gpio20-pins { + pins = "GPIO20/SMB4CSDA/SMB15SDA"; + bias-disable; + input-enable; + }; + gpio20o_pins: gpio20o-pins { + pins = "GPIO20/SMB4CSDA/SMB15SDA"; + bias-disable; + output-high; + }; + gpio20ol_pins: gpio20ol-pins { + pins = "GPIO20/SMB4CSDA/SMB15SDA"; + bias-disable; + output-low; + }; + gpio21_pins: gpio21-pins { + pins = "GPIO21/SMB4CSCL/SMB15SCL"; + bias-disable; + input-enable; + }; + gpio21ol_pins: gpio21ol-pins { + pins = "GPIO21/SMB4CSCL/SMB15SCL"; + bias-disable; + output-low; + }; + gpio22_pins: gpio22-pins { + pins = "GPIO22/SMB4DSDA/SMB14SDA"; + bias-disable; + input-enable; + }; + gpio22ol_pins: gpio22ol-pins { + pins = "GPIO22/SMB4DSDA/SMB14SDA"; + bias-disable; + output-low; + }; + gpio23_pins: gpio23-pins { + pins = "GPIO23/SMB4DSCL/SMB14SCL"; + bias-disable; + input-enable; + }; + gpio23ol_pins: gpio23ol-pins { + pins = "GPIO23/SMB4DSCL/SMB14SCL"; + bias-disable; + output-low; + }; + gpio24_pins: gpio24-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + input-enable; + }; + gpio24o_pins: gpio24o-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + output-high; + }; + gpio24ol_pins: gpio24ol-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + output-low; + }; + gpio25_pins: gpio25-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + input-enable; + }; + gpio25o_pins: gpio25o-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + output-high; + }; + gpio25ol_pins: gpio25ol-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + output-low; + }; + gpio26_pins: gpio26-pins { + pins = "GPIO26/SMB5SDA"; + bias-disable; + input-enable; + }; + gpio27_pins: gpio27-pins { + pins = "GPIO27/SMB5SCL"; + bias-disable; + input-enable; + }; + gpio32_pins: gpio32-pins { + pins = "GPIO32/nSPI0CS1"; + bias-disable; + input-enable; + }; + gpio32o_pins: gpio32o-pins { + pins = "GPIO32/nSPI0CS1"; + bias-disable; + output-high; + }; + gpio32ol_pins: gpio32ol-pins { + pins = "GPIO32/nSPI0CS1"; + bias-disable; + output-low; + }; + gpio37_pins: gpio37-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + input-enable; + }; + gpio37o_pins: gpio37o-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + output-high; + }; + gpio37ol_pins: gpio37ol-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + output-low; + }; + gpio38_pins: gpio38-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio38o_pins: gpio38o-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + output-high; + }; + gpio38ol_pins: gpio38ol-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + output-low; + }; + gpio39_pins: gpio39-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio39o_pins: gpio39o-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + output-high; + }; + gpio39ol_pins: gpio39ol-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + output-low; + }; + gpio40_pins: gpio40-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + input-enable; + }; + gpio40o_pins: gpio40o-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + output-high; + }; + gpio40ol_pins: gpio40ol-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + output-low; + }; + gpio41_pins: gpio41-pins { + pins = "GPIO41/BSPRXD"; + input-enable; + }; + gpio42_pins: gpio42-pins { + pins = "GPO42/BSPTXD/STRAP11"; + bias-disable; + input-enable; + }; + gpio43_pins: gpio43-pins { + pins = "GPIO43/RXD1/JTMS2/BU1RXD"; + bias-disable; + input-enable; + }; + gpio44_pins: gpio44-pins { + pins = "GPIO44/nCTS1/JTDI2/BU1CTS"; + bias-disable; + input-enable; + }; + gpio45_pins: gpio45-pins { + pins = "GPIO45/nDCD1/JTDO2"; + bias-disable; + input-enable; + }; + gpio46_pins: gpio46-pins { + pins = "GPIO46/nDSR1/JTCK2"; + bias-disable; + input-enable; + }; + gpio47_pins: gpio47-pins { + pins = "GPIO47/nRI1/JCP_RDY2"; + bias-disable; + input-enable; + }; + gpio48_pins: gpio48-pins { + pins = "GPIO48/TXD2/BSPTXD"; + bias-disable; + input-enable; + }; + gpio49_pins: gpio49-pins { + pins = "GPIO49/RXD2/BSPRXD"; + bias-disable; + input-enable; + }; + gpio50_pins: gpio50-pins { + pins = "GPIO50/nCTS2"; + bias-disable; + input-enable; + }; + gpio50ol_pins: gpio50ol-pins { + pins = "GPIO50/nCTS2"; + bias-disable; + output-low; + }; + gpio51_pins: gpio51-pins { + pins = "GPO51/nRTS2/STRAP2"; + bias-disable; + input-enable; + }; + gpio51o_pins: gpio51o-pins { + pins = "GPO51/nRTS2/STRAP2"; + bias-disable; + output-high; + }; + gpio52_pins: gpio52-pins { + pins = "GPIO52/nDCD2"; + bias-disable; + input-enable; + }; + gpio52ol_pins: gpio52ol-pins { + pins = "GPIO52/nDCD2"; + bias-disable; + output-low; + }; + gpio53_pins: gpio53-pins { + pins = "GPO53/nDTR2_BOUT2/STRAP1"; + bias-disable; + input-enable; + }; + gpio53o_pins: gpio53o-pins { + pins = "GPO53/nDTR2_BOUT2/STRAP1"; + bias-disable; + output-high; + }; + gpio54_pins: gpio54-pins { + pins = "GPIO54/nDSR2"; + bias-disable; + input-enable; + }; + gpio54ol_pins: gpio54ol-pins { + pins = "GPIO54/nDSR2"; + bias-disable; + output-low; + }; + gpio55_pins: gpio55-pins { + pins = "GPIO55/nRI2"; + bias-disable; + input-enable; + }; + gpio55ol_pins: gpio55ol-pins { + pins = "GPIO55/nRI2"; + bias-disable; + output-low; + }; + gpio56_pins: gpio56-pins { + pins = "GPIO56/R1RXERR"; + bias-disable; + input-enable; + }; + gpio57_pins: gpio57-pins { + pins = "GPIO57/R1MDC"; + bias-disable; + input-enable; + }; + gpio57ol_pins: gpio57ol-pins { + pins = "GPIO57/R1MDC"; + bias-disable; + output-low; + }; + gpio58_pins: gpio58-pins { + pins = "GPIO58/R1MDIO"; + bias-disable; + input-enable; + }; + gpio58ol_pins: gpio58ol-pins { + pins = "GPIO58/R1MDIO"; + bias-disable; + output-low; + }; + gpio59_pins: gpio59-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + input-enable; + }; + gpio59o_pins: gpio59o-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + output-high; + }; + gpio59ol_pins: gpio59ol-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + output-low; + }; + gpio60_pins: gpio60-pins { + pins = "GPIO60/SMB3DSCL"; + bias-disable; + input-enable; + }; + gpio60o_pins: gpio60o-pins { + pins = "GPIO60/SMB3DSCL"; + bias-disable; + output-high; + }; + gpio60ol_pins: gpio60ol-pins { + pins = "GPIO60/SMB3DSCL"; + bias-disable; + output-low; + }; + gpio61_pins: gpio61-pins { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + input-enable; + }; + gpio61o_pins: gpio61o-pins { + pins = "GPO61/nDTR1_BOUT1/STRAP6"; + bias-disable; + output-high; + }; + gpio62_pins: gpio62-pins { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + input-enable; + }; + gpio62o_pins: gpio62o-pins { + pins = "GPO62/nRTST1/STRAP5"; + bias-disable; + output-high; + }; + gpio63_pins: gpio63-pins { + pins = "GPO63/TXD1/STRAP4"; + bias-disable; + input-enable; + }; + gpio63o_pins: gpio63o-pins { + pins = "GPO63/TXD1/STRAP4"; + bias-disable; + output-high; + }; + gpio64_pins: gpio64-pins { + pins = "GPIO64/FANIN0"; + bias-disable; + input-enable; + }; + gpio64o_pins: gpio64o-pins { + pins = "GPIO64/FANIN0"; + bias-disable; + output-high; + }; + gpio65_pins: gpio65-pins { + pins = "GPIO65/FANIN1"; + bias-disable; + input-enable; + }; + gpio66_pins: gpio66-pins { + pins = "GPIO66/FANIN2"; + bias-disable; + input-enable; + }; + gpio67_pins: gpio67-pins { + pins = "GPIO67/FANIN3"; + bias-disable; + input-enable; + }; + gpio68_pins: gpio68-pins { + pins = "GPIO68/FANIN4"; + bias-disable; + input-enable; + }; + gpio69_pins: gpio69-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + input-enable; + }; + gpio69ol_pins: gpio69ol-pins { + pins = "GPIO69/FANIN5"; + bias-disable; + output-low; + }; + gpio70_pins: gpio70-pins { + pins = "GPIO70/FANIN6"; + bias-disable; + input-enable; + }; + gpio71_pins: gpio71-pins { + pins = "GPIO71/FANIN7"; + bias-disable; + input-enable; + }; + gpio72_pins: gpio72-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + input-enable; + }; + gpio72ol_pins: gpio72ol-pins { + pins = "GPIO72/FANIN8"; + bias-disable; + output-low; + }; + gpio73_pins: gpio73-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + input-enable; + }; + gpio73ol_pins: gpio73ol-pins { + pins = "GPIO73/FANIN9"; + bias-disable; + output-low; + }; + gpio74_pins: gpio74-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + input-enable; + }; + gpio74ol_pins: gpio74ol-pins { + pins = "GPIO74/FANIN10"; + bias-disable; + output-low; + }; + gpio75_pins: gpio75-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + input-enable; + }; + gpio75ol_pins: gpio75ol-pins { + pins = "GPIO75/FANIN11"; + bias-disable; + output-low; + }; + gpio76_pins: gpio76-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio76ol_pins: gpio76ol-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + output-low; + }; + gpio77_pins: gpio77-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio77ol_pins: gpio77ol-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + output-low; + }; + gpio78_pins: gpio78-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + input-enable; + }; + gpio78ol_pins: gpio78ol-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + output-low; + }; + gpio79_pins: gpio79-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + input-enable; + }; + gpio79ol_pins: gpio79ol-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + output-low; + }; + gpio80_pins: gpio80-pins { + pins = "GPIO80/PWM0"; + bias-disable; + input-enable; + }; + gpio81_pins: gpio81-pins { + pins = "GPIO81/PWM1"; + bias-disable; + input-enable; + }; + gpio82_pins: gpio82-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84_pins: gpio84-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + input-enable; + }; + gpio84o_pins: gpio84ol-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + output-high; + }; + gpio85_pins: gpio85-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + input-enable; + }; + gpio85o_pins: gpio85o-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + output-high; + }; + gpio86_pins: gpio86-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + input-enable; + }; + gpio86o_pins: gpio86o-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + output-high; + }; + gpio87_pins: gpio87-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + input-enable; + }; + gpio87o_pins: gpio87o-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + output-high; + }; + gpio88_pins: gpio88-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + input-enable; + }; + gpio88ol_pins: gpio88ol-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + output-low; + }; + gpio89_pins: gpio89-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + input-enable; + }; + gpio89ol_pins: gpio89ol-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + output-low; + }; + gpio90_pins: gpio90-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + input-enable; + }; + gpio90o_pins: gpio90o0-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + output-high; + }; + gpio90ol_pins: gpio90ol-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + output-low; + }; + gpio91_pins: gpio91-pins { + pins = "GPIO91/R2MDC"; + bias-disable; + input-enable; + }; + gpio91o_pins: gpio91o-pins { + pins = "GPIO91/R2MDC"; + bias-disable; + output-high; + }; + gpio91ol_pins: gpio91ol-pins { + pins = "GPIO91/R2MDC"; + bias-disable; + output-low; + }; + gpio92_pins: gpio92-pins { + pins = "GPIO92/R2MDIO"; + bias-disable; + input-enable; + }; + gpio92o_pins: gpio92o-pins { + pins = "GPIO92/R2MDIO"; + bias-disable; + output-high; + }; + gpio92ol_pins: gpio92ol-pins { + pins = "GPIO92/R2MDIO"; + bias-disable; + output-low; + }; + gpio93_pins: gpio93-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + input-enable; + }; + gpio93ol_pins: gpio93ol-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + output-low; + }; + gpio94_pins: gpio94-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + input-enable; + }; + gpio94o_pins: gpio94o-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + output-high; + }; + gpio95_pins: gpio95-pins { + pins = "GPIO95/nLRESET/nESPIRST"; + bias-disable; + input-enable; + }; + gpio96_pins: gpio96-pins { + pins = "GPIO96/RG1TXD0"; + bias-disable; + input-enable; + }; + gpio96ol_pins: gpio96ol-pins { + pins = "GPIO96/RG1TXD0"; + bias-disable; + output-low; + }; + gpio97_pins: gpio97-pins { + pins = "GPIO97/RG1TXD1"; + bias-disable; + input-enable; + }; + gpio97ol_pins: gpio97ol-pins { + pins = "GPIO97/RG1TXD1"; + bias-disable; + output-low; + }; + gpio98_pins: gpio98-pins { + pins = "GPIO98/RG1TXD2"; + bias-disable; + input-enable; + }; + gpio98ol_pins: gpio98ol-pins { + pins = "GPIO98/RG1TXD2"; + bias-disable; + output-low; + }; + gpio99_pins: gpio99-pins { + pins = "GPIO99/RG1TXD3"; + bias-disable; + input-enable; + }; + gpio99ol_pins: gpio99ol-pins { + pins = "GPIO99/RG1TXD3"; + bias-disable; + output-low; + }; + gpio100_pins: gpio100-pins { + pins = "GPIO100/RG1TXC"; + bias-disable; + input-enable; + }; + gpio100ol_pins: gpio100ol-pins { + pins = "GPIO100/RG1TXC"; + bias-disable; + output-low; + }; + gpio101_pins: gpio101-pins { + pins = "GPIO101/RG1TXCTL"; + bias-disable; + input-enable; + }; + gpio101ol_pins: gpio101ol-pins { + pins = "GPIO101/RG1TXCTL"; + bias-disable; + output-low; + }; + gpio102_pins: gpio102-pins { + pins = "GPIO102/RG1RXD0"; + bias-disable; + input-enable; + }; + gpio102ol_pins: gpio102ol-pins { + pins = "GPIO102/RG1RXD0"; + bias-disable; + output-low; + }; + gpio103_pins: gpio103-pins { + pins = "GPIO103/RG1RXD1"; + bias-disable; + input-enable; + }; + gpio103ol_pins: gpio103ol-pins { + pins = "GPIO103/RG1RXD1"; + bias-disable; + output-low; + }; + gpio104_pins: gpio104-pins { + pins = "GPIO104/RG1RXD2"; + bias-disable; + input-enable; + }; + gpio104ol_pins: gpio104ol-pins { + pins = "GPIO104/RG1RXD2"; + bias-disable; + output-low; + }; + gpio105_pins: gpio105-pins { + pins = "GPIO105/RG1RXD3"; + bias-disable; + input-enable; + }; + gpio105ol_pins: gpio105ol-pins { + pins = "GPIO105/RG1RXD3"; + bias-disable; + output-low; + }; + gpio106_pins: gpio106-pins { + pins = "GPIO106/RG1RXC"; + bias-disable; + input-enable; + }; + gpio106ol_pins: gpio106ol-pins { + pins = "GPIO106/RG1RXC"; + bias-disable; + output-low; + }; + gpio107_pins: gpio107-pins { + pins = "GPIO107/RG1RXCTL"; + bias-disable; + input-enable; + }; + gpio107ol_pins: gpio107ol-pins { + pins = "GPIO107/RG1RXCTL"; + bias-disable; + output-low; + }; + gpio108_pins: gpio108-pins { + pins = "GPIO108/RG1MDC"; + bias-disable; + input-enable; + }; + gpio108ol_pins: gpio108ol-pins { + pins = "GPIO108/RG1MDC"; + bias-disable; + output-low; + }; + gpio109_pins: gpio109-pins { + pins = "GPIO109/RG1MDIO"; + bias-disable; + input-enable; + }; + gpio109ol_pins: gpio109ol-pins { + pins = "GPIO109/RG1MDIO"; + bias-disable; + output-low; + }; + gpio110_pins: gpio110-pins { + pins = "GPIO110/RG2TXD0/DDRV0"; + bias-disable; + input-enable; + }; + gpio110ol_pins: gpio110ol-pins { + pins = "GPIO110/RG2TXD0/DDRV0"; + bias-disable; + output-low; + }; + gpio111_pins: gpio111-pins { + pins = "GPIO111/RG2TXD1/DDRV1"; + bias-disable; + input-enable; + }; + gpio111ol_pins: gpio111ol-pins { + pins = "GPIO111/RG2TXD1/DDRV1"; + bias-disable; + output-low; + }; + gpio112_pins: gpio112-pins { + pins = "GPIO112/RG2TXD2/DDRV2"; + bias-disable; + input-enable; + }; + gpio112ol_pins: gpio112ol-pins { + pins = "GPIO112/RG2TXD2/DDRV2"; + bias-disable; + output-low; + }; + gpio113_pins: gpio113-pins { + pins = "GPIO113/RG2TXD3/DDRV3"; + bias-disable; + input-enable; + }; + gpio113ol_pins: gpio113ol-pins { + pins = "GPIO113/RG2TXD3/DDRV3"; + bias-disable; + output-low; + }; + gpio118_pins: gpio118-pins { + pins = "GPIO118/SMB2SCL"; + bias-disable; + input-enable; + }; + gpio119_pins: gpio119-pins { + pins = "GPIO119/SMB2SDA"; + bias-disable; + input-enable; + }; + gpio120_pins: gpio120-pins { + pins = "GPIO120/SMB2CSDA"; + bias-disable; + input-enable; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122_pins: gpio122-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124_pins: gpio124-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125_pins: gpio125-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126_pins: gpio126-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127_pins: gpio127-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + input-enable; + }; + gpio128o_pins: gpio128o-pins { + pins = "GPIO128/SMB8SCL"; + bias-disable; + output-high; + }; + gpio130_pins: gpio130-pins { + pins = "GPIO130/SMB9SCL"; + bias-disable; + input-enable; + }; + gpio131_pins: gpio131-pins { + pins = "GPIO131/SMB9SDA"; + bias-disable; + input-enable; + }; + gpio132_pins: gpio132-pins { + pins = "GPIO132/SMB10SCL"; + bias-disable; + input-enable; + }; + gpio133_pins: gpio133-pins { + pins = "GPIO133/SMB10SDA"; + bias-disable; + input-enable; + }; + gpio134_pins: gpio134-pins { + pins = "GPIO134/SMB11SCL"; + bias-disable; + input-enable; + }; + gpio135_pins: gpio135-pins { + pins = "GPIO135/SMB11SDA"; + bias-disable; + input-enable; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio136o_pins: gpio136o-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + output-high; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio137o_pins: gpio137o-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + output-high; + }; + gpio138_pins: gpio138-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio138o_pins: gpio138o-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + output-high; + }; + gpio139_pins: gpio139-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio139o_pins: gpio139o-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + output-high; + }; + gpio140_pins: gpio140-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio140o_pins: gpio140o-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + output-high; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio141o_pins: gpio141o-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + output-high; + }; + gpio142_pins: gpio142-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + input-enable; + }; + gpio142o_pins: gpio142o-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + output-high; + }; + gpio143_pins: gpio143-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + input-enable; + }; + gpio143o_pins: gpio143o-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + output-high; + }; + gpio143ol_pins: gpio143ol-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + output-low; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio148_pins: gpio148-pins { + pins = "GPIO148/MMCDT4"; + bias-disable; + input-enable; + }; + gpio148o_pins: gpio148o-pins { + pins = "GPIO148/MMCDT4"; + bias-disable; + output-high; + }; + gpio148ol_pins: gpio148ol_pins { + pins = "GPIO148/MMCDT4"; + bias-disable; + output-low; + }; + gpio149_pins: gpio149-pins { + pins = "GPIO149/MMCDT5"; + bias-disable; + input-enable; + }; + gpio149o_pins: gpio149o-pins { + pins = "GPIO149/MMCDT5"; + bias-disable; + output-high; + }; + gpio149ol_pins: gpio149ol-pins { + pins = "GPIO149/MMCDT5"; + bias-disable; + output-low; + }; + gpio150_pins: gpio150-pins { + pins = "GPIO150/MMCDT6"; + bias-disable; + input-enable; + }; + gpio150o_pins: gpio150o-pins { + pins = "GPIO150/MMCDT6"; + bias-disable; + output-high; + }; + gpio150ol_pins: gpio150ol-pins { + pins = "GPIO150/MMCDT6"; + bias-disable; + output-low; + }; + gpio151_pins: gpio151-pins { + pins = "GPIO151/MMCDT7"; + bias-disable; + input-enable; + }; + gpio151o_pins: gpio151o-pins { + pins = "GPIO151/MMCDT7"; + bias-disable; + output-high; + }; + gpio151ol_pins: gpio151ol-pins { + pins = "GPIO151/MMCDT7"; + bias-disable; + output-low; + }; + gpio152_pins: gpio152-pins { + pins = "GPIO152/MMCCLK"; + bias-disable; + input-enable; + }; + gpio152o_pins: gpio152o-pins { + pins = "GPIO152/MMCCLK"; + bias-disable; + output-high; + }; + gpio152ol_pins: gpio152ol-pins { + pins = "GPIO152/MMCCLK"; + bias-disable; + output-low; + }; + gpio153_pins: gpio153-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + input-enable; + }; + gpio153ol_pins: gpio153ol-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + output-low; + }; + gpio154_pins: gpio154-pins { + pins = "GPIO154/MMCCMD"; + bias-disable; + input-enable; + }; + gpio154ol_pins: gpio154ol-pins { + pins = "GPIO154/MMCCMD"; + bias-disable; + output-low; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio155ol_pins: gpio155ol-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + output-low; + }; + gpio156_pins: gpio156-pins { + pins = "GPIO156/MMCDT0"; + bias-disable; + input-enable; + }; + gpio156ol_pins: gpio156ol-pins { + pins = "GPIO156/MMCDT0"; + bias-disable; + output-low; + }; + gpio157_pins: gpio157-pins { + pins = "GPIO157/MMCDT1"; + bias-disable; + input-enable; + }; + gpio157o_pins: gpio157o-pins { + pins = "GPIO157/MMCDT1"; + bias-disable; + output-high; + }; + gpio157ol_pins: gpio157ol-pins { + pins = "GPIO157/MMCDT1"; + bias-disable; + output-low; + }; + gpio158_pins: gpio158-pins { + pins = "GPIO158/MMCDT2"; + bias-disable; + input-enable; + }; + gpio158o_pins: gpio158o-pins { + pins = "GPIO158/MMCDT2"; + bias-disable; + output-high; + }; + gpio158ol_pins: gpio158ol-pins { + pins = "GPIO158/MMCDT2"; + bias-disable; + output-low; + }; + gpio159_pins: gpio159-pins { + pins = "GPIO159/MMCDT3"; + bias-disable; + input-enable; + }; + gpio159o_pins: gpio159o-pins { + pins = "GPIO159/MMCDT3"; + bias-disable; + output-high; + }; + gpio159ol_pins: gpio159ol-pins { + pins = "GPIO159/MMCDT3"; + bias-disable; + output-low; + }; + gpio160_pins: gpio160-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + input-enable; + }; + gpio160o_pins: gpio160o-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + output-high; + }; + gpio160ol_pins: gpio160ol-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + output-low; + }; + gpio161_pins: gpio161-pins { + pins = "GPIO161/nLFRAME/nESPICS"; + bias-disable; + input-enable; + }; + gpio162_pins: gpio162-pins { + pins = "GPIO162/SERIRQ"; + bias-disable; + input-enable; + }; + gpio163_pins: gpio163-pins { + pins = "GPIO163/LCLK/ESPICLK"; + bias-disable; + input-enable; + }; + gpio164_pins: gpio164-pins { + pins = "GPIO164/LAD0/ESPI_IO0"; + bias-disable; + input-enable; + }; + gpio165_pins: gpio165-pins { + pins = "GPIO165/LAD1/ESPI_IO1"; + bias-disable; + input-enable; + }; + gpio166_pins: gpio166-pins { + pins = "GPIO166/LAD2/ESPI_IO2"; + bias-disable; + input-enable; + }; + gpio167_pins: gpio167-pins { + pins = "GPIO167/LAD3/ESPI_IO3"; + bias-disable; + input-enable; + }; + gpio168_pins: gpio168-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + input-enable; + }; + gpio168ol_pins: gpio168ol-pins { + pins = "GPIO168/nCLKRUN/nESPIALERT"; + bias-disable; + output-low; + }; + gpio169_pins: gpio169-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + input-enable; + }; + gpio169o_pins: gpio169o-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio169ol_pins: gpio169ol-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-low; + }; + gpio170_pins: gpio170-pins { + pins = "GPIO170/nSMI"; + bias-disable; + input-enable; + }; + gpio170ol_pins: gpio170ol-pins { + pins = "GPIO170/nSMI"; + bias-disable; + output-low; + }; + gpio173o_pins: gpio173o-pins { + pins = "GPIO173/SMB7SCL"; + bias-disable; + output-high; + }; + gpio173ol_pins: gpio173ol-pins { + pins = "GPIO173/SMB7SCL"; + bias-disable; + output-low; + }; + gpio174_pins: gpio174-pins { + pins = "GPIO174/SMB7SDA"; + bias-disable; + input-enable; + }; + gpio175_pins: gpio175-pins { + pins = "GPIO175/PSPI1CK/FANIN19"; + bias-disable; + input-enable; + }; + gpio175o_pins: gpio175o-pins { + pins = "GPIO175/PSPI1CK/FANIN19"; + bias-disable; + output-high; + }; + gpio175ol_pins: gpio175ol-pins { + pins = "GPIO175/PSPI1CK/FANIN19"; + bias-disable; + output-low; + }; + gpio176_pins: gpio176-pins { + pins = "GPIO176/PSPI1DO/FANIN18"; + bias-disable; + input-enable; + }; + gpio176o_pins: gpio176o-pins { + pins = "GPIO176/PSPI1DO/FANIN18"; + bias-disable; + output-high; + }; + gpio176ol_pins: gpio176ol-pins { + pins = "GPIO176/PSPI1DO/FANIN18"; + bias-disable; + output-low; + }; + gpio177_pins: gpio177-pins { + pins = "GPIO177/PSPI1DI/FANIN17"; + bias-disable; + input-enable; + }; + gpio177o_pins: gpio177o-pins { + pins = "GPIO177/PSPI1DI/FANIN17"; + bias-disable; + output-high; + }; + gpio177ol_pins: gpio177ol-pins { + pins = "GPIO177/PSPI1DI/FANIN17"; + bias-disable; + output-low; + }; + gpio187_pins: gpio187-pins { + pins = "GPIO187/nSPI3CS1"; + bias-disable; + input-enable; + }; + gpio187o_pins: gpio187o-pins { + pins = "GPIO187/nSPI3CS1"; + bias-disable; + output-high; + }; + gpio187ol_pins: gpio187ol-pins { + pins = "GPIO187/nSPI3CS1"; + bias-disable; + output-low; + }; + gpio188_pins: gpio188-pins { + pins = "GPIO188/SPI3D2/nSPI3CS2"; + bias-disable; + input-enable; + }; + gpio188o_pins: gpio188o-pins { + pins = "GPIO188/SPI3D2/nSPI3CS2"; + bias-disable; + output-high; + }; + gpio189o_pins: gpio189o-pins { + pins = "GPIO189/SPI3D3/nSPI3CS3"; + bias-disable; + output-high; + }; + gpio190_pins: gpio190-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + input-enable; + }; + gpio190o_pins: gpio190o-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-high; + }; + gpio190ol_pins: gpio190ol-pins { + pins = "GPIO190/nPRD_SMI"; + bias-disable; + output-low; + }; + gpio191o_pins: gpio191o-pins { + pins = "GPIO191"; + bias-disable; + output-high; + }; + gpio191ol_pins: gpio191ol-pins { + pins = "GPIO191"; + bias-disable; + output-low; + }; + gpio192_pins: gpio192-pins { + pins = "GPIO192"; + bias-disable; + input-enable; + }; + gpio192o_pins: gpio192o-pins { + pins = "GPIO192"; + bias-disable; + output-high; + }; + gpio192ol_pins: gpio192ol-pins { + pins = "GPIO192"; + bias-disable; + output-low; + }; + gpio194_pins: gpio194-pins { + pins = "GPIO194/SMB0BSCL"; + bias-disable; + input-enable; + }; + gpio194o_pins: gpio194o-pins { + pins = "GPIO194/SMB0BSCL"; + bias-disable; + output-high; + }; + gpio195_pins: gpio195-pins { + pins = "GPIO195/SMB0BSDA"; + bias-disable; + input-enable; + }; + gpio196_pins: gpio196-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + input-enable; + }; + gpio197_pins: gpio197-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + input-enable; + }; + gpio197o_pins: gpio197o-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + output-high; + }; + gpio197ol_pins: gpio197ol-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + output-low; + }; + gpio198o_pins: gpio198o-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + output-high; + }; + gpio198ol_pins: gpio198ol-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + output-low; + }; + gpio199_pins: gpio199-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + input-enable; + }; + gpio200_pins: gpio200-pins { + pins = "GPIO200/R2CK"; + input-enable; + bias-disable; + }; + gpio200ol_pins: gpio200ol-pins { + pins = "GPIO200/R2CK"; + bias-disable; + output-low; + }; + gpio201ol_pins: gpio201ol-pins { + pins = "GPIO200/R2CK"; + bias-disable; + output-low; + }; + gpio202_pins: gpio202-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + input-enable; + }; + gpio203_pins: gpio203-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + input-enable; + }; + gpio203o_pins: gpio203o-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + output-high; + }; + gpio203ol_pins: gpio203ol-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + output-low; + }; + gpio204_pins: gpio204-pins { + pins = "GPIO204/DDC2SCL"; + bias-disable; + input-enable; + }; + gpio204o_pins: gpio204o-pins { + pins = "GPIO204/DDC2SCL"; + bias-disable; + output-high; + }; + gpio204ol_pins: gpio204ol-pins { + pins = "GPIO204/DDC2SCL"; + bias-disable; + output-low; + }; + gpio205_pins: gpio205-pins { + pins = "GPIO205/DDC2SDA"; + bias-disable; + input-enable; + }; + gpio205o_pins: gpio205o-pins { + pins = "GPIO205/DDC2SDA"; + bias-disable; + output-high; + }; + gpio205ol_pins: gpio205ol-pins { + pins = "GPIO205/DDC2SDA"; + bias-disable; + output-low; + }; + gpio206_pins: gpio206-pins { + pins = "GPIO206/HSYNC2"; + bias-disable; + input-enable; + }; + gpio206o_pins: gpio206o-pins { + pins = "GPIO206/HSYNC2"; + bias-disable; + output-high; + }; + gpio206ol_pins: gpio206ol-pins { + pins = "GPIO206/HSYNC2"; + bias-disable; + output-low; + }; + gpio207_pins: gpio207-pins { + pins = "GPIO207/VSYNC2"; + bias-disable; + input-enable; + }; + gpio207o_pins: gpio207o-pins { + pins = "GPIO207/VSYNC2"; + bias-disable; + output-high; + }; + gpio207ol_pins: gpio207ol-pins { + pins = "GPIO207/VSYNC2"; + bias-disable; + output-low; + }; + gpio208_pins: gpio208-pins { + pins = "GPIO208/RG2TXC/DVCK"; + bias-disable; + input-enable; + }; + gpio208o_pins: gpio208o-pins { + pins = "GPIO208/RG2TXC/DVCK"; + bias-disable; + output-high; + }; + gpio208ol_pins: gpio208ol-pins { + pins = "GPIO208/RG2TXC/DVCK"; + bias-disable; + output-low; + }; + gpio209_pins: gpio209-pins { + pins = "GPIO209/RG2TXCTL/DDRV4"; + bias-disable; + input-enable; + }; + gpio209ol_pins: gpio209ol-pins { + pins = "GPIO209/RG2TXCTL/DDRV4"; + bias-disable; + output-low; + }; + gpio210_pins: gpio210-pins { + pins = "GPIO210/RG2RXD0/DDRV5"; + bias-disable; + input-enable; + }; + gpio210o_pins: gpio210o-pins { + pins = "GPIO210/RG2RXD0/DDRV5"; + bias-disable; + output-high; + }; + gpio210ol_pins: gpio210ol-pins { + pins = "GPIO210/RG2RXD0/DDRV5"; + bias-disable; + output-low; + }; + gpio211_pins: gpio211-pins { + pins = "GPIO211/RG2RXD1/DDRV6"; + bias-disable; + input-enable; + }; + gpio211o_pins: gpio211o-pins { + pins = "GPIO211/RG2RXD1/DDRV6"; + bias-disable; + output-high; + }; + gpio211ol_pins: gpio211ol-pins { + pins = "GPIO211/RG2RXD1/DDRV6"; + bias-disable; + output-low; + }; + gpio212_pins: gpio212-pins { + pins = "GPIO212/RG2RXD2/DDRV7"; + bias-disable; + input-enable; + }; + gpio212o_pins: gpio212o-pins { + pins = "GPIO212/RG2RXD2/DDRV7"; + bias-disable; + output-high; + }; + gpio212ol_pins: gpio212ol-pins { + pins = "GPIO212/RG2RXD2/DDRV7"; + bias-disable; + output-low; + }; + gpio213_pins: gpio213-pins { + pins = "GPIO213/RG2RXD3/DDRV8"; + bias-disable; + input-enable; + }; + gpio213o_pins: gpio213o-pins { + pins = "GPIO213/RG2RXD3/DDRV8"; + bias-disable; + output-high; + }; + gpio213ol_pins: gpio213ol-pins { + pins = "GPIO213/RG2RXD3/DDRV8"; + bias-disable; + output-low; + }; + gpio214_pins: gpio214-pins { + pins = "GPIO214/RG2RXC/DDRV9"; + bias-disable; + input-enable; + }; + gpio214ol_pins: gpio214ol-pins { + pins = "GPIO214/RG2RXC/DDRV9"; + bias-disable; + output-low; + }; + gpio215_pins: gpio215-pins { + pins = "GPIO215/RG2RXCTL/DDRV10"; + bias-disable; + input-enable; + }; + gpio215ol_pins: gpio215ol-pins { + pins = "GPIO215/RG2RXCTL/DDRV10"; + bias-disable; + output-low; + }; + gpio216_pins: gpio216-pins { + pins = "GPIO216/RG2MDC/DDRV11"; + bias-disable; + input-enable; + }; + gpio216ol_pins: gpio216ol-pins { + pins = "GPIO216/RG2MDC/DDRV11"; + bias-disable; + output-low; + }; + gpio217_pins: gpio217-pins { + pins = "GPIO217/RG2MDIO/DVHSYNC"; + bias-disable; + input-enable; + }; + gpio217ol_pins: gpio217ol-pins { + pins = "GPIO217/RG2MDIO/DVHSYNC"; + bias-disable; + output-low; + }; + gpio218_pins: gpio218-pins { + pins = "GPIO218/nWDO1"; + bias-disable; + input-enable; + }; + gpio218ol_pins: gpio218ol-pins { + pins = "GPIO218/nWDO1"; + bias-disable; + output-low; + }; + gpio219_pins: gpio219-pins { + pins = "GPIO219/nWDO2"; + bias-disable; + input-enable; + }; + gpio219ol_pins: gpio219ol-pins { + pins = "GPIO219/nWDO2"; + bias-disable; + output-low; + }; + gpio220ol_pins: gpio220ol-pins { + pins = "GPIO220/SMB12SCL"; + bias-disable; + output-low; + }; + gpio221o_pins: gpio221o-pins { + pins = "GPIO221/SMB12SDA"; + bias-disable; + output-high; + }; + gpio222_pins: gpio222-pins { + pins = "GPIO222/SMB13SCL"; + bias-disable; + input-enable; + }; + gpio222o_pins: gpio222o-pins { + pins = "GPIO222/SMB13SCL"; + bias-disable; + output-high; + }; + gpio223_pins: gpio223-pins { + pins = "GPIO223/SMB13SDA"; + bias-disable; + input-enable; + }; + gpio223ol_pins: gpio223ol-pins { + pins = "GPIO223/SMB13SDA"; + bias-disable; + output-low; + }; + gpio224_pins: gpio224-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + input-enable; + }; + gpio224o_pins: gpio224o-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + output-high; + }; + gpio224ol_pins: gpio224ol-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + output-low; + }; + gpio225_pins: gpio225-pins { + pins = "GPO225/SPIXD0/STRAP12"; + bias-disable; + input-enable; + }; + gpio225o_pins: gpio225o-pins { + pins = "GPO225/SPIXD0/STRAP12"; + bias-disable; + output-high; + }; + gpio226_pins: gpio226-pins { + pins = "GPO226/SPIXD1/STRAP13"; + bias-disable; + input-enable; + }; + gpio226o_pins: gpio226o-pins { + pins = "GPO226/SPIXD1/STRAP13"; + bias-disable; + output-high; + }; + gpio227_pins: gpio227-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + input-enable; + }; + gpio227o_pins: gpio227o-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + output-high; + }; + gpio227ol_pins: gpio227ol-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + output-low; + }; + gpio228_pins: gpio228-pins { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + input-enable; + }; + gpio228ol_pins: gpio228ol-pins { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-low; + }; + gpio229_pins: gpio229-pins { + pins = "GPO229/SPIXD2/STRAP3"; + bias-disable; + input-enable; + }; + gpio229o_pins: gpio229o-pins { + pins = "GPO229/SPIXD2/STRAP3"; + bias-disable; + output-high; + }; + gpio230_pins: gpio230-pins { + pins = "GPIO230/SPIXD3"; + bias-disable; + input-enable; + }; + gpio230o_pins: gpio230o-pins { + pins = "GPIO230/SPIXD3"; + bias-disable; + output-high; + }; + gpio230ol_pins: gpio230ol-pins { + pins = "GPIO230/SPIXD3"; + bias-disable; + output-low; + }; + gpio231_pins: gpio231-pins { + pins = "GPIO231/nCLKREQ"; + bias-disable; + input-enable; + }; + gpio231o_pins: gpio231o-pins { + pins = "GPIO231/nCLKREQ"; + bias-disable; + output-high; + }; + gpio255_pins: gpio255-pins { + pins = "GPI255/DACOSEL"; + bias-disable; + input-enable; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi new file mode 100644 index 000000000000..230cb344b2e1 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus-pincfg.dtsi @@ -0,0 +1,517 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com + +/ { + pinctrl: pinctrl@f0800000 { + gpio0ol_pins: gpio0ol-pins { + pins = "GPIO0/IOX1DI"; + bias-disable; + output-low; + }; + gpio1ol_pins: gpio1ol-pins { + pins = "GPIO1/IOX1LD"; + bias-disable; + output-low; + }; + gpio2ol_pins: gpio2ol-pins { + pins = "GPIO2/IOX1CK"; + bias-disable; + output-low; + }; + gpio3ol_pins: gpio3ol-pins { + pins = "GPIO3/IOX1D0"; + bias-disable; + output-low; + }; + gpio5_pins: gpio5-pins { + pins = "GPIO5/IOX2LD/SMB1DSCL"; + bias-disable; + input-enable; + }; + gpio6_pins: gpio6-pins { + pins = "GPIO6/IOX2CK/SMB2DSDA"; + bias-disable; + input-enable; + }; + gpio7_pins: gpio7-pins { + pins = "GPIO7/IOX2D0/SMB2DSCL"; + bias-disable; + input-enable; + }; + gpio8o_pins: gpio8o-pins { + pins = "GPIO8/LKGPO1"; + bias-disable; + output-high; + }; + gpio9ol_pins: gpio9ol-pins { + pins = "GPIO9/LKGPO2"; + bias-disable; + output-low; + }; + gpio10_pins: gpio10-pins { + pins = "GPIO10/IOXHLD"; + bias-disable; + input-enable; + }; + gpio11_pins: gpio11-pins { + pins = "GPIO11/IOXHCK"; + bias-disable; + input-enable; + }; + gpio12ol_pins: gpio12ol-pins { + pins = "GPIO12/GSPICK/SMB5BSCL"; + bias-disable; + output-low; + }; + gpio13ol_pins: gpio13ol-pins { + pins = "GPIO13/GSPIDO/SMB5BSDA"; + bias-disable; + output-low; + }; + gpio14ol_pins: gpio14ol-pins { + pins = "GPIO14/GSPIDI/SMB5CSCL"; + bias-disable; + output-low; + }; + gpio15ol_pins: gpio15ol-pins { + pins = "GPIO15/GSPICS/SMB5CSDA"; + bias-disable; + output-low; + }; + gpio20_pins: gpio20-pins { + pins = "GPIO20/SMB4CSDA/SMB15SDA"; + bias-disable; + input-enable; + }; + gpio21_pins: gpio21-pins { + pins = "GPIO21/SMB4CSCL/SMB15SCL"; + bias-disable; + input-enable; + }; + gpio22o_pins: gpio22o-pins { + pins = "GPIO22/SMB4DSDA/SMB14SDA"; + bias-disable; + output-high; + }; + gpio23_pins: gpio23-pins { + pins = "GPIO23/SMB4DSCL/SMB14SCL"; + bias-disable; + input-enable; + }; + gpio24_pins: gpio24-pins { + pins = "GPIO24/IOXHDO"; + bias-disable; + input-enable; + }; + gpio25_pins: gpio25-pins { + pins = "GPIO25/IOXHDI"; + bias-disable; + input-enable; + }; + gpio30_pins: gpio30-pins { + pins = "GPIO30/SMB3SDA"; + bias-disable; + input-enable; + }; + gpio31_pins: gpio31-pins { + pins = "GPIO31/SMB3SCL"; + bias-disable; + input-enable; + }; + gpio37o_pins: gpio37o-pins { + pins = "GPIO37/SMB3CSDA"; + bias-disable; + output-high; + }; + gpio38_pins: gpio38-pins { + pins = "GPIO38/SMB3CSCL"; + bias-disable; + input-enable; + }; + gpio39_pins: gpio39-pins { + pins = "GPIO39/SMB3BSDA"; + bias-disable; + input-enable; + }; + gpio40o_pins: gpio40o-pins { + pins = "GPIO40/SMB3BSCL"; + bias-disable; + output-high; + }; + gpio59_pins: gpio59-pins { + pins = "GPIO59/SMB3DSDA"; + bias-disable; + input-enable; + }; + gpio76_pins: gpio76-pins { + pins = "GPIO76/FANIN12"; + bias-disable; + input-enable; + }; + gpio77_pins: gpio77-pins { + pins = "GPIO77/FANIN13"; + bias-disable; + input-enable; + }; + gpio78o_pins: gpio78o-pins { + pins = "GPIO78/FANIN14"; + bias-disable; + output-high; + }; + gpio79_pins: gpio79-pins { + pins = "GPIO79/FANIN15"; + bias-disable; + input-enable; + }; + gpio82_pins: gpio82-pins { + pins = "GPIO82/PWM2"; + bias-disable; + input-enable; + }; + gpio83_pins: gpio83-pins { + pins = "GPIO83/PWM3"; + bias-disable; + input-enable; + }; + gpio84_pins: gpio84-pins { + pins = "GPIO84/R2TXD0"; + bias-disable; + input-enable; + }; + gpio85o_pins: gpio85o-pins { + pins = "GPIO85/R2TXD1"; + bias-disable; + output-high; + }; + gpio86ol_pins: gpio86ol-pins { + pins = "GPIO86/R2TXEN"; + bias-disable; + output-low; + }; + gpio87_pins: gpio87-pins { + pins = "GPIO87/R2RXD0"; + bias-disable; + input-enable; + }; + gpio88_pins: gpio88-pins { + pins = "GPIO88/R2RXD1"; + bias-disable; + input-enable; + }; + gpio89_pins: gpio89-pins { + pins = "GPIO89/R2CRSDV"; + bias-disable; + input-enable; + }; + gpio90_pins: gpio90-pins { + pins = "GPIO90/R2RXERR"; + bias-disable; + input-enable; + }; + gpio93_pins: gpio93-pins { + pins = "GPIO93/GA20/SMB5DSCL"; + bias-disable; + input-enable; + }; + gpio94ol_pins: gpio94ol-pins { + pins = "GPIO94/nKBRST/SMB5DSDA"; + bias-disable; + output-low; + }; + gpio108ol_pins: gpio108ol-pins { + pins = "GPIO108/RG1MDC"; + bias-disable; + output-low; + }; + gpio109ol_pins: gpio109ol-pins { + pins = "GPIO109/RG1MDIO"; + bias-disable; + output-low; + }; + gpio110ol_pins: gpio110ol-pins { + pins = "GPIO110/RG2TXD0/DDRV0"; + bias-disable; + output-low; + }; + gpio111ol_pins: gpio111ol-pins { + pins = "GPIO111/RG2TXD1/DDRV1"; + bias-disable; + output-low; + }; + gpio112ol_pins: gpio112ol-pins { + pins = "GPIO112/RG2TXD2/DDRV2"; + bias-disable; + output-low; + }; + gpio113ol_pins: gpio113ol-pins { + pins = "GPIO113/RG2TXD3/DDRV3"; + bias-disable; + output-low; + }; + gpio114o_pins: gpio114o-pins { + pins = "GPIO114/SMB0SCL"; + bias-disable; + output-high; + }; + gpio115_pins: gpio115-pins { + pins = "GPIO115/SMB0SDA"; + bias-disable; + input-enable; + }; + gpio120_pins: gpio120-pins { + pins = "GPIO120/SMB2CSDA"; + bias-disable; + input-enable; + }; + gpio121_pins: gpio121-pins { + pins = "GPIO121/SMB2CSCL"; + bias-disable; + input-enable; + }; + gpio122_pins: gpio122-pins { + pins = "GPIO122/SMB2BSDA"; + bias-disable; + input-enable; + }; + gpio123_pins: gpio123-pins { + pins = "GPIO123/SMB2BSCL"; + bias-disable; + input-enable; + }; + gpio124_pins: gpio124-pins { + pins = "GPIO124/SMB1CSDA"; + bias-disable; + input-enable; + }; + gpio125_pins: gpio125-pins { + pins = "GPIO125/SMB1CSCL"; + bias-disable; + input-enable; + }; + gpio126_pins: gpio126-pins { + pins = "GPIO126/SMB1BSDA"; + bias-disable; + input-enable; + }; + gpio127o_pins: gpio127o-pins { + pins = "GPIO127/SMB1BSCL"; + bias-disable; + output-high; + }; + gpio136_pins: gpio136-pins { + pins = "GPIO136/SD1DT0"; + bias-disable; + input-enable; + }; + gpio137_pins: gpio137-pins { + pins = "GPIO137/SD1DT1"; + bias-disable; + input-enable; + }; + gpio138_pins: gpio138-pins { + pins = "GPIO138/SD1DT2"; + bias-disable; + input-enable; + }; + gpio139_pins: gpio139-pins { + pins = "GPIO139/SD1DT3"; + bias-disable; + input-enable; + }; + gpio140_pins: gpio140-pins { + pins = "GPIO140/SD1CLK"; + bias-disable; + input-enable; + }; + gpio141_pins: gpio141-pins { + pins = "GPIO141/SD1WP"; + bias-disable; + input-enable; + }; + gpio142_pins: gpio142-pins { + pins = "GPIO142/SD1CMD"; + bias-disable; + input-enable; + }; + gpio143_pins: gpio143-pins { + pins = "GPIO143/SD1CD/SD1PWR"; + bias-disable; + input-enable; + }; + gpio144_pins: gpio144-pins { + pins = "GPIO144/PWM4"; + bias-disable; + input-enable; + }; + gpio145_pins: gpio145-pins { + pins = "GPIO145/PWM5"; + bias-disable; + input-enable; + }; + gpio146_pins: gpio146-pins { + pins = "GPIO146/PWM6"; + bias-disable; + input-enable; + }; + gpio147_pins: gpio147-pins { + pins = "GPIO147/PWM7"; + bias-disable; + input-enable; + }; + gpio153o_pins: gpio153o-pins { + pins = "GPIO153/MMCWP"; + bias-disable; + output-high; + }; + gpio155_pins: gpio155-pins { + pins = "GPIO155/nMMCCD/nMMCRST"; + bias-disable; + input-enable; + }; + gpio160o_pins: gpio160o-pins { + pins = "GPIO160/CLKOUT/RNGOSCOUT"; + bias-disable; + output-high; + }; + gpio169o_pins: gpio169o-pins { + pins = "GPIO169/nSCIPME"; + bias-disable; + output-high; + }; + gpio188o_pins: gpio188o-pins { + pins = "GPIO188/SPI3D2/nSPI3CS2"; + bias-disable; + output-high; + }; + gpio189_pins: gpio189-pins { + pins = "GPIO189/SPI3D3/nSPI3CS3"; + bias-disable; + input-enable; + }; + gpio196_pins: gpio196-pins { + pins = "GPIO196/SMB0CSCL"; + bias-disable; + input-enable; + }; + gpio197_pins: gpio197-pins { + pins = "GPIO197/SMB0DEN"; + bias-disable; + input-enable; + }; + gpio198o_pins: gpio198o-pins { + pins = "GPIO198/SMB0DSDA"; + bias-disable; + output-high; + }; + gpio199o_pins: gpio199o-pins { + pins = "GPIO199/SMB0DSCL"; + bias-disable; + output-high; + }; + gpio200_pins: gpio200-pins { + pins = "GPIO200/R2CK"; + input-enable; + bias-disable; + }; + gpio202_pins: gpio202-pins { + pins = "GPIO202/SMB0CSDA"; + bias-disable; + input-enable; + }; + gpio203o_pins: gpio203o-pins { + pins = "GPIO203/FANIN16"; + bias-disable; + output-high; + }; + gpio208_pins: gpio208-pins { + pins = "GPIO208/RG2TXC/DVCK"; + bias-disable; + input-enable; + }; + gpio209ol_pins: gpio209ol-pins { + pins = "GPIO209/RG2TXCTL/DDRV4"; + bias-disable; + output-low; + }; + gpio210ol_pins: gpio210ol-pins { + pins = "GPIO210/RG2RXD0/DDRV5"; + bias-disable; + output-low; + }; + gpio211ol_pins: gpio211ol-pins { + pins = "GPIO211/RG2RXD1/DDRV6"; + bias-disable; + output-low; + }; + gpio212ol_pins: gpio212ol-pins { + pins = "GPIO212/RG2RXD2/DDRV7"; + bias-disable; + output-low; + }; + gpio213ol_pins: gpio213ol-pins { + pins = "GPIO213/RG2RXD3/DDRV8"; + bias-disable; + output-low; + }; + gpio214ol_pins: gpio214ol-pins { + pins = "GPIO214/RG2RXC/DDRV9"; + bias-disable; + output-low; + }; + gpio215ol_pins: gpio215ol-pins { + pins = "GPIO215/RG2RXCTL/DDRV10"; + bias-disable; + output-low; + }; + gpio216ol_pins: gpio216ol-pins { + pins = "GPIO216/RG2MDC/DDRV11"; + bias-disable; + output-low; + }; + gpio217ol_pins: gpio217ol-pins { + pins = "GPIO217/RG2MDIO/DVHSYNC"; + bias-disable; + output-low; + }; + gpio224_pins: gpio224-pins { + pins = "GPIO224/SPIXCK"; + bias-disable; + input-enable; + }; + gpio225ol_pins: gpio225ol-pins { + pins = "GPO225/SPIXD0/STRAP12"; + bias-disable; + output-low; + }; + gpio226ol_pins: gpio226ol-pins { + pins = "GPO226/SPIXD1/STRAP13"; + bias-disable; + output-low; + }; + gpio227ol_pins: gpio227ol-pins { + pins = "GPIO227/nSPIXCS0"; + bias-disable; + output-low; + }; + gpio228o_pins: gpio228ol-pins { + pins = "GPIO228/nSPIXCS1"; + bias-disable; + output-high; + }; + gpio229o_pins: gpio229o-pins { + pins = "GPO229/SPIXD2/STRAP3"; + bias-disable; + output-high; + }; + gpio230_pins: gpio230-pins { + pins = "GPIO230/SPIXD3"; + bias-disable; + input-enable; + }; + gpio231o_pins: gpio231o-pins { + pins = "GPIO231/nCLKREQ"; + bias-disable; + output-high; + }; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts new file mode 100644 index 000000000000..71b384676301 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-runbmc-olympus.dts @@ -0,0 +1,1197 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology kwliu@nuvoton.com +// Copyright (c) 2019 Quanta Computer Inc. Samuel.Jiang@quantatw.com + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" +#include "nuvoton-npcm750-runbmc-olympus-pincfg.dtsi" + +/ { + model = "Nuvoton npcm750 RunBMC Olympus"; + compatible = "nuvoton,npcm750"; + + aliases { + ethernet0 = &emc0; + ethernet1 = &gmac0; + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + udc0 = &udc0; + udc1 = &udc1; + udc2 = &udc2; + udc3 = &udc3; + udc4 = &udc4; + udc5 = &udc5; + udc6 = &udc6; + udc7 = &udc7; + udc8 = &udc8; + udc9 = &udc9; + emmc0 = &sdhci0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + spi0 = &spi0; + spi1 = &spi1; + fiu0 = &fiu0; + fiu1 = &fiu3; + }; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, + <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>; + }; + + ahb { + gmac0: eth@f0802000 { + phy-mode = "rgmii-id"; + snps,eee-force-disable; + status = "okay"; + }; + + emc0: eth@f0825000 { + phy-mode = "rmii"; + use-ncsi; + status = "okay"; + }; + + ehci1: usb@f0806000 { + status = "okay"; + }; + + ohci1: ohci@f0807000 { + status = "okay"; + }; + + udc0:udc@f0830000 { + status = "okay"; + }; + + udc1:udc@f0831000 { + status = "okay"; + }; + + udc2:udc@f0832000 { + status = "okay"; + }; + + udc3:udc@f0833000 { + status = "okay"; + }; + + udc4:udc@f0834000 { + status = "okay"; + }; + + udc5:udc@f0835000 { + status = "okay"; + }; + + udc6:udc@f0836000 { + status = "okay"; + }; + + udc7:udc@f0837000 { + status = "okay"; + }; + + udc8:udc@f0838000 { + status = "okay"; + }; + + udc9:udc@f0839000 { + status = "okay"; + }; + + aes:aes@f0858000 { + status = "okay"; + }; + + sha:sha@f085a000 { + status = "okay"; + }; + + fiu0: fiu@fb000000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0cs1_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + partitions@80000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + bmc@0{ + label = "bmc"; + reg = <0x000000 0x2000000>; + }; + u-boot@0 { + label = "u-boot"; + reg = <0x0000000 0x80000>; + read-only; + }; + u-boot-env@100000{ + label = "u-boot-env"; + reg = <0x00100000 0x40000>; + }; + kernel@200000 { + label = "kernel"; + reg = <0x0200000 0x600000>; + }; + rofs@800000 { + label = "rofs"; + reg = <0x800000 0x1500000>; + }; + rwfs@1d00000 { + label = "rwfs"; + reg = <0x1d00000 0x300000>; + }; + }; + }; + spi-nor@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + npcm,fiu-rx-bus-width = <2>; + partitions@88000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + spare1@0 { + label = "spi0-cs1-spare1"; + reg = <0x0 0x800000>; + }; + spare2@800000 { + label = "spi0-cs1-spare2"; + reg = <0x800000 0x0>; + }; + }; + }; + }; + + fiu3: fiu@c0000000 { + pinctrl-0 = <&spi3_pins>; + status = "okay"; + spi-nor@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-rx-bus-width = <2>; + partitions@A0000000 { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + system1@0 { + label = "spi3-system1"; + reg = <0x0 0x800000>; + }; + system2@800000 { + label = "spi3-system2"; + reg = <0x800000 0x0>; + }; + }; + }; + }; + + sdhci0: sdhci@f0842000 { + status = "okay"; + }; + + pcimbox: pcimbox@f0848000 { + status = "okay"; + }; + + vcd: vcd@f0810000 { + status = "okay"; + }; + + ece: ece@f0820000 { + status = "okay"; + }; + + apb { + + watchdog1: watchdog@901C { + status = "okay"; + }; + + rng: rng@b000 { + status = "okay"; + }; + + serial0: serial@1000 { + status = "okay"; + }; + + serial1: serial@2000 { + status = "okay"; + }; + + serial2: serial@3000 { + status = "okay"; + }; + + serial3: serial@4000 { + status = "okay"; + }; + + adc: adc@c000 { + #io-channel-cells = <1>; + status = "okay"; + }; + + otp:otp@189000 { + status = "okay"; + }; + + lpc_kcs: lpc_kcs@7000 { + kcs1: kcs1@0 { + status = "okay"; + }; + + kcs2: kcs2@0 { + status = "okay"; + }; + + kcs3: kcs3@0 { + status = "okay"; + }; + }; + + lpc_host: lpc_host@7000 { + lpc_bpc: lpc_bpc@40 { + monitor-ports = <0x80>; + status = "okay"; + }; + }; + + i2c0: i2c@80000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@81000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + i2c-switch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c_slot1a: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_slot1b: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + i2c_slot2a: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_slot2b: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + + i2c_slot3: i2c-bus@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + + i2c_slot4: i2c-bus@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + }; + + i2c_slot5: i2c-bus@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + }; + }; + + i2c-switch@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + i2c_m2_s1: i2c-bus@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + i2c_m2_s2: i2c-bus@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + i2c_m2_s3: i2c-bus@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + i2c_m2_s4: i2c-bus@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + i2c2: i2c@82000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + power-supply@58 { + compatible = "delta,dps800"; + reg = <0x58>; + }; + }; + + i2c3: i2c@83000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c4: i2c@84000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + eeprom@54 { + compatible = "atmel,24c64"; + reg = <0x54>; + }; + }; + + i2c5: i2c@85000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + slave_mqueue: i2c-slave-mqueue@40000010 { + compatible = "i2c-slave-mqueue"; + reg = <0x40000010>; + status = "okay"; + }; + }; + + i2c6: i2c@86000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + ina219@40 { + compatible = "ti,ina219"; + reg = <0x40>; + }; + ina219@41 { + compatible = "ti,ina219"; + reg = <0x41>; + }; + ina219@44 { + compatible = "ti,ina219"; + reg = <0x44>; + }; + ina219@45 { + compatible = "ti,ina219"; + reg = <0x45>; + }; + tps53679@60 { + compatible = "ti,tps53679"; + reg = <0x60>; + }; + tps53659@62 { + compatible = "ti,tps53659"; + reg = <0x62>; + }; + tps53659@64 { + compatible = "ti,tps53659"; + reg = <0x64>; + }; + tps53622@67 { + compatible = "ti,tps53622"; + reg = <0x67>; + }; + tps53622@69 { + compatible = "ti,tps53622"; + reg = <0x69>; + }; + tps53679@70 { + compatible = "ti,tps53679"; + reg = <0x70>; + }; + tps53659@72 { + compatible = "ti,tps53659"; + reg = <0x72>; + }; + tps53659@74 { + compatible = "ti,tps53659"; + reg = <0x74>; + }; + tps53622@77 { + compatible = "ti,tps53622"; + reg = <0x77>; + }; + }; + + i2c7: i2c@87000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + tmp421@4c { + compatible = "ti,tmp421"; + reg = <0x4c>; + }; + }; + + i2c8: i2c@88000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + adm1278@11 { + compatible = "adm1278"; + reg = <0x11>; + Rsense = <500>; + }; + }; + + i2c9: i2c@89000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + }; + + i2c10: i2c@8a000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + gpio: pca9555@27 { + compatible = "nxp,pca9555"; + reg = <0x27>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; + + i2c11: i2c@8b000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + pca9539_g1a: pca9539-g1a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + G1A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "TPM_BMC_ALERT_N"; + }; + G1A_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_TOP_SWAP"; + }; + G1A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_BIOS_PREFRB2_GOOD"; + }; + G1A_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "BMC_SATAXPCIE_0TO3_SEL"; + }; + G1A_P0_4 { + gpio-hog; + gpios = <4 0>; + input; + line-name = "BMC_SATAXPCIE_4TO7_SEL"; + }; + G1A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "FM_UV_ADR_TRIGGER_EN_N"; + }; + G1A_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "RM_THROTTLE_EN_N"; + }; + G1A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_BMC_TPM_PRES_N"; + }; + G1A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_CPU0_SKTOCC_LVT3_N"; + }; + G1A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_CPU1_SKTOCC_LVT3_N"; + }; + G1A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_ALERT_N"; + }; + G1A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "PSU2_ALERT_N"; + }; + G1A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "H_CPU0_FAST_WAKE_LVT3_N"; + }; + G1A_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "I2C_MUX1_RESET_N"; + }; + G1A_P1_7 { + gpio-hog; + gpios = <15 0>; + input; + line-name = "FM_CPU_CATERR_LVT3_N"; + }; + }; + pca9539_g1b: pca9539-g1b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G1B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "PVDDQ_ABC_PINALERT_N"; + }; + G1B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "PVDDQ_DEF_PINALERT_N"; + }; + G1B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "PVDDQ_GHJ_PINALERT_N"; + }; + G1B_P0_3 { + gpio-hog; + gpios = <3 0>; + input; + line-name = "PVDDQ_KLM_PINALERT_N"; + }; + G1B_P0_5 { + gpio-hog; + gpios = <5 0>; + input; + line-name = "FM_BOARD_REV_ID0"; + }; + G1B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BOARD_REV_ID1"; + }; + G1B_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "FM_BOARD_REV_ID2"; + }; + G1B_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_OC_DETECT_EN_N"; + }; + G1B_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_FLASH_DESC_OVERRIDE"; + }; + G1B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "FP_PWR_ID_LED_N"; + }; + G1B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "BMC_LED_PWR_GRN"; + }; + G1B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "BMC_LED_PWR_AMBER"; + }; + G1B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-high; + line-name = "FM_BMC_FAULT_LED_N"; + }; + G1B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_CPLD_BMC_PWRDN_N"; + }; + G1B_P1_7 { + gpio-hog; + gpios = <15 0>; + output-high; + line-name = "BMC_LED_CATERR_N"; + }; + }; + }; + + i2c12: i2c@8c000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + pca9539_g2a: pca9539-g2a@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + reset-gpios = <&gpio5 28 GPIO_ACTIVE_LOW>; + G2A_P0_0 { + gpio-hog; + gpios = <0 0>; + output-high; + line-name = "BMC_PON_RST_REQ_N"; + }; + G2A_P0_1 { + gpio-hog; + gpios = <1 0>; + output-high; + line-name = "BMC_RST_IND_REQ_N"; + }; + G2A_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "RST_BMC_RTCRST"; + }; + G2A_P0_3 { + gpio-hog; + gpios = <3 0>; + output-high; + line-name = "FM_BMC_PWRBTN_OUT_N"; + }; + G2A_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "RST_BMC_SYSRST_BTN_OUT_N"; + }; + G2A_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "FM_BATTERY_SENSE_EN_N"; + }; + G2A_P0_6 { + gpio-hog; + gpios = <6 0>; + output-high; + line-name = "FM_BMC_READY_N"; + }; + G2A_P0_7 { + gpio-hog; + gpios = <7 0>; + input; + line-name = "IRQ_BMC_PCH_SMI_LPC_N"; + }; + G2A_P1_0 { + gpio-hog; + gpios = <8 0>; + input; + line-name = "FM_SLOT4_CFG0"; + }; + G2A_P1_1 { + gpio-hog; + gpios = <9 0>; + input; + line-name = "FM_SLOT4_CFG1"; + }; + G2A_P1_2 { + gpio-hog; + gpios = <10 0>; + input; + line-name = "FM_NVDIMM_EVENT_N"; + }; + G2A_P1_3 { + gpio-hog; + gpios = <11 0>; + input; + line-name = "PSU1_BLADE_EN_N"; + }; + G2A_P1_4 { + gpio-hog; + gpios = <12 0>; + input; + line-name = "BMC_PCH_FNM"; + }; + G2A_P1_5 { + gpio-hog; + gpios = <13 0>; + input; + line-name = "FM_SOL_UART_CH_SEL"; + }; + G2A_P1_6 { + gpio-hog; + gpios = <14 0>; + input; + line-name = "FM_BIOS_POST_CMPLT_N"; + }; + }; + + pca9539_g2b: pca9539-g2b@75 { + compatible = "nxp,pca9539"; + reg = <0x75>; + gpio-controller; + #gpio-cells = <2>; + G2B_P0_0 { + gpio-hog; + gpios = <0 0>; + input; + line-name = "FM_CPU_MSMI_LVT3_N"; + }; + G2B_P0_1 { + gpio-hog; + gpios = <1 0>; + input; + line-name = "FM_BIOS_MRC_DEBUG_MSG_DIS"; + }; + G2B_P0_2 { + gpio-hog; + gpios = <2 0>; + input; + line-name = "FM_CPU1_DISABLE_BMC_N"; + }; + G2B_P0_3 { + gpio-hog; + gpios = <3 0>; + output-low; + line-name = "BMC_JTAG_SELECT"; + }; + G2B_P0_4 { + gpio-hog; + gpios = <4 0>; + output-high; + line-name = "PECI_MUX_SELECT"; + }; + G2B_P0_5 { + gpio-hog; + gpios = <5 0>; + output-high; + line-name = "I2C_MUX2_RESET_N"; + }; + G2B_P0_6 { + gpio-hog; + gpios = <6 0>; + input; + line-name = "FM_BMC_CPLD_PSU2_ON"; + }; + G2B_P0_7 { + gpio-hog; + gpios = <7 0>; + output-high; + line-name = "PSU2_ALERT_EN_N"; + }; + G2B_P1_0 { + gpio-hog; + gpios = <8 0>; + output-high; + line-name = "FM_CPU_BMC_INIT"; + }; + G2B_P1_1 { + gpio-hog; + gpios = <9 0>; + output-high; + line-name = "IRQ_BMC_PCH_SCI_LPC_N"; + }; + G2B_P1_2 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PMB_ALERT_EN_N"; + }; + G2B_P1_3 { + gpio-hog; + gpios = <11 0>; + output-high; + line-name = "FM_FAST_PROCHOT_EN_N"; + }; + G2B_P1_4 { + gpio-hog; + gpios = <12 0>; + output-high; + line-name = "BMC_NVDIMM_PRSNT_N"; + }; + G2B_P1_5 { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "FM_BACKUP_BIOS_SEL_H_BMC"; + }; + G2B_P1_6 { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "FM_PWRBRK_N"; + }; + }; + }; + + i2c13: i2c@8d000 { + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <100000>; + status = "okay"; + tmp75@4a { + compatible = "ti,tmp75"; + reg = <0x4a>; + status = "okay"; + }; + m24128_fru@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + pagesize = <64>; + status = "okay"; + }; + }; + + pwm_fan:pwm-fan-controller@103000 { + pinctrl-names = "default"; + pinctrl-0 = < &pwm0_pins &pwm1_pins + &fanin0_pins &fanin1_pins + &fanin2_pins &fanin3_pins + &fanin4_pins &fanin5_pins + &fanin6_pins &fanin7_pins + &fanin8_pins &fanin9_pins + &fanin10_pins &fanin11_pins>; + status = "okay"; + fan@0 { + reg = <0x00>; + fan-tach-ch = /bits/ 8 <0x00 0x01>; + cooling-levels = <127 255>; + }; + fan@1 { + reg = <0x01>; + fan-tach-ch = /bits/ 8 <0x02 0x03>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@2 { + reg = <0x02>; + fan-tach-ch = /bits/ 8 <0x04 0x05>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@3 { + reg = <0x03>; + fan-tach-ch = /bits/ 8 <0x06 0x07>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@4 { + reg = <0x04>; + fan-tach-ch = /bits/ 8 <0x08 0x09>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@5 { + reg = <0x05>; + fan-tach-ch = /bits/ 8 <0x0A 0x0B>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@6 { + reg = <0x06>; + fan-tach-ch = /bits/ 8 <0x0C 0x0D>; + cooling-levels = /bits/ 8 <127 255>; + }; + fan@7 { + reg = <0x07>; + fan-tach-ch = /bits/ 8 <0x0E 0x0F>; + cooling-levels = /bits/ 8 <127 255>; + }; + }; + + peci: peci-bus@100000 { + cmd-timeout-ms = <1000>; + pull-down = <0>; + host-neg-bit-rate = <15>; + status = "okay"; + intel-peci-dimmtemp@30 { + compatible = "intel,peci-client"; + reg = <0x30>; + status = "okay"; + }; + intel-peci-dimmtemp@31 { + compatible = "intel,peci-client"; + reg = <0x31>; + status = "okay"; + }; + }; + + spi0: spi@200000 { + cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + spi1: spi@201000 { + status = "okay"; + }; + }; + }; + + pinctrl: pinctrl@f0800000 { + pinctrl-names = "default"; + pinctrl-0 = < + /******* RunBMC inside Module pins *******/ + &gpio0ol_pins + &gpio1ol_pins + &gpio2ol_pins + &gpio3ol_pins + &gpio8o_pins + &gpio9ol_pins + &gpio12ol_pins + &gpio13ol_pins + &gpio14ol_pins + &gpio15ol_pins + &gpio37o_pins + &gpio38_pins + &gpio39_pins + &gpio94ol_pins + &gpio108ol_pins + &gpio109ol_pins + &gpio111ol_pins + &gpio112ol_pins + &gpio113ol_pins + &gpio208_pins + &gpio209ol_pins + &gpio210ol_pins + &gpio211ol_pins + &gpio212ol_pins + &gpio213ol_pins + &gpio214ol_pins + &gpio215ol_pins + &gpio216ol_pins + &gpio217ol_pins + /******* RunBMC outside Connector pins *******/ + &gpio5_pins + &gpio6_pins + &gpio7_pins + &gpio10_pins + &gpio11_pins + &gpio20_pins + &gpio21_pins + &gpio22o_pins + &gpio23_pins + &gpio24_pins + &gpio25_pins + &gpio30_pins + &gpio31_pins + &gpio40o_pins + &gpio59_pins + &gpio76_pins + &gpio77_pins + &gpio78o_pins + &gpio79_pins + &gpio82_pins + &gpio83_pins + &gpio84_pins + &gpio85o_pins + &gpio86ol_pins + &gpio87_pins + &gpio88_pins + &gpio89_pins + &gpio90_pins + &gpio93_pins + &gpio114o_pins + &gpio115_pins + &gpio120_pins + &gpio121_pins + &gpio122_pins + &gpio123_pins + &gpio124_pins + &gpio125_pins + &gpio126_pins + &gpio127o_pins + &gpio136_pins + &gpio137_pins + &gpio138_pins + &gpio139_pins + &gpio140_pins + &gpio141_pins + &gpio142_pins + &gpio143_pins + &gpio144_pins + &gpio146_pins + &gpio145_pins + &gpio147_pins + &gpio153o_pins + &gpio155_pins + &gpio160o_pins + &gpio169o_pins + &gpio188o_pins + &gpio189_pins + &gpio196_pins + &gpio197_pins + &gpio198o_pins + &gpio199o_pins + &gpio200_pins + &gpio202_pins + &gpio203o_pins + &gpio224_pins + &gpio225ol_pins + &gpio226ol_pins + &gpio227ol_pins + &gpio228o_pins + &gpio229o_pins + &gpio230_pins + &gpio231o_pins + &ddc_pins + &wdog1_pins + &wdog2_pins + >; + }; + + leds { + compatible = "gpio-leds"; + heartbeat { + label = "heartbeat"; + gpios = <&gpio3 14 1>; + }; + + identify { + label = "identify"; + gpios = <&gpio3 15 1>; + }; + }; + + jtag { + compatible = "nuvoton,npcm750-jtag"; + enable_pspi_jtag = <1>; + pspi-index = <2>; + tck { + label = "tck"; + gpios = <&gpio0 19 0>; /* gpio19 */ + regbase = <0xf0010000 0x1000>; + }; + + tdi { + label = "tdi"; + gpios = <&gpio0 18 0>; /* gpio18 */ + regbase = <0xf0010000 0x1000>; + }; + + tdo { + label = "tdo"; + gpios = <&gpio0 17 0>; /* gpio17 */ + regbase = <0xf0010000 0x1000>; + }; + tms { + label = "tms"; + gpios = <&gpio0 16 0>; /* gpio16 */ + regbase = <0xf0010000 0x1000>; + }; + }; +}; + +&gcr { + serial_port_mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + + mux-reg-masks = <0x38 0x07>; + idle-states = <6>; + }; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi index 6ac340533587..14b3d5b1206f 100644 --- a/arch/arm/boot/dts/nuvoton-npcm750.dtsi +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -3,6 +3,7 @@ // Copyright 2018 Google, Inc. #include "nuvoton-common-npcm7xx.dtsi" +#include "nuvoton-npcm750-gpio.dtsi" / { #address-cells = <1>; @@ -17,7 +18,7 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; - clocks = <&clk 0>; + clocks = <&clk NPCM7XX_CLK_CPU>; clock-names = "clk_cpu"; reg = <0>; next-level-cache = <&l2>; @@ -26,19 +27,152 @@ cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; - clocks = <&clk 0>; + clocks = <&clk NPCM7XX_CLK_CPU>; clock-names = "clk_cpu"; reg = <1>; next-level-cache = <&l2>; }; }; + soc { timer@3fe600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x3fe600 0x20>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; - clocks = <&clk 5>; + clocks = <&clk NPCM7XX_CLK_AHB>; + }; + }; + + ahb { + gmac1: eth@f0804000 { + device_type = "network"; + compatible = "snps,dwmac"; + reg = <0xf0804000 0x2000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + ethernet = <1>; + clocks = <&clk_rg2refck>, <&clk NPCM7XX_CLK_AHB>; + clock-names = "stmmaceth", "clk_gmac"; + pinctrl-names = "default"; + pinctrl-0 = <&rg2_pins + &rg2mdio_pins>; + status = "disabled"; + }; + + emc1: eth@f0826000 { + device_type = "network"; + compatible = "nuvoton,npcm750-emc"; + reg = <0xf0826000 0x1000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_AHB>; + clock-names = "clk_emc"; + pinctrl-names = "default"; + pinctrl-0 = <&r2_pins + &r2err_pins + &r2md_pins>; + status = "disabled"; + }; + + udc0:udc@f0830000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0830000 0x1000 + 0xfffd0000 0x800>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc1:udc@f0831000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0831000 0x1000 + 0xfffd0800 0x800>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc2:udc@f0832000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0832000 0x1000 + 0xfffd1000 0x800>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc3:udc@f0833000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0833000 0x1000 + 0xfffd1800 0x800>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc4:udc@f0834000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0834000 0x1000 + 0xfffd2000 0x800>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc5:udc@f0835000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0835000 0x1000 + 0xfffd2800 0x800>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc6:udc@f0836000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0836000 0x1000 + 0xfffd3000 0x800>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc7:udc@f0837000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0837000 0x1000 + 0xfffd3800 0x800>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc8:udc@f0838000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0838000 0x1000 + 0xfffd4000 0x800>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; + }; + + udc9:udc@f0839000 { + compatible = "nuvoton,npcm750-udc"; + reg = <0xf0839000 0x1000 + 0xfffd4800 0x800>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + clocks = <&clk NPCM7XX_CLK_SU>; + clock-names = "clk_usb_bridge"; }; }; }; diff --git a/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi b/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi new file mode 100644 index 000000000000..05101a38c5bd --- /dev/null +++ b/arch/arm/boot/dts/openbmc-flash-layout-128.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ + +partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + u-boot@0 { + reg = <0x0 0xe0000>; // 896KB + label = "u-boot"; + }; + + u-boot-env@e0000 { + reg = <0xe0000 0x20000>; // 128KB + label = "u-boot-env"; + }; + + kernel@100000 { + reg = <0x100000 0x900000>; // 9MB + label = "kernel"; + }; + + rofs@a00000 { + reg = <0xa00000 0x5600000>; // 86MB + label = "rofs"; + }; + + rwfs@6000000 { + reg = <0x6000000 0x2000000>; // 32MB + label = "rwfs"; + }; +}; diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig index 019828d7b251..9cd514b7c1e0 100644 --- a/arch/arm/configs/aspeed_g4_defconfig +++ b/arch/arm/configs/aspeed_g4_defconfig @@ -3,6 +3,8 @@ CONFIG_KERNEL_XZ=y CONFIG_SYSVIPC=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 @@ -20,29 +22,26 @@ CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_JUMP_LABEL=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_GCC_PLUGINS=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEBUG_FS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_MQ_IOSCHED_DEADLINE is not set -# CONFIG_MQ_IOSCHED_KYBER is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_ASPEED=y CONFIG_MACH_ASPEED_G4=y CONFIG_VMSPLIT_2G=y CONFIG_AEABI=y -# CONFIG_COMPACTION is not set CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_SECCOMP=y # CONFIG_ATAGS is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 -CONFIG_ARM_APPENDED_DTB=y -CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_KEXEC=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_JUMP_LABEL=y +CONFIG_STRICT_KERNEL_RWX=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPACTION is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=y @@ -50,19 +49,20 @@ CONFIG_UNIX=y CONFIG_UNIX_DIAG=y CONFIG_INET=y CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_ADVANCED is not set CONFIG_VLAN_8021Q=y CONFIG_NET_NCSI=y -CONFIG_BPF_STREAM_PARSER=y # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -77,6 +77,7 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y CONFIG_EEPROM_AT24=y CONFIG_NETDEVICES=y CONFIG_NETCONSOLE=y @@ -98,6 +99,7 @@ CONFIG_FTGMAC100=y # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set @@ -140,7 +142,6 @@ CONFIG_ASPEED_BT_IPMI_BMC=y CONFIG_HW_RANDOM_TIMERIOMEM=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_ASPEED=y @@ -155,6 +156,10 @@ CONFIG_SENSORS_ASPEED=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_SENSORS_LM75=y CONFIG_SENSORS_NCT7904=y +CONFIG_SENSORS_OCC_P8_I2C=y +CONFIG_SENSORS_OCC_P9_SBE=y +CONFIG_SENSORS_PECI_CPUTEMP=y +CONFIG_SENSORS_PECI_DIMMTEMP=y CONFIG_PMBUS=y CONFIG_SENSORS_ADM1275=y CONFIG_SENSORS_IBM_CFFPS=y @@ -171,6 +176,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_V4L_PLATFORM_DRIVERS=y CONFIG_VIDEO_ASPEED=y CONFIG_DRM=y +CONFIG_DRM_ASPEED_GFX=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_DYNAMIC_MINORS=y @@ -204,6 +210,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_EDAC=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_PCF8523=y @@ -218,13 +225,16 @@ CONFIG_IIO=y CONFIG_ASPEED_ADC=y CONFIG_MAX1363=y CONFIG_BMP280=y +CONFIG_RAS=y CONFIG_FSI=y CONFIG_FSI_MASTER_GPIO=y CONFIG_FSI_MASTER_HUB=y CONFIG_FSI_MASTER_AST_CF=y CONFIG_FSI_SCOM=y CONFIG_FSI_SBEFIFO=y -CONFIG_FIRMWARE_MEMMAP=y +CONFIG_FSI_OCC=y +CONFIG_PECI=y +CONFIG_PECI_ASPEED=y CONFIG_FANOTIFY=y CONFIG_OVERLAY_FS=y CONFIG_TMPFS=y @@ -237,6 +247,16 @@ CONFIG_SQUASHFS=y CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_ZSTD=y # CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_USER_API_HASH=y +# CONFIG_CRYPTO_HW is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_SPARC is not set CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_INFO=y @@ -255,14 +275,3 @@ CONFIG_FUNCTION_TRACER=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_DEBUG_WX=y CONFIG_DEBUG_USER=y -CONFIG_HARDENED_USERCOPY=y -CONFIG_FORTIFY_SOURCE=y -# CONFIG_CRYPTO_ECHAINIV is not set -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_USER_API_HASH=y -# CONFIG_CRYPTO_HW is not set -# CONFIG_XZ_DEC_X86 is not set -# CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_IA64 is not set -# CONFIG_XZ_DEC_SPARC is not set diff --git a/arch/arm/configs/aspeed_g5_defconfig b/arch/arm/configs/aspeed_g5_defconfig index 28fe392c7dfa..0fbb9335679b 100644 --- a/arch/arm/configs/aspeed_g5_defconfig +++ b/arch/arm/configs/aspeed_g5_defconfig @@ -3,6 +3,8 @@ CONFIG_KERNEL_XZ=y CONFIG_SYSVIPC=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_PSI=y +CONFIG_PSI_DEFAULT_DISABLED=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=16 @@ -20,29 +22,33 @@ CONFIG_PERF_EVENTS=y # CONFIG_COMPAT_BRK is not set CONFIG_SLAB=y CONFIG_SLAB_FREELIST_RANDOM=y -CONFIG_JUMP_LABEL=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_GCC_PLUGINS=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_BLK_DEBUG_FS is not set -# CONFIG_IOSCHED_DEADLINE is not set -# CONFIG_MQ_IOSCHED_DEADLINE is not set -# CONFIG_MQ_IOSCHED_KYBER is not set CONFIG_ARCH_MULTI_V6=y -# CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_ASPEED=y CONFIG_MACH_ASPEED_G5=y +CONFIG_MACH_ASPEED_G6=y # CONFIG_CACHE_L2X0 is not set +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set CONFIG_VMSPLIT_2G=y -# CONFIG_COMPACTION is not set +CONFIG_NR_CPUS=2 +CONFIG_HIGHMEM=y CONFIG_UACCESS_WITH_MEMCPY=y CONFIG_SECCOMP=y # CONFIG_ATAGS is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 CONFIG_KEXEC=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_JUMP_LABEL=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_SUSPEND is not set +# CONFIG_COMPACTION is not set CONFIG_NET=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=y @@ -50,19 +56,20 @@ CONFIG_UNIX=y CONFIG_UNIX_DIAG=y CONFIG_INET=y CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y CONFIG_SYN_COOKIES=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set # CONFIG_INET_DIAG is not set -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_ADVANCED is not set CONFIG_VLAN_8021Q=y CONFIG_NET_NCSI=y -CONFIG_BPF_STREAM_PARSER=y # CONFIG_WIRELESS is not set CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y @@ -77,7 +84,11 @@ CONFIG_MTD_UBI=y CONFIG_MTD_UBI_FASTMAP=y CONFIG_MTD_UBI_BLOCK=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y CONFIG_EEPROM_AT24=y +CONFIG_MD=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_VERITY=y CONFIG_NETDEVICES=y CONFIG_NETCONSOLE=y # CONFIG_NET_VENDOR_ALACRITECH is not set @@ -98,6 +109,7 @@ CONFIG_FTGMAC100=y # CONFIG_NET_VENDOR_MARVELL is not set # CONFIG_NET_VENDOR_MELLANOX is not set # CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set # CONFIG_NET_VENDOR_MICROSEMI is not set # CONFIG_NET_VENDOR_NATSEMI is not set # CONFIG_NET_VENDOR_NETRONOME is not set @@ -134,31 +146,41 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=6 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_ASPEED_VUART=y CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_ASPEED_KCS_IPMI_BMC=y CONFIG_ASPEED_BT_IPMI_BMC=y CONFIG_HW_RANDOM_TIMERIOMEM=y # CONFIG_I2C_COMPAT is not set CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA9541=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_ASPEED=y CONFIG_I2C_FSI=y +CONFIG_SPI=y CONFIG_GPIOLIB=y CONFIG_GPIO_SYSFS=y CONFIG_GPIO_ASPEED=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y CONFIG_W1=y CONFIG_W1_MASTER_GPIO=y CONFIG_W1_SLAVE_THERM=y +CONFIG_SENSORS_ADT7475=y CONFIG_SENSORS_ASPEED=y CONFIG_SENSORS_IIO_HWMON=y CONFIG_SENSORS_LM75=y CONFIG_SENSORS_NCT7904=y +CONFIG_SENSORS_OCC_P8_I2C=y +CONFIG_SENSORS_OCC_P9_SBE=y +CONFIG_SENSORS_PECI_CPUTEMP=y +CONFIG_SENSORS_PECI_DIMMTEMP=y CONFIG_PMBUS=y CONFIG_SENSORS_ADM1275=y CONFIG_SENSORS_IBM_CFFPS=y CONFIG_SENSORS_IR35221=y +CONFIG_SENSORS_IR38064=y +CONFIG_SENSORS_ISL68137=y CONFIG_SENSORS_LM25066=y CONFIG_SENSORS_MAX31785=y CONFIG_SENSORS_UCD9000=y @@ -179,22 +201,14 @@ CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_GADGET=y -CONFIG_U_SERIAL_CONSOLE=y CONFIG_USB_ASPEED_VHUB=y CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_SERIAL=y -CONFIG_USB_CONFIGFS_ACM=y -CONFIG_USB_CONFIGFS_OBEX=y -CONFIG_USB_CONFIGFS_NCM=y -CONFIG_USB_CONFIGFS_ECM=y -CONFIG_USB_CONFIGFS_ECM_SUBSET=y -CONFIG_USB_CONFIGFS_RNDIS=y -CONFIG_USB_CONFIGFS_EEM=y CONFIG_USB_CONFIGFS_MASS_STORAGE=y -CONFIG_USB_CONFIGFS_F_LB_SS=y -CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_HID=y -CONFIG_USB_CONFIGFS_F_PRINTER=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ASPEED=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=y @@ -206,6 +220,7 @@ CONFIG_LEDS_TRIGGER_TIMER=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_EDAC=y +# CONFIG_EDAC_LEGACY_SYSFS is not set CONFIG_EDAC_ASPEED=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_DS1307=y @@ -221,14 +236,19 @@ CONFIG_IIO=y CONFIG_ASPEED_ADC=y CONFIG_MAX1363=y CONFIG_BMP280=y +CONFIG_DPS310=y CONFIG_RAS=y CONFIG_FSI=y CONFIG_FSI_MASTER_GPIO=y CONFIG_FSI_MASTER_HUB=y CONFIG_FSI_MASTER_AST_CF=y +CONFIG_FSI_MASTER_ASPEED=y CONFIG_FSI_SCOM=y CONFIG_FSI_SBEFIFO=y -CONFIG_FIRMWARE_MEMMAP=y +CONFIG_FSI_OCC=y +CONFIG_PECI=y +CONFIG_PECI_ASPEED=y +CONFIG_EXT4_FS=y CONFIG_FANOTIFY=y CONFIG_OVERLAY_FS=y CONFIG_TMPFS=y @@ -241,6 +261,16 @@ CONFIG_SQUASHFS=y CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_ZSTD=y # CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_USER_API_HASH=y +# CONFIG_CRYPTO_HW is not set +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_SPARC is not set CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_INFO=y @@ -259,14 +289,3 @@ CONFIG_FUNCTION_TRACER=y # CONFIG_RUNTIME_TESTING_MENU is not set CONFIG_DEBUG_WX=y CONFIG_DEBUG_USER=y -CONFIG_HARDENED_USERCOPY=y -CONFIG_FORTIFY_SOURCE=y -# CONFIG_CRYPTO_ECHAINIV is not set -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_USER_API_HASH=y -# CONFIG_CRYPTO_HW is not set -# CONFIG_XZ_DEC_X86 is not set -# CONFIG_XZ_DEC_POWERPC is not set -# CONFIG_XZ_DEC_IA64 is not set -# CONFIG_XZ_DEC_SPARC is not set diff --git a/arch/arm/configs/npcm7xx_defconfig b/arch/arm/configs/npcm7xx_defconfig new file mode 100644 index 000000000000..62aaffdba4dd --- /dev/null +++ b/arch/arm/configs/npcm7xx_defconfig @@ -0,0 +1,127 @@ +CONFIG_KERNEL_XZ=y +CONFIG_SYSVIPC=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_LOG_BUF_SHIFT=21 +CONFIG_CGROUPS=y +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_ARCH_NPCM=y +CONFIG_ARCH_NPCM7XX=y +CONFIG_SMP=y +CONFIG_VMSPLIT_3G_OPT=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_MTD=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_RAM=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SPI_NOR=y +CONFIG_SPI_NPCM_FIU=y +CONFIG_OF_OVERLAY=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=1 +CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_NPCM7XX_LPC_BPC=y +CONFIG_NPCM7XX_PCI_MBOX=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_NETDEVICES=y +CONFIG_NPCM7XX_EMC_ETH=y +CONFIG_STMMAC_ETH=y +CONFIG_BROADCOM_PHY=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_NPCM750_OTP=y +CONFIG_NPCM750_OTP_WRITE_ENABLE=y +CONFIG_NPCM7XX_KCS_IPMI_BMC=y +CONFIG_HW_RANDOM=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_NPCM7XX=y +CONFIG_I2C_SLAVE_EEPROM=y +CONFIG_SPI=y +CONFIG_SPI_NPCM_PSPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_SENSORS_LM75=y +CONFIG_SENSORS_NPCM7XX=y +CONFIG_SENSORS_TMP102=y +CONFIG_WATCHDOG=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_NPCM750_VCD=y +CONFIG_NPCM750_ECE=y +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_NPCMX50_USB2=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_EDM_KBD_MOUSE=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_NPCM750=y +CONFIG_IIO=y +CONFIG_NPCM_ADC=y +CONFIG_IIO_MUX=y +CONFIG_MUX_MMIO=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=y +CONFIG_CIFS_XATTR=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +CONFIG_READABLE_ASM=y +CONFIG_DEBUG_SECTION_MISMATCH=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_FUNCTION_TRACER=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_DEV_NPCMX50=y +CONFIG_ARM_CRYPTO=y +CONFIG_PECI=y +CONFIG_PECI_NPCM=y +CONFIG_MFD_INTEL_PECI_CLIENT=y +CONFIG_SENSORS_PECI_CPUTEMP=y +CONFIG_SENSORS_PECI_DIMMTEMP=y diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index a15c3a291386..693cbddae3d8 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -1,11 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only menuconfig ARCH_ASPEED bool "Aspeed BMC architectures" - depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 + depends on ARCH_MULTI_V5 || ARCH_MULTI_V6 || ARCH_MULTI_V7 select SRAM select WATCHDOG select ASPEED_WATCHDOG - select FTTMR010_TIMER select MFD_SYSCON select PINCTRL help @@ -18,6 +17,7 @@ config MACH_ASPEED_G4 depends on ARCH_MULTI_V5 select CPU_ARM926T select PINCTRL_ASPEED_G4 + select FTTMR010_TIMER help Say yes if you intend to run on an Aspeed ast2400 or similar fourth generation BMCs, such as those used by OpenPower Power8 @@ -25,11 +25,24 @@ config MACH_ASPEED_G4 config MACH_ASPEED_G5 bool "Aspeed SoC 5th Generation" + # This implies ARMv6K which covers the ARM1176 depends on ARCH_MULTI_V6 - select CPU_V6 select PINCTRL_ASPEED_G5 + select FTTMR010_TIMER help Say yes if you intend to run on an Aspeed ast2500 or similar fifth generation Aspeed BMCs. +config MACH_ASPEED_G6 + bool "Aspeed SoC 6th Generation" + depends on ARCH_MULTI_V7 + select CPU_V7 + select PINCTRL_ASPEED_G6 + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + select HAVE_SMP + help + Say yes if you intend to run on an Aspeed ast2600 or similar + sixth generation Aspeed BMCs. + endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile new file mode 100644 index 000000000000..1951b3317a76 --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) ASPEED Technology Inc. +# Copyright IBM Corp. + +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-aspeed/platsmp.c b/arch/arm/mach-aspeed/platsmp.c new file mode 100644 index 000000000000..2324becf7991 --- /dev/null +++ b/arch/arm/mach-aspeed/platsmp.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (C) ASPEED Technology Inc. +// Copyright IBM Corp. + +#include <linux/of_address.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/smp.h> + +#define BOOT_ADDR 0x00 +#define BOOT_SIG 0x04 + +static struct device_node *secboot_node; + +static int aspeed_g6_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + void __iomem *base; + + base = of_iomap(secboot_node, 0); + if (!base) { + pr_err("could not map the secondary boot base!"); + return -ENODEV; + } + + writel_relaxed(0, base + BOOT_ADDR); + writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); + writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); + + dsb_sev(); + + iounmap(base); + + return 0; +} + +static void __init aspeed_g6_smp_prepare_cpus(unsigned int max_cpus) +{ + void __iomem *base; + + secboot_node = of_find_compatible_node(NULL, NULL, "aspeed,ast2600-smpmem"); + if (!secboot_node) { + pr_err("secboot device node found!!\n"); + return; + } + + base = of_iomap(secboot_node, 0); + if (!base) { + pr_err("could not map the secondary boot base!"); + return; + } + __raw_writel(0xBADABABA, base + BOOT_SIG); + + iounmap(base); +} + +static const struct smp_operations aspeed_smp_ops __initconst = { + .smp_prepare_cpus = aspeed_g6_smp_prepare_cpus, + .smp_boot_secondary = aspeed_g6_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(aspeed_smp, "aspeed,ast2600-smp", &aspeed_smp_ops); diff --git a/drivers/Kconfig b/drivers/Kconfig index 61cf4ea2c229..92f4a9bb83f1 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -230,4 +230,6 @@ source "drivers/interconnect/Kconfig" source "drivers/counter/Kconfig" +source "drivers/peci/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 6d37564e783c..47cad1b9f992 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -187,3 +187,4 @@ obj-$(CONFIG_SIOX) += siox/ obj-$(CONFIG_GNSS) += gnss/ obj-$(CONFIG_INTERCONNECT) += interconnect/ obj-$(CONFIG_COUNTER) += counter/ +obj-$(CONFIG_PECI) += peci/ diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index 3e866885a405..aa460e01002b 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -16,6 +16,15 @@ config DEVMEM memory. When in doubt, say "Y". +config DEVMEM_BOOTPARAM + bool "mem.devmem boot parameter" + depends on DEVMEM + default n + help + This option adds a 'mem.devmem' kernel parameter which activates + the /dev/mem device when enabled. + When in doubt, say "N". + config DEVKMEM bool "/dev/kmem virtual device support" # On arm64, VMALLOC_START < PAGE_OFFSET, which confuses kmem read/write diff --git a/drivers/char/ipmi/bt-bmc.c b/drivers/char/ipmi/bt-bmc.c index 40b9927c072c..0e600449931b 100644 --- a/drivers/char/ipmi/bt-bmc.c +++ b/drivers/char/ipmi/bt-bmc.c @@ -513,6 +513,7 @@ static int bt_bmc_remove(struct platform_device *pdev) static const struct of_device_id bt_bmc_match[] = { { .compatible = "aspeed,ast2400-ibt-bmc" }, { .compatible = "aspeed,ast2500-ibt-bmc" }, + { .compatible = "aspeed,ast2600-ibt-bmc" }, { }, }; diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c b/drivers/char/ipmi/kcs_bmc_aspeed.c index 3c955946e647..a0a8bb89c9b3 100644 --- a/drivers/char/ipmi/kcs_bmc_aspeed.c +++ b/drivers/char/ipmi/kcs_bmc_aspeed.c @@ -301,6 +301,7 @@ static int aspeed_kcs_remove(struct platform_device *pdev) static const struct of_device_id ast_kcs_bmc_match[] = { { .compatible = "aspeed,ast2400-kcs-bmc" }, { .compatible = "aspeed,ast2500-kcs-bmc" }, + { .compatible = "aspeed,ast2600-kcs-bmc" }, { } }; MODULE_DEVICE_TABLE(of, ast_kcs_bmc_match); diff --git a/drivers/char/mem.c b/drivers/char/mem.c index 9eb564c002f6..e11d47e23f6a 100644 --- a/drivers/char/mem.c +++ b/drivers/char/mem.c @@ -10,6 +10,7 @@ */ #include <linux/mm.h> +#include <linux/moduleparam.h> #include <linux/miscdevice.h> #include <linux/slab.h> #include <linux/vmalloc.h> @@ -36,6 +37,7 @@ # include <linux/efi.h> #endif +#define DEVMEM_MINOR 1 #define DEVPORT_MINOR 4 static inline unsigned long size_inside_page(unsigned long start, @@ -934,6 +936,12 @@ static char *mem_devnode(struct device *dev, umode_t *mode) return NULL; } +#ifdef CONFIG_DEVMEM_BOOTPARAM +static bool devmem; +module_param(devmem, bool, 0444); +MODULE_PARM_DESC(devmem, "kernel parameter to activate /dev/mem"); +#endif + static struct class *mem_class; static int __init chr_dev_init(void) @@ -952,6 +960,10 @@ static int __init chr_dev_init(void) if (!devlist[minor].name) continue; +#ifdef CONFIG_DEVMEM_BOOTPARAM + if (minor == DEVMEM_MINOR && !devmem) + continue; +#endif /* * Create /dev/port? */ diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 0cad76021297..0138fb14e6f8 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_ARCH_EFM32) += clk-efm32gg.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o +obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c index 42b4df6ba249..9bd5155598d6 100644 --- a/drivers/clk/clk-aspeed.c +++ b/drivers/clk/clk-aspeed.c @@ -1,20 +1,20 @@ // SPDX-License-Identifier: GPL-2.0+ +// Copyright IBM Corp #define pr_fmt(fmt) "clk-aspeed: " fmt -#include <linux/clk-provider.h> #include <linux/mfd/syscon.h> #include <linux/of_address.h> #include <linux/of_device.h> #include <linux/platform_device.h> #include <linux/regmap.h> -#include <linux/reset-controller.h> #include <linux/slab.h> -#include <linux/spinlock.h> #include <dt-bindings/clock/aspeed-clock.h> -#define ASPEED_NUM_CLKS 36 +#include "clk-aspeed.h" + +#define ASPEED_NUM_CLKS 38 #define ASPEED_RESET2_OFFSET 32 @@ -28,6 +28,7 @@ #define AST2400_HPLL_BYPASS_EN BIT(17) #define ASPEED_MISC_CTRL 0x2c #define UART_DIV13_EN BIT(12) +#define ASPEED_MAC_CLK_DLY 0x48 #define ASPEED_STRAP 0x70 #define CLKIN_25MHZ_EN BIT(23) #define AST2400_CLK_SOURCE_SEL BIT(18) @@ -42,48 +43,6 @@ static struct clk_hw_onecell_data *aspeed_clk_data; static void __iomem *scu_base; -/** - * struct aspeed_gate_data - Aspeed gated clocks - * @clock_idx: bit used to gate this clock in the clock register - * @reset_idx: bit used to reset this IP in the reset register. -1 if no - * reset is required when enabling the clock - * @name: the clock name - * @parent_name: the name of the parent clock - * @flags: standard clock framework flags - */ -struct aspeed_gate_data { - u8 clock_idx; - s8 reset_idx; - const char *name; - const char *parent_name; - unsigned long flags; -}; - -/** - * struct aspeed_clk_gate - Aspeed specific clk_gate structure - * @hw: handle between common and hardware-specific interfaces - * @reg: register controlling gate - * @clock_idx: bit used to gate this clock in the clock register - * @reset_idx: bit used to reset this IP in the reset register. -1 if no - * reset is required when enabling the clock - * @flags: hardware-specific flags - * @lock: register lock - * - * Some of the clocks in the Aspeed SoC must be put in reset before enabling. - * This modified version of clk_gate allows an optional reset bit to be - * specified. - */ -struct aspeed_clk_gate { - struct clk_hw hw; - struct regmap *map; - u8 clock_idx; - s8 reset_idx; - u8 flags; - spinlock_t *lock; -}; - -#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) - /* TODO: ask Aspeed about the actual parent data */ static const struct aspeed_gate_data aspeed_gates[] = { /* clk rst name parent flags */ @@ -208,13 +167,6 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) mult, div); } -struct aspeed_clk_soc_data { - const struct clk_div_table *div_table; - const struct clk_div_table *eclk_div_table; - const struct clk_div_table *mac_div_table; - struct clk_hw *(*calc_pll)(const char *name, u32 val); -}; - static const struct aspeed_clk_soc_data ast2500_data = { .div_table = ast2500_div_table, .eclk_div_table = ast2500_eclk_div_table, @@ -315,18 +267,6 @@ static const struct clk_ops aspeed_clk_gate_ops = { .is_enabled = aspeed_clk_is_enabled, }; -/** - * struct aspeed_reset - Aspeed reset controller - * @map: regmap to access the containing system controller - * @rcdev: reset controller device - */ -struct aspeed_reset { - struct regmap *map; - struct reset_controller_dev rcdev; -}; - -#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) - static const u8 aspeed_resets[] = { /* SCU04 resets */ [ASPEED_RESET_XDMA] = 25, @@ -500,9 +440,14 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; - /* SD/SDIO clock divider (TODO: There's a gate too) */ - hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, - scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, + /* SD/SDIO clock divider and gate */ + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, + scu_base + ASPEED_CLK_SELECTION, 15, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", + 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, soc_data->div_table, &aspeed_clk_lock); if (IS_ERR(hw)) @@ -518,6 +463,30 @@ static int aspeed_clk_probe(struct platform_device *pdev) return PTR_ERR(hw); aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; + if (of_device_is_compatible(pdev->dev.of_node, "aspeed,ast2500-scu")) { + /* RMII 50MHz RCLK */ + hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, + 50000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + /* RMII1 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 29, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_GATE_MAC1RCLK] = hw; + + /* RMII2 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, + scu_base + ASPEED_MAC_CLK_DLY, 30, 0, + &aspeed_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_clk_data->hws[ASPEED_CLK_GATE_MAC2RCLK] = hw; + } + /* LPC Host (LHCLK) clock divider */ hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, diff --git a/drivers/clk/clk-aspeed.h b/drivers/clk/clk-aspeed.h new file mode 100644 index 000000000000..5296b15b1c88 --- /dev/null +++ b/drivers/clk/clk-aspeed.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Structures used by ASPEED clock drivers + * + * Copyright 2019 IBM Corp. + */ + +#include <linux/clk-provider.h> +#include <linux/kernel.h> +#include <linux/reset-controller.h> +#include <linux/spinlock.h> + +struct clk_div_table; +struct regmap; + +/** + * struct aspeed_gate_data - Aspeed gated clocks + * @clock_idx: bit used to gate this clock in the clock register + * @reset_idx: bit used to reset this IP in the reset register. -1 if no + * reset is required when enabling the clock + * @name: the clock name + * @parent_name: the name of the parent clock + * @flags: standard clock framework flags + */ +struct aspeed_gate_data { + u8 clock_idx; + s8 reset_idx; + const char *name; + const char *parent_name; + unsigned long flags; +}; + +/** + * struct aspeed_clk_gate - Aspeed specific clk_gate structure + * @hw: handle between common and hardware-specific interfaces + * @reg: register controlling gate + * @clock_idx: bit used to gate this clock in the clock register + * @reset_idx: bit used to reset this IP in the reset register. -1 if no + * reset is required when enabling the clock + * @flags: hardware-specific flags + * @lock: register lock + * + * Some of the clocks in the Aspeed SoC must be put in reset before enabling. + * This modified version of clk_gate allows an optional reset bit to be + * specified. + */ +struct aspeed_clk_gate { + struct clk_hw hw; + struct regmap *map; + u8 clock_idx; + s8 reset_idx; + u8 flags; + spinlock_t *lock; +}; + +#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) + +/** + * struct aspeed_reset - Aspeed reset controller + * @map: regmap to access the containing system controller + * @rcdev: reset controller device + */ +struct aspeed_reset { + struct regmap *map; + struct reset_controller_dev rcdev; +}; + +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) + +/** + * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information + * @div_table: Common divider lookup table + * @eclk_div_table: Divider lookup table for ECLK + * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks + * @calc_pll: Callback to maculate common PLL settings + */ +struct aspeed_clk_soc_data { + const struct clk_div_table *div_table; + const struct clk_div_table *eclk_div_table; + const struct clk_div_table *mac_div_table; + struct clk_hw *(*calc_pll)(const char *name, u32 val); +}; diff --git a/drivers/clk/clk-ast2600.c b/drivers/clk/clk-ast2600.c new file mode 100644 index 000000000000..8201d65018b9 --- /dev/null +++ b/drivers/clk/clk-ast2600.c @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright IBM Corp +// Copyright ASPEED Technology + +#define pr_fmt(fmt) "clk-ast2600: " fmt + +#include <linux/mfd/syscon.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/ast2600-clock.h> + +#include "clk-aspeed.h" + +#define ASPEED_G6_NUM_CLKS 71 + +#define ASPEED_G6_SILICON_REV 0x004 + +#define ASPEED_G6_RESET_CTRL 0x040 +#define ASPEED_G6_RESET_CTRL2 0x050 + +#define ASPEED_G6_CLK_STOP_CTRL 0x080 +#define ASPEED_G6_CLK_STOP_CTRL2 0x090 + +#define ASPEED_G6_MISC_CTRL 0x0C0 +#define UART_DIV13_EN BIT(12) + +#define ASPEED_G6_CLK_SELECTION1 0x300 +#define ASPEED_G6_CLK_SELECTION2 0x304 +#define ASPEED_G6_CLK_SELECTION4 0x310 + +#define ASPEED_HPLL_PARAM 0x200 +#define ASPEED_APLL_PARAM 0x210 +#define ASPEED_MPLL_PARAM 0x220 +#define ASPEED_EPLL_PARAM 0x240 +#define ASPEED_DPLL_PARAM 0x260 + +#define ASPEED_G6_STRAP1 0x500 + +#define ASPEED_MAC12_CLK_DLY 0x340 +#define ASPEED_MAC34_CLK_DLY 0x350 + +/* Globally visible clocks */ +static DEFINE_SPINLOCK(aspeed_g6_clk_lock); + +/* Keeps track of all clocks */ +static struct clk_hw_onecell_data *aspeed_g6_clk_data; + +static void __iomem *scu_g6_base; + +/* + * Clocks marked with CLK_IS_CRITICAL: + * + * ref0 and ref1 are essential for the SoC to operate + * mpll is required if SDRAM is used + */ +static const struct aspeed_gate_data aspeed_g6_gates[] = { + /* clk rst name parent flags */ + [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ + [ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ + [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ + /* vclk parent - dclk/d1clk/hclk/mclk */ + [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ + [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */ + /* From dpll */ + [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ + [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL }, + [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ + /* Reserved 8 */ + [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ + /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */ + [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */ + /* Reserved 11/12 */ + [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ + [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ + [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ + /* Reserved 16/19 */ + [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */ + [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */ + /* Reserved 22/23 */ + [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */ + [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */ + /* Reserved 26 */ + [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */ + /* Reserved 28/29/30 */ + [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */ + [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ + [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL }, + /* Reserved 35 */ + [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ + [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ + /* Reserved 38 RSA: no longer used */ + /* Reserved 39 */ + [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */ + [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */ + [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */ + [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */ + [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */ + [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */ + [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */ + [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */ + [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ + [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ + [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ + [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ + [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */ + [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */ + [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */ + [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */ + [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */ + [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */ + [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */ + [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */ + [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */ + [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */ + [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */ +}; + +static const char * const eclk_parent_names[] = { "mpll", "hpll", "dpll" }; + +static const struct clk_div_table ast2600_eclk_div_table[] = { + { 0x0, 2 }, + { 0x1, 2 }, + { 0x2, 3 }, + { 0x3, 4 }, + { 0x4, 5 }, + { 0x5, 6 }, + { 0x6, 7 }, + { 0x7, 8 }, + { 0 } +}; + +static const struct clk_div_table ast2600_mac_div_table[] = { + { 0x0, 4 }, + { 0x1, 4 }, + { 0x2, 6 }, + { 0x3, 8 }, + { 0x4, 10 }, + { 0x5, 12 }, + { 0x6, 14 }, + { 0x7, 16 }, + { 0 } +}; + +static const struct clk_div_table ast2600_div_table[] = { + { 0x0, 4 }, + { 0x1, 8 }, + { 0x2, 12 }, + { 0x3, 16 }, + { 0x4, 20 }, + { 0x5, 24 }, + { 0x6, 28 }, + { 0x7, 32 }, + { 0 } +}; + +/* For hpll/dpll/epll/mpll */ +static struct clk_hw *ast2600_calc_pll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & BIT(24)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */ + u32 m = val & 0x1fff; + u32 n = (val >> 13) & 0x3f; + u32 p = (val >> 19) & 0xf; + mult = (m + 1) / (n + 1); + div = (p + 1); + } + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +}; + +static struct clk_hw *ast2600_calc_apll(const char *name, u32 val) +{ + unsigned int mult, div; + + if (val & BIT(20)) { + /* Pass through mode */ + mult = div = 1; + } else { + /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */ + u32 m = (val >> 5) & 0x3f; + u32 od = (val >> 4) & 0x1; + u32 n = val & 0xf; + + mult = (2 - od) * (m + 2); + div = n + 1; + } + return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, + mult, div); +}; + +static u32 get_bit(u8 idx) +{ + return BIT(idx % 32); +} + +static u32 get_reset_reg(struct aspeed_clk_gate *gate) +{ + if (gate->reset_idx < 32) + return ASPEED_G6_RESET_CTRL; + + return ASPEED_G6_RESET_CTRL2; +} + +static u32 get_clock_reg(struct aspeed_clk_gate *gate) +{ + if (gate->clock_idx < 32) + return ASPEED_G6_CLK_STOP_CTRL; + + return ASPEED_G6_CLK_STOP_CTRL2; +} + +static int aspeed_g6_clk_is_enabled(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + u32 clk = get_bit(gate->clock_idx); + u32 rst = get_bit(gate->reset_idx); + u32 reg; + u32 enval; + + /* + * If the IP is in reset, treat the clock as not enabled, + * this happens with some clocks such as the USB one when + * coming from cold reset. Without this, aspeed_clk_enable() + * will fail to lift the reset. + */ + if (gate->reset_idx >= 0) { + regmap_read(gate->map, get_reset_reg(gate), ®); + + if (reg & rst) + return 0; + } + + regmap_read(gate->map, get_clock_reg(gate), ®); + + enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; + + return ((reg & clk) == enval) ? 1 : 0; +} + +static int aspeed_g6_clk_enable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = get_bit(gate->clock_idx); + u32 rst = get_bit(gate->reset_idx); + + spin_lock_irqsave(gate->lock, flags); + + if (aspeed_g6_clk_is_enabled(hw)) { + spin_unlock_irqrestore(gate->lock, flags); + return 0; + } + + if (gate->reset_idx >= 0) { + /* Put IP in reset */ + regmap_write(gate->map, get_reset_reg(gate), rst); + /* Delay 100us */ + udelay(100); + } + + /* Enable clock */ + if (gate->flags & CLK_GATE_SET_TO_DISABLE) { + /* Clock is clear to enable, so use set to clear register */ + regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk); + } else { + /* Clock is set to enable, so use write to set register */ + regmap_write(gate->map, get_clock_reg(gate), clk); + } + + if (gate->reset_idx >= 0) { + /* A delay of 10ms is specified by the ASPEED docs */ + mdelay(10); + /* Take IP out of reset */ + regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst); + } + + spin_unlock_irqrestore(gate->lock, flags); + + return 0; +} + +static void aspeed_g6_clk_disable(struct clk_hw *hw) +{ + struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); + unsigned long flags; + u32 clk = get_bit(gate->clock_idx); + + spin_lock_irqsave(gate->lock, flags); + + if (gate->flags & CLK_GATE_SET_TO_DISABLE) { + regmap_write(gate->map, get_clock_reg(gate), clk); + } else { + /* Use set to clear register */ + regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk); + } + + spin_unlock_irqrestore(gate->lock, flags); +} + +static const struct clk_ops aspeed_g6_clk_gate_ops = { + .enable = aspeed_g6_clk_enable, + .disable = aspeed_g6_clk_disable, + .is_enabled = aspeed_g6_clk_is_enabled, +}; + +static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = get_bit(id); + u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; + + /* Use set to clear register */ + return regmap_write(ar->map, reg + 0x04, rst); +} + +static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + u32 rst = get_bit(id); + u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; + + return regmap_write(ar->map, reg, rst); +} + +static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct aspeed_reset *ar = to_aspeed_reset(rcdev); + int ret; + u32 val; + u32 rst = get_bit(id); + u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL; + + ret = regmap_read(ar->map, reg, &val); + if (ret) + return ret; + + return !!(val & rst); +} + +static const struct reset_control_ops aspeed_g6_reset_ops = { + .assert = aspeed_g6_reset_assert, + .deassert = aspeed_g6_reset_deassert, + .status = aspeed_g6_reset_status, +}; + +static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev, + const char *name, const char *parent_name, unsigned long flags, + struct regmap *map, u8 clock_idx, u8 reset_idx, + u8 clk_gate_flags, spinlock_t *lock) +{ + struct aspeed_clk_gate *gate; + struct clk_init_data init; + struct clk_hw *hw; + int ret; + + gate = kzalloc(sizeof(*gate), GFP_KERNEL); + if (!gate) + return ERR_PTR(-ENOMEM); + + init.name = name; + init.ops = &aspeed_g6_clk_gate_ops; + init.flags = flags; + init.parent_names = parent_name ? &parent_name : NULL; + init.num_parents = parent_name ? 1 : 0; + + gate->map = map; + gate->clock_idx = clock_idx; + gate->reset_idx = reset_idx; + gate->flags = clk_gate_flags; + gate->lock = lock; + gate->hw.init = &init; + + hw = &gate->hw; + ret = clk_hw_register(dev, hw); + if (ret) { + kfree(gate); + hw = ERR_PTR(ret); + } + + return hw; +} + +static const char * const vclk_parent_names[] = { + "dpll", + "d1pll", + "hclk", + "mclk", +}; + +static const char * const d1clk_parent_names[] = { + "dpll", + "epll", + "usb-phy-40m", + "gpioc6_clkin", + "dp_phy_pll", +}; + +static int aspeed_g6_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct aspeed_reset *ar; + struct regmap *map; + struct clk_hw *hw; + u32 val, rate; + int i, ret; + + map = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(map)) { + dev_err(dev, "no syscon regmap\n"); + return PTR_ERR(map); + } + + ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); + if (!ar) + return -ENOMEM; + + ar->map = map; + + ar->rcdev.owner = THIS_MODULE; + ar->rcdev.nr_resets = 64; + ar->rcdev.ops = &aspeed_g6_reset_ops; + ar->rcdev.of_node = dev->of_node; + + ret = devm_reset_controller_register(dev, &ar->rcdev); + if (ret) { + dev_err(dev, "could not register reset controller\n"); + return ret; + } + + /* UART clock div13 setting */ + regmap_read(map, ASPEED_G6_MISC_CTRL, &val); + if (val & UART_DIV13_EN) + rate = 24000000 / 13; + else + rate = 24000000; + hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw; + + /* UART6~13 clock div13 setting */ + regmap_read(map, 0x80, &val); + if (val & BIT(31)) + rate = 24000000 / 13; + else + rate = 24000000; + hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw; + + /* EMMC ext clock divider */ + hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "hpll", 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 15, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + hw = clk_hw_register_divider_table(dev, "emmc_extclk", "emmc_extclk_gate", 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 12, 3, 0, + ast2600_div_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw; + + /* SD/SDIO clock divider and gate */ + hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", + 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0, + ast2600_div_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw; + + /* MAC1/2 RMII 50MHz RCLK */ + hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + /* MAC1/2 AHB bus clock divider */ + hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0, + ast2600_mac_div_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw; + + /* RMII1 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0, + scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC1RCLK] = hw; + + /* RMII2 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0, + scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC2RCLK] = hw; + + /* MAC1/2 RMII 50MHz RCLK */ + hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + /* MAC3/4 AHB bus clock divider */ + hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0, + scu_g6_base + 0x310, 24, 3, 0, + ast2600_mac_div_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw; + + /* RMII3 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0, + scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC3RCLK] = hw; + + /* RMII4 50MHz (RCLK) output enable */ + hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0, + scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_GATE_MAC4RCLK] = hw; + + /* LPC Host (LHCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, + ast2600_div_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw; + + /* gfx d1clk : use dp clk */ + regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10)); + /* SoC Display clock selection */ + hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names, + ARRAY_SIZE(d1clk_parent_names), 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw; + + /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */ + regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */ + + /* P-Bus (BCLK) clock divider */ + hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0, + ast2600_div_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw; + + /* Video Capture clock selection */ + hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names, + ARRAY_SIZE(vclk_parent_names), 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw; + + /* Video Engine clock divider */ + hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0, + scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0, + ast2600_eclk_div_table, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw; + + for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) { + const struct aspeed_gate_data *gd = &aspeed_g6_gates[i]; + u32 gate_flags; + + /* + * Special case: the USB port 1 clock (bit 14) is always + * working the opposite way from the other ones. + */ + gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; + hw = aspeed_g6_clk_hw_register_gate(dev, + gd->name, + gd->parent_name, + gd->flags, + map, + gd->clock_idx, + gd->reset_idx, + gate_flags, + &aspeed_g6_clk_lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + aspeed_g6_clk_data->hws[i] = hw; + } + + return 0; +}; + +static const struct of_device_id aspeed_g6_clk_dt_ids[] = { + { .compatible = "aspeed,ast2600-scu" }, + { } +}; + +static struct platform_driver aspeed_g6_clk_driver = { + .probe = aspeed_g6_clk_probe, + .driver = { + .name = "ast2600-clk", + .of_match_table = aspeed_g6_clk_dt_ids, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(aspeed_g6_clk_driver); + +static const u32 ast2600_a0_axi_ahb_div_table[] = { + 2, 2, 3, 5, +}; + +static const u32 ast2600_a1_axi_ahb_div_table[] = { + 4, 6, 2, 4, +}; + +static void __init aspeed_g6_cc(struct regmap *map) +{ + struct clk_hw *hw; + u32 val, div, chip_id, axi_div, ahb_div; + + clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000); + + /* + * High-speed PLL clock derived from the crystal. This the CPU clock, + * and we assume that it is enabled + */ + regmap_read(map, ASPEED_HPLL_PARAM, &val); + aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val); + + regmap_read(map, ASPEED_MPLL_PARAM, &val); + aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val); + + regmap_read(map, ASPEED_DPLL_PARAM, &val); + aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val); + + regmap_read(map, ASPEED_EPLL_PARAM, &val); + aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val); + + regmap_read(map, ASPEED_APLL_PARAM, &val); + aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val); + + /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/ + regmap_read(map, ASPEED_G6_STRAP1, &val); + if (val & BIT(16)) + axi_div = 1; + else + axi_div = 2; + + regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id); + if (chip_id & BIT(16)) + ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3]; + else + ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3]; + + hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div); + aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw; + + regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val); + val = (val >> 23) & 0x7; + div = 4 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div); + aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw; + + regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val); + val = (val >> 9) & 0x7; + div = 2 * (val + 1); + hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div); + aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw; + + /* USB 2.0 port1 phy 40MHz clock */ + hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000); + aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw; +}; + +static void __init aspeed_g6_cc_init(struct device_node *np) +{ + struct regmap *map; + int ret; + int i; + + scu_g6_base = of_iomap(np, 0); + if (!scu_g6_base) + return; + + aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws, + ASPEED_G6_NUM_CLKS), GFP_KERNEL); + if (!aspeed_g6_clk_data) + return; + + /* + * This way all clocks fetched before the platform device probes, + * except those we assign here for early use, will be deferred. + */ + for (i = 0; i < ASPEED_G6_NUM_CLKS; i++) + aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + /* + * We check that the regmap works on this very first access, + * but as this is an MMIO-backed regmap, subsequent regmap + * access is not going to fail and we skip error checks from + * this point. + */ + map = syscon_node_to_regmap(np); + if (IS_ERR(map)) { + pr_err("no syscon regmap\n"); + return; + } + + aspeed_g6_cc(map); + aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS; + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data); + if (ret) + pr_err("failed to add DT provider: %d\n", ret); +}; +CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init); diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c index fadff7915dd9..688d540ebddd 100644 --- a/drivers/clocksource/timer-fttmr010.c +++ b/drivers/clocksource/timer-fttmr010.c @@ -38,6 +38,11 @@ #define TIMER_CR (0x30) /* + Control register set to clear for ast2600 only. + */ +#define TIMER_CR_CLR (0x3c) + +/* * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers. */ #define TIMER_1_CR_ENABLE BIT(0) @@ -97,6 +102,7 @@ struct fttmr010 { bool is_aspeed; u32 t1_enable_val; struct clock_event_device clkevt; + int (*timer_shutdown)(struct clock_event_device *evt); #ifdef CONFIG_ARM struct delay_timer delay_timer; #endif @@ -140,9 +146,7 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, u32 cr; /* Stop */ - cr = readl(fttmr010->base + TIMER_CR); - cr &= ~fttmr010->t1_enable_val; - writel(cr, fttmr010->base + TIMER_CR); + fttmr010->timer_shutdown(evt); if (fttmr010->is_aspeed) { /* @@ -164,6 +168,16 @@ static int fttmr010_timer_set_next_event(unsigned long cycles, return 0; } +static int ast2600_timer_shutdown(struct clock_event_device *evt) +{ + struct fttmr010 *fttmr010 = to_fttmr010(evt); + + /* Stop */ + writel(fttmr010->t1_enable_val, fttmr010->base + TIMER_CR_CLR); + + return 0; +} + static int fttmr010_timer_shutdown(struct clock_event_device *evt) { struct fttmr010 *fttmr010 = to_fttmr010(evt); @@ -183,9 +197,7 @@ static int fttmr010_timer_set_oneshot(struct clock_event_device *evt) u32 cr; /* Stop */ - cr = readl(fttmr010->base + TIMER_CR); - cr &= ~fttmr010->t1_enable_val; - writel(cr, fttmr010->base + TIMER_CR); + fttmr010->timer_shutdown(evt); /* Setup counter start from 0 or ~0 */ writel(0, fttmr010->base + TIMER1_COUNT); @@ -211,9 +223,7 @@ static int fttmr010_timer_set_periodic(struct clock_event_device *evt) u32 cr; /* Stop */ - cr = readl(fttmr010->base + TIMER_CR); - cr &= ~fttmr010->t1_enable_val; - writel(cr, fttmr010->base + TIMER_CR); + fttmr010->timer_shutdown(evt); /* Setup timer to fire at 1/HZ intervals. */ if (fttmr010->is_aspeed) { @@ -249,7 +259,21 @@ static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) +static irqreturn_t ast2600_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = dev_id; + struct fttmr010 *fttmr010 = to_fttmr010(evt); + + writel(0x1, fttmr010->base + TIMER_INTR_STATE); + + evt->event_handler(evt); + return IRQ_HANDLED; +} + +static int __init fttmr010_common_init(struct device_node *np, + bool is_aspeed, + int (*timer_shutdown)(struct clock_event_device *), + irq_handler_t handler) { struct fttmr010 *fttmr010; int irq; @@ -350,6 +374,8 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) fttmr010->tick_rate); } + fttmr010->timer_shutdown = timer_shutdown; + /* * Setup clockevent timer (interrupt-driven) on timer 1. */ @@ -357,7 +383,7 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) writel(0, fttmr010->base + TIMER1_LOAD); writel(0, fttmr010->base + TIMER1_MATCH1); writel(0, fttmr010->base + TIMER1_MATCH2); - ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER, + ret = request_irq(irq, handler, IRQF_TIMER, "FTTMR010-TIMER1", &fttmr010->clkevt); if (ret) { pr_err("FTTMR010-TIMER1 no IRQ\n"); @@ -370,10 +396,10 @@ static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed) fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event; - fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown; + fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown; fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic; fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot; - fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown; + fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown; fttmr010->clkevt.cpumask = cpumask_of(0); fttmr010->clkevt.irq = irq; clockevents_config_and_register(&fttmr010->clkevt, @@ -404,14 +430,25 @@ out_disable_clock: return ret; } +static __init int ast2600_timer_init(struct device_node *np) +{ + return fttmr010_common_init(np, true, + ast2600_timer_shutdown, + ast2600_timer_interrupt); +} + static __init int aspeed_timer_init(struct device_node *np) { - return fttmr010_common_init(np, true); + return fttmr010_common_init(np, true, + fttmr010_timer_shutdown, + fttmr010_timer_interrupt); } static __init int fttmr010_timer_init(struct device_node *np) { - return fttmr010_common_init(np, false); + return fttmr010_common_init(np, false, + fttmr010_timer_shutdown, + fttmr010_timer_interrupt); } TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init); @@ -419,3 +456,4 @@ TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init); TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init); TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init); TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init); +TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init); diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 200c04ce5b0e..6d7aa4a89458 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -510,4 +510,11 @@ config EDAC_ASPEED First, ECC must be configured in the bootloader. Then, this driver will expose error counters via the EDAC kernel framework. +config EDAC_NPCM7XX + tristate "Nuvoton NPCM7xx DDR Memory Controller" + depends on ARCH_NPCM7XX + help + Support for error detection and correction on the + Nuvoton NPCM7xx DDR memory controller. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 165ca65e1a3a..6697ba11190b 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -85,3 +85,4 @@ obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o +obj-$(CONFIG_EDAC_NPCM7XX) += npcm7xx_edac.o diff --git a/drivers/edac/npcm7xx_edac.c b/drivers/edac/npcm7xx_edac.c new file mode 100644 index 000000000000..2d2deb81e49c --- /dev/null +++ b/drivers/edac/npcm7xx_edac.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Quanta Computer lnc. + */ + +#include <linux/edac.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of_address.h> +#include <linux/of_device.h> + +#include "edac_module.h" + +#define ECC_ENABLE BIT(24) +#define ECC_EN_INT_MASK 0x7fffff87 + +#define INT_STATUS_ADDR 116 +#define INT_ACK_ADDR 117 +#define INT_MASK_ADDR 118 + +#define ECC_EN_ADDR 93 +#define ECC_C_ADDR_ADDR 98 +#define ECC_C_DATA_ADDR 100 +#define ECC_C_ID_ADDR 101 +#define ECC_C_SYND_ADDR 99 +#define ECC_U_ADDR_ADDR 95 +#define ECC_U_DATA_ADDR 97 +#define ECC_U_ID_ADDR 101 +#define ECC_U_SYND_ADDR 96 + +#define ECC_ERROR -1 +#define EDAC_MSG_SIZE 256 +#define EDAC_MOD_NAME "npcm7xx-edac" + +struct ecc_error_signature_info { + u32 ecc_addr; + u32 ecc_data; + u32 ecc_id; + u32 ecc_synd; +}; + +struct npcm7xx_ecc_int_status { + u32 int_mask; + u32 int_status; + u32 int_ack; + u32 ce_cnt; + u32 ue_cnt; + struct ecc_error_signature_info ceinfo; + struct ecc_error_signature_info ueinfo; +}; + +struct npcm7xx_edac_priv { + void __iomem *baseaddr; + char message[EDAC_MSG_SIZE]; + struct npcm7xx_ecc_int_status stat; +}; + +/** + * npcm7xx_edac_get_ecc_syndrom - Get the current ecc error info + * @base: Pointer to the base address of the ddr memory controller + * @p: Pointer to the Nuvoton ecc status structure + * + * Determines there is any ecc error or not + * + * Return: ECC detection status + */ +static int npcm7xx_edac_get_ecc_syndrom(void __iomem *base, + struct npcm7xx_ecc_int_status *p) +{ + int status = 0; + u32 int_status = 0; + + int_status = readl(base + 4*INT_STATUS_ADDR); + writel(int_status, base + 4*INT_ACK_ADDR); + edac_dbg(3, "int_status: %#08x\n", int_status); + + if ((int_status & (1 << 6)) == (1 << 6)) { + edac_dbg(3, "6-Mult uncorrectable detected.\n"); + p->ue_cnt++; + status = ECC_ERROR; + } + + if ((int_status & (1 << 5)) == (1 << 5)) { + edac_dbg(3, "5-An uncorrectable detected\n"); + p->ue_cnt++; + status = ECC_ERROR; + } + + if ((int_status & (1 << 4)) == (1 << 4)) { + edac_dbg(3, "4-mult correctable detected.\n"); + p->ce_cnt++; + status = ECC_ERROR; + } + + if ((int_status & (1 << 3)) == (1 << 3)) { + edac_dbg(3, "3-A correctable detected.\n"); + p->ce_cnt++; + status = ECC_ERROR; + } + + if (status == ECC_ERROR) { + u32 ecc_id; + + p->ceinfo.ecc_addr = readl(base + 4*ECC_C_ADDR_ADDR); + p->ceinfo.ecc_data = readl(base + 4*ECC_C_DATA_ADDR); + p->ceinfo.ecc_synd = readl(base + 4*ECC_C_SYND_ADDR); + + p->ueinfo.ecc_addr = readl(base + 4*ECC_U_ADDR_ADDR); + p->ueinfo.ecc_data = readl(base + 4*ECC_U_DATA_ADDR); + p->ueinfo.ecc_synd = readl(base + 4*ECC_U_SYND_ADDR); + + /* ECC_C_ID_ADDR has same value as ECC_U_ID_ADDR */ + ecc_id = readl(base + 4*ECC_C_ID_ADDR); + p->ueinfo.ecc_id = ecc_id & 0xffff; + p->ceinfo.ecc_id = ecc_id >> 16; + } + + return status; +} + +/** + * npcm7xx_edac_handle_error - Handle controller error types CE and UE + * @mci: Pointer to the edac memory controller instance + * @p: Pointer to the Nuvoton ecc status structure + * + * Handles the controller ECC correctable and un correctable error. + */ +static void npcm7xx_edac_handle_error(struct mem_ctl_info *mci, + struct npcm7xx_ecc_int_status *p) +{ + struct npcm7xx_edac_priv *priv = mci->pvt_info; + u32 page, offset; + + if (p->ce_cnt) { + snprintf(priv->message, EDAC_MSG_SIZE, + "DDR ECC: synd=%#08x addr=%#08x data=%#08x source_id=%#08x ", + p->ceinfo.ecc_synd, p->ceinfo.ecc_addr, + p->ceinfo.ecc_data, p->ceinfo.ecc_id); + + page = p->ceinfo.ecc_addr >> PAGE_SHIFT; + offset = p->ceinfo.ecc_addr & ~PAGE_MASK; + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, + p->ce_cnt, page, offset, + p->ceinfo.ecc_synd, + 0, 0, -1, + priv->message, ""); + } + + if (p->ue_cnt) { + snprintf(priv->message, EDAC_MSG_SIZE, + "DDR ECC: synd=%#08x addr=%#08x data=%#08x source_id=%#08x ", + p->ueinfo.ecc_synd, p->ueinfo.ecc_addr, + p->ueinfo.ecc_data, p->ueinfo.ecc_id); + + page = p->ueinfo.ecc_addr >> PAGE_SHIFT; + offset = p->ueinfo.ecc_addr & ~PAGE_MASK; + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, + p->ue_cnt, page, offset, + p->ueinfo.ecc_synd, + 0, 0, -1, + priv->message, ""); + } + + memset(p, 0, sizeof(*p)); +} + +/** + * npcm7xx_edac_check - Check controller for ECC errors + * @mci: Pointer to the edac memory controller instance + * + * This routine is used to check and post ECC errors and is called by + * this driver's CE and UE interrupt handler. + */ +static void npcm7xx_edac_check(struct mem_ctl_info *mci) +{ + struct npcm7xx_edac_priv *priv = mci->pvt_info; + int status = 0; + + status = npcm7xx_edac_get_ecc_syndrom(priv->baseaddr, &priv->stat); + if (status != ECC_ERROR) + return; + + npcm7xx_edac_handle_error(mci, &priv->stat); +} + +/** + * npcm7xx_edac_isr - CE/UE interrupt service routine + * @irq: The virtual interrupt number being serviced. + * @dev_id: A pointer to the EDAC memory controller instance + * associated with the interrupt being handled. + * + * This routine implements the interrupt handler for both correctable + * (CE) and uncorrectable (UE) ECC errors for the Nuvoton Cadence DDR + * controller. It simply calls through to the routine used to check, + * report and clear the ECC status. + * + * Unconditionally returns IRQ_HANDLED. + */ +static irqreturn_t npcm7xx_edac_isr(int irq, void *dev_id) +{ + struct mem_ctl_info *mci = dev_id; + int npcm_edac_report = 0; + + npcm_edac_report = edac_get_report_status(); + if (npcm_edac_report != EDAC_REPORTING_DISABLED) + npcm7xx_edac_check(mci); + + return IRQ_HANDLED; +} + +static int npcm7xx_edac_register_irq(struct mem_ctl_info *mci, + struct platform_device *pdev) +{ + int status = 0; + int mc_irq; + struct npcm7xx_edac_priv *priv = mci->pvt_info; + + /* Only enable MC interrupts with ECC - clear int_mask[6:3] */ + writel(ECC_EN_INT_MASK, priv->baseaddr + 4*INT_MASK_ADDR); + + mc_irq = platform_get_irq(pdev, 0); + + if (!mc_irq) { + edac_printk(KERN_ERR, EDAC_MC, "Unable to map interrupts.\n"); + status = -ENODEV; + goto fail; + } + + status = devm_request_irq(&pdev->dev, mc_irq, npcm7xx_edac_isr, 0, + "npcm-memory-controller", mci); + + if (status < 0) { + edac_printk(KERN_ERR, EDAC_MC, + "Unable to request irq %d for ECC", + mc_irq); + status = -ENODEV; + goto fail; + } + + return 0; + +fail: + return status; +} + +static const struct of_device_id npcm7xx_edac_of_match[] = { + { .compatible = "nuvoton,npcm7xx-sdram-edac"}, + { /* end of table */ } +}; + +MODULE_DEVICE_TABLE(of, npcm7xx_edac_of_match); + +/** + * npcm7xx_edac_mc_init - Initialize driver instance + * @mci: Pointer to the edac memory controller instance + * @pdev: Pointer to the platform_device struct + * + * Performs initialization of the EDAC memory controller instance and + * related driver-private data associated with the memory controller the + * instance is bound to. + * + * Returns 0 if OK; otherwise, < 0 on error. + */ +static int npcm7xx_edac_mc_init(struct mem_ctl_info *mci, + struct platform_device *pdev) +{ + const struct of_device_id *id; + + id = of_match_device(npcm7xx_edac_of_match, &pdev->dev); + if (!id) + return -ENODEV; + + /* Initialize controller capabilities and configuration */ + mci->mtype_cap = MEM_FLAG_DDR4; + mci->edac_ctl_cap = EDAC_FLAG_SECDED; + mci->edac_cap = EDAC_FLAG_SECDED; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + mci->scrub_mode = SCRUB_HW_SRC; + mci->ctl_name = id->compatible; + mci->dev_name = dev_name(&pdev->dev); + mci->mod_name = EDAC_MOD_NAME; + + edac_op_state = EDAC_OPSTATE_INT; + + return 0; +} + +/** + * npcm7xx_edac_get_eccstate - Return the controller ecc enable/disable status + * @base: Pointer to the ddr memory controller base address + * + * Get the ECC enable/disable status for the controller + * + * Return: a ecc status boolean i.e true/false - enabled/disabled. + */ +static bool npcm7xx_edac_get_eccstate(void __iomem *base) +{ + u32 ecc_en; + bool state = false; + + ecc_en = readl(base + 4*ECC_EN_ADDR); + if (ecc_en & ECC_ENABLE) { + edac_printk(KERN_INFO, EDAC_MC, "ECC reporting and correcting on. "); + state = true; + } + + return state; +} + +/** + * npcm7xx_edac_mc_probe - Check controller and bind driver + * @pdev: Pointer to the platform_device struct + * + * Probes a specific controller instance for binding with the driver. + * + * Return: 0 if the controller instance was successfully bound to the + * driver; otherwise, < 0 on error. + */ +static int npcm7xx_edac_mc_probe(struct platform_device *pdev) +{ + struct mem_ctl_info *mci; + struct edac_mc_layer layers[1]; + struct npcm7xx_edac_priv *priv; + struct resource *res; + void __iomem *baseaddr; + int rc; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + baseaddr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(baseaddr)) { + edac_printk(KERN_ERR, EDAC_MOD_NAME, + "DDR controller regs not defined\n"); + return PTR_ERR(baseaddr); + } + + /* + * Check if ECC is enabled. + * If not, there is no useful monitoring that can be done + * for this controller. + */ + if (!npcm7xx_edac_get_eccstate(baseaddr)) { + edac_printk(KERN_INFO, EDAC_MC, "ECC disabled\n"); + return -ENXIO; + } + + /* + * Allocate an EDA controller instance and perform the appropriate + * initialization. + */ + layers[0].type = EDAC_MC_LAYER_ALL_MEM; + layers[0].size = 1; + + mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, + sizeof(struct npcm7xx_edac_priv)); + if (!mci) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed memory allocation for mc instance\n"); + return -ENOMEM; + } + + mci->pdev = &pdev->dev; + priv = mci->pvt_info; + priv->baseaddr = baseaddr; + platform_set_drvdata(pdev, mci); + + rc = npcm7xx_edac_mc_init(mci, pdev); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed to initialize instance\n"); + goto free_edac_mc; + } + + /* Attempt to register it with the EDAC subsystem */ + rc = edac_mc_add_mc(mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed to register with EDAC core\n"); + goto free_edac_mc; + } + + /* Register interrupts */ + rc = npcm7xx_edac_register_irq(mci, pdev); + if (rc) + goto free_edac_mc; + + return 0; + +free_edac_mc: + edac_mc_free(mci); + + return rc; +} + +/** + * npcm7xx_edac_mc_remove - Unbind driver from controller + * @pdev: Pointer to the platform_device struct + * + * Return: Unconditionally 0 + */ +static int npcm7xx_edac_mc_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = platform_get_drvdata(pdev); + + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + + return 0; +} + +static struct platform_driver npcm7xx_edac_driver = { + .probe = npcm7xx_edac_mc_probe, + .remove = npcm7xx_edac_mc_remove, + .driver = { + .name = EDAC_MOD_NAME, + .of_match_table = npcm7xx_edac_of_match, + }, +}; + +module_platform_driver(npcm7xx_edac_driver); + +MODULE_AUTHOR("Quanta Computer Inc."); +MODULE_DESCRIPTION("Nuvoton NPCM7xx EDAC Driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/fsi/Kconfig b/drivers/fsi/Kconfig index c612db7a914a..12e8c4a04fb1 100644 --- a/drivers/fsi/Kconfig +++ b/drivers/fsi/Kconfig @@ -53,6 +53,12 @@ config FSI_MASTER_AST_CF lines driven by the internal ColdFire coprocessor. This requires the corresponding machine specific ColdFire firmware to be available. +config FSI_MASTER_ASPEED + tristate "FSI ASPEED master" + help + This option enables a FSI master that is present behind an OPB bridge + in the AST2600. + config FSI_SCOM tristate "SCOM FSI client device driver" ---help--- diff --git a/drivers/fsi/Makefile b/drivers/fsi/Makefile index e4a2ff043c32..da218a1ad8e1 100644 --- a/drivers/fsi/Makefile +++ b/drivers/fsi/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_FSI) += fsi-core.o obj-$(CONFIG_FSI_MASTER_HUB) += fsi-master-hub.o +obj-$(CONFIG_FSI_MASTER_ASPEED) += fsi-master-aspeed.o obj-$(CONFIG_FSI_MASTER_GPIO) += fsi-master-gpio.o obj-$(CONFIG_FSI_MASTER_AST_CF) += fsi-master-ast-cf.o obj-$(CONFIG_FSI_SCOM) += fsi-scom.o diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 1f76740f33b6..1ea15621e588 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -1241,6 +1241,19 @@ static ssize_t master_break_store(struct device *dev, static DEVICE_ATTR(break, 0200, NULL, master_break_store); +static struct attribute *master_attrs[] = { + &dev_attr_break.attr, + &dev_attr_rescan.attr, + NULL +}; + +ATTRIBUTE_GROUPS(master); + +struct class fsi_master_class = { + .name = "fsi-master", + .dev_groups = master_groups, +}; + int fsi_master_register(struct fsi_master *master) { int rc; @@ -1249,6 +1262,7 @@ int fsi_master_register(struct fsi_master *master) mutex_init(&master->scan_lock); master->idx = ida_simple_get(&master_ida, 0, INT_MAX, GFP_KERNEL); dev_set_name(&master->dev, "fsi%d", master->idx); + master->dev.class = &fsi_master_class; rc = device_register(&master->dev); if (rc) { @@ -1256,19 +1270,12 @@ int fsi_master_register(struct fsi_master *master) return rc; } - rc = device_create_file(&master->dev, &dev_attr_rescan); - if (rc) { - device_del(&master->dev); - ida_simple_remove(&master_ida, master->idx); - return rc; - } - - rc = device_create_file(&master->dev, &dev_attr_break); - if (rc) { - device_del(&master->dev); - ida_simple_remove(&master_ida, master->idx); - return rc; - } + /* For temporary compatibility reasons, create a symlink from + * the class interface to the top-level device node */ + rc = sysfs_create_link(master->dev.kobj.parent->parent, + &master->dev.kobj, dev_name(&master->dev)); + if (rc) + dev_info(&master->dev, "can't create class compat symlink"); np = dev_of_node(&master->dev); if (!of_property_read_bool(np, "no-scan-on-init")) { @@ -1350,8 +1357,15 @@ static int __init fsi_init(void) rc = bus_register(&fsi_bus_type); if (rc) goto fail_bus; + + rc = class_register(&fsi_master_class); + if (rc) + goto fail_class; + return 0; + fail_class: + bus_unregister(&fsi_bus_type); fail_bus: unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); return rc; @@ -1360,6 +1374,7 @@ postcore_initcall(fsi_init); static void fsi_exit(void) { + class_unregister(&fsi_master_class); bus_unregister(&fsi_bus_type); unregister_chrdev_region(fsi_base_dev, FSI_CHAR_MAX_DEVICES); ida_destroy(&fsi_minor_ida); diff --git a/drivers/fsi/fsi-master-aspeed.c b/drivers/fsi/fsi-master-aspeed.c new file mode 100644 index 000000000000..8da29fb9a69e --- /dev/null +++ b/drivers/fsi/fsi-master-aspeed.c @@ -0,0 +1,789 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) IBM Corporation 2018 +// FSI master driver for AST2600 + +#include <linux/clk.h> +#include <linux/debugfs.h> +#include <linux/delay.h> +#include <linux/fsi.h> +#include <linux/io.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/slab.h> +#include <linux/iopoll.h> + +#include "fsi-master.h" + +#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ + +#define FSI_NUM_DEBUGFS_ENTRIES 17 + +#define DEFAULT_DIVISOR 14 + +struct fsi_master_aspeed; + +struct fsi_master_aspeed_debugfs_entry { + struct fsi_master_aspeed *aspeed; + uint32_t addr; +}; + +struct fsi_master_aspeed { + struct fsi_master master; + struct device *dev; + void __iomem *base; + struct clk *clk; + + struct dentry *debugfs_dir; + struct fsi_master_aspeed_debugfs_entry debugfs[FSI_NUM_DEBUGFS_ENTRIES]; +}; + +#define to_fsi_master_aspeed(m) \ + container_of(m, struct fsi_master_aspeed, master) + +/* Control register (size 0x400) */ +static const u32 ctrl_base = 0x80000000; + +static const u32 fsi_base = 0xa0000000; + +#define OPB_FSI_VER 0x00 +#define OPB_TRIGGER 0x04 +#define OPB_CTRL_BASE 0x08 +#define OPB_FSI_BASE 0x0c +#define OPB_CLK_SYNC 0x3c +#define OPB_IRQ_CLEAR 0x40 +#define OPB_IRQ_MASK 0x44 +#define OPB_IRQ_STATUS 0x48 + +#define OPB0_SELECT 0x10 +#define OPB0_RW 0x14 +#define OPB0_XFER_SIZE 0x18 +#define OPB0_FSI_ADDR 0x1c +#define OPB0_FSI_DATA_W 0x20 +#define OPB0_STATUS 0x80 +#define OPB0_FSI_DATA_R 0x84 + +#define OPB0_WRITE_ORDER1 0x4c +#define OPB0_WRITE_ORDER2 0x50 +#define OPB1_WRITE_ORDER1 0x54 +#define OPB1_WRITE_ORDER2 0x58 +#define OPB0_READ_ORDER1 0x5c +#define OPB1_READ_ORDER2 0x60 + +#define OPB_RETRY_COUNTER 0x64 + +/* OPBn_STATUS */ +#define STATUS_HALFWORD_ACK BIT(0) +#define STATUS_FULLWORD_ACK BIT(1) +#define STATUS_ERR_ACK BIT(2) +#define STATUS_RETRY BIT(3) +#define STATUS_TIMEOUT BIT(4) + +/* OPB_IRQ_MASK */ +#define OPB1_XFER_ACK_EN BIT(17) +#define OPB0_XFER_ACK_EN BIT(16) + +#define OPB_IRQ_CH0_DMA_EOT BIT(0) +#define OPB_IRQ_CH1_DMA_EOT BIT(1) +#define OPB_IRQ_CH2_DMA_EOT BIT(2) +#define OPB_IRQ_CH3_DMA_EOT BIT(3) +#define OPB_IRQ_CH0_DMA_FIFO_FULL BIT(4) +#define OPB_IRQ_CH1_DMA_FIFO_FULL BIT(5) +#define OPB_IRQ_CH2_DMA_FIFO_FULL BIT(6) +#define OPB_IRQ_CH3_DMA_FIFO_FULL BIT(7) +#define OPB_IRQ_CH0_DMA_FIFO_EMPTY BIT(8) +#define OPB_IRQ_CH1_DMA_FIFO_EMPTY BIT(9) +#define OPB_IRQ_CH2_DMA_FIFO_EMPTY BIT(10) +#define OPB_IRQ_CH3_DMA_FIFO_EMPTY BIT(11) +#define OPB_IRQ_CH0_DMA_TCONT_DONE BIT(12) +#define OPB_IRQ_CH1_DMA_TCONT_DONE BIT(13) +#define OPB_IRQ_CH2_DMA_TCONT_DONE BIT(14) +#define OPB_IRQ_CH3_DMA_TCONT_DONE BIT(15) +#define OPB_IRQ_OPB1_XFER_ACK BIT(16) +#define OPB_IRQ_OPB0_XFER_ACK BIT(17) +#define OPB_IRQ_SLAVE0 BIT(18) +#define OPB_IRQ_SLAVE1 BIT(19) +#define OPB_IRQ_SLAVE2 BIT(20) +#define OPB_IRQ_SLAVE3 BIT(21) +#define OPB_IRQ_SLAVE4 BIT(22) +#define OPB_IRQ_SLAVE5 BIT(23) +#define OPB_IRQ_SLAVE6 BIT(24) +#define OPB_IRQ_SLAVE7 BIT(25) +#define OPB_IRQ_ANY_HOTPLUG BIT(26) +#define OPB_IRQ_ANY_PORT_ERROR BIT(27) +#define OPB_IRQ_ANY_MST_ERROR BIT(28) + +/* OPB_RW */ +#define CMD_READ BIT(0) +#define CMD_WRITE 0 + +/* OPBx_XFER_SIZE */ +#define XFER_WORD (BIT(1) | BIT(0)) +#define XFER_HALFWORD (BIT(0)) +#define XFER_BYTE (0) + +#define CREATE_TRACE_POINTS +#include <trace/events/fsi_master_aspeed.h> + +static int __opb_write(struct fsi_master_aspeed *aspeed, u32 addr, + u32 val, u32 transfer_size) +{ + void __iomem *base = aspeed->base; + u32 reg, status; + int ret; + + writel(CMD_WRITE, base + OPB0_RW); + writel(transfer_size, base + OPB0_XFER_SIZE); + writel(addr, base + OPB0_FSI_ADDR); + writel(val, base + OPB0_FSI_DATA_W); + writel(0x1, base + OPB_IRQ_CLEAR); + writel(0x1, base + OPB_TRIGGER); + + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, + (reg & OPB0_XFER_ACK_EN) != 0, + 0, 10000); + + status = readl(base + OPB0_STATUS); + + trace_fsi_master_aspeed_opb_write(addr, val, transfer_size, status, reg); + + /* Return error when poll timed out */ + if (ret) + return ret; + + /* Command failed, master will reset */ + if (status & STATUS_ERR_ACK) + return -EIO; + + return 0; +} + +static int opb_writeb(struct fsi_master_aspeed *aspeed, u32 addr, u8 val) +{ + return __opb_write(aspeed, addr, val, XFER_BYTE); +} + +static int opb_writew(struct fsi_master_aspeed *aspeed, u32 addr, __be16 val) +{ + return __opb_write(aspeed, addr, (__force u16)val, XFER_HALFWORD); +} + +static int opb_writel(struct fsi_master_aspeed *aspeed, u32 addr, __be32 val) +{ + return __opb_write(aspeed, addr, (__force u32)val, XFER_WORD); +} + +static int __opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, + u32 transfer_size, void *out) +{ + void __iomem *base = aspeed->base; + u32 result, reg; + int status, ret; + + writel(CMD_READ, base + OPB0_RW); + writel(transfer_size, base + OPB0_XFER_SIZE); + writel(addr, base + OPB0_FSI_ADDR); + writel(0x1, base + OPB_IRQ_CLEAR); + writel(0x1, base + OPB_TRIGGER); + + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, + (reg & OPB0_XFER_ACK_EN) != 0, + 0, 10000); + + status = readl(base + OPB0_STATUS); + + result = readl(base + OPB0_FSI_DATA_R); + + trace_fsi_master_aspeed_opb_read(addr, transfer_size, result, + readl(base + OPB0_STATUS), + reg); + + /* Return error when poll timed out */ + if (ret) + return ret; + + /* Command failed, master will reset */ + if (status & STATUS_ERR_ACK) + return -EIO; + + if (out) { + switch (transfer_size) { + case XFER_BYTE: + *(u8 *)out = result; + break; + case XFER_HALFWORD: + *(u16 *)out = result; + break; + case XFER_WORD: + *(u32 *)out = result; + break; + default: + return -EINVAL; + } + + } + + return 0; +} + +static int opb_readl(struct fsi_master_aspeed *aspeed, uint32_t addr, __be32 *out) +{ + return __opb_read(aspeed, addr, XFER_WORD, out); +} + +static int opb_readw(struct fsi_master_aspeed *aspeed, uint32_t addr, __be16 *out) +{ + return __opb_read(aspeed, addr, XFER_HALFWORD, (void *)out); +} + +static int opb_readb(struct fsi_master_aspeed *aspeed, uint32_t addr, u8 *out) +{ + return __opb_read(aspeed, addr, XFER_BYTE, (void *)out); +} + +static int check_errors(struct fsi_master_aspeed *aspeed, int err) +{ + int ret; + + if (trace_fsi_master_aspeed_opb_error_enabled()) { + __be32 mresp0, mstap0, mesrb0; + + opb_readl(aspeed, ctrl_base + FSI_MRESP0, &mresp0); + opb_readl(aspeed, ctrl_base + FSI_MSTAP0, &mstap0); + opb_readl(aspeed, ctrl_base + FSI_MESRB0, &mesrb0); + + trace_fsi_master_aspeed_opb_error( + be32_to_cpu(mresp0), + be32_to_cpu(mstap0), + be32_to_cpu(mesrb0)); + }; + + if (err == -EIO) { + /* Check MAEB (0x70) ? */ + + /* Then clear errors in master */ + ret = opb_writel(aspeed, ctrl_base + FSI_MRESP0, + cpu_to_be32(FSI_MRESP_RST_ALL_MASTER)); + if (ret) { + /* TODO: log? return different code? */ + return ret; + } + /* TODO: confirm that 0x70 was okay */ + } + + /* This will pass through timeout errors */ + return err; +} + +static int aspeed_master_read(struct fsi_master *master, int link, + uint8_t id, uint32_t addr, void *val, size_t size) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + int ret; + + if (id != 0) + return -EINVAL; + + addr += link * FSI_HUB_LINK_SIZE; + + switch (size) { + case 1: + ret = opb_readb(aspeed, fsi_base + addr, val); + break; + case 2: + ret = opb_readw(aspeed, fsi_base + addr, val); + break; + case 4: + ret = opb_readl(aspeed, fsi_base + addr, val); + break; + default: + return -EINVAL; + } + + ret = check_errors(aspeed, ret); + if (ret) + return ret; + + return 0; +} + +static int aspeed_master_write(struct fsi_master *master, int link, + uint8_t id, uint32_t addr, const void *val, size_t size) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + int ret; + + if (id != 0) + return -EINVAL; + + addr += link * FSI_HUB_LINK_SIZE; + + switch (size) { + case 1: + ret = opb_writeb(aspeed, fsi_base + addr, *(u8 *)val); + break; + case 2: + ret = opb_writew(aspeed, fsi_base + addr, *(__be16 *)val); + break; + case 4: + ret = opb_writel(aspeed, fsi_base + addr, *(__be32 *)val); + break; + default: + return -EINVAL; + } + + ret = check_errors(aspeed, ret); + if (ret) + return ret; + + return 0; +} + +static int aspeed_master_link_enable(struct fsi_master *master, int link) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + int idx, bit, ret; + __be32 reg, result; + + idx = link / 32; + bit = link % 32; + + reg = cpu_to_be32(0x80000000 >> bit); + + ret = opb_writel(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), reg); + if (ret) + return ret; + + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + ret = opb_readl(aspeed, ctrl_base + FSI_MENP0 + (4 * idx), &result); + if (ret) + return ret; + + if (result != reg) { + dev_err(aspeed->dev, "%s failed: %08x\n", __func__, result); + return -EIO; + } + + return 0; +} + +static int aspeed_master_term(struct fsi_master *master, int link, uint8_t id) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + uint32_t addr; + __be32 cmd; + int rc; + + addr = 0x4; + cmd = cpu_to_be32(0xecc00000); + + dev_dbg(aspeed->dev, "sending term to link %d slave %d\n", link, id); + + rc = aspeed_master_write(master, link, id, addr, &cmd, 4); + + dev_dbg(aspeed->dev, "term done (%d)\n", rc); + + return rc; +} + +static int aspeed_master_break(struct fsi_master *master, int link) +{ + struct fsi_master_aspeed *aspeed = to_fsi_master_aspeed(master); + uint32_t addr; + __be32 cmd; + int rc; + + addr = 0x0; + cmd = cpu_to_be32(0xc0de0000); + + dev_dbg(aspeed->dev, "sending break to link %d\n", link); + + rc = aspeed_master_write(master, link, 0, addr, &cmd, 4); + + dev_dbg(aspeed->dev, "break done (%d)\n", rc); + + return rc; +} + +static void aspeed_master_release(struct device *dev) +{ + struct fsi_master_aspeed *aspeed = + to_fsi_master_aspeed(dev_to_fsi_master(dev)); + + kfree(aspeed); +} + +/* mmode encoders */ +static inline u32 fsi_mmode_crs0(u32 x) +{ + return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; +} + +static inline u32 fsi_mmode_crs1(u32 x) +{ + return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; +} + +static int aspeed_master_init(struct fsi_master_aspeed *aspeed) +{ + __be32 reg; + + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); + + /* Initialize the MFSI (hub master) engine */ + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); + + reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); + opb_writel(aspeed, ctrl_base + FSI_MECTRL, reg); + + reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA + | fsi_mmode_crs0(DEFAULT_DIVISOR) + | fsi_mmode_crs1(DEFAULT_DIVISOR) + | FSI_MMODE_P8_TO_LSB); + opb_writel(aspeed, ctrl_base + FSI_MMODE, reg); + + reg = cpu_to_be32(0xffff0000); + opb_writel(aspeed, ctrl_base + FSI_MDLYR, reg); + + reg = cpu_to_be32(~0); + opb_writel(aspeed, ctrl_base + FSI_MSENP0, reg); + + /* Leave enabled long enough for master logic to set up */ + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + opb_writel(aspeed, ctrl_base + FSI_MCENP0, reg); + + opb_readl(aspeed, ctrl_base + FSI_MAEB, NULL); + + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); + opb_writel(aspeed, ctrl_base + FSI_MRESP0, reg); + + opb_readl(aspeed, ctrl_base + FSI_MLEVP0, NULL); + + /* Reset the master bridge */ + reg = cpu_to_be32(FSI_MRESB_RST_GEN); + opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); + + reg = cpu_to_be32(FSI_MRESB_RST_ERR); + opb_writel(aspeed, ctrl_base + FSI_MRESB0, reg); + + return 0; +} + +static int fsi_master_aspeed_debugfs_get(void *data, u64 *val) +{ + struct fsi_master_aspeed_debugfs_entry *entry = data; + __be32 out; + int rc; + + rc = opb_readl(entry->aspeed, ctrl_base + entry->addr, &out); + if (rc) + return rc; + + *val = (u64)be32_to_cpu(out); + return 0; +} +static int fsi_master_aspeed_debugfs_set(void *data, u64 val) +{ + struct fsi_master_aspeed_debugfs_entry *entry = data; + int rc; + + rc = opb_writel(entry->aspeed, ctrl_base + entry->addr, + cpu_to_be32(val)); + if (rc) + return rc; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(fsi_master_aspeed_debugfs_ops, + fsi_master_aspeed_debugfs_get, + fsi_master_aspeed_debugfs_set, "0x%08llx\n"); + +static int fsi_master_aspeed_clock_debugfs_get(void *data, u64 *val) +{ + struct fsi_master_aspeed *aspeed = data; + __be32 out; + int rc; + + rc = opb_readl(aspeed, ctrl_base, &out); + if (rc) + return rc; + + *val = (be32_to_cpu(out) >> FSI_MMODE_CRS0SHFT) & FSI_MMODE_CRS0MASK; + + return 0; +} + +static int fsi_master_aspeed_clock_debugfs_set(void *data, u64 val) +{ + struct fsi_master_aspeed *aspeed = data; + u32 reg, rc; + __be32 raw; + + if (val > 0x3ff) + return -EINVAL; + + rc = opb_readl(aspeed, ctrl_base, &raw); + if (rc) + return rc; + + reg = be32_to_cpu(raw); + + + reg &= ~(FSI_MMODE_CRS0MASK << FSI_MMODE_CRS0SHFT); + reg |= fsi_mmode_crs0(val); + + rc = opb_writel(aspeed, ctrl_base, cpu_to_be32(reg)); + if (rc) + return rc; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(fsi_master_aspeed_clock_debugfs_ops, + fsi_master_aspeed_clock_debugfs_get, + fsi_master_aspeed_clock_debugfs_set, "0x%llx\n"); + + +static int fsi_master_aspeed_probe(struct platform_device *pdev) +{ + struct fsi_master_aspeed *aspeed; + struct resource *res; + int rc, links, reg; + __be32 raw; + + aspeed = devm_kzalloc(&pdev->dev, sizeof(*aspeed), GFP_KERNEL); + if (!aspeed) + return -ENOMEM; + + aspeed->dev = &pdev->dev; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + aspeed->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(aspeed->base)) + return PTR_ERR(aspeed->base); + + aspeed->clk = devm_clk_get(aspeed->dev, NULL); + if (IS_ERR(aspeed->clk)) { + dev_err(aspeed->dev, "couldn't get clock\n"); + return PTR_ERR(aspeed->clk); + } + rc = clk_prepare_enable(aspeed->clk); + if (rc) { + dev_err(aspeed->dev, "couldn't enable clock\n"); + return rc; + } + + writel(0x1, aspeed->base + OPB_CLK_SYNC); + writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN, + aspeed->base + OPB_IRQ_MASK); + + /* TODO: determine an appropriate value */ + writel(0x10, aspeed->base + OPB_RETRY_COUNTER); + + writel(ctrl_base, aspeed->base + OPB_CTRL_BASE); + writel(fsi_base, aspeed->base + OPB_FSI_BASE); + + /* Set read data order */ + writel(0x00030b1b, aspeed->base + OPB0_READ_ORDER1); + + /* Set write data order */ + writel(0x0011101b, aspeed->base + OPB0_WRITE_ORDER1); + writel(0x0c330f3f, aspeed->base + OPB0_WRITE_ORDER2); + + /* + * Select OPB0 for all operations. + * Will need to be reworked when enabling DMA or anything that uses + * OPB1. + */ + writel(0x1, aspeed->base + OPB0_SELECT); + + rc = opb_readl(aspeed, ctrl_base + FSI_MVER, &raw); + if (rc) { + dev_err(&pdev->dev, "failed to read hub version\n"); + return rc; + } + + reg = be32_to_cpu(raw); + links = (reg >> 8) & 0xff; + dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links); + + aspeed->master.dev.parent = &pdev->dev; + aspeed->master.dev.release = aspeed_master_release; + aspeed->master.dev.of_node = of_node_get(dev_of_node(&pdev->dev)); + + aspeed->master.n_links = links; + aspeed->master.read = aspeed_master_read; + aspeed->master.write = aspeed_master_write; + aspeed->master.send_break = aspeed_master_break; + aspeed->master.term = aspeed_master_term; + aspeed->master.link_enable = aspeed_master_link_enable; + + dev_set_drvdata(&pdev->dev, aspeed); + + aspeed_master_init(aspeed); + + aspeed->debugfs_dir = debugfs_create_dir("fsi-master-aspeed", NULL); + if (aspeed->debugfs_dir) { + int idx = 0; + struct fsi_master_aspeed_debugfs_entry *etrs = aspeed->debugfs; + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MMODE; + debugfs_create_file("mmode", 0644, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MDLYR; + debugfs_create_file("mdlyr", 0644, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MCRSP; + debugfs_create_file("mcrsp0", 0644, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MENP0; + debugfs_create_file("menp0", 0644, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MLEVP0; + debugfs_create_file("mlevp0", 0444, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MSENP0; + debugfs_create_file("msenp0", 0200, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MCENP0; + debugfs_create_file("mcenp0", 0200, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MAEB; + debugfs_create_file("maeb", 0444, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MVER; + debugfs_create_file("mver", 0444, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MSTAP0; + debugfs_create_file("mstap0", 0444, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MRESP0; + debugfs_create_file("mresp0", 0200, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MESRB0; + debugfs_create_file("mesrb0", 0444, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MRESB0; + debugfs_create_file("mresb0", 0200, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MSCSB0; + debugfs_create_file("mscsb0", 0200, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MATRB0; + debugfs_create_file("matrb0", 0200, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MDTRB0; + debugfs_create_file("mdtrb0", 0200, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + etrs[idx].aspeed = aspeed; + etrs[idx].addr = FSI_MECTRL; + debugfs_create_file("mectrl", 0644, aspeed->debugfs_dir, + &etrs[idx++], + &fsi_master_aspeed_debugfs_ops); + + debugfs_create_file("clock_div", 0644, aspeed->debugfs_dir, + aspeed, &fsi_master_aspeed_clock_debugfs_ops); + } + + rc = fsi_master_register(&aspeed->master); + if (rc) + goto err_release; + + /* At this point, fsi_master_register performs the device_initialize(), + * and holds the sole reference on master.dev. This means the device + * will be freed (via ->release) during any subsequent call to + * fsi_master_unregister. We add our own reference to it here, so we + * can perform cleanup (in _remove()) without it being freed before + * we're ready. + */ + get_device(&aspeed->master.dev); + return 0; + +err_release: + clk_disable_unprepare(aspeed->clk); + return rc; +} + +static int fsi_master_aspeed_remove(struct platform_device *pdev) +{ + struct fsi_master_aspeed *aspeed = platform_get_drvdata(pdev); + + debugfs_remove_recursive(aspeed->debugfs_dir); + + fsi_master_unregister(&aspeed->master); + clk_disable_unprepare(aspeed->clk); + + return 0; +} + +static const struct of_device_id fsi_master_aspeed_match[] = { + { .compatible = "aspeed,ast2600-fsi-master" }, + { }, +}; + +static struct platform_driver fsi_master_aspeed_driver = { + .driver = { + .name = "fsi-master-aspeed", + .of_match_table = fsi_master_aspeed_match, + }, + .probe = fsi_master_aspeed_probe, + .remove = fsi_master_aspeed_remove, +}; + +module_platform_driver(fsi_master_aspeed_driver); +MODULE_LICENSE("GPL"); diff --git a/drivers/fsi/fsi-master-hub.c b/drivers/fsi/fsi-master-hub.c index f158b1a88286..def35cf92571 100644 --- a/drivers/fsi/fsi-master-hub.c +++ b/drivers/fsi/fsi-master-hub.c @@ -13,53 +13,7 @@ #include "fsi-master.h" -/* Control Registers */ -#define FSI_MMODE 0x0 /* R/W: mode */ -#define FSI_MDLYR 0x4 /* R/W: delay */ -#define FSI_MCRSP 0x8 /* R/W: clock rate */ -#define FSI_MENP0 0x10 /* R/W: enable */ -#define FSI_MLEVP0 0x18 /* R: plug detect */ -#define FSI_MSENP0 0x18 /* S: Set enable */ -#define FSI_MCENP0 0x20 /* C: Clear enable */ -#define FSI_MAEB 0x70 /* R: Error address */ -#define FSI_MVER 0x74 /* R: master version/type */ -#define FSI_MRESP0 0xd0 /* W: Port reset */ -#define FSI_MESRB0 0x1d0 /* R: Master error status */ -#define FSI_MRESB0 0x1d0 /* W: Reset bridge */ -#define FSI_MECTRL 0x2e0 /* W: Error control */ - -/* MMODE: Mode control */ -#define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */ -#define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */ -#define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */ -#define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */ - /* MSB=1, LSB=0 is 0.8 ms */ - /* MSB=0, LSB=1 is 0.9 ms */ -#define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */ -#define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */ -#define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */ -#define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */ - -/* MRESB: Reset brindge */ -#define FSI_MRESB_RST_GEN 0x80000000 /* General reset */ -#define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */ - -/* MRESB: Reset port */ -#define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */ -#define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */ -#define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */ -#define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */ -#define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */ - -/* MECTRL: Error control */ -#define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */ - /* master 0 in error */ -#define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */ - #define FSI_ENGID_HUB_MASTER 0x1c -#define FSI_HUB_LINK_OFFSET 0x80000 -#define FSI_HUB_LINK_SIZE 0x80000 -#define FSI_HUB_MASTER_MAX_LINKS 8 #define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ diff --git a/drivers/fsi/fsi-master.h b/drivers/fsi/fsi-master.h index c7174237e864..6e8d4d4d5149 100644 --- a/drivers/fsi/fsi-master.h +++ b/drivers/fsi/fsi-master.h @@ -12,6 +12,71 @@ #include <linux/device.h> #include <linux/mutex.h> +/* + * Master registers + * + * These are used by hardware masters, such as the one in the FSP2, AST2600 and + * the hub master in POWER processors. + */ + +/* Control Registers */ +#define FSI_MMODE 0x0 /* R/W: mode */ +#define FSI_MDLYR 0x4 /* R/W: delay */ +#define FSI_MCRSP 0x8 /* R/W: clock rate */ +#define FSI_MENP0 0x10 /* R/W: enable */ +#define FSI_MLEVP0 0x18 /* R: plug detect */ +#define FSI_MSENP0 0x18 /* S: Set enable */ +#define FSI_MCENP0 0x20 /* C: Clear enable */ +#define FSI_MAEB 0x70 /* R: Error address */ +#define FSI_MVER 0x74 /* R: master version/type */ +#define FSI_MSTAP0 0xd0 /* R: Port status */ +#define FSI_MRESP0 0xd0 /* W: Port reset */ +#define FSI_MESRB0 0x1d0 /* R: Master error status */ +#define FSI_MRESB0 0x1d0 /* W: Reset bridge */ +#define FSI_MSCSB0 0x1d4 /* R: Master sub command stack */ +#define FSI_MATRB0 0x1d8 /* R: Master address trace */ +#define FSI_MDTRB0 0x1dc /* R: Master data trace */ +#define FSI_MECTRL 0x2e0 /* W: Error control */ + +/* MMODE: Mode control */ +#define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */ +#define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */ +#define FSI_MMODE_RELA 0x20000000 /* Enable relative address commands */ +#define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */ +#define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */ + /* MSB=1, LSB=0 is 0.8 ms */ + /* MSB=0, LSB=1 is 0.9 ms */ +#define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */ +#define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */ +#define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */ +#define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */ + +/* MRESB: Reset brindge */ +#define FSI_MRESB_RST_GEN 0x80000000 /* General reset */ +#define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */ + +/* MRESP: Reset port */ +#define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */ +#define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */ +#define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */ +#define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */ +#define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */ + +/* MECTRL: Error control */ +#define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */ + /* master 0 in error */ +#define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */ + +#define FSI_HUB_LINK_OFFSET 0x80000 +#define FSI_HUB_LINK_SIZE 0x80000 +#define FSI_HUB_MASTER_MAX_LINKS 8 + +/* + * Protocol definitions + * + * These are used by low level masters that bit-bang out the protocol + */ + /* Various protocol delays */ #define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */ #define FSI_SEND_DELAY_CLOCKS 16 /* Number clocks for send delay */ @@ -47,6 +112,12 @@ /* fsi-master definition and flags */ #define FSI_MASTER_FLAG_SWCLOCK 0x1 +/* + * Structures and function prototypes + * + * These are common to all masters + */ + struct fsi_master { struct device dev; int idx; diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 13d80bfbc3b6..09e53c5f3b0a 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -52,6 +52,7 @@ struct aspeed_gpio_config { */ struct aspeed_gpio { struct gpio_chip chip; + struct irq_chip irqc; spinlock_t lock; void __iomem *base; int irq; @@ -661,12 +662,14 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc) struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct irq_chip *ic = irq_desc_get_chip(desc); struct aspeed_gpio *data = gpiochip_get_data(gc); - unsigned int i, p, girq; + unsigned int i, p, girq, banks; unsigned long reg; + struct aspeed_gpio *gpio = gpiochip_get_data(gc); chained_irq_enter(ic, desc); - for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) { + banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); + for (i = 0; i < banks; i++) { const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; reg = ioread32(bank_reg(data, bank, reg_irq_status)); @@ -681,16 +684,11 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(ic, desc); } -static struct irq_chip aspeed_gpio_irqchip = { - .name = "aspeed-gpio", - .irq_ack = aspeed_gpio_irq_ack, - .irq_mask = aspeed_gpio_irq_mask, - .irq_unmask = aspeed_gpio_irq_unmask, - .irq_set_type = aspeed_gpio_set_type, -}; - -static void set_irq_valid_mask(struct aspeed_gpio *gpio) +static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) { + struct aspeed_gpio *gpio = gpiochip_get_data(gc); const struct aspeed_bank_props *props = gpio->config->props; while (!is_bank_props_sentinel(props)) { @@ -701,42 +699,16 @@ static void set_irq_valid_mask(struct aspeed_gpio *gpio) for_each_clear_bit(offset, &input, 32) { unsigned int i = props->bank * 32 + offset; - if (i >= gpio->config->nr_gpios) + if (i >= gpio->chip.ngpio) break; - clear_bit(i, gpio->chip.irq.valid_mask); + clear_bit(i, valid_mask); } props++; } } -static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, - struct platform_device *pdev) -{ - int rc; - - rc = platform_get_irq(pdev, 0); - if (rc < 0) - return rc; - - gpio->irq = rc; - - set_irq_valid_mask(gpio); - - rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, - 0, handle_bad_irq, IRQ_TYPE_NONE); - if (rc) { - dev_info(&pdev->dev, "Could not add irqchip\n"); - return rc; - } - - gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, - gpio->irq, aspeed_gpio_irq_handler); - - return 0; -} - static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, unsigned int offset, bool enable) { @@ -1040,10 +1012,10 @@ int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, unsigned long flags; if (!gpio->cf_copro_bankmap) - gpio->cf_copro_bankmap = kzalloc(gpio->config->nr_gpios >> 3, GFP_KERNEL); + gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); if (!gpio->cf_copro_bankmap) return -ENOMEM; - if (offset < 0 || offset > gpio->config->nr_gpios) + if (offset < 0 || offset > gpio->chip.ngpio) return -EINVAL; bindex = offset >> 3; @@ -1088,7 +1060,7 @@ int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) if (!gpio->cf_copro_bankmap) return -ENXIO; - if (offset < 0 || offset > gpio->config->nr_gpios) + if (offset < 0 || offset > gpio->chip.ngpio) return -EINVAL; bindex = offset >> 3; @@ -1141,9 +1113,25 @@ static const struct aspeed_gpio_config ast2500_config = /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ { .nr_gpios = 232, .props = ast2500_bank_props, }; +static const struct aspeed_bank_props ast2600_bank_props[] = { + /* input output */ + {5, 0xffffffff, 0x0000ffff}, /* U/V/W/X */ + {6, 0xffff0000, 0x0fff0000}, /* Y/Z */ + { }, +}; + +static const struct aspeed_gpio_config ast2600_config = + /* + * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs. + * We expect ngpio being set in the device tree and this is a fallback + * option. + */ + { .nr_gpios = 208, .props = ast2600_bank_props, }; + static const struct of_device_id aspeed_gpio_of_table[] = { { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, + { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, }, {} }; MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); @@ -1152,7 +1140,8 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) { const struct of_device_id *gpio_id; struct aspeed_gpio *gpio; - int rc, i, banks; + int rc, i, banks, err; + u32 ngpio; gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); if (!gpio) @@ -1178,7 +1167,10 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) gpio->config = gpio_id->data; gpio->chip.parent = &pdev->dev; - gpio->chip.ngpio = gpio->config->nr_gpios; + err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); + gpio->chip.ngpio = (u16) ngpio; + if (err) + gpio->chip.ngpio = gpio->config->nr_gpios; gpio->chip.direction_input = aspeed_gpio_dir_in; gpio->chip.direction_output = aspeed_gpio_dir_out; gpio->chip.get_direction = aspeed_gpio_get_direction; @@ -1189,10 +1181,9 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) gpio->chip.set_config = aspeed_gpio_set_config; gpio->chip.label = dev_name(&pdev->dev); gpio->chip.base = -1; - gpio->chip.irq.need_valid_mask = true; /* Allocate a cache of the output registers */ - banks = gpio->config->nr_gpios >> 5; + banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); if (!gpio->dcache) @@ -1212,16 +1203,42 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); } - rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); - if (rc < 0) - return rc; + /* Optionally set up an irqchip if there is an IRQ */ + rc = platform_get_irq(pdev, 0); + if (rc > 0) { + struct gpio_irq_chip *girq; + + gpio->irq = rc; + girq = &gpio->chip.irq; + girq->chip = &gpio->irqc; + girq->chip->name = dev_name(&pdev->dev); + girq->chip->irq_ack = aspeed_gpio_irq_ack; + girq->chip->irq_mask = aspeed_gpio_irq_mask; + girq->chip->irq_unmask = aspeed_gpio_irq_unmask; + girq->chip->irq_set_type = aspeed_gpio_set_type; + girq->parent_handler = aspeed_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = gpio->irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->init_valid_mask = aspeed_init_irq_valid_mask; + } gpio->offset_timer = devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); if (!gpio->offset_timer) return -ENOMEM; - return aspeed_gpio_setup_irqs(gpio, pdev); + rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); + if (rc < 0) + return rc; + + return 0; } static struct platform_driver aspeed_gpio_driver = { diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c index dbf9cbe36b2b..994d542daf53 100644 --- a/drivers/gpio/gpio-stmpe.c +++ b/drivers/gpio/gpio-stmpe.c @@ -429,6 +429,23 @@ static irqreturn_t stmpe_gpio_irq(int irq, void *dev) return IRQ_HANDLED; } +static void stmpe_init_irq_valid_mask(struct gpio_chip *gc, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc); + int i; + + if (!stmpe_gpio->norequest_mask) + return; + + /* Forbid unused lines to be mapped as IRQs */ + for (i = 0; i < sizeof(u32); i++) { + if (stmpe_gpio->norequest_mask & BIT(i)) + clear_bit(i, valid_mask); + } +} + static int stmpe_gpio_probe(struct platform_device *pdev) { struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent); @@ -454,14 +471,21 @@ static int stmpe_gpio_probe(struct platform_device *pdev) stmpe_gpio->chip.parent = &pdev->dev; stmpe_gpio->chip.of_node = np; stmpe_gpio->chip.base = -1; + /* + * REVISIT: this makes sure the valid mask gets allocated and + * filled in when adding the gpio_chip, but the rest of the + * gpio_irqchip is still filled in using the old method + * in gpiochip_irqchip_add_nested() so clean this up once we + * get the gpio_irqchip to initialize while adding the + * gpio_chip also for threaded irqchips. + */ + stmpe_gpio->chip.irq.init_valid_mask = stmpe_init_irq_valid_mask; if (IS_ENABLED(CONFIG_DEBUG_FS)) stmpe_gpio->chip.dbg_show = stmpe_dbg_show; of_property_read_u32(np, "st,norequest-mask", &stmpe_gpio->norequest_mask); - if (stmpe_gpio->norequest_mask) - stmpe_gpio->chip.irq.need_valid_mask = true; irq = platform_get_irq(pdev, 0); if (irq < 0) @@ -487,14 +511,6 @@ static int stmpe_gpio_probe(struct platform_device *pdev) dev_err(&pdev->dev, "unable to get irq: %d\n", ret); goto out_disable; } - if (stmpe_gpio->norequest_mask) { - int i; - - /* Forbid unused lines to be mapped as IRQs */ - for (i = 0; i < sizeof(u32); i++) - if (stmpe_gpio->norequest_mask & BIT(i)) - clear_bit(i, stmpe_gpio->chip.irq.valid_mask); - } ret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip, &stmpe_gpio_irq_chip, 0, diff --git a/drivers/gpio/gpio-tqmx86.c b/drivers/gpio/gpio-tqmx86.c index d5880db7f9d4..a3109bcaa0ac 100644 --- a/drivers/gpio/gpio-tqmx86.c +++ b/drivers/gpio/gpio-tqmx86.c @@ -214,11 +214,23 @@ static const struct dev_pm_ops tqmx86_gpio_dev_pm_ops = { tqmx86_gpio_runtime_resume, NULL) }; +static void tqmx86_init_irq_valid_mask(struct gpio_chip *chip, + unsigned long *valid_mask, + unsigned int ngpios) +{ + /* Only GPIOs 4-7 are valid for interrupts. Clear the others */ + clear_bit(0, valid_mask); + clear_bit(1, valid_mask); + clear_bit(2, valid_mask); + clear_bit(3, valid_mask); +} + static int tqmx86_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct tqmx86_gpio_data *gpio; struct gpio_chip *chip; + struct gpio_irq_chip *girq; void __iomem *io_base; struct resource *res; int ret, irq; @@ -259,17 +271,10 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) chip->get = tqmx86_gpio_get; chip->set = tqmx86_gpio_set; chip->ngpio = TQMX86_NGPIO; - chip->irq.need_valid_mask = true; chip->parent = pdev->dev.parent; pm_runtime_enable(&pdev->dev); - ret = devm_gpiochip_add_data(dev, chip, gpio); - if (ret) { - dev_err(dev, "Could not register GPIO chip\n"); - goto out_pm_dis; - } - if (irq) { struct irq_chip *irq_chip = &gpio->irq_chip; u8 irq_status; @@ -287,23 +292,28 @@ static int tqmx86_gpio_probe(struct platform_device *pdev) irq_status = tqmx86_gpio_read(gpio, TQMX86_GPIIS); tqmx86_gpio_write(gpio, irq_status, TQMX86_GPIIS); - ret = gpiochip_irqchip_add(chip, irq_chip, - 0, handle_simple_irq, - IRQ_TYPE_EDGE_BOTH); - if (ret) { - dev_err(dev, "Could not add irq chip\n"); + girq = &chip->irq; + girq->chip = irq_chip; + girq->parent_handler = tqmx86_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) { + ret = -ENOMEM; goto out_pm_dis; } - - gpiochip_set_chained_irqchip(chip, irq_chip, - irq, tqmx86_gpio_irq_handler); + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + girq->init_valid_mask = tqmx86_init_irq_valid_mask; } - /* Only GPIOs 4-7 are valid for interrupts. Clear the others */ - clear_bit(0, chip->irq.valid_mask); - clear_bit(1, chip->irq.valid_mask); - clear_bit(2, chip->irq.valid_mask); - clear_bit(3, chip->irq.valid_mask); + ret = devm_gpiochip_add_data(dev, chip, gpio); + if (ret) { + dev_err(dev, "Could not register GPIO chip\n"); + goto out_pm_dis; + } dev_info(dev, "GPIO functionality initialized with %d pins\n", chip->ngpio); diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 74a77001b1bd..2b73e57cd37f 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1627,15 +1627,19 @@ static struct gpio_chip *find_chip_by_name(const char *name) * The following is irqchip helper code for gpiochips. */ -static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip) +static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gc) { - if (!gpiochip->irq.need_valid_mask) + struct gpio_irq_chip *girq = &gc->irq; + + if (!girq->init_valid_mask) return 0; - gpiochip->irq.valid_mask = gpiochip_allocate_mask(gpiochip); - if (!gpiochip->irq.valid_mask) + girq->valid_mask = gpiochip_allocate_mask(gc); + if (!girq->valid_mask) return -ENOMEM; + girq->init_valid_mask(gc, girq->valid_mask, gc->ngpio); + return 0; } diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 650dd71f9724..c0623fa5ba41 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -1322,6 +1322,34 @@ config SENSORS_PCF8591 These devices are hard to detect and rarely found on mainstream hardware. If unsure, say N. +config SENSORS_PECI_CPUTEMP + tristate "PECI CPU temperature monitoring support" + depends on PECI + select MFD_INTEL_PECI_CLIENT + help + If you say yes here you get support for the generic Intel PECI + cputemp driver which provides Digital Thermal Sensor (DTS) thermal + readings of the CPU package and CPU cores that are accessible using + the PECI Client Command Suite via the processor PECI client. + Check Documentation/hwmon/peci-cputemp for details. + + This driver can also be built as a module. If so, the module + will be called peci-cputemp. + +config SENSORS_PECI_DIMMTEMP + tristate "PECI DIMM temperature monitoring support" + depends on PECI + select MFD_INTEL_PECI_CLIENT + help + If you say yes here you get support for the generic Intel PECI hwmon + driver which provides Digital Thermal Sensor (DTS) thermal readings of + DIMM components that are accessible using the PECI Client Command + Suite via the processor PECI client. + Check Documentation/hwmon/peci-dimmtemp for details. + + This driver can also be built as a module. If so, the module + will be called peci-dimmtemp. + source "drivers/hwmon/pmbus/Kconfig" config SENSORS_PWM_FAN diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 8db472ea04f0..22e0882ffc70 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -142,6 +142,8 @@ obj-$(CONFIG_SENSORS_NTC_THERMISTOR) += ntc_thermistor.o obj-$(CONFIG_SENSORS_PC87360) += pc87360.o obj-$(CONFIG_SENSORS_PC87427) += pc87427.o obj-$(CONFIG_SENSORS_PCF8591) += pcf8591.o +obj-$(CONFIG_SENSORS_PECI_CPUTEMP) += peci-cputemp.o +obj-$(CONFIG_SENSORS_PECI_DIMMTEMP) += peci-dimmtemp.o obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o diff --git a/drivers/hwmon/peci-cputemp.c b/drivers/hwmon/peci-cputemp.c new file mode 100644 index 000000000000..11880c86a854 --- /dev/null +++ b/drivers/hwmon/peci-cputemp.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Intel Corporation + +#include <linux/hwmon.h> +#include <linux/jiffies.h> +#include <linux/mfd/intel-peci-client.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include "peci-hwmon.h" + +#define DEFAULT_CHANNEL_NUMS 4 +#define CORETEMP_CHANNEL_NUMS CORE_NUMS_MAX +#define CPUTEMP_CHANNEL_NUMS (DEFAULT_CHANNEL_NUMS + CORETEMP_CHANNEL_NUMS) + +/* The RESOLVED_CORES register in PCU of a client CPU */ +#define REG_RESOLVED_CORES_BUS 1 +#define REG_RESOLVED_CORES_DEVICE 30 +#define REG_RESOLVED_CORES_FUNCTION 3 +#define REG_RESOLVED_CORES_OFFSET 0xB4 + +struct temp_group { + struct temp_data die; + struct temp_data tcontrol; + struct temp_data tthrottle; + struct temp_data tjmax; + struct temp_data core[CORETEMP_CHANNEL_NUMS]; +}; + +struct peci_cputemp { + struct peci_client_manager *mgr; + struct device *dev; + char name[PECI_NAME_SIZE]; + const struct cpu_gen_info *gen_info; + struct temp_group temp; + u32 core_mask; + u32 temp_config[CPUTEMP_CHANNEL_NUMS + 1]; + uint config_idx; + struct hwmon_channel_info temp_info; + const struct hwmon_channel_info *info[2]; + struct hwmon_chip_info chip; +}; + +enum cputemp_channels { + channel_die, + channel_tcontrol, + channel_tthrottle, + channel_tjmax, + channel_core, +}; + +static const u32 config_table[DEFAULT_CHANNEL_NUMS + 1] = { + /* Die temperature */ + HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | + HWMON_T_CRIT_HYST, + + /* Tcontrol temperature */ + HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_CRIT, + + /* Tthrottle temperature */ + HWMON_T_LABEL | HWMON_T_INPUT, + + /* Tjmax temperature */ + HWMON_T_LABEL | HWMON_T_INPUT, + + /* Core temperature - for all core channels */ + HWMON_T_LABEL | HWMON_T_INPUT | HWMON_T_MAX | HWMON_T_CRIT | + HWMON_T_CRIT_HYST, +}; + +static const char *cputemp_label[CPUTEMP_CHANNEL_NUMS] = { + "Die", + "Tcontrol", + "Tthrottle", + "Tjmax", + "Core 0", "Core 1", "Core 2", "Core 3", + "Core 4", "Core 5", "Core 6", "Core 7", + "Core 8", "Core 9", "Core 10", "Core 11", + "Core 12", "Core 13", "Core 14", "Core 15", + "Core 16", "Core 17", "Core 18", "Core 19", + "Core 20", "Core 21", "Core 22", "Core 23", + "Core 24", "Core 25", "Core 26", "Core 27", +}; + +static s32 ten_dot_six_to_millidegree(s32 val) +{ + return ((val ^ 0x8000) - 0x8000) * 1000 / 64; +} + +static int get_temp_targets(struct peci_cputemp *priv) +{ + s32 tthrottle_offset; + s32 tcontrol_margin; + u8 pkg_cfg[4]; + int rc; + + /** + * Just use only the tcontrol marker to determine if target values need + * update. + */ + if (!peci_temp_need_update(&priv->temp.tcontrol)) + return 0; + + rc = peci_client_read_package_config(priv->mgr, + MBX_INDEX_TEMP_TARGET, 0, pkg_cfg); + if (rc) + return rc; + + priv->temp.tjmax.value = pkg_cfg[2] * 1000; + + tcontrol_margin = pkg_cfg[1]; + tcontrol_margin = ((tcontrol_margin ^ 0x80) - 0x80) * 1000; + priv->temp.tcontrol.value = priv->temp.tjmax.value - tcontrol_margin; + + tthrottle_offset = (pkg_cfg[3] & 0x2f) * 1000; + priv->temp.tthrottle.value = priv->temp.tjmax.value - tthrottle_offset; + + peci_temp_mark_updated(&priv->temp.tcontrol); + + return 0; +} + +static int get_die_temp(struct peci_cputemp *priv) +{ + struct peci_get_temp_msg msg; + int rc; + + if (!peci_temp_need_update(&priv->temp.die)) + return 0; + + msg.addr = priv->mgr->client->addr; + + rc = peci_command(priv->mgr->client->adapter, PECI_CMD_GET_TEMP, + &msg); + if (rc) + return rc; + + /* Note that the tjmax should be available before calling it */ + priv->temp.die.value = priv->temp.tjmax.value + + (msg.temp_raw * 1000 / 64); + + peci_temp_mark_updated(&priv->temp.die); + + return 0; +} + +static int get_core_temp(struct peci_cputemp *priv, int core_index) +{ + s32 core_dts_margin; + u8 pkg_cfg[4]; + int rc; + + if (!peci_temp_need_update(&priv->temp.core[core_index])) + return 0; + + rc = peci_client_read_package_config(priv->mgr, + MBX_INDEX_PER_CORE_DTS_TEMP, + core_index, pkg_cfg); + if (rc) + return rc; + + core_dts_margin = le16_to_cpup((__le16 *)pkg_cfg); + + /** + * Processors return a value of the core DTS reading in 10.6 format + * (10 bits signed decimal, 6 bits fractional). + * Error codes: + * 0x8000: General sensor error + * 0x8001: Reserved + * 0x8002: Underflow on reading value + * 0x8003-0x81ff: Reserved + */ + if (core_dts_margin >= 0x8000 && core_dts_margin <= 0x81ff) + return -EIO; + + core_dts_margin = ten_dot_six_to_millidegree(core_dts_margin); + + /* Note that the tjmax should be available before calling it */ + priv->temp.core[core_index].value = priv->temp.tjmax.value + + core_dts_margin; + + peci_temp_mark_updated(&priv->temp.core[core_index]); + + return 0; +} + +static int cputemp_read_string(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + if (attr != hwmon_temp_label) + return -EOPNOTSUPP; + + *str = cputemp_label[channel]; + return 0; +} + +static int cputemp_read(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct peci_cputemp *priv = dev_get_drvdata(dev); + int rc, core_index; + + if (channel >= CPUTEMP_CHANNEL_NUMS || + !(priv->temp_config[channel] & BIT(attr))) + return -EOPNOTSUPP; + + rc = get_temp_targets(priv); + if (rc) + return rc; + + switch (attr) { + case hwmon_temp_input: + switch (channel) { + case channel_die: + rc = get_die_temp(priv); + if (rc) + break; + + *val = priv->temp.die.value; + break; + case channel_tcontrol: + *val = priv->temp.tcontrol.value; + break; + case channel_tthrottle: + *val = priv->temp.tthrottle.value; + break; + case channel_tjmax: + *val = priv->temp.tjmax.value; + break; + default: + core_index = channel - DEFAULT_CHANNEL_NUMS; + rc = get_core_temp(priv, core_index); + if (rc) + break; + + *val = priv->temp.core[core_index].value; + break; + } + break; + case hwmon_temp_max: + *val = priv->temp.tcontrol.value; + break; + case hwmon_temp_crit: + *val = priv->temp.tjmax.value; + break; + case hwmon_temp_crit_hyst: + *val = priv->temp.tjmax.value - priv->temp.tcontrol.value; + break; + default: + rc = -EOPNOTSUPP; + break; + } + + return rc; +} + +static umode_t cputemp_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct peci_cputemp *priv = data; + + if (priv->temp_config[channel] & BIT(attr)) + if (channel < DEFAULT_CHANNEL_NUMS || + (channel >= DEFAULT_CHANNEL_NUMS && + (priv->core_mask & BIT(channel - DEFAULT_CHANNEL_NUMS)))) + return 0444; + + return 0; +} + +static const struct hwmon_ops cputemp_ops = { + .is_visible = cputemp_is_visible, + .read_string = cputemp_read_string, + .read = cputemp_read, +}; + +static int check_resolved_cores(struct peci_cputemp *priv) +{ + struct peci_rd_pci_cfg_local_msg msg; + int rc; + + /* Get the RESOLVED_CORES register value */ + msg.addr = priv->mgr->client->addr; + msg.bus = REG_RESOLVED_CORES_BUS; + msg.device = REG_RESOLVED_CORES_DEVICE; + msg.function = REG_RESOLVED_CORES_FUNCTION; + msg.reg = REG_RESOLVED_CORES_OFFSET; + msg.rx_len = 4; + + rc = peci_command(priv->mgr->client->adapter, + PECI_CMD_RD_PCI_CFG_LOCAL, &msg); + if (rc) + return rc; + + priv->core_mask = le32_to_cpup((__le32 *)msg.pci_config); + if (!priv->core_mask) + return -EAGAIN; + + dev_dbg(priv->dev, "Scanned resolved cores: 0x%x\n", priv->core_mask); + return 0; +} + +static int create_core_temp_info(struct peci_cputemp *priv) +{ + int rc, i; + + rc = check_resolved_cores(priv); + if (rc) + return rc; + + for (i = 0; i < priv->gen_info->core_max; i++) + if (priv->core_mask & BIT(i)) + while (i + DEFAULT_CHANNEL_NUMS >= priv->config_idx) + priv->temp_config[priv->config_idx++] = + config_table[channel_core]; + + return 0; +} + +static int peci_cputemp_probe(struct platform_device *pdev) +{ + struct peci_client_manager *mgr = dev_get_drvdata(pdev->dev.parent); + struct device *dev = &pdev->dev; + struct peci_cputemp *priv; + struct device *hwmon_dev; + int rc; + + if ((mgr->client->adapter->cmd_mask & + (BIT(PECI_CMD_GET_TEMP) | BIT(PECI_CMD_RD_PKG_CFG))) != + (BIT(PECI_CMD_GET_TEMP) | BIT(PECI_CMD_RD_PKG_CFG))) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + priv->mgr = mgr; + priv->dev = dev; + priv->gen_info = mgr->gen_info; + + snprintf(priv->name, PECI_NAME_SIZE, "peci_cputemp.cpu%d", + mgr->client->addr - PECI_BASE_ADDR); + + priv->temp_config[priv->config_idx++] = config_table[channel_die]; + priv->temp_config[priv->config_idx++] = config_table[channel_tcontrol]; + priv->temp_config[priv->config_idx++] = config_table[channel_tthrottle]; + priv->temp_config[priv->config_idx++] = config_table[channel_tjmax]; + + rc = create_core_temp_info(priv); + if (rc) + dev_dbg(dev, "Skipped creating core temp info\n"); + + priv->chip.ops = &cputemp_ops; + priv->chip.info = priv->info; + + priv->info[0] = &priv->temp_info; + + priv->temp_info.type = hwmon_temp; + priv->temp_info.config = priv->temp_config; + + hwmon_dev = devm_hwmon_device_register_with_info(priv->dev, + priv->name, + priv, + &priv->chip, + NULL); + + if (IS_ERR(hwmon_dev)) + return PTR_ERR(hwmon_dev); + + dev_dbg(dev, "%s: sensor '%s'\n", dev_name(hwmon_dev), priv->name); + + return 0; +} + +static const struct platform_device_id peci_cputemp_ids[] = { + { .name = "peci-cputemp", .driver_data = 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, peci_cputemp_ids); + +static struct platform_driver peci_cputemp_driver = { + .probe = peci_cputemp_probe, + .id_table = peci_cputemp_ids, + .driver = { .name = "peci-cputemp", }, +}; +module_platform_driver(peci_cputemp_driver); + +MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>"); +MODULE_DESCRIPTION("PECI cputemp driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwmon/peci-dimmtemp.c b/drivers/hwmon/peci-dimmtemp.c new file mode 100644 index 000000000000..86a45a90805b --- /dev/null +++ b/drivers/hwmon/peci-dimmtemp.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Intel Corporation + +#include <linux/hwmon.h> +#include <linux/jiffies.h> +#include <linux/mfd/intel-peci-client.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/workqueue.h> +#include "peci-hwmon.h" + +#define DIMM_MASK_CHECK_DELAY_JIFFIES msecs_to_jiffies(5000) +#define DIMM_MASK_CHECK_RETRY_MAX 60 /* 60 x 5 secs = 5 minutes */ + +struct peci_dimmtemp { + struct peci_client_manager *mgr; + struct device *dev; + char name[PECI_NAME_SIZE]; + const struct cpu_gen_info *gen_info; + struct workqueue_struct *work_queue; + struct delayed_work work_handler; + struct temp_data temp[DIMM_NUMS_MAX]; + u32 dimm_mask; + int retry_count; + u32 temp_config[DIMM_NUMS_MAX + 1]; + struct hwmon_channel_info temp_info; + const struct hwmon_channel_info *info[2]; + struct hwmon_chip_info chip; +}; + +static const char *dimmtemp_label[CHAN_RANK_MAX][DIMM_IDX_MAX] = { + { "DIMM A1", "DIMM A2", "DIMM A3" }, + { "DIMM B1", "DIMM B2", "DIMM B3" }, + { "DIMM C1", "DIMM C2", "DIMM C3" }, + { "DIMM D1", "DIMM D2", "DIMM D3" }, + { "DIMM E1", "DIMM E2", "DIMM E3" }, + { "DIMM F1", "DIMM F2", "DIMM F3" }, + { "DIMM G1", "DIMM G2", "DIMM G3" }, + { "DIMM H1", "DIMM H2", "DIMM H3" }, +}; + +static int get_dimm_temp(struct peci_dimmtemp *priv, int dimm_no) +{ + int dimm_order = dimm_no % priv->gen_info->dimm_idx_max; + int chan_rank = dimm_no / priv->gen_info->dimm_idx_max; + u8 cfg_data[4]; + int rc; + + if (!peci_temp_need_update(&priv->temp[dimm_no])) + return 0; + + rc = peci_client_read_package_config(priv->mgr, + MBX_INDEX_DDR_DIMM_TEMP, + chan_rank, cfg_data); + if (rc) + return rc; + + priv->temp[dimm_no].value = cfg_data[dimm_order] * 1000; + + peci_temp_mark_updated(&priv->temp[dimm_no]); + + return 0; +} + +static int dimmtemp_read_string(struct device *dev, + enum hwmon_sensor_types type, + u32 attr, int channel, const char **str) +{ + struct peci_dimmtemp *priv = dev_get_drvdata(dev); + u32 dimm_idx_max = priv->gen_info->dimm_idx_max; + int chan_rank, dimm_idx; + + if (attr != hwmon_temp_label) + return -EOPNOTSUPP; + + chan_rank = channel / dimm_idx_max; + dimm_idx = channel % dimm_idx_max; + *str = dimmtemp_label[chan_rank][dimm_idx]; + return 0; +} + +static int dimmtemp_read(struct device *dev, enum hwmon_sensor_types type, + u32 attr, int channel, long *val) +{ + struct peci_dimmtemp *priv = dev_get_drvdata(dev); + int rc; + + if (attr != hwmon_temp_input) + return -EOPNOTSUPP; + + rc = get_dimm_temp(priv, channel); + if (rc) + return rc; + + *val = priv->temp[channel].value; + return 0; +} + +static umode_t dimmtemp_is_visible(const void *data, + enum hwmon_sensor_types type, + u32 attr, int channel) +{ + const struct peci_dimmtemp *priv = data; + + if (priv->temp_config[channel] & BIT(attr) && + priv->dimm_mask & BIT(channel)) + return 0444; + + return 0; +} + +static const struct hwmon_ops dimmtemp_ops = { + .is_visible = dimmtemp_is_visible, + .read_string = dimmtemp_read_string, + .read = dimmtemp_read, +}; + +static int check_populated_dimms(struct peci_dimmtemp *priv) +{ + u32 chan_rank_max = priv->gen_info->chan_rank_max; + u32 dimm_idx_max = priv->gen_info->dimm_idx_max; + int chan_rank, dimm_idx, rc; + u8 cfg_data[4]; + + for (chan_rank = 0; chan_rank < chan_rank_max; chan_rank++) { + rc = peci_client_read_package_config(priv->mgr, + MBX_INDEX_DDR_DIMM_TEMP, + chan_rank, cfg_data); + if (rc) { + priv->dimm_mask = 0; + return rc; + } + + for (dimm_idx = 0; dimm_idx < dimm_idx_max; dimm_idx++) + if (cfg_data[dimm_idx]) + priv->dimm_mask |= BIT(chan_rank * + dimm_idx_max + + dimm_idx); + } + + if (!priv->dimm_mask) + return -EAGAIN; + + dev_dbg(priv->dev, "Scanned populated DIMMs: 0x%x\n", priv->dimm_mask); + return 0; +} + +static int create_dimm_temp_info(struct peci_dimmtemp *priv) +{ + int rc, i, config_idx, channels; + struct device *hwmon_dev; + + rc = check_populated_dimms(priv); + if (rc) { + if (rc == -EAGAIN) { + if (priv->retry_count < DIMM_MASK_CHECK_RETRY_MAX) { + queue_delayed_work(priv->work_queue, + &priv->work_handler, + DIMM_MASK_CHECK_DELAY_JIFFIES); + priv->retry_count++; + dev_dbg(priv->dev, + "Deferred DIMM temp info creation\n"); + } else { + dev_err(priv->dev, + "Timeout DIMM temp info creation\n"); + rc = -ETIMEDOUT; + } + } + + return rc; + } + + channels = priv->gen_info->chan_rank_max * + priv->gen_info->dimm_idx_max; + for (i = 0, config_idx = 0; i < channels; i++) + if (priv->dimm_mask & BIT(i)) + while (i >= config_idx) + priv->temp_config[config_idx++] = + HWMON_T_LABEL | HWMON_T_INPUT; + + priv->chip.ops = &dimmtemp_ops; + priv->chip.info = priv->info; + + priv->info[0] = &priv->temp_info; + + priv->temp_info.type = hwmon_temp; + priv->temp_info.config = priv->temp_config; + + hwmon_dev = devm_hwmon_device_register_with_info(priv->dev, + priv->name, + priv, + &priv->chip, + NULL); + rc = PTR_ERR_OR_ZERO(hwmon_dev); + if (!rc) + dev_dbg(priv->dev, "%s: sensor '%s'\n", + dev_name(hwmon_dev), priv->name); + + return rc; +} + +static void create_dimm_temp_info_delayed(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct peci_dimmtemp *priv = container_of(dwork, struct peci_dimmtemp, + work_handler); + int rc; + + rc = create_dimm_temp_info(priv); + if (rc && rc != -EAGAIN) + dev_dbg(priv->dev, "Failed to create DIMM temp info\n"); +} + +static int peci_dimmtemp_probe(struct platform_device *pdev) +{ + struct peci_client_manager *mgr = dev_get_drvdata(pdev->dev.parent); + struct device *dev = &pdev->dev; + struct peci_dimmtemp *priv; + int rc; + + if ((mgr->client->adapter->cmd_mask & + (BIT(PECI_CMD_GET_TEMP) | BIT(PECI_CMD_RD_PKG_CFG))) != + (BIT(PECI_CMD_GET_TEMP) | BIT(PECI_CMD_RD_PKG_CFG))) + return -ENODEV; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + priv->mgr = mgr; + priv->dev = dev; + priv->gen_info = mgr->gen_info; + + snprintf(priv->name, PECI_NAME_SIZE, "peci_dimmtemp.cpu%d", + priv->mgr->client->addr - PECI_BASE_ADDR); + + priv->work_queue = alloc_ordered_workqueue(priv->name, 0); + if (!priv->work_queue) + return -ENOMEM; + + INIT_DELAYED_WORK(&priv->work_handler, create_dimm_temp_info_delayed); + + rc = create_dimm_temp_info(priv); + if (rc && rc != -EAGAIN) { + dev_err(dev, "Failed to create DIMM temp info\n"); + goto err_free_wq; + } + + return 0; + +err_free_wq: + destroy_workqueue(priv->work_queue); + return rc; +} + +static int peci_dimmtemp_remove(struct platform_device *pdev) +{ + struct peci_dimmtemp *priv = dev_get_drvdata(&pdev->dev); + + cancel_delayed_work_sync(&priv->work_handler); + destroy_workqueue(priv->work_queue); + + return 0; +} + +static const struct platform_device_id peci_dimmtemp_ids[] = { + { .name = "peci-dimmtemp", .driver_data = 0 }, + { } +}; +MODULE_DEVICE_TABLE(platform, peci_dimmtemp_ids); + +static struct platform_driver peci_dimmtemp_driver = { + .probe = peci_dimmtemp_probe, + .remove = peci_dimmtemp_remove, + .id_table = peci_dimmtemp_ids, + .driver = { .name = "peci-dimmtemp", }, +}; +module_platform_driver(peci_dimmtemp_driver); + +MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>"); +MODULE_DESCRIPTION("PECI dimmtemp driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/hwmon/peci-hwmon.h b/drivers/hwmon/peci-hwmon.h new file mode 100644 index 000000000000..6ca1855a86bb --- /dev/null +++ b/drivers/hwmon/peci-hwmon.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Intel Corporation */ + +#ifndef __PECI_HWMON_H +#define __PECI_HWMON_H + +#include <linux/peci.h> + +#define TEMP_TYPE_PECI 6 /* Sensor type 6: Intel PECI */ +#define UPDATE_INTERVAL HZ + +/** + * struct temp_data - PECI temperature information + * @valid: flag to indicate the temperature value is valid + * @value: temperature value in millidegree Celsius + * @last_updated: time of the last update in jiffies + */ +struct temp_data { + uint valid; + s32 value; + ulong last_updated; +}; + +/** + * peci_temp_need_update - check whether temperature update is needed or not + * @temp: pointer to temperature data struct + * + * Return: true if update is needed, false if not. + */ +static inline bool peci_temp_need_update(struct temp_data *temp) +{ + if (temp->valid && + time_before(jiffies, temp->last_updated + UPDATE_INTERVAL)) + return false; + + return true; +} + +/** + * peci_temp_mark_updated - mark the temperature is updated + * @temp: pointer to temperature data struct + */ +static inline void peci_temp_mark_updated(struct temp_data *temp) +{ + temp->valid = 1; + temp->last_updated = jiffies; +} + +#endif /* __PECI_HWMON_H */ diff --git a/drivers/hwmon/pmbus/ibm-cffps.c b/drivers/hwmon/pmbus/ibm-cffps.c index ee2ee9e3ffd7..d359b76bcb36 100644 --- a/drivers/hwmon/pmbus/ibm-cffps.c +++ b/drivers/hwmon/pmbus/ibm-cffps.c @@ -3,6 +3,7 @@ * Copyright 2017 IBM Corp. */ +#include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/debugfs.h> #include <linux/device.h> @@ -12,6 +13,7 @@ #include <linux/leds.h> #include <linux/module.h> #include <linux/mutex.h> +#include <linux/of_device.h> #include <linux/pmbus.h> #include "pmbus.h" @@ -20,13 +22,18 @@ #define CFFPS_PN_CMD 0x9B #define CFFPS_SN_CMD 0x9E #define CFFPS_CCIN_CMD 0xBD -#define CFFPS_FW_CMD_START 0xFA -#define CFFPS_FW_NUM_BYTES 4 +#define CFFPS_FW_CMD 0xFA +#define CFFPS1_FW_NUM_BYTES 4 +#define CFFPS2_FW_NUM_WORDS 3 #define CFFPS_SYS_CONFIG_CMD 0xDA #define CFFPS_INPUT_HISTORY_CMD 0xD6 #define CFFPS_INPUT_HISTORY_SIZE 100 +#define CFFPS_CCIN_VERSION GENMASK(15, 8) +#define CFFPS_CCIN_VERSION_1 0x2b +#define CFFPS_CCIN_VERSION_2 0x2e + /* STATUS_MFR_SPECIFIC bits */ #define CFFPS_MFR_FAN_FAULT BIT(0) #define CFFPS_MFR_THERMAL_FAULT BIT(1) @@ -37,9 +44,13 @@ #define CFFPS_MFR_VAUX_FAULT BIT(6) #define CFFPS_MFR_CURRENT_SHARE_WARNING BIT(7) +/* + * LED off state actually relinquishes LED control to PSU firmware, so it can + * turn on the LED for faults. + */ +#define CFFPS_LED_OFF 0 #define CFFPS_LED_BLINK BIT(0) #define CFFPS_LED_ON BIT(1) -#define CFFPS_LED_OFF BIT(2) #define CFFPS_BLINK_RATE_MS 250 enum { @@ -52,6 +63,8 @@ enum { CFFPS_DEBUGFS_NUM_ENTRIES }; +enum versions { cffps1, cffps2, cffps_unknown }; + struct ibm_cffps_input_history { struct mutex update_lock; unsigned long last_update; @@ -61,6 +74,7 @@ struct ibm_cffps_input_history { }; struct ibm_cffps { + enum versions version; struct i2c_client *client; struct ibm_cffps_input_history input_history; @@ -132,6 +146,8 @@ static ssize_t ibm_cffps_debugfs_op(struct file *file, char __user *buf, struct ibm_cffps *psu = to_psu(idxp, idx); char data[I2C_SMBUS_BLOCK_MAX] = { 0 }; + pmbus_set_page(psu->client, 0); + switch (idx) { case CFFPS_DEBUGFS_INPUT_HISTORY: return ibm_cffps_read_input_history(psu, buf, count, ppos); @@ -152,16 +168,36 @@ static ssize_t ibm_cffps_debugfs_op(struct file *file, char __user *buf, rc = snprintf(data, 5, "%04X", rc); goto done; case CFFPS_DEBUGFS_FW: - for (i = 0; i < CFFPS_FW_NUM_BYTES; ++i) { - rc = i2c_smbus_read_byte_data(psu->client, - CFFPS_FW_CMD_START + i); - if (rc < 0) - return rc; + switch (psu->version) { + case cffps1: + for (i = 0; i < CFFPS1_FW_NUM_BYTES; ++i) { + rc = i2c_smbus_read_byte_data(psu->client, + CFFPS_FW_CMD + + i); + if (rc < 0) + return rc; + + snprintf(&data[i * 2], 3, "%02X", rc); + } - snprintf(&data[i * 2], 3, "%02X", rc); - } + rc = i * 2; + break; + case cffps2: + for (i = 0; i < CFFPS2_FW_NUM_WORDS; ++i) { + rc = i2c_smbus_read_word_data(psu->client, + CFFPS_FW_CMD + + i); + if (rc < 0) + return rc; + + snprintf(&data[i * 4], 5, "%04X", rc); + } - rc = i * 2; + rc = i * 4; + break; + default: + return -EOPNOTSUPP; + } goto done; default: return -EINVAL; @@ -265,26 +301,38 @@ static int ibm_cffps_read_word_data(struct i2c_client *client, int page, return rc; } -static void ibm_cffps_led_brightness_set(struct led_classdev *led_cdev, - enum led_brightness brightness) +static int ibm_cffps_led_brightness_set(struct led_classdev *led_cdev, + enum led_brightness brightness) { int rc; + u8 next_led_state; struct ibm_cffps *psu = container_of(led_cdev, struct ibm_cffps, led); if (brightness == LED_OFF) { - psu->led_state = CFFPS_LED_OFF; + next_led_state = CFFPS_LED_OFF; } else { brightness = LED_FULL; + if (psu->led_state != CFFPS_LED_BLINK) - psu->led_state = CFFPS_LED_ON; + next_led_state = CFFPS_LED_ON; + else + next_led_state = CFFPS_LED_BLINK; } + dev_dbg(&psu->client->dev, "LED brightness set: %d. Command: %d.\n", + brightness, next_led_state); + + pmbus_set_page(psu->client, 0); + rc = i2c_smbus_write_byte_data(psu->client, CFFPS_SYS_CONFIG_CMD, - psu->led_state); + next_led_state); if (rc < 0) - return; + return rc; + psu->led_state = next_led_state; led_cdev->brightness = brightness; + + return 0; } static int ibm_cffps_led_blink_set(struct led_classdev *led_cdev, @@ -294,16 +342,17 @@ static int ibm_cffps_led_blink_set(struct led_classdev *led_cdev, int rc; struct ibm_cffps *psu = container_of(led_cdev, struct ibm_cffps, led); - psu->led_state = CFFPS_LED_BLINK; + dev_dbg(&psu->client->dev, "LED blink set.\n"); - if (led_cdev->brightness == LED_OFF) - return 0; + pmbus_set_page(psu->client, 0); rc = i2c_smbus_write_byte_data(psu->client, CFFPS_SYS_CONFIG_CMD, CFFPS_LED_BLINK); if (rc < 0) return rc; + psu->led_state = CFFPS_LED_BLINK; + led_cdev->brightness = LED_FULL; *delay_on = CFFPS_BLINK_RATE_MS; *delay_off = CFFPS_BLINK_RATE_MS; @@ -320,7 +369,7 @@ static void ibm_cffps_create_led_class(struct ibm_cffps *psu) client->addr); psu->led.name = psu->led_name; psu->led.max_brightness = LED_FULL; - psu->led.brightness_set = ibm_cffps_led_brightness_set; + psu->led.brightness_set_blocking = ibm_cffps_led_brightness_set; psu->led.blink_set = ibm_cffps_led_blink_set; rc = devm_led_classdev_register(dev, &psu->led); @@ -328,15 +377,32 @@ static void ibm_cffps_create_led_class(struct ibm_cffps *psu) dev_warn(dev, "failed to register led class: %d\n", rc); } -static struct pmbus_driver_info ibm_cffps_info = { - .pages = 1, - .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | - PMBUS_HAVE_PIN | PMBUS_HAVE_FAN12 | PMBUS_HAVE_TEMP | - PMBUS_HAVE_TEMP2 | PMBUS_HAVE_TEMP3 | PMBUS_HAVE_STATUS_VOUT | - PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_STATUS_INPUT | - PMBUS_HAVE_STATUS_TEMP | PMBUS_HAVE_STATUS_FAN12, - .read_byte_data = ibm_cffps_read_byte_data, - .read_word_data = ibm_cffps_read_word_data, +static struct pmbus_driver_info ibm_cffps_info[] = { + [cffps1] = { + .pages = 1, + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | + PMBUS_HAVE_PIN | PMBUS_HAVE_FAN12 | PMBUS_HAVE_TEMP | + PMBUS_HAVE_TEMP2 | PMBUS_HAVE_TEMP3 | + PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_STATUS_IOUT | + PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_TEMP | + PMBUS_HAVE_STATUS_FAN12, + .read_byte_data = ibm_cffps_read_byte_data, + .read_word_data = ibm_cffps_read_word_data, + }, + [cffps2] = { + .pages = 2, + .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | + PMBUS_HAVE_PIN | PMBUS_HAVE_FAN12 | PMBUS_HAVE_TEMP | + PMBUS_HAVE_TEMP2 | PMBUS_HAVE_TEMP3 | + PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_STATUS_IOUT | + PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_TEMP | + PMBUS_HAVE_STATUS_FAN12, + .func[1] = PMBUS_HAVE_VOUT | PMBUS_HAVE_IOUT | + PMBUS_HAVE_TEMP | PMBUS_HAVE_TEMP2 | PMBUS_HAVE_TEMP3 | + PMBUS_HAVE_STATUS_VOUT | PMBUS_HAVE_STATUS_IOUT, + .read_byte_data = ibm_cffps_read_byte_data, + .read_word_data = ibm_cffps_read_word_data, + }, }; static struct pmbus_platform_data ibm_cffps_pdata = { @@ -347,12 +413,40 @@ static int ibm_cffps_probe(struct i2c_client *client, const struct i2c_device_id *id) { int i, rc; + enum versions vs = cffps_unknown; struct dentry *debugfs; struct dentry *ibm_cffps_dir; struct ibm_cffps *psu; + const void *md = of_device_get_match_data(&client->dev); + + if (md) + vs = (enum versions)md; + else if (id) + vs = (enum versions)id->driver_data; + + if (vs == cffps_unknown) { + u16 ccin_version = CFFPS_CCIN_VERSION_1; + int ccin = i2c_smbus_read_word_swapped(client, CFFPS_CCIN_CMD); + + if (ccin > 0) + ccin_version = FIELD_GET(CFFPS_CCIN_VERSION, ccin); + + switch (ccin_version) { + default: + case CFFPS_CCIN_VERSION_1: + vs = cffps1; + break; + case CFFPS_CCIN_VERSION_2: + vs = cffps2; + break; + } + + /* Set the client name to include the version number. */ + snprintf(client->name, I2C_NAME_SIZE, "cffps%d", vs + 1); + } client->dev.platform_data = &ibm_cffps_pdata; - rc = pmbus_do_probe(client, id, &ibm_cffps_info); + rc = pmbus_do_probe(client, id, &ibm_cffps_info[vs]); if (rc) return rc; @@ -364,6 +458,7 @@ static int ibm_cffps_probe(struct i2c_client *client, if (!psu) return 0; + psu->version = vs; psu->client = client; mutex_init(&psu->input_history.update_lock); psu->input_history.last_update = jiffies - HZ; @@ -405,13 +500,26 @@ static int ibm_cffps_probe(struct i2c_client *client, } static const struct i2c_device_id ibm_cffps_id[] = { - { "ibm_cffps1", 1 }, + { "ibm_cffps1", cffps1 }, + { "ibm_cffps2", cffps2 }, + { "ibm_cffps", cffps_unknown }, {} }; MODULE_DEVICE_TABLE(i2c, ibm_cffps_id); static const struct of_device_id ibm_cffps_of_match[] = { - { .compatible = "ibm,cffps1" }, + { + .compatible = "ibm,cffps1", + .data = (void *)cffps1 + }, + { + .compatible = "ibm,cffps2", + .data = (void *)cffps2 + }, + { + .compatible = "ibm,cffps", + .data = (void *)cffps_unknown + }, {} }; MODULE_DEVICE_TABLE(of, ibm_cffps_of_match); diff --git a/drivers/hwmon/pmbus/max31785.c b/drivers/hwmon/pmbus/max31785.c index 69d9029ea410..209cb559e549 100644 --- a/drivers/hwmon/pmbus/max31785.c +++ b/drivers/hwmon/pmbus/max31785.c @@ -12,40 +12,126 @@ enum max31785_regs { MFR_REVISION = 0x9b, + MFR_FAULT_RESPONSE = 0xd9, + MFR_TEMP_SENSOR_CONFIG = 0xf0, MFR_FAN_CONFIG = 0xf1, + MFR_FAN_FAULT_LIMIT = 0xf5, }; #define MAX31785 0x3030 #define MAX31785A 0x3040 #define MFR_FAN_CONFIG_DUAL_TACH BIT(12) +#define MFR_FAN_CONFIG_TSFO BIT(9) +#define MFR_FAN_CONFIG_TACHO BIT(8) +#define MFR_FAN_CONFIG_HEALTH BIT(4) +#define MFR_FAN_CONFIG_ROTOR_HI_LO BIT(3) +#define MFR_FAN_CONFIG_ROTOR BIT(2) + +#define MFR_FAULT_RESPONSE_MONITOR BIT(0) #define MAX31785_NR_PAGES 23 #define MAX31785_NR_FAN_PAGES 6 +/* + * MAX31785 dragons ahead + * + * We see weird issues where some transfers fail. There doesn't appear to be + * any pattern to the problem, so below we wrap all the read/write calls with a + * retry. The device provides no indication of this besides NACK'ing master + * Txs; no bits are set in STATUS_BYTE to suggest anything has gone wrong. + */ + +#define max31785_retry(_func, ...) ({ \ + /* All relevant functions return int, sue me */ \ + int _ret = _func(__VA_ARGS__); \ + if (_ret == -EIO) \ + _ret = _func(__VA_ARGS__); \ + _ret; \ +}) + +static int max31785_i2c_smbus_read_byte_data(struct i2c_client *client, + int command) +{ + return max31785_retry(i2c_smbus_read_byte_data, client, command); +} + + +static int max31785_i2c_smbus_write_byte_data(struct i2c_client *client, + int command, u16 data) +{ + return max31785_retry(i2c_smbus_write_byte_data, client, command, data); +} + +static int max31785_i2c_smbus_read_word_data(struct i2c_client *client, + int command) +{ + return max31785_retry(i2c_smbus_read_word_data, client, command); +} + +static int max31785_i2c_smbus_write_word_data(struct i2c_client *client, + int command, u16 data) +{ + return max31785_retry(i2c_smbus_write_word_data, client, command, data); +} + +static int max31785_pmbus_write_byte(struct i2c_client *client, int page, + u8 value) +{ + return max31785_retry(pmbus_write_byte, client, page, value); +} + +static int max31785_pmbus_read_byte_data(struct i2c_client *client, int page, + int command) +{ + return max31785_retry(pmbus_read_byte_data, client, page, command); +} + +static int max31785_pmbus_write_byte_data(struct i2c_client *client, int page, + int command, u16 data) +{ + return max31785_retry(pmbus_write_byte_data, client, page, command, + data); +} + +static int max31785_pmbus_read_word_data(struct i2c_client *client, int page, + int command) +{ + return max31785_retry(pmbus_read_word_data, client, page, command); +} + +static int max31785_pmbus_write_word_data(struct i2c_client *client, int page, + int command, u16 data) +{ + return max31785_retry(pmbus_write_word_data, client, page, command, + data); +} + static int max31785_read_byte_data(struct i2c_client *client, int page, int reg) { - if (page < MAX31785_NR_PAGES) - return -ENODATA; - switch (reg) { case PMBUS_VOUT_MODE: - return -ENOTSUPP; + if (page >= MAX31785_NR_PAGES) + return -ENOTSUPP; + break; case PMBUS_FAN_CONFIG_12: - return pmbus_read_byte_data(client, page - MAX31785_NR_PAGES, - reg); + if (page >= MAX31785_NR_PAGES) + return max31785_pmbus_read_byte_data(client, + page - MAX31785_NR_PAGES, + reg); + break; } - return -ENODATA; + return max31785_pmbus_read_byte_data(client, page, reg); } static int max31785_write_byte(struct i2c_client *client, int page, u8 value) { - if (page < MAX31785_NR_PAGES) - return -ENODATA; + if (page >= MAX31785_NR_PAGES) + return -ENOTSUPP; - return -ENOTSUPP; + return max31785_pmbus_write_byte(client, page, value); } static int max31785_read_long_data(struct i2c_client *client, int page, @@ -106,11 +192,13 @@ static int max31785_get_pwm_mode(struct i2c_client *client, int page) int config; int command; - config = pmbus_read_byte_data(client, page, PMBUS_FAN_CONFIG_12); + config = max31785_pmbus_read_byte_data(client, page, + PMBUS_FAN_CONFIG_12); if (config < 0) return config; - command = pmbus_read_word_data(client, page, PMBUS_FAN_COMMAND_1); + command = max31785_pmbus_read_word_data(client, page, + PMBUS_FAN_COMMAND_1); if (command < 0) return command; @@ -134,15 +222,14 @@ static int max31785_read_word_data(struct i2c_client *client, int page, switch (reg) { case PMBUS_READ_FAN_SPEED_1: if (page < MAX31785_NR_PAGES) - return -ENODATA; + return max31785_pmbus_read_word_data(client, page, reg); rv = max31785_read_long_data(client, page - MAX31785_NR_PAGES, reg, &val); if (rv < 0) return rv; - rv = (val >> 16) & 0xffff; - break; + return (val >> 16) & 0xffff; case PMBUS_FAN_COMMAND_1: /* * PMBUS_FAN_COMMAND_x is probed to judge whether or not to @@ -150,20 +237,28 @@ static int max31785_read_word_data(struct i2c_client *client, int page, * * Don't expose fan_target attribute for virtual pages. */ - rv = (page >= MAX31785_NR_PAGES) ? -ENOTSUPP : -ENODATA; + if (page >= MAX31785_NR_PAGES) + return -ENOTSUPP; break; + case PMBUS_VIRT_FAN_TARGET_1: + if (page >= MAX31785_NR_PAGES) + return -ENOTSUPP; + + return -ENODATA; case PMBUS_VIRT_PWM_1: - rv = max31785_get_pwm(client, page); - break; + return max31785_get_pwm(client, page); case PMBUS_VIRT_PWM_ENABLE_1: - rv = max31785_get_pwm_mode(client, page); - break; + return max31785_get_pwm_mode(client, page); default: - rv = -ENODATA; + if (page >= MAX31785_NR_PAGES) + return -ENXIO; break; } - return rv; + if (reg >= PMBUS_VIRT_BASE) + return -ENXIO; + + return max31785_pmbus_read_word_data(client, page, reg); } static inline u32 max31785_scale_pwm(u32 sensor_val) @@ -187,6 +282,31 @@ static inline u32 max31785_scale_pwm(u32 sensor_val) return (sensor_val * 100) / 255; } +static int max31785_update_fan(struct i2c_client *client, int page, + u8 config, u8 mask, u16 command) +{ + int from, rv; + u8 to; + + from = max31785_pmbus_read_byte_data(client, page, PMBUS_FAN_CONFIG_12); + if (from < 0) + return from; + + to = (from & ~mask) | (config & mask); + + if (to != from) { + rv = max31785_pmbus_write_byte_data(client, page, + PMBUS_FAN_CONFIG_12, to); + if (rv < 0) + return rv; + } + + rv = max31785_pmbus_write_word_data(client, page, PMBUS_FAN_COMMAND_1, + command); + + return rv; +} + static int max31785_pwm_enable(struct i2c_client *client, int page, u16 word) { @@ -216,15 +336,18 @@ static int max31785_pwm_enable(struct i2c_client *client, int page, return -EINVAL; } - return pmbus_update_fan(client, page, 0, config, PB_FAN_1_RPM, rate); + return max31785_update_fan(client, page, config, PB_FAN_1_RPM, rate); } static int max31785_write_word_data(struct i2c_client *client, int page, int reg, u16 word) { switch (reg) { + case PMBUS_VIRT_FAN_TARGET_1: + return max31785_update_fan(client, page, PB_FAN_1_RPM, + PB_FAN_1_RPM, word); case PMBUS_VIRT_PWM_1: - return pmbus_update_fan(client, page, 0, 0, PB_FAN_1_RPM, + return max31785_update_fan(client, page, 0, PB_FAN_1_RPM, max31785_scale_pwm(word)); case PMBUS_VIRT_PWM_ENABLE_1: return max31785_pwm_enable(client, page, word); @@ -232,7 +355,279 @@ static int max31785_write_word_data(struct i2c_client *client, int page, break; } - return -ENODATA; + if (reg < PMBUS_VIRT_BASE) + return max31785_pmbus_write_word_data(client, page, reg, word); + + return -ENXIO; +} + +/* + * Returns negative error codes if an unrecoverable problem is detected, 0 if a + * recoverable problem is detected, or a positive value on success. + */ +static int max31785_of_fan_config(struct i2c_client *client, + struct pmbus_driver_info *info, + struct device_node *child) +{ + int mfr_cfg = 0, mfr_fault_resp = 0, pb_cfg; + struct device *dev = &client->dev; + char *lock_polarity = NULL; + const char *sval; + u32 page; + u32 uval; + int ret; + + if (!of_device_is_compatible(child, "pmbus-fan")) + return 0; + + ret = of_property_read_u32(child, "reg", &page); + if (ret < 0) { + dev_err(&client->dev, "Missing valid reg property\n"); + return ret; + } + + if (!(info->func[page] & PMBUS_HAVE_FAN12)) { + dev_err(dev, "Page %d does not have fan capabilities\n", page); + return -ENXIO; + } + + ret = max31785_i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); + if (ret < 0) + return ret; + + pb_cfg = max31785_i2c_smbus_read_byte_data(client, PMBUS_FAN_CONFIG_12); + if (pb_cfg < 0) + return pb_cfg; + + if (of_property_read_bool(child->parent, "use-stored-presence")) { + if (!(pb_cfg & PB_FAN_1_INSTALLED)) + dev_info(dev, "Fan %d is configured but not installed\n", + page); + } else { + pb_cfg |= PB_FAN_1_INSTALLED; + } + + ret = of_property_read_string(child, "maxim,fan-rotor-input", &sval); + if (ret < 0) { + dev_err(dev, "Missing valid maxim,fan-rotor-input property for fan %d\n", + page); + return ret; + } + + if (strcmp("tach", sval) && strcmp("lock", sval)) { + dev_err(dev, "maxim,fan-rotor-input has invalid value for fan %d: %s\n", + page, sval); + return -EINVAL; + } else if (!strcmp("lock", sval)) { + mfr_cfg |= MFR_FAN_CONFIG_ROTOR; + + ret = max31785_i2c_smbus_write_word_data(client, + MFR_FAN_FAULT_LIMIT, + 1); + if (ret < 0) + return ret; + + ret = of_property_read_string(child, "maxim,fan-lock-polarity", + &sval); + if (ret < 0) { + dev_err(dev, "Missing valid maxim,fan-lock-polarity property for fan %d\n", + page); + return ret; + } + + if (strcmp("low", sval) && strcmp("high", sval)) { + dev_err(dev, "maxim,fan-lock-polarity has invalid value for fan %d: %s\n", + page, lock_polarity); + return -EINVAL; + } else if (!strcmp("high", sval)) + mfr_cfg |= MFR_FAN_CONFIG_ROTOR_HI_LO; + } + + if (!of_property_read_string(child, "fan-mode", &sval)) { + if (!strcmp("rpm", sval)) + pb_cfg |= PB_FAN_1_RPM; + else if (!strcmp("pwm", sval)) + pb_cfg &= ~PB_FAN_1_RPM; + else { + dev_err(dev, "fan-mode has invalid value for fan %d: %s\n", + page, sval); + return -EINVAL; + } + } + + ret = of_property_read_u32(child, "tach-pulses", &uval); + if (ret < 0) { + pb_cfg &= ~PB_FAN_1_PULSE_MASK; + } else if (uval && (uval - 1) < 4) { + pb_cfg = ((pb_cfg & ~PB_FAN_1_PULSE_MASK) | ((uval - 1) << 4)); + } else { + dev_err(dev, "tach-pulses has invalid value for fan %d: %u\n", + page, uval); + return -EINVAL; + } + + if (of_property_read_bool(child, "maxim,fan-health")) + mfr_cfg |= MFR_FAN_CONFIG_HEALTH; + + if (of_property_read_bool(child, "maxim,fan-no-watchdog") || + of_property_read_bool(child, "maxim,tmp-no-fault-ramp")) + mfr_cfg |= MFR_FAN_CONFIG_TSFO; + + if (of_property_read_bool(child, "maxim,fan-dual-tach")) + mfr_cfg |= MFR_FAN_CONFIG_DUAL_TACH; + + if (of_property_read_bool(child, "maxim,fan-no-fault-ramp")) + mfr_cfg |= MFR_FAN_CONFIG_TACHO; + + if (!of_property_read_u32(child, "maxim,fan-startup", &uval)) { + uval /= 2; + if (uval < 5) { + mfr_cfg |= uval; + } else { + dev_err(dev, "maxim,fan-startup has invalid value for fan %d: %u\n", + page, uval); + return -EINVAL; + } + } + + if (!of_property_read_u32(child, "maxim,fan-ramp", &uval)) { + if (uval < 8) { + mfr_cfg |= uval << 5; + } else { + dev_err(dev, "maxim,fan-ramp has invalid value for fan %d: %u\n", + page, uval); + return -EINVAL; + } + } + + if (!of_property_read_u32(child, "maxim,tmp-hysteresis", &uval)) { + uval /= 2; + uval -= 1; + if (uval < 4) { + mfr_cfg |= uval << 10; + } else { + dev_err(dev, "maxim,tmp-hysteresis has invalid value for fan %d, %u\n", + page, uval); + return -EINVAL; + } + } + + if (!of_property_read_u32(child, "maxim,fan-pwm-freq", &uval)) { + u16 val; + + if (uval == 30) { + val = 0; + } else if (uval == 50) { + val = 1; + } else if (uval == 100) { + val = 2; + } else if (uval == 150) { + val = 3; + } else if (uval == 25000) { + val = 7; + } else { + dev_err(dev, "maxim,fan-pwm-freq has invalid value for fan %d: %u\n", + page, uval); + return -EINVAL; + } + + mfr_cfg |= val << 13; + } + + if (of_property_read_bool(child, "maxim,fan-fault-pin-mon")) + mfr_fault_resp |= MFR_FAULT_RESPONSE_MONITOR; + + ret = max31785_i2c_smbus_write_byte_data(client, PMBUS_FAN_CONFIG_12, + pb_cfg & ~PB_FAN_1_INSTALLED); + if (ret < 0) + return ret; + + ret = max31785_i2c_smbus_write_word_data(client, MFR_FAN_CONFIG, + mfr_cfg); + if (ret < 0) + return ret; + + ret = max31785_i2c_smbus_write_byte_data(client, MFR_FAULT_RESPONSE, + mfr_fault_resp); + if (ret < 0) + return ret; + + ret = max31785_i2c_smbus_write_byte_data(client, PMBUS_FAN_CONFIG_12, + pb_cfg); + if (ret < 0) + return ret; + + /* + * Fans are on pages 0 - 5. If the page property of a fan node is + * greater than 5 we will have errored in checks above out above. + * Therefore we don't need to cope with values up to 31, and the int + * return type is enough. + * + * The bit mask return value is used to populate a bitfield of fans + * who are both configured in the devicetree _and_ reported as + * installed by the hardware. Any fans that are not configured in the + * devicetree but are reported as installed by the hardware will have + * their hardware configuration updated to unset the installed bit. + */ + return BIT(page); +} + +static int max31785_of_tmp_config(struct i2c_client *client, + struct pmbus_driver_info *info, + struct device_node *child) +{ + struct device *dev = &client->dev; + struct device_node *np; + u16 mfr_tmp_cfg = 0; + u32 page; + u32 uval; + int ret; + int i; + + if (!of_device_is_compatible(child, "pmbus-temperature")) + return 0; + + ret = of_property_read_u32(child, "reg", &page); + if (ret < 0) { + dev_err(&client->dev, "Missing valid reg property\n"); + return ret; + } + + if (!(info->func[page] & PMBUS_HAVE_TEMP)) { + dev_err(dev, "Page %d does not have temp capabilities\n", page); + return -ENXIO; + } + + ret = max31785_i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); + if (ret < 0) + return ret; + + if (!of_property_read_u32(child, "maxim,tmp-offset", &uval)) { + if (uval < 32) + mfr_tmp_cfg |= uval << 10; + } + + i = 0; + while ((np = of_parse_phandle(child, "maxim,tmp-fans", i))) { + if (of_property_read_u32(np, "reg", &uval)) { + dev_err(&client->dev, "Failed to read fan reg property for phandle index %d\n", + i); + } else { + if (uval < 6) + mfr_tmp_cfg |= BIT(uval); + else + dev_warn(&client->dev, "Invalid fan page: %d\n", + uval); + } + i++; + } + + ret = max31785_i2c_smbus_write_word_data(client, MFR_TEMP_SENSOR_CONFIG, + mfr_tmp_cfg); + if (ret < 0) + return ret; + + return 0; } #define MAX31785_FAN_FUNCS \ @@ -306,11 +701,11 @@ static int max31785_configure_dual_tach(struct i2c_client *client, int i; for (i = 0; i < MAX31785_NR_FAN_PAGES; i++) { - ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, i); + ret = max31785_i2c_smbus_write_byte_data(client, PMBUS_PAGE, i); if (ret < 0) return ret; - ret = i2c_smbus_read_word_data(client, MFR_FAN_CONFIG); + ret = max31785_i2c_smbus_read_word_data(client, MFR_FAN_CONFIG); if (ret < 0) return ret; @@ -330,9 +725,12 @@ static int max31785_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct device *dev = &client->dev; + struct device_node *child; struct pmbus_driver_info *info; bool dual_tach = false; + u32 fans; s64 ret; + int i; if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA | @@ -345,7 +743,7 @@ static int max31785_probe(struct i2c_client *client, *info = max31785_info; - ret = i2c_smbus_write_byte_data(client, PMBUS_PAGE, 255); + ret = max31785_i2c_smbus_write_byte_data(client, PMBUS_PAGE, 255); if (ret < 0) return ret; @@ -362,6 +760,49 @@ static int max31785_probe(struct i2c_client *client, return -ENODEV; } + fans = 0; + for_each_child_of_node(dev->of_node, child) { + ret = max31785_of_fan_config(client, info, child); + if (ret < 0) { + of_node_put(child); + return ret; + } + + if (ret) + fans |= ret; + + ret = max31785_of_tmp_config(client, info, child); + if (ret < 0) { + of_node_put(child); + return ret; + } + } + + for (i = 0; i < MAX31785_NR_PAGES; i++) { + bool have_fan = !!(info->func[i] & PMBUS_HAVE_FAN12); + bool fan_configured = !!(fans & BIT(i)); + + if (!have_fan || fan_configured) + continue; + + ret = max31785_i2c_smbus_write_byte_data(client, PMBUS_PAGE, + i); + if (ret < 0) + return ret; + + ret = max31785_i2c_smbus_read_byte_data(client, + PMBUS_FAN_CONFIG_12); + if (ret < 0) + return ret; + + ret &= ~PB_FAN_1_INSTALLED; + ret = max31785_i2c_smbus_write_word_data(client, + PMBUS_FAN_CONFIG_12, + ret); + if (ret < 0) + return ret; + } + if (dual_tach) { ret = max31785_configure_dual_tach(client, info); if (ret < 0) diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c index 8470097907bc..898d7378f4f8 100644 --- a/drivers/hwmon/pmbus/pmbus_core.c +++ b/drivers/hwmon/pmbus/pmbus_core.c @@ -155,9 +155,17 @@ int pmbus_set_page(struct i2c_client *client, int page) return 0; if (!(data->info->func[page] & PMBUS_PAGE_VIRTUAL)) { + dev_dbg(&client->dev, "Want page %u, %u cached\n", page, + data->currpage); + rv = i2c_smbus_write_byte_data(client, PMBUS_PAGE, page); - if (rv < 0) - return rv; + if (rv) { + rv = i2c_smbus_write_byte_data(client, PMBUS_PAGE, + page); + dev_dbg(&client->dev, + "Failed to set page %u, performed one-shot retry %s: %d\n", + page, rv ? "and failed" : "with success", rv); + } rv = i2c_smbus_read_byte_data(client, PMBUS_PAGE); if (rv < 0) @@ -433,15 +441,15 @@ static int pmbus_get_fan_rate(struct i2c_client *client, int page, int id, return s->data; } - config = pmbus_read_byte_data(client, page, - pmbus_fan_config_registers[id]); + config = _pmbus_read_byte_data(client, page, + pmbus_fan_config_registers[id]); if (config < 0) return config; have_rpm = !!(config & pmbus_fan_rpm_mask[id]); if (want_rpm == have_rpm) - return pmbus_read_word_data(client, page, - pmbus_fan_command_registers[id]); + return _pmbus_read_word_data(client, page, + pmbus_fan_command_registers[id]); /* Can't sensibly map between RPM and PWM, just return zero */ return 0; diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 09367fc014c3..52e54b58512e 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -785,6 +785,18 @@ config I2C_NOMADIK I2C interface from ST-Ericsson's Nomadik and Ux500 architectures, as well as the STA2X11 PCIe I/O HUB. +config I2C_NPCM7XX + tristate "Nuvoton I2C Controller" + depends on ARCH_NPCM7XX + select I2C_SLAVE + select CRC8 + help + If you say yes to this option, support will be included for the + Nuvoton I2C controller. + + This driver can also be built as a module. If so, the module + will be called i2c-npcm7xx. + config I2C_OCORES tristate "OpenCores I2C Controller" help diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile index 80c23895eaaf..f4a27319ee41 100644 --- a/drivers/i2c/busses/Makefile +++ b/drivers/i2c/busses/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o obj-$(CONFIG_I2C_MXS) += i2c-mxs.o obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o +obj-$(CONFIG_I2C_NPCM7XX) += i2c-npcm7xx.o obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o obj-$(CONFIG_I2C_OMAP) += i2c-omap.o obj-$(CONFIG_I2C_OWL) += i2c-owl.o diff --git a/drivers/i2c/busses/i2c-aspeed.c b/drivers/i2c/busses/i2c-aspeed.c index 7b098ff5f5dd..b63ecc20777e 100644 --- a/drivers/i2c/busses/i2c-aspeed.c +++ b/drivers/i2c/busses/i2c-aspeed.c @@ -600,6 +600,17 @@ static irqreturn_t aspeed_i2c_bus_irq(int irq, void *dev_id) spin_lock(&bus->lock); irq_received = readl(bus->base + ASPEED_I2C_INTR_STS_REG); + + /* + * On the AST2600, interrupts have been observed with no interrupt + * status bits set. In this case, the handler should return IRQ_NONE + * immediately to prevent driver state machine corruption. + */ + if (!irq_received) { + spin_unlock(&bus->lock); + return IRQ_NONE; + } + /* Ack all interrupts except for Rx done */ writel(irq_received & ~ASPEED_I2CD_INTR_RX_DONE, bus->base + ASPEED_I2C_INTR_STS_REG); @@ -952,6 +963,10 @@ static const struct of_device_id aspeed_i2c_bus_of_table[] = { .compatible = "aspeed,ast2500-i2c-bus", .data = aspeed_i2c_25xx_get_clk_reg_val, }, + { + .compatible = "aspeed,ast2600-i2c-bus", + .data = aspeed_i2c_25xx_get_clk_reg_val, + }, { }, }; MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table); diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c new file mode 100644 index 000000000000..6d177d3f0e0b --- /dev/null +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -0,0 +1,2017 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Nuvoton NPCM7xx SMB Controller driver + * + * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com + */ +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/clk/nuvoton.h> +#include <linux/crc8.h> +#include <linux/errno.h> +#include <linux/i2c.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#define I2C_VERSION "0.0.3" + +enum smb_mode { + SMB_SLAVE = 1, + SMB_MASTER +}; + +/* + * External SMB Interface driver xfer indication values, which indicate status + * of the bus. + */ +enum smb_state_ind { + SMB_NO_STATUS_IND = 0, + SMB_SLAVE_RCV_IND = 1, + SMB_SLAVE_XMIT_IND = 2, + SMB_SLAVE_XMIT_MISSING_DATA_IND = 3, + SMB_SLAVE_RESTART_IND = 4, + SMB_SLAVE_DONE_IND = 5, + SMB_MASTER_DONE_IND = 6, + SMB_NO_DATA_IND = 7, + SMB_NACK_IND = 8, + SMB_BUS_ERR_IND = 9, + SMB_WAKE_UP_IND = 10, + SMB_MASTER_PEC_ERR_IND = 11, + SMB_BLOCK_BYTES_ERR_IND = 12, + SMB_SLAVE_PEC_ERR_IND = 13, + SMB_SLAVE_RCV_MISSING_DATA_IND = 14, +}; + +// SMBus Operation type values +enum smb_oper { + SMB_NO_OPER = 0, + SMB_WRITE_OPER = 1, + SMB_READ_OPER = 2 +}; + +// SMBus Bank (FIFO mode) +enum smb_bank { + SMB_BANK_0 = 0, + SMB_BANK_1 = 1 +}; + +// Internal SMB states values (for the SMB module state machine). +enum smb_state { + SMB_DISABLE = 0, + SMB_IDLE, + SMB_MASTER_START, + SMB_SLAVE_MATCH, + SMB_OPER_STARTED, + SMB_REPEATED_START, + SMB_STOP_PENDING +}; + +// Module supports setting multiple own slave addresses: +enum smb_addr { + SMB_SLAVE_ADDR1 = 0, + SMB_SLAVE_ADDR2, + SMB_SLAVE_ADDR3, + SMB_SLAVE_ADDR4, + SMB_SLAVE_ADDR5, + SMB_SLAVE_ADDR6, + SMB_SLAVE_ADDR7, + SMB_SLAVE_ADDR8, + SMB_SLAVE_ADDR9, + SMB_SLAVE_ADDR10, + SMB_GC_ADDR, + SMB_ARP_ADDR +}; + +// global regs +static struct regmap *gcr_regmap; +static struct regmap *clk_regmap; + +#define NPCM_I2CSEGCTL 0xE4 +#define NPCM_SECCNT 0x68 +#define NPCM_CNTR25M 0x6C +#define I2CSEGCTL_VAL 0x0333F000 + +// Common regs +#define NPCM_SMBSDA 0x000 +#define NPCM_SMBST 0x002 +#define NPCM_SMBCST 0x004 +#define NPCM_SMBCTL1 0x006 +#define NPCM_SMBADDR1 0x008 +#define NPCM_SMBCTL2 0x00A +#define NPCM_SMBADDR2 0x00C +#define NPCM_SMBCTL3 0x00E +#define NPCM_SMBCST2 0x018 +#define NPCM_SMBCST3 0x019 +#define SMB_VER 0x01F + +// BANK 0 regs +#define NPCM_SMBADDR3 0x010 +#define NPCM_SMBADDR7 0x011 +#define NPCM_SMBADDR4 0x012 +#define NPCM_SMBADDR8 0x013 +#define NPCM_SMBADDR5 0x014 +#define NPCM_SMBADDR9 0x015 +#define NPCM_SMBADDR6 0x016 +#define NPCM_SMBADDR10 0x017 + +// SMBADDR array: because the addr regs are sprincled all over the address space +const int NPCM_SMBADDR[10] = {NPCM_SMBADDR1, NPCM_SMBADDR2, NPCM_SMBADDR3, + NPCM_SMBADDR4, NPCM_SMBADDR5, NPCM_SMBADDR6, + NPCM_SMBADDR7, NPCM_SMBADDR8, NPCM_SMBADDR9, + NPCM_SMBADDR10}; + +#define NPCM_SMBCTL4 0x01A +#define NPCM_SMBCTL5 0x01B +#define NPCM_SMBSCLLT 0x01C // SCL Low Time +#define NPCM_SMBFIF_CTL 0x01D // FIFO Control +#define NPCM_SMBSCLHT 0x01E // SCL High Time + +// BANK 1 regs +#define NPCM_SMBFIF_CTS 0x010 // FIFO Control +#define NPCM_SMBTXF_CTL 0x012 // Tx-FIFO Control +#define NPCM_SMBT_OUT 0x014 // Bus T.O. +#define NPCM_SMBPEC 0x016 // PEC Data +#define NPCM_SMBTXF_STS 0x01A // Tx-FIFO Status +#define NPCM_SMBRXF_STS 0x01C // Rx-FIFO Status +#define NPCM_SMBRXF_CTL 0x01E // Rx-FIFO Control + +// NPCM_SMBST reg fields +#define NPCM_SMBST_XMIT BIT(0) +#define NPCM_SMBST_MASTER BIT(1) +#define NPCM_SMBST_NMATCH BIT(2) +#define NPCM_SMBST_STASTR BIT(3) +#define NPCM_SMBST_NEGACK BIT(4) +#define NPCM_SMBST_BER BIT(5) +#define NPCM_SMBST_SDAST BIT(6) +#define NPCM_SMBST_SLVSTP BIT(7) + +// NPCM_SMBCST reg fields +#define NPCM_SMBCST_BUSY BIT(0) +#define NPCM_SMBCST_BB BIT(1) +#define NPCM_SMBCST_MATCH BIT(2) +#define NPCM_SMBCST_GCMATCH BIT(3) +#define NPCM_SMBCST_TSDA BIT(4) +#define NPCM_SMBCST_TGSCL BIT(5) +#define NPCM_SMBCST_MATCHAF BIT(6) +#define NPCM_SMBCST_ARPMATCH BIT(7) + +// NPCM_SMBCTL1 reg fields +#define NPCM_SMBCTL1_START BIT(0) +#define NPCM_SMBCTL1_STOP BIT(1) +#define NPCM_SMBCTL1_INTEN BIT(2) +#define NPCM_SMBCTL1_EOBINTE BIT(3) +#define NPCM_SMBCTL1_ACK BIT(4) +#define NPCM_SMBCTL1_GCMEN BIT(5) +#define NPCM_SMBCTL1_NMINTE BIT(6) +#define NPCM_SMBCTL1_STASTRE BIT(7) + +// RW1S fields (inside a RW reg): +#define NPCM_SMBCTL1_RWS_FIELDS (NPCM_SMBCTL1_START | NPCM_SMBCTL1_STOP | \ + NPCM_SMBCTL1_ACK) +// NPCM_SMBADDR reg fields +#define NPCM_SMBADDR_ADDR GENMASK(6, 0) +#define NPCM_SMBADDR_SAEN BIT(7) + +// NPCM_SMBCTL2 reg fields +#define SMBCTL2_ENABLE BIT(0) +#define SMBCTL2_SCLFRQ6_0 GENMASK(7, 1) + +// NPCM_SMBCTL3 reg fields +#define SMBCTL3_SCLFRQ8_7 GENMASK(1, 0) +#define SMBCTL3_ARPMEN BIT(2) +#define SMBCTL3_IDL_START BIT(3) +#define SMBCTL3_400K_MODE BIT(4) +#define SMBCTL3_BNK_SEL BIT(5) +#define SMBCTL3_SDA_LVL BIT(6) +#define SMBCTL3_SCL_LVL BIT(7) + +// NPCM_SMBCST2 reg fields +#define NPCM_SMBCST2_MATCHA1F BIT(0) +#define NPCM_SMBCST2_MATCHA2F BIT(1) +#define NPCM_SMBCST2_MATCHA3F BIT(2) +#define NPCM_SMBCST2_MATCHA4F BIT(3) +#define NPCM_SMBCST2_MATCHA5F BIT(4) +#define NPCM_SMBCST2_MATCHA6F BIT(5) +#define NPCM_SMBCST2_MATCHA7F BIT(5) +#define NPCM_SMBCST2_INTSTS BIT(7) + +// NPCM_SMBCST3 reg fields +#define NPCM_SMBCST3_MATCHA8F BIT(0) +#define NPCM_SMBCST3_MATCHA9F BIT(1) +#define NPCM_SMBCST3_MATCHA10F BIT(2) +#define NPCM_SMBCST3_EO_BUSY BIT(7) + +// NPCM_SMBCTL4 reg fields +#define SMBCTL4_HLDT GENMASK(5, 0) +#define SMBCTL4_LVL_WE BIT(7) + +// NPCM_SMBCTL5 reg fields +#define SMBCTL5_DBNCT GENMASK(3, 0) + +// NPCM_SMBFIF_CTS reg fields +#define NPCM_SMBFIF_CTS_RXF_TXE BIT(1) +#define NPCM_SMBFIF_CTS_RFTE_IE BIT(3) +#define NPCM_SMBFIF_CTS_CLR_FIFO BIT(6) +#define NPCM_SMBFIF_CTS_SLVRSTR BIT(7) + +// NPCM_SMBTXF_CTL reg fields +#ifdef SMB_CAPABILITY_32B_FIFO +#define NPCM_SMBTXF_CTL_TX_THR GENMASK(5, 0) +#else +#define NPCM_SMBTXF_CTL_TX_THR GENMASK(4, 0) +#endif +#define NPCM_SMBTXF_CTL_THR_TXIE BIT(6) + +// NPCM_SMBT_OUT reg fields +#define NPCM_SMBT_OUT_TO_CKDIV GENMASK(5, 0) +#define NPCM_SMBT_OUT_T_OUTIE BIT(6) +#define NPCM_SMBT_OUT_T_OUTST BIT(7) + +// NPCM_SMBTXF_STS reg fields +#ifdef SMB_CAPABILITY_32B_FIFO +#define NPCM_SMBTXF_STS_TX_BYTES GENMASK(5, 0) +#else +#define NPCM_SMBTXF_STS_TX_BYTES GENMASK(4, 0) +#endif +#define NPCM_SMBTXF_STS_TX_THST BIT(6) + +// NPCM_SMBRXF_STS reg fields +#ifdef SMB_CAPABILITY_32B_FIFO +#define NPCM_SMBRXF_STS_RX_BYTES GENMASK(5, 0) +#else +#define NPCM_SMBRXF_STS_RX_BYTES GENMASK(4, 0) +#endif +#define NPCM_SMBRXF_STS_RX_THST BIT(6) + +// NPCM_SMBFIF_CTL reg fields +#define NPCM_SMBFIF_CTL_FIFO_EN BIT(4) + +// NPCM_SMBRXF_CTL reg fields +// Note: on the next HW version of this module, this HW is about to switch to +// 32 bytes FIFO. This size will be set using a config. +// on current version 16 bytes FIFO is set using a define +#ifdef SMB_CAPABILITY_32B_FIFO +#define NPCM_SMBRXF_CTL_RX_THR GENMASK(5, 0) +#define NPCM_SMBRXF_CTL_THR_RXIE BIT(6) +#define NPCM_SMBRXF_CTL_LAST_PEC BIT(7) +#define SMBUS_FIFO_SIZE 32 +#else +#define NPCM_SMBRXF_CTL_RX_THR GENMASK(4, 0) +#define NPCM_SMBRXF_CTL_LAST_PEC BIT(5) +#define NPCM_SMBRXF_CTL_THR_RXIE BIT(6) +#define SMBUS_FIFO_SIZE 16 +#endif + +// SMB_VER reg fields +#define SMB_VER_VERSION GENMASK(6, 0) +#define SMB_VER_FIFO_EN BIT(7) + +// stall/stuck timeout +const unsigned int DEFAULT_STALL_COUNT = 25; + +// Data abort timeout +const unsigned int ABORT_TIMEOUT = 1000; + +// SMBus spec. values in KHZ +const unsigned int SMBUS_FREQ_MIN = 10; +const unsigned int SMBUS_FREQ_MAX = 1000; +const unsigned int SMBUS_FREQ_100KHZ = 100; +const unsigned int SMBUS_FREQ_400KHZ = 400; +const unsigned int SMBUS_FREQ_1MHZ = 1000; + +// SCLFRQ min/max field values +const unsigned int SCLFRQ_MIN = 10; +const unsigned int SCLFRQ_MAX = 511; + +// SCLFRQ field position +#define SCLFRQ_0_TO_6 GENMASK(6, 0) +#define SCLFRQ_7_TO_8 GENMASK(8, 7) + +// SMB Maximum Retry Trials (on Bus Arbitration Loss) +const unsigned int SMB_RETRY_MAX_COUNT = 2; +const unsigned int SMB_NUM_OF_ADDR = 10; + +// for logging: +#define NPCM_I2C_EVENT_START BIT(0) +#define NPCM_I2C_EVENT_STOP BIT(1) +#define NPCM_I2C_EVENT_ABORT BIT(2) +#define NPCM_I2C_EVENT_WRITE BIT(3) +#define NPCM_I2C_EVENT_READ BIT(4) +#define NPCM_I2C_EVENT_BER BIT(5) +#define NPCM_I2C_EVENT_NACK BIT(6) +#define NPCM_I2C_EVENT_TO BIT(7) +#define NPCM_I2C_EVENT_EOB BIT(8) + +#define NPCM_I2C_EVENT_LOG(event) (bus->event_log |= event) + +#define SMB_RECOVERY_SUPPORT + +// slave mode: if end device reads more data than available, ask issuer or +// request for more data: +#define SMB_WRAP_AROUND_BUFFER + +// Status of one SMBus module +struct npcm_i2c { + struct i2c_adapter adap; + struct device *dev; + unsigned char __iomem *reg; + spinlock_t lock; /* IRQ synchronization */ + struct completion cmd_complete; + int irq; + int cmd_err; + struct i2c_msg *msgs; + int msgs_num; + int num; + u32 apb_clk; + enum smb_state state; + enum smb_oper operation; + enum smb_mode master_or_slave; + enum smb_state_ind stop_ind; + u8 dest_addr; + u8 *rd_buf; + u16 rd_size; + u16 rd_ind; + u8 *wr_buf; + u16 wr_size; + u16 wr_ind; + bool fifo_use; + u8 threshold_fifo; + + // PEC bit mask per slave address. + // 1: use PEC for this address, + // 0: do not use PEC for this address + u16 PEC_mask; + bool PEC_use; + u8 crc_data; + bool read_block_use; + u8 retry_count; + u8 int_cnt; + u32 event_log; + u32 clk_period_us; + u32 int_time_stamp[2]; +}; + +static inline void _npcm7xx_get_time_stamp(u32 *time_quad0, u32 *time_quad1) +{ + u32 seconds, seconds_last; + u32 ref_clock; + + regmap_read(clk_regmap, NPCM_SECCNT, &seconds_last); + + do { + regmap_read(clk_regmap, NPCM_SECCNT, &seconds); + regmap_read(clk_regmap, NPCM_CNTR25M, &ref_clock); + regmap_read(clk_regmap, NPCM_SECCNT, &seconds_last); + } while (seconds_last != seconds); + + *time_quad0 = ref_clock; + *time_quad1 = seconds; +} + +#define EXT_CLOCK_FREQUENCY_MHZ 25 +#define CNTR25M_ACCURECY EXT_CLOCK_FREQUENCY_MHZ // minimum accurecy + +// Function: _npcm7xx_delay_relative +// Parameters: +// us_delay - number of microseconds to delay since t0_time. +// if zero: no delay. +// +// t0_time - start time , to measure time from. +// get a time stamp, delay us_delay from it. If us_delay has already passed +// since the time stamp , then no delay is executed. returns the time elapsed +// since t0_time + +static inline u32 _npcm7xx_delay_relative(u32 us_delay, u32 t0_time0, + u32 t0_time1) +{ + u32 t1_time_0, t1_time_1; + u32 time_elapsed; + u32 minimum_delay = (us_delay * EXT_CLOCK_FREQUENCY_MHZ) + + CNTR25M_ACCURECY; + + // this is equivalent to microSec/0.64 + minimal tic length. + do { + _npcm7xx_get_time_stamp(&t1_time_0, &t1_time_1); + time_elapsed = ((EXT_CLOCK_FREQUENCY_MHZ * 1000000) * + (t1_time_1 - t0_time1)) + + (t1_time_0 - t0_time0); + } while (time_elapsed < minimum_delay); + + // return elapsed time + return (u32)(time_elapsed / EXT_CLOCK_FREQUENCY_MHZ); +} + +static inline void npcm_smb_select_bank(struct npcm_i2c *bus, + enum smb_bank bank) +{ + if (bus->fifo_use) + iowrite8((ioread8(bus->reg + NPCM_SMBCTL3) & ~SMBCTL3_BNK_SEL) | + FIELD_PREP(SMBCTL3_BNK_SEL, bank), + bus->reg + NPCM_SMBCTL3); +} + +DECLARE_CRC8_TABLE(npcm7xx_crc8); + +static u8 npcm_smb_calc_crc8(u8 crc_data, u8 data) +{ + crc_data = crc8(npcm7xx_crc8, &data, 1, crc_data); + return crc_data; +} + +static void npcm_smb_calc_PEC(struct npcm_i2c *bus, u8 data) +{ + if (bus->PEC_use) + bus->crc_data = npcm_smb_calc_crc8(bus->crc_data, data); +} + +static inline void npcm_smb_wr_byte(struct npcm_i2c *bus, u8 data) +{ + iowrite8(data, bus->reg + NPCM_SMBSDA); + npcm_smb_calc_PEC(bus, data); +} + +static inline void npcm_smb_rd_byte(struct npcm_i2c *bus, u8 *data) +{ + *data = ioread8(bus->reg + NPCM_SMBSDA); + npcm_smb_calc_PEC(bus, *data); +} + +static inline u8 npcm_smb_get_PEC(struct npcm_i2c *bus) +{ + if (bus->PEC_use) + return bus->crc_data; + else + return 0; +} + +static inline void npcm_smb_write_PEC(struct npcm_i2c *bus) +{ + if (bus->PEC_use) { + // get PAC value and write to the bus: + npcm_smb_wr_byte(bus, npcm_smb_get_PEC(bus)); + } +} + +// +// NPCM7XX SMB module allows writing to SCL and SDA pins directly +// without the need to change muxing of pins. +// This feature will be used for recovery sequences i.e. +// +static void npcm_smb_set_SCL(struct i2c_adapter *_adap, int level) +{ +#ifdef SMB_CAPABILITY_FORCE_SCL_SDA + unsigned long flags; + struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); + + // Select Bank 0 to access NPCM_SMBCTL4 + spin_lock_irqsave(&bus->lock, flags); + npcm_smb_select_bank(bus, SMB_BANK_0); + + // Set SCL_LVL, SDA_LVL bits as Read/Write (R/W) + iowrite8(ioread8(bus->reg + NPCM_SMBCTL4) | SMBCTL4_LVL_WE, + bus->reg + NPCM_SMBCTL4); + + // Set level + iowrite8((ioread8(bus->reg + NPCM_SMBCTL3) + & ~SMBCTL3_SCL_LVL) | FIELD_PREP(SMBCTL3_SCL_LVL, + level), bus->reg + NPCM_SMBCTL3); + + // Set SCL_LVL, SDA_LVL bits as Read Only (RO) + iowrite8(ioread8(bus->reg + NPCM_SMBCTL4) + & ~SMBCTL4_LVL_WE, bus->reg + NPCM_SMBCTL4); + + // Return to Bank 1 + npcm_smb_select_bank(bus, SMB_BANK_1); + spin_unlock_irqrestore(&bus->lock, flags); +#endif +} + +static int npcm_smb_get_SCL(struct i2c_adapter *_adap) +{ + unsigned long flags; + unsigned int ret = 0; + struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); + + // Select Bank 0 to access NPCM_SMBCTL4 + spin_lock_irqsave(&bus->lock, flags); + npcm_smb_select_bank(bus, SMB_BANK_0); + + // Get SCL level + ret = FIELD_GET(SMBCTL3_SCL_LVL, ioread8(bus->reg + NPCM_SMBCTL3)); + + // Return to Bank 1 + npcm_smb_select_bank(bus, SMB_BANK_1); + spin_unlock_irqrestore(&bus->lock, flags); + return ret; +} + +static int npcm_smb_get_SDA(struct i2c_adapter *_adap) +{ + unsigned long flags; + unsigned int ret = 0; + struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); + + // Select Bank 0 to access NPCM_SMBCTL4 + spin_lock_irqsave(&bus->lock, flags); + npcm_smb_select_bank(bus, SMB_BANK_0); + + // Get SDA level + ret = FIELD_GET(SMBCTL3_SDA_LVL, ioread8(bus->reg + NPCM_SMBCTL3)); + + // Return to Bank 1 + npcm_smb_select_bank(bus, SMB_BANK_1); + spin_unlock_irqrestore(&bus->lock, flags); + return ret; +} + +static inline u16 npcm_smb_get_index(struct npcm_i2c *bus) +{ + u16 index = 0; + + if (bus->operation == SMB_READ_OPER) + index = bus->rd_ind; + else if (bus->operation == SMB_WRITE_OPER) + index = bus->wr_ind; + + return index; +} + +// quick protocol: +static inline bool npcm_smb_is_quick(struct npcm_i2c *bus) +{ + if (bus->wr_size == 0 && bus->rd_size == 0) + return true; + return false; +} + +static void npcm_smb_disable(struct npcm_i2c *bus) +{ + int i; + + // select bank 0 for SMB addresses + npcm_smb_select_bank(bus, SMB_BANK_0); + + // Slave Addresses Removal + for (i = SMB_SLAVE_ADDR1; i < SMB_NUM_OF_ADDR; i++) + iowrite8(0, bus->reg + NPCM_SMBADDR[i]); + + // select bank 0 for SMB addresses + npcm_smb_select_bank(bus, SMB_BANK_1); + + // Disable module. + iowrite8(ioread8(bus->reg + NPCM_SMBCTL2) & ~SMBCTL2_ENABLE, + bus->reg + NPCM_SMBCTL2); + + // Set module disable + bus->state = SMB_DISABLE; +} + +static void npcm_smb_enable(struct npcm_i2c *bus) +{ + iowrite8((ioread8(bus->reg + NPCM_SMBCTL2) | SMBCTL2_ENABLE), + bus->reg + NPCM_SMBCTL2); +} + +// enable\disable end of busy (EOB) interrupt +static inline void npcm_smb_eob_int(struct npcm_i2c *bus, bool enable) +{ + if (enable) { + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) | + NPCM_SMBCTL1_EOBINTE) & ~NPCM_SMBCTL1_RWS_FIELDS, + bus->reg + NPCM_SMBCTL1); + } else { + iowrite8(ioread8(bus->reg + NPCM_SMBCTL1) & + ~NPCM_SMBCTL1_EOBINTE & ~NPCM_SMBCTL1_RWS_FIELDS, + bus->reg + NPCM_SMBCTL1); + + // Clear EO_BUSY pending bit: + iowrite8(ioread8(bus->reg + NPCM_SMBCST3) | + NPCM_SMBCST3_EO_BUSY, bus->reg + NPCM_SMBCST3); + } +} + +static inline bool npcm_smb_tx_fifo_full(struct npcm_i2c *bus) +{ + // check if TX FIFO full: + return (bool)FIELD_GET(NPCM_SMBTXF_STS_TX_THST, + ioread8(bus->reg + NPCM_SMBTXF_STS)); +} + +static inline bool npcm_smb_rx_fifo_full(struct npcm_i2c *bus) +{ + // check if RX FIFO full: + return (bool)FIELD_GET(NPCM_SMBRXF_STS_RX_THST, + ioread8(bus->reg + NPCM_SMBRXF_STS)); +} + +static inline void npcm_smb_clear_tx_fifo(struct npcm_i2c *bus) +{ + // clear TX FIFO: + iowrite8(ioread8(bus->reg + NPCM_SMBTXF_STS) | + NPCM_SMBTXF_STS_TX_THST, + bus->reg + NPCM_SMBTXF_STS); +} + +static inline void npcm_smb_clear_rx_fifo(struct npcm_i2c *bus) +{ + // clear RX FIFO: + iowrite8(ioread8(bus->reg + NPCM_SMBRXF_STS) | + NPCM_SMBRXF_STS_RX_THST, + bus->reg + NPCM_SMBRXF_STS); +} + +static void npcm_smb_int_enable(struct npcm_i2c *bus, bool enable) +{ + if (enable) + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) | + NPCM_SMBCTL1_INTEN) & ~NPCM_SMBCTL1_RWS_FIELDS, + bus->reg + NPCM_SMBCTL1); + else + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) & + ~NPCM_SMBCTL1_INTEN) & ~NPCM_SMBCTL1_RWS_FIELDS, + bus->reg + NPCM_SMBCTL1); +} + +static inline void npcm_smb_master_start(struct npcm_i2c *bus) +{ + NPCM_I2C_EVENT_LOG(NPCM_I2C_EVENT_START); + + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) | NPCM_SMBCTL1_START) & + ~(NPCM_SMBCTL1_STOP | NPCM_SMBCTL1_ACK), + bus->reg + NPCM_SMBCTL1); +} + +static inline void npcm_smb_master_stop(struct npcm_i2c *bus) +{ + NPCM_I2C_EVENT_LOG(NPCM_I2C_EVENT_STOP); + + // override HW issue: SMBus may fail to supply stop condition in Master + // Write operation. + // Need to delay at least 5 us from the last int, before issueing a stop + _npcm7xx_delay_relative(5, bus->int_time_stamp[0], + bus->int_time_stamp[1]); + + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) | NPCM_SMBCTL1_STOP) & + ~(NPCM_SMBCTL1_START | NPCM_SMBCTL1_ACK), + bus->reg + NPCM_SMBCTL1); + + if (bus->fifo_use) { + npcm_smb_select_bank(bus, SMB_BANK_1); + + if (bus->operation == SMB_READ_OPER) + npcm_smb_clear_rx_fifo(bus); + else + npcm_smb_clear_tx_fifo(bus); + + iowrite8(ioread8(bus->reg + NPCM_SMBFIF_CTS) | + NPCM_SMBFIF_CTS_SLVRSTR | + NPCM_SMBFIF_CTS_RXF_TXE, + bus->reg + NPCM_SMBFIF_CTS); + + iowrite8(0, bus->reg + NPCM_SMBTXF_CTL); + } +} + +static inline void npcm_smb_abort_data(struct npcm_i2c *bus) +{ + unsigned int timeout = ABORT_TIMEOUT; + u8 data; + + NPCM_I2C_EVENT_LOG(NPCM_I2C_EVENT_ABORT); + // Generate a STOP condition + npcm_smb_master_stop(bus); + npcm_smb_rd_byte(bus, &data); + + // Clear NEGACK, STASTR and BER bits + iowrite8(NPCM_SMBST_STASTR | NPCM_SMBST_NEGACK | + NPCM_SMBST_BER, bus->reg + NPCM_SMBST); + + // Wait till STOP condition is generated + while (FIELD_GET(NPCM_SMBCTL1_STOP, ioread8(bus->reg + NPCM_SMBCTL1))) { + timeout--; + if (!FIELD_GET(NPCM_SMBCTL1_STOP, + ioread8(bus->reg + NPCM_SMBCTL1))) + break; + if (timeout <= 1) { + dev_err(bus->dev, "%s, abort timeout!\n", __func__); + break; + } + } +} + +static inline void npcm_smb_stall_after_start(struct npcm_i2c *bus, bool stall) +{ + if (stall) + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) | + NPCM_SMBCTL1_STASTRE) & ~NPCM_SMBCTL1_RWS_FIELDS, + bus->reg + NPCM_SMBCTL1); + else + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) & + ~NPCM_SMBCTL1_STASTRE) & ~NPCM_SMBCTL1_RWS_FIELDS, + bus->reg + NPCM_SMBCTL1); +} + +static inline void npcm_smb_nack(struct npcm_i2c *bus) +{ + if (bus->rd_ind < (bus->rd_size - 1)) + dev_info(bus->dev, + "\tNACK err bus%d, SA=0x%x, rd(%d\%d), op=%d st=%d\n", + bus->num, bus->dest_addr, bus->rd_ind, bus->rd_size, + bus->operation, bus->state); + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) | NPCM_SMBCTL1_ACK) & + ~(NPCM_SMBCTL1_STOP | NPCM_SMBCTL1_START), + bus->reg + NPCM_SMBCTL1); +} + +static void npcm_smb_reset(struct npcm_i2c *bus) +{ + // Save NPCM_SMBCTL1 relevant bits. It is being cleared when the + // module is disabled + u8 smbctl1 = ioread8(bus->reg + NPCM_SMBCTL1) & (NPCM_SMBCTL1_GCMEN + | NPCM_SMBCTL1_INTEN + | NPCM_SMBCTL1_NMINTE); + + // Disable the SMB module + iowrite8((ioread8(bus->reg + NPCM_SMBCTL2) & ~SMBCTL2_ENABLE), + bus->reg + NPCM_SMBCTL2); + + // Enable the SMB module + npcm_smb_enable(bus); + + // Restore NPCM_SMBCTL1 status + iowrite8(smbctl1 & ~NPCM_SMBCTL1_RWS_FIELDS, bus->reg + NPCM_SMBCTL1); + + // Reset driver status + bus->state = SMB_IDLE; + // + // Configure FIFO disabled mode so slave will not use fifo + // (master will set it on if supported) + iowrite8(ioread8(bus->reg + NPCM_SMBFIF_CTL) & + ~NPCM_SMBFIF_CTL_FIFO_EN, + bus->reg + NPCM_SMBFIF_CTL); + bus->fifo_use = false; +} + +static inline bool npcm_smb_is_master(struct npcm_i2c *bus) +{ + return (bool)FIELD_GET(NPCM_SMBST_MASTER, + ioread8(bus->reg + NPCM_SMBST)); +} + +static int npcm_smb_master_abort(struct npcm_i2c *bus) +{ + int ret = -(EIO); + + // Only current master is allowed to issue Stop Condition + if (npcm_smb_is_master(bus)) { + npcm_smb_abort_data(bus); + ret = 0; + } + + npcm_smb_reset(bus); + + return ret; +} + +static void npcm_smb_callback(struct npcm_i2c *bus, + enum smb_state_ind op_status, u16 info) +{ + struct i2c_msg *msgs = bus->msgs; + int msgs_num = bus->msgs_num; + + switch (op_status) { + case SMB_MASTER_DONE_IND: + // Master transaction finished and all transmit bytes were sent + // info: number of bytes actually received after the Master + // receive operation (if Master didn't issue receive it + // should be 0) + // Notify that not all data was received on Master or Slave + // info: + // on receive: number of actual bytes received + // when PEC is used even if 'info' is the expected number + // of bytes, it means that PEC error occurred. + { + if (msgs[0].flags & I2C_M_RD) + msgs[0].len = info; + else if (msgs_num == 2 && msgs[1].flags & I2C_M_RD) + msgs[1].len = info; + + bus->cmd_err = 0; + complete(&bus->cmd_complete); + } + break; + + case SMB_NO_DATA_IND: + // Notify that not all data was received on Master or Slave + // info: + //on receive: number of actual bytes received + // when PEC is used even if 'info' is the expected number + // of bytes,it means that PEC error occurred. + { + if (msgs[0].flags & I2C_M_RD) + msgs[0].len = info; + else if (msgs_num == 2 && msgs[1].flags & I2C_M_RD) + msgs[1].len = info; + + bus->cmd_err = -EFAULT; + complete(&bus->cmd_complete); + } + break; + case SMB_NACK_IND: + // MASTER transmit got a NAK before transmitting all bytes + // info: number of transmitted bytes + bus->cmd_err = -EAGAIN; + complete(&bus->cmd_complete); + + break; + case SMB_BUS_ERR_IND: + // Bus error + // info: has no meaning + bus->cmd_err = -EIO; + complete(&bus->cmd_complete); + break; + case SMB_WAKE_UP_IND: + // SMBus wake up + // info: has no meaning + break; + default: + break; + } +} + +static u32 npcm_smb_get_fifo_fullness(struct npcm_i2c *bus) +{ + if (bus->operation == SMB_WRITE_OPER) + return FIELD_GET(NPCM_SMBTXF_STS_TX_BYTES, + ioread8(bus->reg + NPCM_SMBTXF_STS)); + else if (bus->operation == SMB_READ_OPER) + return FIELD_GET(NPCM_SMBRXF_STS_RX_BYTES, + ioread8(bus->reg + NPCM_SMBRXF_STS)); + return 0; +} + +static void npcm_smb_write_to_fifo(struct npcm_i2c *bus, u16 max_bytes_to_send) +{ + // Fill the FIFO, while the FIFO is not full and there are more bytes to + // write + while ((max_bytes_to_send--) && (SMBUS_FIFO_SIZE - + npcm_smb_get_fifo_fullness(bus))) { + // write the data + if (bus->wr_ind < bus->wr_size) { + if (bus->PEC_use && + (bus->wr_ind + 1 == bus->wr_size) && + (bus->rd_size == 0 || + bus->master_or_slave == SMB_SLAVE)) { + // Master send PEC in write protocol, Slave send + // PEC in read protocol. + npcm_smb_write_PEC(bus); + bus->wr_ind++; + } else { + npcm_smb_wr_byte(bus, + bus->wr_buf[bus->wr_ind++]); + } + } else { +#ifdef SMB_WRAP_AROUND_BUFFER + // We're out of bytes. Ask the higher level for + // more bytes. Let it know that driver + // used all its' bytes + + npcm_smb_clear_tx_fifo(bus); + + // Reset state for the remaining bytes transaction + bus->state = SMB_SLAVE_MATCH; + + // Notify upper layer of transaction completion + npcm_smb_callback(bus, SMB_SLAVE_XMIT_MISSING_DATA_IND, + bus->wr_ind); + + iowrite8(NPCM_SMBST_SDAST, bus->reg + NPCM_SMBST); +#else + npcm_smb_wr_byte(bus, 0xFF); +#endif + } + } +} + +// configure the FIFO before using it. If nread is -1 RX FIFO will not be +// configured. same for nwrite +static void npcm_smb_set_fifo(struct npcm_i2c *bus, int nread, int nwrite) +{ + if (!bus->fifo_use) + return; + npcm_smb_select_bank(bus, SMB_BANK_1); + npcm_smb_clear_tx_fifo(bus); + npcm_smb_clear_rx_fifo(bus); + + // configure RX FIFO + if (nread > 0) { + // clear LAST bit: + iowrite8(ioread8(bus->reg + NPCM_SMBRXF_CTL) & + (~NPCM_SMBRXF_CTL_LAST_PEC), + bus->reg + NPCM_SMBRXF_CTL); + + if (nread > SMBUS_FIFO_SIZE) + iowrite8((ioread8(bus->reg + NPCM_SMBRXF_CTL) & + ~NPCM_SMBRXF_CTL_RX_THR) + | FIELD_PREP(NPCM_SMBRXF_CTL_RX_THR, + SMBUS_FIFO_SIZE), bus->reg + NPCM_SMBRXF_CTL); + else + iowrite8((ioread8(bus->reg + NPCM_SMBRXF_CTL) & + ~NPCM_SMBRXF_CTL_RX_THR) | + FIELD_PREP(NPCM_SMBRXF_CTL_RX_THR, + (u8)(nread)), + bus->reg + NPCM_SMBRXF_CTL); + + if (nread <= SMBUS_FIFO_SIZE && !bus->read_block_use) + iowrite8(ioread8(bus->reg + NPCM_SMBRXF_CTL) | + NPCM_SMBRXF_CTL_LAST_PEC, + bus->reg + NPCM_SMBRXF_CTL); + } + + // configure TX FIFO + if (nwrite > 0) { + if (nwrite > SMBUS_FIFO_SIZE) + // data to send is more then FIFO size. + // Configure the FIFO int to be mid of FIFO. + iowrite8(NPCM_SMBTXF_CTL_THR_TXIE | + (SMBUS_FIFO_SIZE / 2), + bus->reg + NPCM_SMBTXF_CTL); + else if (nwrite > (SMBUS_FIFO_SIZE / 2) && + bus->wr_ind != 0) + // wr_ind != 0 means that this is not the first + // write. since int is in the mid of FIFO, only + // half of the fifo is empty. + // Continue to configure the FIFO int to be mid + // of FIFO. + iowrite8(NPCM_SMBTXF_CTL_THR_TXIE | + (SMBUS_FIFO_SIZE / 2), + bus->reg + NPCM_SMBTXF_CTL); + else + // This is the either first write (wr_ind = 0) + // and data to send is less or equal to FIFO + // size. + // Or this is the last write and data to send + // is less or equal half FIFO size. + // In both cases disable the FIFO threshold int. + // The next int will happen after the FIFO will + // get empty. + iowrite8(0, bus->reg + NPCM_SMBTXF_CTL); + npcm_smb_clear_tx_fifo(bus); + } +} + +static void npcm_smb_read_from_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo) +{ + while (bytes_in_fifo--) { + // Keep read data + u8 data = ioread8(bus->reg + NPCM_SMBSDA); + + npcm_smb_calc_PEC(bus, data); + if (bus->rd_ind < bus->rd_size) { + bus->rd_buf[bus->rd_ind++] = data; + if (bus->rd_ind == 1 && bus->read_block_use) + // First byte indicates length in block protocol + bus->rd_size = data; + } + } +} + +static void npcm_smb_master_fifo_read(struct npcm_i2c *bus) +{ + u16 rcount; + u8 fifo_bytes; + enum smb_state_ind ind = SMB_MASTER_DONE_IND; + + rcount = bus->rd_size - bus->rd_ind; + + // In order not to change the RX_TRH during transaction (we found that + // this might be problematic if it takes too much time to read the FIFO) + // we read the data in the following way. If the number of bytes to + // read == FIFO Size + C (where C < FIFO Size)then first read C bytes + // and in the next int we read rest of the data. + if (rcount < (2 * SMBUS_FIFO_SIZE) && rcount > SMBUS_FIFO_SIZE) + fifo_bytes = (u8)(rcount - SMBUS_FIFO_SIZE); + else + fifo_bytes = npcm_smb_get_fifo_fullness(bus); + + if (rcount - fifo_bytes == 0) { + // last byte is about to be read - end of transaction. + // Stop should be set before reading last byte. + npcm_smb_eob_int(bus, true); + npcm_smb_master_stop(bus); + npcm_smb_read_from_fifo(bus, fifo_bytes); + + if (npcm_smb_get_PEC(bus) != 0) + ind = SMB_MASTER_PEC_ERR_IND; + bus->state = SMB_STOP_PENDING; + bus->stop_ind = ind; + + } else { + npcm_smb_read_from_fifo(bus, fifo_bytes); + rcount = bus->rd_size - bus->rd_ind; + npcm_smb_set_fifo(bus, rcount, -1); + } +} + +static void npcm_smb_int_master_handler_write(struct npcm_i2c *bus) +{ + u16 wcount; + + NPCM_I2C_EVENT_LOG(NPCM_I2C_EVENT_WRITE); + if (bus->fifo_use) + npcm_smb_clear_tx_fifo(bus); + + // Master write operation - last byte handling + if (bus->wr_ind == bus->wr_size) { + if (bus->fifo_use && npcm_smb_get_fifo_fullness(bus) > 0) + // No more bytes to send (to add to the FIFO), however the FIFO is not + // empty yet. It is still in the middle of tx. Currently there's nothing + // to do except for waiting to the end of the tx. + // We will get an int when the FIFO will get empty. + return; + + if (bus->rd_size == 0) { + // all bytes have been written, in a pure wr operation + npcm_smb_eob_int(bus, true); + + // Issue a STOP condition on the bus + npcm_smb_master_stop(bus); + // Clear SDA Status bit (by writing dummy byte) + npcm_smb_wr_byte(bus, 0xFF); + + bus->state = SMB_STOP_PENDING; + bus->stop_ind = SMB_MASTER_DONE_IND; + } else { + // last write-byte written on previous int - need to + // restart & send slave address + if (bus->PEC_use && !bus->read_block_use && + !npcm_smb_is_quick(bus)) + // PEC is used but the protocol is not block read + // then we add extra bytes for PEC support + bus->rd_size += 1; + + if (bus->fifo_use) { + if (bus->rd_size == 1 || bus->read_block_use) { + // SMBus Block read transaction. + iowrite8(0, bus->reg + NPCM_SMBTXF_CTL); + iowrite8(1, bus->reg + NPCM_SMBRXF_CTL); + } + } + + npcm_smb_set_fifo(bus, bus->rd_size, -1); + + // Generate (Repeated) Start upon next write to SDA + npcm_smb_master_start(bus); + + if (bus->rd_size == 1) + + // Receiving one byte only - stall after successful completion of send + // address byte. If we NACK here, and slave doesn't ACK the address, we + // might unintentionally NACK the next multi-byte read + + npcm_smb_stall_after_start(bus, true); + + // send the slave address in read direction + npcm_smb_wr_byte(bus, bus->dest_addr | 0x1); + + // Next int will occur on read + bus->operation = SMB_READ_OPER; + } + } else { + if (bus->PEC_use && !npcm_smb_is_quick(bus)) + // extra bytes for PEC support + bus->wr_size += 1; + + // write next byte not last byte and not slave address + if (!bus->fifo_use || bus->wr_size == 1) { + if (bus->PEC_use && bus->rd_size == 0 && + (bus->wr_ind + 1 == bus->wr_size)) { + // Master write protocol to send PEC byte. + npcm_smb_write_PEC(bus); + bus->wr_ind++; + } else { + npcm_smb_wr_byte(bus, + bus->wr_buf[bus->wr_ind++]); + } + } else { // FIFO is used + wcount = bus->wr_size - bus->wr_ind; + npcm_smb_set_fifo(bus, -1, wcount); + npcm_smb_write_to_fifo(bus, wcount); + } + } +} + +static void npcm_smb_int_master_handler_read(struct npcm_i2c *bus) +{ + u16 block_zero_bytes; + u32 fifo_bytes; + + // Master read operation (pure read or following a write operation). + NPCM_I2C_EVENT_LOG(NPCM_I2C_EVENT_READ); + + // Initialize number of bytes to include only the first byte (presents + // a case where number of bytes to read is zero); add PEC if applicable + block_zero_bytes = 1; + if (bus->PEC_use) + block_zero_bytes++; + + fifo_bytes = FIELD_GET(NPCM_SMBRXF_CTL_RX_THR, + ioread8(bus->reg + NPCM_SMBRXF_CTL)); + + // Perform master read, distinguishing between last byte and the rest of + // the bytes. The last byte should be read when the clock is stopped + if ((bus->rd_ind < (bus->rd_size - 1)) || bus->fifo_use) { + u8 data; + + // byte to be read is not the last one + // Check if byte-before-last is about to be read + if ((bus->rd_ind == (bus->rd_size - 2)) && + !bus->fifo_use){ + // Set nack before reading byte-before-last, so that + // nack will be generated after receive of last byte + npcm_smb_nack(bus); + + if (!FIELD_GET(NPCM_SMBST_SDAST, + ioread8(bus->reg + NPCM_SMBST))) { + // No data available - reset state for new xfer + bus->state = SMB_IDLE; + + // Notify upper layer of rx completion + npcm_smb_callback(bus, SMB_NO_DATA_IND, + bus->rd_ind); + } + } else if (bus->rd_ind == 0) { //first byte handling: + // in block protocol first byte is the size + if (bus->read_block_use) { + npcm_smb_rd_byte(bus, &data); + + // First byte indicates length in block protocol + bus->rd_buf[bus->rd_ind++] = data; + bus->rd_size = data + 1; + + if (bus->PEC_use) { + bus->rd_size += 1; + data += 1; + } + + if (bus->fifo_use) { + iowrite8(NPCM_SMBFIF_CTS_RXF_TXE | + ioread8(bus->reg + + NPCM_SMBFIF_CTS), + bus->reg + NPCM_SMBFIF_CTS); + + // first byte in block protocol + // is zero -> not supported. read at + // least one byte + if (data == 0) + data = 1; + } + npcm_smb_set_fifo(bus, bus->rd_size, -1); + } else { + if (!bus->fifo_use) { + npcm_smb_rd_byte(bus, &data); + bus->rd_buf[bus->rd_ind++] = data; + } else { + npcm_smb_clear_tx_fifo(bus); + npcm_smb_master_fifo_read(bus); + } + } + + } else { + if (bus->fifo_use) { + if (bus->rd_size == block_zero_bytes && + bus->read_block_use) { + npcm_smb_eob_int(bus, true); + npcm_smb_master_stop(bus); + npcm_smb_read_from_fifo(bus, + fifo_bytes); + bus->state = SMB_STOP_PENDING; + bus->stop_ind = SMB_BLOCK_BYTES_ERR_IND; + + } else { + npcm_smb_master_fifo_read(bus); + } + } else { + npcm_smb_rd_byte(bus, &data); + bus->rd_buf[bus->rd_ind++] = data; + } + } + } else { + // last byte is about to be read - end of transaction. + // Stop should be set before reading last byte. + u8 data; + enum smb_state_ind ind = SMB_MASTER_DONE_IND; + + npcm_smb_eob_int(bus, true); + + npcm_smb_master_stop(bus); + + npcm_smb_rd_byte(bus, &data); + + if (bus->rd_size == block_zero_bytes && bus->read_block_use) { + ind = SMB_BLOCK_BYTES_ERR_IND; + } else { + bus->rd_buf[bus->rd_ind++] = data; + if (npcm_smb_get_PEC(bus) != 0) + ind = SMB_MASTER_PEC_ERR_IND; + } + + bus->state = SMB_STOP_PENDING; + bus->stop_ind = ind; + } +} + +static void npcm_smb_int_master_handler(struct npcm_i2c *bus) +{ + // A negative acknowledge has occurred + if (FIELD_GET(NPCM_SMBST_NEGACK, ioread8(bus->reg + NPCM_SMBST))) { + NPCM_I2C_EVENT_LOG(NPCM_I2C_EVENT_NACK); + if (bus->fifo_use) { + // if there are still untransmitted bytes in TX FIFO + // reduce them from wr_ind + + if (bus->operation == SMB_WRITE_OPER) + bus->wr_ind -= npcm_smb_get_fifo_fullness(bus); + // clear the FIFO + iowrite8(NPCM_SMBFIF_CTS_CLR_FIFO, + bus->reg + NPCM_SMBFIF_CTS); + } + + // In master write operation, NACK is a problem + // number of bytes sent to master less than required + npcm_smb_master_abort(bus); + bus->state = SMB_IDLE; + + // In Master mode, NEGACK should be cleared only after + // generating STOP. + // In such case, the bus is released from stall only after the + // software clears NEGACK bit. + // Then a Stop condition is sent. + iowrite8(NPCM_SMBST_NEGACK, bus->reg + NPCM_SMBST); + npcm_smb_callback(bus, SMB_NACK_IND, bus->wr_ind); + return; + } + + // Master mode: a Bus Error has been identified + if (FIELD_GET(NPCM_SMBST_BER, ioread8(bus->reg + NPCM_SMBST))) { + // Check whether bus arbitration or Start or Stop during data + // xfer bus arbitration problem should not result in recovery + if (npcm_smb_is_master(bus)) { + // Only current master is allowed to issue stop + npcm_smb_master_abort(bus); + } else { + // Bus arbitration loss + if (bus->retry_count-- > 0) { + // Perform a retry (generate a start condition) + // as soon as the SMBus is free + iowrite8(NPCM_SMBST_BER, bus->reg + NPCM_SMBST); + npcm_smb_master_start(bus); + return; + } + } + iowrite8(NPCM_SMBST_BER, bus->reg + NPCM_SMBST); + bus->state = SMB_IDLE; + npcm_smb_callback(bus, SMB_BUS_ERR_IND, + npcm_smb_get_index(bus)); + return; + } + + // A Master End of Busy (meaning Stop Condition happened) + // End of Busy int is on and End of Busy is set + if ((FIELD_GET(NPCM_SMBCTL1_EOBINTE, + ioread8(bus->reg + NPCM_SMBCTL1)) == 1) && + (FIELD_GET(NPCM_SMBCST3_EO_BUSY, + ioread8(bus->reg + NPCM_SMBCST3)))) { + NPCM_I2C_EVENT_LOG(NPCM_I2C_EVENT_EOB); + npcm_smb_eob_int(bus, false); + bus->state = SMB_IDLE; + if (npcm_smb_is_quick(bus)) + npcm_smb_callback(bus, bus->stop_ind, 0); + else + npcm_smb_callback(bus, bus->stop_ind, bus->rd_ind); + return; + } + + // Address sent and requested stall occurred (Master mode) + if (FIELD_GET(NPCM_SMBST_STASTR, ioread8(bus->reg + NPCM_SMBST))) { + // Check for Quick Command SMBus protocol + if (npcm_smb_is_quick(bus)) { + npcm_smb_eob_int(bus, true); + npcm_smb_master_stop(bus); + + // Update status + bus->state = SMB_STOP_PENDING; + bus->stop_ind = SMB_MASTER_DONE_IND; + + } else if (bus->rd_size == 1) { + // Receiving one byte only - set NACK after ensuring + // slave ACKed the address byte + npcm_smb_nack(bus); + } + + // Reset stall-after-address-byte + npcm_smb_stall_after_start(bus, false); + + // Clear stall only after setting STOP + iowrite8(NPCM_SMBST_STASTR, bus->reg + NPCM_SMBST); + + return; + } + + // SDA status is set - transmit or receive, master + if (FIELD_GET(NPCM_SMBST_SDAST, ioread8(bus->reg + NPCM_SMBST)) || + (bus->fifo_use && + (npcm_smb_tx_fifo_full(bus) || npcm_smb_rx_fifo_full(bus)))) { + // Status Bit is cleared by writing to or reading from SDA + // (depending on current direction) + switch (bus->state) { + // Handle unsuccessful bus mastership + case SMB_IDLE: + npcm_smb_master_abort(bus); + return; + + case SMB_MASTER_START: + if (npcm_smb_is_master(bus)) { + u8 addr_byte = bus->dest_addr; + + bus->crc_data = 0; + if (npcm_smb_is_quick(bus)) { + // Need to stall after successful + // completion of sending address byte + npcm_smb_stall_after_start(bus, true); + } else if (bus->wr_size == 0) { + // Set direction to Read + addr_byte |= (u8)0x1; + bus->operation = SMB_READ_OPER; + } else { + bus->operation = SMB_WRITE_OPER; + } + + // Receiving one byte only - stall after successful completion of + // sending address byte. If we NACK here, and slave doesn't ACK the + // address, we might unintentionally NACK the next multi-byte read + if (bus->wr_size == 0 && bus->rd_size == 1) + npcm_smb_stall_after_start(bus, true); + + // Write the address to the bus + bus->state = SMB_OPER_STARTED; + npcm_smb_wr_byte(bus, addr_byte); + } else { + dev_err(bus->dev, + "SDA, bus%d is not master, wr %d 0x%x...\n", + bus->num, bus->wr_size, + bus->wr_buf[0]); + } + break; + + // SDA status is set - transmit or receive: Handle master mode + case SMB_OPER_STARTED: + if (bus->operation == SMB_WRITE_OPER) + npcm_smb_int_master_handler_write(bus); + else if (bus->operation == SMB_READ_OPER) + npcm_smb_int_master_handler_read(bus); + else + pr_err("I2C%d: unknown operation\n", bus->num); + break; + default: + dev_err(bus->dev, "i2c%d master sda err on state machine\n", + bus->num); + } + } +} + +static int npcm_smb_recovery(struct i2c_adapter *_adap) +{ + u8 iter = 27; // Allow one byte to be sent by the Slave + u16 timeout; + bool done = false; + struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); + + dev_info(bus->dev, "recovery bus%d\n", bus->num); + + might_sleep(); + + // Disable int + npcm_smb_int_enable(bus, false); + + // Check If the SDA line is active (low) + if (FIELD_GET(NPCM_SMBCST_TSDA, ioread8(bus->reg + NPCM_SMBCST)) == 0) { + // Repeat the following sequence until SDA is released + do { + // Issue a single SCL cycle + iowrite8(NPCM_SMBCST_TGSCL, bus->reg + NPCM_SMBCST); + timeout = ABORT_TIMEOUT; + while (timeout != 0 && + FIELD_GET(NPCM_SMBCST_TGSCL, + ioread8(bus->reg + NPCM_SMBCST) == 0)) + timeout--; + + // If SDA line is inactive (high), stop + if (FIELD_GET(NPCM_SMBCST_TSDA, + ioread8(bus->reg + NPCM_SMBCST)) == 1) + done = true; + } while ((!done) && (--iter != 0)); + + // If SDA line is released (high) + if (done) { + // Clear BB (BUS BUSY) bit + iowrite8(NPCM_SMBCST_BB, bus->reg + NPCM_SMBCST); + + // Generate a START, to synchronize Master and Slave + npcm_smb_master_start(bus); + + // Wait until START condition is sent, or timeout + timeout = ABORT_TIMEOUT; + while (timeout != 0 && !npcm_smb_is_master(bus)) + timeout--; + + // If START condition was sent + if (timeout > 0) { + // Send an address byte + npcm_smb_wr_byte(bus, bus->dest_addr); + + // Generate a STOP condition + npcm_smb_master_stop(bus); + } + return 0; + } + } + + // check if success: + if (npcm_smb_get_SCL(_adap) == 1 && npcm_smb_get_SDA(_adap) == 1) + goto npcm_smb_recovery_done; + + // hold clock low for 35ms: 25 and some spair: + npcm_smb_set_SCL(_adap, 0); + usleep_range(35000, 40000); + npcm_smb_set_SCL(_adap, 1); + usleep_range(1000, 2000); + + // check if success: + if (npcm_smb_get_SCL(_adap) == 1 && npcm_smb_get_SDA(_adap) == 1) + goto npcm_smb_recovery_done; + + return 0; + +npcm_smb_recovery_done: + + npcm_smb_int_enable(bus, true); + return -(ENOTRECOVERABLE); +} + +static bool npcm_smb_init_clk(struct npcm_i2c *bus, enum smb_mode mode, + u32 bus_freq) +{ + u32 k1 = 0; + u32 k2 = 0; + u8 dbnct = 0; + u32 sclfrq = 0; + u8 hldt = 7; + bool fast_mode = false; + u32 src_clk_freq; // in KHz + + src_clk_freq = bus->apb_clk / 1000; + + if (bus_freq <= SMBUS_FREQ_100KHZ) { + sclfrq = src_clk_freq / (bus_freq * 4); + + if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) + return false; + + if (src_clk_freq >= 40000) + hldt = 17; + else if (src_clk_freq >= 12500) + hldt = 15; + else + hldt = 7; + } + + else if (bus_freq == SMBUS_FREQ_400KHZ) { + sclfrq = 0; + fast_mode = true; + + if ((mode == SMB_MASTER && src_clk_freq < 7500) || + (mode == SMB_SLAVE && src_clk_freq < 10000)) + // 400KHZ cannot be supported for master core clock < 7.5 MHZ + // or slave core clock < 10 MHZ + return false; + + // Master or Slave with frequency > 25 MHZ + if (mode == SMB_MASTER || src_clk_freq > 25000) { + hldt = (u8)__KERNEL_DIV_ROUND_UP(src_clk_freq * 300, + 1000000) + 7; + if (mode == SMB_MASTER) { + k1 = __KERNEL_DIV_ROUND_UP(src_clk_freq * 1600, + 1000000); + k2 = __KERNEL_DIV_ROUND_UP(src_clk_freq * 900, + 1000000); + k1 = round_up(k1, 2); + k2 = round_up(k2 + 1, 2); + if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || + k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) + return false; + } + } else { // Slave with frequency 10-25 MHZ + hldt = 7; + dbnct = 2; + } + } + + else if (bus_freq == SMBUS_FREQ_1MHZ) { + sclfrq = 0; + fast_mode = true; + + if ((mode == SMB_MASTER && src_clk_freq < 15000) || + (mode == SMB_SLAVE && src_clk_freq < 24000)) + // 1MHZ cannot be supported for master core clock < 15 MHZ + // or slave core clock < 24 MHZ + return false; + + if (mode == SMB_MASTER) { + k1 = round_up((__KERNEL_DIV_ROUND_UP(src_clk_freq * 620, + 1000000)), 2); + k2 = round_up((__KERNEL_DIV_ROUND_UP(src_clk_freq * 380, + 1000000) + 1), 2); + if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || + k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) { + return false; + } + } + + // Master or Slave with frequency > 40 MHZ + if (mode == SMB_MASTER || src_clk_freq > 40000) { + // Set HLDT: + // SDA hold time: (HLDT-7) * T(CLK) >= 120 + // HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7 + hldt = (u8)__KERNEL_DIV_ROUND_UP(src_clk_freq * 120, + 1000000) + 7; + + // Slave with frequency 24-40 MHZ + } else { + hldt = 7; + dbnct = 2; + } + } + + // Frequency larger than 1 MHZ + else + return false; + + // After clock parameters calculation update the reg + iowrite8((ioread8(bus->reg + NPCM_SMBCTL2) + & ~SMBCTL2_SCLFRQ6_0) | FIELD_PREP(SMBCTL2_SCLFRQ6_0, + sclfrq & 0x7F), bus->reg + NPCM_SMBCTL2); + + iowrite8((ioread8(bus->reg + NPCM_SMBCTL3) & ~SMBCTL3_SCLFRQ8_7) | + FIELD_PREP(SMBCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3), + bus->reg + NPCM_SMBCTL3); + + iowrite8((ioread8(bus->reg + NPCM_SMBCTL3) & ~SMBCTL3_400K_MODE) | + FIELD_PREP(SMBCTL3_400K_MODE, fast_mode), + bus->reg + NPCM_SMBCTL3); + + // Select Bank 0 to access NPCM_SMBCTL4/NPCM_SMBCTL5 + npcm_smb_select_bank(bus, SMB_BANK_0); + + if (bus_freq >= SMBUS_FREQ_400KHZ) { + // k1 and k2 are relevant for master mode only + if (mode == SMB_MASTER) { + // Set SCL Low/High Time: + // k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2 + // k2 = 2 * SCLLT7-0 -> High Time = k2 / 2 + iowrite8((u8)k1 / 2, bus->reg + NPCM_SMBSCLLT); + iowrite8((u8)k2 / 2, bus->reg + NPCM_SMBSCLHT); + } else { // DBNCT is relevant for slave mode only + iowrite8((ioread8(bus->reg + NPCM_SMBCTL5) & + ~SMBCTL5_DBNCT) | + FIELD_PREP(SMBCTL5_DBNCT, dbnct), + bus->reg + NPCM_SMBCTL5); + } + } + + iowrite8((ioread8(bus->reg + NPCM_SMBCTL4) & ~SMBCTL4_HLDT) + | FIELD_PREP(SMBCTL4_HLDT, hldt), bus->reg + NPCM_SMBCTL4); + + // Return to Bank 1, and stay there by default: + npcm_smb_select_bank(bus, SMB_BANK_1); + + dev_dbg(bus->dev, "k1 = %d k2 = %d dbnct = %d sclfrq = %d hldt = %d src_clk_freq %d fast_mode %d\n", + k1, k2, dbnct, sclfrq, hldt, src_clk_freq, fast_mode); + + return true; +} + +static bool npcm_smb_init_module(struct npcm_i2c *bus, enum smb_mode mode, + u32 bus_freq) +{ + // Check whether module already enabled or frequency is out of bounds + if ((bus->state != SMB_DISABLE && bus->state != SMB_IDLE) || + bus_freq < SMBUS_FREQ_MIN || bus_freq > SMBUS_FREQ_MAX) + return false; + // Configure FIFO disabled mode so slave will not use fifo + // (maste will set it on if supported) + bus->threshold_fifo = SMBUS_FIFO_SIZE; + iowrite8(ioread8(bus->reg + NPCM_SMBFIF_CTL) & ~NPCM_SMBFIF_CTL_FIFO_EN, + bus->reg + NPCM_SMBFIF_CTL); + + bus->fifo_use = false; + + // Configure SMB module clock frequency + if (!npcm_smb_init_clk(bus, mode, bus_freq)) { + pr_err("npcm_smb_init_clk failed\n"); + return false; + } + npcm_smb_disable(bus); + + // Enable module (before configuring CTL1) + npcm_smb_enable(bus); + bus->state = SMB_IDLE; + + // Enable SMB int and New Address Match int source + iowrite8((ioread8(bus->reg + NPCM_SMBCTL1) | NPCM_SMBCTL1_NMINTE) & + ~NPCM_SMBCTL1_RWS_FIELDS, + bus->reg + NPCM_SMBCTL1); + + npcm_smb_int_enable(bus, true); + return true; +} + +static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev) +{ + u32 clk_freq; + int ret; + + // Initialize the internal data structures + bus->state = SMB_DISABLE; + bus->master_or_slave = SMB_SLAVE; + + ret = of_property_read_u32(pdev->dev.of_node, + "bus-frequency", &clk_freq); + if (ret < 0) { + dev_err(&pdev->dev, + "Could not read bus-frequency property\n"); + clk_freq = 100000; + } + ret = npcm_smb_init_module(bus, SMB_MASTER, clk_freq / 1000); + if (!ret) { + dev_err(&pdev->dev, + "npcm_smb_init_module() failed\n"); + return -1; + } + + crc8_populate_lsb(npcm7xx_crc8, 0x07); + crc8_populate_msb(npcm7xx_crc8, 0x07); + return 0; +} + +static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id) +{ + struct npcm_i2c *bus = dev_id; + + bus->int_cnt++; + _npcm7xx_get_time_stamp(&bus->int_time_stamp[0], + &bus->int_time_stamp[1]); + if (bus->master_or_slave == SMB_MASTER) { + npcm_smb_int_master_handler(bus); + return IRQ_HANDLED; + } + + dev_err(bus->dev, "int unknown on bus%d\n", bus->num); + return IRQ_NONE; +} + +static bool npcm_smb_master_start_xmit(struct npcm_i2c *bus, + u8 slave_addr, u16 nwrite, u16 nread, + u8 *write_data, u8 *read_data, + bool use_PEC) +{ + // + // Allow only if bus is not busy + // + if (bus->state != SMB_IDLE) { + dev_info(bus->dev, "\tbus%d->state != SMB_IDLE\n", bus->num); + return false; + } + + // Configure FIFO mode : + if (FIELD_GET(SMB_VER_FIFO_EN, ioread8(bus->reg + SMB_VER))) { + bus->fifo_use = true; + iowrite8(ioread8(bus->reg + NPCM_SMBFIF_CTL) | + NPCM_SMBFIF_CTL_FIFO_EN, bus->reg + NPCM_SMBFIF_CTL); + } else { + bus->fifo_use = false; + } + + // Update driver state + bus->master_or_slave = SMB_MASTER; + bus->state = SMB_MASTER_START; + if (nwrite > 0) + bus->operation = SMB_WRITE_OPER; + else + bus->operation = SMB_READ_OPER; + + if (npcm_smb_is_quick(bus)) + bus->operation = SMB_WRITE_OPER; // send the address with W bit. + + bus->dest_addr = (u8)(slave_addr << 1);// Translate 7bit to 8bit format + bus->wr_buf = write_data; + bus->wr_size = nwrite; + bus->wr_ind = 0; + bus->rd_buf = read_data; + bus->rd_size = nread; + bus->rd_ind = 0; + bus->PEC_use = use_PEC; + bus->retry_count = SMB_RETRY_MAX_COUNT; + + // clear BER just in case it is set due to a previous transaction + iowrite8(NPCM_SMBST_BER, bus->reg + NPCM_SMBST); + + // Initiate SMBus master transaction + // Generate a Start condition on the SMBus + if (bus->fifo_use) { + // select bank 1 for FIFO regs + npcm_smb_select_bank(bus, SMB_BANK_1); + + // clear FIFO and relevant status bits. + iowrite8(ioread8(bus->reg + NPCM_SMBFIF_CTS) | + NPCM_SMBFIF_CTS_SLVRSTR | + NPCM_SMBFIF_CTS_CLR_FIFO | + NPCM_SMBFIF_CTS_RXF_TXE, bus->reg + NPCM_SMBFIF_CTS); + + if (bus->operation == SMB_READ_OPER) { + //This is a read only operation. Configure the FIFO + //threshold according to the needed # of bytes to read. + npcm_smb_set_fifo(bus, nread, -1); + } else if (bus->operation == SMB_WRITE_OPER) { + npcm_smb_set_fifo(bus, -1, nwrite); + } + } + + bus->int_cnt = 0; + bus->event_log = 0; + npcm_smb_master_start(bus); + + return true; +} + +static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, + int num) +{ + struct npcm_i2c *bus = adap->algo_data; + struct i2c_msg *msg0, *msg1; + unsigned long time_left, flags; + u16 nwrite, nread; + u8 *write_data, *read_data; + u8 slave_addr; + int ret = 0; + + spin_lock_irqsave(&bus->lock, flags); + bus->cmd_err = -EPERM; + bus->int_cnt = 0; + bus->stop_ind = SMB_NO_STATUS_IND; + bus->read_block_use = false; + + iowrite8(0xFF, bus->reg + NPCM_SMBST); + + if (num > 2 || num < 1) { + pr_err("I2C command not supported, num of msgs = %d\n", num); + spin_unlock_irqrestore(&bus->lock, flags); + return -EINVAL; + } + + msg0 = &msgs[0]; + slave_addr = msg0->addr; + if (msg0->flags & I2C_M_RD) { // read + if (num == 2) { + pr_err(" num = 2 but first msg is rd instead of wr\n"); + spin_unlock_irqrestore(&bus->lock, flags); + return -EINVAL; + } + nwrite = 0; + write_data = NULL; + if (msg0->flags & I2C_M_RECV_LEN) { + nread = 1; + bus->read_block_use = true; + + } else { + nread = msg0->len; + } + read_data = msg0->buf; + + } else { // write + nwrite = msg0->len; + write_data = msg0->buf; + nread = 0; + read_data = NULL; + if (num == 2) { + msg1 = &msgs[1]; + if (slave_addr != msg1->addr) { + pr_err("SA==%02x but msg1->addr == %02x\n", + slave_addr, msg1->addr); + spin_unlock_irqrestore(&bus->lock, flags); + return -EINVAL; + } + if ((msg1->flags & I2C_M_RD) == 0) { + pr_err("num = 2 but both msg are write.\n"); + spin_unlock_irqrestore(&bus->lock, flags); + return -EINVAL; + } + if (msg1->flags & I2C_M_RECV_LEN) { + nread = 1; + bus->read_block_use = true; + } else { + nread = msg1->len; + bus->read_block_use = false; + } + + read_data = msg1->buf; + } + } + + bus->msgs = msgs; + bus->msgs_num = num; + + if (nwrite >= 32 * 1024 || nread >= 32 * 1024) { + pr_err("i2c%d buffer too big\n", bus->num); + return -EINVAL; + } + + reinit_completion(&bus->cmd_complete); + + if (npcm_smb_master_start_xmit(bus, slave_addr, nwrite, nread, + write_data, read_data, 0) == false) + ret = -(EBUSY); + + if (ret != -(EBUSY)) { + time_left = wait_for_completion_timeout(&bus->cmd_complete, + bus->adap.timeout); + + if (time_left == 0 && bus->cmd_err == -EPERM) { + npcm_smb_master_abort(bus); + ret = -ETIMEDOUT; + } else { + ret = bus->cmd_err; + } + } + + bus->msgs = NULL; + bus->msgs_num = 0; + spin_unlock_irqrestore(&bus->lock, flags); + + // If nothing went wrong, return number of messages xferred. + if (ret >= 0) + return num; + else + return ret; +} + +static u32 npcm_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; +} + +static const struct i2c_algorithm npcm_i2c_algo = { + .master_xfer = npcm_i2c_master_xfer, + .functionality = npcm_i2c_functionality, +}; + +static struct i2c_bus_recovery_info npcm_i2c_recovery = { + .recover_bus = npcm_smb_recovery, + .get_scl = npcm_smb_get_SCL, + .set_scl = npcm_smb_set_SCL, + .get_sda = npcm_smb_get_SDA, +}; + +static int npcm_i2c_probe_bus(struct platform_device *pdev) +{ + struct npcm_i2c *bus; + struct resource *res; + struct clk *i2c_clk; + int ret; + int num; + + bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); + if (!bus) + return -ENOMEM; + +#ifdef CONFIG_OF + num = of_alias_get_id(pdev->dev.of_node, "i2c"); + bus->num = num; + i2c_clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(i2c_clk)) { + pr_err(" I2C probe failed: can't read clk.\n"); + return -EPROBE_DEFER; + } + bus->apb_clk = clk_get_rate(i2c_clk); + dev_dbg(bus->dev, "I2C APB clock is %d\n", bus->apb_clk); +#endif // CONFIG_OF + + gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); + if (IS_ERR(gcr_regmap)) { + pr_err("%s: failed to find nuvoton,npcm750-gcr\n", __func__); + return IS_ERR(gcr_regmap); + } + regmap_write(gcr_regmap, NPCM_I2CSEGCTL, I2CSEGCTL_VAL); + dev_dbg(bus->dev, "I2C%d: gcr mapped\n", bus->num); + + clk_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-clk"); + if (IS_ERR(clk_regmap)) { + pr_err("%s: failed to find nuvoton,npcm750-clk\n", __func__); + return IS_ERR(clk_regmap); + } + dev_dbg(bus->dev, "I2C%d: clk mapped\n", bus->num); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dev_dbg(bus->dev, "resource: %pR\n", res); + bus->reg = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR((bus)->reg)) + return PTR_ERR((bus)->reg); + dev_dbg(bus->dev, "base = %p\n", bus->reg); + + // Initialize the I2C adapter + spin_lock_init(&bus->lock); + init_completion(&bus->cmd_complete); + bus->adap.owner = THIS_MODULE; + bus->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + bus->adap.retries = 0; + bus->adap.timeout = 500 * HZ / 1000; + bus->adap.algo = &npcm_i2c_algo; + bus->adap.algo_data = bus; + bus->adap.dev.parent = &pdev->dev; + bus->adap.dev.of_node = pdev->dev.of_node; + bus->adap.bus_recovery_info = &npcm_i2c_recovery; + + snprintf(bus->adap.name, sizeof(bus->adap.name), "Nuvoton i2c"); + + bus->dev = &pdev->dev; + + ret = __npcm_i2c_init(bus, pdev); + if (ret < 0) + return ret; + + bus->irq = platform_get_irq(pdev, 0); + if (bus->irq < 0) { + pr_err("I2C platform_get_irq error."); + return -ENODEV; + } + dev_dbg(bus->dev, "irq = %d\n", bus->irq); + + ret = request_irq(bus->irq, npcm_i2c_bus_irq, 0, + dev_name(&pdev->dev), (void *)bus); + if (ret) { + dev_err(&pdev->dev, "I2C%d: request_irq fail\n", bus->num); + return ret; + } + + ret = i2c_add_adapter(&bus->adap); + if (ret < 0) { + dev_err(&pdev->dev, "I2C%d: i2c_add_adapter fail\n", bus->num); + return ret; + } + + platform_set_drvdata(pdev, bus); + pr_info("i2c bus %d registered\n", bus->adap.nr); + + return 0; +} + +static int npcm_i2c_remove_bus(struct platform_device *pdev) +{ + unsigned long lock_flags; + struct npcm_i2c *bus = platform_get_drvdata(pdev); + + spin_lock_irqsave(&bus->lock, lock_flags); + npcm_smb_disable(bus); + spin_unlock_irqrestore(&bus->lock, lock_flags); + i2c_del_adapter(&bus->adap); + + return 0; +} + +static const struct of_device_id npcm_i2c_bus_of_table[] = { + { .compatible = "nuvoton,npcm750-i2c", }, + {}, +}; +MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table); + +static struct platform_driver npcm_i2c_bus_driver = { + .probe = npcm_i2c_probe_bus, + .remove = npcm_i2c_remove_bus, + .driver = { + .name = "nuvoton-i2c", + .of_match_table = npcm_i2c_bus_of_table, + } +}; +module_platform_driver(npcm_i2c_bus_driver); + +MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>"); +MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>"); +MODULE_DESCRIPTION("Nuvoton I2C Bus Driver"); +MODULE_LICENSE("GPL v2"); +MODULE_VERSION(I2C_VERSION); diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index f129f9678940..5d8954652e6d 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -629,6 +629,20 @@ config MFD_INTEL_MSIC Passage) chip. This chip embeds audio, battery, GPIO, etc. devices used in Intel Medfield platforms. +config MFD_INTEL_PECI_CLIENT + bool "Intel PECI client" + depends on (PECI || COMPILE_TEST) + select MFD_CORE + help + If you say yes to this option, support will be included for the + Intel PECI (Platform Environment Control Interface) client. PECI is a + one-wire bus interface that provides a communication channel from PECI + clients in Intel processors and chipset components to external + monitoring or control devices. + + Additional drivers must be enabled in order to use the functionality + of the device. + config MFD_IPAQ_MICRO bool "Atmel Micro ASIC (iPAQ h3100/h3600/h3700) Support" depends on SA1100_H3100 || SA1100_H3600 diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index f026ada68f6a..abef75cb2a86 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -215,6 +215,7 @@ obj-$(CONFIG_MFD_INTEL_LPSS) += intel-lpss.o obj-$(CONFIG_MFD_INTEL_LPSS_PCI) += intel-lpss-pci.o obj-$(CONFIG_MFD_INTEL_LPSS_ACPI) += intel-lpss-acpi.o obj-$(CONFIG_MFD_INTEL_MSIC) += intel_msic.o +obj-$(CONFIG_MFD_INTEL_PECI_CLIENT) += intel-peci-client.o obj-$(CONFIG_MFD_PALMAS) += palmas.o obj-$(CONFIG_MFD_VIPERBOARD) += viperboard.o obj-$(CONFIG_MFD_RC5T583) += rc5t583.o rc5t583-irq.o diff --git a/drivers/mfd/intel-peci-client.c b/drivers/mfd/intel-peci-client.c new file mode 100644 index 000000000000..d53e4f1078ac --- /dev/null +++ b/drivers/mfd/intel-peci-client.c @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Intel Corporation + +#include <linux/bitfield.h> +#include <linux/mfd/core.h> +#include <linux/mfd/intel-peci-client.h> +#include <linux/module.h> +#include <linux/peci.h> +#include <linux/of_device.h> + +#define CPU_ID_MODEL_MASK GENMASK(7, 4) +#define CPU_ID_FAMILY_MASK GENMASK(11, 8) +#define CPU_ID_EXT_MODEL_MASK GENMASK(19, 16) +#define CPU_ID_EXT_FAMILY_MASK GENMASK(27, 20) + +#define LOWER_NIBBLE_MASK GENMASK(3, 0) +#define UPPER_NIBBLE_MASK GENMASK(7, 4) +#define LOWER_BYTE_MASK GENMASK(7, 0) +#define UPPER_BYTE_MASK GENMASK(16, 8) + +enum cpu_gens { + CPU_GEN_HSX = 0, /* Haswell Xeon */ + CPU_GEN_BRX, /* Broadwell Xeon */ + CPU_GEN_SKX, /* Skylake Xeon */ +}; + +static struct mfd_cell peci_functions[] = { + { .name = "peci-cputemp", }, + { .name = "peci-dimmtemp", }, + /* TODO: Add additional PECI sideband functions into here */ +}; + +static const struct cpu_gen_info cpu_gen_info_table[] = { + [CPU_GEN_HSX] = { + .family = 6, /* Family code */ + .model = INTEL_FAM6_HASWELL_X, + .core_max = CORE_MAX_ON_HSX, + .chan_rank_max = CHAN_RANK_MAX_ON_HSX, + .dimm_idx_max = DIMM_IDX_MAX_ON_HSX }, + [CPU_GEN_BRX] = { + .family = 6, /* Family code */ + .model = INTEL_FAM6_BROADWELL_X, + .core_max = CORE_MAX_ON_BDX, + .chan_rank_max = CHAN_RANK_MAX_ON_BDX, + .dimm_idx_max = DIMM_IDX_MAX_ON_BDX }, + [CPU_GEN_SKX] = { + .family = 6, /* Family code */ + .model = INTEL_FAM6_SKYLAKE_X, + .core_max = CORE_MAX_ON_SKX, + .chan_rank_max = CHAN_RANK_MAX_ON_SKX, + .dimm_idx_max = DIMM_IDX_MAX_ON_SKX }, +}; + +static int peci_client_get_cpu_gen_info(struct peci_client_manager *priv) +{ + u32 cpu_id; + u16 family; + u8 model; + int rc; + int i; + + rc = peci_get_cpu_id(priv->client->adapter, priv->client->addr, + &cpu_id); + if (rc) + return rc; + + family = FIELD_PREP(LOWER_BYTE_MASK, + FIELD_GET(CPU_ID_FAMILY_MASK, cpu_id)) | + FIELD_PREP(UPPER_BYTE_MASK, + FIELD_GET(CPU_ID_EXT_FAMILY_MASK, cpu_id)); + model = FIELD_PREP(LOWER_NIBBLE_MASK, + FIELD_GET(CPU_ID_MODEL_MASK, cpu_id)) | + FIELD_PREP(UPPER_NIBBLE_MASK, + FIELD_GET(CPU_ID_EXT_MODEL_MASK, cpu_id)); + + for (i = 0; i < ARRAY_SIZE(cpu_gen_info_table); i++) { + const struct cpu_gen_info *cpu_info = &cpu_gen_info_table[i]; + + if (family == cpu_info->family && model == cpu_info->model) { + priv->gen_info = cpu_info; + break; + } + } + + if (!priv->gen_info) { + dev_err(priv->dev, "Can't support this CPU: 0x%x\n", cpu_id); + rc = -ENODEV; + } + + return rc; +} + +static int peci_client_probe(struct peci_client *client) +{ + struct device *dev = &client->dev; + struct peci_client_manager *priv; + uint cpu_no; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + dev_set_drvdata(dev, priv); + priv->client = client; + priv->dev = dev; + cpu_no = client->addr - PECI_BASE_ADDR; + + ret = peci_client_get_cpu_gen_info(priv); + if (ret) + return ret; + + ret = devm_mfd_add_devices(priv->dev, cpu_no, peci_functions, + ARRAY_SIZE(peci_functions), NULL, 0, NULL); + if (ret < 0) { + dev_err(priv->dev, "Failed to register child devices: %d\n", + ret); + return ret; + } + + return 0; +} + +#ifdef CONFIG_OF +static const struct of_device_id peci_client_of_table[] = { + { .compatible = "intel,peci-client" }, + { } +}; +MODULE_DEVICE_TABLE(of, peci_client_of_table); +#endif + +static const struct peci_device_id peci_client_ids[] = { + { .name = "peci-client" }, + { } +}; +MODULE_DEVICE_TABLE(peci, peci_client_ids); + +static struct peci_driver peci_client_driver = { + .probe = peci_client_probe, + .id_table = peci_client_ids, + .driver = { + .name = "peci-client", + .of_match_table = of_match_ptr(peci_client_of_table), + }, +}; +module_peci_driver(peci_client_driver); + +MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>"); +MODULE_DESCRIPTION("PECI client driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 16900357afc2..d681b7201f8c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -488,6 +488,21 @@ config PVPANIC a paravirtualized device provided by QEMU; it lets a virtual machine (guest) communicate panic events to the host. +config NPCM7XX_LPC_BPC + tristate "NPCM7xx LPC BIOS Post Code support" + depends on (ARCH_NPCM7XX || COMPILE_TEST) + help + Provides a NPCM7xx driver to control the LPC BIOS Post Code + interface which allows the BMC to monitoring and save + the data written by the host to an arbitrary LPC I/O port. + +config NPCM7XX_PCI_MBOX + tristate "NPCM7xx PCI Mailbox Controller" + depends on (ARCH_NPCM7XX || COMPILE_TEST) && REGMAP && MFD_SYSCON + help + Expose the NPCM750/730/715/705 PCI MBOX registers found on + Nuvoton SOCs to userspace. + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index abd8ae249746..fdd404120ed8 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -59,3 +59,5 @@ obj-y += cardreader/ obj-$(CONFIG_PVPANIC) += pvpanic.o obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o +obj-$(CONFIG_NPCM7XX_LPC_BPC) += npcm7xx-lpc-bpc.o +obj-$(CONFIG_NPCM7XX_PCI_MBOX) += npcm7xx-pci-mbox.o diff --git a/drivers/misc/npcm7xx-lpc-bpc.c b/drivers/misc/npcm7xx-lpc-bpc.c new file mode 100644 index 000000000000..e014e07cd4a4 --- /dev/null +++ b/drivers/misc/npcm7xx-lpc-bpc.c @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2014-2018 Nuvoton Technology corporation. + +#include <linux/fs.h> +#include <linux/bitops.h> +#include <linux/interrupt.h> +#include <linux/kfifo.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/miscdevice.h> +#include <linux/poll.h> + +#define DEVICE_NAME "npcm7xx-lpc-bpc" + +#define NUM_BPC_CHANNELS 2 +#define DW_PAD_SIZE 3 + +/* BIOS POST Code FIFO Registers */ +#define NPCM7XX_BPCFA2L_REG 0x2 //BIOS POST Code FIFO Address 2 LSB +#define NPCM7XX_BPCFA2M_REG 0x4 //BIOS POST Code FIFO Address 2 MSB +#define NPCM7XX_BPCFEN_REG 0x6 //BIOS POST Code FIFO Enable +#define NPCM7XX_BPCFSTAT_REG 0x8 //BIOS POST Code FIFO Status +#define NPCM7XX_BPCFDATA_REG 0xA //BIOS POST Code FIFO Data +#define NPCM7XX_BPCFMSTAT_REG 0xC //BIOS POST Code FIFO Miscellaneous Status +#define NPCM7XX_BPCFA1L_REG 0x10 //BIOS POST Code FIFO Address 1 LSB +#define NPCM7XX_BPCFA1M_REG 0x12 //BIOS POST Code FIFO Address 1 MSB + +/*BIOS regiser data*/ +#define FIFO_IOADDR1_ENABLE 0x80 +#define FIFO_IOADDR2_ENABLE 0x40 + +/* BPC interface package and structure definition */ +#define BPC_KFIFO_SIZE 0x400 + +/*BPC regiser data*/ +#define FIFO_DATA_VALID 0x80 +#define FIFO_OVERFLOW 0x20 +#define FIFO_READY_INT_ENABLE 0x8 +#define FIFO_DWCAPTURE 0x4 +#define FIFO_ADDR_DECODE 0x1 + +/*Host Reset*/ +#define HOST_RESET_INT_ENABLE 0x10 +#define HOST_RESET_CHANGED 0x40 + +struct npcm7xx_bpc_channel { + struct npcm7xx_bpc *data; + struct kfifo fifo; + wait_queue_head_t wq; + bool host_reset; + struct miscdevice miscdev; +}; + +struct npcm7xx_bpc { + void __iomem *base; + int irq; + bool en_dwcap; + struct npcm7xx_bpc_channel ch[NUM_BPC_CHANNELS]; +}; + +static struct npcm7xx_bpc_channel *npcm7xx_file_to_ch(struct file *file) +{ + return container_of(file->private_data, struct npcm7xx_bpc_channel, + miscdev); +} + +static ssize_t npcm7xx_bpc_read(struct file *file, char __user *buffer, + size_t count, loff_t *ppos) +{ + struct npcm7xx_bpc_channel *chan = npcm7xx_file_to_ch(file); + struct npcm7xx_bpc *lpc_bpc = chan->data; + unsigned int copied; + int ret = 0; + int cond_size = 1; + + if (lpc_bpc->en_dwcap) + cond_size = 3; + + if (kfifo_len(&chan->fifo) < cond_size) { + if (file->f_flags & O_NONBLOCK) + return -EAGAIN; + + ret = wait_event_interruptible + (chan->wq, kfifo_len(&chan->fifo) > cond_size); + if (ret == -ERESTARTSYS) + return -EINTR; + } + + ret = kfifo_to_user(&chan->fifo, buffer, count, &copied); + + return ret ? ret : copied; +} + +static __poll_t npcm7xx_bpc_poll(struct file *file, + struct poll_table_struct *pt) +{ + struct npcm7xx_bpc_channel *chan = npcm7xx_file_to_ch(file); + __poll_t mask = 0; + + poll_wait(file, &chan->wq, pt); + if (!kfifo_is_empty(&chan->fifo)) + mask |= POLLIN; + + if (chan->host_reset) { + mask |= POLLHUP; + chan->host_reset = false; + } + + return mask; +} + +static const struct file_operations npcm7xx_bpc_fops = { + .owner = THIS_MODULE, + .read = npcm7xx_bpc_read, + .poll = npcm7xx_bpc_poll, + .llseek = noop_llseek, +}; + +static irqreturn_t npcm7xx_bpc_irq(int irq, void *arg) +{ + struct npcm7xx_bpc *lpc_bpc = arg; + u8 fifo_st; + u8 host_st; + u8 addr_index = 0; + u8 Data; + u8 padzero[3] = {0}; + u8 last_addr_bit = 0; + bool isr_flag = false; + + fifo_st = ioread8(lpc_bpc->base + NPCM7XX_BPCFSTAT_REG); + while (FIFO_DATA_VALID & fifo_st) { + /* If dwcapture enabled only channel 0 (FIFO 0) used */ + if (!lpc_bpc->en_dwcap) + addr_index = fifo_st & FIFO_ADDR_DECODE; + else + last_addr_bit = fifo_st & FIFO_ADDR_DECODE; + + /*Read data from FIFO to clear interrupt*/ + Data = ioread8(lpc_bpc->base + NPCM7XX_BPCFDATA_REG); + if (kfifo_is_full(&lpc_bpc->ch[addr_index].fifo)) + kfifo_skip(&lpc_bpc->ch[addr_index].fifo); + kfifo_put(&lpc_bpc->ch[addr_index].fifo, Data); + if (fifo_st & FIFO_OVERFLOW) + pr_info("BIOS Post Codes FIFO Overflow!!!\n"); + + fifo_st = ioread8(lpc_bpc->base + NPCM7XX_BPCFSTAT_REG); + if (lpc_bpc->en_dwcap && last_addr_bit) { + if ((fifo_st & FIFO_ADDR_DECODE) || + ((FIFO_DATA_VALID & fifo_st) == 0)) { + while (kfifo_avail(&lpc_bpc->ch[addr_index].fifo) < DW_PAD_SIZE) + kfifo_skip(&lpc_bpc->ch[addr_index].fifo); + kfifo_in(&lpc_bpc->ch[addr_index].fifo, + padzero, DW_PAD_SIZE); + } + } + isr_flag = true; + } + + host_st = ioread8(lpc_bpc->base + NPCM7XX_BPCFMSTAT_REG); + if (host_st & HOST_RESET_CHANGED) { + iowrite8(HOST_RESET_CHANGED, + lpc_bpc->base + NPCM7XX_BPCFMSTAT_REG); + lpc_bpc->ch[addr_index].host_reset = true; + isr_flag = true; + } + + if (isr_flag) { + wake_up_interruptible(&lpc_bpc->ch[addr_index].wq); + return IRQ_HANDLED; + } + + return IRQ_NONE; +} + +static int npcm7xx_bpc_config_irq(struct npcm7xx_bpc *lpc_bpc, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int rc; + + lpc_bpc->irq = platform_get_irq(pdev, 0); + if (lpc_bpc->irq < 0) { + dev_err(dev, "get IRQ failed\n"); + return lpc_bpc->irq; + } + + rc = devm_request_irq(dev, lpc_bpc->irq, + npcm7xx_bpc_irq, IRQF_SHARED, + DEVICE_NAME, lpc_bpc); + if (rc < 0) { + dev_warn(dev, "Unable to request IRQ %d\n", lpc_bpc->irq); + return rc; + } + + return 0; +} + +static int npcm7xx_enable_bpc(struct npcm7xx_bpc *lpc_bpc, struct device *dev, + int channel, u16 lpc_port) +{ + int rc; + u8 addr_en, reg_en; + + init_waitqueue_head(&lpc_bpc->ch[channel].wq); + + rc = kfifo_alloc(&lpc_bpc->ch[channel].fifo, + BPC_KFIFO_SIZE, GFP_KERNEL); + if (rc) + return rc; + + lpc_bpc->ch[channel].miscdev.minor = MISC_DYNAMIC_MINOR; + lpc_bpc->ch[channel].miscdev.name = + devm_kasprintf(dev, GFP_KERNEL, "%s%d", DEVICE_NAME, channel); + lpc_bpc->ch[channel].miscdev.fops = &npcm7xx_bpc_fops; + lpc_bpc->ch[channel].miscdev.parent = dev; + rc = misc_register(&lpc_bpc->ch[channel].miscdev); + if (rc) + return rc; + + lpc_bpc->ch[channel].data = lpc_bpc; + lpc_bpc->ch[channel].host_reset = false; + + /* Enable LPC snoop channel at requested port */ + switch (channel) { + case 0: + addr_en = FIFO_IOADDR1_ENABLE; + iowrite8((u8)lpc_port & 0xFF, + lpc_bpc->base + NPCM7XX_BPCFA1L_REG); + iowrite8((u8)(lpc_port >> 8), + lpc_bpc->base + NPCM7XX_BPCFA1M_REG); + break; + case 1: + addr_en = FIFO_IOADDR2_ENABLE; + iowrite8((u8)lpc_port & 0xFF, + lpc_bpc->base + NPCM7XX_BPCFA2L_REG); + iowrite8((u8)(lpc_port >> 8), + lpc_bpc->base + NPCM7XX_BPCFA2M_REG); + break; + default: + return -EINVAL; + } + + if (lpc_bpc->en_dwcap) + addr_en = FIFO_DWCAPTURE; + + /* + * Enable FIFO Ready Interrupt, FIFO Capture of I/O addr, + * and Host Reset + */ + reg_en = ioread8(lpc_bpc->base + NPCM7XX_BPCFEN_REG); + iowrite8(reg_en | addr_en | FIFO_READY_INT_ENABLE | + HOST_RESET_INT_ENABLE, lpc_bpc->base + NPCM7XX_BPCFEN_REG); + + return 0; +} + +static void npcm7xx_disable_bpc(struct npcm7xx_bpc *lpc_bpc, int channel) +{ + u8 reg_en; + + switch (channel) { + case 0: + reg_en = ioread8(lpc_bpc->base + NPCM7XX_BPCFEN_REG); + if (lpc_bpc->en_dwcap) + iowrite8(reg_en & ~FIFO_DWCAPTURE, + lpc_bpc->base + NPCM7XX_BPCFEN_REG); + else + iowrite8(reg_en & ~FIFO_IOADDR1_ENABLE, + lpc_bpc->base + NPCM7XX_BPCFEN_REG); + break; + case 1: + reg_en = ioread8(lpc_bpc->base + NPCM7XX_BPCFEN_REG); + iowrite8(reg_en & ~FIFO_IOADDR2_ENABLE, + lpc_bpc->base + NPCM7XX_BPCFEN_REG); + break; + default: + return; + } + + if (!(reg_en & (FIFO_IOADDR1_ENABLE | FIFO_IOADDR2_ENABLE))) + iowrite8(reg_en & + ~(FIFO_READY_INT_ENABLE | HOST_RESET_INT_ENABLE), + lpc_bpc->base + NPCM7XX_BPCFEN_REG); + + kfifo_free(&lpc_bpc->ch[channel].fifo); + misc_deregister(&lpc_bpc->ch[channel].miscdev); +} + +static int npcm7xx_bpc_probe(struct platform_device *pdev) +{ + struct npcm7xx_bpc *lpc_bpc; + struct resource *res; + struct device *dev; + u32 port; + int rc; + + dev = &pdev->dev; + + lpc_bpc = devm_kzalloc(dev, sizeof(*lpc_bpc), GFP_KERNEL); + if (!lpc_bpc) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(dev, "BIOS post code reg resource not found\n"); + return -ENODEV; + } + + dev_dbg(dev, "BIOS post code base resource is %pR\n", res); + lpc_bpc->base = devm_ioremap_resource(dev, res); + if (IS_ERR(lpc_bpc->base)) + return PTR_ERR(lpc_bpc->base); + + dev_set_drvdata(&pdev->dev, lpc_bpc); + + rc = of_property_read_u32_index(dev->of_node, "monitor-ports", 0, + &port); + if (rc) { + dev_err(dev, "no monitor ports configured\n"); + return -ENODEV; + } + + lpc_bpc->en_dwcap = + of_property_read_bool(dev->of_node, "bpc-en-dwcapture"); + + rc = npcm7xx_bpc_config_irq(lpc_bpc, pdev); + if (rc) + return rc; + + rc = npcm7xx_enable_bpc(lpc_bpc, dev, 0, port); + if (rc) { + dev_err(dev, "Enable BIOS post code I/O port 0 failed\n"); + return rc; + } + + /* + * Configuration of second BPC channel port is optional + * Double-Word Capture ignoring address 2 + */ + if (!lpc_bpc->en_dwcap) { + if (of_property_read_u32_index(dev->of_node, "monitor-ports", + 1, &port) == 0) { + rc = npcm7xx_enable_bpc(lpc_bpc, dev, 1, port); + if (rc) { + dev_err(dev, "Enable BIOS post code I/O port 1 failed, disable I/O port 0\n"); + npcm7xx_disable_bpc(lpc_bpc, 0); + return rc; + } + } + } + + pr_info("npcm7xx BIOS post code probe\n"); + + return rc; +} + +static int npcm7xx_bpc_remove(struct platform_device *pdev) +{ + struct npcm7xx_bpc *lpc_bpc = dev_get_drvdata(&pdev->dev); + u8 reg_en; + + reg_en = ioread8(lpc_bpc->base + NPCM7XX_BPCFEN_REG); + + if (reg_en & FIFO_IOADDR1_ENABLE) + npcm7xx_disable_bpc(lpc_bpc, 0); + if (reg_en & FIFO_IOADDR2_ENABLE) + npcm7xx_disable_bpc(lpc_bpc, 1); + + return 0; +} + +static const struct of_device_id npcm7xx_bpc_match[] = { + { .compatible = "nuvoton,npcm750-lpc-bpc" }, + { }, +}; + +static struct platform_driver npcm7xx_bpc_driver = { + .driver = { + .name = DEVICE_NAME, + .of_match_table = npcm7xx_bpc_match, + }, + .probe = npcm7xx_bpc_probe, + .remove = npcm7xx_bpc_remove, +}; + +module_platform_driver(npcm7xx_bpc_driver); + +MODULE_DEVICE_TABLE(of, npcm7xx_bpc_match); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); +MODULE_DESCRIPTION("Linux driver to control NPCM7XX LPC BIOS post code monitoring"); diff --git a/drivers/misc/npcm7xx-pci-mbox.c b/drivers/misc/npcm7xx-pci-mbox.c new file mode 100644 index 000000000000..1a80661a4296 --- /dev/null +++ b/drivers/misc/npcm7xx-pci-mbox.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2014-2018 Nuvoton Technology corporation. + +#include <linux/interrupt.h> +#include <linux/mfd/syscon.h> +#include <linux/miscdevice.h> +#include <linux/module.h> +#include <linux/of_irq.h> +#include <linux/platform_device.h> +#include <linux/poll.h> +#include <linux/regmap.h> +#include <linux/slab.h> + +#define DEVICE_NAME "npcm7xx-pci-mbox" + +#define NPCM7XX_MBOX_BMBXSTAT 0x0 +#define NPCM7XX_MBOX_BMBXCTL 0x4 +#define NPCM7XX_MBOX_BMBXCMD 0x8 + +#define NPCM7XX_MBOX_CIF_0 BIT(0) +#define NPCM7XX_MBOX_CIE_0 BIT(0) +#define NPCM7XX_MBOX_HIF_0 BIT(0) + +#define NPCM7XX_MBOX_ALL_CIF GENMASK(7, 0) +#define NPCM7XX_MBOX_ALL_CIE GENMASK(7, 0) +#define NPCM7XX_MBOX_ALL_HIF GENMASK(7, 0) + +struct npcm7xx_mbox { + struct miscdevice miscdev; + struct regmap *regmap; + void __iomem *memory; + wait_queue_head_t queue; + spinlock_t lock; /* mbox access mutex */ + bool cif0; + u32 max_buf_size; +}; + +static atomic_t npcm7xx_mbox_open_count = ATOMIC_INIT(0); + +static struct npcm7xx_mbox *file_mbox(struct file *file) +{ + return container_of(file->private_data, struct npcm7xx_mbox, miscdev); +} + +static int npcm7xx_mbox_open(struct inode *inode, struct file *file) +{ + struct npcm7xx_mbox *mbox = file_mbox(file); + + if (atomic_inc_return(&npcm7xx_mbox_open_count) == 1) { + /* enable mailbox interrupt */ + regmap_update_bits(mbox->regmap, NPCM7XX_MBOX_BMBXCTL, + NPCM7XX_MBOX_ALL_CIE, NPCM7XX_MBOX_CIE_0); + return 0; + } + + atomic_dec(&npcm7xx_mbox_open_count); + return -EBUSY; +} + +static ssize_t npcm7xx_mbox_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + struct npcm7xx_mbox *mbox = file_mbox(file); + unsigned long flags; + + if (!access_ok(buf, count)) + return -EFAULT; + + if ((*ppos + count) > mbox->max_buf_size) + return -EINVAL; + + if (file->f_flags & O_NONBLOCK) { + if (!mbox->cif0) + return -EAGAIN; + } else if (wait_event_interruptible(mbox->queue, mbox->cif0)) { + return -ERESTARTSYS; + } + + spin_lock_irqsave(&mbox->lock, flags); + + if (copy_to_user((void __user *)buf, + (const void *)(mbox->memory + *ppos), count)) { + spin_unlock_irqrestore(&mbox->lock, flags); + return -EFAULT; + } + + mbox->cif0 = false; + spin_unlock_irqrestore(&mbox->lock, flags); + return count; +} + +static ssize_t npcm7xx_mbox_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + struct npcm7xx_mbox *mbox = file_mbox(file); + unsigned long flags; + + if (!access_ok(buf, count)) + return -EFAULT; + + if ((*ppos + count) > mbox->max_buf_size) + return -EINVAL; + + spin_lock_irqsave(&mbox->lock, flags); + + if (copy_from_user((void *)(mbox->memory + *ppos), + (void __user *)buf, count)) { + spin_unlock_irqrestore(&mbox->lock, flags); + return -EFAULT; + } + + regmap_update_bits(mbox->regmap, NPCM7XX_MBOX_BMBXCMD, + NPCM7XX_MBOX_ALL_HIF, NPCM7XX_MBOX_HIF_0); + + spin_unlock_irqrestore(&mbox->lock, flags); + return count; +} + +static unsigned int npcm7xx_mbox_poll(struct file *file, poll_table *wait) +{ + struct npcm7xx_mbox *mbox = file_mbox(file); + unsigned int mask = 0; + + poll_wait(file, &mbox->queue, wait); + if (mbox->cif0) + mask |= POLLIN; + + return mask; +} + +static int npcm7xx_mbox_release(struct inode *inode, struct file *file) +{ + atomic_dec(&npcm7xx_mbox_open_count); + return 0; +} + +static const struct file_operations npcm7xx_mbox_fops = { + .owner = THIS_MODULE, + .llseek = no_seek_end_llseek, + .read = npcm7xx_mbox_read, + .write = npcm7xx_mbox_write, + .open = npcm7xx_mbox_open, + .release = npcm7xx_mbox_release, + .poll = npcm7xx_mbox_poll, +}; + +static irqreturn_t npcm7xx_mbox_irq(int irq, void *arg) +{ + struct npcm7xx_mbox *mbox = arg; + u32 val; + + regmap_read(mbox->regmap, NPCM7XX_MBOX_BMBXSTAT, &val); + if ((val & NPCM7XX_MBOX_CIF_0) != NPCM7XX_MBOX_CIF_0) + return IRQ_NONE; + + /* + * Leave the status bit set so that we know the data is for us, + * clear it once it has been read. + */ + mbox->cif0 = true; + + /* Mask it off, we'll clear it when we the data gets read */ + regmap_write_bits(mbox->regmap, NPCM7XX_MBOX_BMBXSTAT, + NPCM7XX_MBOX_ALL_CIF, NPCM7XX_MBOX_CIF_0); + + wake_up(&mbox->queue); + + return IRQ_HANDLED; +} + +static int npcm7xx_mbox_config_irq(struct npcm7xx_mbox *mbox, + struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int rc, irq; + u32 val; + + /* Disable all register based interrupts */ + regmap_update_bits(mbox->regmap, NPCM7XX_MBOX_BMBXCTL, + NPCM7XX_MBOX_ALL_CIE, 0); +/* + * These registers are write one to clear. Clear them. + * Per spec, cleared bits should not be re-cleared. + * Need to read and clear needed bits only, instead of blindly clearing all. + */ + regmap_read(mbox->regmap, NPCM7XX_MBOX_BMBXSTAT, &val); + val &= NPCM7XX_MBOX_ALL_CIF; + + /* If any bit is set, write back to clear */ + if (val) + regmap_write_bits(mbox->regmap, NPCM7XX_MBOX_BMBXSTAT, + NPCM7XX_MBOX_ALL_CIF, val); + + irq = irq_of_parse_and_map(dev->of_node, 0); + if (!irq) + return -ENODEV; + + rc = devm_request_irq(dev, irq, npcm7xx_mbox_irq, 0, DEVICE_NAME, mbox); + if (rc < 0) { + dev_err(dev, "Unable to request IRQ %d\n", irq); + return rc; + } + + return 0; +} + +static int npcm7xx_mbox_probe(struct platform_device *pdev) +{ + struct npcm7xx_mbox *mbox; + struct device *dev; + struct resource *res; + int rc; + + dev = &pdev->dev; + + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); + if (!mbox) + return -ENOMEM; + + dev_set_drvdata(&pdev->dev, mbox); + + mbox->regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(mbox->regmap)) { + dev_err(dev, "Couldn't get regmap\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + mbox->memory = devm_ioremap_resource(dev, res); + if (IS_ERR(mbox->memory)) + return PTR_ERR(mbox->memory); + mbox->max_buf_size = resource_size(res); + + spin_lock_init(&mbox->lock); + init_waitqueue_head(&mbox->queue); + + mbox->miscdev.minor = MISC_DYNAMIC_MINOR; + mbox->miscdev.name = DEVICE_NAME; + mbox->miscdev.fops = &npcm7xx_mbox_fops; + mbox->miscdev.parent = dev; + mbox->cif0 = false; + rc = misc_register(&mbox->miscdev); + if (rc) { + dev_err(dev, "Unable to register device\n"); + return rc; + } + + rc = npcm7xx_mbox_config_irq(mbox, pdev); + if (rc) { + dev_err(dev, "Failed to configure IRQ\n"); + misc_deregister(&mbox->miscdev); + return rc; + } + + pr_info("NPCM7xx PCI Mailbox probed\n"); + + return 0; +} + +static int npcm7xx_mbox_remove(struct platform_device *pdev) +{ + struct npcm7xx_mbox *mbox = dev_get_drvdata(&pdev->dev); + + misc_deregister(&mbox->miscdev); + + return 0; +} + +static const struct of_device_id npcm7xx_mbox_match[] = { + { .compatible = "nuvoton,npcm750-pci-mbox" }, + { }, +}; + +static struct platform_driver npcm7xx_mbox_driver = { + .driver = { + .name = DEVICE_NAME, + .of_match_table = npcm7xx_mbox_match, + }, + .probe = npcm7xx_mbox_probe, + .remove = npcm7xx_mbox_remove, +}; + +module_platform_driver(npcm7xx_mbox_driver); + +MODULE_DEVICE_TABLE(of, npcm7xx_mbox_match); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); +MODULE_DESCRIPTION("NPCM7XX mailbox device driver"); diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 14d89a108edd..3a52f5703286 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -154,6 +154,18 @@ config MMC_SDHCI_OF_ARASAN If unsure, say N. +config MMC_SDHCI_OF_ASPEED + tristate "SDHCI OF support for the ASPEED SDHCI controller" + depends on MMC_SDHCI_PLTFM + depends on OF && OF_ADDRESS + help + This selects the ASPEED Secure Digital Host Controller Interface. + + If you have a controller with this interface, say Y or M here. You + also need to enable an appropriate bus interface. + + If unsure, say N. + config MMC_SDHCI_OF_AT91 tristate "SDHCI OF support for the Atmel SDMMC controller" depends on MMC_SDHCI_PLTFM diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f119..390ee162fe71 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o obj-$(CONFIG_MMC_SDHCI_OF_ARASAN) += sdhci-of-arasan.o +obj-$(CONFIG_MMC_SDHCI_OF_ASPEED) += sdhci-of-aspeed.o obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c new file mode 100644 index 000000000000..8962f6664381 --- /dev/null +++ b/drivers/mmc/host/sdhci-of-aspeed.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2019 ASPEED Technology Inc. */ +/* Copyright (C) 2019 IBM Corp. */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/mmc/host.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#include "sdhci-pltfm.h" + +#define ASPEED_SDC_INFO 0x00 +#define ASPEED_SDC_S1MMC8 BIT(25) +#define ASPEED_SDC_S0MMC8 BIT(24) + +struct aspeed_sdc { + struct clk *clk; + struct resource *res; + + spinlock_t lock; + void __iomem *regs; +}; + +struct aspeed_sdhci { + struct aspeed_sdc *parent; + u32 width_mask; +}; + +static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc, + struct aspeed_sdhci *sdhci, + bool bus8) +{ + u32 info; + + /* Set/clear 8 bit mode */ + spin_lock(&sdc->lock); + info = readl(sdc->regs + ASPEED_SDC_INFO); + if (bus8) + info |= sdhci->width_mask; + else + info &= ~sdhci->width_mask; + writel(info, sdc->regs + ASPEED_SDC_INFO); + spin_unlock(&sdc->lock); +} + +static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host; + unsigned long parent; + int div; + u16 clk; + + pltfm_host = sdhci_priv(host); + parent = clk_get_rate(pltfm_host->clk); + + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return; + + if (WARN_ON(clock > host->max_clk)) + clock = host->max_clk; + + for (div = 1; div < 256; div *= 2) { + if ((parent / div) <= clock) + break; + } + div >>= 1; + + clk = div << SDHCI_DIVIDER_SHIFT; + + sdhci_enable_clk(host, clk); +} + +static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host) +{ + if (host->mmc->f_max) + return host->mmc->f_max; + + return sdhci_pltfm_clk_get_max_clock(host); +} + +static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width) +{ + struct sdhci_pltfm_host *pltfm_priv; + struct aspeed_sdhci *aspeed_sdhci; + struct aspeed_sdc *aspeed_sdc; + u8 ctrl; + + pltfm_priv = sdhci_priv(host); + aspeed_sdhci = sdhci_pltfm_priv(pltfm_priv); + aspeed_sdc = aspeed_sdhci->parent; + + /* Set/clear 8-bit mode */ + aspeed_sdc_configure_8bit_mode(aspeed_sdc, aspeed_sdhci, + width == MMC_BUS_WIDTH_8); + + /* Set/clear 1 or 4 bit mode */ + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + if (width == MMC_BUS_WIDTH_4) + ctrl |= SDHCI_CTRL_4BITBUS; + else + ctrl &= ~SDHCI_CTRL_4BITBUS; + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +} + +static const struct sdhci_ops aspeed_sdhci_ops = { + .set_clock = aspeed_sdhci_set_clock, + .get_max_clock = aspeed_sdhci_get_max_clock, + .set_bus_width = aspeed_sdhci_set_bus_width, + .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + +static const struct sdhci_pltfm_data aspeed_sdhci_pdata = { + .ops = &aspeed_sdhci_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, +}; + +static inline int aspeed_sdhci_calculate_slot(struct aspeed_sdhci *dev, + struct resource *res) +{ + resource_size_t delta; + + if (!res || resource_type(res) != IORESOURCE_MEM) + return -EINVAL; + + if (res->start < dev->parent->res->start) + return -EINVAL; + + delta = res->start - dev->parent->res->start; + if (delta & (0x100 - 1)) + return -EINVAL; + + return (delta / 0x100) - 1; +} + +static int aspeed_sdhci_probe(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct aspeed_sdhci *dev; + struct sdhci_host *host; + struct resource *res; + int slot; + int ret; + + host = sdhci_pltfm_init(pdev, &aspeed_sdhci_pdata, sizeof(*dev)); + if (IS_ERR(host)) + return PTR_ERR(host); + + pltfm_host = sdhci_priv(host); + dev = sdhci_pltfm_priv(pltfm_host); + dev->parent = dev_get_drvdata(pdev->dev.parent); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + slot = aspeed_sdhci_calculate_slot(dev, res); + + if (slot < 0) + return slot; + else if (slot >= 2) + return -EINVAL; + + dev_info(&pdev->dev, "Configuring for slot %d\n", slot); + dev->width_mask = !slot ? ASPEED_SDC_S0MMC8 : ASPEED_SDC_S1MMC8; + + sdhci_get_of_property(pdev); + + pltfm_host->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pltfm_host->clk)) + return PTR_ERR(pltfm_host->clk); + + ret = clk_prepare_enable(pltfm_host->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable SDIO clock\n"); + goto err_pltfm_free; + } + + ret = mmc_of_parse(host->mmc); + if (ret) + goto err_sdhci_add; + + ret = sdhci_add_host(host); + if (ret) + goto err_sdhci_add; + + return 0; + +err_sdhci_add: + clk_disable_unprepare(pltfm_host->clk); +err_pltfm_free: + sdhci_pltfm_free(pdev); + return ret; +} + +static int aspeed_sdhci_remove(struct platform_device *pdev) +{ + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_host *host; + int dead = 0; + + host = platform_get_drvdata(pdev); + pltfm_host = sdhci_priv(host); + + sdhci_remove_host(host, dead); + + clk_disable_unprepare(pltfm_host->clk); + + sdhci_pltfm_free(pdev); + + return 0; +} + +static const struct of_device_id aspeed_sdhci_of_match[] = { + { .compatible = "aspeed,ast2400-sdhci", }, + { .compatible = "aspeed,ast2500-sdhci", }, + { .compatible = "aspeed,ast2600-sdhci", }, + { } +}; + +static struct platform_driver aspeed_sdhci_driver = { + .driver = { + .name = "sdhci-aspeed", + .of_match_table = aspeed_sdhci_of_match, + }, + .probe = aspeed_sdhci_probe, + .remove = aspeed_sdhci_remove, +}; + +static int aspeed_sdc_probe(struct platform_device *pdev) + +{ + struct device_node *parent, *child; + struct aspeed_sdc *sdc; + int ret; + + sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); + if (!sdc) + return -ENOMEM; + + spin_lock_init(&sdc->lock); + + sdc->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(sdc->clk)) + return PTR_ERR(sdc->clk); + + ret = clk_prepare_enable(sdc->clk); + if (ret) { + dev_err(&pdev->dev, "Unable to enable SDCLK\n"); + return ret; + } + + sdc->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + sdc->regs = devm_ioremap_resource(&pdev->dev, sdc->res); + if (IS_ERR(sdc->regs)) { + ret = PTR_ERR(sdc->regs); + goto err_clk; + } + + dev_set_drvdata(&pdev->dev, sdc); + + parent = pdev->dev.of_node; + for_each_available_child_of_node(parent, child) { + struct platform_device *cpdev; + + cpdev = of_platform_device_create(child, NULL, &pdev->dev); + if (!cpdev) { + of_node_put(child); + ret = -ENODEV; + goto err_clk; + } + } + + return 0; + +err_clk: + clk_disable_unprepare(sdc->clk); + return ret; +} + +static int aspeed_sdc_remove(struct platform_device *pdev) +{ + struct aspeed_sdc *sdc = dev_get_drvdata(&pdev->dev); + + clk_disable_unprepare(sdc->clk); + + return 0; +} + +static const struct of_device_id aspeed_sdc_of_match[] = { + { .compatible = "aspeed,ast2400-sd-controller", }, + { .compatible = "aspeed,ast2500-sd-controller", }, + { .compatible = "aspeed,ast2600-sd-controller", }, + { } +}; + +MODULE_DEVICE_TABLE(of, aspeed_sdc_of_match); + +static struct platform_driver aspeed_sdc_driver = { + .driver = { + .name = "sd-controller-aspeed", + .pm = &sdhci_pltfm_pmops, + .of_match_table = aspeed_sdc_of_match, + }, + .probe = aspeed_sdc_probe, + .remove = aspeed_sdc_remove, +}; + +static int __init aspeed_sdc_init(void) +{ + int rc; + + rc = platform_driver_register(&aspeed_sdhci_driver); + if (rc < 0) + return rc; + + rc = platform_driver_register(&aspeed_sdc_driver); + if (rc < 0) + platform_driver_unregister(&aspeed_sdhci_driver); + + return rc; +} +module_init(aspeed_sdc_init); + +static void __exit aspeed_sdc_exit(void) +{ + platform_driver_unregister(&aspeed_sdc_driver); + platform_driver_unregister(&aspeed_sdhci_driver); +} +module_exit(aspeed_sdc_exit); + +MODULE_DESCRIPTION("Driver for the ASPEED SD/SDIO/SDHCI Controllers"); +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>"); +MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mtd/spi-nor/aspeed-smc.c b/drivers/mtd/spi-nor/aspeed-smc.c index 19b8757325d2..ff367c70001d 100644 --- a/drivers/mtd/spi-nor/aspeed-smc.c +++ b/drivers/mtd/spi-nor/aspeed-smc.c @@ -6,6 +6,7 @@ */ #include <linux/bug.h> +#include <linux/clk.h> #include <linux/device.h> #include <linux/io.h> #include <linux/module.h> @@ -16,6 +17,7 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/sizes.h> +#include <linux/slab.h> #include <linux/sysfs.h> #define DEVICE_NAME "aspeed-smc" @@ -30,6 +32,7 @@ enum aspeed_smc_flash_type { }; struct aspeed_smc_chip; +struct aspeed_smc_controller; struct aspeed_smc_info { u32 maxsize; /* maximum size of chip window */ @@ -37,12 +40,34 @@ struct aspeed_smc_info { bool hastype; /* flash type field exists in config reg */ u8 we0; /* shift for write enable bit for CE0 */ u8 ctl0; /* offset in regs of ctl for CE0 */ + u8 timing; /* offset in regs of timing */ + u32 hclk_mask; /* clock frequency mask in CEx Control reg */ + u32 hdiv_max; /* Max HCLK divisor on read timing reg */ void (*set_4b)(struct aspeed_smc_chip *chip); + int (*optimize_read)(struct aspeed_smc_chip *chip, u32 max_freq); + int (*calibrate)(struct aspeed_smc_chip *chip, u32 hdiv, + const u8 *golden_buf, u8 *test_buf); + + u32 (*segment_start)(struct aspeed_smc_controller *controller, u32 reg); + u32 (*segment_end)(struct aspeed_smc_controller *controller, u32 reg); + u32 (*segment_reg)(struct aspeed_smc_controller *controller, + u32 start, u32 end); }; static void aspeed_smc_chip_set_4b_spi_2400(struct aspeed_smc_chip *chip); static void aspeed_smc_chip_set_4b(struct aspeed_smc_chip *chip); +static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, + u32 max_freq); +static int aspeed_smc_calibrate_reads(struct aspeed_smc_chip *chip, u32 hdiv, + const u8 *golden_buf, u8 *test_buf); + +static u32 aspeed_smc_segment_start( + struct aspeed_smc_controller *controller, u32 reg); +static u32 aspeed_smc_segment_end( + struct aspeed_smc_controller *controller, u32 reg); +static u32 aspeed_smc_segment_reg( + struct aspeed_smc_controller *controller, u32 start, u32 end); static const struct aspeed_smc_info fmc_2400_info = { .maxsize = 64 * 1024 * 1024, @@ -50,7 +75,15 @@ static const struct aspeed_smc_info fmc_2400_info = { .hastype = true, .we0 = 16, .ctl0 = 0x10, + .timing = 0x94, + .hclk_mask = 0xfffff0ff, + .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, + .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, + .segment_start = aspeed_smc_segment_start, + .segment_end = aspeed_smc_segment_end, + .segment_reg = aspeed_smc_segment_reg, }; static const struct aspeed_smc_info spi_2400_info = { @@ -59,7 +92,13 @@ static const struct aspeed_smc_info spi_2400_info = { .hastype = false, .we0 = 0, .ctl0 = 0x04, + .timing = 0x14, + .hclk_mask = 0xfffff0ff, + .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b_spi_2400, + .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, + /* No segment registers */ }; static const struct aspeed_smc_info fmc_2500_info = { @@ -68,7 +107,15 @@ static const struct aspeed_smc_info fmc_2500_info = { .hastype = true, .we0 = 16, .ctl0 = 0x10, + .timing = 0x94, + .hclk_mask = 0xfffff0ff, + .hdiv_max = 1, .set_4b = aspeed_smc_chip_set_4b, + .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, + .segment_start = aspeed_smc_segment_start, + .segment_end = aspeed_smc_segment_end, + .segment_reg = aspeed_smc_segment_reg, }; static const struct aspeed_smc_info spi_2500_info = { @@ -77,7 +124,59 @@ static const struct aspeed_smc_info spi_2500_info = { .hastype = false, .we0 = 16, .ctl0 = 0x10, + .timing = 0x94, + .hclk_mask = 0xfffff0ff, + .hdiv_max = 1, + .set_4b = aspeed_smc_chip_set_4b, + .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads, + .segment_start = aspeed_smc_segment_start, + .segment_end = aspeed_smc_segment_end, + .segment_reg = aspeed_smc_segment_reg, +}; + +static u32 aspeed_smc_segment_start_ast2600( + struct aspeed_smc_controller *controller, u32 reg); +static u32 aspeed_smc_segment_end_ast2600( + struct aspeed_smc_controller *controller, u32 reg); +static u32 aspeed_smc_segment_reg_ast2600( + struct aspeed_smc_controller *controller, u32 start, u32 end); + +static int aspeed_smc_calibrate_reads_ast2600(struct aspeed_smc_chip *chip, + u32 hdiv, const u8 *golden_buf, u8 *test_buf); + +static const struct aspeed_smc_info fmc_2600_info = { + .maxsize = 256 * 1024 * 1024, + .nce = 3, + .hastype = false, /* SPI Only */ + .we0 = 16, + .ctl0 = 0x10, + .timing = 0x94, + .hclk_mask = 0xf0fff0ff, + .hdiv_max = 2, + .set_4b = aspeed_smc_chip_set_4b, + .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads_ast2600, + .segment_start = aspeed_smc_segment_start_ast2600, + .segment_end = aspeed_smc_segment_end_ast2600, + .segment_reg = aspeed_smc_segment_reg_ast2600, +}; + +static const struct aspeed_smc_info spi_2600_info = { + .maxsize = 256 * 1024 * 1024, + .nce = 2, + .hastype = false, + .we0 = 16, + .ctl0 = 0x10, + .timing = 0x94, + .hclk_mask = 0xf0fff0ff, + .hdiv_max = 2, .set_4b = aspeed_smc_chip_set_4b, + .optimize_read = aspeed_smc_optimize_read, + .calibrate = aspeed_smc_calibrate_reads_ast2600, + .segment_start = aspeed_smc_segment_start_ast2600, + .segment_end = aspeed_smc_segment_end_ast2600, + .segment_reg = aspeed_smc_segment_reg_ast2600, }; enum aspeed_smc_ctl_reg_value { @@ -98,6 +197,7 @@ struct aspeed_smc_chip { u32 ctl_val[smc_max]; /* control settings */ enum aspeed_smc_flash_type type; /* what type of flash */ struct spi_nor nor; + u32 clk_rate; }; struct aspeed_smc_controller { @@ -106,12 +206,17 @@ struct aspeed_smc_controller { struct mutex mutex; /* controller access mutex */ const struct aspeed_smc_info *info; /* type info of controller */ void __iomem *regs; /* controller registers */ - void __iomem *ahb_base; /* per-chip windows resource */ + void __iomem *ahb_base; /* per-chip window resource */ + u32 ahb_base_phy; /* phys addr of AHB window */ u32 ahb_window_size; /* full mapping window size */ + unsigned long clk_frequency; + struct aspeed_smc_chip *chips[0]; /* pointers to attached chips */ }; +#define ASPEED_SPI_DEFAULT_FREQ 50000000 + /* * SPI Flash Configuration Register (AST2500 SPI) * or @@ -181,23 +286,82 @@ struct aspeed_smc_controller { (CONTROL_AAF_MODE | CONTROL_CE_INACTIVE_MASK | CONTROL_CLK_DIV4 | \ CONTROL_CLOCK_FREQ_SEL_MASK | CONTROL_LSB_FIRST | CONTROL_CLOCK_MODE_3) -/* - * The Segment Register uses a 8MB unit to encode the start address - * and the end address of the mapping window of a flash SPI slave : - * - * | byte 1 | byte 2 | byte 3 | byte 4 | - * +--------+--------+--------+--------+ - * | end | start | 0 | 0 | - */ #define SEGMENT_ADDR_REG0 0x30 -#define SEGMENT_ADDR_START(_r) ((((_r) >> 16) & 0xFF) << 23) -#define SEGMENT_ADDR_END(_r) ((((_r) >> 24) & 0xFF) << 23) -#define SEGMENT_ADDR_VALUE(start, end) \ - (((((start) >> 23) & 0xFF) << 16) | ((((end) >> 23) & 0xFF) << 24)) #define SEGMENT_ADDR_REG(controller, cs) \ ((controller)->regs + SEGMENT_ADDR_REG0 + (cs) * 4) /* + * The Segment Registers of the AST2400 and AST2500 have a 8MB + * unit. The address range of a flash SPI slave is encoded with + * absolute addresses which should be part of the overall controller + * window. + */ +static u32 aspeed_smc_segment_start( + struct aspeed_smc_controller *controller, u32 reg) +{ + return ((reg >> 16) & 0xFF) << 23; +} + +static u32 aspeed_smc_segment_end( + struct aspeed_smc_controller *controller, u32 reg) +{ + return ((reg >> 24) & 0xFF) << 23; +} + +static u32 aspeed_smc_segment_reg( + struct aspeed_smc_controller *controller, u32 start, u32 end) +{ + return (((start >> 23) & 0xFF) << 16) | (((end >> 23) & 0xFF) << 24); +} + +/* + * The Segment Registers of the AST2600 have a 1MB unit. The address + * range of a flash SPI slave is encoded with offsets in the overall + * controller window. The previous SoC AST2400 and AST2500 used + * absolute addresses. Only bits [27:20] are relevant and the end + * address is an upper bound limit. + */ + +#define AST2600_SEG_ADDR_MASK 0x0ff00000 + +static u32 aspeed_smc_segment_start_ast2600( + struct aspeed_smc_controller *controller, u32 reg) +{ + uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; + + return controller->ahb_base_phy + start_offset; +} + +static u32 aspeed_smc_segment_end_ast2600( + struct aspeed_smc_controller *controller, u32 reg) +{ + uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; + + /* segment is disabled */ + if (!end_offset) + return controller->ahb_base_phy; + + return controller->ahb_base_phy + end_offset + 0x100000; +} + +static u32 aspeed_smc_segment_reg_ast2600( + struct aspeed_smc_controller *controller, u32 start, u32 end) +{ + /* disable zero size segments */ + if (start == end) + return 0; + + return ((start & AST2600_SEG_ADDR_MASK) >> 16) | + ((end - 1) & AST2600_SEG_ADDR_MASK); +} + +/* + * Switch to turn off read optimisation if needed + */ +static bool optimize_read = true; +module_param(optimize_read, bool, 0644); + +/* * In user mode all data bytes read or written to the chip decode address * range are transferred to or from the SPI bus. The range is treated as a * fifo of arbitratry 1, 2, or 4 byte width but each write has to be aligned @@ -369,18 +533,49 @@ static void aspeed_smc_send_cmd_addr(struct spi_nor *nor, u8 cmd, u32 addr) } } +static int aspeed_smc_get_io_mode(struct aspeed_smc_chip *chip) +{ + switch (chip->nor.read_proto) { + case SNOR_PROTO_1_1_1: + return 0; + case SNOR_PROTO_1_1_2: + return CONTROL_IO_DUAL_DATA; + case SNOR_PROTO_1_2_2: + return CONTROL_IO_DUAL_ADDR_DATA; + default: + dev_err(chip->nor.dev, "unsupported SPI read mode\n"); + return -EINVAL; + } +} + +static void aspeed_smc_set_io_mode(struct aspeed_smc_chip *chip, u32 io_mode) +{ + u32 ctl; + + if (io_mode > 0) { + ctl = readl(chip->ctl) & ~CONTROL_IO_MODE_MASK; + ctl |= io_mode; + writel(ctl, chip->ctl); + } +} + static ssize_t aspeed_smc_read_user(struct spi_nor *nor, loff_t from, size_t len, u_char *read_buf) { struct aspeed_smc_chip *chip = nor->priv; int i; u8 dummy = 0xFF; + int io_mode = aspeed_smc_get_io_mode(chip); aspeed_smc_start_user(nor); aspeed_smc_send_cmd_addr(nor, nor->read_opcode, from); for (i = 0; i < chip->nor.read_dummy / 8; i++) aspeed_smc_write_to_ahb(chip->ahb_base, &dummy, sizeof(dummy)); + /* Set IO mode only for data */ + if (io_mode == CONTROL_IO_DUAL_DATA) + aspeed_smc_set_io_mode(chip, io_mode); + aspeed_smc_read_from_ahb(read_buf, chip->ahb_base, len); aspeed_smc_stop_user(nor); return len; @@ -398,6 +593,31 @@ static ssize_t aspeed_smc_write_user(struct spi_nor *nor, loff_t to, return len; } +static ssize_t aspeed_smc_read(struct spi_nor *nor, loff_t from, size_t len, + u_char *read_buf) +{ + struct aspeed_smc_chip *chip = nor->priv; + + /* + * The AHB window configured for the chip is too small for the + * read offset. Use the "User mode" of the controller to + * perform the read. + */ + if (from >= chip->ahb_window_size) { + aspeed_smc_read_user(nor, from, len, read_buf); + goto out; + } + + /* + * Use the "Command mode" to do a direct read from the AHB + * window configured for the chip. This should be the default. + */ + memcpy_fromio(read_buf, chip->ahb_base + from, len); + +out: + return len; +} + static int aspeed_smc_unregister(struct aspeed_smc_controller *controller) { struct aspeed_smc_chip *chip; @@ -422,6 +642,8 @@ static const struct of_device_id aspeed_smc_matches[] = { { .compatible = "aspeed,ast2400-spi", .data = &spi_2400_info }, { .compatible = "aspeed,ast2500-fmc", .data = &fmc_2500_info }, { .compatible = "aspeed,ast2500-spi", .data = &spi_2500_info }, + { .compatible = "aspeed,ast2600-fmc", .data = &fmc_2600_info }, + { .compatible = "aspeed,ast2600-spi", .data = &spi_2600_info }, { } }; MODULE_DEVICE_TABLE(of, aspeed_smc_matches); @@ -437,36 +659,32 @@ static void __iomem *aspeed_smc_chip_base(struct aspeed_smc_chip *chip, struct resource *res) { struct aspeed_smc_controller *controller = chip->controller; + const struct aspeed_smc_info *info = controller->info; u32 offset = 0; u32 reg; - if (controller->info->nce > 1) { + if (info->nce > 1) { reg = readl(SEGMENT_ADDR_REG(controller, chip->cs)); - if (SEGMENT_ADDR_START(reg) >= SEGMENT_ADDR_END(reg)) + if (info->segment_start(controller, reg) >= + info->segment_end(controller, reg)) { return NULL; + } - offset = SEGMENT_ADDR_START(reg) - res->start; + offset = info->segment_start(controller, reg) - res->start; } return controller->ahb_base + offset; } -static u32 aspeed_smc_ahb_base_phy(struct aspeed_smc_controller *controller) -{ - u32 seg0_val = readl(SEGMENT_ADDR_REG(controller, 0)); - - return SEGMENT_ADDR_START(seg0_val); -} - static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, u32 size) { struct aspeed_smc_controller *controller = chip->controller; + const struct aspeed_smc_info *info = controller->info; void __iomem *seg_reg; - u32 seg_oldval, seg_newval, ahb_base_phy, end; - - ahb_base_phy = aspeed_smc_ahb_base_phy(controller); + u32 seg_oldval, seg_newval, end; + u32 ahb_base_phy = controller->ahb_base_phy; seg_reg = SEGMENT_ADDR_REG(controller, cs); seg_oldval = readl(seg_reg); @@ -476,8 +694,15 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, * size, but take into account the possible overlap with the * previous segment */ - if (!size) - size = SEGMENT_ADDR_END(seg_oldval) - start; + if (!size) { + end = info->segment_end(controller, seg_oldval); + + /* + * Check for disabled segment (AST2600). + */ + if (end != ahb_base_phy) + size = end - start; + } /* * The segment cannot exceed the maximum window size of the @@ -490,7 +715,7 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, } end = start + size; - seg_newval = SEGMENT_ADDR_VALUE(start, end); + seg_newval = info->segment_reg(controller, start, end); writel(seg_newval, seg_reg); /* @@ -501,13 +726,13 @@ static u32 chip_set_segment(struct aspeed_smc_chip *chip, u32 cs, u32 start, if (seg_newval != readl(seg_reg)) { dev_err(chip->nor.dev, "CE%d window invalid", cs); writel(seg_oldval, seg_reg); - start = SEGMENT_ADDR_START(seg_oldval); - end = SEGMENT_ADDR_END(seg_oldval); + start = info->segment_start(controller, seg_oldval); + end = info->segment_end(controller, seg_oldval); size = end - start; } - dev_info(chip->nor.dev, "CE%d window [ 0x%.8x - 0x%.8x ] %dMB", - cs, start, end, size >> 20); + dev_info(chip->nor.dev, "CE%d window [ 0x%.8x - 0x%.8x ] %dMB%s", + cs, start, end, size >> 20, size ? "" : " (disabled)"); return size; } @@ -555,7 +780,7 @@ static u32 aspeed_smc_chip_set_segment(struct aspeed_smc_chip *chip) chip->cs, size >> 20); } - ahb_base_phy = aspeed_smc_ahb_base_phy(controller); + ahb_base_phy = controller->ahb_base_phy; /* * As a start address for the current segment, use the default @@ -565,7 +790,7 @@ static u32 aspeed_smc_chip_set_segment(struct aspeed_smc_chip *chip) if (chip->cs) { u32 prev = readl(SEGMENT_ADDR_REG(controller, chip->cs - 1)); - start = SEGMENT_ADDR_END(prev); + start = controller->info->segment_end(controller, prev); } else { start = ahb_base_phy; } @@ -702,10 +927,258 @@ static int aspeed_smc_chip_setup_init(struct aspeed_smc_chip *chip, return 0; } + +#define CALIBRATE_BUF_SIZE 16384 + +static bool aspeed_smc_check_reads(struct aspeed_smc_chip *chip, + const u8 *golden_buf, u8 *test_buf) +{ + int i; + + for (i = 0; i < 10; i++) { + memcpy_fromio(test_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); + if (memcmp(test_buf, golden_buf, CALIBRATE_BUF_SIZE) != 0) + return false; + } + return true; +} + +static int aspeed_smc_calibrate_reads(struct aspeed_smc_chip *chip, u32 hdiv, + const u8 *golden_buf, u8 *test_buf) +{ + struct aspeed_smc_controller *controller = chip->controller; + const struct aspeed_smc_info *info = controller->info; + int i; + int good_pass = -1, pass_count = 0; + u32 shift = (hdiv - 1) << 2; + u32 mask = ~(0xfu << shift); + u32 fread_timing_val = 0; + +#define FREAD_TPASS(i) (((i) / 2) | (((i) & 1) ? 0 : 8)) + + /* Try HCLK delay 0..5, each one with/without delay and look for a + * good pair. + */ + for (i = 0; i < 12; i++) { + bool pass; + + fread_timing_val &= mask; + fread_timing_val |= FREAD_TPASS(i) << shift; + + writel(fread_timing_val, controller->regs + info->timing); + pass = aspeed_smc_check_reads(chip, golden_buf, test_buf); + dev_dbg(chip->nor.dev, + " * [%08x] %d HCLK delay, %dns DI delay : %s", + fread_timing_val, i/2, (i & 1) ? 0 : 4, + pass ? "PASS" : "FAIL"); + if (pass) { + pass_count++; + if (pass_count == 3) { + good_pass = i - 1; + break; + } + } else + pass_count = 0; + } + + /* No good setting for this frequency */ + if (good_pass < 0) + return -1; + + /* We have at least one pass of margin, let's use first pass */ + fread_timing_val &= mask; + fread_timing_val |= FREAD_TPASS(good_pass) << shift; + writel(fread_timing_val, controller->regs + info->timing); + dev_dbg(chip->nor.dev, " * -> good is pass %d [0x%08x]", + good_pass, fread_timing_val); + return 0; +} + +static bool aspeed_smc_check_calib_data(const u8 *test_buf, u32 size) +{ + const u32 *tb32 = (const u32 *) test_buf; + u32 i, cnt = 0; + + /* We check if we have enough words that are neither all 0 + * nor all 1's so the calibration can be considered valid. + * + * I use an arbitrary threshold for now of 64 + */ + size >>= 2; + for (i = 0; i < size; i++) { + if (tb32[i] != 0 && tb32[i] != 0xffffffff) + cnt++; + } + return cnt >= 64; +} + +static const uint32_t aspeed_smc_hclk_divs[] = { + 0xf, /* HCLK */ + 0x7, /* HCLK/2 */ + 0xe, /* HCLK/3 */ + 0x6, /* HCLK/4 */ + 0xd, /* HCLK/5 */ +}; +#define ASPEED_SMC_HCLK_DIV(i) \ + (aspeed_smc_hclk_divs[(i) - 1] << CONTROL_CLOCK_FREQ_SEL_SHIFT) + +static u32 aspeed_smc_default_read(struct aspeed_smc_chip *chip) +{ + /* + * Keep the 4Byte address mode on the AST2400 SPI controller. + * Other controllers set the 4Byte mode in the CE Control + * Register + */ + u32 ctl_mask = chip->controller->info == &spi_2400_info ? + CONTROL_IO_ADDRESS_4B : 0; + u8 cmd = chip->nor.flags & SNOR_F_4B_OPCODES ? SPINOR_OP_READ_4B : + SPINOR_OP_READ; + + /* + * Use the "read command" mode to customize the opcode. In + * normal command mode, the value is necessarily READ (0x3) on + * the AST2400/2500 SoCs. + */ + return (chip->ctl_val[smc_read] & ctl_mask) | + (0x00 << 28) | /* Single bit */ + (0x00 << 24) | /* CE# max */ + (cmd << 16) | /* use read mode to support 4B opcode */ + (0x00 << 8) | /* HCLK/16 */ + (0x00 << 6) | /* no dummy cycle */ + (0x01); /* read mode */ +} + +static int aspeed_smc_optimize_read(struct aspeed_smc_chip *chip, + u32 max_freq) +{ + struct aspeed_smc_controller *controller = chip->controller; + const struct aspeed_smc_info *info = controller->info; + u8 *golden_buf, *test_buf; + int i, rc, best_div = -1; + u32 save_read_val = chip->ctl_val[smc_read]; + u32 ahb_freq = chip->controller->clk_frequency; + + dev_dbg(chip->nor.dev, "AHB frequency: %d MHz", ahb_freq / 1000000); + + test_buf = kmalloc(CALIBRATE_BUF_SIZE * 2, GFP_KERNEL); + golden_buf = test_buf + CALIBRATE_BUF_SIZE; + + /* We start with the dumbest setting (keep 4Byte bit) and read + * some data + */ + chip->ctl_val[smc_read] = aspeed_smc_default_read(chip); + + writel(chip->ctl_val[smc_read], chip->ctl); + + memcpy_fromio(golden_buf, chip->ahb_base, CALIBRATE_BUF_SIZE); + + /* Establish our read mode with freq field set to 0 (HCLK/16) */ + chip->ctl_val[smc_read] = save_read_val & info->hclk_mask; + + /* Check if calibration data is suitable */ + if (!aspeed_smc_check_calib_data(golden_buf, CALIBRATE_BUF_SIZE)) { + dev_info(chip->nor.dev, + "Calibration area too uniform, using low speed"); + writel(chip->ctl_val[smc_read], chip->ctl); + kfree(test_buf); + return 0; + } + + /* Now we iterate the HCLK dividers until we find our breaking point */ + for (i = ARRAY_SIZE(aspeed_smc_hclk_divs); i > info->hdiv_max - 1; i--) { + u32 tv, freq; + + /* Compare timing to max */ + freq = ahb_freq / i; + if (freq > max_freq) + continue; + + /* Set the timing */ + tv = chip->ctl_val[smc_read] | ASPEED_SMC_HCLK_DIV(i); + writel(tv, chip->ctl); + dev_dbg(chip->nor.dev, "Trying HCLK/%d [%08x] ...", i, tv); + rc = info->calibrate(chip, i, golden_buf, test_buf); + if (rc == 0) + best_div = i; + } + kfree(test_buf); + + /* Nothing found ? */ + if (best_div < 0) + dev_warn(chip->nor.dev, "No good frequency, using dumb slow"); + else { + dev_dbg(chip->nor.dev, "Found good read timings at HCLK/%d", + best_div); + chip->ctl_val[smc_read] |= ASPEED_SMC_HCLK_DIV(best_div); + } + + writel(chip->ctl_val[smc_read], chip->ctl); + return 0; +} + +#define TIMING_DELAY_DI BIT(3) +#define TIMING_DELAY_HCYCLE_MAX 5 +#define TIMING_REG_AST2600(chip) \ + ((chip)->controller->regs + (chip)->controller->info->timing + \ + (chip)->cs * 4) + +static int aspeed_smc_calibrate_reads_ast2600(struct aspeed_smc_chip *chip, u32 hdiv, + const u8 *golden_buf, u8 *test_buf) +{ + int hcycle; + u32 shift = (hdiv - 2) << 3; + u32 mask = ~(0xfu << shift); + u32 fread_timing_val = 0; + + for (hcycle = 0; hcycle <= TIMING_DELAY_HCYCLE_MAX; hcycle++) { + int delay_ns; + bool pass = false; + + fread_timing_val &= mask; + fread_timing_val |= hcycle << shift; + + /* no DI input delay first */ + writel(fread_timing_val, TIMING_REG_AST2600(chip)); + pass = aspeed_smc_check_reads(chip, golden_buf, test_buf); + dev_dbg(chip->nor.dev, + " * [%08x] %d HCLK delay, DI delay none : %s", + fread_timing_val, hcycle, pass ? "PASS" : "FAIL"); + if (pass) + return 0; + + /* Add DI input delays */ + fread_timing_val &= mask; + fread_timing_val |= (TIMING_DELAY_DI | hcycle) << shift; + + for (delay_ns = 0; delay_ns < 0x10; delay_ns++) { + fread_timing_val &= ~(0xf << (4 + shift)); + fread_timing_val |= delay_ns << (4 + shift); + + writel(fread_timing_val, TIMING_REG_AST2600(chip)); + pass = aspeed_smc_check_reads(chip, golden_buf, test_buf); + dev_dbg(chip->nor.dev, + " * [%08x] %d HCLK delay, DI delay %d.%dns : %s", + fread_timing_val, hcycle, (delay_ns + 1)/2, + (delay_ns + 1) & 1 ? 5 : 5, pass ? "PASS" : "FAIL"); + /* + * TODO: This is optimistic. We should look + * for a working interval and save the middle + * value in the read timing register. + */ + if (pass) + return 0; + } + } + + /* No good setting for this frequency */ + return -1; +} + static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip) { struct aspeed_smc_controller *controller = chip->controller; const struct aspeed_smc_info *info = controller->info; + int io_mode; u32 cmd; if (chip->nor.addr_width == 4 && info->set_4b) @@ -728,21 +1201,24 @@ static int aspeed_smc_chip_setup_finish(struct aspeed_smc_chip *chip) * TODO: Adjust clocks if fast read is supported and interpret * SPI-NOR flags to adjust controller settings. */ - if (chip->nor.read_proto == SNOR_PROTO_1_1_1) { - if (chip->nor.read_dummy == 0) - cmd = CONTROL_COMMAND_MODE_NORMAL; - else - cmd = CONTROL_COMMAND_MODE_FREAD; - } else { - dev_err(chip->nor.dev, "unsupported SPI read mode\n"); - return -EINVAL; - } + io_mode = aspeed_smc_get_io_mode(chip); + if (io_mode < 0) + return io_mode; + + if (chip->nor.read_dummy == 0) + cmd = CONTROL_COMMAND_MODE_NORMAL; + else + cmd = CONTROL_COMMAND_MODE_FREAD; - chip->ctl_val[smc_read] |= cmd | + chip->ctl_val[smc_read] |= cmd | io_mode | + chip->nor.read_opcode << CONTROL_COMMAND_SHIFT | CONTROL_IO_DUMMY_SET(chip->nor.read_dummy / 8); - dev_dbg(controller->dev, "base control register: %08x\n", + dev_info(controller->dev, "read control register: %08x\n", chip->ctl_val[smc_read]); + + if (optimize_read && info->optimize_read) + info->optimize_read(chip, chip->clk_rate); return 0; } @@ -752,6 +1228,7 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller, const struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST | + SNOR_HWCAPS_READ_1_1_2 | SNOR_HWCAPS_PP, }; const struct aspeed_smc_info *info = controller->info; @@ -795,6 +1272,13 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller, break; } + if (of_property_read_u32(child, "spi-max-frequency", + &chip->clk_rate)) { + chip->clk_rate = ASPEED_SPI_DEFAULT_FREQ; + } + dev_info(dev, "Using %d MHz SPI frequency\n", + chip->clk_rate / 1000000); + chip->controller = controller; chip->ctl = controller->regs + info->ctl0 + cs * 4; chip->cs = cs; @@ -805,7 +1289,7 @@ static int aspeed_smc_setup_flash(struct aspeed_smc_controller *controller, nor->dev = dev; nor->priv = chip; spi_nor_set_flash_node(nor, child); - nor->read = aspeed_smc_read_user; + nor->read = aspeed_smc_read; nor->write = aspeed_smc_write_user; nor->read_reg = aspeed_smc_read_reg; nor->write_reg = aspeed_smc_write_reg; @@ -849,6 +1333,7 @@ static int aspeed_smc_probe(struct platform_device *pdev) struct aspeed_smc_controller *controller; const struct of_device_id *match; const struct aspeed_smc_info *info; + struct clk *clk; struct resource *res; int ret; @@ -874,12 +1359,19 @@ static int aspeed_smc_probe(struct platform_device *pdev) return PTR_ERR(controller->regs); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + controller->ahb_base_phy = res->start; controller->ahb_base = devm_ioremap_resource(dev, res); if (IS_ERR(controller->ahb_base)) return PTR_ERR(controller->ahb_base); controller->ahb_window_size = resource_size(res); + clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + controller->clk_frequency = clk_get_rate(clk); + devm_clk_put(&pdev->dev, clk); + ret = aspeed_smc_setup_flash(controller, np, res); if (ret) dev_err(dev, "Aspeed SMC probe failed %d\n", ret); diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 654bdc41fc99..ff6b719fd267 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1973,7 +1973,7 @@ static const struct flash_info spi_nor_ids[] = { { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, - { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { "mx66l51235f", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) }, @@ -2151,6 +2151,8 @@ static const struct flash_info spi_nor_ids[] = { { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) }, { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { "w25q512jv", INFO(0xef4020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, { "w25m512jv", INFO(0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ) }, diff --git a/drivers/net/ethernet/faraday/Kconfig b/drivers/net/ethernet/faraday/Kconfig index a9b105803fb7..73e4f2648e49 100644 --- a/drivers/net/ethernet/faraday/Kconfig +++ b/drivers/net/ethernet/faraday/Kconfig @@ -32,6 +32,7 @@ config FTGMAC100 depends on ARM || NDS32 || COMPILE_TEST depends on !64BIT || BROKEN select PHYLIB + select MDIO_ASPEED if MACH_ASPEED_G6 ---help--- This driver supports the FTGMAC100 Gigabit Ethernet controller from Faraday. It is used on Faraday A369, Andes AG102 and some diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/ethernet/faraday/ftgmac100.c index 713dc30f9dbb..2e5fba354412 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -17,6 +17,7 @@ #include <linux/module.h> #include <linux/netdevice.h> #include <linux/of.h> +#include <linux/of_mdio.h> #include <linux/phy.h> #include <linux/platform_device.h> #include <linux/property.h> @@ -89,6 +90,9 @@ struct ftgmac100 { struct mii_bus *mii_bus; struct clk *clk; + /* 2600 RMII clock gate */ + struct clk *rclk; + /* Link management */ int cur_speed; int cur_duplex; @@ -773,7 +777,7 @@ static netdev_tx_t ftgmac100_hard_start_xmit(struct sk_buff *skb, for (i = 0; i < nfrags; i++) { skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; - len = frag->size; + len = skb_frag_size(frag); /* Map it */ map = skb_frag_dma_map(priv->dev, frag, 0, len, @@ -1618,8 +1622,13 @@ static int ftgmac100_setup_mdio(struct net_device *netdev) if (!priv->mii_bus) return -EIO; - if (priv->is_aspeed) { - /* This driver supports the old MDIO interface */ + if (of_device_is_compatible(np, "aspeed,ast2400-mac") || + of_device_is_compatible(np, "aspeed,ast2500-mac")) { + /* The AST2600 has a separate MDIO controller */ + + /* For the AST2400 and AST2500 this driver only supports the + * old MDIO interface + */ reg = ioread32(priv->base + FTGMAC100_OFFSET_REVR); reg &= ~FTGMAC100_REVR_NEW_MDIO_INTERFACE; iowrite32(reg, priv->base + FTGMAC100_OFFSET_REVR); @@ -1711,12 +1720,14 @@ static void ftgmac100_ncsi_handler(struct ncsi_dev *nd) nd->link_up ? "up" : "down"); } -static void ftgmac100_setup_clk(struct ftgmac100 *priv) +static int ftgmac100_setup_clk(struct ftgmac100 *priv) { - priv->clk = devm_clk_get(priv->dev, NULL); - if (IS_ERR(priv->clk)) - return; + struct clk *clk; + clk = devm_clk_get(priv->dev, NULL /* MACCLK */); + if (IS_ERR(clk)) + return PTR_ERR(clk); + priv->clk = clk; clk_prepare_enable(priv->clk); /* Aspeed specifies a 100MHz clock is required for up to @@ -1725,6 +1736,14 @@ static void ftgmac100_setup_clk(struct ftgmac100 *priv) */ clk_set_rate(priv->clk, priv->use_ncsi ? FTGMAC_25MHZ : FTGMAC_100MHZ); + + /* RCLK is for RMII, typically used for NCSI. Optional because its not + * necessary if it's the 2400 MAC or the MAC is configured for RGMII + */ + priv->rclk = devm_clk_get_optional(priv->dev, "RCLK"); + clk_prepare_enable(priv->rclk); + + return 0; } static int ftgmac100_probe(struct platform_device *pdev) @@ -1796,7 +1815,8 @@ static int ftgmac100_probe(struct platform_device *pdev) np = pdev->dev.of_node; if (np && (of_device_is_compatible(np, "aspeed,ast2400-mac") || - of_device_is_compatible(np, "aspeed,ast2500-mac"))) { + of_device_is_compatible(np, "aspeed,ast2500-mac") || + of_device_is_compatible(np, "aspeed,ast2600-mac"))) { priv->rxdes0_edorr_mask = BIT(30); priv->txdes0_edotr_mask = BIT(30); priv->is_aspeed = true; @@ -1816,15 +1836,40 @@ static int ftgmac100_probe(struct platform_device *pdev) priv->ndev = ncsi_register_dev(netdev, ftgmac100_ncsi_handler); if (!priv->ndev) goto err_ncsi_dev; - } else { + } else if (np && of_get_property(np, "phy-handle", NULL)) { + struct phy_device *phy; + + phy = of_phy_get_and_connect(priv->netdev, np, + &ftgmac100_adjust_link); + if (!phy) { + dev_err(&pdev->dev, "Failed to connect to phy\n"); + goto err_setup_mdio; + } + + /* Indicate that we support PAUSE frames (see comment in + * Documentation/networking/phy.txt) + */ + phy_support_asym_pause(phy); + + /* Display what we found */ + phy_attached_info(phy); + } else if (np && !of_get_child_by_name(np, "mdio")) { + /* Support legacy ASPEED devicetree descriptions that decribe a + * MAC with an embedded MDIO controller but have no "mdio" + * child node. Automatically scan the MDIO bus for available + * PHYs. + */ priv->use_ncsi = false; err = ftgmac100_setup_mdio(netdev); if (err) goto err_setup_mdio; } - if (priv->is_aspeed) - ftgmac100_setup_clk(priv); + if (priv->is_aspeed) { + err = ftgmac100_setup_clk(priv); + if (err) + goto err_ncsi_dev; + } /* Default ring sizes */ priv->rx_q_entries = priv->new_rx_q_entries = DEF_RX_QUEUE_ENTRIES; @@ -1856,8 +1901,11 @@ static int ftgmac100_probe(struct platform_device *pdev) return 0; -err_ncsi_dev: err_register_netdev: + if (priv->rclk) + clk_disable_unprepare(priv->rclk); + clk_disable_unprepare(priv->clk); +err_ncsi_dev: ftgmac100_destroy_mdio(netdev); err_setup_mdio: iounmap(priv->base); @@ -1879,6 +1927,8 @@ static int ftgmac100_remove(struct platform_device *pdev) unregister_netdev(netdev); + if (priv->rclk) + clk_disable_unprepare(priv->rclk); clk_disable_unprepare(priv->clk); /* There's a small chance the reset task will have been re-queued, diff --git a/drivers/net/ethernet/nuvoton/Kconfig b/drivers/net/ethernet/nuvoton/Kconfig index 325e26c549f8..4408ad500a75 100644 --- a/drivers/net/ethernet/nuvoton/Kconfig +++ b/drivers/net/ethernet/nuvoton/Kconfig @@ -6,7 +6,7 @@ config NET_VENDOR_NUVOTON bool "Nuvoton devices" default y - depends on ARM && ARCH_W90X900 + depends on ARM && (ARCH_W90X900 || ARCH_NPCM7XX) ---help--- If you have a network (Ethernet) card belonging to this class, say Y. @@ -26,4 +26,19 @@ config W90P910_ETH Say Y here if you want to use built-in Ethernet ports on w90p910 processor. +config NPCM7XX_EMC_ETH + bool "Nuvoton NPCM7XX Ethernet EMC" + depends on ARM && ARCH_NPCM7XX + select PHYLIB + select MII + help + Say Y here if you want to use built-in Ethernet MAC + on NPCM750 MCU. + +config NPCM7XX_EMC_ETH_DEBUG + bool "Nuvoton NPCM7XX Ethernet EMC debug" + depends on NPCM7XX_EMC_ETH + help + Say Y here if you want debug info via /proc/driver/npcm7xx_emc.x + endif # NET_VENDOR_NUVOTON diff --git a/drivers/net/ethernet/nuvoton/Makefile b/drivers/net/ethernet/nuvoton/Makefile index 66f6e728d54b..e32be694e987 100644 --- a/drivers/net/ethernet/nuvoton/Makefile +++ b/drivers/net/ethernet/nuvoton/Makefile @@ -3,4 +3,6 @@ # Makefile for the Nuvoton network device drivers. # +#Eternet 10/100 EMC obj-$(CONFIG_W90P910_ETH) += w90p910_ether.o +obj-$(CONFIG_NPCM7XX_EMC_ETH) += npcm7xx_emc.o diff --git a/drivers/net/ethernet/nuvoton/npcm7xx_emc.c b/drivers/net/ethernet/nuvoton/npcm7xx_emc.c new file mode 100644 index 000000000000..efb441d511c5 --- /dev/null +++ b/drivers/net/ethernet/nuvoton/npcm7xx_emc.c @@ -0,0 +1,2091 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2014-2019 Nuvoton Technology corporation. + +#ifdef CONFIG_NPCM7XX_EMC_ETH_DEBUG +#define DEBUG +#endif + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/mii.h> +#include <linux/phy.h> +#include <linux/netdevice.h> +#include <linux/etherdevice.h> +#include <linux/skbuff.h> +#include <linux/ethtool.h> +#include <linux/platform_device.h> +#include <linux/gfp.h> +#include <linux/kthread.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/ctype.h> +#include <linux/debugfs.h> + +#include <linux/clk.h> + +#include <linux/of.h> +#include <linux/of_net.h> +#include <linux/of_device.h> +#include <linux/dma-mapping.h> + +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> + +#include <linux/if_ether.h> + +#include <net/ip.h> +#include <net/ncsi.h> + +#ifdef CONFIG_DEBUG_FS +static struct dentry *npcm7xx_fs_dir; +#endif + +#define MFSEL1_OFFSET 0x00C +#define MFSEL3_OFFSET 0x064 +#define INTCR_OFFSET 0x03C + +#define IPSRST1_OFFSET 0x020 + +#define DRV_MODULE_NAME "npcm7xx-emc" +#define DRV_MODULE_VERSION "3.90" + +/* Ethernet MAC Registers */ +#define REG_CAMCMR 0x00 +#define REG_CAMEN 0x04 +#define REG_CAMM_BASE 0x08 +#define REG_CAML_BASE 0x0c +#define REG_TXDLSA 0x88 +#define REG_RXDLSA 0x8C +#define REG_MCMDR 0x90 +#define REG_MIID 0x94 +#define REG_MIIDA 0x98 +#define REG_FFTCR 0x9C +#define REG_TSDR 0xa0 +#define REG_RSDR 0xa4 +#define REG_DMARFC 0xa8 +#define REG_MIEN 0xac +#define REG_MISTA 0xb0 +#define REG_MGSTA 0xb4 +#define REG_MPCNT 0xb8 +#define REG_MRPC 0xbc +#define REG_MRPCC 0xc0 +#define REG_MREPC 0xc4 +#define REG_DMARFS 0xc8 +#define REG_CTXDSA 0xcc +#define REG_CTXBSA 0xd0 +#define REG_CRXDSA 0xd4 +#define REG_CRXBSA 0xd8 + +/* EMC Diagnostic Registers */ +#define REG_RXFSM 0x200 +#define REG_TXFSM 0x204 +#define REG_FSM0 0x208 +#define REG_FSM1 0x20c +#define REG_DCR 0x210 +#define REG_DMMIR 0x214 +#define REG_BISTR 0x300 + +/* mac controller bit */ +#define MCMDR_RXON BIT(0) +#define MCMDR_ALP BIT(1) +#define MCMDR_ACP BIT(3) +#define MCMDR_SPCRC BIT(5) +#define MCMDR_TXON BIT(8) +#define MCMDR_NDEF BIT(9) +#define MCMDR_FDUP BIT(18) +#define MCMDR_ENMDC BIT(19) +#define MCMDR_OPMOD BIT(20) +#define SWR BIT(24) + +/* cam command regiser */ +#define CAMCMR_AUP BIT(0) +#define CAMCMR_AMP BIT(1) +#define CAMCMR_ABP BIT(2) +#define CAMCMR_CCAM BIT(3) +#define CAMCMR_ECMP BIT(4) + +/* cam enable regiser */ +#define CAM0EN BIT(0) + +/* mac mii controller bit */ +#define PHYAD BIT(8) +#define PHYWR BIT(16) +#define PHYBUSY BIT(17) +#define PHYPRESP BIT(18) +#define MDCON BIT(19) +#define CAM_ENTRY_SIZE 0x08 + +/* rx and tx status */ +#define TXDS_TXCP BIT(19) +#define RXDS_CRCE BIT(17) +#define RXDS_PTLE BIT(19) +#define RXDS_RXGD BIT(20) +#define RXDS_ALIE BIT(21) +#define RXDS_RP BIT(22) + +/* mac interrupt status*/ +#define MISTA_RXINTR BIT(0) +#define MISTA_CRCE BIT(1) +#define MISTA_RXOV BIT(2) +#define MISTA_PTLE BIT(3) +#define MISTA_RXGD BIT(4) +#define MISTA_ALIE BIT(5) +#define MISTA_RP BIT(6) +#define MISTA_MMP BIT(7) +#define MISTA_DFOI BIT(8) +#define MISTA_DENI BIT(9) +#define MISTA_RDU BIT(10) +#define MISTA_RXBERR BIT(11) +#define MISTA_CFR BIT(14) +#define MISTA_TXINTR BIT(16) +#define MISTA_TXEMP BIT(17) +#define MISTA_TXCP BIT(18) +#define MISTA_EXDEF BIT(19) +#define MISTA_NCS BIT(20) +#define MISTA_TXABT BIT(21) +#define MISTA_LC BIT(22) +#define MISTA_TDU BIT(23) +#define MISTA_TXBERR BIT(24) + +/* Transmit/Receive Start Demand Register */ +#define ENSTART BIT(0) + +#define ENRXINTR BIT(0) +#define ENCRCE BIT(1) +#define EMRXOV BIT(2) +#define ENPTLE BIT(3) +#define ENRXGD BIT(4) +#define ENALIE BIT(5) +#define ENRP BIT(6) +#define ENMMP BIT(7) +#define ENDFO BIT(8) +#define ENDENI BIT(9) +#define ENRDU BIT(10) +#define ENRXBERR BIT(11) +#define ENCFR BIT(14) +#define ENTXINTR BIT(16) +#define ENTXEMP BIT(17) +#define ENTXCP BIT(18) +#define ENTXDEF BIT(19) +#define ENNCS BIT(20) +#define ENTXABT BIT(21) +#define ENLC BIT(22) +#define ENTDU BIT(23) +#define ENTXBERR BIT(24) + +/* rx and tx owner bit */ +#define RX_OWN_DMA BIT(31) +#define TX_OWN_DMA BIT(31) + +/* tx frame desc controller bit */ +#define MACTXINTEN BIT(2) +#define CRCMODE BIT(1) +#define PADDINGMODE BIT(0) + +/* fftcr controller bit */ +#define RXTHD (0x03 << 0) +#define TXTHD (0x02 << 8) +#define BLENGTH (0x02 << 20) + +/* global setting for driver */ +#define RX_QUEUE_LEN 128 +#define TX_QUEUE_LEN 64 +#define MAX_RBUFF_SZ 0x600 +#define MAX_TBUFF_SZ 0x600 +#define TX_TIMEOUT 50 +#define DELAY 1000 +#define CAM0 0x0 +#define RX_POLL_SIZE 16 + +#ifdef CONFIG_VLAN_8021Q +#define IS_VLAN 1 +#else +#define IS_VLAN 0 +#endif + +#define MAX_PACKET_SIZE (1514 + (IS_VLAN * 4)) +#define MAX_PACKET_SIZE_W_CRC (MAX_PACKET_SIZE + 4) /* 1518 */ + +#define MHZ (1000 * 1000) +#define MII_TIMEOUT 100 + +struct plat_npcm7xx_emc_data { + char *phy_bus_name; + int phy_addr; + unsigned char mac_addr[ETH_ALEN]; +}; + +struct npcm7xx_rxbd { + __le32 sl; + __le32 buffer; + __le32 reserved; + __le32 next; +}; + +struct npcm7xx_txbd { + __le32 mode; /* Ownership bit and some other bits */ + __le32 buffer; /* Transmit Buffer Starting Address */ + __le32 sl; /* Transmit Byte Count and status bits */ + __le32 next; /* Next Tx Descriptor Starting Address */ +}; + +struct npcm7xx_ether { + struct sk_buff *rx_skb[RX_QUEUE_LEN]; + struct sk_buff *tx_skb[TX_QUEUE_LEN]; + spinlock_t lock; /* lock sk */ + struct npcm7xx_rxbd *rdesc; + struct npcm7xx_txbd *tdesc; + dma_addr_t rdesc_phys; + dma_addr_t tdesc_phys; + struct net_device_stats stats; + struct platform_device *pdev; + struct net_device *ndev; + struct resource *res; + unsigned int msg_enable; + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + struct napi_struct napi; + struct ncsi_dev *ncsidev; + bool use_ncsi; + void __iomem *reg; + int rxirq; + int txirq; + unsigned int cur_tx; + unsigned int cur_rx; + unsigned int finish_tx; + unsigned int pending_tx; + __le32 start_tx_ptr; + __le32 start_rx_ptr; + unsigned int rx_berr; + unsigned int rx_err; + unsigned int rdu; + unsigned int rxov; + __le32 camcmr; + unsigned int rx_stuck; + int link; + int speed; + int duplex; + int need_reset; + char *dump_buf; + struct regmap *rst_regmap; + + /* debug counters */ + unsigned int max_waiting_rx; + unsigned int rx_count_pool; + unsigned int count_xmit; + unsigned int rx_int_count; + unsigned int rx_err_count; + unsigned int tx_int_count; + unsigned int tx_tdu; + unsigned int tx_tdu_i; + unsigned int tx_cp_i; + unsigned int count_finish; + +#ifdef CONFIG_DEBUG_FS + struct dentry *dbgfs_dir; + struct dentry *dbgfs_status; + struct dentry *dbgfs_dma_cap; +#endif +}; + +#if defined CONFIG_NPCM7XX_EMC_ETH_DEBUG || defined CONFIG_DEBUG_FS +#define REG_PRINT(reg_name) {t = scnprintf(next, size, "%-10s = %08X\n", \ + #reg_name, readl(ether->reg + reg_name)); size -= t; next += t; } +#define DUMP_PRINT(f, x...) {t = scnprintf(next, size, f, ## x); size -= t; \ + next += t; } + +static int npcm7xx_info_dump(char *buf, int count, struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct npcm7xx_txbd *txbd; + struct npcm7xx_rxbd *rxbd; + unsigned long flags; + unsigned int i, cur, txd_offset, rxd_offset; + char *next = buf; + unsigned int size = count; + int t; + int is_locked = spin_is_locked(ðer->lock); + + if (!is_locked) + spin_lock_irqsave(ðer->lock, flags); + + /* ------basic driver information ---- */ + DUMP_PRINT("NPCM7XX EMC %s driver version: %s\n", dev->name, + DRV_MODULE_VERSION); + + REG_PRINT(REG_CAMCMR); + REG_PRINT(REG_CAMEN); + REG_PRINT(REG_CAMM_BASE); + REG_PRINT(REG_CAML_BASE); + REG_PRINT(REG_TXDLSA); + REG_PRINT(REG_RXDLSA); + REG_PRINT(REG_MCMDR); + REG_PRINT(REG_MIID); + REG_PRINT(REG_MIIDA); + REG_PRINT(REG_FFTCR); + REG_PRINT(REG_TSDR); + REG_PRINT(REG_RSDR); + REG_PRINT(REG_DMARFC); + REG_PRINT(REG_MIEN); + REG_PRINT(REG_MISTA); + REG_PRINT(REG_MGSTA); + REG_PRINT(REG_MPCNT); + writel(0x7FFF, (ether->reg + REG_MPCNT)); + REG_PRINT(REG_MRPC); + REG_PRINT(REG_MRPCC); + REG_PRINT(REG_MREPC); + REG_PRINT(REG_DMARFS); + REG_PRINT(REG_CTXDSA); + REG_PRINT(REG_CTXBSA); + REG_PRINT(REG_CRXDSA); + REG_PRINT(REG_CRXBSA); + REG_PRINT(REG_RXFSM); + REG_PRINT(REG_TXFSM); + REG_PRINT(REG_FSM0); + REG_PRINT(REG_FSM1); + REG_PRINT(REG_DCR); + REG_PRINT(REG_DMMIR); + REG_PRINT(REG_BISTR); + DUMP_PRINT("\n"); + + DUMP_PRINT("netif_queue %s\n\n", netif_queue_stopped(dev) ? + "Stopped" : "Running"); + if (ether->rdesc) + DUMP_PRINT("napi is %s\n\n", test_bit(NAPI_STATE_SCHED, + ðer->napi.state) ? + "scheduled" : + "not scheduled"); + + txd_offset = (readl((ether->reg + REG_CTXDSA)) - + readl((ether->reg + REG_TXDLSA))) / + sizeof(struct npcm7xx_txbd); + DUMP_PRINT("TXD offset %6d\n", txd_offset); + DUMP_PRINT("cur_tx %6d\n", ether->cur_tx); + DUMP_PRINT("finish_tx %6d\n", ether->finish_tx); + DUMP_PRINT("pending_tx %6d\n", ether->pending_tx); + /* debug counters */ + DUMP_PRINT("tx_tdu %6d\n", ether->tx_tdu); + ether->tx_tdu = 0; + DUMP_PRINT("tx_tdu_i %6d\n", ether->tx_tdu_i); + ether->tx_tdu_i = 0; + DUMP_PRINT("tx_cp_i %6d\n", ether->tx_cp_i); + ether->tx_cp_i = 0; + DUMP_PRINT("tx_int_count %6d\n", ether->tx_int_count); + ether->tx_int_count = 0; + DUMP_PRINT("count_xmit tx %6d\n", ether->count_xmit); + ether->count_xmit = 0; + DUMP_PRINT("count_finish %6d\n", ether->count_finish); + ether->count_finish = 0; + DUMP_PRINT("\n"); + + rxd_offset = (readl((ether->reg + REG_CRXDSA)) - + readl((ether->reg + REG_RXDLSA))) + / sizeof(struct npcm7xx_txbd); + DUMP_PRINT("RXD offset %6d\n", rxd_offset); + DUMP_PRINT("cur_rx %6d\n", ether->cur_rx); + DUMP_PRINT("rx_err %6d\n", ether->rx_err); + ether->rx_err = 0; + DUMP_PRINT("rx_berr %6d\n", ether->rx_berr); + ether->rx_berr = 0; + DUMP_PRINT("rx_stuck %6d\n", ether->rx_stuck); + ether->rx_stuck = 0; + DUMP_PRINT("rdu %6d\n", ether->rdu); + ether->rdu = 0; + DUMP_PRINT("rxov rx %6d\n", ether->rxov); + ether->rxov = 0; + /* debug counters */ + DUMP_PRINT("rx_int_count %6d\n", ether->rx_int_count); + ether->rx_int_count = 0; + DUMP_PRINT("rx_err_count %6d\n", ether->rx_err_count); + ether->rx_err_count = 0; + DUMP_PRINT("rx_count_pool %6d\n", ether->rx_count_pool); + ether->rx_count_pool = 0; + DUMP_PRINT("max_waiting_rx %5d\n", ether->max_waiting_rx); + ether->max_waiting_rx = 0; + DUMP_PRINT("\n"); + DUMP_PRINT("need_reset %5d\n", ether->need_reset); + + if (ether->tdesc && ether->rdesc) { + cur = ether->finish_tx - 2; + for (i = 0; i < 3; i++) { + cur = (cur + 1) % TX_QUEUE_LEN; + txbd = (ether->tdesc + cur); + DUMP_PRINT("finish %3d txbd mode %08X buffer %08X sl %08X next %08X tx_skb %p\n", + cur, txbd->mode, txbd->buffer, + txbd->sl, txbd->next, ether->tx_skb[cur]); + } + DUMP_PRINT("\n"); + + cur = txd_offset - 2; + for (i = 0; i < 3; i++) { + cur = (cur + 1) % TX_QUEUE_LEN; + txbd = (ether->tdesc + cur); + DUMP_PRINT("txd_of %3d txbd mode %08X buffer %08X sl %08X next %08X\n", + cur, txbd->mode, txbd->buffer, + txbd->sl, txbd->next); + } + DUMP_PRINT("\n"); + + cur = ether->cur_tx - 63; + for (i = 0; i < 64; i++) { + cur = (cur + 1) % TX_QUEUE_LEN; + txbd = (ether->tdesc + cur); + DUMP_PRINT("cur_tx %3d txbd mode %08X buffer %08X sl %08X next %08X\n", + cur, txbd->mode, txbd->buffer, + txbd->sl, txbd->next); + } + DUMP_PRINT("\n"); + + cur = ether->cur_rx - 63; + for (i = 0; i < 64; i++) { + cur = (cur + 1) % RX_QUEUE_LEN; + rxbd = (ether->rdesc + cur); + DUMP_PRINT("cur_rx %3d rxbd sl %08X buffer %08X sl %08X next %08X\n", + cur, rxbd->sl, rxbd->buffer, + rxbd->reserved, rxbd->next); + } + DUMP_PRINT("\n"); + + cur = rxd_offset - 2; + for (i = 0; i < 3; i++) { + cur = (cur + 1) % RX_QUEUE_LEN; + rxbd = (ether->rdesc + cur); + DUMP_PRINT("rxd_of %3d rxbd sl %08X buffer %08X sl %08X next %08X\n", + cur, rxbd->sl, rxbd->buffer, + rxbd->reserved, rxbd->next); + } + DUMP_PRINT("\n"); + } + + if (!is_locked) + spin_unlock_irqrestore(ðer->lock, flags); + + return count - size; +} +#endif + +#ifdef CONFIG_NPCM7XX_EMC_ETH_DEBUG +static void npcm7xx_info_print(struct net_device *dev) +{ + char *emc_dump_buf; + int count; + struct npcm7xx_ether *ether; + struct platform_device *pdev; + const size_t print_size = 5 * PAGE_SIZE; + + ether = netdev_priv(dev); + pdev = ether->pdev; + + emc_dump_buf = kmalloc(print_size, GFP_KERNEL); + if (!emc_dump_buf) { + dev_err(&pdev->dev, "kmalloc failed\n"); + } else { + char c; + char *tmp_buf = emc_dump_buf; + + count = npcm7xx_info_dump(emc_dump_buf, print_size, dev); + while (count > 512) { + c = tmp_buf[512]; + tmp_buf[512] = 0; + dev_info(&pdev->dev, "%s", tmp_buf); + tmp_buf += 512; + tmp_buf[0] = c; + count -= 512; + } + dev_info(&pdev->dev, "%s", tmp_buf); + kfree(emc_dump_buf); + } +} +#endif + +#ifdef CONFIG_DEBUG_FS +#include <linux/seq_file.h> + +static int npcm7xx_debug_show(struct seq_file *sf, void *v) +{ + struct net_device *dev = (struct net_device *)sf->private; + struct npcm7xx_ether *ether = netdev_priv(dev); + const size_t print_size = 5 * PAGE_SIZE; + + if (!ether->dump_buf) { + ether->dump_buf = kmalloc(print_size, GFP_KERNEL); + if (!ether->dump_buf) + return -1; + npcm7xx_info_dump(ether->dump_buf, print_size, dev); + } + + seq_printf(sf, "%s", ether->dump_buf); + if (sf->count < sf->size) { + kfree(ether->dump_buf); + ether->dump_buf = NULL; + } + + return 0; +} + +static int npcm7xx_debug_show_open(struct inode *inode, struct file *file) +{ + return single_open(file, npcm7xx_debug_show, inode->i_private); +} + +static const struct file_operations npcm7xx_debug_show_fops = { + .open = npcm7xx_debug_show_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int npcm7xx_debug_reset(struct seq_file *sf, void *v) +{ + struct net_device *dev = (struct net_device *)sf->private; + struct npcm7xx_ether *ether = netdev_priv(dev); + unsigned long flags; + + seq_puts(sf, "Ask to reset the module\n"); + spin_lock_irqsave(ðer->lock, flags); + writel(0, (ether->reg + REG_MIEN)); + spin_unlock_irqrestore(ðer->lock, flags); + ether->need_reset = 1; + napi_schedule(ðer->napi); + + return 0; +} + +static int npcm7xx_debug_reset_open(struct inode *inode, struct file *file) +{ + return single_open(file, npcm7xx_debug_reset, inode->i_private); +} + +static const struct file_operations npcm7xx_debug_reset_fops = { + .owner = THIS_MODULE, + .open = npcm7xx_debug_reset_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int npcm7xx_debug_fs(struct npcm7xx_ether *ether) +{ + /* Create debugfs main directory if it doesn't exist yet */ + if (!npcm7xx_fs_dir) { + npcm7xx_fs_dir = debugfs_create_dir(DRV_MODULE_NAME, NULL); + + if (!npcm7xx_fs_dir || IS_ERR(npcm7xx_fs_dir)) { + dev_err(ðer->pdev->dev, "ERROR %s, debugfs create directory failed\n", + DRV_MODULE_NAME); + return -ENOMEM; + } + } + + /* Create per netdev entries */ + ether->dbgfs_dir = debugfs_create_dir(ether->ndev->name, + npcm7xx_fs_dir); + if (!ether->dbgfs_dir || IS_ERR(ether->dbgfs_dir)) { + dev_err(ðer->pdev->dev, "ERROR failed to create %s directory\n", ether->ndev->name); + return -ENOMEM; + } + + /* Entry to report DMA RX/TX rings */ + ether->dbgfs_status = + debugfs_create_file("status", 0444, + ether->dbgfs_dir, ether->ndev, + &npcm7xx_debug_show_fops); + + if (!ether->dbgfs_status || IS_ERR(ether->dbgfs_status)) { + dev_err(ðer->pdev->dev, "ERROR creating \'status\' debugfs file\n"); + debugfs_remove_recursive(ether->dbgfs_dir); + + return -ENOMEM; + } + + /* Entry to report the DMA HW features */ + ether->dbgfs_dma_cap = debugfs_create_file("do_reset", 0444, + ether->dbgfs_dir, + ether->ndev, + &npcm7xx_debug_reset_fops); + + if (!ether->dbgfs_dma_cap || IS_ERR(ether->dbgfs_dma_cap)) { + dev_err(ðer->pdev->dev, "ERROR creating stmmac \'do_reset\' debugfs file\n"); + debugfs_remove_recursive(ether->dbgfs_dir); + + return -ENOMEM; + } + + return 0; +} +#endif + +static void npcm7xx_opmode(struct net_device *dev, int speed, int duplex) +{ + __le32 val; + struct npcm7xx_ether *ether = netdev_priv(dev); + + val = readl((ether->reg + REG_MCMDR)); + if (speed == 100) + val |= MCMDR_OPMOD; + else + val &= ~MCMDR_OPMOD; + + if (duplex == DUPLEX_FULL) + val |= MCMDR_FDUP; + else + val &= ~MCMDR_FDUP; + + writel(val, (ether->reg + REG_MCMDR)); +} + +static void adjust_link(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct phy_device *phydev = ether->phy_dev; + bool status_change = false; + unsigned long flags; + + /* clear GPIO interrupt status whihc indicates PHY statu change? */ + spin_lock_irqsave(ðer->lock, flags); + + if (phydev->link) { + if (ether->speed != phydev->speed || + ether->duplex != phydev->duplex) { + ether->speed = phydev->speed; + ether->duplex = phydev->duplex; + status_change = true; + } + } else { + ether->speed = 0; + ether->duplex = -1; + } + + if (phydev->link != ether->link) { + ether->link = phydev->link; + status_change = true; + } + + spin_unlock_irqrestore(ðer->lock, flags); + + if (status_change) + npcm7xx_opmode(dev, ether->speed, ether->duplex); +} + +static void npcm7xx_write_cam(struct net_device *dev, + unsigned int x, unsigned char *pval) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + __le32 msw, lsw; + + msw = (pval[0] << 24) | (pval[1] << 16) | (pval[2] << 8) | pval[3]; + + lsw = (pval[4] << 24) | (pval[5] << 16); + + writel(lsw, (ether->reg + REG_CAML_BASE) + x * CAM_ENTRY_SIZE); + writel(msw, (ether->reg + REG_CAMM_BASE) + x * CAM_ENTRY_SIZE); + dev_dbg(ðer->pdev->dev, "REG_CAML_BASE = 0x%08X REG_CAMM_BASE = 0x%08X", lsw, msw); +} + +static struct sk_buff *get_new_skb(struct net_device *dev, u32 i) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct sk_buff *skb = dev_alloc_skb(roundup(MAX_PACKET_SIZE_W_CRC, 4)); + + if (!skb) + return NULL; + + /* Do not unmark the following skb_reserve() Receive Buffer Starting + * Address must be aligned to 4 bytes and the following line + * if unmarked will make it align to 2 and this likely will + * hult the RX and crash the linux skb_reserve(skb, NET_IP_ALIGN); + */ + skb->dev = dev; + (ether->rdesc + i)->buffer = + dma_map_single(&dev->dev, skb->data, + roundup(MAX_PACKET_SIZE_W_CRC, 4), + DMA_FROM_DEVICE); + ether->rx_skb[i] = skb; + + return skb; +} + +static int npcm7xx_init_desc(struct net_device *dev) +{ + struct npcm7xx_ether *ether; + struct npcm7xx_txbd *tdesc; + struct npcm7xx_rxbd *rdesc; + struct platform_device *pdev; + unsigned int i; + + ether = netdev_priv(dev); + pdev = ether->pdev; + + if (!ether->tdesc) { + ether->tdesc = (struct npcm7xx_txbd *) + dma_alloc_coherent(&pdev->dev, + sizeof(struct npcm7xx_txbd) * + TX_QUEUE_LEN, + ðer->tdesc_phys, + GFP_KERNEL); + + if (!ether->tdesc) { + dev_err(&pdev->dev, "Failed to allocate memory for tx desc\n"); + return -ENOMEM; + } + } + + if (!ether->rdesc) { + ether->rdesc = (struct npcm7xx_rxbd *) + dma_alloc_coherent(&pdev->dev, + sizeof(struct npcm7xx_rxbd) * + RX_QUEUE_LEN, + ðer->rdesc_phys, + GFP_KERNEL); + + if (!ether->rdesc) { + dev_err(&pdev->dev, "Failed to allocate memory for rx desc\n"); + dma_free_coherent(&pdev->dev, + sizeof(struct npcm7xx_txbd) * + TX_QUEUE_LEN, ether->tdesc, + ether->tdesc_phys); + ether->tdesc = NULL; + return -ENOMEM; + } + } + + for (i = 0; i < TX_QUEUE_LEN; i++) { + unsigned int offset; + + tdesc = (ether->tdesc + i); + + if (i == TX_QUEUE_LEN - 1) + offset = 0; + else + offset = sizeof(struct npcm7xx_txbd) * (i + 1); + + tdesc->next = ether->tdesc_phys + offset; + tdesc->buffer = (__le32)NULL; + tdesc->sl = 0; + tdesc->mode = 0; + } + + ether->start_tx_ptr = ether->tdesc_phys; + + for (i = 0; i < RX_QUEUE_LEN; i++) { + unsigned int offset; + + rdesc = (ether->rdesc + i); + + if (i == RX_QUEUE_LEN - 1) + offset = 0; + else + offset = sizeof(struct npcm7xx_rxbd) * (i + 1); + + rdesc->next = ether->rdesc_phys + offset; + rdesc->sl = RX_OWN_DMA; + + if (!get_new_skb(dev, i)) { + dev_err(&pdev->dev, "get_new_skb() failed\n"); + + for (; i != 0; i--) { + dma_unmap_single(&dev->dev, (dma_addr_t) + ((ether->rdesc + i)->buffer), + roundup(MAX_PACKET_SIZE_W_CRC, + 4), DMA_FROM_DEVICE); + dev_kfree_skb_any(ether->rx_skb[i]); + ether->rx_skb[i] = NULL; + } + + dma_free_coherent(&pdev->dev, + sizeof(struct npcm7xx_txbd) * + TX_QUEUE_LEN, + ether->tdesc, ether->tdesc_phys); + dma_free_coherent(&pdev->dev, + sizeof(struct npcm7xx_rxbd) * + RX_QUEUE_LEN, + ether->rdesc, ether->rdesc_phys); + + return -ENOMEM; + } + } + + ether->start_rx_ptr = ether->rdesc_phys; + wmb(); + for (i = 0; i < TX_QUEUE_LEN; i++) + ether->tx_skb[i] = NULL; + + return 0; +} + +/* This API must call with Tx/Rx stopped */ +static void npcm7xx_free_desc(struct net_device *dev, + bool free_also_descriptors) +{ + struct sk_buff *skb; + u32 i; + struct npcm7xx_ether *ether = netdev_priv(dev); + struct platform_device *pdev = ether->pdev; + + for (i = 0; i < TX_QUEUE_LEN; i++) { + skb = ether->tx_skb[i]; + if (skb) { + dma_unmap_single(&dev->dev, (dma_addr_t)((ether->tdesc + + i)->buffer), + skb->len, DMA_TO_DEVICE); + dev_kfree_skb_any(skb); + ether->tx_skb[i] = NULL; + } + } + + for (i = 0; i < RX_QUEUE_LEN; i++) { + skb = ether->rx_skb[i]; + if (skb) { + dma_unmap_single(&dev->dev, (dma_addr_t)((ether->rdesc + + i)->buffer), + roundup(MAX_PACKET_SIZE_W_CRC, 4), + DMA_FROM_DEVICE); + dev_kfree_skb_any(skb); + ether->rx_skb[i] = NULL; + } + } + + if (free_also_descriptors) { + if (ether->tdesc) + dma_free_coherent(&pdev->dev, + sizeof(struct npcm7xx_txbd) * + TX_QUEUE_LEN, + ether->tdesc, ether->tdesc_phys); + ether->tdesc = NULL; + + if (ether->rdesc) + dma_free_coherent(&pdev->dev, + sizeof(struct npcm7xx_rxbd) * + RX_QUEUE_LEN, + ether->rdesc, ether->rdesc_phys); + ether->rdesc = NULL; + } +} + +static void npcm7xx_set_fifo_threshold(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + __le32 val; + + val = RXTHD | TXTHD | BLENGTH; + writel(val, (ether->reg + REG_FFTCR)); +} + +static void npcm7xx_return_default_idle(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + __le32 val; + __le32 saved_bits; + + val = readl((ether->reg + REG_MCMDR)); + saved_bits = val & (MCMDR_FDUP | MCMDR_OPMOD); + val |= SWR; + writel(val, (ether->reg + REG_MCMDR)); + + /* During the EMC reset the AHB will read 0 from all registers, + * so in order to see if the reset finished we can't count on + * (ether->reg + REG_MCMDR).SWR to become 0, instead we read another + * register that its reset value is not 0, + * we choose (ether->reg + REG_FFTCR). + */ + do { + val = readl((ether->reg + REG_FFTCR)); + } while (val == 0); + + /* + * Now we can verify if (ether->reg + REG_MCMDR).SWR became + * 0 (probably it will be 0 on the first read). + */ + do { + val = readl((ether->reg + REG_MCMDR)); + } while (val & SWR); + + /* restore values */ + writel(saved_bits, (ether->reg + REG_MCMDR)); +} + +static void npcm7xx_enable_mac_interrupt(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + __le32 val; + + val = ENRXINTR | /* Start of RX interrupts */ + ENCRCE | + EMRXOV | + (ENPTLE * (!IS_VLAN)) | /* If we don't support VLAN we want interrupt on long packets */ + ENRXGD | + ENALIE | + ENRP | + ENMMP | + ENDFO | + /* ENDENI | */ /* We don't need interrupt on DMA Early Notification */ + ENRDU | /* We don't need interrupt on Receive Descriptor Unavailable Interrupt */ + ENRXBERR | + /* ENCFR | */ + ENTXINTR | /* Start of TX interrupts */ + ENTXEMP | + ENTXCP | + ENTXDEF | + ENNCS | + ENTXABT | + ENLC | + /* ENTDU | */ /* We don't need interrupt on Transmit Descriptor Unavailable at start of operation */ + ENTXBERR; + writel(val, (ether->reg + REG_MIEN)); +} + +static void npcm7xx_get_and_clear_int(struct net_device *dev, + __le32 *val, __le32 mask) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + + *val = readl((ether->reg + REG_MISTA)) & mask; + writel(*val, (ether->reg + REG_MISTA)); +} + +static void npcm7xx_set_global_maccmd(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + __le32 val; + + val = readl((ether->reg + REG_MCMDR)); + + val |= MCMDR_SPCRC | MCMDR_ENMDC | MCMDR_ACP | MCMDR_NDEF; + if (IS_VLAN) { + /* + * we set ALP accept long packets since VLAN packets + * are 4 bytes longer than 1518 + */ + val |= MCMDR_ALP; + /* limit receive length to 1522 bytes due to VLAN */ + writel(MAX_PACKET_SIZE_W_CRC, (ether->reg + REG_DMARFC)); + } + writel(val, (ether->reg + REG_MCMDR)); +} + +static void npcm7xx_enable_cam(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + __le32 val; + + npcm7xx_write_cam(dev, CAM0, dev->dev_addr); + + val = readl((ether->reg + REG_CAMEN)); + val |= CAM0EN; + writel(val, (ether->reg + REG_CAMEN)); +} + +static void npcm7xx_set_curdest(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + + writel(ether->start_rx_ptr, (ether->reg + REG_RXDLSA)); + writel(ether->start_tx_ptr, (ether->reg + REG_TXDLSA)); +} + +static void npcm7xx_ether_set_rx_mode(struct net_device *dev) +{ + struct npcm7xx_ether *ether; + __le32 rx_mode; + + ether = netdev_priv(dev); + + dev_dbg(ðer->pdev->dev, "%s CAMCMR_AUP\n", + (dev->flags & IFF_PROMISC) ? "Set" : "Clear"); + if (dev->flags & IFF_PROMISC) + rx_mode = CAMCMR_AUP | CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP; + else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) + rx_mode = CAMCMR_AMP | CAMCMR_ABP | CAMCMR_ECMP; + else + rx_mode = CAMCMR_ECMP | CAMCMR_ABP; + writel(rx_mode, (ether->reg + REG_CAMCMR)); + ether->camcmr = rx_mode; +} + +static void npcm7xx_reset_mac(struct net_device *dev, int need_free) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + + netif_tx_lock(dev); + + /* disable RX and TX */ + writel(readl((ether->reg + REG_MCMDR)) & ~(MCMDR_TXON | MCMDR_RXON), + (ether->reg + REG_MCMDR)); + + npcm7xx_return_default_idle(dev); + npcm7xx_set_fifo_threshold(dev); + + if (need_free) + npcm7xx_free_desc(dev, false); + + npcm7xx_init_desc(dev); + + ether->cur_tx = 0x0; + ether->finish_tx = 0x0; + ether->pending_tx = 0x0; + ether->cur_rx = 0x0; + ether->tx_tdu = 0; + ether->tx_tdu_i = 0; + ether->tx_cp_i = 0; + + npcm7xx_set_curdest(dev); + npcm7xx_enable_cam(dev); + npcm7xx_ether_set_rx_mode(dev); + npcm7xx_enable_mac_interrupt(dev); + npcm7xx_set_global_maccmd(dev); + + /* enable RX and TX */ + writel(readl((ether->reg + REG_MCMDR)) | MCMDR_TXON | MCMDR_RXON, + (ether->reg + REG_MCMDR)); + + /* trigger RX */ + writel(ENSTART, (ether->reg + REG_RSDR)); + + ether->need_reset = 0; + + netif_wake_queue(dev); + netif_tx_unlock(dev); +} + +static int npcm7xx_mdio_write(struct mii_bus *bus, int phy_id, int regnum, + u16 value) +{ + struct npcm7xx_ether *ether = bus->priv; + unsigned long timeout = jiffies + msecs_to_jiffies(MII_TIMEOUT * 100); + + writel(value, (ether->reg + REG_MIID)); + writel((phy_id << 0x08) | regnum | PHYBUSY | PHYWR, + (ether->reg + REG_MIIDA)); + + /* Wait for completion */ + while (readl((ether->reg + REG_MIIDA)) & PHYBUSY) { + if (time_after(jiffies, timeout)) { + dev_dbg(ðer->pdev->dev, "mdio read timed out\n ether->reg = 0x%x phy_id=0x%x REG_MIIDA=0x%x\n", + (unsigned int)ether->reg, phy_id + , readl((ether->reg + REG_MIIDA))); + return -ETIMEDOUT; + } + cpu_relax(); + } + + return 0; +} + +static int npcm7xx_mdio_read(struct mii_bus *bus, int phy_id, int regnum) +{ + struct npcm7xx_ether *ether = bus->priv; + unsigned long timeout = jiffies + msecs_to_jiffies(MII_TIMEOUT * 100); + + writel((phy_id << 0x08) | regnum | PHYBUSY, (ether->reg + REG_MIIDA)); + + /* Wait for completion */ + while (readl((ether->reg + REG_MIIDA)) & PHYBUSY) { + if (time_after(jiffies, timeout)) { + dev_dbg(ðer->pdev->dev, "mdio read timed out\n ether->reg = 0x%x phy_id=0x%x REG_MIIDA=0x%x\n", + (unsigned int)ether->reg, phy_id + , readl((ether->reg + REG_MIIDA))); + return -ETIMEDOUT; + } + cpu_relax(); + } + + return readl((ether->reg + REG_MIID)); +} + +static int npcm7xx_mdio_reset(struct mii_bus *bus) +{ + /* reset EMAC engine?? */ + return 0; +} + +static int npcm7xx_set_mac_address(struct net_device *dev, void *addr) +{ + struct sockaddr *address = addr; + + if (!is_valid_ether_addr((u8 *)address->sa_data)) + return -EADDRNOTAVAIL; + + memcpy(dev->dev_addr, address->sa_data, dev->addr_len); + npcm7xx_write_cam(dev, CAM0, dev->dev_addr); + + return 0; +} + +static int npcm7xx_ether_close(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + + npcm7xx_return_default_idle(dev); + + if (ether->phy_dev) + phy_stop(ether->phy_dev); + else if (ether->use_ncsi) + ncsi_stop_dev(ether->ncsidev); + + msleep(20); + + free_irq(ether->txirq, dev); + free_irq(ether->rxirq, dev); + + netif_stop_queue(dev); + napi_disable(ðer->napi); + + npcm7xx_free_desc(dev, true); + + kfree(ether->dump_buf); + ether->dump_buf = NULL; + + return 0; +} + +static struct net_device_stats *npcm7xx_ether_stats(struct net_device *dev) +{ + struct npcm7xx_ether *ether; + + ether = netdev_priv(dev); + return ðer->stats; +} + +static int npcm7xx_clean_tx(struct net_device *dev, bool from_xmit) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct npcm7xx_txbd *txbd; + struct sk_buff *s; + dma_addr_t cur_entry, entry; + __le32 sl; + + if (ether->pending_tx == 0) + return (0); + + cur_entry = readl((ether->reg + REG_CTXDSA)); + + /* Release old used buffers */ + entry = ether->tdesc_phys + sizeof(struct npcm7xx_txbd) * + (ether->finish_tx); + + while (entry != cur_entry) { + txbd = (ether->tdesc + ether->finish_tx); + s = ether->tx_skb[ether->finish_tx]; + if (!s) + break; + + ether->count_finish++; + + dma_unmap_single(&dev->dev, txbd->buffer, s->len, + DMA_TO_DEVICE); + consume_skb(s); + ether->tx_skb[ether->finish_tx] = NULL; + + if (++ether->finish_tx >= TX_QUEUE_LEN) + ether->finish_tx = 0; + ether->pending_tx--; + + sl = txbd->sl; + if (sl & TXDS_TXCP) { + ether->stats.tx_packets++; + ether->stats.tx_bytes += (sl & 0xFFFF); + } else { + ether->stats.tx_errors++; + } + + entry = ether->tdesc_phys + sizeof(struct npcm7xx_txbd) * + (ether->finish_tx); + } + + if (!from_xmit && unlikely(netif_queue_stopped(dev) && + (TX_QUEUE_LEN - ether->pending_tx) > 1)) { + netif_tx_lock(dev); + if (netif_queue_stopped(dev) && + (TX_QUEUE_LEN - ether->pending_tx) > 1) { + netif_wake_queue(dev); + } + netif_tx_unlock(dev); + } + + return(0); +} + +static int npcm7xx_ether_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct npcm7xx_txbd *txbd; + unsigned long flags; + + ether->count_xmit++; + + /* Insert new buffer */ + txbd = (ether->tdesc + ether->cur_tx); + txbd->buffer = dma_map_single(&dev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + ether->tx_skb[ether->cur_tx] = skb; + if (skb->len > MAX_PACKET_SIZE) + dev_err(ðer->pdev->dev, "skb->len (= %d) > MAX_PACKET_SIZE (= %d)\n", + skb->len, MAX_PACKET_SIZE); + + txbd->sl = skb->len > MAX_PACKET_SIZE ? MAX_PACKET_SIZE : skb->len; + dma_wmb(); + + txbd->mode = TX_OWN_DMA | PADDINGMODE | CRCMODE; + wmb(); + + /* trigger TX */ + writel(ENSTART, (ether->reg + REG_TSDR)); + + if (++ether->cur_tx >= TX_QUEUE_LEN) + ether->cur_tx = 0; + + spin_lock_irqsave(ðer->lock, flags); + ether->pending_tx++; + + npcm7xx_clean_tx(dev, true); + + if (ether->pending_tx >= TX_QUEUE_LEN - 1) { + __le32 reg_mien; + unsigned int index_to_wake = ether->cur_tx + + ((TX_QUEUE_LEN * 3) / 4); + + if (index_to_wake >= TX_QUEUE_LEN) + index_to_wake -= TX_QUEUE_LEN; + + txbd = (ether->tdesc + index_to_wake); + txbd->mode = TX_OWN_DMA | PADDINGMODE | CRCMODE | MACTXINTEN; + wmb(); + + writel(MISTA_TDU, (ether->reg + REG_MISTA)); + /* Clear TDU interrupt */ + reg_mien = readl((ether->reg + REG_MIEN)); + + if (reg_mien != 0) + /* Enable TDU interrupt */ + writel(reg_mien | ENTDU, (ether->reg + REG_MIEN)); + + ether->tx_tdu++; + netif_stop_queue(dev); + } + + spin_unlock_irqrestore(ðer->lock, flags); + + return 0; +} + +static irqreturn_t npcm7xx_tx_interrupt(int irq, void *dev_id) +{ + struct npcm7xx_ether *ether; + struct platform_device *pdev; + struct net_device *dev; + __le32 status; + unsigned long flags; + + dev = dev_id; + ether = netdev_priv(dev); + pdev = ether->pdev; + + npcm7xx_get_and_clear_int(dev, &status, 0xFFFF0000); + + ether->tx_int_count++; + + if (status & MISTA_EXDEF) + dev_err(&pdev->dev, "emc defer exceed interrupt status=0x%08X\n" + , status); + else if (status & MISTA_TXBERR) { + dev_err(&pdev->dev, "emc bus error interrupt status=0x%08X\n", + status); +#ifdef CONFIG_NPCM7XX_EMC_ETH_DEBUG + npcm7xx_info_print(dev); +#endif + spin_lock_irqsave(ðer->lock, flags); + writel(0, (ether->reg + REG_MIEN)); /* disable any interrupt */ + spin_unlock_irqrestore(ðer->lock, flags); + ether->need_reset = 1; + } else if (status & ~(MISTA_TXINTR | MISTA_TXCP | MISTA_TDU)) + dev_err(&pdev->dev, "emc other error interrupt status=0x%08X\n", + status); + + /* if we got MISTA_TXCP | MISTA_TDU remove those interrupt and call napi */ + if (status & (MISTA_TXCP | MISTA_TDU) & + readl((ether->reg + REG_MIEN))) { + __le32 reg_mien; + + spin_lock_irqsave(ðer->lock, flags); + reg_mien = readl((ether->reg + REG_MIEN)); + if (reg_mien & ENTDU) + /* Disable TDU interrupt */ + writel(reg_mien & (~ENTDU), (ether->reg + REG_MIEN)); + + spin_unlock_irqrestore(ðer->lock, flags); + + if (status & MISTA_TXCP) + ether->tx_cp_i++; + if (status & MISTA_TDU) + ether->tx_tdu_i++; + } else { + dev_dbg(&pdev->dev, "status=0x%08X\n", status); + } + + napi_schedule(ðer->napi); + + return IRQ_HANDLED; +} + +static irqreturn_t npcm7xx_rx_interrupt(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct npcm7xx_ether *ether = netdev_priv(dev); + struct platform_device *pdev = ether->pdev; + __le32 status; + unsigned long flags; + unsigned int any_err = 0; + __le32 rxfsm; + + npcm7xx_get_and_clear_int(dev, &status, 0xFFFF); + ether->rx_int_count++; + + if (unlikely(status & MISTA_RXBERR)) { + ether->rx_berr++; + dev_err(&pdev->dev, "emc rx bus error status=0x%08X\n", status); +#ifdef CONFIG_NPCM7XX_EMC_ETH_DEBUG + npcm7xx_info_print(dev); +#endif + spin_lock_irqsave(ðer->lock, flags); + writel(0, (ether->reg + REG_MIEN)); /* disable any interrupt */ + spin_unlock_irqrestore(ðer->lock, flags); + ether->need_reset = 1; + napi_schedule(ðer->napi); + return IRQ_HANDLED; + } + + if (unlikely(status & (MISTA_RXOV | MISTA_RDU))) { + /* + * filter out all received packets until we have + * enough available buffer descriptors + */ + writel(0, (ether->reg + REG_CAMCMR)); + any_err = 1; + if (status & (MISTA_RXOV)) + ether->rxov++; + if (status & (MISTA_RDU)) + ether->rdu++; + + /* + * workaround Errata 1.36: EMC Hangs on receiving 253-256 + * byte packet + */ + rxfsm = readl((ether->reg + REG_RXFSM)); + + if ((rxfsm & 0xFFFFF000) == 0x08044000) { + int i; + + for (i = 0; i < 32; i++) { + rxfsm = readl((ether->reg + REG_RXFSM)); + if ((rxfsm & 0xFFFFF000) != 0x08044000) + break; + } + if (i == 32) { + ether->rx_stuck++; + spin_lock_irqsave(ðer->lock, flags); +#ifdef CONFIG_NPCM7XX_EMC_ETH_DEBUG + npcm7xx_info_print(dev); +#endif + writel(0, (ether->reg + REG_MIEN)); + spin_unlock_irqrestore(ðer->lock, flags); + ether->need_reset = 1; + napi_schedule(ðer->napi); + dev_err(&pdev->dev, "stuck on REG_RXFSM = 0x%08X status=%08X doing reset!\n", rxfsm, status); + return IRQ_HANDLED; + } + } + } + + /* echo MISTA status on unexpected flags although we don't do anithing with them */ + if (unlikely(status & + (/* MISTA_RXINTR | */ /* Receive - all RX interrupt set this */ + MISTA_CRCE | /* CRC Error */ + /* MISTA_RXOV | */ /* Receive FIFO Overflow - we alread handled it */ + (MISTA_PTLE * !IS_VLAN) | /* Packet Too Long is needed if VLAN is not supported */ + /* MISTA_RXGD | */ /* Receive Good - this is the common good case */ + MISTA_ALIE | /* Alignment Error */ + MISTA_RP | /* Runt Packet */ + MISTA_MMP | /* More Missed Packet */ + MISTA_DFOI | /* Maximum Frame Length */ + /* MISTA_DENI | */ /* DMA Early Notification - every packet get this */ + /* MISTA_RDU | */ /* Receive Descriptor Unavailable */ + /* MISTA_RXBERR | */ /* Receive Bus Error Interrupt - we alread handled it */ + /* MISTA_CFR | */ /* Control Frame Receive - not an error */ + 0))) { + dev_dbg(&pdev->dev, "emc rx MISTA status=0x%08X\n", status); + any_err = 1; + ether->rx_err++; + } + + if (!any_err && ((status & MISTA_RXGD) == 0)) + dev_err(&pdev->dev, "emc rx MISTA status=0x%08X\n", status); + + spin_lock_irqsave(ðer->lock, flags); + writel(readl((ether->reg + REG_MIEN)) & ~ENRXGD, + (ether->reg + REG_MIEN)); + spin_unlock_irqrestore(ðer->lock, flags); + napi_schedule(ðer->napi); + + return IRQ_HANDLED; +} + +static int npcm7xx_poll(struct napi_struct *napi, int budget) +{ + struct npcm7xx_ether *ether = + container_of(napi, struct npcm7xx_ether, napi); + struct npcm7xx_rxbd *rxbd; + struct net_device *dev = ether->ndev; + struct platform_device *pdev = ether->pdev; + struct sk_buff *skb, *s; + unsigned int length; + __le32 status; + unsigned long flags; + int rx_cnt = 0; + int complete = 0; + unsigned int rx_offset = (readl((ether->reg + REG_CRXDSA)) - + ether->start_rx_ptr) / + sizeof(struct npcm7xx_txbd); + unsigned int local_count = (rx_offset >= ether->cur_rx) ? + rx_offset - ether->cur_rx : rx_offset + + RX_QUEUE_LEN - ether->cur_rx; + + if (local_count > ether->max_waiting_rx) + ether->max_waiting_rx = local_count; + + if (local_count > (4 * RX_POLL_SIZE)) + /* + * we are porbably in a storm of short packets and we don't + * want to get into RDU since short packets in RDU cause + * many RXOV which may cause EMC halt, so we filter out all + * coming packets + */ + writel(0, (ether->reg + REG_CAMCMR)); + + if (local_count <= budget) + /* we can restore accepting of packets */ + writel(ether->camcmr, (ether->reg + REG_CAMCMR)); + + spin_lock_irqsave(ðer->lock, flags); + npcm7xx_clean_tx(dev, false); + spin_unlock_irqrestore(ðer->lock, flags); + + rxbd = (ether->rdesc + ether->cur_rx); + + while (rx_cnt < budget) { + status = rxbd->sl; + if ((status & RX_OWN_DMA) == RX_OWN_DMA) { + complete = 1; + break; + } + /* for debug puposes we save the previous value */ + rxbd->reserved = status; + s = ether->rx_skb[ether->cur_rx]; + length = status & 0xFFFF; + + /* + * If VLAN is not supporte RXDS_PTLE (packet too long) is also + * an error + */ + if (likely((status & (RXDS_RXGD | RXDS_CRCE | RXDS_ALIE | + RXDS_RP | (IS_VLAN ? 0 : RXDS_PTLE))) == + RXDS_RXGD) && likely(length <= MAX_PACKET_SIZE)) { + dma_unmap_single(&dev->dev, (dma_addr_t)rxbd->buffer, + roundup(MAX_PACKET_SIZE_W_CRC, 4), + DMA_FROM_DEVICE); + + skb_put(s, length); + s->protocol = eth_type_trans(s, dev); + netif_receive_skb(s); + ether->stats.rx_packets++; + ether->stats.rx_bytes += length; + rx_cnt++; + ether->rx_count_pool++; + + /* now we allocate new skb instead if the used one. */ + skb = dev_alloc_skb(roundup(MAX_PACKET_SIZE_W_CRC, 4)); + if (!skb) { + dev_err(&pdev->dev, "get skb buffer error\n"); + ether->stats.rx_dropped++; + goto rx_out; + } + + /* Do not unmark the following skb_reserve() Receive + * Buffer Starting Address must be aligned + * to 4 bytes and the following line if unmarked + * will make it align to 2 and this likely + * will hult the RX and crash the linux + * skb_reserve(skb, NET_IP_ALIGN); + */ + skb->dev = dev; + + rxbd->buffer = dma_map_single(&dev->dev, skb->data, + roundup(MAX_PACKET_SIZE_W_CRC, 4), + DMA_FROM_DEVICE); + ether->rx_skb[ether->cur_rx] = skb; + } else { + ether->rx_err_count++; + ether->stats.rx_errors++; + dev_dbg(&pdev->dev, "rx_errors = %lu status = 0x%08X\n", + ether->stats.rx_errors, status); + + if (status & RXDS_RP) { + ether->stats.rx_length_errors++; + dev_dbg(&pdev->dev, "rx_length_errors = %lu\n", + ether->stats.rx_length_errors); + } else if (status & RXDS_CRCE) { + ether->stats.rx_crc_errors++; + dev_dbg(&pdev->dev, "rx_crc_errors = %lu\n", + ether->stats.rx_crc_errors); + } else if (status & RXDS_ALIE) { + ether->stats.rx_frame_errors++; + dev_dbg(&pdev->dev, "rx_frame_errors = %lu\n", + ether->stats.rx_frame_errors); + } else if (((!IS_VLAN) && (status & RXDS_PTLE)) || + length > MAX_PACKET_SIZE) { + ether->stats.rx_length_errors++; + dev_dbg(&pdev->dev, "rx_length_errors = %lu\n", + ether->stats.rx_length_errors); + } + } + + wmb(); + rxbd->sl = RX_OWN_DMA; + wmb(); + + if (++ether->cur_rx >= RX_QUEUE_LEN) + ether->cur_rx = 0; + + rxbd = (ether->rdesc + ether->cur_rx); + } + + if (complete) { + napi_complete(napi); + + if (ether->need_reset) { + dev_dbg(&pdev->dev, "Reset\n"); + npcm7xx_reset_mac(dev, 1); + } + + spin_lock_irqsave(ðer->lock, flags); + writel(readl((ether->reg + REG_MIEN)) | ENRXGD, (ether->reg + + REG_MIEN)); + spin_unlock_irqrestore(ðer->lock, flags); + } else { + rx_offset = (readl((ether->reg + REG_CRXDSA)) - + ether->start_rx_ptr) / sizeof(struct npcm7xx_txbd); + local_count = (rx_offset >= ether->cur_rx) ? rx_offset - + ether->cur_rx : rx_offset + RX_QUEUE_LEN - + ether->cur_rx; + + if (local_count > ether->max_waiting_rx) + ether->max_waiting_rx = local_count; + + if (local_count > (3 * RX_POLL_SIZE)) + /* + * we are porbably in a storm of short packets and + * we don't want to get into RDU since short packets in + * RDU cause many RXOV which may cause + * EMC halt, so we filter out all coming packets + */ + writel(0, (ether->reg + REG_CAMCMR)); + if (local_count <= RX_POLL_SIZE) + /* we can restore accepting of packets */ + writel(ether->camcmr, (ether->reg + REG_CAMCMR)); + } +rx_out: + + /* trigger RX */ + writel(ENSTART, (ether->reg + REG_RSDR)); + return rx_cnt; +} + +static int npcm7xx_ether_open(struct net_device *dev) +{ + struct npcm7xx_ether *ether; + struct platform_device *pdev; + + ether = netdev_priv(dev); + pdev = ether->pdev; + + if (ether->use_ncsi) { + ether->speed = 100; + ether->duplex = DUPLEX_FULL; + npcm7xx_opmode(dev, 100, DUPLEX_FULL); + } + npcm7xx_reset_mac(dev, 0); + + if (request_irq(ether->txirq, npcm7xx_tx_interrupt, 0x0, pdev->name, + dev)) { + dev_err(&pdev->dev, "register irq tx failed\n"); + npcm7xx_ether_close(dev); + return -EAGAIN; + } + + if (request_irq(ether->rxirq, npcm7xx_rx_interrupt, 0x0, pdev->name, + dev)) { + dev_err(&pdev->dev, "register irq rx failed\n"); + npcm7xx_ether_close(dev); + return -EAGAIN; + } + + if (ether->phy_dev) + phy_start(ether->phy_dev); + else if (ether->use_ncsi) + netif_carrier_on(dev); + + netif_start_queue(dev); + napi_enable(ðer->napi); + + /* trigger RX */ + writel(ENSTART, (ether->reg + REG_RSDR)); + + /* Start the NCSI device */ + if (ether->use_ncsi) { + int err = ncsi_start_dev(ether->ncsidev); + + if (err) { + npcm7xx_ether_close(dev); + return err; + } + } + + dev_info(&pdev->dev, "%s is OPENED\n", dev->name); + + return 0; +} + +static int npcm7xx_ether_ioctl(struct net_device *dev, + struct ifreq *ifr, int cmd) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct phy_device *phydev = ether->phy_dev; + + if (!netif_running(dev)) + return -EINVAL; + + if (!phydev) + return -ENODEV; + + return phy_mii_ioctl(phydev, ifr, cmd); +} + +static void npcm7xx_get_drvinfo(struct net_device *dev, + struct ethtool_drvinfo *info) +{ + strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); + strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); + strlcpy(info->fw_version, "N/A", sizeof(info->fw_version)); + strlcpy(info->bus_info, "N/A", sizeof(info->bus_info)); +} + +static int npcm7xx_get_settings(struct net_device *dev, + struct ethtool_link_ksettings *cmd) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct phy_device *phydev = ether->phy_dev; + + if (!phydev) + return -ENODEV; + + dev_info(ðer->pdev->dev, "\n\nnpcm7xx_get_settings\n"); + phy_ethtool_ksettings_get(phydev, cmd); + + return 0; +} + +static int npcm7xx_set_settings(struct net_device *dev, + const struct ethtool_link_ksettings *cmd) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct phy_device *phydev = ether->phy_dev; + int ret; + + if (!phydev) + return -ENODEV; + + dev_info(ðer->pdev->dev, "\n\nnpcm7xx_set_settings\n"); + ret = phy_ethtool_ksettings_set(phydev, cmd); + + return ret; +} + +static u32 npcm7xx_get_msglevel(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + + return ether->msg_enable; +} + +static void npcm7xx_set_msglevel(struct net_device *dev, u32 level) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + + ether->msg_enable = level; +} + +static const struct ethtool_ops npcm7xx_ether_ethtool_ops = { + .get_link_ksettings = npcm7xx_get_settings, + .set_link_ksettings = npcm7xx_set_settings, + .get_drvinfo = npcm7xx_get_drvinfo, + .get_msglevel = npcm7xx_get_msglevel, + .set_msglevel = npcm7xx_set_msglevel, + .get_link = ethtool_op_get_link, +}; + +static const struct net_device_ops npcm7xx_ether_netdev_ops = { + .ndo_open = npcm7xx_ether_open, + .ndo_stop = npcm7xx_ether_close, + .ndo_start_xmit = npcm7xx_ether_start_xmit, + .ndo_get_stats = npcm7xx_ether_stats, + .ndo_set_rx_mode = npcm7xx_ether_set_rx_mode, + .ndo_set_mac_address = npcm7xx_set_mac_address, + .ndo_do_ioctl = npcm7xx_ether_ioctl, + .ndo_validate_addr = eth_validate_addr, + .ndo_change_mtu = eth_change_mtu, +}; + +static void get_mac_address(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct platform_device *pdev = ether->pdev; + struct device_node *np = ether->pdev->dev.of_node; + const u8 *mac_address = NULL; + + mac_address = of_get_mac_address(np); + + if (mac_address != 0) + ether_addr_copy(dev->dev_addr, mac_address); + + if (is_valid_ether_addr(dev->dev_addr)) { + dev_info(&pdev->dev, "%s: device MAC address : %pM\n", + pdev->name, dev->dev_addr); + } else { + eth_hw_addr_random(dev); + dev_info(&pdev->dev, "%s: device MAC address (random generator) %pM\n", + dev->name, dev->dev_addr); + } +} + +static int npcm7xx_mii_setup(struct net_device *dev) +{ + struct npcm7xx_ether *ether = netdev_priv(dev); + struct platform_device *pdev; + struct phy_device *phydev = NULL; + int i, err = 0; + + pdev = ether->pdev; + + ether->mii_bus = mdiobus_alloc(); + if (!ether->mii_bus) { + err = -ENOMEM; + dev_err(&pdev->dev, "mdiobus_alloc() failed\n"); + goto out0; + } + + ether->mii_bus->name = "npcm7xx_rmii"; + ether->mii_bus->read = &npcm7xx_mdio_read; + ether->mii_bus->write = &npcm7xx_mdio_write; + ether->mii_bus->reset = &npcm7xx_mdio_reset; + snprintf(ether->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + ether->pdev->name, ether->pdev->id); + dev_dbg(&pdev->dev, "%s ether->mii_bus->id=%s\n", __func__, + ether->mii_bus->id); + ether->mii_bus->priv = ether; + ether->mii_bus->parent = ðer->pdev->dev; + + for (i = 0; i < PHY_MAX_ADDR; i++) + ether->mii_bus->irq[i] = PHY_POLL; + + platform_set_drvdata(ether->pdev, ether->mii_bus); + + /* Enable MDIO Clock */ + writel(readl((ether->reg + REG_MCMDR)) | MCMDR_ENMDC, + (ether->reg + REG_MCMDR)); + + if (mdiobus_register(ether->mii_bus)) { + dev_err(&pdev->dev, "mdiobus_register() failed\n"); + goto out2; + } + + phydev = phy_find_first(ether->mii_bus); + if (!phydev) { + dev_err(&pdev->dev, "phy_find_first() failed\n"); + goto out3; + } + + dev_info(&pdev->dev, " name = %s ETH-Phy-Id = 0x%x\n", + phydev_name(phydev), phydev->phy_id); + + phydev = phy_connect(dev, phydev_name(phydev), + &adjust_link, + PHY_INTERFACE_MODE_RMII); + + dev_info(&pdev->dev, " ETH-Phy-Id = 0x%x name = %s\n", + phydev->phy_id, phydev->drv->name); + + if (IS_ERR(phydev)) { + err = PTR_ERR(phydev); + dev_err(&pdev->dev, "phy_connect() failed - %d\n", err); + goto out3; + } + + linkmode_and(phydev->supported, phydev->supported, PHY_BASIC_FEATURES); + linkmode_copy(phydev->advertising, phydev->supported); + ether->phy_dev = phydev; + + return 0; + +out3: + mdiobus_unregister(ether->mii_bus); +out2: + kfree(ether->mii_bus->irq); + mdiobus_free(ether->mii_bus); +out0: + + return err; +} + +static const struct of_device_id emc_dt_id[] = { + { .compatible = "nuvoton,npcm750-emc", }, + {}, +}; +MODULE_DEVICE_TABLE(of, emc_dt_id); + +static void npcm7xx_ncsi_handler(struct ncsi_dev *nd) +{ + if (unlikely(nd->state != ncsi_dev_state_functional)) + return; + + netdev_info(nd->dev, "NCSI interface %s\n", + nd->link_up ? "up" : "down"); +} + +static int npcm7xx_ether_probe(struct platform_device *pdev) +{ + struct npcm7xx_ether *ether; + struct net_device *dev; + int error; + + struct clk *emc_clk = NULL; + struct device_node *np = pdev->dev.of_node; + + pdev->id = of_alias_get_id(np, "ethernet"); + if (pdev->id < 0) + pdev->id = 0; + + emc_clk = devm_clk_get(&pdev->dev, NULL); + + if (IS_ERR(emc_clk)) + return PTR_ERR(emc_clk); + + /* Enable Clock */ + clk_prepare_enable(emc_clk); + + error = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); + if (error) + return -ENODEV; + + dev = alloc_etherdev(sizeof(struct npcm7xx_ether)); + if (!dev) + return -ENOMEM; + + ether = netdev_priv(dev); + + ether->rst_regmap = + syscon_regmap_lookup_by_compatible("nuvoton,npcm750-rst"); + if (IS_ERR(ether->rst_regmap)) { + dev_err(&pdev->dev, "%s: failed to find nuvoton,npcm750-rst\n", __func__); + return IS_ERR(ether->rst_regmap); + } + + /* Reset EMC module */ + if (pdev->id == 0) { + regmap_update_bits(ether->rst_regmap, IPSRST1_OFFSET, + (0x1 << 6), (0x1 << 6)); + regmap_update_bits(ether->rst_regmap, IPSRST1_OFFSET, + (0x1 << 6), 0); + } + if (pdev->id == 1) { + regmap_update_bits(ether->rst_regmap, IPSRST1_OFFSET, + (0x1 << 21), (0x1 << 21)); + regmap_update_bits(ether->rst_regmap, IPSRST1_OFFSET, + (0x1 << 21), 0); + } + + ether->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!ether->res) { + dev_err(&pdev->dev, "failed to get I/O memory\n"); + error = -ENXIO; + goto failed_free; + } + + if (!request_mem_region(ether->res->start, + resource_size(ether->res), pdev->name)) { + dev_err(&pdev->dev, "failed to request I/O memory\n"); + error = -EBUSY; + goto failed_free; + } + + ether->reg = ioremap(ether->res->start, resource_size(ether->res)); + dev_dbg(&pdev->dev, "%s ether->reg = 0x%x\n", __func__, + (unsigned int)ether->reg); + + if (!ether->reg) { + dev_err(&pdev->dev, "failed to remap I/O memory\n"); + error = -ENXIO; + goto failed_free_mem; + } + + ether->txirq = platform_get_irq(pdev, 0); + if (ether->txirq < 0) { + dev_err(&pdev->dev, "failed to get ether tx irq\n"); + error = -ENXIO; + goto failed_free_io; + } + + ether->rxirq = platform_get_irq(pdev, 1); + if (ether->rxirq < 0) { + dev_err(&pdev->dev, "failed to get ether rx irq\n"); + error = -ENXIO; + goto failed_free_io; + } + + SET_NETDEV_DEV(dev, &pdev->dev); + platform_set_drvdata(pdev, dev); + ether->ndev = dev; + + ether->pdev = pdev; + ether->msg_enable = NETIF_MSG_LINK; + + dev->netdev_ops = &npcm7xx_ether_netdev_ops; + dev->ethtool_ops = &npcm7xx_ether_ethtool_ops; + + dev->tx_queue_len = TX_QUEUE_LEN; + dev->dma = 0x0; + dev->watchdog_timeo = TX_TIMEOUT; + + get_mac_address(dev); + + ether->cur_tx = 0x0; + ether->cur_rx = 0x0; + ether->finish_tx = 0x0; + ether->pending_tx = 0x0; + ether->link = 0; + ether->speed = 100; + ether->duplex = DUPLEX_FULL; + ether->need_reset = 0; + ether->dump_buf = NULL; + ether->rx_berr = 0; + ether->rx_err = 0; + ether->rdu = 0; + ether->rxov = 0; + ether->rx_stuck = 0; + /* debug counters */ + ether->max_waiting_rx = 0; + ether->rx_count_pool = 0; + ether->count_xmit = 0; + ether->rx_int_count = 0; + ether->rx_err_count = 0; + ether->tx_int_count = 0; + ether->count_finish = 0; + ether->tx_tdu = 0; + ether->tx_tdu_i = 0; + ether->tx_cp_i = 0; + + spin_lock_init(ðer->lock); + + netif_napi_add(dev, ðer->napi, npcm7xx_poll, RX_POLL_SIZE); + + if (pdev->dev.of_node && + of_get_property(pdev->dev.of_node, "use-ncsi", NULL)) { + if (!IS_ENABLED(CONFIG_NET_NCSI)) { + dev_err(&pdev->dev, "CONFIG_NET_NCSI not enabled\n"); + error = -ENODEV; + goto failed_free_napi; + } + dev_info(&pdev->dev, "Using NCSI interface\n"); + ether->use_ncsi = true; + ether->ncsidev = ncsi_register_dev(dev, npcm7xx_ncsi_handler); + if (!ether->ncsidev) { + error = -ENODEV; + goto failed_free_napi; + } + } else { + ether->use_ncsi = false; + error = npcm7xx_mii_setup(dev); + if (error < 0) { + dev_err(&pdev->dev, "npcm7xx_mii_setup err\n"); + goto failed_free_napi; + } + } + + error = register_netdev(dev); + if (error != 0) { + dev_err(&pdev->dev, "register_netdev() failed\n"); + error = -ENODEV; + goto failed_free_napi; + } + +#ifdef CONFIG_DEBUG_FS + npcm7xx_debug_fs(ether); +#endif + + return 0; + +failed_free_napi: + netif_napi_del(ðer->napi); + platform_set_drvdata(pdev, NULL); +failed_free_io: + iounmap(ether->reg); +failed_free_mem: + release_mem_region(ether->res->start, resource_size(ether->res)); +failed_free: + free_netdev(dev); + + return error; +} + +static int npcm7xx_ether_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct npcm7xx_ether *ether = netdev_priv(dev); + +#ifdef CONFIG_DEBUG_FS + debugfs_remove_recursive(ether->dbgfs_dir); +#endif + + unregister_netdev(dev); + + free_irq(ether->txirq, dev); + free_irq(ether->rxirq, dev); + + if (ether->phy_dev) + phy_disconnect(ether->phy_dev); + + mdiobus_unregister(ether->mii_bus); + kfree(ether->mii_bus->irq); + mdiobus_free(ether->mii_bus); + + platform_set_drvdata(pdev, NULL); + + free_netdev(dev); + return 0; +} + +static struct platform_driver npcm7xx_ether_driver = { + .probe = npcm7xx_ether_probe, + .remove = npcm7xx_ether_remove, + .driver = { + .name = DRV_MODULE_NAME, + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(emc_dt_id), + }, +}; + +module_platform_driver(npcm7xx_ether_driver); + +MODULE_AUTHOR("Nuvoton Technology Corp."); +MODULE_DESCRIPTION("NPCM750 EMC driver"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:npcm750-emc"); +MODULE_VERSION(DRV_MODULE_VERSION); diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 20f14c5fbb7e..206d8650ee7f 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -21,6 +21,19 @@ config MDIO_BUS if MDIO_BUS +config MDIO_ASPEED + tristate "ASPEED MDIO bus controller" + depends on ARCH_ASPEED || COMPILE_TEST + depends on OF_MDIO && HAS_IOMEM + help + This module provides a driver for the independent MDIO bus + controllers found in the ASPEED AST2600 SoC. This is a driver for the + third revision of the ASPEED MDIO register interface - the first two + revisions are the "old" and "new" interfaces found in the AST2400 and + AST2500, embedded in the MAC. For legacy reasons, FTGMAC100 driver + continues to drive the embedded MDIO controller for the AST2400 and + AST2500 SoCs, so say N if AST2600 support is not required. + config MDIO_BCM_IPROC tristate "Broadcom iProc MDIO bus controller" depends on ARCH_BCM_IPROC || COMPILE_TEST diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 839acb292c38..ba07c27e4208 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -22,6 +22,7 @@ libphy-$(CONFIG_LED_TRIGGER_PHY) += phy_led_triggers.o obj-$(CONFIG_PHYLINK) += phylink.o obj-$(CONFIG_PHYLIB) += libphy.o +obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o diff --git a/drivers/net/phy/mdio-aspeed.c b/drivers/net/phy/mdio-aspeed.c new file mode 100644 index 000000000000..cad820568f75 --- /dev/null +++ b/drivers/net/phy/mdio-aspeed.c @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2019 IBM Corp. */ + +#include <linux/bitfield.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <linux/mdio.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_mdio.h> +#include <linux/phy.h> +#include <linux/platform_device.h> + +#define DRV_NAME "mdio-aspeed" + +#define ASPEED_MDIO_CTRL 0x0 +#define ASPEED_MDIO_CTRL_FIRE BIT(31) +#define ASPEED_MDIO_CTRL_ST BIT(28) +#define ASPEED_MDIO_CTRL_ST_C45 0 +#define ASPEED_MDIO_CTRL_ST_C22 1 +#define ASPEED_MDIO_CTRL_OP GENMASK(27, 26) +#define MDIO_C22_OP_WRITE 0b01 +#define MDIO_C22_OP_READ 0b10 +#define ASPEED_MDIO_CTRL_PHYAD GENMASK(25, 21) +#define ASPEED_MDIO_CTRL_REGAD GENMASK(20, 16) +#define ASPEED_MDIO_CTRL_MIIWDATA GENMASK(15, 0) + +#define ASPEED_MDIO_DATA 0x4 +#define ASPEED_MDIO_DATA_MDC_THRES GENMASK(31, 24) +#define ASPEED_MDIO_DATA_MDIO_EDGE BIT(23) +#define ASPEED_MDIO_DATA_MDIO_LATCH GENMASK(22, 20) +#define ASPEED_MDIO_DATA_IDLE BIT(16) +#define ASPEED_MDIO_DATA_MIIRDATA GENMASK(15, 0) + +#define ASPEED_MDIO_INTERVAL_US 100 +#define ASPEED_MDIO_TIMEOUT_US (ASPEED_MDIO_INTERVAL_US * 10) + +struct aspeed_mdio { + void __iomem *base; +}; + +static int aspeed_mdio_read(struct mii_bus *bus, int addr, int regnum) +{ + struct aspeed_mdio *ctx = bus->priv; + u32 ctrl; + u32 data; + int rc; + + dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d\n", __func__, addr, + regnum); + + /* Just clause 22 for the moment */ + if (regnum & MII_ADDR_C45) + return -EOPNOTSUPP; + + ctrl = ASPEED_MDIO_CTRL_FIRE + | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) + | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_READ) + | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) + | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regnum); + + iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL); + + rc = readl_poll_timeout(ctx->base + ASPEED_MDIO_DATA, data, + data & ASPEED_MDIO_DATA_IDLE, + ASPEED_MDIO_INTERVAL_US, + ASPEED_MDIO_TIMEOUT_US); + if (rc < 0) + return rc; + + return FIELD_GET(ASPEED_MDIO_DATA_MIIRDATA, data); +} + +static int aspeed_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val) +{ + struct aspeed_mdio *ctx = bus->priv; + u32 ctrl; + + dev_dbg(&bus->dev, "%s: addr: %d, regnum: %d, val: 0x%x\n", + __func__, addr, regnum, val); + + /* Just clause 22 for the moment */ + if (regnum & MII_ADDR_C45) + return -EOPNOTSUPP; + + ctrl = ASPEED_MDIO_CTRL_FIRE + | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) + | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_WRITE) + | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) + | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regnum) + | FIELD_PREP(ASPEED_MDIO_CTRL_MIIWDATA, val); + + iowrite32(ctrl, ctx->base + ASPEED_MDIO_CTRL); + + return readl_poll_timeout(ctx->base + ASPEED_MDIO_CTRL, ctrl, + !(ctrl & ASPEED_MDIO_CTRL_FIRE), + ASPEED_MDIO_INTERVAL_US, + ASPEED_MDIO_TIMEOUT_US); +} + +static int aspeed_mdio_probe(struct platform_device *pdev) +{ + struct aspeed_mdio *ctx; + struct mii_bus *bus; + int rc; + + bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*ctx)); + if (!bus) + return -ENOMEM; + + ctx = bus->priv; + ctx->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ctx->base)) + return PTR_ERR(ctx->base); + + bus->name = DRV_NAME; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id); + bus->parent = &pdev->dev; + bus->read = aspeed_mdio_read; + bus->write = aspeed_mdio_write; + + rc = of_mdiobus_register(bus, pdev->dev.of_node); + if (rc) { + dev_err(&pdev->dev, "Cannot register MDIO bus!\n"); + return rc; + } + + platform_set_drvdata(pdev, bus); + + return 0; +} + +static int aspeed_mdio_remove(struct platform_device *pdev) +{ + mdiobus_unregister(platform_get_drvdata(pdev)); + + return 0; +} + +static const struct of_device_id aspeed_mdio_of_match[] = { + { .compatible = "aspeed,ast2600-mdio", }, + { }, +}; + +static struct platform_driver aspeed_mdio_driver = { + .driver = { + .name = DRV_NAME, + .of_match_table = aspeed_mdio_of_match, + }, + .probe = aspeed_mdio_probe, + .remove = aspeed_mdio_remove, +}; + +module_platform_driver(aspeed_mdio_driver); + +MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/peci/Kconfig b/drivers/peci/Kconfig new file mode 100644 index 000000000000..7293108fb543 --- /dev/null +++ b/drivers/peci/Kconfig @@ -0,0 +1,50 @@ +# +# Platform Environment Control Interface (PECI) subsystem configuration +# + +config PECI + bool "PECI support" + select RT_MUTEXES + select CRC8 + help + The Platform Environment Control Interface (PECI) is a one-wire bus + interface that provides a communication channel from Intel processors + and chipset components to external monitoring or control devices. + + If you want PECI support, you should say Y here and also to the + specific driver for your bus adapter(s) below. + +if PECI + +# +# PECI hardware bus configuration +# + +menu "PECI Hardware Bus support" + +config PECI_ASPEED + tristate "ASPEED PECI support" + select REGMAP_MMIO + depends on OF + depends on ARCH_ASPEED || COMPILE_TEST + help + Say Y here if you want support for the Platform Environment Control + Interface (PECI) bus adapter driver on the ASPEED SoCs. + + This support is also available as a module. If so, the module + will be called peci-aspeed. + +config PECI_NPCM + tristate "Nuvoton NPCM PECI support" + select REGMAP_MMIO + depends on OF + depends on ARCH_NPCM || COMPILE_TEST + help + Say Y here if you want support for the Platform Environment Control + Interface (PECI) bus adapter driver on the Nuvoton NPCM SoCs. + + This support is also available as a module. If so, the module + will be called peci-npcm. +endmenu + +endif # PECI diff --git a/drivers/peci/Makefile b/drivers/peci/Makefile new file mode 100644 index 000000000000..3326da54a21a --- /dev/null +++ b/drivers/peci/Makefile @@ -0,0 +1,10 @@ +# +# Makefile for the PECI core and bus drivers. +# + +# Core functionality +obj-$(CONFIG_PECI) += peci-core.o + +# Hardware specific bus drivers +obj-$(CONFIG_PECI_ASPEED) += peci-aspeed.o +obj-$(CONFIG_PECI_NPCM) += peci-npcm.o diff --git a/drivers/peci/peci-aspeed.c b/drivers/peci/peci-aspeed.c new file mode 100644 index 000000000000..51cb2563ceb6 --- /dev/null +++ b/drivers/peci/peci-aspeed.c @@ -0,0 +1,505 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2012-2017 ASPEED Technology Inc. +// Copyright (c) 2018 Intel Corporation + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/jiffies.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/peci.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset.h> + +/* ASPEED PECI Registers */ +#define ASPEED_PECI_CTRL 0x00 +#define ASPEED_PECI_TIMING 0x04 +#define ASPEED_PECI_CMD 0x08 +#define ASPEED_PECI_CMD_CTRL 0x0c +#define ASPEED_PECI_EXP_FCS 0x10 +#define ASPEED_PECI_CAP_FCS 0x14 +#define ASPEED_PECI_INT_CTRL 0x18 +#define ASPEED_PECI_INT_STS 0x1c +#define ASPEED_PECI_W_DATA0 0x20 +#define ASPEED_PECI_W_DATA1 0x24 +#define ASPEED_PECI_W_DATA2 0x28 +#define ASPEED_PECI_W_DATA3 0x2c +#define ASPEED_PECI_R_DATA0 0x30 +#define ASPEED_PECI_R_DATA1 0x34 +#define ASPEED_PECI_R_DATA2 0x38 +#define ASPEED_PECI_R_DATA3 0x3c +#define ASPEED_PECI_W_DATA4 0x40 +#define ASPEED_PECI_W_DATA5 0x44 +#define ASPEED_PECI_W_DATA6 0x48 +#define ASPEED_PECI_W_DATA7 0x4c +#define ASPEED_PECI_R_DATA4 0x50 +#define ASPEED_PECI_R_DATA5 0x54 +#define ASPEED_PECI_R_DATA6 0x58 +#define ASPEED_PECI_R_DATA7 0x5c + +/* ASPEED_PECI_CTRL - 0x00 : Control Register */ +#define PECI_CTRL_SAMPLING_MASK GENMASK(19, 16) +#define PECI_CTRL_READ_MODE_MASK GENMASK(13, 12) +#define PECI_CTRL_READ_MODE_COUNT BIT(12) +#define PECI_CTRL_READ_MODE_DBG BIT(13) +#define PECI_CTRL_CLK_SOURCE_MASK BIT(11) +#define PECI_CTRL_CLK_DIV_MASK GENMASK(10, 8) +#define PECI_CTRL_INVERT_OUT BIT(7) +#define PECI_CTRL_INVERT_IN BIT(6) +#define PECI_CTRL_BUS_CONTENT_EN BIT(5) +#define PECI_CTRL_PECI_EN BIT(4) +#define PECI_CTRL_PECI_CLK_EN BIT(0) + +/* ASPEED_PECI_TIMING - 0x04 : Timing Negotiation Register */ +#define PECI_TIMING_MESSAGE_MASK GENMASK(15, 8) +#define PECI_TIMING_ADDRESS_MASK GENMASK(7, 0) + +/* ASPEED_PECI_CMD - 0x08 : Command Register */ +#define PECI_CMD_PIN_MON BIT(31) +#define PECI_CMD_STS_MASK GENMASK(27, 24) +#define PECI_CMD_IDLE_MASK (PECI_CMD_STS_MASK | PECI_CMD_PIN_MON) +#define PECI_CMD_FIRE BIT(0) + +/* ASPEED_PECI_LEN - 0x0C : Read/Write Length Register */ +#define PECI_AW_FCS_EN BIT(31) +#define PECI_READ_LEN_MASK GENMASK(23, 16) +#define PECI_WRITE_LEN_MASK GENMASK(15, 8) +#define PECI_TAGET_ADDR_MASK GENMASK(7, 0) + +/* ASPEED_PECI_EXP_FCS - 0x10 : Expected FCS Data Register */ +#define PECI_EXPECT_READ_FCS_MASK GENMASK(23, 16) +#define PECI_EXPECT_AW_FCS_AUTO_MASK GENMASK(15, 8) +#define PECI_EXPECT_WRITE_FCS_MASK GENMASK(7, 0) + +/* ASPEED_PECI_CAP_FCS - 0x14 : Captured FCS Data Register */ +#define PECI_CAPTURE_READ_FCS_MASK GENMASK(23, 16) +#define PECI_CAPTURE_WRITE_FCS_MASK GENMASK(7, 0) + +/* ASPEED_PECI_INT_CTRL/STS - 0x18/0x1c : Interrupt Register */ +#define PECI_INT_TIMING_RESULT_MASK GENMASK(31, 30) +#define PECI_INT_TIMEOUT BIT(4) +#define PECI_INT_CONNECT BIT(3) +#define PECI_INT_W_FCS_BAD BIT(2) +#define PECI_INT_W_FCS_ABORT BIT(1) +#define PECI_INT_CMD_DONE BIT(0) + +#define PECI_INT_MASK (PECI_INT_TIMEOUT | PECI_INT_CONNECT | \ + PECI_INT_W_FCS_BAD | PECI_INT_W_FCS_ABORT | \ + PECI_INT_CMD_DONE) + +#define PECI_IDLE_CHECK_TIMEOUT_USEC 50000 +#define PECI_IDLE_CHECK_INTERVAL_USEC 10000 + +#define PECI_RD_SAMPLING_POINT_DEFAULT 8 +#define PECI_RD_SAMPLING_POINT_MAX 15 +#define PECI_CLK_DIV_DEFAULT 0 +#define PECI_CLK_DIV_MAX 7 +#define PECI_MSG_TIMING_DEFAULT 1 +#define PECI_MSG_TIMING_MAX 255 +#define PECI_ADDR_TIMING_DEFAULT 1 +#define PECI_ADDR_TIMING_MAX 255 +#define PECI_CMD_TIMEOUT_MS_DEFAULT 1000 +#define PECI_CMD_TIMEOUT_MS_MAX 60000 + +struct aspeed_peci { + struct peci_adapter *adapter; + struct device *dev; + struct regmap *regmap; + struct clk *clk; + struct reset_control *rst; + int irq; + spinlock_t lock; /* to sync completion status handling */ + struct completion xfer_complete; + u32 status; + u32 cmd_timeout_ms; +}; + +static int aspeed_peci_xfer_native(struct aspeed_peci *priv, + struct peci_xfer_msg *msg) +{ + long err, timeout = msecs_to_jiffies(priv->cmd_timeout_ms); + u32 peci_head, peci_state, rx_data, cmd_sts; + unsigned long flags; + int i, rc; + uint reg; + + /* Check command sts and bus idle state */ + rc = regmap_read_poll_timeout(priv->regmap, ASPEED_PECI_CMD, cmd_sts, + !(cmd_sts & PECI_CMD_IDLE_MASK), + PECI_IDLE_CHECK_INTERVAL_USEC, + PECI_IDLE_CHECK_TIMEOUT_USEC); + if (rc) + return rc; /* -ETIMEDOUT */ + + spin_lock_irqsave(&priv->lock, flags); + reinit_completion(&priv->xfer_complete); + + peci_head = FIELD_PREP(PECI_TAGET_ADDR_MASK, msg->addr) | + FIELD_PREP(PECI_WRITE_LEN_MASK, msg->tx_len) | + FIELD_PREP(PECI_READ_LEN_MASK, msg->rx_len); + + regmap_write(priv->regmap, ASPEED_PECI_CMD_CTRL, peci_head); + + for (i = 0; i < msg->tx_len; i += 4) { + reg = i < 16 ? ASPEED_PECI_W_DATA0 + i % 16 : + ASPEED_PECI_W_DATA4 + i % 16; + regmap_write(priv->regmap, reg, + le32_to_cpup((__le32 *)&msg->tx_buf[i])); + } + + dev_dbg(priv->dev, "HEAD : 0x%08x\n", peci_head); + print_hex_dump_debug("TX : ", DUMP_PREFIX_NONE, 16, 1, + msg->tx_buf, msg->tx_len, true); + + priv->status = 0; + regmap_write(priv->regmap, ASPEED_PECI_CMD, PECI_CMD_FIRE); + spin_unlock_irqrestore(&priv->lock, flags); + + err = wait_for_completion_interruptible_timeout(&priv->xfer_complete, + timeout); + + spin_lock_irqsave(&priv->lock, flags); + dev_dbg(priv->dev, "INT_STS : 0x%08x\n", priv->status); + regmap_read(priv->regmap, ASPEED_PECI_CMD, &peci_state); + dev_dbg(priv->dev, "PECI_STATE : 0x%lx\n", + FIELD_GET(PECI_CMD_STS_MASK, peci_state)); + + regmap_write(priv->regmap, ASPEED_PECI_CMD, 0); + + if (err <= 0 || priv->status != PECI_INT_CMD_DONE) { + if (err < 0) { /* -ERESTARTSYS */ + rc = (int)err; + goto err_irqrestore; + } else if (err == 0) { + dev_dbg(priv->dev, "Timeout waiting for a response!\n"); + rc = -ETIMEDOUT; + goto err_irqrestore; + } + + dev_dbg(priv->dev, "No valid response!\n"); + rc = -EIO; + goto err_irqrestore; + } + + /** + * Note that rx_len and rx_buf size can be an odd number. + * Byte handling is more efficient. + */ + for (i = 0; i < msg->rx_len; i++) { + u8 byte_offset = i % 4; + + if (byte_offset == 0) { + reg = i < 16 ? ASPEED_PECI_R_DATA0 + i % 16 : + ASPEED_PECI_R_DATA4 + i % 16; + regmap_read(priv->regmap, reg, &rx_data); + } + + msg->rx_buf[i] = (u8)(rx_data >> (byte_offset << 3)); + } + + print_hex_dump_debug("RX : ", DUMP_PREFIX_NONE, 16, 1, + msg->rx_buf, msg->rx_len, true); + + regmap_read(priv->regmap, ASPEED_PECI_CMD, &peci_state); + dev_dbg(priv->dev, "PECI_STATE : 0x%lx\n", + FIELD_GET(PECI_CMD_STS_MASK, peci_state)); + dev_dbg(priv->dev, "------------------------\n"); + +err_irqrestore: + spin_unlock_irqrestore(&priv->lock, flags); + return rc; +} + +static irqreturn_t aspeed_peci_irq_handler(int irq, void *arg) +{ + struct aspeed_peci *priv = arg; + u32 status_ack = 0; + u32 status; + + spin_lock(&priv->lock); + regmap_read(priv->regmap, ASPEED_PECI_INT_STS, &status); + priv->status |= (status & PECI_INT_MASK); + + /** + * In most cases, interrupt bits will be set one by one but also note + * that multiple interrupt bits could be set at the same time. + */ + if (status & PECI_INT_TIMEOUT) { + dev_dbg(priv->dev, "PECI_INT_TIMEOUT\n"); + status_ack |= PECI_INT_TIMEOUT; + } + + if (status & PECI_INT_CONNECT) { + dev_dbg(priv->dev, "PECI_INT_CONNECT\n"); + status_ack |= PECI_INT_CONNECT; + } + + if (status & PECI_INT_W_FCS_BAD) { + dev_dbg(priv->dev, "PECI_INT_W_FCS_BAD\n"); + status_ack |= PECI_INT_W_FCS_BAD; + } + + if (status & PECI_INT_W_FCS_ABORT) { + dev_dbg(priv->dev, "PECI_INT_W_FCS_ABORT\n"); + status_ack |= PECI_INT_W_FCS_ABORT; + } + + /** + * All commands should be ended up with a PECI_INT_CMD_DONE bit set + * even in an error case. + */ + if (status & PECI_INT_CMD_DONE) { + dev_dbg(priv->dev, "PECI_INT_CMD_DONE\n"); + status_ack |= PECI_INT_CMD_DONE; + complete(&priv->xfer_complete); + } + + regmap_write(priv->regmap, ASPEED_PECI_INT_STS, status_ack); + spin_unlock(&priv->lock); + return IRQ_HANDLED; +} + +static int aspeed_peci_init_ctrl(struct aspeed_peci *priv) +{ + u32 msg_timing, addr_timing, rd_sampling_point; + u32 clk_freq, clk_divisor, clk_div_val = 0; + int ret; + + priv->clk = devm_clk_get(priv->dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(priv->dev, "Failed to get clk source.\n"); + return PTR_ERR(priv->clk); + } + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(priv->dev, "Failed to enable clock.\n"); + return ret; + } + + ret = of_property_read_u32(priv->dev->of_node, "clock-frequency", + &clk_freq); + if (ret) { + dev_err(priv->dev, + "Could not read clock-frequency property.\n"); + clk_disable_unprepare(priv->clk); + return ret; + } + + clk_divisor = clk_get_rate(priv->clk) / clk_freq; + + while ((clk_divisor >> 1) && (clk_div_val < PECI_CLK_DIV_MAX)) + clk_div_val++; + + ret = of_property_read_u32(priv->dev->of_node, "msg-timing", + &msg_timing); + if (ret || msg_timing > PECI_MSG_TIMING_MAX) { + if (!ret) + dev_warn(priv->dev, + "Invalid msg-timing : %u, Use default : %u\n", + msg_timing, PECI_MSG_TIMING_DEFAULT); + msg_timing = PECI_MSG_TIMING_DEFAULT; + } + + ret = of_property_read_u32(priv->dev->of_node, "addr-timing", + &addr_timing); + if (ret || addr_timing > PECI_ADDR_TIMING_MAX) { + if (!ret) + dev_warn(priv->dev, + "Invalid addr-timing : %u, Use default : %u\n", + addr_timing, PECI_ADDR_TIMING_DEFAULT); + addr_timing = PECI_ADDR_TIMING_DEFAULT; + } + + ret = of_property_read_u32(priv->dev->of_node, "rd-sampling-point", + &rd_sampling_point); + if (ret || rd_sampling_point > PECI_RD_SAMPLING_POINT_MAX) { + if (!ret) + dev_warn(priv->dev, + "Invalid rd-sampling-point : %u. Use default : %u\n", + rd_sampling_point, + PECI_RD_SAMPLING_POINT_DEFAULT); + rd_sampling_point = PECI_RD_SAMPLING_POINT_DEFAULT; + } + + ret = of_property_read_u32(priv->dev->of_node, "cmd-timeout-ms", + &priv->cmd_timeout_ms); + if (ret || priv->cmd_timeout_ms > PECI_CMD_TIMEOUT_MS_MAX || + priv->cmd_timeout_ms == 0) { + if (!ret) + dev_warn(priv->dev, + "Invalid cmd-timeout-ms : %u. Use default : %u\n", + priv->cmd_timeout_ms, + PECI_CMD_TIMEOUT_MS_DEFAULT); + priv->cmd_timeout_ms = PECI_CMD_TIMEOUT_MS_DEFAULT; + } + + regmap_write(priv->regmap, ASPEED_PECI_CTRL, + FIELD_PREP(PECI_CTRL_CLK_DIV_MASK, PECI_CLK_DIV_DEFAULT) | + PECI_CTRL_PECI_CLK_EN); + + /** + * Timing negotiation period setting. + * The unit of the programmed value is 4 times of PECI clock period. + */ + regmap_write(priv->regmap, ASPEED_PECI_TIMING, + FIELD_PREP(PECI_TIMING_MESSAGE_MASK, msg_timing) | + FIELD_PREP(PECI_TIMING_ADDRESS_MASK, addr_timing)); + + /* Clear interrupts */ + regmap_write(priv->regmap, ASPEED_PECI_INT_STS, PECI_INT_MASK); + + /* Enable interrupts */ + regmap_write(priv->regmap, ASPEED_PECI_INT_CTRL, PECI_INT_MASK); + + /* Read sampling point and clock speed setting */ + regmap_write(priv->regmap, ASPEED_PECI_CTRL, + FIELD_PREP(PECI_CTRL_SAMPLING_MASK, rd_sampling_point) | + FIELD_PREP(PECI_CTRL_CLK_DIV_MASK, clk_div_val) | + PECI_CTRL_PECI_EN | PECI_CTRL_PECI_CLK_EN); + + return 0; +} + +static const struct regmap_config aspeed_peci_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = ASPEED_PECI_R_DATA7, + .val_format_endian = REGMAP_ENDIAN_LITTLE, + .fast_io = true, +}; + +static int aspeed_peci_xfer(struct peci_adapter *adapter, + struct peci_xfer_msg *msg) +{ + struct aspeed_peci *priv = peci_get_adapdata(adapter); + + return aspeed_peci_xfer_native(priv, msg); +} + +static int aspeed_peci_probe(struct platform_device *pdev) +{ + struct peci_adapter *adapter; + struct aspeed_peci *priv; + struct resource *res; + void __iomem *base; + u32 cmd_sts; + int ret; + + adapter = peci_alloc_adapter(&pdev->dev, sizeof(*priv)); + if (!adapter) + return -ENOMEM; + + priv = peci_get_adapdata(adapter); + priv->adapter = adapter; + priv->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, priv); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto err_put_adapter_dev; + } + + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &aspeed_peci_regmap_config); + if (IS_ERR(priv->regmap)) { + ret = PTR_ERR(priv->regmap); + goto err_put_adapter_dev; + } + + /** + * We check that the regmap works on this very first access, + * but as this is an MMIO-backed regmap, subsequent regmap + * access is not going to fail and we skip error checks from + * this point. + */ + ret = regmap_read(priv->regmap, ASPEED_PECI_CMD, &cmd_sts); + if (ret) { + ret = -EIO; + goto err_put_adapter_dev; + } + + priv->irq = platform_get_irq(pdev, 0); + if (!priv->irq) { + ret = -ENODEV; + goto err_put_adapter_dev; + } + + ret = devm_request_irq(&pdev->dev, priv->irq, aspeed_peci_irq_handler, + 0, "peci-aspeed-irq", priv); + if (ret) + goto err_put_adapter_dev; + + init_completion(&priv->xfer_complete); + spin_lock_init(&priv->lock); + + priv->adapter->owner = THIS_MODULE; + priv->adapter->dev.of_node = of_node_get(dev_of_node(priv->dev)); + strlcpy(priv->adapter->name, pdev->name, sizeof(priv->adapter->name)); + priv->adapter->xfer = aspeed_peci_xfer; + + priv->rst = devm_reset_control_get(&pdev->dev, NULL); + if (IS_ERR(priv->rst)) { + dev_err(&pdev->dev, + "missing or invalid reset controller entry"); + ret = PTR_ERR(priv->rst); + goto err_put_adapter_dev; + } + reset_control_deassert(priv->rst); + + ret = aspeed_peci_init_ctrl(priv); + if (ret) + goto err_put_adapter_dev; + + ret = peci_add_adapter(priv->adapter); + if (ret) + goto err_put_adapter_dev; + + dev_info(&pdev->dev, "peci bus %d registered, irq %d\n", + priv->adapter->nr, priv->irq); + + return 0; + +err_put_adapter_dev: + put_device(&adapter->dev); + return ret; +} + +static int aspeed_peci_remove(struct platform_device *pdev) +{ + struct aspeed_peci *priv = dev_get_drvdata(&pdev->dev); + + clk_disable_unprepare(priv->clk); + reset_control_assert(priv->rst); + peci_del_adapter(priv->adapter); + of_node_put(priv->adapter->dev.of_node); + + return 0; +} + +static const struct of_device_id aspeed_peci_of_table[] = { + { .compatible = "aspeed,ast2400-peci", }, + { .compatible = "aspeed,ast2500-peci", }, + { } +}; +MODULE_DEVICE_TABLE(of, aspeed_peci_of_table); + +static struct platform_driver aspeed_peci_driver = { + .probe = aspeed_peci_probe, + .remove = aspeed_peci_remove, + .driver = { + .name = "peci-aspeed", + .of_match_table = of_match_ptr(aspeed_peci_of_table), + }, +}; +module_platform_driver(aspeed_peci_driver); + +MODULE_AUTHOR("Ryan Chen <ryan_chen@aspeedtech.com>"); +MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>"); +MODULE_DESCRIPTION("ASPEED PECI driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/peci/peci-core.c b/drivers/peci/peci-core.c new file mode 100644 index 000000000000..6f241469ec7e --- /dev/null +++ b/drivers/peci/peci-core.c @@ -0,0 +1,1527 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Intel Corporation + +#include <linux/bitfield.h> +#include <linux/crc8.h> +#include <linux/delay.h> +#include <linux/fs.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/peci.h> +#include <linux/pm_domain.h> +#include <linux/pm_runtime.h> +#include <linux/slab.h> +#include <linux/uaccess.h> + +/* Mask for getting minor revision number from DIB */ +#define REVISION_NUM_MASK GENMASK(15, 8) + +/* CRC8 table for Assure Write Frame Check */ +#define PECI_CRC8_POLYNOMIAL 0x07 +DECLARE_CRC8_TABLE(peci_crc8_table); + +static struct device_type peci_adapter_type; +static struct device_type peci_client_type; + +/* Max number of peci cdev */ +#define PECI_CDEV_MAX 16 + +static dev_t peci_devt; +static bool is_registered; + +static DEFINE_MUTEX(core_lock); +static DEFINE_IDR(peci_adapter_idr); + +static struct peci_adapter *peci_get_adapter(int nr) +{ + struct peci_adapter *adapter; + + mutex_lock(&core_lock); + adapter = idr_find(&peci_adapter_idr, nr); + if (!adapter) + goto out_unlock; + + if (try_module_get(adapter->owner)) + get_device(&adapter->dev); + else + adapter = NULL; + +out_unlock: + mutex_unlock(&core_lock); + return adapter; +} + +static void peci_put_adapter(struct peci_adapter *adapter) +{ + if (!adapter) + return; + + put_device(&adapter->dev); + module_put(adapter->owner); +} + +static ssize_t name_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return sprintf(buf, "%s\n", dev->type == &peci_client_type ? + to_peci_client(dev)->name : to_peci_adapter(dev)->name); +} +static DEVICE_ATTR_RO(name); + +static void peci_client_dev_release(struct device *dev) +{ + struct peci_client *client = to_peci_client(dev); + + dev_dbg(dev, "%s: %s\n", __func__, client->name); + peci_put_adapter(client->adapter); + kfree(client); +} + +static struct attribute *peci_device_attrs[] = { + &dev_attr_name.attr, + NULL +}; +ATTRIBUTE_GROUPS(peci_device); + +static struct device_type peci_client_type = { + .groups = peci_device_groups, + .release = peci_client_dev_release, +}; + +/** + * peci_verify_client - return parameter as peci_client, or NULL + * @dev: device, probably from some driver model iterator + * + * Return: pointer to peci_client on success, else NULL. + */ +struct peci_client *peci_verify_client(struct device *dev) +{ + return (dev->type == &peci_client_type) + ? to_peci_client(dev) + : NULL; +} +EXPORT_SYMBOL_GPL(peci_verify_client); + +static u8 peci_aw_fcs(u8 *data, int len) +{ + return crc8(peci_crc8_table, data, (size_t)len, 0); +} + +static int __peci_xfer(struct peci_adapter *adapter, struct peci_xfer_msg *msg, + bool do_retry, bool has_aw_fcs) +{ + ktime_t start, end; + s64 elapsed_ms; + int rc = 0; + + /** + * For some commands, the PECI originator may need to retry a command if + * the processor PECI client responds with a 0x8x completion code. In + * each instance, the processor PECI client may have started the + * operation but not completed it yet. When the 'retry' bit is set, the + * PECI client will ignore a new request if it exactly matches a + * previous valid request. + */ + + if (do_retry) + start = ktime_get(); + + do { + rc = adapter->xfer(adapter, msg); + + if (!do_retry || rc) + break; + + if (msg->rx_buf[0] == DEV_PECI_CC_SUCCESS) + break; + + /* Retry is needed when completion code is 0x8x */ + if ((msg->rx_buf[0] & DEV_PECI_CC_RETRY_CHECK_MASK) != + DEV_PECI_CC_NEED_RETRY) { + rc = -EIO; + break; + } + + /* Set the retry bit to indicate a retry attempt */ + msg->tx_buf[1] |= DEV_PECI_RETRY_BIT; + + /* Recalculate the AW FCS if it has one */ + if (has_aw_fcs) + msg->tx_buf[msg->tx_len - 1] = 0x80 ^ + peci_aw_fcs((u8 *)msg, + 2 + msg->tx_len); + + /** + * Retry for at least 250ms before returning an error. + * Retry interval guideline: + * No minimum < Retry Interval < No maximum + * (recommend 10ms) + */ + end = ktime_get(); + elapsed_ms = ktime_to_ms(ktime_sub(end, start)); + if (elapsed_ms >= DEV_PECI_RETRY_TIME_MS) { + dev_dbg(&adapter->dev, "Timeout retrying xfer!\n"); + rc = -ETIMEDOUT; + break; + } + + usleep_range((DEV_PECI_RETRY_INTERVAL_USEC >> 2) + 1, + DEV_PECI_RETRY_INTERVAL_USEC); + } while (true); + + if (rc) + dev_dbg(&adapter->dev, "xfer error, rc: %d\n", rc); + + return rc; +} + +static int peci_xfer(struct peci_adapter *adapter, struct peci_xfer_msg *msg) +{ + return __peci_xfer(adapter, msg, false, false); +} + +static int peci_xfer_with_retries(struct peci_adapter *adapter, + struct peci_xfer_msg *msg, + bool has_aw_fcs) +{ + return __peci_xfer(adapter, msg, true, has_aw_fcs); +} + +static int peci_scan_cmd_mask(struct peci_adapter *adapter) +{ + struct peci_xfer_msg msg; + u8 revision; + int rc = 0; + u64 dib; + + /* Update command mask just once */ + if (adapter->cmd_mask & BIT(PECI_CMD_XFER)) + return 0; + + msg.addr = PECI_BASE_ADDR; + msg.tx_len = GET_DIB_WR_LEN; + msg.rx_len = GET_DIB_RD_LEN; + msg.tx_buf[0] = GET_DIB_PECI_CMD; + + rc = peci_xfer(adapter, &msg); + if (rc) + return rc; + + dib = le64_to_cpup((__le64 *)msg.rx_buf); + + /* Check special case for Get DIB command */ + if (dib == 0) { + dev_dbg(&adapter->dev, "DIB read as 0\n"); + return -EIO; + } + + /** + * Setting up the supporting commands based on minor revision number. + * See PECI Spec Table 3-1. + */ + revision = FIELD_GET(REVISION_NUM_MASK, dib); + if (revision >= 0x36) /* Rev. 3.6 */ + adapter->cmd_mask |= BIT(PECI_CMD_WR_IA_MSR); + if (revision >= 0x35) /* Rev. 3.5 */ + adapter->cmd_mask |= BIT(PECI_CMD_WR_PCI_CFG); + if (revision >= 0x34) /* Rev. 3.4 */ + adapter->cmd_mask |= BIT(PECI_CMD_RD_PCI_CFG); + if (revision >= 0x33) { /* Rev. 3.3 */ + adapter->cmd_mask |= BIT(PECI_CMD_RD_PCI_CFG_LOCAL); + adapter->cmd_mask |= BIT(PECI_CMD_WR_PCI_CFG_LOCAL); + } + if (revision >= 0x32) /* Rev. 3.2 */ + adapter->cmd_mask |= BIT(PECI_CMD_RD_IA_MSR); + if (revision >= 0x31) { /* Rev. 3.1 */ + adapter->cmd_mask |= BIT(PECI_CMD_RD_PKG_CFG); + adapter->cmd_mask |= BIT(PECI_CMD_WR_PKG_CFG); + } + + adapter->cmd_mask |= BIT(PECI_CMD_XFER); + adapter->cmd_mask |= BIT(PECI_CMD_GET_TEMP); + adapter->cmd_mask |= BIT(PECI_CMD_GET_DIB); + adapter->cmd_mask |= BIT(PECI_CMD_PING); + + return rc; +} + +static int peci_cmd_support(struct peci_adapter *adapter, enum peci_cmd cmd) +{ + if (!(adapter->cmd_mask & BIT(PECI_CMD_PING)) && + peci_scan_cmd_mask(adapter) < 0) { + dev_dbg(&adapter->dev, "Failed to scan command mask\n"); + return -EIO; + } + + if (!(adapter->cmd_mask & BIT(cmd))) { + dev_dbg(&adapter->dev, "Command %d is not supported\n", cmd); + return -EINVAL; + } + + return 0; +} + +static int peci_ioctl_xfer(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_xfer_msg *msg = vmsg; + + return peci_xfer(adapter, msg); +} + +static int peci_ioctl_ping(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_ping_msg *umsg = vmsg; + struct peci_xfer_msg msg; + + msg.addr = umsg->addr; + msg.tx_len = 0; + msg.rx_len = 0; + + return peci_xfer(adapter, &msg); +} + +static int peci_ioctl_get_dib(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_get_dib_msg *umsg = vmsg; + struct peci_xfer_msg msg; + int rc; + + msg.addr = umsg->addr; + msg.tx_len = GET_DIB_WR_LEN; + msg.rx_len = GET_DIB_RD_LEN; + msg.tx_buf[0] = GET_DIB_PECI_CMD; + + rc = peci_xfer(adapter, &msg); + if (rc) + return rc; + + umsg->dib = le64_to_cpup((__le64 *)msg.rx_buf); + + return 0; +} + +static int peci_ioctl_get_temp(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_get_temp_msg *umsg = vmsg; + struct peci_xfer_msg msg; + int rc; + + msg.addr = umsg->addr; + msg.tx_len = GET_TEMP_WR_LEN; + msg.rx_len = GET_TEMP_RD_LEN; + msg.tx_buf[0] = GET_TEMP_PECI_CMD; + + rc = peci_xfer(adapter, &msg); + if (rc) + return rc; + + umsg->temp_raw = le16_to_cpup((__le16 *)msg.rx_buf); + + return 0; +} + +static int peci_ioctl_rd_pkg_cfg(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_rd_pkg_cfg_msg *umsg = vmsg; + struct peci_xfer_msg msg; + int rc = 0; + + /* Per the PECI spec, the read length must be a byte, word, or dword */ + if (umsg->rx_len != 1 && umsg->rx_len != 2 && umsg->rx_len != 4) { + dev_dbg(&adapter->dev, "Invalid read length, rx_len: %d\n", + umsg->rx_len); + return -EINVAL; + } + + msg.addr = umsg->addr; + msg.tx_len = RDPKGCFG_WRITE_LEN; + /* read lengths of 1 and 2 result in an error, so only use 4 for now */ + msg.rx_len = RDPKGCFG_READ_LEN_BASE + umsg->rx_len; + msg.tx_buf[0] = RDPKGCFG_PECI_CMD; + msg.tx_buf[1] = 0; /* request byte for Host ID | Retry bit */ + /* Host ID is 0 for PECI 3.0 */ + msg.tx_buf[2] = umsg->index; /* RdPkgConfig index */ + msg.tx_buf[3] = (u8)umsg->param; /* LSB - Config parameter */ + msg.tx_buf[4] = (u8)(umsg->param >> 8); /* MSB - Config parameter */ + + rc = peci_xfer_with_retries(adapter, &msg, false); + if (!rc) + memcpy(umsg->pkg_config, &msg.rx_buf[1], umsg->rx_len); + + return rc; +} + +static int peci_ioctl_wr_pkg_cfg(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_wr_pkg_cfg_msg *umsg = vmsg; + struct peci_xfer_msg msg; + int rc = 0, i; + + /* Per the PECI spec, the write length must be a dword */ + if (umsg->tx_len != 4) { + dev_dbg(&adapter->dev, "Invalid write length, tx_len: %d\n", + umsg->tx_len); + return -EINVAL; + } + + msg.addr = umsg->addr; + msg.tx_len = WRPKGCFG_WRITE_LEN_BASE + umsg->tx_len; + /* read lengths of 1 and 2 result in an error, so only use 4 for now */ + msg.rx_len = WRPKGCFG_READ_LEN; + msg.tx_buf[0] = WRPKGCFG_PECI_CMD; + msg.tx_buf[1] = 0; /* request byte for Host ID | Retry bit */ + /* Host ID is 0 for PECI 3.0 */ + msg.tx_buf[2] = umsg->index; /* RdPkgConfig index */ + msg.tx_buf[3] = (u8)umsg->param; /* LSB - Config parameter */ + msg.tx_buf[4] = (u8)(umsg->param >> 8); /* MSB - Config parameter */ + for (i = 0; i < umsg->tx_len; i++) + msg.tx_buf[5 + i] = (u8)(umsg->value >> (i << 3)); + + /* Add an Assure Write Frame Check Sequence byte */ + msg.tx_buf[5 + i] = 0x80 ^ + peci_aw_fcs((u8 *)&msg, 8 + umsg->tx_len); + + rc = peci_xfer_with_retries(adapter, &msg, true); + + return rc; +} + +static int peci_ioctl_rd_ia_msr(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_rd_ia_msr_msg *umsg = vmsg; + struct peci_xfer_msg msg; + int rc = 0; + + msg.addr = umsg->addr; + msg.tx_len = RDIAMSR_WRITE_LEN; + msg.rx_len = RDIAMSR_READ_LEN; + msg.tx_buf[0] = RDIAMSR_PECI_CMD; + msg.tx_buf[1] = 0; + msg.tx_buf[2] = umsg->thread_id; + msg.tx_buf[3] = (u8)umsg->address; + msg.tx_buf[4] = (u8)(umsg->address >> 8); + + rc = peci_xfer_with_retries(adapter, &msg, false); + if (!rc) + memcpy(&umsg->value, &msg.rx_buf[1], sizeof(uint64_t)); + + return rc; +} + +static int peci_ioctl_rd_pci_cfg(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_rd_pci_cfg_msg *umsg = vmsg; + struct peci_xfer_msg msg; + u32 address; + int rc = 0; + + address = umsg->reg; /* [11:0] - Register */ + address |= (u32)umsg->function << 12; /* [14:12] - Function */ + address |= (u32)umsg->device << 15; /* [19:15] - Device */ + address |= (u32)umsg->bus << 20; /* [27:20] - Bus */ + /* [31:28] - Reserved */ + msg.addr = umsg->addr; + msg.tx_len = RDPCICFG_WRITE_LEN; + msg.rx_len = RDPCICFG_READ_LEN; + msg.tx_buf[0] = RDPCICFG_PECI_CMD; + msg.tx_buf[1] = 0; /* request byte for Host ID | Retry bit */ + /* Host ID is 0 for PECI 3.0 */ + msg.tx_buf[2] = (u8)address; /* LSB - PCI Config Address */ + msg.tx_buf[3] = (u8)(address >> 8); /* PCI Config Address */ + msg.tx_buf[4] = (u8)(address >> 16); /* PCI Config Address */ + msg.tx_buf[5] = (u8)(address >> 24); /* MSB - PCI Config Address */ + + rc = peci_xfer_with_retries(adapter, &msg, false); + if (!rc) + memcpy(umsg->pci_config, &msg.rx_buf[1], 4); + + return rc; +} + +static int peci_ioctl_rd_pci_cfg_local(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_rd_pci_cfg_local_msg *umsg = vmsg; + struct peci_xfer_msg msg; + u32 address; + int rc = 0; + + /* Per the PECI spec, the read length must be a byte, word, or dword */ + if (umsg->rx_len != 1 && umsg->rx_len != 2 && umsg->rx_len != 4) { + dev_dbg(&adapter->dev, "Invalid read length, rx_len: %d\n", + umsg->rx_len); + return -EINVAL; + } + + address = umsg->reg; /* [11:0] - Register */ + address |= (u32)umsg->function << 12; /* [14:12] - Function */ + address |= (u32)umsg->device << 15; /* [19:15] - Device */ + address |= (u32)umsg->bus << 20; /* [23:20] - Bus */ + + msg.addr = umsg->addr; + msg.tx_len = RDPCICFGLOCAL_WRITE_LEN; + msg.rx_len = RDPCICFGLOCAL_READ_LEN_BASE + umsg->rx_len; + msg.tx_buf[0] = RDPCICFGLOCAL_PECI_CMD; + msg.tx_buf[1] = 0; /* request byte for Host ID | Retry bit */ + /* Host ID is 0 for PECI 3.0 */ + msg.tx_buf[2] = (u8)address; /* LSB - PCI Configuration Address */ + msg.tx_buf[3] = (u8)(address >> 8); /* PCI Configuration Address */ + msg.tx_buf[4] = (u8)(address >> 16); /* PCI Configuration Address */ + + rc = peci_xfer_with_retries(adapter, &msg, false); + if (!rc) + memcpy(umsg->pci_config, &msg.rx_buf[1], umsg->rx_len); + + return rc; +} + +static int peci_ioctl_wr_pci_cfg_local(struct peci_adapter *adapter, void *vmsg) +{ + struct peci_wr_pci_cfg_local_msg *umsg = vmsg; + struct peci_xfer_msg msg; + int rc = 0, i; + u32 address; + + /* Per the PECI spec, the write length must be a byte, word, or dword */ + if (umsg->tx_len != 1 && umsg->tx_len != 2 && umsg->tx_len != 4) { + dev_dbg(&adapter->dev, "Invalid write length, tx_len: %d\n", + umsg->tx_len); + return -EINVAL; + } + + address = umsg->reg; /* [11:0] - Register */ + address |= (u32)umsg->function << 12; /* [14:12] - Function */ + address |= (u32)umsg->device << 15; /* [19:15] - Device */ + address |= (u32)umsg->bus << 20; /* [23:20] - Bus */ + + msg.addr = umsg->addr; + msg.tx_len = WRPCICFGLOCAL_WRITE_LEN_BASE + umsg->tx_len; + msg.rx_len = WRPCICFGLOCAL_READ_LEN; + msg.tx_buf[0] = WRPCICFGLOCAL_PECI_CMD; + msg.tx_buf[1] = 0; /* request byte for Host ID | Retry bit */ + /* Host ID is 0 for PECI 3.0 */ + msg.tx_buf[2] = (u8)address; /* LSB - PCI Configuration Address */ + msg.tx_buf[3] = (u8)(address >> 8); /* PCI Configuration Address */ + msg.tx_buf[4] = (u8)(address >> 16); /* PCI Configuration Address */ + for (i = 0; i < umsg->tx_len; i++) + msg.tx_buf[5 + i] = (u8)(umsg->value >> (i << 3)); + + /* Add an Assure Write Frame Check Sequence byte */ + msg.tx_buf[5 + i] = 0x80 ^ + peci_aw_fcs((u8 *)&msg, 8 + umsg->tx_len); + + rc = peci_xfer_with_retries(adapter, &msg, true); + + return rc; +} + +typedef int (*peci_ioctl_fn_type)(struct peci_adapter *, void *); + +static const peci_ioctl_fn_type peci_ioctl_fn[PECI_CMD_MAX] = { + peci_ioctl_xfer, + peci_ioctl_ping, + peci_ioctl_get_dib, + peci_ioctl_get_temp, + peci_ioctl_rd_pkg_cfg, + peci_ioctl_wr_pkg_cfg, + peci_ioctl_rd_ia_msr, + NULL, /* Reserved */ + peci_ioctl_rd_pci_cfg, + NULL, /* Reserved */ + peci_ioctl_rd_pci_cfg_local, + peci_ioctl_wr_pci_cfg_local, +}; + +/** + * peci_command - transfer function of a PECI command + * @adapter: pointer to peci_adapter + * @vmsg: pointer to PECI messages + * Context: can sleep + * + * This performs a transfer of a PECI command using PECI messages parameter + * which has various formats on each command. + * + * Return: zero on success, else a negative error code. + */ +int peci_command(struct peci_adapter *adapter, enum peci_cmd cmd, void *vmsg) +{ + int rc = 0; + + if (cmd >= PECI_CMD_MAX || cmd < PECI_CMD_XFER) + return -EINVAL; + + dev_dbg(&adapter->dev, "%s, cmd=0x%02x\n", __func__, cmd); + + if (!peci_ioctl_fn[cmd]) + return -EINVAL; + + rt_mutex_lock(&adapter->bus_lock); + + rc = peci_cmd_support(adapter, cmd); + if (!rc) + rc = peci_ioctl_fn[cmd](adapter, vmsg); + + rt_mutex_unlock(&adapter->bus_lock); + + return rc; +} +EXPORT_SYMBOL_GPL(peci_command); + +static long peci_ioctl(struct file *file, unsigned int iocmd, unsigned long arg) +{ + struct peci_adapter *adapter = file->private_data; + void __user *argp = (void __user *)arg; + unsigned int msg_len; + enum peci_cmd cmd; + int rc = 0; + u8 *msg; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + dev_dbg(&adapter->dev, "ioctl, cmd=0x%x, arg=0x%lx\n", iocmd, arg); + + switch (iocmd) { + case PECI_IOC_XFER: + case PECI_IOC_PING: + case PECI_IOC_GET_DIB: + case PECI_IOC_GET_TEMP: + case PECI_IOC_RD_PKG_CFG: + case PECI_IOC_WR_PKG_CFG: + case PECI_IOC_RD_IA_MSR: + case PECI_IOC_RD_PCI_CFG: + case PECI_IOC_RD_PCI_CFG_LOCAL: + case PECI_IOC_WR_PCI_CFG_LOCAL: + cmd = _IOC_NR(iocmd); + msg_len = _IOC_SIZE(iocmd); + break; + + default: + dev_dbg(&adapter->dev, "Invalid ioctl cmd : 0x%x\n", iocmd); + return -ENOTTY; + } + + if (!access_ok(argp, msg_len)) + return -EFAULT; + + msg = memdup_user(argp, msg_len); + if (IS_ERR(msg)) + return PTR_ERR(msg); + + rc = peci_command(adapter, cmd, msg); + + if (!rc && copy_to_user(argp, msg, msg_len)) + rc = -EFAULT; + + kfree(msg); + return (long)rc; +} + +static int peci_open(struct inode *inode, struct file *file) +{ + unsigned int minor = iminor(inode); + struct peci_adapter *adapter; + + adapter = peci_get_adapter(minor); + if (!adapter) + return -ENODEV; + + file->private_data = adapter; + + return 0; +} + +static int peci_release(struct inode *inode, struct file *file) +{ + struct peci_adapter *adapter = file->private_data; + + peci_put_adapter(adapter); + file->private_data = NULL; + + return 0; +} + +static const struct file_operations peci_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = peci_ioctl, + .open = peci_open, + .release = peci_release, +}; + +static int peci_detect(struct peci_adapter *adapter, u8 addr) +{ + struct peci_ping_msg msg; + + msg.addr = addr; + + return peci_command(adapter, PECI_CMD_PING, &msg); +} + +static const struct of_device_id * +peci_of_match_device(const struct of_device_id *matches, + struct peci_client *client) +{ +#if IS_ENABLED(CONFIG_OF) + if (!(client && matches)) + return NULL; + + return of_match_device(matches, &client->dev); +#else + return NULL; +#endif +} + +static const struct peci_device_id * +peci_match_id(const struct peci_device_id *id, struct peci_client *client) +{ + if (!(id && client)) + return NULL; + + while (id->name[0]) { + if (!strncmp(client->name, id->name, PECI_NAME_SIZE)) + return id; + id++; + } + + return NULL; +} + +static int peci_device_match(struct device *dev, struct device_driver *drv) +{ + struct peci_client *client = peci_verify_client(dev); + struct peci_driver *driver; + + /* Attempt an OF style match */ + if (peci_of_match_device(drv->of_match_table, client)) + return 1; + + driver = to_peci_driver(drv); + + /* Finally an ID match */ + if (peci_match_id(driver->id_table, client)) + return 1; + + return 0; +} + +static int peci_device_probe(struct device *dev) +{ + struct peci_client *client = peci_verify_client(dev); + struct peci_driver *driver; + int status = -EINVAL; + + if (!client) + return 0; + + driver = to_peci_driver(dev->driver); + + if (!driver->id_table && + !peci_of_match_device(dev->driver->of_match_table, client)) + return -ENODEV; + + dev_dbg(dev, "%s: name:%s\n", __func__, client->name); + + status = dev_pm_domain_attach(&client->dev, true); + if (status == -EPROBE_DEFER) + return status; + + if (driver->probe) + status = driver->probe(client); + else + status = -EINVAL; + + if (status) + goto err_detach_pm_domain; + + return 0; + +err_detach_pm_domain: + dev_pm_domain_detach(&client->dev, true); + return status; +} + +static int peci_device_remove(struct device *dev) +{ + struct peci_client *client = peci_verify_client(dev); + struct peci_driver *driver; + int status = 0; + + if (!client || !dev->driver) + return 0; + + driver = to_peci_driver(dev->driver); + if (driver->remove) { + dev_dbg(dev, "%s: name:%s\n", __func__, client->name); + status = driver->remove(client); + } + + dev_pm_domain_detach(&client->dev, true); + + return status; +} + +static void peci_device_shutdown(struct device *dev) +{ + struct peci_client *client = peci_verify_client(dev); + struct peci_driver *driver; + + if (!client || !dev->driver) + return; + + dev_dbg(dev, "%s: name:%s\n", __func__, client->name); + + driver = to_peci_driver(dev->driver); + if (driver->shutdown) + driver->shutdown(client); +} + +static struct bus_type peci_bus_type = { + .name = "peci", + .match = peci_device_match, + .probe = peci_device_probe, + .remove = peci_device_remove, + .shutdown = peci_device_shutdown, +}; + +static int peci_check_addr_validity(u8 addr) +{ + if (addr < PECI_BASE_ADDR && addr > PECI_BASE_ADDR + PECI_OFFSET_MAX) + return -EINVAL; + + return 0; +} + +static int peci_check_client_busy(struct device *dev, void *client_new_p) +{ + struct peci_client *client = peci_verify_client(dev); + struct peci_client *client_new = client_new_p; + + if (client && client->addr == client_new->addr) + return -EBUSY; + + return 0; +} + +/** + * peci_get_cpu_id - read CPU ID from the Package Configuration Space of CPU + * @adapter: pointer to peci_adapter + * @addr: address of the PECI client CPU + * @cpu_id: where the CPU ID will be stored + * Context: can sleep + * + * Return: zero on success, else a negative error code. + */ +int peci_get_cpu_id(struct peci_adapter *adapter, u8 addr, u32 *cpu_id) +{ + struct peci_rd_pkg_cfg_msg msg; + int rc; + + msg.addr = addr; + msg.index = MBX_INDEX_CPU_ID; + msg.param = PKG_ID_CPU_ID; + msg.rx_len = 4; + + rc = peci_command(adapter, PECI_CMD_RD_PKG_CFG, &msg); + if (!rc) + *cpu_id = le32_to_cpup((__le32 *)msg.pkg_config); + + return rc; +} +EXPORT_SYMBOL_GPL(peci_get_cpu_id); + +static struct peci_client *peci_new_device(struct peci_adapter *adapter, + struct peci_board_info const *info) +{ + struct peci_client *client; + int rc; + + /* Increase reference count for the adapter assigned */ + if (!peci_get_adapter(adapter->nr)) + return NULL; + + client = kzalloc(sizeof(*client), GFP_KERNEL); + if (!client) + goto err_put_adapter; + + client->adapter = adapter; + client->addr = info->addr; + strlcpy(client->name, info->type, sizeof(client->name)); + + rc = peci_check_addr_validity(client->addr); + if (rc) { + dev_err(&adapter->dev, "Invalid PECI CPU address 0x%02hx\n", + client->addr); + goto err_free_client_silent; + } + + /* Check online status of client */ + rc = peci_detect(adapter, client->addr); + if (rc) + goto err_free_client; + + rc = device_for_each_child(&adapter->dev, client, + peci_check_client_busy); + if (rc) + goto err_free_client; + + client->dev.parent = &client->adapter->dev; + client->dev.bus = &peci_bus_type; + client->dev.type = &peci_client_type; + client->dev.of_node = info->of_node; + dev_set_name(&client->dev, "%d-%02x", adapter->nr, client->addr); + + rc = device_register(&client->dev); + if (rc) + goto err_free_client; + + dev_dbg(&adapter->dev, "client [%s] registered with bus id %s\n", + client->name, dev_name(&client->dev)); + + return client; + +err_free_client: + dev_err(&adapter->dev, + "Failed to register peci client %s at 0x%02x (%d)\n", + client->name, client->addr, rc); +err_free_client_silent: + kfree(client); +err_put_adapter: + peci_put_adapter(adapter); + return NULL; +} + +static void peci_unregister_device(struct peci_client *client) +{ + if (!client) + return; + + if (client->dev.of_node) + of_node_clear_flag(client->dev.of_node, OF_POPULATED); + + device_unregister(&client->dev); +} + +static int peci_unregister_client(struct device *dev, void *dummy) +{ + struct peci_client *client = peci_verify_client(dev); + + peci_unregister_device(client); + + return 0; +} + +static void peci_adapter_dev_release(struct device *dev) +{ + struct peci_adapter *adapter = to_peci_adapter(dev); + + dev_dbg(dev, "%s: %s\n", __func__, adapter->name); + mutex_destroy(&adapter->userspace_clients_lock); + rt_mutex_destroy(&adapter->bus_lock); + kfree(adapter); +} + +static ssize_t peci_sysfs_new_device(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct peci_adapter *adapter = to_peci_adapter(dev); + struct peci_board_info info = {}; + struct peci_client *client; + char *blank, end; + int rc; + + /* Parse device type */ + blank = strchr(buf, ' '); + if (!blank) { + dev_err(dev, "%s: Missing parameters\n", "new_device"); + return -EINVAL; + } + if (blank - buf > PECI_NAME_SIZE - 1) { + dev_err(dev, "%s: Invalid device type\n", "new_device"); + return -EINVAL; + } + memcpy(info.type, buf, blank - buf); + + /* Parse remaining parameters, reject extra parameters */ + rc = sscanf(++blank, "%hi%c", &info.addr, &end); + if (rc < 1) { + dev_err(dev, "%s: Can't parse client address\n", "new_device"); + return -EINVAL; + } + if (rc > 1 && end != '\n') { + dev_err(dev, "%s: Extra parameters\n", "new_device"); + return -EINVAL; + } + + client = peci_new_device(adapter, &info); + if (!client) + return -EINVAL; + + /* Keep track of the added device */ + mutex_lock(&adapter->userspace_clients_lock); + list_add_tail(&client->detected, &adapter->userspace_clients); + mutex_unlock(&adapter->userspace_clients_lock); + dev_info(dev, "%s: Instantiated device %s at 0x%02hx\n", "new_device", + info.type, info.addr); + + return count; +} +static DEVICE_ATTR(new_device, 0200, NULL, peci_sysfs_new_device); + +static ssize_t peci_sysfs_delete_device(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct peci_adapter *adapter = to_peci_adapter(dev); + struct peci_client *client, *next; + struct peci_board_info info = {}; + struct peci_driver *driver; + char *blank, end; + int rc; + + /* Parse device type */ + blank = strchr(buf, ' '); + if (!blank) { + dev_err(dev, "%s: Missing parameters\n", "delete_device"); + return -EINVAL; + } + if (blank - buf > PECI_NAME_SIZE - 1) { + dev_err(dev, "%s: Invalid device type\n", "delete_device"); + return -EINVAL; + } + memcpy(info.type, buf, blank - buf); + + /* Parse remaining parameters, reject extra parameters */ + rc = sscanf(++blank, "%hi%c", &info.addr, &end); + if (rc < 1) { + dev_err(dev, "%s: Can't parse client address\n", + "delete_device"); + return -EINVAL; + } + if (rc > 1 && end != '\n') { + dev_err(dev, "%s: Extra parameters\n", "delete_device"); + return -EINVAL; + } + + /* Make sure the device was added through sysfs */ + rc = -ENOENT; + mutex_lock(&adapter->userspace_clients_lock); + list_for_each_entry_safe(client, next, &adapter->userspace_clients, + detected) { + driver = to_peci_driver(client->dev.driver); + + if (client->addr == info.addr && + !strncmp(client->name, info.type, PECI_NAME_SIZE)) { + dev_info(dev, "%s: Deleting device %s at 0x%02hx\n", + "delete_device", client->name, client->addr); + list_del(&client->detected); + peci_unregister_device(client); + rc = count; + break; + } + } + mutex_unlock(&adapter->userspace_clients_lock); + + if (rc < 0) + dev_err(dev, "%s: Can't find device in list\n", + "delete_device"); + + return rc; +} +static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, 0200, NULL, + peci_sysfs_delete_device); + +static struct attribute *peci_adapter_attrs[] = { + &dev_attr_name.attr, + &dev_attr_new_device.attr, + &dev_attr_delete_device.attr, + NULL +}; +ATTRIBUTE_GROUPS(peci_adapter); + +static struct device_type peci_adapter_type = { + .groups = peci_adapter_groups, + .release = peci_adapter_dev_release, +}; + +/** + * peci_verify_adapter - return parameter as peci_adapter, or NULL + * @dev: device, probably from some driver model iterator + * + * Return: pointer to peci_adapter on success, else NULL. + */ +struct peci_adapter *peci_verify_adapter(struct device *dev) +{ + return (dev->type == &peci_adapter_type) + ? to_peci_adapter(dev) + : NULL; +} +EXPORT_SYMBOL_GPL(peci_verify_adapter); + +#if IS_ENABLED(CONFIG_OF) +static struct peci_client *peci_of_register_device(struct peci_adapter *adapter, + struct device_node *node) +{ + struct peci_board_info info = {}; + struct peci_client *result; + const __be32 *addr_be; + int len; + + dev_dbg(&adapter->dev, "register %pOF\n", node); + + if (of_modalias_node(node, info.type, sizeof(info.type)) < 0) { + dev_err(&adapter->dev, "modalias failure on %pOF\n", node); + return ERR_PTR(-EINVAL); + } + + addr_be = of_get_property(node, "reg", &len); + if (!addr_be || len < sizeof(*addr_be)) { + dev_err(&adapter->dev, "invalid reg on %pOF\n", node); + return ERR_PTR(-EINVAL); + } + + info.addr = be32_to_cpup(addr_be); + info.of_node = of_node_get(node); + + result = peci_new_device(adapter, &info); + if (!result) + result = ERR_PTR(-EINVAL); + + of_node_put(node); + return result; +} + +static void peci_of_register_devices(struct peci_adapter *adapter) +{ + struct device_node *bus, *node; + struct peci_client *client; + + /* Only register child devices if the adapter has a node pointer set */ + if (!adapter->dev.of_node) + return; + + bus = of_get_child_by_name(adapter->dev.of_node, "peci-bus"); + if (!bus) + bus = of_node_get(adapter->dev.of_node); + + for_each_available_child_of_node(bus, node) { + if (of_node_test_and_set_flag(node, OF_POPULATED)) + continue; + + client = peci_of_register_device(adapter, node); + if (IS_ERR(client)) { + dev_warn(&adapter->dev, + "Failed to create PECI device for %pOF\n", + node); + of_node_clear_flag(node, OF_POPULATED); + } + } + + of_node_put(bus); +} +#else +static void peci_of_register_devices(struct peci_adapter *adapter) { } +#endif /* CONFIG_OF */ + +#if IS_ENABLED(CONFIG_OF_DYNAMIC) +static int peci_of_match_node(struct device *dev, void *data) +{ + return dev->of_node == data; +} + +/* must call put_device() when done with returned peci_client device */ +static struct peci_client *peci_of_find_device(struct device_node *node) +{ + struct peci_client *client; + struct device *dev; + + dev = bus_find_device(&peci_bus_type, NULL, node, peci_of_match_node); + if (!dev) + return NULL; + + client = peci_verify_client(dev); + if (!client) + put_device(dev); + + return client; +} + +/* must call put_device() when done with returned peci_adapter device */ +static struct peci_adapter *peci_of_find_adapter(struct device_node *node) +{ + struct peci_adapter *adapter; + struct device *dev; + + dev = bus_find_device(&peci_bus_type, NULL, node, peci_of_match_node); + if (!dev) + return NULL; + + adapter = peci_verify_adapter(dev); + if (!adapter) + put_device(dev); + + return adapter; +} + +static int peci_of_notify(struct notifier_block *nb, + unsigned long action, + void *arg) +{ + struct of_reconfig_data *rd = arg; + struct peci_adapter *adapter; + struct peci_client *client; + + switch (of_reconfig_get_state_change(action, rd)) { + case OF_RECONFIG_CHANGE_ADD: + adapter = peci_of_find_adapter(rd->dn->parent); + if (!adapter) + return NOTIFY_OK; /* not for us */ + + if (of_node_test_and_set_flag(rd->dn, OF_POPULATED)) { + put_device(&adapter->dev); + return NOTIFY_OK; + } + + client = peci_of_register_device(adapter, rd->dn); + put_device(&adapter->dev); + + if (IS_ERR(client)) { + dev_err(&adapter->dev, + "failed to create client for '%pOF'\n", rd->dn); + of_node_clear_flag(rd->dn, OF_POPULATED); + return notifier_from_errno(PTR_ERR(client)); + } + break; + case OF_RECONFIG_CHANGE_REMOVE: + /* already depopulated? */ + if (!of_node_check_flag(rd->dn, OF_POPULATED)) + return NOTIFY_OK; + + /* find our device by node */ + client = peci_of_find_device(rd->dn); + if (!client) + return NOTIFY_OK; /* no? not meant for us */ + + /* unregister takes one ref away */ + peci_unregister_device(client); + + /* and put the reference of the find */ + put_device(&client->dev); + break; + } + + return NOTIFY_OK; +} + +static struct notifier_block peci_of_notifier = { + .notifier_call = peci_of_notify, +}; +#else +extern struct notifier_block peci_of_notifier; +#endif /* CONFIG_OF_DYNAMIC */ + +/** + * peci_alloc_adapter - allocate a PECI adapter + * @dev: the adapter, possibly using the platform_bus + * @size: how much zeroed driver-private data to allocate; the pointer to this + * memory is in the driver_data field of the returned device, + * accessible with peci_get_adapdata(). + * Context: can sleep + * + * This call is used only by PECI adapter drivers, which are the only ones + * directly touching chip registers. It's how they allocate a peci_adapter + * structure, prior to calling peci_add_adapter(). + * + * This must be called from context that can sleep. + * + * The caller is responsible for initializing the adapter's methods before + * calling peci_add_adapter(); and (after errors while adding the device) + * calling put_device() to prevent a memory leak. + * + * Return: the peci_adapter structure on success, else NULL. + */ +struct peci_adapter *peci_alloc_adapter(struct device *dev, unsigned int size) +{ + struct peci_adapter *adapter; + + if (!dev) + return NULL; + + adapter = kzalloc(size + sizeof(*adapter), GFP_KERNEL); + if (!adapter) + return NULL; + + device_initialize(&adapter->dev); + adapter->dev.parent = dev; + adapter->dev.bus = &peci_bus_type; + adapter->dev.type = &peci_adapter_type; + peci_set_adapdata(adapter, &adapter[1]); + + return adapter; +} +EXPORT_SYMBOL_GPL(peci_alloc_adapter); + +static int peci_register_adapter(struct peci_adapter *adapter) +{ + int rc = -EINVAL; + + /* Can't register until after driver model init */ + if (WARN_ON(!is_registered)) + goto err_free_idr; + + if (WARN(!adapter->name[0], "peci adapter has no name")) + goto err_free_idr; + + if (WARN(!adapter->xfer, "peci adapter has no xfer function\n")) + goto err_free_idr; + + rt_mutex_init(&adapter->bus_lock); + mutex_init(&adapter->userspace_clients_lock); + INIT_LIST_HEAD(&adapter->userspace_clients); + + dev_set_name(&adapter->dev, "peci-%d", adapter->nr); + + /* cdev */ + cdev_init(&adapter->cdev, &peci_fops); + adapter->cdev.owner = THIS_MODULE; + adapter->dev.devt = MKDEV(MAJOR(peci_devt), adapter->nr); + rc = cdev_add(&adapter->cdev, adapter->dev.devt, 1); + if (rc) { + pr_err("adapter '%s': can't add cdev (%d)\n", + adapter->name, rc); + goto err_free_idr; + } + rc = device_add(&adapter->dev); + if (rc) { + pr_err("adapter '%s': can't add device (%d)\n", + adapter->name, rc); + goto err_del_cdev; + } + + dev_dbg(&adapter->dev, "adapter [%s] registered\n", adapter->name); + + pm_runtime_no_callbacks(&adapter->dev); + pm_suspend_ignore_children(&adapter->dev, true); + pm_runtime_enable(&adapter->dev); + + /* create pre-declared device nodes */ + peci_of_register_devices(adapter); + + return 0; + +err_del_cdev: + cdev_del(&adapter->cdev); +err_free_idr: + mutex_lock(&core_lock); + idr_remove(&peci_adapter_idr, adapter->nr); + mutex_unlock(&core_lock); + return rc; +} + +static int peci_add_numbered_adapter(struct peci_adapter *adapter) +{ + int id; + + mutex_lock(&core_lock); + id = idr_alloc(&peci_adapter_idr, adapter, + adapter->nr, adapter->nr + 1, GFP_KERNEL); + mutex_unlock(&core_lock); + if (WARN(id < 0, "couldn't get idr")) + return id == -ENOSPC ? -EBUSY : id; + + return peci_register_adapter(adapter); +} + +/** + * peci_add_adapter - add a PECI adapter + * @adapter: initialized adapter, originally from peci_alloc_adapter() + * Context: can sleep + * + * PECI adapters connect to their drivers using some non-PECI bus, + * such as the platform bus. The final stage of probe() in that code + * includes calling peci_add_adapter() to hook up to this PECI bus glue. + * + * This must be called from context that can sleep. + * + * It returns zero on success, else a negative error code (dropping the + * adapter's refcount). After a successful return, the caller is responsible + * for calling peci_del_adapter(). + * + * Return: zero on success, else a negative error code. + */ +int peci_add_adapter(struct peci_adapter *adapter) +{ + struct device *dev = &adapter->dev; + int id; + + if (dev->of_node) { + id = of_alias_get_id(dev->of_node, "peci"); + if (id >= 0) { + adapter->nr = id; + return peci_add_numbered_adapter(adapter); + } + } + + mutex_lock(&core_lock); + id = idr_alloc(&peci_adapter_idr, adapter, 0, 0, GFP_KERNEL); + mutex_unlock(&core_lock); + if (WARN(id < 0, "couldn't get idr")) + return id; + + adapter->nr = id; + + return peci_register_adapter(adapter); +} +EXPORT_SYMBOL_GPL(peci_add_adapter); + +/** + * peci_del_adapter - delete a PECI adapter + * @adapter: the adpater being deleted + * Context: can sleep + * + * This call is used only by PECI adpater drivers, which are the only ones + * directly touching chip registers. + * + * This must be called from context that can sleep. + * + * Note that this function also drops a reference to the adapter. + */ +void peci_del_adapter(struct peci_adapter *adapter) +{ + struct peci_client *client, *next; + struct peci_adapter *found; + int nr; + + /* First make sure that this adapter was ever added */ + mutex_lock(&core_lock); + found = idr_find(&peci_adapter_idr, adapter->nr); + mutex_unlock(&core_lock); + + if (found != adapter) + return; + + /* Remove devices instantiated from sysfs */ + mutex_lock(&adapter->userspace_clients_lock); + list_for_each_entry_safe(client, next, &adapter->userspace_clients, + detected) { + dev_dbg(&adapter->dev, "Removing %s at 0x%x\n", client->name, + client->addr); + list_del(&client->detected); + peci_unregister_device(client); + } + mutex_unlock(&adapter->userspace_clients_lock); + + /** + * Detach any active clients. This can't fail, thus we do not + * check the returned value. + */ + device_for_each_child(&adapter->dev, NULL, peci_unregister_client); + + /* device name is gone after device_unregister */ + dev_dbg(&adapter->dev, "adapter [%s] unregistered\n", adapter->name); + + /* free cdev */ + cdev_del(&adapter->cdev); + + pm_runtime_disable(&adapter->dev); + + nr = adapter->nr; + + device_unregister(&adapter->dev); + + /* free bus id */ + mutex_lock(&core_lock); + idr_remove(&peci_adapter_idr, nr); + mutex_unlock(&core_lock); +} +EXPORT_SYMBOL_GPL(peci_del_adapter); + +/** + * peci_register_driver - register a PECI driver + * @owner: owner module of the driver being registered + * @driver: the driver being registered + * Context: can sleep + * + * Return: zero on success, else a negative error code. + */ +int peci_register_driver(struct module *owner, struct peci_driver *driver) +{ + int rc; + + /* Can't register until after driver model init */ + if (WARN_ON(!is_registered)) + return -EAGAIN; + + /* add the driver to the list of peci drivers in the driver core */ + driver->driver.owner = owner; + driver->driver.bus = &peci_bus_type; + + /** + * When registration returns, the driver core + * will have called probe() for all matching-but-unbound devices. + */ + rc = driver_register(&driver->driver); + if (rc) + return rc; + + pr_debug("driver [%s] registered\n", driver->driver.name); + + return 0; +} +EXPORT_SYMBOL_GPL(peci_register_driver); + +/** + * peci_del_driver - unregister a PECI driver + * @driver: the driver being unregistered + * Context: can sleep + */ +void peci_del_driver(struct peci_driver *driver) +{ + driver_unregister(&driver->driver); + pr_debug("driver [%s] unregistered\n", driver->driver.name); +} +EXPORT_SYMBOL_GPL(peci_del_driver); + +static int __init peci_init(void) +{ + int ret; + + ret = bus_register(&peci_bus_type); + if (ret < 0) { + pr_err("peci: Failed to register PECI bus type!\n"); + return ret; + } + + ret = alloc_chrdev_region(&peci_devt, 0, PECI_CDEV_MAX, "peci"); + if (ret < 0) { + pr_err("peci: Failed to allocate chr dev region!\n"); + bus_unregister(&peci_bus_type); + return ret; + } + + crc8_populate_msb(peci_crc8_table, PECI_CRC8_POLYNOMIAL); + + if (IS_ENABLED(CONFIG_OF_DYNAMIC)) + WARN_ON(of_reconfig_notifier_register(&peci_of_notifier)); + + is_registered = true; + + return 0; +} + +static void __exit peci_exit(void) +{ + if (IS_ENABLED(CONFIG_OF_DYNAMIC)) + WARN_ON(of_reconfig_notifier_unregister(&peci_of_notifier)); + + unregister_chrdev_region(peci_devt, PECI_CDEV_MAX); + bus_unregister(&peci_bus_type); +} + +postcore_initcall(peci_init); +module_exit(peci_exit); + +MODULE_AUTHOR("Jason M Biils <jason.m.bills@linux.intel.com>"); +MODULE_AUTHOR("Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>"); +MODULE_DESCRIPTION("PECI bus core module"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/peci/peci-npcm.c b/drivers/peci/peci-npcm.c new file mode 100644 index 000000000000..f632365b1416 --- /dev/null +++ b/drivers/peci/peci-npcm.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology corporation. + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/jiffies.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/peci.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> +#include <linux/reset.h> + +/* NPCM7xx GCR module */ +#define NPCM7XX_INTCR3_OFFSET 0x9C +#define NPCM7XX_INTCR3_PECIVSEL BIT(19) + +/* NPCM PECI Registers */ +#define NPCM_PECI_CTL_STS 0x00 +#define NPCM_PECI_RD_LENGTH 0x04 +#define NPCM_PECI_ADDR 0x08 +#define NPCM_PECI_CMD 0x0C +#define NPCM_PECI_CTL2 0x10 +#define NPCM_PECI_WR_LENGTH 0x1C +#define NPCM_PECI_PDDR 0x2C +#define NPCM_PECI_DAT_INOUT(n) (0x100 + ((n) * 4)) + +#define NPCM_PECI_MAX_REG 0x200 + +/* NPCM_PECI_CTL_STS - 0x00 : Control Register */ +#define NPCM_PECI_CTRL_DONE_INT_EN BIT(6) +#define NPCM_PECI_CTRL_ABRT_ERR BIT(4) +#define NPCM_PECI_CTRL_CRC_ERR BIT(3) +#define NPCM_PECI_CTRL_DONE BIT(1) +#define NPCM_PECI_CTRL_START_BUSY BIT(0) + +/* NPCM_PECI_RD_LENGTH - 0x04 : Command Register */ +#define NPCM_PECI_RD_LEN_MASK GENMASK(6, 0) + +/* NPCM_PECI_CMD - 0x10 : Command Register */ +#define NPCM_PECI_CTL2_MASK GENMASK(7, 6) + +/* NPCM_PECI_WR_LENGTH - 0x1C : Command Register */ +#define NPCM_PECI_WR_LEN_MASK GENMASK(6, 0) + +/* NPCM_PECI_PDDR - 0x2C : Command Register */ +#define NPCM_PECI_PDDR_MASK GENMASK(4, 0) + +#define NPCM_PECI_INT_MASK (NPCM_PECI_CTRL_ABRT_ERR | \ + NPCM_PECI_CTRL_CRC_ERR | \ + NPCM_PECI_CTRL_DONE) + +#define NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC 50000 +#define NPCM_PECI_IDLE_CHECK_INTERVAL_USEC 10000 +#define NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT 1000 +#define NPCM_PECI_CMD_TIMEOUT_MS_MAX 60000 +#define NPCM_PECI_HOST_NEG_BIT_RATE_MAX 31 +#define NPCM_PECI_HOST_NEG_BIT_RATE_MIN 7 +#define NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT 15 +#define NPCM_PECI_PULL_DOWN_DEFAULT 0 +#define NPCM_PECI_PULL_DOWN_MAX 2 + +struct npcm_peci { + u32 cmd_timeout_ms; + u32 host_bit_rate; + struct completion xfer_complete; + struct regmap *gcr_regmap; + struct peci_adapter *adapter; + struct regmap *regmap; + u32 status; + spinlock_t lock; /* to sync completion status handling */ + struct device *dev; + struct clk *clk; + int irq; +}; + +static int npcm_peci_xfer_native(struct npcm_peci *priv, + struct peci_xfer_msg *msg) +{ + long err, timeout = msecs_to_jiffies(priv->cmd_timeout_ms); + unsigned long flags; + unsigned int msg_rd; + u32 cmd_sts; + int i, rc; + + /* Check command sts and bus idle state */ + rc = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts, + !(cmd_sts & NPCM_PECI_CTRL_START_BUSY), + NPCM_PECI_IDLE_CHECK_INTERVAL_USEC, + NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC); + if (rc) + return rc; /* -ETIMEDOUT */ + + spin_lock_irqsave(&priv->lock, flags); + reinit_completion(&priv->xfer_complete); + + regmap_write(priv->regmap, NPCM_PECI_ADDR, msg->addr); + regmap_write(priv->regmap, NPCM_PECI_RD_LENGTH, + NPCM_PECI_WR_LEN_MASK & msg->rx_len); + regmap_write(priv->regmap, NPCM_PECI_WR_LENGTH, + NPCM_PECI_WR_LEN_MASK & msg->tx_len); + + if (msg->tx_len) { + regmap_write(priv->regmap, NPCM_PECI_CMD, msg->tx_buf[0]); + + for (i = 0; i < (msg->tx_len - 1); i++) + regmap_write(priv->regmap, NPCM_PECI_DAT_INOUT(i), + msg->tx_buf[i + 1]); + } + + priv->status = 0; + regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, + NPCM_PECI_CTRL_START_BUSY, + NPCM_PECI_CTRL_START_BUSY); + + spin_unlock_irqrestore(&priv->lock, flags); + + err = wait_for_completion_interruptible_timeout(&priv->xfer_complete, + timeout); + + spin_lock_irqsave(&priv->lock, flags); + + regmap_write(priv->regmap, NPCM_PECI_CMD, 0); + + if (err <= 0 || priv->status != NPCM_PECI_CTRL_DONE) { + if (err < 0) { /* -ERESTARTSYS */ + rc = (int)err; + goto err_irqrestore; + } else if (err == 0) { + dev_dbg(priv->dev, "Timeout waiting for a response!\n"); + rc = -ETIMEDOUT; + goto err_irqrestore; + } + + dev_dbg(priv->dev, "No valid response!\n"); + rc = -EIO; + goto err_irqrestore; + } + + for (i = 0; i < msg->rx_len; i++) { + regmap_read(priv->regmap, NPCM_PECI_DAT_INOUT(i), &msg_rd); + msg->rx_buf[i] = (u8)msg_rd; + } + +err_irqrestore: + spin_unlock_irqrestore(&priv->lock, flags); + return rc; +} + +static irqreturn_t npcm_peci_irq_handler(int irq, void *arg) +{ + struct npcm_peci *priv = arg; + u32 status_ack = 0; + u32 status; + + spin_lock(&priv->lock); + regmap_read(priv->regmap, NPCM_PECI_CTL_STS, &status); + priv->status |= (status & NPCM_PECI_INT_MASK); + + if (status & NPCM_PECI_CTRL_CRC_ERR) { + dev_dbg(priv->dev, "PECI_INT_W_FCS_BAD\n"); + status_ack |= NPCM_PECI_CTRL_CRC_ERR; + } + + if (status & NPCM_PECI_CTRL_ABRT_ERR) { + dev_dbg(priv->dev, "NPCM_PECI_CTRL_ABRT_ERR\n"); + status_ack |= NPCM_PECI_CTRL_ABRT_ERR; + } + + /* + * All commands should be ended up with a NPCM_PECI_CTRL_DONE + * bit set even in an error case. + */ + if (status & NPCM_PECI_CTRL_DONE) { + dev_dbg(priv->dev, "NPCM_PECI_CTRL_DONE\n"); + status_ack |= NPCM_PECI_CTRL_DONE; + complete(&priv->xfer_complete); + } + + regmap_write_bits(priv->regmap, NPCM_PECI_CTL_STS, + NPCM_PECI_INT_MASK, status_ack); + + spin_unlock(&priv->lock); + return IRQ_HANDLED; +} + +static int npcm_peci_init_ctrl(struct npcm_peci *priv) +{ + u32 cmd_sts, host_neg_bit_rate = 0, pull_down = 0; + int ret; + bool volt; + + priv->clk = devm_clk_get(priv->dev, NULL); + if (IS_ERR(priv->clk)) { + dev_err(priv->dev, "Failed to get clk source.\n"); + return PTR_ERR(priv->clk); + } + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(priv->dev, "Failed to enable clock.\n"); + return ret; + } + + ret = of_property_read_u32(priv->dev->of_node, "cmd-timeout-ms", + &priv->cmd_timeout_ms); + if (ret || priv->cmd_timeout_ms > NPCM_PECI_CMD_TIMEOUT_MS_MAX || + priv->cmd_timeout_ms == 0) { + if (ret) + dev_warn(priv->dev, + "cmd-timeout-ms not found, use default : %u\n", + NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT); + else + dev_warn(priv->dev, + "Invalid cmd-timeout-ms : %u. Use default : %u\n", + priv->cmd_timeout_ms, + NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT); + + priv->cmd_timeout_ms = NPCM_PECI_CMD_TIMEOUT_MS_DEFAULT; + } + + if (of_device_is_compatible(priv->dev->of_node, + "nuvoton,npcm750-peci")) { + priv->gcr_regmap = syscon_regmap_lookup_by_compatible + ("nuvoton,npcm750-gcr"); + if (!IS_ERR(priv->gcr_regmap)) { + volt = of_property_read_bool(priv->dev->of_node, + "high-volt-range"); + if (volt) + regmap_update_bits(priv->gcr_regmap, + NPCM7XX_INTCR3_OFFSET, + NPCM7XX_INTCR3_PECIVSEL, + NPCM7XX_INTCR3_PECIVSEL); + else + regmap_update_bits(priv->gcr_regmap, + NPCM7XX_INTCR3_OFFSET, + NPCM7XX_INTCR3_PECIVSEL, 0); + } + } + + ret = of_property_read_u32(priv->dev->of_node, "pull-down", + &pull_down); + if (ret || pull_down > NPCM_PECI_PULL_DOWN_MAX) { + if (ret) + dev_warn(priv->dev, + "pull-down not found, use default : %u\n", + NPCM_PECI_PULL_DOWN_DEFAULT); + else + dev_warn(priv->dev, + "Invalid pull-down : %u. Use default : %u\n", + pull_down, + NPCM_PECI_PULL_DOWN_DEFAULT); + pull_down = NPCM_PECI_PULL_DOWN_DEFAULT; + } + + regmap_update_bits(priv->regmap, NPCM_PECI_CTL2, NPCM_PECI_CTL2_MASK, + pull_down << 6); + + ret = of_property_read_u32(priv->dev->of_node, "host-neg-bit-rate", + &host_neg_bit_rate); + if (ret || host_neg_bit_rate > NPCM_PECI_HOST_NEG_BIT_RATE_MAX || + host_neg_bit_rate < NPCM_PECI_HOST_NEG_BIT_RATE_MIN) { + if (ret) + dev_warn(priv->dev, + "host-neg-bit-rate not found, use default : %u\n", + NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT); + else + dev_warn(priv->dev, + "Invalid host-neg-bit-rate : %u. Use default : %u\n", + host_neg_bit_rate, + NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT); + host_neg_bit_rate = NPCM_PECI_HOST_NEG_BIT_RATE_DEFAULT; + } + + regmap_update_bits(priv->regmap, NPCM_PECI_PDDR, NPCM_PECI_PDDR_MASK, + host_neg_bit_rate); + + priv->host_bit_rate = clk_get_rate(priv->clk) / + (4 * (host_neg_bit_rate + 1)); + + ret = regmap_read_poll_timeout(priv->regmap, NPCM_PECI_CTL_STS, cmd_sts, + !(cmd_sts & NPCM_PECI_CTRL_START_BUSY), + NPCM_PECI_IDLE_CHECK_INTERVAL_USEC, + NPCM_PECI_IDLE_CHECK_TIMEOUT_USEC); + if (ret) + return ret; /* -ETIMEDOUT */ + + /* PECI interrupt enable */ + regmap_update_bits(priv->regmap, NPCM_PECI_CTL_STS, + NPCM_PECI_CTRL_DONE_INT_EN, + NPCM_PECI_CTRL_DONE_INT_EN); + + return 0; +} + +static const struct regmap_config npcm_peci_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = NPCM_PECI_MAX_REG, + .fast_io = true, +}; + +static int npcm_peci_xfer(struct peci_adapter *adapter, + struct peci_xfer_msg *msg) +{ + struct npcm_peci *priv = peci_get_adapdata(adapter); + + return npcm_peci_xfer_native(priv, msg); +} + +static int npcm_peci_probe(struct platform_device *pdev) +{ + struct peci_adapter *adapter; + struct npcm_peci *priv; + struct resource *res; + void __iomem *base; + int ret; + + adapter = peci_alloc_adapter(&pdev->dev, sizeof(*priv)); + if (!adapter) + return -ENOMEM; + + priv = peci_get_adapdata(adapter); + priv->adapter = adapter; + priv->dev = &pdev->dev; + dev_set_drvdata(&pdev->dev, priv); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + ret = PTR_ERR(base); + goto err_put_adapter_dev; + } + + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &npcm_peci_regmap_config); + if (IS_ERR(priv->regmap)) { + ret = PTR_ERR(priv->regmap); + goto err_put_adapter_dev; + } + + priv->irq = platform_get_irq(pdev, 0); + if (!priv->irq) { + ret = -ENODEV; + goto err_put_adapter_dev; + } + + ret = devm_request_irq(&pdev->dev, priv->irq, npcm_peci_irq_handler, + 0, "peci-npcm-irq", priv); + if (ret) + goto err_put_adapter_dev; + + init_completion(&priv->xfer_complete); + spin_lock_init(&priv->lock); + + priv->adapter->owner = THIS_MODULE; + priv->adapter->dev.of_node = of_node_get(dev_of_node(priv->dev)); + strlcpy(priv->adapter->name, pdev->name, sizeof(priv->adapter->name)); + priv->adapter->xfer = npcm_peci_xfer; + + ret = npcm_peci_init_ctrl(priv); + if (ret) + goto err_put_adapter_dev; + + ret = peci_add_adapter(priv->adapter); + if (ret) + goto err_put_adapter_dev; + + dev_info(&pdev->dev, "peci bus %d registered, host negotiation bit rate %dHz", + priv->adapter->nr, priv->host_bit_rate); + + return 0; + +err_put_adapter_dev: + put_device(&adapter->dev); + return ret; +} + +static int npcm_peci_remove(struct platform_device *pdev) +{ + struct npcm_peci *priv = dev_get_drvdata(&pdev->dev); + + clk_disable_unprepare(priv->clk); + peci_del_adapter(priv->adapter); + of_node_put(priv->adapter->dev.of_node); + + return 0; +} + +static const struct of_device_id npcm_peci_of_table[] = { + { .compatible = "nuvoton,npcm750-peci", }, + { } +}; +MODULE_DEVICE_TABLE(of, npcm_peci_of_table); + +static struct platform_driver npcm_peci_driver = { + .probe = npcm_peci_probe, + .remove = npcm_peci_remove, + .driver = { + .name = "peci-npcm", + .of_match_table = of_match_ptr(npcm_peci_of_table), + }, +}; +module_platform_driver(npcm_peci_driver); + +MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); +MODULE_DESCRIPTION("NPCM Platform Environment Control Interface (PECI) driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 4cf54172f8fb..de8b185c4fee 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -23,3 +23,11 @@ config PINCTRL_ASPEED_G5 help Say Y here to enable pin controller support for Aspeed's 5th generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G6 + bool "Aspeed G6 SoC pin control" + depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 6th + generation SoCs. GPIO is provided by a separate GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile index ea8962645e49..489ea1778353 100644 --- a/drivers/pinctrl/aspeed/Makefile +++ b/drivers/pinctrl/aspeed/Makefile @@ -5,3 +5,4 @@ ccflags-y += $(call cc-option,-Woverride-init) obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o +obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 22256576b69a..bfed0e274643 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -21,6 +21,13 @@ #include "pinmux-aspeed.h" #include "pinctrl-aspeed.h" +/* Wrap some of the common macros for clarity */ +#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \ + SIG_EXPR_DECL(sig, func, func, __VA_ARGS__) + +#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG +#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG + /* * The "Multi-function Pins Mapping and Control" table in the SoC datasheet * references registers by the device/offset mnemonic. The register macros @@ -80,16 +87,16 @@ SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); #define I2C9_DESC SIG_DESC_SET(SCU90, 22) #define C5 4 -SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); -MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5); +SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); +PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5); FUNC_GROUP_DECL(TIMER5, C5); #define B4 5 -SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); -MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6); +SIG_EXPR_LIST_DECL_SINGLE(B4, SDA9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B4, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); +PIN_DECL_2(B4, GPIOA5, SDA9, TIMER6); FUNC_GROUP_DECL(TIMER6, B4); FUNC_GROUP_DECL(I2C9, C5, B4); @@ -97,16 +104,16 @@ FUNC_GROUP_DECL(I2C9, C5, B4); #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) #define A3 6 -SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); -MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7); +SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); +PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7); FUNC_GROUP_DECL(TIMER7, A3); #define D5 7 -SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); -MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); +SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); +PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8); FUNC_GROUP_DECL(TIMER8, D5); FUNC_GROUP_DECL(MDIO2, A3, D5); @@ -124,18 +131,18 @@ SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10)); SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11)); #define E19 12 -SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); -SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); -SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS); -SS_PIN_DECL(E19, GPIOB4, LPCRST); +SIG_EXPR_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); +SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); +SIG_EXPR_LIST_DECL_DUAL(E19, LPCRST, LPCRST, LPCRSTS); +PIN_DECL_1(E19, GPIOB4, LPCRST); FUNC_GROUP_DECL(LPCRST, E19); #define H19 13 #define H19_DESC SIG_DESC_SET(SCU80, 13) -SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC); -MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI); +SIG_EXPR_LIST_DECL_SINGLE(H19, LPCPD, LPCPD, H19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(H19, LPCSMI, LPCSMI, H19_DESC); +PIN_DECL_2(H19, GPIOB5, LPCPD, LPCSMI); FUNC_GROUP_DECL(LPCPD, H19); FUNC_GROUP_DECL(LPCSMI, H19); @@ -144,14 +151,14 @@ FUNC_GROUP_DECL(LPCSMI, H19); SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); #define E18 15 -SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST, +SIG_EXPR_LIST_DECL_SINGLE(E18, EXTRST, EXTRST, SIG_DESC_SET(SCU80, 15), SIG_DESC_BIT(SCU90, 31, 0), SIG_DESC_SET(SCU3C, 3)); -SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1, +SIG_EXPR_LIST_DECL_SINGLE(E18, SPICS1, SPICS1, SIG_DESC_SET(SCU80, 15), SIG_DESC_SET(SCU90, 31)); -MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1); +PIN_DECL_2(E18, GPIOB7, EXTRST, SPICS1); FUNC_GROUP_DECL(EXTRST, E18); FUNC_GROUP_DECL(SPICS1, E18); @@ -160,56 +167,56 @@ FUNC_GROUP_DECL(SPICS1, E18); #define I2C10_DESC SIG_DESC_SET(SCU90, 23) #define C4 16 -SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); -MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10); +SIG_EXPR_LIST_DECL_SINGLE(C4, SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C4, SCL10, I2C10, I2C10_DESC); +PIN_DECL_2(C4, GPIOC0, SD1CLK, SCL10); #define B3 17 -SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); -MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10); +SIG_EXPR_LIST_DECL_SINGLE(B3, SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B3, SDA10, I2C10, I2C10_DESC); +PIN_DECL_2(B3, GPIOC1, SD1CMD, SDA10); FUNC_GROUP_DECL(I2C10, C4, B3); #define I2C11_DESC SIG_DESC_SET(SCU90, 24) #define A2 18 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); -MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11); +SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC); +PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11); #define E5 19 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); -MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11); +SIG_EXPR_LIST_DECL_SINGLE(E5, SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E5, SDA11, I2C11, I2C11_DESC); +PIN_DECL_2(E5, GPIOC3, SD1DAT1, SDA11); FUNC_GROUP_DECL(I2C11, A2, E5); #define I2C12_DESC SIG_DESC_SET(SCU90, 25) #define D4 20 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); -MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12); +SIG_EXPR_LIST_DECL_SINGLE(D4, SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D4, SCL12, I2C12, I2C12_DESC); +PIN_DECL_2(D4, GPIOC4, SD1DAT2, SCL12); #define C3 21 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); -MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12); +SIG_EXPR_LIST_DECL_SINGLE(C3, SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C3, SDA12, I2C12, I2C12_DESC); +PIN_DECL_2(C3, GPIOC5, SD1DAT3, SDA12); FUNC_GROUP_DECL(I2C12, D4, C3); #define I2C13_DESC SIG_DESC_SET(SCU90, 26) #define B2 22 -SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); -MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13); +SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC); +PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13); #define A1 23 -SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); -MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13); +SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC); +PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13); FUNC_GROUP_DECL(I2C13, B2, A1); FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); @@ -219,72 +226,72 @@ FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); #define GPID0_DESC SIG_DESC_SET(SCU8C, 8) #define A18 24 -SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); -MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN); +SIG_EXPR_LIST_DECL_SINGLE(A18, SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(A18, GPID0IN, GPID0, GPID); +PIN_DECL_2(A18, GPIOD0, SD2CLK, GPID0IN); #define D16 25 -SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); -MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); +SIG_EXPR_LIST_DECL_SINGLE(D16, SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(D16, GPID0OUT, GPID0, GPID); +PIN_DECL_2(D16, GPIOD1, SD2CMD, GPID0OUT); FUNC_GROUP_DECL(GPID0, A18, D16); #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) #define B17 26 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); -MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN); +SIG_EXPR_LIST_DECL_SINGLE(B17, SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(B17, GPID2IN, GPID2, GPID); +PIN_DECL_2(B17, GPIOD2, SD2DAT0, GPID2IN); #define A17 27 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); -MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT); +SIG_EXPR_LIST_DECL_SINGLE(A17, SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(A17, GPID2OUT, GPID2, GPID); +PIN_DECL_2(A17, GPIOD3, SD2DAT1, GPID2OUT); FUNC_GROUP_DECL(GPID2, B17, A17); #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) #define C16 28 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); -MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN); +SIG_EXPR_LIST_DECL_SINGLE(C16, SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(C16, GPID4IN, GPID4, GPID); +PIN_DECL_2(C16, GPIOD4, SD2DAT2, GPID4IN); #define B16 29 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); -MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT); +SIG_EXPR_LIST_DECL_SINGLE(B16, SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(B16, GPID4OUT, GPID4, GPID); +PIN_DECL_2(B16, GPIOD5, SD2DAT3, GPID4OUT); FUNC_GROUP_DECL(GPID4, C16, B16); #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) #define A16 30 -SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); -MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN); +SIG_EXPR_LIST_DECL_SINGLE(A16, SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(A16, GPID6IN, GPID6, GPID); +PIN_DECL_2(A16, GPIOD6, SD2CD, GPID6IN); #define E15 31 -SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); -MS_PIN_DECL(E15, GPIOD7, SD2WP, GPID6OUT); +SIG_EXPR_LIST_DECL_SINGLE(E15, SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(E15, GPID6OUT, GPID6, GPID); +PIN_DECL_2(E15, GPIOD7, SD2WP, GPID6OUT); FUNC_GROUP_DECL(GPID6, A16, E15); FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15); @@ -297,77 +304,77 @@ FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15); #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) #define D15 32 -SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); -SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); -MS_PIN_DECL(D15, GPIOE0, NCTS3, GPIE0IN); +SIG_EXPR_LIST_DECL_SINGLE(D15, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(D15, GPIE0IN, GPIE0, GPIE); +PIN_DECL_2(D15, GPIOE0, NCTS3, GPIE0IN); FUNC_GROUP_DECL(NCTS3, D15); #define C15 33 -SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); -SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); -MS_PIN_DECL(C15, GPIOE1, NDCD3, GPIE0OUT); +SIG_EXPR_LIST_DECL_SINGLE(C15, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(C15, GPIE0OUT, GPIE0, GPIE); +PIN_DECL_2(C15, GPIOE1, NDCD3, GPIE0OUT); FUNC_GROUP_DECL(NDCD3, C15); FUNC_GROUP_DECL(GPIE0, D15, C15); #define B15 34 -SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); -SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); -MS_PIN_DECL(B15, GPIOE2, NDSR3, GPIE2IN); +SIG_EXPR_LIST_DECL_SINGLE(B15, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B15, GPIE2IN, GPIE2, GPIE); +PIN_DECL_2(B15, GPIOE2, NDSR3, GPIE2IN); FUNC_GROUP_DECL(NDSR3, B15); #define A15 35 -SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); -SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); -MS_PIN_DECL(A15, GPIOE3, NRI3, GPIE2OUT); +SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE); +PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT); FUNC_GROUP_DECL(NRI3, A15); FUNC_GROUP_DECL(GPIE2, B15, A15); #define E14 36 -SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); -SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); -MS_PIN_DECL(E14, GPIOE4, NDTR3, GPIE4IN); +SIG_EXPR_LIST_DECL_SINGLE(E14, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(E14, GPIE4IN, GPIE4, GPIE); +PIN_DECL_2(E14, GPIOE4, NDTR3, GPIE4IN); FUNC_GROUP_DECL(NDTR3, E14); #define D14 37 -SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); -SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); -MS_PIN_DECL(D14, GPIOE5, NRTS3, GPIE4OUT); +SIG_EXPR_LIST_DECL_SINGLE(D14, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(D14, GPIE4OUT, GPIE4, GPIE); +PIN_DECL_2(D14, GPIOE5, NRTS3, GPIE4OUT); FUNC_GROUP_DECL(NRTS3, D14); FUNC_GROUP_DECL(GPIE4, E14, D14); #define C14 38 -SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); -SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); -MS_PIN_DECL(C14, GPIOE6, TXD3, GPIE6IN); +SIG_EXPR_LIST_DECL_SINGLE(C14, TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(C14, GPIE6IN, GPIE6, GPIE); +PIN_DECL_2(C14, GPIOE6, TXD3, GPIE6IN); FUNC_GROUP_DECL(TXD3, C14); #define B14 39 -SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); -SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); -MS_PIN_DECL(B14, GPIOE7, RXD3, GPIE6OUT); +SIG_EXPR_LIST_DECL_SINGLE(B14, RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B14, GPIE6OUT, GPIE6, GPIE); +PIN_DECL_2(B14, GPIOE7, RXD3, GPIE6OUT); FUNC_GROUP_DECL(RXD3, B14); FUNC_GROUP_DECL(GPIE6, C14, B14); @@ -378,29 +385,29 @@ SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24)); #define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0) #define B19 41 -SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); -SIG_EXPR_DECL(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); -SIG_EXPR_DECL(SIOPBI, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); -MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); +SIG_EXPR_LIST_DECL_SINGLE(B19, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(B19, SIOPBI, SIOPBI, ACPI); +PIN_DECL_2(B19, GPIOF1, NDCD4, SIOPBI); FUNC_GROUP_DECL(NDCD4, B19); FUNC_GROUP_DECL(SIOPBI, B19); #define A20 42 -SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); -SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); -SIG_EXPR_DECL(SIOPWRGD, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); -MS_PIN_DECL(A20, GPIOF2, NDSR4, SIOPWRGD); +SIG_EXPR_LIST_DECL_SINGLE(A20, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(A20, SIOPWRGD, SIOPWRGD, ACPI); +PIN_DECL_2(A20, GPIOF2, NDSR4, SIOPWRGD); FUNC_GROUP_DECL(NDSR4, A20); FUNC_GROUP_DECL(SIOPWRGD, A20); #define D17 43 -SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); -SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); -SIG_EXPR_DECL(SIOPBO, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); -MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); +SIG_EXPR_LIST_DECL_SINGLE(D17, NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); +SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(D17, SIOPBO, SIOPBO, ACPI); +PIN_DECL_2(D17, GPIOF3, NRI4, SIOPBO); FUNC_GROUP_DECL(NRI4, D17); FUNC_GROUP_DECL(SIOPBO, D17); @@ -408,11 +415,11 @@ FUNC_GROUP_DECL(SIOPBO, D17); SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28)); #define A19 45 -SIG_EXPR_LIST_DECL_SINGLE(NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); -SIG_EXPR_DECL(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); -SIG_EXPR_DECL(SIOSCI, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); -MS_PIN_DECL(A19, GPIOF5, NDTS4, SIOSCI); +SIG_EXPR_LIST_DECL_SINGLE(A19, NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); +SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); +SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(A19, SIOSCI, SIOSCI, ACPI); +PIN_DECL_2(A19, GPIOF5, NDTS4, SIOSCI); FUNC_GROUP_DECL(NDTS4, A19); FUNC_GROUP_DECL(SIOSCI, A19); @@ -435,17 +442,17 @@ SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2)); SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3)); #define B13 52 -SIG_EXPR_LIST_DECL_SINGLE(OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); -MS_PIN_DECL(B13, GPIOG4, OSCCLK, WDTRST1); +SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); +SIG_EXPR_LIST_DECL_SINGLE(B13, WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); +PIN_DECL_2(B13, GPIOG4, OSCCLK, WDTRST1); FUNC_GROUP_DECL(OSCCLK, B13); FUNC_GROUP_DECL(WDTRST1, B13); #define Y21 53 -SIG_EXPR_LIST_DECL_SINGLE(USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); -MS_PIN_DECL(Y21, GPIOG5, USBCKI, WDTRST2); +SIG_EXPR_LIST_DECL_SINGLE(Y21, USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); +SIG_EXPR_LIST_DECL_SINGLE(Y21, WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); +PIN_DECL_2(Y21, GPIOG5, USBCKI, WDTRST2); FUNC_GROUP_DECL(USBCKI, Y21); FUNC_GROUP_DECL(WDTRST2, Y21); @@ -462,60 +469,60 @@ SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); #define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 } #define A8 56 -SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD8, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, UART6_DESC); -MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); +SIG_EXPR_DECL_SINGLE(ROMD8, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC); +PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6); #define C7 57 -SIG_EXPR_DECL(ROMD9, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD9, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NDCD6, NDCD6, UART6_DESC); -MS_PIN_DECL(C7, GPIOH1, ROMD9, NDCD6); +SIG_EXPR_DECL_SINGLE(ROMD9, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(C7, ROMD9, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(C7, NDCD6, NDCD6, UART6_DESC); +PIN_DECL_2(C7, GPIOH1, ROMD9, NDCD6); #define B7 58 -SIG_EXPR_DECL(ROMD10, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD10, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NDSR6, NDSR6, UART6_DESC); -MS_PIN_DECL(B7, GPIOH2, ROMD10, NDSR6); +SIG_EXPR_DECL_SINGLE(ROMD10, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(B7, ROMD10, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(B7, NDSR6, NDSR6, UART6_DESC); +PIN_DECL_2(B7, GPIOH2, ROMD10, NDSR6); #define A7 59 -SIG_EXPR_DECL(ROMD11, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD11, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NRI6, NRI6, UART6_DESC); -MS_PIN_DECL(A7, GPIOH3, ROMD11, NRI6); +SIG_EXPR_DECL_SINGLE(ROMD11, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(A7, ROMD11, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(A7, NRI6, NRI6, UART6_DESC); +PIN_DECL_2(A7, GPIOH3, ROMD11, NRI6); #define D7 60 -SIG_EXPR_DECL(ROMD12, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD12, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NDTR6, NDTR6, UART6_DESC); -MS_PIN_DECL(D7, GPIOH4, ROMD12, NDTR6); +SIG_EXPR_DECL_SINGLE(ROMD12, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(D7, ROMD12, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(D7, NDTR6, NDTR6, UART6_DESC); +PIN_DECL_2(D7, GPIOH4, ROMD12, NDTR6); #define B6 61 -SIG_EXPR_DECL(ROMD13, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD13, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NRTS6, NRTS6, UART6_DESC); -MS_PIN_DECL(B6, GPIOH5, ROMD13, NRTS6); +SIG_EXPR_DECL_SINGLE(ROMD13, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(B6, ROMD13, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(B6, NRTS6, NRTS6, UART6_DESC); +PIN_DECL_2(B6, GPIOH5, ROMD13, NRTS6); #define A6 62 -SIG_EXPR_DECL(ROMD14, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD14, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(TXD6, TXD6, UART6_DESC); -MS_PIN_DECL(A6, GPIOH6, ROMD14, TXD6); +SIG_EXPR_DECL_SINGLE(ROMD14, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(A6, ROMD14, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(A6, TXD6, TXD6, UART6_DESC); +PIN_DECL_2(A6, GPIOH6, ROMD14, TXD6); #define E7 63 -SIG_EXPR_DECL(ROMD15, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD15, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(RXD6, RXD6, UART6_DESC); -MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); +SIG_EXPR_DECL_SINGLE(ROMD15, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(E7, ROMD15, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(E7, RXD6, RXD6, UART6_DESC); +PIN_DECL_2(E7, GPIOH7, ROMD15, RXD6); FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); @@ -527,70 +534,78 @@ FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } #define C22 64 -SIG_EXPR_DECL(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C22, GPIOI0, SYSCS); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C22, SYSCS, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C22, GPIOI0, SYSCS); #define G18 65 -SIG_EXPR_DECL(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(G18, GPIOI1, SYSCK); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(G18, SYSCK, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(G18, GPIOI1, SYSCK); #define D19 66 -SIG_EXPR_DECL(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSDO, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(D19, GPIOI2, SYSDO); +SIG_EXPR_DECL_SINGLE(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(D19, SYSDO, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(D19, GPIOI2, SYSDO); #define C20 67 -SIG_EXPR_DECL(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSDI, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C20, GPIOI3, SYSDI); +SIG_EXPR_DECL_SINGLE(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C20, SYSDI, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C20, GPIOI3, SYSDI); #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) #define B22 68 -SIG_EXPR_DECL(SPI1CS0, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CS0, SPI1, + SIG_EXPR_PTR(SPI1CS0, SPI1), SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(B22, GPIOI4, SPI1CS0, VBCS); +SIG_EXPR_LIST_ALIAS(B22, SPI1CS0, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(B22, VBCS, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(B22, GPIOI4, SPI1CS0, VBCS); #define G19 69 -SIG_EXPR_DECL(SPI1CK, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CK, SPI1, + SIG_EXPR_PTR(SPI1CK, SPI1), SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(G19, GPIOI5, SPI1CK, VBCK); +SIG_EXPR_LIST_ALIAS(G19, SPI1CK, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(G19, VBCK, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(G19, GPIOI5, SPI1CK, VBCK); #define C18 70 -SIG_EXPR_DECL(SPI1DO, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1DO, SIG_EXPR_PTR(SPI1DO, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DO, SPI1, + SIG_EXPR_PTR(SPI1DO, SPI1), SIG_EXPR_PTR(SPI1DO, SPI1DEBUG), SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBDO, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(C18, GPIOI6, SPI1DO, VBDO); +SIG_EXPR_LIST_ALIAS(C18, SPI1DO, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(C18, VBDO, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(C18, GPIOI6, SPI1DO, VBDO); #define E20 71 -SIG_EXPR_DECL(SPI1DI, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1DI, SIG_EXPR_PTR(SPI1DI, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DI, SPI1, + SIG_EXPR_PTR(SPI1DI, SPI1), SIG_EXPR_PTR(SPI1DI, SPI1DEBUG), SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBDI, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(E20, GPIOI7, SPI1DI, VBDI); +SIG_EXPR_LIST_ALIAS(E20, SPI1DI, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(E20, VBDI, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(E20, GPIOI7, SPI1DI, VBDI); FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20); FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20); @@ -624,48 +639,48 @@ SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15)); #define I2C5_DESC SIG_DESC_SET(SCU90, 18) #define E3 80 -SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); -SS_PIN_DECL(E3, GPIOK0, SCL5); +SIG_EXPR_LIST_DECL_SINGLE(E3, SCL5, I2C5, I2C5_DESC); +PIN_DECL_1(E3, GPIOK0, SCL5); #define D2 81 -SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); -SS_PIN_DECL(D2, GPIOK1, SDA5); +SIG_EXPR_LIST_DECL_SINGLE(D2, SDA5, I2C5, I2C5_DESC); +PIN_DECL_1(D2, GPIOK1, SDA5); FUNC_GROUP_DECL(I2C5, E3, D2); #define I2C6_DESC SIG_DESC_SET(SCU90, 19) #define C1 82 -SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); -SS_PIN_DECL(C1, GPIOK2, SCL6); +SIG_EXPR_LIST_DECL_SINGLE(C1, SCL6, I2C6, I2C6_DESC); +PIN_DECL_1(C1, GPIOK2, SCL6); #define F4 83 -SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); -SS_PIN_DECL(F4, GPIOK3, SDA6); +SIG_EXPR_LIST_DECL_SINGLE(F4, SDA6, I2C6, I2C6_DESC); +PIN_DECL_1(F4, GPIOK3, SDA6); FUNC_GROUP_DECL(I2C6, C1, F4); #define I2C7_DESC SIG_DESC_SET(SCU90, 20) #define E2 84 -SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); -SS_PIN_DECL(E2, GPIOK4, SCL7); +SIG_EXPR_LIST_DECL_SINGLE(E2, SCL7, I2C7, I2C7_DESC); +PIN_DECL_1(E2, GPIOK4, SCL7); #define D1 85 -SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); -SS_PIN_DECL(D1, GPIOK5, SDA7); +SIG_EXPR_LIST_DECL_SINGLE(D1, SDA7, I2C7, I2C7_DESC); +PIN_DECL_1(D1, GPIOK5, SDA7); FUNC_GROUP_DECL(I2C7, E2, D1); #define I2C8_DESC SIG_DESC_SET(SCU90, 21) #define G5 86 -SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); -SS_PIN_DECL(G5, GPIOK6, SCL8); +SIG_EXPR_LIST_DECL_SINGLE(G5, SCL8, I2C8, I2C8_DESC); +PIN_DECL_1(G5, GPIOK6, SCL8); #define F3 87 -SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); -SS_PIN_DECL(F3, GPIOK7, SDA8); +SIG_EXPR_LIST_DECL_SINGLE(F3, SDA8, I2C8, I2C8_DESC); +PIN_DECL_1(F3, GPIOK7, SDA8); FUNC_GROUP_DECL(I2C8, G5, F3); @@ -678,297 +693,341 @@ SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); #define T5 89 #define T5_DESC SIG_DESC_SET(SCU84, 17) -SIG_EXPR_DECL(VPIDE, VPI18, VPI18_DESC, T5_DESC); -SIG_EXPR_DECL(VPIDE, VPI24, VPI24_DESC, T5_DESC); -SIG_EXPR_DECL(VPIDE, VPI30, VPI30_DESC, T5_DESC); -SIG_EXPR_LIST_DECL(VPIDE, SIG_EXPR_PTR(VPIDE, VPI18), - SIG_EXPR_PTR(VPIDE, VPI24), - SIG_EXPR_PTR(VPIDE, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T5_DESC); -MS_PIN_DECL(T5, GPIOL1, VPIDE, NDCD1); +SIG_EXPR_DECL_SINGLE(VPIDE, VPI18, VPI18_DESC, T5_DESC); +SIG_EXPR_DECL_SINGLE(VPIDE, VPI24, VPI24_DESC, T5_DESC); +SIG_EXPR_DECL_SINGLE(VPIDE, VPI30, VPI30_DESC, T5_DESC); +SIG_EXPR_LIST_DECL(VPIDE, VPI, + SIG_EXPR_PTR(VPIDE, VPI18), + SIG_EXPR_PTR(VPIDE, VPI24), + SIG_EXPR_PTR(VPIDE, VPI30)); +SIG_EXPR_LIST_ALIAS(T5, VPIDE, VPI); +SIG_EXPR_LIST_DECL_SINGLE(T5, NDCD1, NDCD1, T5_DESC); +PIN_DECL_2(T5, GPIOL1, VPIDE, NDCD1); FUNC_GROUP_DECL(NDCD1, T5); #define U3 90 #define U3_DESC SIG_DESC_SET(SCU84, 18) -SIG_EXPR_DECL(VPIODD, VPI18, VPI18_DESC, U3_DESC); -SIG_EXPR_DECL(VPIODD, VPI24, VPI24_DESC, U3_DESC); -SIG_EXPR_DECL(VPIODD, VPI30, VPI30_DESC, U3_DESC); -SIG_EXPR_LIST_DECL(VPIODD, SIG_EXPR_PTR(VPIODD, VPI18), +SIG_EXPR_DECL_SINGLE(VPIODD, VPI18, VPI18_DESC, U3_DESC); +SIG_EXPR_DECL_SINGLE(VPIODD, VPI24, VPI24_DESC, U3_DESC); +SIG_EXPR_DECL_SINGLE(VPIODD, VPI30, VPI30_DESC, U3_DESC); +SIG_EXPR_LIST_DECL(VPIODD, VPI, + SIG_EXPR_PTR(VPIODD, VPI18), SIG_EXPR_PTR(VPIODD, VPI24), SIG_EXPR_PTR(VPIODD, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U3_DESC); -MS_PIN_DECL(U3, GPIOL2, VPIODD, NDSR1); +SIG_EXPR_LIST_ALIAS(U3, VPIODD, VPI); +SIG_EXPR_LIST_DECL_SINGLE(U3, NDSR1, NDSR1, U3_DESC); +PIN_DECL_2(U3, GPIOL2, VPIODD, NDSR1); FUNC_GROUP_DECL(NDSR1, U3); #define V1 91 #define V1_DESC SIG_DESC_SET(SCU84, 19) -SIG_EXPR_DECL(VPIHS, VPI18, VPI18_DESC, V1_DESC); -SIG_EXPR_DECL(VPIHS, VPI24, VPI24_DESC, V1_DESC); -SIG_EXPR_DECL(VPIHS, VPI30, VPI30_DESC, V1_DESC); -SIG_EXPR_LIST_DECL(VPIHS, SIG_EXPR_PTR(VPIHS, VPI18), +SIG_EXPR_DECL_SINGLE(VPIHS, VPI18, VPI18_DESC, V1_DESC); +SIG_EXPR_DECL_SINGLE(VPIHS, VPI24, VPI24_DESC, V1_DESC); +SIG_EXPR_DECL_SINGLE(VPIHS, VPI30, VPI30_DESC, V1_DESC); +SIG_EXPR_LIST_DECL(VPIHS, VPI, + SIG_EXPR_PTR(VPIHS, VPI18), SIG_EXPR_PTR(VPIHS, VPI24), SIG_EXPR_PTR(VPIHS, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, V1_DESC); -MS_PIN_DECL(V1, GPIOL3, VPIHS, NRI1); +SIG_EXPR_LIST_ALIAS(V1, VPIHS, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V1, NRI1, NRI1, V1_DESC); +PIN_DECL_2(V1, GPIOL3, VPIHS, NRI1); FUNC_GROUP_DECL(NRI1, V1); #define U4 92 #define U4_DESC SIG_DESC_SET(SCU84, 20) -SIG_EXPR_DECL(VPIVS, VPI18, VPI18_DESC, U4_DESC); -SIG_EXPR_DECL(VPIVS, VPI24, VPI24_DESC, U4_DESC); -SIG_EXPR_DECL(VPIVS, VPI30, VPI30_DESC, U4_DESC); -SIG_EXPR_LIST_DECL(VPIVS, SIG_EXPR_PTR(VPIVS, VPI18), +SIG_EXPR_DECL_SINGLE(VPIVS, VPI18, VPI18_DESC, U4_DESC); +SIG_EXPR_DECL_SINGLE(VPIVS, VPI24, VPI24_DESC, U4_DESC); +SIG_EXPR_DECL_SINGLE(VPIVS, VPI30, VPI30_DESC, U4_DESC); +SIG_EXPR_LIST_DECL(VPIVS, VPI, + SIG_EXPR_PTR(VPIVS, VPI18), SIG_EXPR_PTR(VPIVS, VPI24), SIG_EXPR_PTR(VPIVS, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, U4_DESC); -MS_PIN_DECL(U4, GPIOL4, VPIVS, NDTR1); +SIG_EXPR_LIST_ALIAS(U4, VPIVS, VPI); +SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC); +PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1); FUNC_GROUP_DECL(NDTR1, U4); #define V2 93 #define V2_DESC SIG_DESC_SET(SCU84, 21) -SIG_EXPR_DECL(VPICLK, VPI18, VPI18_DESC, V2_DESC); -SIG_EXPR_DECL(VPICLK, VPI24, VPI24_DESC, V2_DESC); -SIG_EXPR_DECL(VPICLK, VPI30, VPI30_DESC, V2_DESC); -SIG_EXPR_LIST_DECL(VPICLK, SIG_EXPR_PTR(VPICLK, VPI18), +SIG_EXPR_DECL_SINGLE(VPICLK, VPI18, VPI18_DESC, V2_DESC); +SIG_EXPR_DECL_SINGLE(VPICLK, VPI24, VPI24_DESC, V2_DESC); +SIG_EXPR_DECL_SINGLE(VPICLK, VPI30, VPI30_DESC, V2_DESC); +SIG_EXPR_LIST_DECL(VPICLK, VPI, + SIG_EXPR_PTR(VPICLK, VPI18), SIG_EXPR_PTR(VPICLK, VPI24), SIG_EXPR_PTR(VPICLK, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, V2_DESC); -MS_PIN_DECL(V2, GPIOL5, VPICLK, NRTS1); +SIG_EXPR_LIST_ALIAS(V2, VPICLK, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V2, NRTS1, NRTS1, V2_DESC); +PIN_DECL_2(V2, GPIOL5, VPICLK, NRTS1); FUNC_GROUP_DECL(NRTS1, V2); #define W1 94 #define W1_DESC SIG_DESC_SET(SCU84, 22) -SIG_EXPR_LIST_DECL_SINGLE(VPIB0, VPI30, VPI30_DESC, W1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, W1_DESC); -MS_PIN_DECL(W1, GPIOL6, VPIB0, TXD1); +SIG_EXPR_LIST_DECL_SINGLE(W1, VPIB0, VPI30, VPI30_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W1, TXD1, TXD1, W1_DESC); +PIN_DECL_2(W1, GPIOL6, VPIB0, TXD1); FUNC_GROUP_DECL(TXD1, W1); #define U5 95 #define U5_DESC SIG_DESC_SET(SCU84, 23) -SIG_EXPR_LIST_DECL_SINGLE(VPIB1, VPI30, VPI30_DESC, U5_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC); -MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1); +SIG_EXPR_LIST_DECL_SINGLE(U5, VPIB1, VPI30, VPI30_DESC, U5_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U5, RXD1, RXD1, U5_DESC); +PIN_DECL_2(U5, GPIOL7, VPIB1, RXD1); FUNC_GROUP_DECL(RXD1, U5); #define V3 96 #define V3_DESC SIG_DESC_SET(SCU84, 24) -SIG_EXPR_DECL(VPIOB2, VPI18, VPI18_DESC, V3_DESC); -SIG_EXPR_DECL(VPIOB2, VPI24, VPI24_DESC, V3_DESC); -SIG_EXPR_DECL(VPIOB2, VPI30, VPI30_DESC, V3_DESC); -SIG_EXPR_LIST_DECL(VPIOB2, SIG_EXPR_PTR(VPIOB2, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB2, VPI18, VPI18_DESC, V3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB2, VPI24, VPI24_DESC, V3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB2, VPI30, VPI30_DESC, V3_DESC); +SIG_EXPR_LIST_DECL(VPIOB2, VPI, + SIG_EXPR_PTR(VPIOB2, VPI18), SIG_EXPR_PTR(VPIOB2, VPI24), SIG_EXPR_PTR(VPIOB2, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, V3_DESC); -MS_PIN_DECL(V3, GPIOM0, VPIOB2, NCTS2); +SIG_EXPR_LIST_ALIAS(V3, VPIOB2, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V3, NCTS2, NCTS2, V3_DESC); +PIN_DECL_2(V3, GPIOM0, VPIOB2, NCTS2); FUNC_GROUP_DECL(NCTS2, V3); #define W2 97 #define W2_DESC SIG_DESC_SET(SCU84, 25) -SIG_EXPR_DECL(VPIOB3, VPI18, VPI18_DESC, W2_DESC); -SIG_EXPR_DECL(VPIOB3, VPI24, VPI24_DESC, W2_DESC); -SIG_EXPR_DECL(VPIOB3, VPI30, VPI30_DESC, W2_DESC); -SIG_EXPR_LIST_DECL(VPIOB3, SIG_EXPR_PTR(VPIOB3, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB3, VPI18, VPI18_DESC, W2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB3, VPI24, VPI24_DESC, W2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB3, VPI30, VPI30_DESC, W2_DESC); +SIG_EXPR_LIST_DECL(VPIOB3, VPI, + SIG_EXPR_PTR(VPIOB3, VPI18), SIG_EXPR_PTR(VPIOB3, VPI24), SIG_EXPR_PTR(VPIOB3, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, W2_DESC); -MS_PIN_DECL(W2, GPIOM1, VPIOB3, NDCD2); +SIG_EXPR_LIST_ALIAS(W2, VPIOB3, VPI); +SIG_EXPR_LIST_DECL_SINGLE(W2, NDCD2, NDCD2, W2_DESC); +PIN_DECL_2(W2, GPIOM1, VPIOB3, NDCD2); FUNC_GROUP_DECL(NDCD2, W2); #define Y1 98 #define Y1_DESC SIG_DESC_SET(SCU84, 26) -SIG_EXPR_DECL(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); -SIG_EXPR_DECL(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); -SIG_EXPR_DECL(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); -SIG_EXPR_LIST_DECL(VPIOB4, SIG_EXPR_PTR(VPIOB4, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); +SIG_EXPR_LIST_DECL(VPIOB4, VPI, + SIG_EXPR_PTR(VPIOB4, VPI18), SIG_EXPR_PTR(VPIOB4, VPI24), SIG_EXPR_PTR(VPIOB4, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, Y1_DESC); -MS_PIN_DECL(Y1, GPIOM2, VPIOB4, NDSR2); +SIG_EXPR_LIST_ALIAS(Y1, VPIOB4, VPI); +SIG_EXPR_LIST_DECL_SINGLE(Y1, NDSR2, NDSR2, Y1_DESC); +PIN_DECL_2(Y1, GPIOM2, VPIOB4, NDSR2); FUNC_GROUP_DECL(NDSR2, Y1); #define V4 99 #define V4_DESC SIG_DESC_SET(SCU84, 27) -SIG_EXPR_DECL(VPIOB5, VPI18, VPI18_DESC, V4_DESC); -SIG_EXPR_DECL(VPIOB5, VPI24, VPI24_DESC, V4_DESC); -SIG_EXPR_DECL(VPIOB5, VPI30, VPI30_DESC, V4_DESC); -SIG_EXPR_LIST_DECL(VPIOB5, SIG_EXPR_PTR(VPIOB5, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB5, VPI18, VPI18_DESC, V4_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB5, VPI24, VPI24_DESC, V4_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB5, VPI30, VPI30_DESC, V4_DESC); +SIG_EXPR_LIST_DECL(VPIOB5, VPI, + SIG_EXPR_PTR(VPIOB5, VPI18), SIG_EXPR_PTR(VPIOB5, VPI24), SIG_EXPR_PTR(VPIOB5, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, V4_DESC); -MS_PIN_DECL(V4, GPIOM3, VPIOB5, NRI2); +SIG_EXPR_LIST_ALIAS(V4, VPIOB5, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V4, NRI2, NRI2, V4_DESC); +PIN_DECL_2(V4, GPIOM3, VPIOB5, NRI2); FUNC_GROUP_DECL(NRI2, V4); #define W3 100 #define W3_DESC SIG_DESC_SET(SCU84, 28) -SIG_EXPR_DECL(VPIOB6, VPI18, VPI18_DESC, W3_DESC); -SIG_EXPR_DECL(VPIOB6, VPI24, VPI24_DESC, W3_DESC); -SIG_EXPR_DECL(VPIOB6, VPI30, VPI30_DESC, W3_DESC); -SIG_EXPR_LIST_DECL(VPIOB6, SIG_EXPR_PTR(VPIOB6, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB6, VPI18, VPI18_DESC, W3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB6, VPI24, VPI24_DESC, W3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB6, VPI30, VPI30_DESC, W3_DESC); +SIG_EXPR_LIST_DECL(VPIOB6, VPI, + SIG_EXPR_PTR(VPIOB6, VPI18), SIG_EXPR_PTR(VPIOB6, VPI24), SIG_EXPR_PTR(VPIOB6, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, W3_DESC); -MS_PIN_DECL(W3, GPIOM4, VPIOB6, NDTR2); +SIG_EXPR_LIST_ALIAS(W3, VPIOB6, VPI); +SIG_EXPR_LIST_DECL_SINGLE(W3, NDTR2, NDTR2, W3_DESC); +PIN_DECL_2(W3, GPIOM4, VPIOB6, NDTR2); FUNC_GROUP_DECL(NDTR2, W3); #define Y2 101 #define Y2_DESC SIG_DESC_SET(SCU84, 29) -SIG_EXPR_DECL(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); -SIG_EXPR_DECL(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); -SIG_EXPR_DECL(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); -SIG_EXPR_LIST_DECL(VPIOB7, SIG_EXPR_PTR(VPIOB7, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); +SIG_EXPR_LIST_DECL(VPIOB7, VPI, + SIG_EXPR_PTR(VPIOB7, VPI18), SIG_EXPR_PTR(VPIOB7, VPI24), SIG_EXPR_PTR(VPIOB7, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, Y2_DESC); -MS_PIN_DECL(Y2, GPIOM5, VPIOB7, NRTS2); +SIG_EXPR_LIST_ALIAS(Y2, VPIOB7, VPI); +SIG_EXPR_LIST_DECL_SINGLE(Y2, NRTS2, NRTS2, Y2_DESC); +PIN_DECL_2(Y2, GPIOM5, VPIOB7, NRTS2); FUNC_GROUP_DECL(NRTS2, Y2); #define AA1 102 #define AA1_DESC SIG_DESC_SET(SCU84, 30) -SIG_EXPR_DECL(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); -SIG_EXPR_DECL(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); -SIG_EXPR_DECL(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); -SIG_EXPR_LIST_DECL(VPIOB8, SIG_EXPR_PTR(VPIOB8, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); +SIG_EXPR_LIST_DECL(VPIOB8, VPI, + SIG_EXPR_PTR(VPIOB8, VPI18), SIG_EXPR_PTR(VPIOB8, VPI24), SIG_EXPR_PTR(VPIOB8, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, AA1_DESC); -MS_PIN_DECL(AA1, GPIOM6, VPIOB8, TXD2); +SIG_EXPR_LIST_ALIAS(AA1, VPIOB8, VPI); +SIG_EXPR_LIST_DECL_SINGLE(AA1, TXD2, TXD2, AA1_DESC); +PIN_DECL_2(AA1, GPIOM6, VPIOB8, TXD2); FUNC_GROUP_DECL(TXD2, AA1); #define V5 103 #define V5_DESC SIG_DESC_SET(SCU84, 31) -SIG_EXPR_DECL(VPIOB9, VPI18, VPI18_DESC, V5_DESC); -SIG_EXPR_DECL(VPIOB9, VPI24, VPI24_DESC, V5_DESC); -SIG_EXPR_DECL(VPIOB9, VPI30, VPI30_DESC, V5_DESC); -SIG_EXPR_LIST_DECL(VPIOB9, SIG_EXPR_PTR(VPIOB9, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB9, VPI18, VPI18_DESC, V5_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB9, VPI24, VPI24_DESC, V5_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB9, VPI30, VPI30_DESC, V5_DESC); +SIG_EXPR_LIST_DECL(VPIOB9, VPI, + SIG_EXPR_PTR(VPIOB9, VPI18), SIG_EXPR_PTR(VPIOB9, VPI24), SIG_EXPR_PTR(VPIOB9, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, V5_DESC); -MS_PIN_DECL(V5, GPIOM7, VPIOB9, RXD2); +SIG_EXPR_LIST_ALIAS(V5, VPIOB9, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V5, RXD2, RXD2, V5_DESC); +PIN_DECL_2(V5, GPIOM7, VPIOB9, RXD2); FUNC_GROUP_DECL(RXD2, V5); #define W4 104 #define W4_DESC SIG_DESC_SET(SCU88, 0) -SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, W4_DESC); -MS_PIN_DECL(W4, GPION0, VPIG0, PWM0); +SIG_EXPR_LIST_DECL_SINGLE(W4, VPIG0, VPI30, VPI30_DESC, W4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W4, PWM0, PWM0, W4_DESC); +PIN_DECL_2(W4, GPION0, VPIG0, PWM0); FUNC_GROUP_DECL(PWM0, W4); #define Y3 105 #define Y3_DESC SIG_DESC_SET(SCU88, 1) -SIG_EXPR_LIST_DECL_SINGLE(VPIG1, VPI30, VPI30_DESC, Y3_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, Y3_DESC); -MS_PIN_DECL(Y3, GPION1, VPIG1, PWM1); +SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG1, VPI30, VPI30_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM1, PWM1, Y3_DESC); +PIN_DECL_2(Y3, GPION1, VPIG1, PWM1); FUNC_GROUP_DECL(PWM1, Y3); #define AA2 106 #define AA2_DESC SIG_DESC_SET(SCU88, 2) -SIG_EXPR_DECL(VPIG2, VPI18, VPI18_DESC, AA2_DESC); -SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, AA2_DESC); -SIG_EXPR_DECL(VPIG2, VPI30, VPI30_DESC, AA2_DESC); -SIG_EXPR_LIST_DECL(VPIG2, SIG_EXPR_PTR(VPIG2, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG2, VPI18, VPI18_DESC, AA2_DESC); +SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, AA2_DESC); +SIG_EXPR_DECL_SINGLE(VPIG2, VPI30, VPI30_DESC, AA2_DESC); +SIG_EXPR_LIST_DECL(VPIG2, VPI, + SIG_EXPR_PTR(VPIG2, VPI18), SIG_EXPR_PTR(VPIG2, VPI24), SIG_EXPR_PTR(VPIG2, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, AA2_DESC); -MS_PIN_DECL(AA2, GPION2, VPIG2, PWM2); +SIG_EXPR_LIST_ALIAS(AA2, VPIG2, VPI); +SIG_EXPR_LIST_DECL_SINGLE(AA2, PWM2, PWM2, AA2_DESC); +PIN_DECL_2(AA2, GPION2, VPIG2, PWM2); FUNC_GROUP_DECL(PWM2, AA2); #define AB1 107 #define AB1_DESC SIG_DESC_SET(SCU88, 3) -SIG_EXPR_DECL(VPIG3, VPI18, VPI18_DESC, AB1_DESC); -SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, AB1_DESC); -SIG_EXPR_DECL(VPIG3, VPI30, VPI30_DESC, AB1_DESC); -SIG_EXPR_LIST_DECL(VPIG3, SIG_EXPR_PTR(VPIG3, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG3, VPI18, VPI18_DESC, AB1_DESC); +SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, AB1_DESC); +SIG_EXPR_DECL_SINGLE(VPIG3, VPI30, VPI30_DESC, AB1_DESC); +SIG_EXPR_LIST_DECL(VPIG3, VPI, + SIG_EXPR_PTR(VPIG3, VPI18), SIG_EXPR_PTR(VPIG3, VPI24), SIG_EXPR_PTR(VPIG3, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, AB1_DESC); -MS_PIN_DECL(AB1, GPION3, VPIG3, PWM3); +SIG_EXPR_LIST_ALIAS(AB1, VPIG3, VPI); +SIG_EXPR_LIST_DECL_SINGLE(AB1, PWM3, PWM3, AB1_DESC); +PIN_DECL_2(AB1, GPION3, VPIG3, PWM3); FUNC_GROUP_DECL(PWM3, AB1); #define W5 108 #define W5_DESC SIG_DESC_SET(SCU88, 4) -SIG_EXPR_DECL(VPIG4, VPI18, VPI18_DESC, W5_DESC); -SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W5_DESC); -SIG_EXPR_DECL(VPIG4, VPI30, VPI30_DESC, W5_DESC); -SIG_EXPR_LIST_DECL(VPIG4, SIG_EXPR_PTR(VPIG4, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG4, VPI18, VPI18_DESC, W5_DESC); +SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W5_DESC); +SIG_EXPR_DECL_SINGLE(VPIG4, VPI30, VPI30_DESC, W5_DESC); +SIG_EXPR_LIST_DECL(VPIG4, VPI, + SIG_EXPR_PTR(VPIG4, VPI18), SIG_EXPR_PTR(VPIG4, VPI24), SIG_EXPR_PTR(VPIG4, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W5_DESC); -MS_PIN_DECL(W5, GPION4, VPIG4, PWM4); +SIG_EXPR_LIST_ALIAS(W5, VPIG4, VPI); +SIG_EXPR_LIST_DECL_SINGLE(W5, PWM4, PWM4, W5_DESC); +PIN_DECL_2(W5, GPION4, VPIG4, PWM4); FUNC_GROUP_DECL(PWM4, W5); #define Y4 109 #define Y4_DESC SIG_DESC_SET(SCU88, 5) -SIG_EXPR_DECL(VPIG5, VPI18, VPI18_DESC, Y4_DESC); -SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, Y4_DESC); -SIG_EXPR_DECL(VPIG5, VPI30, VPI30_DESC, Y4_DESC); -SIG_EXPR_LIST_DECL(VPIG5, SIG_EXPR_PTR(VPIG5, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG5, VPI18, VPI18_DESC, Y4_DESC); +SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, Y4_DESC); +SIG_EXPR_DECL_SINGLE(VPIG5, VPI30, VPI30_DESC, Y4_DESC); +SIG_EXPR_LIST_DECL(VPIG5, VPI, + SIG_EXPR_PTR(VPIG5, VPI18), SIG_EXPR_PTR(VPIG5, VPI24), SIG_EXPR_PTR(VPIG5, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, Y4_DESC); -MS_PIN_DECL(Y4, GPION5, VPIG5, PWM5); +SIG_EXPR_LIST_ALIAS(Y4, VPIG5, VPI); +SIG_EXPR_LIST_DECL_SINGLE(Y4, PWM5, PWM5, Y4_DESC); +PIN_DECL_2(Y4, GPION5, VPIG5, PWM5); FUNC_GROUP_DECL(PWM5, Y4); #define AA3 110 #define AA3_DESC SIG_DESC_SET(SCU88, 6) -SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI30, VPI30_DESC, AA3_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, AA3_DESC); -MS_PIN_DECL(AA3, GPION6, VPIG6, PWM6); +SIG_EXPR_LIST_DECL_SINGLE(AA3, VPIG6, VPI30, VPI30_DESC, AA3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM6, PWM6, AA3_DESC); +PIN_DECL_2(AA3, GPION6, VPIG6, PWM6); FUNC_GROUP_DECL(PWM6, AA3); #define AB2 111 #define AB2_DESC SIG_DESC_SET(SCU88, 7) -SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI30, VPI30_DESC, AB2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, AB2_DESC); -MS_PIN_DECL(AB2, GPION7, VPIG7, PWM7); +SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIG7, VPI30, VPI30_DESC, AB2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB2, PWM7, PWM7, AB2_DESC); +PIN_DECL_2(AB2, GPION7, VPIG7, PWM7); FUNC_GROUP_DECL(PWM7, AB2); #define V6 112 -SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); -SS_PIN_DECL(V6, GPIOO0, VPIG8); +SIG_EXPR_LIST_DECL_SINGLE(V6, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); +PIN_DECL_1(V6, GPIOO0, VPIG8); #define Y5 113 -SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); -SS_PIN_DECL(Y5, GPIOO1, VPIG9); +SIG_EXPR_LIST_DECL_SINGLE(Y5, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); +PIN_DECL_1(Y5, GPIOO1, VPIG9); #define AA4 114 -SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10)); -SS_PIN_DECL(AA4, GPIOO2, VPIR0); +SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR0, VPI30, VPI30_DESC, + SIG_DESC_SET(SCU88, 10)); +PIN_DECL_1(AA4, GPIOO2, VPIR0); #define AB3 115 -SIG_EXPR_LIST_DECL_SINGLE(VPIR1, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 11)); -SS_PIN_DECL(AB3, GPIOO3, VPIR1); +SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR1, VPI30, VPI30_DESC, + SIG_DESC_SET(SCU88, 11)); +PIN_DECL_1(AB3, GPIOO3, VPIR1); #define W6 116 -SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12)); -SS_PIN_DECL(W6, GPIOO4, VPIR2); +SIG_EXPR_LIST_DECL_SINGLE(W6, VPIR2, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 12)); +PIN_DECL_1(W6, GPIOO4, VPIR2); #define AA5 117 -SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13)); -SS_PIN_DECL(AA5, GPIOO5, VPIR3); +SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR3, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 13)); +PIN_DECL_1(AA5, GPIOO5, VPIR3); #define AB4 118 -SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14)); -SS_PIN_DECL(AB4, GPIOO6, VPIR4); +SIG_EXPR_LIST_DECL_SINGLE(AB4, VPIR4, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 14)); +PIN_DECL_1(AB4, GPIOO6, VPIR4); #define V7 119 -SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15)); -SS_PIN_DECL(V7, GPIOO7, VPIR5); +SIG_EXPR_LIST_DECL_SINGLE(V7, VPIR5, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 15)); +PIN_DECL_1(V7, GPIOO7, VPIR5); #define Y6 120 -SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16)); -SS_PIN_DECL(Y6, GPIOP0, VPIR6); +SIG_EXPR_LIST_DECL_SINGLE(Y6, VPIR6, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 16)); +PIN_DECL_1(Y6, GPIOP0, VPIR6); #define AB5 121 -SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17)); -SS_PIN_DECL(AB5, GPIOP1, VPIR7); +SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR7, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 17)); +PIN_DECL_1(AB5, GPIOP1, VPIR7); #define W7 122 -SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18)); -SS_PIN_DECL(W7, GPIOP2, VPIR8); +SIG_EXPR_LIST_DECL_SINGLE(W7, VPIR8, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 18)); +PIN_DECL_1(W7, GPIOP2, VPIR8); #define AA6 123 -SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19)); -SS_PIN_DECL(AA6, GPIOP3, VPIR9); +SIG_EXPR_LIST_DECL_SINGLE(AA6, VPIR9, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 19)); +PIN_DECL_1(AA6, GPIOP3, VPIR9); FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, AA22, W5, Y4, AA3, AB2); @@ -979,12 +1038,12 @@ FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1, V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3); #define AB6 124 -SIG_EXPR_LIST_DECL_SINGLE(GPIOP4, GPIOP4); -MS_PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(GPIOP4)); +SIG_EXPR_LIST_DECL_SINGLE(AB6, GPIOP4, GPIOP4); +PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(AB6, GPIOP4)); #define Y7 125 -SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5); -MS_PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(GPIOP5)); +SIG_EXPR_LIST_DECL_SINGLE(Y7, GPIOP5, GPIOP5); +PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(Y7, GPIOP5)); #define AA7 126 SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22)); @@ -995,36 +1054,36 @@ SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23)); #define I2C3_DESC SIG_DESC_SET(SCU90, 16) #define D3 128 -SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); -SS_PIN_DECL(D3, GPIOQ0, SCL3); +SIG_EXPR_LIST_DECL_SINGLE(D3, SCL3, I2C3, I2C3_DESC); +PIN_DECL_1(D3, GPIOQ0, SCL3); #define C2 129 -SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); -SS_PIN_DECL(C2, GPIOQ1, SDA3); +SIG_EXPR_LIST_DECL_SINGLE(C2, SDA3, I2C3, I2C3_DESC); +PIN_DECL_1(C2, GPIOQ1, SDA3); FUNC_GROUP_DECL(I2C3, D3, C2); #define I2C4_DESC SIG_DESC_SET(SCU90, 17) #define B1 130 -SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); -SS_PIN_DECL(B1, GPIOQ2, SCL4); +SIG_EXPR_LIST_DECL_SINGLE(B1, SCL4, I2C4, I2C4_DESC); +PIN_DECL_1(B1, GPIOQ2, SCL4); #define F5 131 -SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); -SS_PIN_DECL(F5, GPIOQ3, SDA4); +SIG_EXPR_LIST_DECL_SINGLE(F5, SDA4, I2C4, I2C4_DESC); +PIN_DECL_1(F5, GPIOQ3, SDA4); FUNC_GROUP_DECL(I2C4, B1, F5); #define I2C14_DESC SIG_DESC_SET(SCU90, 27) #define H4 132 -SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); -SS_PIN_DECL(H4, GPIOQ4, SCL14); +SIG_EXPR_LIST_DECL_SINGLE(H4, SCL14, I2C14, I2C14_DESC); +PIN_DECL_1(H4, GPIOQ4, SCL14); #define H3 133 -SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); -SS_PIN_DECL(H3, GPIOQ5, SDA14); +SIG_EXPR_LIST_DECL_SINGLE(H3, SDA14, I2C14, I2C14_DESC); +PIN_DECL_1(H3, GPIOQ5, SDA14); FUNC_GROUP_DECL(I2C14, H4, H3); @@ -1039,12 +1098,12 @@ FUNC_GROUP_DECL(I2C14, H4, H3); #define USB11H3_DESC SIG_DESC_SET(SCU90, 28) #define H2 134 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC); -SS_PIN_DECL(H2, GPIOQ6, USB11HDP3); +SIG_EXPR_LIST_DECL_SINGLE(H2, USB11HDP3, USB11H3, USB11H3_DESC); +PIN_DECL_1(H2, GPIOQ6, USB11HDP3); #define H1 135 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC); -SS_PIN_DECL(H1, GPIOQ7, USB11HDN3); +SIG_EXPR_LIST_DECL_SINGLE(H1, USB11HDN3, USB11H3, USB11H3_DESC); +PIN_DECL_1(H1, GPIOQ7, USB11HDN3); #define V20 136 SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); @@ -1067,303 +1126,333 @@ SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); #define V21 140 #define V21_DESC SIG_DESC_SET(SCU88, 28) -SIG_EXPR_DECL(ROMA24, ROM8, V21_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA24, ROM16, V21_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA24, SIG_EXPR_PTR(ROMA24, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA24, ROM8, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA24, ROM16, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA24, ROM, + SIG_EXPR_PTR(ROMA24, ROM8), SIG_EXPR_PTR(ROMA24, ROM16), SIG_EXPR_PTR(ROMA24, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR6, VPO24, V21_DESC, VPO_24_OFF); -MS_PIN_DECL(V21, GPIOR4, ROMA24, VPOR6); +SIG_EXPR_LIST_ALIAS(V21, ROMA24, ROM); +SIG_EXPR_LIST_DECL_SINGLE(V21, VPOR6, VPO24, V21_DESC, VPO_24_OFF); +PIN_DECL_2(V21, GPIOR4, ROMA24, VPOR6); #define W22 141 #define W22_DESC SIG_DESC_SET(SCU88, 29) -SIG_EXPR_DECL(ROMA25, ROM8, W22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA25, ROM16, W22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA25, SIG_EXPR_PTR(ROMA25, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA25, ROM8, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA25, ROM16, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA25, ROM, + SIG_EXPR_PTR(ROMA25, ROM8), SIG_EXPR_PTR(ROMA25, ROM16), SIG_EXPR_PTR(ROMA25, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR7, VPO24, W22_DESC, VPO_24_OFF); -MS_PIN_DECL(W22, GPIOR5, ROMA25, VPOR7); +SIG_EXPR_LIST_ALIAS(W22, ROMA25, ROM); +SIG_EXPR_LIST_DECL_SINGLE(W22, VPOR7, VPO24, W22_DESC, VPO_24_OFF); +PIN_DECL_2(W22, GPIOR5, ROMA25, VPOR7); #define C6 142 -SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); -SS_PIN_DECL(C6, GPIOR6, MDC1); +SIG_EXPR_LIST_DECL_SINGLE(C6, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); +PIN_DECL_1(C6, GPIOR6, MDC1); #define A5 143 -SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); -SS_PIN_DECL(A5, GPIOR7, MDIO1); +SIG_EXPR_LIST_DECL_SINGLE(A5, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); +PIN_DECL_1(A5, GPIOR7, MDIO1); FUNC_GROUP_DECL(MDIO1, C6, A5); #define U21 144 #define U21_DESC SIG_DESC_SET(SCU8C, 0) -SIG_EXPR_DECL(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD4, SIG_EXPR_PTR(ROMD4, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD4, ROM, + SIG_EXPR_PTR(ROMD4, ROM8), SIG_EXPR_PTR(ROMD4, ROM16), SIG_EXPR_PTR(ROMD4, ROM16S)); -SIG_EXPR_DECL(VPODE, VPO12, U21_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPODE, VPO24, U21_DESC, VPO12_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPODE, VPO12, VPO24); -MS_PIN_DECL(U21, GPIOS0, ROMD4, VPODE); +SIG_EXPR_LIST_ALIAS(U21, ROMD4, ROM); +SIG_EXPR_DECL_SINGLE(VPODE, VPO12, U21_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPODE, VPO24, U21_DESC, VPO12_DESC); +SIG_EXPR_LIST_DECL_DUAL(U21, VPODE, VPO12, VPO24); +PIN_DECL_2(U21, GPIOS0, ROMD4, VPODE); #define T19 145 #define T19_DESC SIG_DESC_SET(SCU8C, 1) -SIG_EXPR_DECL(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD5, SIG_EXPR_PTR(ROMD5, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD5, ROM, + SIG_EXPR_PTR(ROMD5, ROM8), SIG_EXPR_PTR(ROMD5, ROM16), SIG_EXPR_PTR(ROMD5, ROM16S)); -SIG_EXPR_DECL(VPOHS, VPO12, T19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOHS, VPO24, T19_DESC, VPO24_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOHS, VPO12, VPO24); -MS_PIN_DECL(T19, GPIOS1, ROMD5, VPOHS); +SIG_EXPR_LIST_ALIAS(T19, ROMD5, ROM); +SIG_EXPR_DECL_SINGLE(VPOHS, VPO12, T19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOHS, VPO24, T19_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(T19, VPOHS, VPO12, VPO24); +PIN_DECL_2(T19, GPIOS1, ROMD5, VPOHS); #define V22 146 #define V22_DESC SIG_DESC_SET(SCU8C, 2) -SIG_EXPR_DECL(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD6, SIG_EXPR_PTR(ROMD6, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD6, ROM, + SIG_EXPR_PTR(ROMD6, ROM8), SIG_EXPR_PTR(ROMD6, ROM16), SIG_EXPR_PTR(ROMD6, ROM16S)); -SIG_EXPR_DECL(VPOVS, VPO12, V22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOVS, VPO24, V22_DESC, VPO24_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOVS, VPO12, VPO24); -MS_PIN_DECL(V22, GPIOS2, ROMD6, VPOVS); +SIG_EXPR_LIST_ALIAS(V22, ROMD6, ROM); +SIG_EXPR_DECL_SINGLE(VPOVS, VPO12, V22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOVS, VPO24, V22_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(V22, VPOVS, VPO12, VPO24); +PIN_DECL_2(V22, GPIOS2, ROMD6, VPOVS); #define U20 147 #define U20_DESC SIG_DESC_SET(SCU8C, 3) -SIG_EXPR_DECL(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD7, SIG_EXPR_PTR(ROMD7, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD7, ROM, + SIG_EXPR_PTR(ROMD7, ROM8), SIG_EXPR_PTR(ROMD7, ROM16), SIG_EXPR_PTR(ROMD7, ROM16S)); -SIG_EXPR_DECL(VPOCLK, VPO12, U20_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOCLK, VPO24, U20_DESC, VPO24_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOCLK, VPO12, VPO24); -MS_PIN_DECL(U20, GPIOS3, ROMD7, VPOCLK); +SIG_EXPR_LIST_ALIAS(U20, ROMD7, ROM); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPO12, U20_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPO24, U20_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(U20, VPOCLK, VPO12, VPO24); +PIN_DECL_2(U20, GPIOS3, ROMD7, VPOCLK); #define R18 148 #define ROMOE_DESC SIG_DESC_SET(SCU8C, 4) -SIG_EXPR_LIST_DECL_SINGLE(GPIOS4, GPIOS4); -SIG_EXPR_DECL(ROMOE, ROM8, ROMOE_DESC); -SIG_EXPR_DECL(ROMOE, ROM16, ROMOE_DESC); -SIG_EXPR_DECL(ROMOE, ROM16S, ROMOE_DESC); -SIG_EXPR_LIST_DECL(ROMOE, SIG_EXPR_PTR(ROMOE, ROM8), +SIG_EXPR_LIST_DECL_SINGLE(R18, GPIOS4, GPIOS4); +SIG_EXPR_DECL_SINGLE(ROMOE, ROM8, ROMOE_DESC); +SIG_EXPR_DECL_SINGLE(ROMOE, ROM16, ROMOE_DESC); +SIG_EXPR_DECL_SINGLE(ROMOE, ROM16S, ROMOE_DESC); +SIG_EXPR_LIST_DECL(ROMOE, ROM, + SIG_EXPR_PTR(ROMOE, ROM8), SIG_EXPR_PTR(ROMOE, ROM16), SIG_EXPR_PTR(ROMOE, ROM16S)); -MS_PIN_DECL_(R18, SIG_EXPR_LIST_PTR(ROMOE), SIG_EXPR_LIST_PTR(GPIOS4)); +SIG_EXPR_LIST_ALIAS(R18, ROMOE, ROM); +PIN_DECL_(R18, SIG_EXPR_LIST_PTR(R18, ROMOE), SIG_EXPR_LIST_PTR(R18, GPIOS4)); #define N21 149 #define ROMWE_DESC SIG_DESC_SET(SCU8C, 5) -SIG_EXPR_LIST_DECL_SINGLE(GPIOS5, GPIOS5); -SIG_EXPR_DECL(ROMWE, ROM8, ROMWE_DESC); -SIG_EXPR_DECL(ROMWE, ROM16, ROMWE_DESC); -SIG_EXPR_DECL(ROMWE, ROM16S, ROMWE_DESC); -SIG_EXPR_LIST_DECL(ROMWE, SIG_EXPR_PTR(ROMWE, ROM8), +SIG_EXPR_LIST_DECL_SINGLE(N21, GPIOS5, GPIOS5); +SIG_EXPR_DECL_SINGLE(ROMWE, ROM8, ROMWE_DESC); +SIG_EXPR_DECL_SINGLE(ROMWE, ROM16, ROMWE_DESC); +SIG_EXPR_DECL_SINGLE(ROMWE, ROM16S, ROMWE_DESC); +SIG_EXPR_LIST_DECL(ROMWE, ROM, + SIG_EXPR_PTR(ROMWE, ROM8), SIG_EXPR_PTR(ROMWE, ROM16), SIG_EXPR_PTR(ROMWE, ROM16S)); -MS_PIN_DECL_(N21, SIG_EXPR_LIST_PTR(ROMWE), SIG_EXPR_LIST_PTR(GPIOS5)); +SIG_EXPR_LIST_ALIAS(N21, ROMWE, ROM); +PIN_DECL_(N21, SIG_EXPR_LIST_PTR(N21, ROMWE), SIG_EXPR_LIST_PTR(N21, GPIOS5)); #define L22 150 #define L22_DESC SIG_DESC_SET(SCU8C, 6) -SIG_EXPR_DECL(ROMA22, ROM8, L22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA22, ROM16, L22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA22, ROM16S, L22_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA22, SIG_EXPR_PTR(ROMA22, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA22, ROM8, L22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA22, ROM16, L22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA22, ROM16S, L22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA22, ROM, + SIG_EXPR_PTR(ROMA22, ROM8), SIG_EXPR_PTR(ROMA22, ROM16), SIG_EXPR_PTR(ROMA22, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR4, VPO24, L22_DESC, VPO_24_OFF); -MS_PIN_DECL(L22, GPIOS6, ROMA22, VPOR4); +SIG_EXPR_LIST_ALIAS(L22, ROMA22, ROM); +SIG_EXPR_LIST_DECL_SINGLE(L22, VPOR4, VPO24, L22_DESC, VPO_24_OFF); +PIN_DECL_2(L22, GPIOS6, ROMA22, VPOR4); #define K18 151 #define K18_DESC SIG_DESC_SET(SCU8C, 7) -SIG_EXPR_DECL(ROMA23, ROM8, K18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA23, ROM16, K18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA23, ROM16S, K18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA23, ROM8, K18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA23, ROM16, K18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA23, ROM16S, K18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA23, ROM, + SIG_EXPR_PTR(ROMA23, ROM8), SIG_EXPR_PTR(ROMA23, ROM16), SIG_EXPR_PTR(ROMA23, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF); -MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5); +SIG_EXPR_LIST_ALIAS(K18, ROMA23, ROM); +SIG_EXPR_LIST_DECL_SINGLE(K18, VPOR5, VPO24, K18_DESC, VPO_24_OFF); +PIN_DECL_2(K18, GPIOS7, ROMA23, VPOR5); #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) #define A12 152 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); -MS_PIN_DECL_(A12, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1TXEN), - SIG_EXPR_LIST_PTR(RGMII1TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(A12, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); +SIG_EXPR_LIST_DECL_SINGLE(A12, RMII1TXEN, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A12, RGMII1TXCK, RGMII1); +PIN_DECL_(A12, SIG_EXPR_LIST_PTR(A12, GPIOT0), + SIG_EXPR_LIST_PTR(A12, RMII1TXEN), + SIG_EXPR_LIST_PTR(A12, RGMII1TXCK)); #define B12 153 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); -SIG_EXPR_LIST_DECL_SINGLE(DASHB12, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); -MS_PIN_DECL_(B12, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(DASHB12), - SIG_EXPR_LIST_PTR(RGMII1TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(B12, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); +SIG_EXPR_LIST_DECL_SINGLE(B12, DASHB12, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B12, RGMII1TXCTL, RGMII1); +PIN_DECL_(B12, SIG_EXPR_LIST_PTR(B12, GPIOT1), SIG_EXPR_LIST_PTR(B12, DASHB12), + SIG_EXPR_LIST_PTR(B12, RGMII1TXCTL)); #define C12 154 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); -MS_PIN_DECL_(C12, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), - SIG_EXPR_LIST_PTR(RGMII1TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(C12, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); +SIG_EXPR_LIST_DECL_SINGLE(C12, RMII1TXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C12, RGMII1TXD0, RGMII1); +PIN_DECL_(C12, SIG_EXPR_LIST_PTR(C12, GPIOT2), + SIG_EXPR_LIST_PTR(C12, RMII1TXD0), + SIG_EXPR_LIST_PTR(C12, RGMII1TXD0)); #define D12 155 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); -MS_PIN_DECL_(D12, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), - SIG_EXPR_LIST_PTR(RGMII1TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(D12, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); +SIG_EXPR_LIST_DECL_SINGLE(D12, RMII1TXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D12, RGMII1TXD1, RGMII1); +PIN_DECL_(D12, SIG_EXPR_LIST_PTR(D12, GPIOT3), + SIG_EXPR_LIST_PTR(D12, RMII1TXD1), + SIG_EXPR_LIST_PTR(D12, RGMII1TXD1)); #define E12 156 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); -SIG_EXPR_LIST_DECL_SINGLE(DASHE12, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); -MS_PIN_DECL_(E12, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(DASHE12), - SIG_EXPR_LIST_PTR(RGMII1TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(E12, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); +SIG_EXPR_LIST_DECL_SINGLE(E12, DASHE12, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E12, RGMII1TXD2, RGMII1); +PIN_DECL_(E12, SIG_EXPR_LIST_PTR(E12, GPIOT4), SIG_EXPR_LIST_PTR(E12, DASHE12), + SIG_EXPR_LIST_PTR(E12, RGMII1TXD2)); #define A13 157 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); -SIG_EXPR_LIST_DECL_SINGLE(DASHA13, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); -MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13), - SIG_EXPR_LIST_PTR(RGMII1TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(A13, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); +SIG_EXPR_LIST_DECL_SINGLE(A13, DASHA13, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A13, RGMII1TXD3, RGMII1); +PIN_DECL_(A13, SIG_EXPR_LIST_PTR(A13, GPIOT5), SIG_EXPR_LIST_PTR(A13, DASHA13), + SIG_EXPR_LIST_PTR(A13, RGMII1TXD3)); #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) #define D9 158 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); -MS_PIN_DECL_(D9, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2TXEN), - SIG_EXPR_LIST_PTR(RGMII2TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(D9, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); +SIG_EXPR_LIST_DECL_SINGLE(D9, RMII2TXEN, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D9, RGMII2TXCK, RGMII2); +PIN_DECL_(D9, SIG_EXPR_LIST_PTR(D9, GPIOT6), SIG_EXPR_LIST_PTR(D9, RMII2TXEN), + SIG_EXPR_LIST_PTR(D9, RGMII2TXCK)); #define E9 159 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); -SIG_EXPR_LIST_DECL_SINGLE(DASHE9, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); -MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(DASHE9), - SIG_EXPR_LIST_PTR(RGMII2TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); +SIG_EXPR_LIST_DECL_SINGLE(E9, DASHE9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII2TXCTL, RGMII2); +PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT7), SIG_EXPR_LIST_PTR(E9, DASHE9), + SIG_EXPR_LIST_PTR(E9, RGMII2TXCTL)); #define A10 160 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); -MS_PIN_DECL_(A10, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), - SIG_EXPR_LIST_PTR(RGMII2TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A10, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); +SIG_EXPR_LIST_DECL_SINGLE(A10, RMII2TXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A10, RGMII2TXD0, RGMII2); +PIN_DECL_(A10, SIG_EXPR_LIST_PTR(A10, GPIOU0), + SIG_EXPR_LIST_PTR(A10, RMII2TXD0), + SIG_EXPR_LIST_PTR(A10, RGMII2TXD0)); #define B10 161 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); -MS_PIN_DECL_(B10, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), - SIG_EXPR_LIST_PTR(RGMII2TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(B10, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); +SIG_EXPR_LIST_DECL_SINGLE(B10, RMII2TXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B10, RGMII2TXD1, RGMII2); +PIN_DECL_(B10, SIG_EXPR_LIST_PTR(B10, GPIOU1), + SIG_EXPR_LIST_PTR(B10, RMII2TXD1), + SIG_EXPR_LIST_PTR(B10, RGMII2TXD1)); #define C10 162 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); -SIG_EXPR_LIST_DECL_SINGLE(DASHC10, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); -MS_PIN_DECL_(C10, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(DASHC10), - SIG_EXPR_LIST_PTR(RGMII2TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(C10, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); +SIG_EXPR_LIST_DECL_SINGLE(C10, DASHC10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C10, RGMII2TXD2, RGMII2); +PIN_DECL_(C10, SIG_EXPR_LIST_PTR(C10, GPIOU2), SIG_EXPR_LIST_PTR(C10, DASHC10), + SIG_EXPR_LIST_PTR(C10, RGMII2TXD2)); #define D10 163 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); -SIG_EXPR_LIST_DECL_SINGLE(DASHD10, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); -MS_PIN_DECL_(D10, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(DASHD10), - SIG_EXPR_LIST_PTR(RGMII2TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(D10, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); +SIG_EXPR_LIST_DECL_SINGLE(D10, DASHD10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D10, RGMII2TXD3, RGMII2); +PIN_DECL_(D10, SIG_EXPR_LIST_PTR(D10, GPIOU3), SIG_EXPR_LIST_PTR(D10, DASHD10), + SIG_EXPR_LIST_PTR(D10, RGMII2TXD3)); #define E11 164 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); -MS_PIN_DECL_(E11, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLK), - SIG_EXPR_LIST_PTR(RGMII1RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(E11, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); +SIG_EXPR_LIST_DECL_SINGLE(E11, RMII1RCLK, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E11, RGMII1RXCK, RGMII1); +PIN_DECL_(E11, SIG_EXPR_LIST_PTR(E11, GPIOU4), + SIG_EXPR_LIST_PTR(E11, RMII1RCLK), + SIG_EXPR_LIST_PTR(E11, RGMII1RXCK)); #define D11 165 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); -SIG_EXPR_LIST_DECL_SINGLE(DASHD11, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); -MS_PIN_DECL_(D11, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(DASHD11), - SIG_EXPR_LIST_PTR(RGMII1RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(D11, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); +SIG_EXPR_LIST_DECL_SINGLE(D11, DASHD11, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D11, RGMII1RXCTL, RGMII1); +PIN_DECL_(D11, SIG_EXPR_LIST_PTR(D11, GPIOU5), SIG_EXPR_LIST_PTR(D11, DASHD11), + SIG_EXPR_LIST_PTR(D11, RGMII1RXCTL)); #define C11 166 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); -MS_PIN_DECL_(C11, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), - SIG_EXPR_LIST_PTR(RGMII1RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(C11, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); +SIG_EXPR_LIST_DECL_SINGLE(C11, RMII1RXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C11, RGMII1RXD0, RGMII1); +PIN_DECL_(C11, SIG_EXPR_LIST_PTR(C11, GPIOU6), + SIG_EXPR_LIST_PTR(C11, RMII1RXD0), + SIG_EXPR_LIST_PTR(C11, RGMII1RXD0)); #define B11 167 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); -MS_PIN_DECL_(B11, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), - SIG_EXPR_LIST_PTR(RGMII1RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(B11, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); +SIG_EXPR_LIST_DECL_SINGLE(B11, RMII1RXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B11, RGMII1RXD1, RGMII1); +PIN_DECL_(B11, SIG_EXPR_LIST_PTR(B11, GPIOU7), + SIG_EXPR_LIST_PTR(B11, RMII1RXD1), + SIG_EXPR_LIST_PTR(B11, RGMII1RXD1)); #define A11 168 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); -MS_PIN_DECL_(A11, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), - SIG_EXPR_LIST_PTR(RGMII1RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(A11, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); +SIG_EXPR_LIST_DECL_SINGLE(A11, RMII1CRSDV, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A11, RGMII1RXD2, RGMII1); +PIN_DECL_(A11, SIG_EXPR_LIST_PTR(A11, GPIOV0), + SIG_EXPR_LIST_PTR(A11, RMII1CRSDV), + SIG_EXPR_LIST_PTR(A11, RGMII1RXD2)); #define E10 169 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); -MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), - SIG_EXPR_LIST_PTR(RGMII1RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); +SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1); +PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1), + SIG_EXPR_LIST_PTR(E10, RMII1RXER), + SIG_EXPR_LIST_PTR(E10, RGMII1RXD3)); #define C9 170 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLK, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); -MS_PIN_DECL_(C9, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLK), - SIG_EXPR_LIST_PTR(RGMII2RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(C9, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); +SIG_EXPR_LIST_DECL_SINGLE(C9, RMII2RCLK, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C9, RGMII2RXCK, RGMII2); +PIN_DECL_(C9, SIG_EXPR_LIST_PTR(C9, GPIOV2), SIG_EXPR_LIST_PTR(C9, RMII2RCLK), + SIG_EXPR_LIST_PTR(C9, RGMII2RXCK)); #define B9 171 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); -SIG_EXPR_LIST_DECL_SINGLE(DASHB9, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); -MS_PIN_DECL_(B9, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(DASHB9), - SIG_EXPR_LIST_PTR(RGMII2RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(B9, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); +SIG_EXPR_LIST_DECL_SINGLE(B9, DASHB9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B9, RGMII2RXCTL, RGMII2); +PIN_DECL_(B9, SIG_EXPR_LIST_PTR(B9, GPIOV3), SIG_EXPR_LIST_PTR(B9, DASHB9), + SIG_EXPR_LIST_PTR(B9, RGMII2RXCTL)); #define A9 172 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); -MS_PIN_DECL_(A9, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), - SIG_EXPR_LIST_PTR(RGMII2RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A9, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); +SIG_EXPR_LIST_DECL_SINGLE(A9, RMII2RXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A9, RGMII2RXD0, RGMII2); +PIN_DECL_(A9, SIG_EXPR_LIST_PTR(A9, GPIOV4), SIG_EXPR_LIST_PTR(A9, RMII2RXD0), + SIG_EXPR_LIST_PTR(A9, RGMII2RXD0)); #define E8 173 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); -MS_PIN_DECL_(E8, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), - SIG_EXPR_LIST_PTR(RGMII2RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(E8, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); +SIG_EXPR_LIST_DECL_SINGLE(E8, RMII2RXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E8, RGMII2RXD1, RGMII2); +PIN_DECL_(E8, SIG_EXPR_LIST_PTR(E8, GPIOV5), SIG_EXPR_LIST_PTR(E8, RMII2RXD1), + SIG_EXPR_LIST_PTR(E8, RGMII2RXD1)); #define D8 174 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); -MS_PIN_DECL_(D8, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), - SIG_EXPR_LIST_PTR(RGMII2RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(D8, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); +SIG_EXPR_LIST_DECL_SINGLE(D8, RMII2CRSDV, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D8, RGMII2RXD2, RGMII2); +PIN_DECL_(D8, SIG_EXPR_LIST_PTR(D8, GPIOV6), SIG_EXPR_LIST_PTR(D8, RMII2CRSDV), + SIG_EXPR_LIST_PTR(D8, RGMII2RXD2)); #define C8 175 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); -MS_PIN_DECL_(C8, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), - SIG_EXPR_LIST_PTR(RGMII2RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(C8, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); +SIG_EXPR_LIST_DECL_SINGLE(C8, RMII2RXER, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C8, RGMII2RXD3, RGMII2); +PIN_DECL_(C8, SIG_EXPR_LIST_PTR(C8, GPIOV7), SIG_EXPR_LIST_PTR(C8, RMII2RXER), + SIG_EXPR_LIST_PTR(C8, RGMII2RXD3)); FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, E10); @@ -1374,354 +1463,390 @@ FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); #define L5 176 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); -SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); -MS_PIN_DECL_(L5, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +SIG_EXPR_LIST_DECL_SINGLE(L5, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(L5, ADC0, ADC0); +PIN_DECL_(L5, SIG_EXPR_LIST_PTR(L5, GPIOW0), SIG_EXPR_LIST_PTR(L5, ADC0)); FUNC_GROUP_DECL(ADC0, L5); #define L4 177 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); -SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); -MS_PIN_DECL_(L4, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +SIG_EXPR_LIST_DECL_SINGLE(L4, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(L4, ADC1, ADC1); +PIN_DECL_(L4, SIG_EXPR_LIST_PTR(L4, GPIOW1), SIG_EXPR_LIST_PTR(L4, ADC1)); FUNC_GROUP_DECL(ADC1, L4); #define L3 178 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); -SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); -MS_PIN_DECL_(L3, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +SIG_EXPR_LIST_DECL_SINGLE(L3, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(L3, ADC2, ADC2); +PIN_DECL_(L3, SIG_EXPR_LIST_PTR(L3, GPIOW2), SIG_EXPR_LIST_PTR(L3, ADC2)); FUNC_GROUP_DECL(ADC2, L3); #define L2 179 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); -SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); -MS_PIN_DECL_(L2, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3); +PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3)); FUNC_GROUP_DECL(ADC3, L2); #define L1 180 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); -SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); -MS_PIN_DECL_(L1, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4); +PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4)); FUNC_GROUP_DECL(ADC4, L1); #define M5 181 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); -SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); -MS_PIN_DECL_(M5, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +SIG_EXPR_LIST_DECL_SINGLE(M5, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(M5, ADC5, ADC5); +PIN_DECL_(M5, SIG_EXPR_LIST_PTR(M5, GPIOW5), SIG_EXPR_LIST_PTR(M5, ADC5)); FUNC_GROUP_DECL(ADC5, M5); #define M4 182 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); -SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); -MS_PIN_DECL_(M4, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +SIG_EXPR_LIST_DECL_SINGLE(M4, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(M4, ADC6, ADC6); +PIN_DECL_(M4, SIG_EXPR_LIST_PTR(M4, GPIOW6), SIG_EXPR_LIST_PTR(M4, ADC6)); FUNC_GROUP_DECL(ADC6, M4); #define M3 183 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); -SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); -MS_PIN_DECL_(M3, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +SIG_EXPR_LIST_DECL_SINGLE(M3, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(M3, ADC7, ADC7); +PIN_DECL_(M3, SIG_EXPR_LIST_PTR(M3, GPIOW7), SIG_EXPR_LIST_PTR(M3, ADC7)); FUNC_GROUP_DECL(ADC7, M3); #define M2 184 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); -SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); -MS_PIN_DECL_(M2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8); +PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8)); FUNC_GROUP_DECL(ADC8, M2); #define M1 185 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); -SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); -MS_PIN_DECL_(M1, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9); +PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9)); FUNC_GROUP_DECL(ADC9, M1); #define N5 186 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); -SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); -MS_PIN_DECL_(N5, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +SIG_EXPR_LIST_DECL_SINGLE(N5, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(N5, ADC10, ADC10); +PIN_DECL_(N5, SIG_EXPR_LIST_PTR(N5, GPIOX2), SIG_EXPR_LIST_PTR(N5, ADC10)); FUNC_GROUP_DECL(ADC10, N5); #define N4 187 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); -SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); -MS_PIN_DECL_(N4, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +SIG_EXPR_LIST_DECL_SINGLE(N4, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(N4, ADC11, ADC11); +PIN_DECL_(N4, SIG_EXPR_LIST_PTR(N4, GPIOX3), SIG_EXPR_LIST_PTR(N4, ADC11)); FUNC_GROUP_DECL(ADC11, N4); #define N3 188 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); -SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); -MS_PIN_DECL_(N3, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +SIG_EXPR_LIST_DECL_SINGLE(N3, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(N3, ADC12, ADC12); +PIN_DECL_(N3, SIG_EXPR_LIST_PTR(N3, GPIOX4), SIG_EXPR_LIST_PTR(N3, ADC12)); FUNC_GROUP_DECL(ADC12, N3); #define N2 189 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); -SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); -MS_PIN_DECL_(N2, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13); +PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13)); FUNC_GROUP_DECL(ADC13, N2); #define N1 190 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); -SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); -MS_PIN_DECL_(N1, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14); +PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14)); FUNC_GROUP_DECL(ADC14, N1); #define P5 191 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); -SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); -MS_PIN_DECL_(P5, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +SIG_EXPR_LIST_DECL_SINGLE(P5, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(P5, ADC15, ADC15); +PIN_DECL_(P5, SIG_EXPR_LIST_PTR(P5, GPIOX7), SIG_EXPR_LIST_PTR(P5, ADC15)); FUNC_GROUP_DECL(ADC15, P5); #define C21 192 -SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); -SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); -SS_PIN_DECL(C21, GPIOY0, SIOS3); +SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(C21, SIOS3, SIOS3, ACPI); +PIN_DECL_1(C21, GPIOY0, SIOS3); FUNC_GROUP_DECL(SIOS3, C21); #define F20 193 -SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); -SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); -SS_PIN_DECL(F20, GPIOY1, SIOS5); +SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(F20, SIOS5, SIOS5, ACPI); +PIN_DECL_1(F20, GPIOY1, SIOS5); FUNC_GROUP_DECL(SIOS5, F20); #define G20 194 -SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); -SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); -SS_PIN_DECL(G20, GPIOY2, SIOPWREQ); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(G20, SIOPWREQ, SIOPWREQ, ACPI); +PIN_DECL_1(G20, GPIOY2, SIOPWREQ); FUNC_GROUP_DECL(SIOPWREQ, G20); #define K20 195 -SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); -SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); -SS_PIN_DECL(K20, GPIOY3, SIOONCTRL); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(K20, SIOONCTRL, SIOONCTRL, ACPI); +PIN_DECL_1(K20, GPIOY3, SIOONCTRL); FUNC_GROUP_DECL(SIOONCTRL, K20); FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20); #define R22 200 #define R22_DESC SIG_DESC_SET(SCUA4, 16) -SIG_EXPR_DECL(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA2, ROM8, ROM16); -SIG_EXPR_DECL(VPOB0, VPO12, R22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB0, VPO24, R22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB0, SIG_EXPR_PTR(VPOB0, VPO12), - SIG_EXPR_PTR(VPOB0, VPO24), SIG_EXPR_PTR(VPOB0, VPOOFF1)); -MS_PIN_DECL(R22, GPIOZ0, ROMA2, VPOB0); +SIG_EXPR_DECL_SINGLE(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(R22, ROMA2, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB0, VPO12, R22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB0, VPO24, R22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB0, VPO, + SIG_EXPR_PTR(VPOB0, VPO12), + SIG_EXPR_PTR(VPOB0, VPO24), + SIG_EXPR_PTR(VPOB0, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(R22, VPOB0, VPO); +PIN_DECL_2(R22, GPIOZ0, ROMA2, VPOB0); #define P18 201 #define P18_DESC SIG_DESC_SET(SCUA4, 17) -SIG_EXPR_DECL(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA3, ROM8, ROM16); -SIG_EXPR_DECL(VPOB1, VPO12, P18_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB1, VPO24, P18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB1, SIG_EXPR_PTR(VPOB1, VPO12), - SIG_EXPR_PTR(VPOB1, VPO24), SIG_EXPR_PTR(VPOB1, VPOOFF1)); -MS_PIN_DECL(P18, GPIOZ1, ROMA3, VPOB1); +SIG_EXPR_DECL_SINGLE(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P18, ROMA3, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB1, VPO12, P18_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB1, VPO24, P18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB1, VPO, + SIG_EXPR_PTR(VPOB1, VPO12), + SIG_EXPR_PTR(VPOB1, VPO24), + SIG_EXPR_PTR(VPOB1, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P18, VPOB1, VPO); +PIN_DECL_2(P18, GPIOZ1, ROMA3, VPOB1); #define P19 202 #define P19_DESC SIG_DESC_SET(SCUA4, 18) -SIG_EXPR_DECL(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA4, ROM8, ROM16); -SIG_EXPR_DECL(VPOB2, VPO12, P19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB2, VPO24, P19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO12), - SIG_EXPR_PTR(VPOB2, VPO24), SIG_EXPR_PTR(VPOB2, VPOOFF1)); -MS_PIN_DECL(P19, GPIOZ2, ROMA4, VPOB2); +SIG_EXPR_DECL_SINGLE(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P19, ROMA4, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB2, VPO12, P19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPO24, P19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB2, VPO, + SIG_EXPR_PTR(VPOB2, VPO12), + SIG_EXPR_PTR(VPOB2, VPO24), + SIG_EXPR_PTR(VPOB2, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P19, VPOB2, VPO); +PIN_DECL_2(P19, GPIOZ2, ROMA4, VPOB2); #define P20 203 #define P20_DESC SIG_DESC_SET(SCUA4, 19) -SIG_EXPR_DECL(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA5, ROM8, ROM16); -SIG_EXPR_DECL(VPOB3, VPO12, P20_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB3, VPO24, P20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO12), - SIG_EXPR_PTR(VPOB3, VPO24), SIG_EXPR_PTR(VPOB3, VPOOFF1)); -MS_PIN_DECL(P20, GPIOZ3, ROMA5, VPOB3); +SIG_EXPR_DECL_SINGLE(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P20, ROMA5, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB3, VPO12, P20_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPO24, P20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB3, VPO, + SIG_EXPR_PTR(VPOB3, VPO12), + SIG_EXPR_PTR(VPOB3, VPO24), + SIG_EXPR_PTR(VPOB3, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P20, VPOB3, VPO); +PIN_DECL_2(P20, GPIOZ3, ROMA5, VPOB3); #define P21 204 #define P21_DESC SIG_DESC_SET(SCUA4, 20) -SIG_EXPR_DECL(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA6, ROM8, ROM16); -SIG_EXPR_DECL(VPOB4, VPO12, P21_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB4, VPO24, P21_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO12), - SIG_EXPR_PTR(VPOB4, VPO24), SIG_EXPR_PTR(VPOB4, VPOOFF1)); -MS_PIN_DECL(P21, GPIOZ4, ROMA6, VPOB4); +SIG_EXPR_DECL_SINGLE(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P21, ROMA6, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB4, VPO12, P21_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPO24, P21_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB4, VPO, + SIG_EXPR_PTR(VPOB4, VPO12), + SIG_EXPR_PTR(VPOB4, VPO24), + SIG_EXPR_PTR(VPOB4, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P21, VPOB4, VPO); +PIN_DECL_2(P21, GPIOZ4, ROMA6, VPOB4); #define P22 205 #define P22_DESC SIG_DESC_SET(SCUA4, 21) -SIG_EXPR_DECL(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA7, ROM8, ROM16); -SIG_EXPR_DECL(VPOB5, VPO12, P22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB5, VPO24, P22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO12), - SIG_EXPR_PTR(VPOB5, VPO24), SIG_EXPR_PTR(VPOB5, VPOOFF1)); -MS_PIN_DECL(P22, GPIOZ5, ROMA7, VPOB5); +SIG_EXPR_DECL_SINGLE(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P22, ROMA7, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB5, VPO12, P22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPO24, P22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB5, VPO, + SIG_EXPR_PTR(VPOB5, VPO12), + SIG_EXPR_PTR(VPOB5, VPO24), + SIG_EXPR_PTR(VPOB5, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P22, VPOB5, VPO); +PIN_DECL_2(P22, GPIOZ5, ROMA7, VPOB5); #define M19 206 #define M19_DESC SIG_DESC_SET(SCUA4, 22) -SIG_EXPR_DECL(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA8, ROM8, ROM16); -SIG_EXPR_DECL(VPOB6, VPO12, M19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB6, VPO24, M19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO12), - SIG_EXPR_PTR(VPOB6, VPO24), SIG_EXPR_PTR(VPOB6, VPOOFF1)); -MS_PIN_DECL(M19, GPIOZ6, ROMA8, VPOB6); +SIG_EXPR_DECL_SINGLE(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M19, ROMA8, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB6, VPO12, M19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPO24, M19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB6, VPO, + SIG_EXPR_PTR(VPOB6, VPO12), + SIG_EXPR_PTR(VPOB6, VPO24), + SIG_EXPR_PTR(VPOB6, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M19, VPOB6, VPO); +PIN_DECL_2(M19, GPIOZ6, ROMA8, VPOB6); #define M20 207 #define M20_DESC SIG_DESC_SET(SCUA4, 23) -SIG_EXPR_DECL(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA9, ROM8, ROM16); -SIG_EXPR_DECL(VPOB7, VPO12, M20_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB7, VPO24, M20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO12), - SIG_EXPR_PTR(VPOB7, VPO24), SIG_EXPR_PTR(VPOB7, VPOOFF1)); -MS_PIN_DECL(M20, GPIOZ7, ROMA9, VPOB7); +SIG_EXPR_DECL_SINGLE(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M20, ROMA9, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB7, VPO12, M20_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPO24, M20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB7, VPO, + SIG_EXPR_PTR(VPOB7, VPO12), + SIG_EXPR_PTR(VPOB7, VPO24), + SIG_EXPR_PTR(VPOB7, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M20, VPOB7, VPO); +PIN_DECL_2(M20, GPIOZ7, ROMA9, VPOB7); #define M21 208 #define M21_DESC SIG_DESC_SET(SCUA4, 24) -SIG_EXPR_DECL(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA10, ROM8, ROM16); -SIG_EXPR_DECL(VPOG0, VPO12, M21_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG0, VPO24, M21_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG0, SIG_EXPR_PTR(VPOG0, VPO12), - SIG_EXPR_PTR(VPOG0, VPO24), SIG_EXPR_PTR(VPOG0, VPOOFF1)); -MS_PIN_DECL(M21, GPIOAA0, ROMA10, VPOG0); +SIG_EXPR_DECL_SINGLE(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M21, ROMA10, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG0, VPO12, M21_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG0, VPO24, M21_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG0, VPO, + SIG_EXPR_PTR(VPOG0, VPO12), + SIG_EXPR_PTR(VPOG0, VPO24), + SIG_EXPR_PTR(VPOG0, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M21, VPOG0, VPO); +PIN_DECL_2(M21, GPIOAA0, ROMA10, VPOG0); #define M22 209 #define M22_DESC SIG_DESC_SET(SCUA4, 25) -SIG_EXPR_DECL(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA11, ROM8, ROM16); -SIG_EXPR_DECL(VPOG1, VPO12, M22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG1, VPO24, M22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG1, SIG_EXPR_PTR(VPOG1, VPO12), - SIG_EXPR_PTR(VPOG1, VPO24), SIG_EXPR_PTR(VPOG1, VPOOFF1)); -MS_PIN_DECL(M22, GPIOAA1, ROMA11, VPOG1); +SIG_EXPR_DECL_SINGLE(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M22, ROMA11, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG1, VPO12, M22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG1, VPO24, M22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG1, VPO, + SIG_EXPR_PTR(VPOG1, VPO12), + SIG_EXPR_PTR(VPOG1, VPO24), + SIG_EXPR_PTR(VPOG1, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M22, VPOG1, VPO); +PIN_DECL_2(M22, GPIOAA1, ROMA11, VPOG1); #define L18 210 #define L18_DESC SIG_DESC_SET(SCUA4, 26) -SIG_EXPR_DECL(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA12, ROM8, ROM16); -SIG_EXPR_DECL(VPOG2, VPO12, L18_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG2, VPO24, L18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO12), - SIG_EXPR_PTR(VPOG2, VPO24), SIG_EXPR_PTR(VPOG2, VPOOFF1)); -MS_PIN_DECL(L18, GPIOAA2, ROMA12, VPOG2); +SIG_EXPR_DECL_SINGLE(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(L18, ROMA12, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG2, VPO12, L18_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPO24, L18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG2, VPO, + SIG_EXPR_PTR(VPOG2, VPO12), + SIG_EXPR_PTR(VPOG2, VPO24), + SIG_EXPR_PTR(VPOG2, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(L18, VPOG2, VPO); +PIN_DECL_2(L18, GPIOAA2, ROMA12, VPOG2); #define L19 211 #define L19_DESC SIG_DESC_SET(SCUA4, 27) -SIG_EXPR_DECL(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA13, ROM8, ROM16); -SIG_EXPR_DECL(VPOG3, VPO12, L19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG3, VPO24, L19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO12), - SIG_EXPR_PTR(VPOG3, VPO24), SIG_EXPR_PTR(VPOG3, VPOOFF1)); -MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3); +SIG_EXPR_DECL_SINGLE(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(L19, ROMA13, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG3, VPO12, L19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPO24, L19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG3, VPO, + SIG_EXPR_PTR(VPOG3, VPO12), + SIG_EXPR_PTR(VPOG3, VPO24), + SIG_EXPR_PTR(VPOG3, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(L19, VPOG3, VPO); +PIN_DECL_2(L19, GPIOAA3, ROMA13, VPOG3); #define L20 212 #define L20_DESC SIG_DESC_SET(SCUA4, 28) -SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16); -SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG4, VPO24, VPOOFF1); -MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4); +SIG_EXPR_DECL_SINGLE(ROMA14, ROM8, L20_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA14, ROM16, L20_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(L20, ROMA14, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG4, VPO24, L20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(L20, VPOG4, VPO24, VPOOFF1); +PIN_DECL_2(L20, GPIOAA4, ROMA14, VPOG4); #define L21 213 #define L21_DESC SIG_DESC_SET(SCUA4, 29) -SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16); -SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG5, VPO24, VPOOFF1); -MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5); +SIG_EXPR_DECL_SINGLE(ROMA15, ROM8, L21_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA15, ROM16, L21_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(L21, ROMA15, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG5, VPO24, L21_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(L21, VPOG5, VPO24, VPOOFF1); +PIN_DECL_2(L21, GPIOAA5, ROMA15, VPOG5); #define T18 214 #define T18_DESC SIG_DESC_SET(SCUA4, 30) -SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16); -SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG6, VPO24, VPOOFF1); -MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6); +SIG_EXPR_DECL_SINGLE(ROMA16, ROM8, T18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA16, ROM16, T18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(T18, ROMA16, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG6, VPO24, T18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(T18, VPOG6, VPO24, VPOOFF1); +PIN_DECL_2(T18, GPIOAA6, ROMA16, VPOG6); #define N18 215 #define N18_DESC SIG_DESC_SET(SCUA4, 31) -SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16); -SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG7, VPO24, VPOOFF1); -MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7); +SIG_EXPR_DECL_SINGLE(ROMA17, ROM8, N18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA17, ROM16, N18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N18, ROMA17, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG7, VPO24, N18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N18, VPOG7, VPO24, VPOOFF1); +PIN_DECL_2(N18, GPIOAA7, ROMA17, VPOG7); #define N19 216 #define N19_DESC SIG_DESC_SET(SCUA8, 0) -SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16); -SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR0, VPO24, VPOOFF1); -MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0); +SIG_EXPR_DECL_SINGLE(ROMA18, ROM8, N19_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA18, ROM16, N19_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N19, ROMA18, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR0, VPO24, N19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N19, VPOR0, VPO24, VPOOFF1); +PIN_DECL_2(N19, GPIOAB0, ROMA18, VPOR0); #define M18 217 #define M18_DESC SIG_DESC_SET(SCUA8, 1) -SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16); -SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR1, VPO24, VPOOFF1); -MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1); +SIG_EXPR_DECL_SINGLE(ROMA19, ROM8, M18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA19, ROM16, M18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(M18, ROMA19, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR1, VPO24, M18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(M18, VPOR1, VPO24, VPOOFF1); +PIN_DECL_2(M18, GPIOAB1, ROMA19, VPOR1); #define N22 218 #define N22_DESC SIG_DESC_SET(SCUA8, 2) -SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16); -SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR2, VPO24, VPOOFF1); -MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2); +SIG_EXPR_DECL_SINGLE(ROMA20, ROM8, N22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA20, ROM16, N22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N22, ROMA20, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR2, VPO24, N22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N22, VPOR2, VPO24, VPOOFF1); +PIN_DECL_2(N22, GPIOAB2, ROMA20, VPOR2); #define N20 219 #define N20_DESC SIG_DESC_SET(SCUA8, 3) -SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16); -SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR3, VPO24, VPOOFF1); -MS_PIN_DECL(N20, GPIOAB3, ROMA21, VPOR3); +SIG_EXPR_DECL_SINGLE(ROMA21, ROM8, N20_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA21, ROM16, N20_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N20, ROMA21, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR3, VPO24, N20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N20, VPOR3, VPO24, VPOOFF1); +PIN_DECL_2(N20, GPIOAB3, ROMA21, VPOR3); FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, @@ -1740,14 +1865,16 @@ FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, #define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0) #define K4 220 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC); -MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1)); +SIG_EXPR_LIST_DECL_SINGLE(K4, USB11HDP2, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(K4, USB11DP1, USB11D1, USB11D1_DESC); +PIN_DECL_(K4, SIG_EXPR_LIST_PTR(K4, USB11HDP2), + SIG_EXPR_LIST_PTR(K4, USB11DP1)); #define K3 221 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC); -MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1)); +SIG_EXPR_LIST_DECL_SINGLE(K3, USB11HDN1, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(K3, USB11DDN1, USB11D1, USB11D1_DESC); +PIN_DECL_(K3, SIG_EXPR_LIST_PTR(K3, USB11HDN1), + SIG_EXPR_LIST_PTR(K3, USB11DDN1)); FUNC_GROUP_DECL(USB11H2, K4, K3); FUNC_GROUP_DECL(USB11D1, K4, K3); @@ -1756,14 +1883,16 @@ FUNC_GROUP_DECL(USB11D1, K4, K3); #define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0) #define AB21 222 -SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC); -MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1)); +SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2HDP1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2DDP1, USB2D1, USB2D1_DESC); +PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, USB2HDP1), + SIG_EXPR_LIST_PTR(AB21, USB2DDP1)); #define AB20 223 -SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC); -MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1)); +SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2HDN1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2DDN1, USB2D1, USB2D1_DESC); +PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, USB2HDN1), + SIG_EXPR_LIST_PTR(AB20, USB2DDN1)); FUNC_GROUP_DECL(USB2H1, AB21, AB20); FUNC_GROUP_DECL(USB2D1, AB21, AB20); @@ -2310,88 +2439,88 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { static const struct aspeed_pin_config aspeed_g4_configs[] = { /* GPIO banks ranges [A, B], [D, J], [M, R] */ - { PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 }, - { PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31), /* GPIOs T[0-5] (RGMII1 Tx pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12), /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14), /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13), /* GPIOs V[2-7] (RGMII2 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15), /* ADC pull-downs (SCUA8[19:4]) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19), /* * Debounce settings for GPIOs D and E passthrough mode are in @@ -2402,14 +2531,14 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = { * controller. Due to this tangle between GPIO and pinctrl we don't yet * fully support pass-through debounce. */ - { PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 }, + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27), }; static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, @@ -2465,6 +2594,14 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, +}; + static const struct aspeed_pinmux_ops aspeed_g4_ops = { .set = aspeed_g4_sig_expr_set, }; @@ -2481,6 +2618,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { }, .configs = aspeed_g4_configs, .nconfigs = ARRAY_SIZE(aspeed_g4_configs), + .confmaps = aspeed_g4_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map), }; static const struct pinmux_ops aspeed_g4_pinmux_ops = { @@ -2531,6 +2670,10 @@ static int aspeed_g4_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id aspeed_g4_pinctrl_of_match[] = { { .compatible = "aspeed,ast2400-pinctrl", }, + /* + * The aspeed,g4-pinctrl compatible has been removed the from the + * bindings, but keep the match in case of old devicetrees. + */ { .compatible = "aspeed,g4-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index ff84d1afd229..0cab4c2576e2 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -21,6 +21,13 @@ #include "../pinctrl-utils.h" #include "pinctrl-aspeed.h" +/* Wrap some of the common macros for clarity */ +#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \ + SIG_EXPR_DECL(sig, func, func, __VA_ARGS__) + +#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG +#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG + /* * The "Multi-function Pins Mapping and Control" table in the SoC datasheet * references registers by the device/offset mnemonic. The register macros @@ -63,9 +70,9 @@ SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); #define D13 2 -SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); -SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); -MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3); +SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); +SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); +PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3); FUNC_GROUP_DECL(SPI1CS1, D13); FUNC_GROUP_DECL(TIMER3, D13); @@ -75,16 +82,16 @@ SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); #define I2C9_DESC SIG_DESC_SET(SCU90, 22) #define C14 4 -SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); -MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5); +SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); +PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5); FUNC_GROUP_DECL(TIMER5, C14); #define A13 5 -SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); -MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6); +SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); +PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6); FUNC_GROUP_DECL(TIMER6, A13); @@ -93,16 +100,16 @@ FUNC_GROUP_DECL(I2C9, C14, A13); #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) #define C13 6 -SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); -MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7); +SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); +PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7); FUNC_GROUP_DECL(TIMER7, C13); #define B13 7 -SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); -MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8); +SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); +PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8); FUNC_GROUP_DECL(TIMER8, B13); @@ -125,9 +132,9 @@ SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); #define H21 13 #define H21_DESC SIG_DESC_SET(SCU80, 13) -SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC); -MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI); +SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC); +PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI); FUNC_GROUP_DECL(LPCPD, H21); FUNC_GROUP_DECL(LPCSMI, H21); @@ -141,53 +148,53 @@ GPIO_PIN_DECL(H20, GPIOB7); #define C12 16 #define I2C10_DESC SIG_DESC_SET(SCU90, 23) -SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); -MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10); +SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC); +PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10); #define A12 17 -SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); -MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10); +SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC); +PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10); FUNC_GROUP_DECL(I2C10, C12, A12); #define B12 18 #define I2C11_DESC SIG_DESC_SET(SCU90, 24) -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); -MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11); +SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC); +PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11); #define D9 19 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); -MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11); +SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC); +PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11); FUNC_GROUP_DECL(I2C11, B12, D9); #define D10 20 #define I2C12_DESC SIG_DESC_SET(SCU90, 25) -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); -MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12); +SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC); +PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12); #define E12 21 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); -MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12); +SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC); +PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12); FUNC_GROUP_DECL(I2C12, D10, E12); #define C11 22 #define I2C13_DESC SIG_DESC_SET(SCU90, 26) -SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); -MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13); +SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC); +PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13); #define B11 23 -SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); -MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13); +SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC); +PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13); FUNC_GROUP_DECL(I2C13, C11, B11); FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); @@ -197,72 +204,72 @@ FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) #define F19 24 -SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); -MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN); +SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID); +PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN); #define E21 25 -SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); -MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT); +SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID); +PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT); FUNC_GROUP_DECL(GPID0, F19, E21); #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) #define F20 26 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); -MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN); +SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID); +PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN); #define D20 27 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); -MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT); +SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID); +PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT); FUNC_GROUP_DECL(GPID2, F20, D20); #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) #define D21 28 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); -MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN); +SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID); +PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN); #define E20 29 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); -MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT); +SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID); +PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT); FUNC_GROUP_DECL(GPID4, D21, E20); #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) #define G18 30 -SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); -MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN); +SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID); +PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN); #define C21 31 -SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); -MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT); +SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID); +PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT); FUNC_GROUP_DECL(GPID6, G18, C21); FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); @@ -271,19 +278,19 @@ FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) #define B20 32 -SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); -SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); -MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); +SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE); +PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN); FUNC_GROUP_DECL(NCTS3, B20); #define C20 33 -SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); -SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); -MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); +SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE); +PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT); FUNC_GROUP_DECL(NDCD3, C20); FUNC_GROUP_DECL(GPIE0, B20, C20); @@ -291,20 +298,20 @@ FUNC_GROUP_DECL(GPIE0, B20, C20); #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) #define F18 34 -SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); -SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); -MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN); +SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE); +PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN); FUNC_GROUP_DECL(NDSR3, F18); #define F17 35 -SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); -SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); -MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT); +SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE); +PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT); FUNC_GROUP_DECL(NRI3, F17); FUNC_GROUP_DECL(GPIE2, F18, F17); @@ -312,19 +319,19 @@ FUNC_GROUP_DECL(GPIE2, F18, F17); #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) #define E18 36 -SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); -SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); -MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN); +SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE); +PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN); FUNC_GROUP_DECL(NDTR3, E18); #define D19 37 -SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); -SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); -MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT); +SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE); +PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT); FUNC_GROUP_DECL(NRTS3, D19); FUNC_GROUP_DECL(GPIE4, E18, D19); @@ -332,19 +339,19 @@ FUNC_GROUP_DECL(GPIE4, E18, D19); #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) #define A20 38 -SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); -SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); -MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN); +SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE); +PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN); FUNC_GROUP_DECL(TXD3, A20); #define B19 39 -SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); -SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); -MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT); +SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE); +PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT); FUNC_GROUP_DECL(RXD3, B19); FUNC_GROUP_DECL(GPIE6, A20, B19); @@ -353,112 +360,112 @@ FUNC_GROUP_DECL(GPIE6, A20, B19); #define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30) #define J19 40 -SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); -MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4); +SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); +PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4); FUNC_GROUP_DECL(NCTS4, J19); #define J18 41 -SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); -MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4); +SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4); FUNC_GROUP_DECL(NDCD4, J18); #define B22 42 -SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); -MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4); +SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4); FUNC_GROUP_DECL(NDSR4, B22); #define B21 43 -SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); -MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4); +SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4); FUNC_GROUP_DECL(NRI4, B21); #define A21 44 -SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); -MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4); +SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); +PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4); FUNC_GROUP_DECL(NDTR4, A21); #define H19 45 -SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); -MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4); +SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); +PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4); FUNC_GROUP_DECL(NRTS4, H19); #define G17 46 -SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); -MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4); +SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); +PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4); FUNC_GROUP_DECL(TXD4, G17); #define H18 47 -SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); -MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4); +SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); +PIN_DECL_2(H18, GPIOF7, LHRST, RXD4); FUNC_GROUP_DECL(RXD4, H18); FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18); FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18); #define A19 48 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); -SS_PIN_DECL(A19, GPIOG0, SGPS1CK); +SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); +PIN_DECL_1(A19, GPIOG0, SGPS1CK); #define E19 49 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); -SS_PIN_DECL(E19, GPIOG1, SGPS1LD); +SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); +PIN_DECL_1(E19, GPIOG1, SGPS1LD); #define C19 50 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); -SS_PIN_DECL(C19, GPIOG2, SGPS1I0); +SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); +PIN_DECL_1(C19, GPIOG2, SGPS1I0); #define E16 51 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); -SS_PIN_DECL(E16, GPIOG3, SGPS1I1); +SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); +PIN_DECL_1(E16, GPIOG3, SGPS1I1); FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16); #define SGPS2_DESC SIG_DESC_SET(SCU94, 12) #define E17 52 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); -MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1); +SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); +PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1); FUNC_GROUP_DECL(SALT1, E17); #define D16 53 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); -MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2); +SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); +PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2); FUNC_GROUP_DECL(SALT2, D16); #define D15 54 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); -MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3); +SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); +PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3); FUNC_GROUP_DECL(SALT3, D15); #define E14 55 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); -MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4); +SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); +PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4); FUNC_GROUP_DECL(SALT4, E14); FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); @@ -466,42 +473,42 @@ FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); #define UART6_DESC SIG_DESC_SET(SCU90, 7) #define A18 56 -SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); -SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6); +SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC); +PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6); #define B18 57 -SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); -SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6); +SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC); +PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6); #define D17 58 -SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); -SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6); +SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC); +PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6); #define C17 59 -SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); -SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6); +SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC); +PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6); #define A17 60 -SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); -SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6); +SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC); +PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6); #define B17 61 -SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); -SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6); +SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC); +PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6); #define A16 62 -SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC); -SS_PIN_DECL(A16, GPIOH6, TXD6); +SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC); +PIN_DECL_1(A16, GPIOH6, TXD6); #define D18 63 -SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC); -SS_PIN_DECL(D18, GPIOH7, RXD6); +SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC); +PIN_DECL_1(D18, GPIOH7, RXD6); FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); @@ -513,70 +520,78 @@ FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } #define C18 64 -SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C18, GPIOI0, SYSCS); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C18, GPIOI0, SYSCS); #define E15 65 -SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(E15, GPIOI1, SYSCK); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(E15, GPIOI1, SYSCK); #define B16 66 -SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(B16, GPIOI2, SYSMOSI); +SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(B16, GPIOI2, SYSMOSI); #define C16 67 -SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C16, GPIOI3, SYSMISO); +SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C16, GPIOI3, SYSMISO); #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) #define B15 68 -SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CS0, SPI1, + SIG_EXPR_PTR(SPI1CS0, SPI1), SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS); +SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS); #define C15 69 -SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CK, SPI1, + SIG_EXPR_PTR(SPI1CK, SPI1), SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK); +SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK); #define A14 70 -SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1, + SIG_EXPR_PTR(SPI1MOSI, SPI1), SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG), SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI); +SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI); #define A15 71 -SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1MISO, SPI1, + SIG_EXPR_PTR(SPI1MISO, SPI1), SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG), SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO); +SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO); FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15); FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15); @@ -584,92 +599,92 @@ FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15); FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15); #define R2 72 -SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); -SS_PIN_DECL(R2, GPIOJ0, SGPMCK); +SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); +PIN_DECL_1(R2, GPIOJ0, SGPMCK); #define L2 73 -SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); -SS_PIN_DECL(L2, GPIOJ1, SGPMLD); +SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); +PIN_DECL_1(L2, GPIOJ1, SGPMLD); #define N3 74 -SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); -SS_PIN_DECL(N3, GPIOJ2, SGPMO); +SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); +PIN_DECL_1(N3, GPIOJ2, SGPMO); #define N4 75 -SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); -SS_PIN_DECL(N4, GPIOJ3, SGPMI); +SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); +PIN_DECL_1(N4, GPIOJ3, SGPMI); FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4); #define N5 76 -SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); -SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); -MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5); +SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); +SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); +PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5); FUNC_GROUP_DECL(VGAHS, N5); #define R4 77 -SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); -SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); -MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4); +SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); +SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); +PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4); FUNC_GROUP_DECL(VGAVS, R4); #define R3 78 -SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); -SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); -MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3); +SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); +SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); +PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3); FUNC_GROUP_DECL(DDCCLK, R3); #define T3 79 -SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); -SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); -MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3); +SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); +SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); +PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3); FUNC_GROUP_DECL(DDCDAT, T3); #define I2C5_DESC SIG_DESC_SET(SCU90, 18) #define L3 80 -SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); -SS_PIN_DECL(L3, GPIOK0, SCL5); +SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC); +PIN_DECL_1(L3, GPIOK0, SCL5); #define L4 81 -SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); -SS_PIN_DECL(L4, GPIOK1, SDA5); +SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC); +PIN_DECL_1(L4, GPIOK1, SDA5); FUNC_GROUP_DECL(I2C5, L3, L4); #define I2C6_DESC SIG_DESC_SET(SCU90, 19) #define L1 82 -SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); -SS_PIN_DECL(L1, GPIOK2, SCL6); +SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC); +PIN_DECL_1(L1, GPIOK2, SCL6); #define N2 83 -SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); -SS_PIN_DECL(N2, GPIOK3, SDA6); +SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC); +PIN_DECL_1(N2, GPIOK3, SDA6); FUNC_GROUP_DECL(I2C6, L1, N2); #define I2C7_DESC SIG_DESC_SET(SCU90, 20) #define N1 84 -SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); -SS_PIN_DECL(N1, GPIOK4, SCL7); +SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC); +PIN_DECL_1(N1, GPIOK4, SCL7); #define P1 85 -SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); -SS_PIN_DECL(P1, GPIOK5, SDA7); +SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC); +PIN_DECL_1(P1, GPIOK5, SDA7); FUNC_GROUP_DECL(I2C7, N1, P1); #define I2C8_DESC SIG_DESC_SET(SCU90, 21) #define P2 86 -SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); -SS_PIN_DECL(P2, GPIOK6, SCL8); +SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC); +PIN_DECL_1(P2, GPIOK6, SCL8); #define R1 87 -SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); -SS_PIN_DECL(R1, GPIOK7, SDA8); +SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC); +PIN_DECL_1(R1, GPIOK7, SDA8); FUNC_GROUP_DECL(I2C8, P2, R1); @@ -684,290 +699,290 @@ SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); #define T1 89 #define T1_DESC SIG_DESC_SET(SCU84, 17) -SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2); -MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1); +SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2); +PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1); FUNC_GROUP_DECL(NDCD1, T1); #define U1 90 #define U1_DESC SIG_DESC_SET(SCU84, 18) -SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC); -MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1); +SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC); +PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1); FUNC_GROUP_DECL(NDSR1, U1); #define U2 91 #define U2_DESC SIG_DESC_SET(SCU84, 19) -SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2); -MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1); +SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2); +PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1); FUNC_GROUP_DECL(NRI1, U2); #define P4 92 #define P4_DESC SIG_DESC_SET(SCU84, 20) -SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2); -MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1); +SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2); +PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1); FUNC_GROUP_DECL(NDTR1, P4); #define P3 93 #define P3_DESC SIG_DESC_SET(SCU84, 21) -SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2); -MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1); +SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2); +PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1); FUNC_GROUP_DECL(NRTS1, P3); #define V1 94 #define V1_DESC SIG_DESC_SET(SCU84, 22) -SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2); -MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1); +SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2); +PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1); FUNC_GROUP_DECL(TXD1, V1); #define W1 95 #define W1_DESC SIG_DESC_SET(SCU84, 23) -SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2); -MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1); +SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2); +PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1); FUNC_GROUP_DECL(RXD1, W1); #define Y1 96 #define Y1_DESC SIG_DESC_SET(SCU84, 24) -SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2); -MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2); +SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2); +PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2); FUNC_GROUP_DECL(NCTS2, Y1); #define AB2 97 #define AB2_DESC SIG_DESC_SET(SCU84, 25) -SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2); -MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2); +SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2); +PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2); FUNC_GROUP_DECL(NDCD2, AB2); #define AA1 98 #define AA1_DESC SIG_DESC_SET(SCU84, 26) -SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2); -MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2); +SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2); +PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2); FUNC_GROUP_DECL(NDSR2, AA1); #define Y2 99 #define Y2_DESC SIG_DESC_SET(SCU84, 27) -SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2); -MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2); +SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2); +PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2); FUNC_GROUP_DECL(NRI2, Y2); #define AA2 100 #define AA2_DESC SIG_DESC_SET(SCU84, 28) -SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2); -MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2); +SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2); +PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2); FUNC_GROUP_DECL(NDTR2, AA2); #define P5 101 #define P5_DESC SIG_DESC_SET(SCU84, 29) -SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2); -MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2); +SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2); +PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2); FUNC_GROUP_DECL(NRTS2, P5); #define R5 102 #define R5_DESC SIG_DESC_SET(SCU84, 30) -SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2); -MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2); +SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2); +PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2); FUNC_GROUP_DECL(TXD2, R5); #define T5 103 #define T5_DESC SIG_DESC_SET(SCU84, 31) -SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2); -MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2); +SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2); +PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2); FUNC_GROUP_DECL(RXD2, T5); #define V2 104 #define V2_DESC SIG_DESC_SET(SCU88, 0) -SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2); -MS_PIN_DECL(V2, GPION0, DASHN0, PWM0); +SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2); +PIN_DECL_2(V2, GPION0, DASHN0, PWM0); FUNC_GROUP_DECL(PWM0, V2); #define W2 105 #define W2_DESC SIG_DESC_SET(SCU88, 1) -SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2); -MS_PIN_DECL(W2, GPION1, DASHN1, PWM1); +SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2); +PIN_DECL_2(W2, GPION1, DASHN1, PWM1); FUNC_GROUP_DECL(PWM1, W2); #define V3 106 #define V3_DESC SIG_DESC_SET(SCU88, 2) -SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); -SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2); -MS_PIN_DECL(V3, GPION2, VPIG2, PWM2); +SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2); +PIN_DECL_2(V3, GPION2, VPIG2, PWM2); FUNC_GROUP_DECL(PWM2, V3); #define U3 107 #define U3_DESC SIG_DESC_SET(SCU88, 3) -SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); -SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2); -MS_PIN_DECL(U3, GPION3, VPIG3, PWM3); +SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2); +PIN_DECL_2(U3, GPION3, VPIG3, PWM3); FUNC_GROUP_DECL(PWM3, U3); #define W3 108 #define W3_DESC SIG_DESC_SET(SCU88, 4) -SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); -SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2); -MS_PIN_DECL(W3, GPION4, VPIG4, PWM4); +SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2); +PIN_DECL_2(W3, GPION4, VPIG4, PWM4); FUNC_GROUP_DECL(PWM4, W3); #define AA3 109 #define AA3_DESC SIG_DESC_SET(SCU88, 5) -SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); -SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2); -MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5); +SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2); +PIN_DECL_2(AA3, GPION5, VPIG5, PWM5); FUNC_GROUP_DECL(PWM5, AA3); #define Y3 110 #define Y3_DESC SIG_DESC_SET(SCU88, 6) -SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2); -MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6); +SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2); +PIN_DECL_2(Y3, GPION6, VPIG6, PWM6); FUNC_GROUP_DECL(PWM6, Y3); #define T4 111 #define T4_DESC SIG_DESC_SET(SCU88, 7) -SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); -MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); +SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2); +PIN_DECL_2(T4, GPION7, VPIG7, PWM7); FUNC_GROUP_DECL(PWM7, T4); #define U5 112 -SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), +SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), COND2); -SS_PIN_DECL(U5, GPIOO0, VPIG8); +PIN_DECL_1(U5, GPIOO0, VPIG8); #define U4 113 -SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), +SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), COND2); -SS_PIN_DECL(U4, GPIOO1, VPIG9); +PIN_DECL_1(U4, GPIOO1, VPIG9); #define V5 114 -SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC, +SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC, SIG_DESC_SET(SCU88, 10)); -SS_PIN_DECL(V5, GPIOO2, DASHV5); +PIN_DECL_1(V5, GPIOO2, DASHV5); #define AB4 115 -SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC, +SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC, SIG_DESC_SET(SCU88, 11)); -SS_PIN_DECL(AB4, GPIOO3, DASHAB4); +PIN_DECL_1(AB4, GPIOO3, DASHAB4); #define AB3 116 -SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12), - COND2); -SS_PIN_DECL(AB3, GPIOO4, VPIR2); +SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 12), COND2); +PIN_DECL_1(AB3, GPIOO4, VPIR2); #define Y4 117 -SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13), - COND2); -SS_PIN_DECL(Y4, GPIOO5, VPIR3); +SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 13), COND2); +PIN_DECL_1(Y4, GPIOO5, VPIR3); #define AA4 118 -SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14), - COND2); -SS_PIN_DECL(AA4, GPIOO6, VPIR4); +SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 14), COND2); +PIN_DECL_1(AA4, GPIOO6, VPIR4); #define W4 119 -SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15), - COND2); -SS_PIN_DECL(W4, GPIOO7, VPIR5); +SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 15), COND2); +PIN_DECL_1(W4, GPIOO7, VPIR5); #define V4 120 -SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16), - COND2); -SS_PIN_DECL(V4, GPIOP0, VPIR6); +SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 16), COND2); +PIN_DECL_1(V4, GPIOP0, VPIR6); #define W5 121 -SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17), - COND2); -SS_PIN_DECL(W5, GPIOP1, VPIR7); +SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 17), COND2); +PIN_DECL_1(W5, GPIOP1, VPIR7); #define AA5 122 -SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18), - COND2); -SS_PIN_DECL(AA5, GPIOP2, VPIR8); +SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 18), COND2); +PIN_DECL_1(AA5, GPIOP2, VPIR8); #define AB5 123 -SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19), - COND2); -SS_PIN_DECL(AB5, GPIOP3, VPIR9); +SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 19), COND2); +PIN_DECL_1(AB5, GPIOP3, VPIR9); FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3, U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5, AB5); #define Y6 124 -SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 20)); -SS_PIN_DECL(Y6, GPIOP4, DASHY6); +PIN_DECL_1(Y6, GPIOP4, DASHY6); #define Y5 125 -SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 21)); -SS_PIN_DECL(Y5, GPIOP5, DASHY5); +PIN_DECL_1(Y5, GPIOP5, DASHY5); #define W6 126 -SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 22)); -SS_PIN_DECL(W6, GPIOP6, DASHW6); +PIN_DECL_1(W6, GPIOP6, DASHW6); #define V6 127 -SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 23)); -SS_PIN_DECL(V6, GPIOP7, DASHV6); +PIN_DECL_1(V6, GPIOP7, DASHV6); #define I2C3_DESC SIG_DESC_SET(SCU90, 16) #define A11 128 -SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); -SS_PIN_DECL(A11, GPIOQ0, SCL3); +SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC); +PIN_DECL_1(A11, GPIOQ0, SCL3); #define A10 129 -SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); -SS_PIN_DECL(A10, GPIOQ1, SDA3); +SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC); +PIN_DECL_1(A10, GPIOQ1, SDA3); FUNC_GROUP_DECL(I2C3, A11, A10); #define I2C4_DESC SIG_DESC_SET(SCU90, 17) #define A9 130 -SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); -SS_PIN_DECL(A9, GPIOQ2, SCL4); +SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC); +PIN_DECL_1(A9, GPIOQ2, SCL4); #define B9 131 -SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); -SS_PIN_DECL(B9, GPIOQ3, SDA4); +SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC); +PIN_DECL_1(B9, GPIOQ3, SDA4); FUNC_GROUP_DECL(I2C4, A9, B9); #define I2C14_DESC SIG_DESC_SET(SCU90, 27) #define N21 132 -SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); -SS_PIN_DECL(N21, GPIOQ4, SCL14); +SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC); +PIN_DECL_1(N21, GPIOQ4, SCL14); #define N22 133 -SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); -SS_PIN_DECL(N22, GPIOQ5, SDA14); +SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC); +PIN_DECL_1(N22, GPIOQ5, SDA14); FUNC_GROUP_DECL(I2C14, N21, N22); @@ -996,12 +1011,12 @@ SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2); SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2); #define D8 142 -SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); -SS_PIN_DECL(D8, GPIOR6, MDC1); +SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); +PIN_DECL_1(D8, GPIOR6, MDC1); #define E10 143 -SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); -SS_PIN_DECL(E10, GPIOR7, MDIO1); +SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); +PIN_DECL_1(E10, GPIOR7, MDIO1); FUNC_GROUP_DECL(MDIO1, D8, E10); @@ -1014,83 +1029,107 @@ FUNC_GROUP_DECL(MDIO1, D8, E10); #define V20 144 #define V20_DESC SIG_DESC_SET(SCU8C, 0) -SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO), - SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC); -MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1); +SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB2, VPO, + SIG_EXPR_PTR(VPOB2, VPO), + SIG_EXPR_PTR(VPOB2, VPOOFF1), + SIG_EXPR_PTR(VPOB2, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO); +SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC); +PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1); FUNC_GROUP_DECL(SPI2CS1, V20); #define U19 145 #define U19_DESC SIG_DESC_SET(SCU8C, 1) -SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO), - SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC); -MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT); +SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB3, VPO, + SIG_EXPR_PTR(VPOB3, VPO), + SIG_EXPR_PTR(VPOB3, VPOOFF1), + SIG_EXPR_PTR(VPOB3, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO); +SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC); +PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT); FUNC_GROUP_DECL(BMCINT, U19); #define R18 146 #define R18_DESC SIG_DESC_SET(SCU8C, 2) -SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO), - SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC); -MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5); +SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB4, VPO, + SIG_EXPR_PTR(VPOB4, VPO), + SIG_EXPR_PTR(VPOB4, VPOOFF1), + SIG_EXPR_PTR(VPOB4, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO); +SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC); +PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5); FUNC_GROUP_DECL(SALT5, R18); #define P18 147 #define P18_DESC SIG_DESC_SET(SCU8C, 3) -SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO), - SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC); -MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6); +SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB5, VPO, + SIG_EXPR_PTR(VPOB5, VPO), + SIG_EXPR_PTR(VPOB5, VPOOFF1), + SIG_EXPR_PTR(VPOB5, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO); +SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC); +PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6); FUNC_GROUP_DECL(SALT6, P18); #define R19 148 #define R19_DESC SIG_DESC_SET(SCU8C, 4) -SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO), - SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2)); -SS_PIN_DECL(R19, GPIOS4, VPOB6); +SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB6, VPO, + SIG_EXPR_PTR(VPOB6, VPO), + SIG_EXPR_PTR(VPOB6, VPOOFF1), + SIG_EXPR_PTR(VPOB6, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO); +PIN_DECL_1(R19, GPIOS4, VPOB6); #define W20 149 #define W20_DESC SIG_DESC_SET(SCU8C, 5) -SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO), - SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2)); -SS_PIN_DECL(W20, GPIOS5, VPOB7); +SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB7, VPO, + SIG_EXPR_PTR(VPOB7, VPO), + SIG_EXPR_PTR(VPOB7, VPOOFF1), + SIG_EXPR_PTR(VPOB7, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO); +PIN_DECL_1(W20, GPIOS5, VPOB7); #define U20 150 #define U20_DESC SIG_DESC_SET(SCU8C, 6) -SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO), - SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2)); -SS_PIN_DECL(U20, GPIOS6, VPOB8); +SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB8, VPO, + SIG_EXPR_PTR(VPOB8, VPO), + SIG_EXPR_PTR(VPOB8, VPOOFF1), + SIG_EXPR_PTR(VPOB8, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO); +PIN_DECL_1(U20, GPIOS6, VPOB8); #define AA20 151 #define AA20_DESC SIG_DESC_SET(SCU8C, 7) -SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO), - SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2)); -SS_PIN_DECL(AA20, GPIOS7, VPOB9); +SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB9, VPO, + SIG_EXPR_PTR(VPOB9, VPO), + SIG_EXPR_PTR(VPOB9, VPOOFF1), + SIG_EXPR_PTR(VPOB9, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO); +PIN_DECL_1(AA20, GPIOS7, VPOB9); /* RGMII1/RMII1 */ @@ -1098,309 +1137,309 @@ SS_PIN_DECL(AA20, GPIOS7, VPOB9); #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) #define B5 152 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC, +SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); +SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC, SIG_DESC_SET(SCU48, 29)); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); -MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO), - SIG_EXPR_LIST_PTR(RGMII1TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1); +PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO), + SIG_EXPR_LIST_PTR(B5, RGMII1TXCK)); #define E9 153 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); -MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN), - SIG_EXPR_LIST_PTR(RGMII1TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); +SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1); +PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN), + SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL)); #define F9 154 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); -MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), - SIG_EXPR_LIST_PTR(RGMII1TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); +SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1); +PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0), + SIG_EXPR_LIST_PTR(F9, RGMII1TXD0)); #define A5 155 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); -MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), - SIG_EXPR_LIST_PTR(RGMII1TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); +SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1); +PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1), + SIG_EXPR_LIST_PTR(A5, RGMII1TXD1)); #define E7 156 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); -MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0), - SIG_EXPR_LIST_PTR(RGMII1TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); +SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1); +PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0), + SIG_EXPR_LIST_PTR(E7, RGMII1TXD2)); #define D7 157 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); -MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1), - SIG_EXPR_LIST_PTR(RGMII1TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); +SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1); +PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1), + SIG_EXPR_LIST_PTR(D7, RGMII1TXD3)); #define B2 158 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC, +SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); +SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC, SIG_DESC_SET(SCU48, 30)); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); -MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO), - SIG_EXPR_LIST_PTR(RGMII2TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2); +PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO), + SIG_EXPR_LIST_PTR(B2, RGMII2TXCK)); #define B1 159 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); -MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN), - SIG_EXPR_LIST_PTR(RGMII2TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); +SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2); +PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN), + SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL)); #define A2 160 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); -MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), - SIG_EXPR_LIST_PTR(RGMII2TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); +SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2); +PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0), + SIG_EXPR_LIST_PTR(A2, RGMII2TXD0)); #define B3 161 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); -MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), - SIG_EXPR_LIST_PTR(RGMII2TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); +SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2); +PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1), + SIG_EXPR_LIST_PTR(B3, RGMII2TXD1)); #define D5 162 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); -MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0), - SIG_EXPR_LIST_PTR(RGMII2TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); +SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2); +PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0), + SIG_EXPR_LIST_PTR(D5, RGMII2TXD2)); #define D4 163 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); -MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1), - SIG_EXPR_LIST_PTR(RGMII2TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); +SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2); +PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1), + SIG_EXPR_LIST_PTR(D4, RGMII2TXD3)); #define B4 164 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); -MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI), - SIG_EXPR_LIST_PTR(RGMII1RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); +SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1); +PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI), + SIG_EXPR_LIST_PTR(B4, RGMII1RXCK)); #define A4 165 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); -MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2), - SIG_EXPR_LIST_PTR(RGMII1RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); +SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1); +PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2), + SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL)); #define A3 166 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); -MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), - SIG_EXPR_LIST_PTR(RGMII1RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); +SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1); +PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0), + SIG_EXPR_LIST_PTR(A3, RGMII1RXD0)); #define D6 167 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); -MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), - SIG_EXPR_LIST_PTR(RGMII1RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); +SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1); +PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1), + SIG_EXPR_LIST_PTR(D6, RGMII1RXD1)); #define C5 168 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); -MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), - SIG_EXPR_LIST_PTR(RGMII1RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); +SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1); +PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV), + SIG_EXPR_LIST_PTR(C5, RGMII1RXD2)); #define C4 169 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); -MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), - SIG_EXPR_LIST_PTR(RGMII1RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); +SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1); +PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER), + SIG_EXPR_LIST_PTR(C4, RGMII1RXD3)); FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7); FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5); #define C2 170 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); -MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI), - SIG_EXPR_LIST_PTR(RGMII2RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); +SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2); +PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI), + SIG_EXPR_LIST_PTR(C2, RGMII2RXCK)); #define C1 171 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); -MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2), - SIG_EXPR_LIST_PTR(RGMII2RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); +SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2); +PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2), + SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL)); #define C3 172 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); -MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), - SIG_EXPR_LIST_PTR(RGMII2RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); +SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2); +PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0), + SIG_EXPR_LIST_PTR(C3, RGMII2RXD0)); #define D1 173 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); -MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), - SIG_EXPR_LIST_PTR(RGMII2RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); +SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2); +PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1), + SIG_EXPR_LIST_PTR(D1, RGMII2RXD1)); #define D2 174 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); -MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), - SIG_EXPR_LIST_PTR(RGMII2RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); +SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2); +PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV), + SIG_EXPR_LIST_PTR(D2, RGMII2RXD2)); #define E6 175 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); -MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), - SIG_EXPR_LIST_PTR(RGMII2RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); +SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2); +PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER), + SIG_EXPR_LIST_PTR(E6, RGMII2RXD3)); FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); #define F4 176 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); -SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); -MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0); +PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0)); FUNC_GROUP_DECL(ADC0, F4); #define F5 177 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); -SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); -MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1); +PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1)); FUNC_GROUP_DECL(ADC1, F5); #define E2 178 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); -SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); -MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2); +PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2)); FUNC_GROUP_DECL(ADC2, E2); #define E1 179 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); -SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); -MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3); +PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3)); FUNC_GROUP_DECL(ADC3, E1); #define F3 180 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); -SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); -MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4); +PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4)); FUNC_GROUP_DECL(ADC4, F3); #define E3 181 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); -SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); -MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5); +PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5)); FUNC_GROUP_DECL(ADC5, E3); #define G5 182 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); -SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); -MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6); +PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6)); FUNC_GROUP_DECL(ADC6, G5); #define G4 183 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); -SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); -MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7); +PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7)); FUNC_GROUP_DECL(ADC7, G4); #define F2 184 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); -SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); -MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8); +PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8)); FUNC_GROUP_DECL(ADC8, F2); #define G3 185 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); -SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); -MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9); +PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9)); FUNC_GROUP_DECL(ADC9, G3); #define G2 186 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); -SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); -MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10); +PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10)); FUNC_GROUP_DECL(ADC10, G2); #define F1 187 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); -SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); -MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11); +PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11)); FUNC_GROUP_DECL(ADC11, F1); #define H5 188 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); -SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); -MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12); +PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12)); FUNC_GROUP_DECL(ADC12, H5); #define G1 189 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); -SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); -MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13); +PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13)); FUNC_GROUP_DECL(ADC13, G1); #define H3 190 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); -SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); -MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14); +PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14)); FUNC_GROUP_DECL(ADC14, H3); #define H4 191 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); -SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); -MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15); +PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15)); FUNC_GROUP_DECL(ADC15, H4); #define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19) #define R22 192 -SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); -SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); -MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22); +SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); +PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22); FUNC_GROUP_DECL(SIOS3, R22); #define R21 193 -SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); -SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); -MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21); +SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); +PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21); FUNC_GROUP_DECL(SIOS5, R21); #define P22 194 -SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); -SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); -MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); +PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22); FUNC_GROUP_DECL(SIOPWREQ, P22); #define P21 195 -SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); -SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); -MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); +PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21); FUNC_GROUP_DECL(SIOONCTRL, P21); #define M18 196 @@ -1419,66 +1458,81 @@ SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15)); #define Y20 200 #define Y20_DESC SIG_DESC_SET(SCUA4, 16) -SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO), - SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2)); -SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC); -SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0); -MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI), - SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0)); +SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG2, VPO, + SIG_EXPR_PTR(VPOG2, VPO), + SIG_EXPR_PTR(VPOG2, VPOOFF1), + SIG_EXPR_PTR(VPOG2, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO); +SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC); +SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC); +SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0); +PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI), + SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0)); FUNC_GROUP_DECL(SIOPBI, Y20); #define AB20 201 #define AB20_DESC SIG_DESC_SET(SCUA4, 17) -SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO), - SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2)); -SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC); -SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1); -MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD), - SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1)); +SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG3, VPO, + SIG_EXPR_PTR(VPOG3, VPO), + SIG_EXPR_PTR(VPOG3, VPOOFF1), + SIG_EXPR_PTR(VPOG3, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC); +SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1); +PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3), + SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1), + SIG_EXPR_LIST_PTR(AB20, GPIOZ1)); FUNC_GROUP_DECL(SIOPWRGD, AB20); #define AB21 202 #define AB21_DESC SIG_DESC_SET(SCUA4, 18) -SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO), - SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2)); -SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC); -SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2); -MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO), - SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2)); +SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG4, VPO, + SIG_EXPR_PTR(VPOG4, VPO), + SIG_EXPR_PTR(VPOG4, VPOOFF1), + SIG_EXPR_PTR(VPOG4, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO); +SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC); +SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC); +SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2); +PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4), + SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2), + SIG_EXPR_LIST_PTR(AB21, GPIOZ2)); FUNC_GROUP_DECL(SIOPBO, AB21); #define AA21 203 #define AA21_DESC SIG_DESC_SET(SCUA4, 19) -SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO), - SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2)); -SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC); -SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3); -MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI), - SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3)); +SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG5, VPO, + SIG_EXPR_PTR(VPOG5, VPO), + SIG_EXPR_PTR(VPOG5, VPOOFF1), + SIG_EXPR_PTR(VPOG5, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO); +SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC); +SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC); +SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3); +PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5), + SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3), + SIG_EXPR_LIST_PTR(AA21, GPIOZ3)); FUNC_GROUP_DECL(SIOSCI, AA21); FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); @@ -1497,199 +1551,248 @@ FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); #define U21 204 #define U21_DESC SIG_DESC_SET(SCUA4, 20) -SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO), - SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC); -MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4); +SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG6, VPO, + SIG_EXPR_PTR(VPOG6, VPO), + SIG_EXPR_PTR(VPOG6, VPOOFF1), + SIG_EXPR_PTR(VPOG6, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO); +SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC); +PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4); #define W22 205 #define W22_DESC SIG_DESC_SET(SCUA4, 21) -SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO), - SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC); -MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5); +SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG7, VPO, + SIG_EXPR_PTR(VPOG7, VPO), + SIG_EXPR_PTR(VPOG7, VPOOFF1), + SIG_EXPR_PTR(VPOG7, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO); +SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC); +PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5); #define V22 206 #define V22_DESC SIG_DESC_SET(SCUA4, 22) -SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO), - SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC); -MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6); +SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG8, VPO, + SIG_EXPR_PTR(VPOG8, VPO), + SIG_EXPR_PTR(VPOG8, VPOOFF1), + SIG_EXPR_PTR(VPOG8, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO); +SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC); +PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6); #define W21 207 #define W21_DESC SIG_DESC_SET(SCUA4, 23) -SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO), - SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC); -MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7); +SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG9, VPO, + SIG_EXPR_PTR(VPOG9, VPO), + SIG_EXPR_PTR(VPOG9, VPOOFF1), + SIG_EXPR_PTR(VPOG9, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO); +SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC); +PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7); #define Y21 208 #define Y21_DESC SIG_DESC_SET(SCUA4, 24) -SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO), - SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0); -MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7), - SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0)); +SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR2, VPO, + SIG_EXPR_PTR(VPOR2, VPO), + SIG_EXPR_PTR(VPOR2, VPOOFF1), + SIG_EXPR_PTR(VPOR2, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO); +SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0); +PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7), + SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0)); FUNC_GROUP_DECL(SALT7, Y21); #define V21 209 #define V21_DESC SIG_DESC_SET(SCUA4, 25) -SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO), - SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1); -MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8), - SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1)); +SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR3, VPO, + SIG_EXPR_PTR(VPOR3, VPO), + SIG_EXPR_PTR(VPOR3, VPOOFF1), + SIG_EXPR_PTR(VPOR3, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO); +SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1); +PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8), + SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1)); FUNC_GROUP_DECL(SALT8, V21); #define Y22 210 #define Y22_DESC SIG_DESC_SET(SCUA4, 26) -SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO), - SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2); -MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9), - SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2)); +SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR4, VPO, + SIG_EXPR_PTR(VPOR4, VPO), + SIG_EXPR_PTR(VPOR4, VPOOFF1), + SIG_EXPR_PTR(VPOR4, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO); +SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2); +PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9), + SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2)); FUNC_GROUP_DECL(SALT9, Y22); #define AA22 211 #define AA22_DESC SIG_DESC_SET(SCUA4, 27) -SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO), - SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3); -MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10), - SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3)); +SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR5, VPO, + SIG_EXPR_PTR(VPOR5, VPO), + SIG_EXPR_PTR(VPOR5, VPOOFF1), + SIG_EXPR_PTR(VPOR5, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO); +SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3); +PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5), + SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3), + SIG_EXPR_LIST_PTR(AA22, GPIOAA3)); FUNC_GROUP_DECL(SALT10, AA22); #define U22 212 #define U22_DESC SIG_DESC_SET(SCUA4, 28) -SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO), - SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4); -MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11), - SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4)); +SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR6, VPO, + SIG_EXPR_PTR(VPOR6, VPO), + SIG_EXPR_PTR(VPOR6, VPOOFF1), + SIG_EXPR_PTR(VPOR6, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO); +SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4); +PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11), + SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4)); FUNC_GROUP_DECL(SALT11, U22); #define T20 213 #define T20_DESC SIG_DESC_SET(SCUA4, 29) -SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO), - SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5); -MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12), - SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5)); +SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR7, VPO, + SIG_EXPR_PTR(VPOR7, VPO), + SIG_EXPR_PTR(VPOR7, VPOOFF1), + SIG_EXPR_PTR(VPOR7, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO); +SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC); +SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5); +PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12), + SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5)); FUNC_GROUP_DECL(SALT12, T20); #define N18 214 #define N18_DESC SIG_DESC_SET(SCUA4, 30) -SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO), - SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6); -MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13), - SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6)); +SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR8, VPO, + SIG_EXPR_PTR(VPOR8, VPO), + SIG_EXPR_PTR(VPOR8, VPOOFF1), + SIG_EXPR_PTR(VPOR8, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO); +SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC); +SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6); +PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13), + SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6)); FUNC_GROUP_DECL(SALT13, N18); #define P19 215 #define P19_DESC SIG_DESC_SET(SCUA4, 31) -SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO), - SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7); -MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14), - SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7)); +SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR9, VPO, + SIG_EXPR_PTR(VPOR9, VPO), + SIG_EXPR_PTR(VPOR9, VPOOFF1), + SIG_EXPR_PTR(VPOR9, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO); +SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7); +PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14), + SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7)); FUNC_GROUP_DECL(SALT14, P19); #define N19 216 #define N19_DESC SIG_DESC_SET(SCUA8, 0) -SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO), - SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC); -MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE); +SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPODE, VPO, + SIG_EXPR_PTR(VPODE, VPO), + SIG_EXPR_PTR(VPODE, VPOOFF1), + SIG_EXPR_PTR(VPODE, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO); +SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC); +PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE); #define T21 217 #define T21_DESC SIG_DESC_SET(SCUA8, 1) -SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO), - SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC); -MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE); +SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOHS, VPO, + SIG_EXPR_PTR(VPOHS, VPO), + SIG_EXPR_PTR(VPOHS, VPOOFF1), + SIG_EXPR_PTR(VPOHS, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO); +SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC); +PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE); FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20, N18, P19, N19, T21); #define T22 218 #define T22_DESC SIG_DESC_SET(SCUA8, 2) -SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO), - SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC); -MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1); +SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOVS, VPO, + SIG_EXPR_PTR(VPOVS, VPO), + SIG_EXPR_PTR(VPOVS, VPOOFF1), + SIG_EXPR_PTR(VPOVS, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO); +SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC); +PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1); FUNC_GROUP_DECL(WDTRST1, T22); #define R20 219 #define R20_DESC SIG_DESC_SET(SCUA8, 3) -SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO), - SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC); -MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOCLK, VPO, + SIG_EXPR_PTR(VPOCLK, VPO), + SIG_EXPR_PTR(VPOCLK, VPOOFF1), + SIG_EXPR_PTR(VPOCLK, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO); +SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC); +PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2); FUNC_GROUP_DECL(WDTRST2, R20); FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, @@ -1699,64 +1802,64 @@ FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, #define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25) #define G21 224 -SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); -MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0); +SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); +PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0); FUNC_GROUP_DECL(LAD0, G21); #define G20 225 -SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); -MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1); +SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); +PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1); FUNC_GROUP_DECL(LAD1, G20); #define D22 226 -SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); -MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2); +SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); +PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2); FUNC_GROUP_DECL(LAD2, D22); #define E22 227 -SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); -MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3); +SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); +PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3); FUNC_GROUP_DECL(LAD3, E22); #define C22 228 -SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); -MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK); +SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); +PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK); FUNC_GROUP_DECL(LCLK, C22); #define F21 229 -SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); -MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME); +SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); +PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME); FUNC_GROUP_DECL(LFRAME, F21); #define F22 230 -SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); -MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ); +SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); +PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ); FUNC_GROUP_DECL(LSIRQ, F22); #define G22 231 -SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); -MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST); +SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); +PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST); FUNC_GROUP_DECL(LPCRST, G22); FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); #define A7 232 -SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); -SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); -MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP)); +SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP)); #define A8 233 -SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); -SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); -MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN)); +SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN)); FUNC_GROUP_DECL(USB2AH, A7, A8); FUNC_GROUP_DECL(USB2AD, A7, A8); @@ -1767,24 +1870,28 @@ FUNC_GROUP_DECL(USB2AD, A7, A8); #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 } #define B6 234 -SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC); -SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC); -SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC); -SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH), +SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH, + SIG_EXPR_PTR(USB2BHDP1, USB2BH), SIG_EXPR_PTR(USB2BHDP2, USB2BH)); -MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP), - SIG_EXPR_LIST_PTR(USB2BHDP)); +SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH); +PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP), + SIG_EXPR_LIST_PTR(B6, USB2BHDP)); #define A6 235 -SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC); -SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC); -SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC); -SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH), +SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH, + SIG_EXPR_PTR(USB2BHDN1, USB2BH), SIG_EXPR_PTR(USB2BHDN2, USB2BH)); -MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN), - SIG_EXPR_LIST_PTR(USB2BHDN)); +SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH); +PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN), + SIG_EXPR_LIST_PTR(A6, USB2BHDN)); FUNC_GROUP_DECL(USB11BHID, B6, A6); FUNC_GROUP_DECL(USB2BD, B6, A6); @@ -2369,124 +2476,124 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { static struct aspeed_pin_config aspeed_g5_configs[] = { /* GPIOA, GPIOQ */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16), /* GPIOB, GPIOR */ - { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17), /* GPIOC, GPIOS*/ - { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18), /* GPIOD, GPIOY */ - { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19), /* GPIOE, GPIOZ */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20), /* GPIOF, GPIOAA */ - { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21), - /* GPIOG, GPIOAB */ - { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 }, + /* GPIOG, GPIOAB */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22), /* GPIOH, GPIOAC */ - { PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23), /* GPIOs [I, P] */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 }, - { PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31), /* GPIOs T[0-5] (RGMII1 Tx pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 }, - { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12), /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 }, - { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14), /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13), /* GPIOs V[2-7] (RGMII2 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15), /* ADC pull-downs (SCUA8[19:4]) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19), /* * Debounce settings for GPIOs D and E passthrough mode are in @@ -2497,14 +2604,14 @@ static struct aspeed_pin_config aspeed_g5_configs[] = { * controller. Due to this tangle between GPIO and pinctrl we don't yet * fully support pass-through debounce. */ - { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 }, + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27), }; static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx, @@ -2673,6 +2780,14 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, +}; + static const struct aspeed_pinmux_ops aspeed_g5_ops = { .eval = aspeed_g5_sig_expr_eval, .set = aspeed_g5_sig_expr_set, @@ -2690,6 +2805,8 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { }, .configs = aspeed_g5_configs, .nconfigs = ARRAY_SIZE(aspeed_g5_configs), + .confmaps = aspeed_g5_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map), }; static const struct pinmux_ops aspeed_g5_pinmux_ops = { @@ -2742,6 +2859,10 @@ static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id aspeed_g5_pinctrl_of_match[] = { { .compatible = "aspeed,ast2500-pinctrl", }, + /* + * The aspeed,g5-pinctrl compatible has been removed the from the + * bindings, but keep the match in case of old devicetrees. + */ { .compatible = "aspeed,g5-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c new file mode 100644 index 000000000000..fb96e8d2e6c8 --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -0,0 +1,2756 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2019 IBM Corp. */ +#include <linux/bitops.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/string.h> +#include <linux/types.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-aspeed.h" + +#define SCU400 0x400 /* Multi-function Pin Control #1 */ +#define SCU404 0x404 /* Multi-function Pin Control #2 */ +#define SCU410 0x410 /* Multi-function Pin Control #4 */ +#define SCU414 0x414 /* Multi-function Pin Control #5 */ +#define SCU418 0x418 /* Multi-function Pin Control #6 */ +#define SCU41C 0x41C /* Multi-function Pin Control #7 */ +#define SCU430 0x430 /* Multi-function Pin Control #8 */ +#define SCU434 0x434 /* Multi-function Pin Control #9 */ +#define SCU438 0x438 /* Multi-function Pin Control #10 */ +#define SCU440 0x440 /* USB Multi-function Pin Control #12 */ +#define SCU450 0x450 /* Multi-function Pin Control #14 */ +#define SCU454 0x454 /* Multi-function Pin Control #15 */ +#define SCU458 0x458 /* Multi-function Pin Control #16 */ +#define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */ +#define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */ +#define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */ +#define SCU4BC 0x4BC /* Multi-function Pin Control #20 */ +#define SCU4D4 0x4D4 /* Multi-function Pin Control #22 */ +#define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */ +#define SCU500 0x500 /* Hardware Strap 1 */ +#define SCU510 0x510 /* Hardware Strap 2 */ +#define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */ +#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */ +#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */ +#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */ +#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ +#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ +#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ +#define SCU694 0x694 /* Multi-function Pin Control #25 */ +#define SCUC20 0xC20 /* PCIE configuration Setting Control */ + +#define ASPEED_G6_NR_PINS 256 + +#define M24 0 +SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); +SIG_EXPR_LIST_DECL_SESG(M24, SCL11, I2C11, SIG_DESC_SET(SCU4B0, 0)); +PIN_DECL_2(M24, GPIOA0, MDC3, SCL11); + +#define M25 1 +SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1)); +SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1)); +PIN_DECL_2(M25, GPIOA1, MDIO3, SDA11); + +FUNC_GROUP_DECL(MDIO3, M24, M25); +FUNC_GROUP_DECL(I2C11, M24, M25); + +#define L26 2 +SIG_EXPR_LIST_DECL_SESG(L26, MDC4, MDIO4, SIG_DESC_SET(SCU410, 2)); +SIG_EXPR_LIST_DECL_SESG(L26, SCL12, I2C12, SIG_DESC_SET(SCU4B0, 2)); +PIN_DECL_2(L26, GPIOA2, MDC4, SCL12); + +#define K24 3 +SIG_EXPR_LIST_DECL_SESG(K24, MDIO4, MDIO4, SIG_DESC_SET(SCU410, 3)); +SIG_EXPR_LIST_DECL_SESG(K24, SDA12, I2C12, SIG_DESC_SET(SCU4B0, 3)); +PIN_DECL_2(K24, GPIOA3, MDIO4, SDA12); + +FUNC_GROUP_DECL(MDIO4, L26, K24); +FUNC_GROUP_DECL(I2C12, L26, K24); + +#define K26 4 +SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4)); +SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4)); +PIN_DECL_2(K26, GPIOA4, MACLINK1, SCL13); +FUNC_GROUP_DECL(MACLINK1, K26); + +#define L24 5 +SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5)); +SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5)); +PIN_DECL_2(L24, GPIOA5, MACLINK2, SDA13); +FUNC_GROUP_DECL(MACLINK2, L24); + +FUNC_GROUP_DECL(I2C13, K26, L24); + +#define L23 6 +SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6)); +SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6)); +PIN_DECL_2(L23, GPIOA6, MACLINK3, SCL14); +FUNC_GROUP_DECL(MACLINK3, L23); + +#define K25 7 +SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); +SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7)); +PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); +FUNC_GROUP_DECL(MACLINK4, K25); + +FUNC_GROUP_DECL(I2C14, L23, K25); + +#define J26 8 +SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8)); +SIG_EXPR_LIST_DECL_SESG(J26, LHAD0, LPCHC, SIG_DESC_SET(SCU4B0, 8)); +PIN_DECL_2(J26, GPIOB0, SALT1, LHAD0); +FUNC_GROUP_DECL(SALT1, J26); + +#define K23 9 +SIG_EXPR_LIST_DECL_SESG(K23, SALT2, SALT2, SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SESG(K23, LHAD1, LPCHC, SIG_DESC_SET(SCU4B0, 9)); +PIN_DECL_2(K23, GPIOB1, SALT2, LHAD1); +FUNC_GROUP_DECL(SALT2, K23); + +#define H26 10 +SIG_EXPR_LIST_DECL_SESG(H26, SALT3, SALT3, SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SESG(H26, LHAD2, LPCHC, SIG_DESC_SET(SCU4B0, 10)); +PIN_DECL_2(H26, GPIOB2, SALT3, LHAD2); +FUNC_GROUP_DECL(SALT3, H26); + +#define J25 11 +SIG_EXPR_LIST_DECL_SESG(J25, SALT4, SALT4, SIG_DESC_SET(SCU410, 11)); +SIG_EXPR_LIST_DECL_SESG(J25, LHAD3, LPCHC, SIG_DESC_SET(SCU4B0, 11)); +PIN_DECL_2(J25, GPIOB3, SALT4, LHAD3); +FUNC_GROUP_DECL(SALT4, J25); + +#define J23 12 +SIG_EXPR_LIST_DECL_SESG(J23, MDC2, MDIO2, SIG_DESC_SET(SCU410, 12)); +SIG_EXPR_LIST_DECL_SESG(J23, LHCLK, LPCHC, SIG_DESC_SET(SCU4B0, 12)); +PIN_DECL_2(J23, GPIOB4, MDC2, LHCLK); + +#define G26 13 +SIG_EXPR_LIST_DECL_SESG(G26, MDIO2, MDIO2, SIG_DESC_SET(SCU410, 13)); +SIG_EXPR_LIST_DECL_SESG(G26, LHFRAME, LPCHC, SIG_DESC_SET(SCU4B0, 13)); +PIN_DECL_2(G26, GPIOB5, MDIO2, LHFRAME); + +FUNC_GROUP_DECL(MDIO2, J23, G26); + +#define H25 14 +SIG_EXPR_LIST_DECL_SESG(H25, TXD4, TXD4, SIG_DESC_SET(SCU410, 14)); +SIG_EXPR_LIST_DECL_SESG(H25, LHSIRQ, LHSIRQ, SIG_DESC_SET(SCU4B0, 14)); +PIN_DECL_2(H25, GPIOB6, TXD4, LHSIRQ); +FUNC_GROUP_DECL(TXD4, H25); +FUNC_GROUP_DECL(LHSIRQ, H25); + +#define J24 15 +SIG_EXPR_LIST_DECL_SESG(J24, RXD4, RXD4, SIG_DESC_SET(SCU410, 15)); +SIG_EXPR_LIST_DECL_SESG(J24, LHRST, LPCHC, SIG_DESC_SET(SCU4B0, 15)); +PIN_DECL_2(J24, GPIOB7, RXD4, LHRST); +FUNC_GROUP_DECL(RXD4, J24); + +FUNC_GROUP_DECL(LPCHC, J26, K23, H26, J25, J23, G26, H25, J24); + +#define H24 16 +SIG_EXPR_LIST_DECL_SESG(H24, RGMII3TXCK, RGMII3, SIG_DESC_SET(SCU410, 16), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(H24, RMII3RCLKO, RMII3, SIG_DESC_SET(SCU410, 16), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(H24, GPIOC0, RGMII3TXCK, RMII3RCLKO); + +#define J22 17 +SIG_EXPR_LIST_DECL_SESG(J22, RGMII3TXCTL, RGMII3, SIG_DESC_SET(SCU410, 17), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(J22, RMII3TXEN, RMII3, SIG_DESC_SET(SCU410, 17), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(J22, GPIOC1, RGMII3TXCTL, RMII3TXEN); + +#define H22 18 +SIG_EXPR_LIST_DECL_SESG(H22, RGMII3TXD0, RGMII3, SIG_DESC_SET(SCU410, 18), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(H22, RMII3TXD0, RMII3, SIG_DESC_SET(SCU410, 18), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(H22, GPIOC2, RGMII3TXD0, RMII3TXD0); + +#define H23 19 +SIG_EXPR_LIST_DECL_SESG(H23, RGMII3TXD1, RGMII3, SIG_DESC_SET(SCU410, 19), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(H23, RMII3TXD1, RMII3, SIG_DESC_SET(SCU410, 19), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(H23, GPIOC3, RGMII3TXD1, RMII3TXD1); + +#define G22 20 +SIG_EXPR_LIST_DECL_SESG(G22, RGMII3TXD2, RGMII3, SIG_DESC_SET(SCU410, 20), + SIG_DESC_SET(SCU510, 0)); +PIN_DECL_1(G22, GPIOC4, RGMII3TXD2); + +#define F22 21 +SIG_EXPR_LIST_DECL_SESG(F22, RGMII3TXD3, RGMII3, SIG_DESC_SET(SCU410, 21), + SIG_DESC_SET(SCU510, 0)); +PIN_DECL_1(F22, GPIOC5, RGMII3TXD3); + +#define G23 22 +SIG_EXPR_LIST_DECL_SESG(G23, RGMII3RXCK, RGMII3, SIG_DESC_SET(SCU410, 22), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(G23, RMII3RCLKI, RMII3, SIG_DESC_SET(SCU410, 22), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(G23, GPIOC6, RGMII3RXCK, RMII3RCLKI); + +#define G24 23 +SIG_EXPR_LIST_DECL_SESG(G24, RGMII3RXCTL, RGMII3, SIG_DESC_SET(SCU410, 23), + SIG_DESC_SET(SCU510, 0)); +PIN_DECL_1(G24, GPIOC7, RGMII3RXCTL); + +#define F23 24 +SIG_EXPR_LIST_DECL_SESG(F23, RGMII3RXD0, RGMII3, SIG_DESC_SET(SCU410, 24), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(F23, RMII3RXD0, RMII3, SIG_DESC_SET(SCU410, 24), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(F23, GPIOD0, RGMII3RXD0, RMII3RXD0); + +#define F26 25 +SIG_EXPR_LIST_DECL_SESG(F26, RGMII3RXD1, RGMII3, SIG_DESC_SET(SCU410, 25), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(F26, RMII3RXD1, RMII3, SIG_DESC_SET(SCU410, 25), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(F26, GPIOD1, RGMII3RXD1, RMII3RXD1); + +#define F25 26 +SIG_EXPR_LIST_DECL_SESG(F25, RGMII3RXD2, RGMII3, SIG_DESC_SET(SCU410, 26), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(F25, RMII3CRSDV, RMII3, SIG_DESC_SET(SCU410, 26), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(F25, GPIOD2, RGMII3RXD2, RMII3CRSDV); + +#define E26 27 +SIG_EXPR_LIST_DECL_SESG(E26, RGMII3RXD3, RGMII3, SIG_DESC_SET(SCU410, 27), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(E26, RMII3RXER, RMII3, SIG_DESC_SET(SCU410, 27), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(E26, GPIOD3, RGMII3RXD3, RMII3RXER); + +FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25, + E26); +FUNC_GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26); + +#define F24 28 +SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28)); +SIG_EXPR_LIST_DECL_SESG(F24, RGMII4TXCK, RGMII4, SIG_DESC_SET(SCU4B0, 28), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(F24, RMII4RCLKO, RMII4, SIG_DESC_SET(SCU4B0, 28), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(F24, GPIOD4, NCTS3, RGMII4TXCK, RMII4RCLKO); +FUNC_GROUP_DECL(NCTS3, F24); + +#define E23 29 +SIG_EXPR_LIST_DECL_SESG(E23, NDCD3, NDCD3, SIG_DESC_SET(SCU410, 29)); +SIG_EXPR_LIST_DECL_SESG(E23, RGMII4TXCTL, RGMII4, SIG_DESC_SET(SCU4B0, 29), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(E23, RMII4TXEN, RMII4, SIG_DESC_SET(SCU4B0, 29), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(E23, GPIOD5, NDCD3, RGMII4TXCTL, RMII4TXEN); +FUNC_GROUP_DECL(NDCD3, E23); + +#define E24 30 +SIG_EXPR_LIST_DECL_SESG(E24, NDSR3, NDSR3, SIG_DESC_SET(SCU410, 30)); +SIG_EXPR_LIST_DECL_SESG(E24, RGMII4TXD0, RGMII4, SIG_DESC_SET(SCU4B0, 30), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(E24, RMII4TXD0, RMII4, SIG_DESC_SET(SCU4B0, 30), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(E24, GPIOD6, NDSR3, RGMII4TXD0, RMII4TXD0); +FUNC_GROUP_DECL(NDSR3, E24); + +#define E25 31 +SIG_EXPR_LIST_DECL_SESG(E25, NRI3, NRI3, SIG_DESC_SET(SCU410, 31)); +SIG_EXPR_LIST_DECL_SESG(E25, RGMII4TXD1, RGMII4, SIG_DESC_SET(SCU4B0, 31), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(E25, RMII4TXD1, RMII4, SIG_DESC_SET(SCU4B0, 31), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(E25, GPIOD7, NRI3, RGMII4TXD1, RMII4TXD1); +FUNC_GROUP_DECL(NRI3, E25); + +#define D26 32 +SIG_EXPR_LIST_DECL_SESG(D26, NDTR3, NDTR3, SIG_DESC_SET(SCU414, 0)); +SIG_EXPR_LIST_DECL_SESG(D26, RGMII4TXD2, RGMII4, SIG_DESC_SET(SCU4B4, 0), + SIG_DESC_SET(SCU510, 1)); +PIN_DECL_2(D26, GPIOE0, NDTR3, RGMII4TXD2); +FUNC_GROUP_DECL(NDTR3, D26); + +#define D24 33 +SIG_EXPR_LIST_DECL_SESG(D24, NRTS3, NRTS3, SIG_DESC_SET(SCU414, 1)); +SIG_EXPR_LIST_DECL_SESG(D24, RGMII4TXD3, RGMII4, SIG_DESC_SET(SCU4B4, 1), + SIG_DESC_SET(SCU510, 1)); +PIN_DECL_2(D24, GPIOE1, NRTS3, RGMII4TXD3); +FUNC_GROUP_DECL(NRTS3, D24); + +#define C25 34 +SIG_EXPR_LIST_DECL_SESG(C25, NCTS4, NCTS4, SIG_DESC_SET(SCU414, 2)); +SIG_EXPR_LIST_DECL_SESG(C25, RGMII4RXCK, RGMII4, SIG_DESC_SET(SCU4B4, 2), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(C25, RMII4RCLKI, RMII4, SIG_DESC_SET(SCU4B4, 2), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(C25, GPIOE2, NCTS4, RGMII4RXCK, RMII4RCLKI); +FUNC_GROUP_DECL(NCTS4, C25); + +#define C26 35 +SIG_EXPR_LIST_DECL_SESG(C26, NDCD4, NDCD4, SIG_DESC_SET(SCU414, 3)); +SIG_EXPR_LIST_DECL_SESG(C26, RGMII4RXCTL, RGMII4, SIG_DESC_SET(SCU4B4, 3), + SIG_DESC_SET(SCU510, 1)); +PIN_DECL_2(C26, GPIOE3, NDCD4, RGMII4RXCTL); +FUNC_GROUP_DECL(NDCD4, C26); + +#define C24 36 +SIG_EXPR_LIST_DECL_SESG(C24, NDSR4, NDSR4, SIG_DESC_SET(SCU414, 4)); +SIG_EXPR_LIST_DECL_SESG(C24, RGMII4RXD0, RGMII4, SIG_DESC_SET(SCU4B4, 4), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(C24, RMII4RXD0, RMII4, SIG_DESC_SET(SCU4B4, 4), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(C24, GPIOE4, NDSR4, RGMII4RXD0, RMII4RXD0); +FUNC_GROUP_DECL(NDSR4, C24); + +#define B26 37 +SIG_EXPR_LIST_DECL_SESG(B26, NRI4, NRI4, SIG_DESC_SET(SCU414, 5)); +SIG_EXPR_LIST_DECL_SESG(B26, RGMII4RXD1, RGMII4, SIG_DESC_SET(SCU4B4, 5), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(B26, RMII4RXD1, RMII4, SIG_DESC_SET(SCU4B4, 5), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(B26, GPIOE5, NRI4, RGMII4RXD1, RMII4RXD1); +FUNC_GROUP_DECL(NRI4, B26); + +#define B25 38 +SIG_EXPR_LIST_DECL_SESG(B25, NDTR4, NDTR4, SIG_DESC_SET(SCU414, 6)); +SIG_EXPR_LIST_DECL_SESG(B25, RGMII4RXD2, RGMII4, SIG_DESC_SET(SCU4B4, 6), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(B25, RMII4CRSDV, RMII4, SIG_DESC_SET(SCU4B4, 6), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(B25, GPIOE6, NDTR4, RGMII4RXD2, RMII4CRSDV); +FUNC_GROUP_DECL(NDTR4, B25); + +#define B24 39 +SIG_EXPR_LIST_DECL_SESG(B24, NRTS4, NRTS4, SIG_DESC_SET(SCU414, 7)); +SIG_EXPR_LIST_DECL_SESG(B24, RGMII4RXD3, RGMII4, SIG_DESC_SET(SCU4B4, 7), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(B24, RMII4RXER, RMII4, SIG_DESC_SET(SCU4B4, 7), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(B24, GPIOE7, NRTS4, RGMII4RXD3, RMII4RXER); +FUNC_GROUP_DECL(NRTS4, B24); + +FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25, + B24); +FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24); + +#define D22 40 +SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8)); +SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU414, 8)); +PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8); +GROUP_DECL(PWM8G0, D22); + +#define E22 41 +SIG_EXPR_LIST_DECL_SESG(E22, SD1CMD, SD1, SIG_DESC_SET(SCU414, 9)); +SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9)); +PIN_DECL_2(E22, GPIOF1, SD1CMD, PWM9); +GROUP_DECL(PWM9G0, E22); + +#define D23 42 +SIG_EXPR_LIST_DECL_SESG(D23, SD1DAT0, SD1, SIG_DESC_SET(SCU414, 10)); +SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10)); +PIN_DECL_2(D23, GPIOF2, SD1DAT0, PWM10); +GROUP_DECL(PWM10G0, D23); + +#define C23 43 +SIG_EXPR_LIST_DECL_SESG(C23, SD1DAT1, SD1, SIG_DESC_SET(SCU414, 11)); +SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11)); +PIN_DECL_2(C23, GPIOF3, SD1DAT1, PWM11); +GROUP_DECL(PWM11G0, C23); + +#define C22 44 +SIG_EXPR_LIST_DECL_SESG(C22, SD1DAT2, SD1, SIG_DESC_SET(SCU414, 12)); +SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12)); +PIN_DECL_2(C22, GPIOF4, SD1DAT2, PWM12); +GROUP_DECL(PWM12G0, C22); + +#define A25 45 +SIG_EXPR_LIST_DECL_SESG(A25, SD1DAT3, SD1, SIG_DESC_SET(SCU414, 13)); +SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13)); +PIN_DECL_2(A25, GPIOF5, SD1DAT3, PWM13); +GROUP_DECL(PWM13G0, A25); + +#define A24 46 +SIG_EXPR_LIST_DECL_SESG(A24, SD1CD, SD1, SIG_DESC_SET(SCU414, 14)); +SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14)); +PIN_DECL_2(A24, GPIOF6, SD1CD, PWM14); +GROUP_DECL(PWM14G0, A24); + +#define A23 47 +SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15)); +SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15)); +PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15); +GROUP_DECL(PWM15G0, A23); + +FUNC_GROUP_DECL(SD1, D22, E22, D23, C23, C22, A25, A24, A23); + +#define E21 48 +SIG_EXPR_LIST_DECL_SESG(E21, TXD6, UART6, SIG_DESC_SET(SCU414, 16)); +SIG_EXPR_LIST_DECL_SESG(E21, SD2CLK, SD2, SIG_DESC_SET(SCU4B4, 16), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(E21, SALT9, SALT9G0, SALT9, SIG_DESC_SET(SCU694, 16)); +PIN_DECL_3(E21, GPIOG0, TXD6, SD2CLK, SALT9); +GROUP_DECL(SALT9G0, E21); + +#define B22 49 +SIG_EXPR_LIST_DECL_SESG(B22, RXD6, UART6, SIG_DESC_SET(SCU414, 17)); +SIG_EXPR_LIST_DECL_SESG(B22, SD2CMD, SD2, SIG_DESC_SET(SCU4B4, 17), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(B22, SALT10, SALT10G0, SALT10, + SIG_DESC_SET(SCU694, 17)); +PIN_DECL_3(B22, GPIOG1, RXD6, SD2CMD, SALT10); +GROUP_DECL(SALT10G0, B22); + +FUNC_GROUP_DECL(UART6, E21, B22); + +#define C21 50 +SIG_EXPR_LIST_DECL_SESG(C21, TXD7, UART7, SIG_DESC_SET(SCU414, 18)); +SIG_EXPR_LIST_DECL_SESG(C21, SD2DAT0, SD2, SIG_DESC_SET(SCU4B4, 18), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(C21, SALT11, SALT11G0, SALT11, + SIG_DESC_SET(SCU694, 18)); +PIN_DECL_3(C21, GPIOG2, TXD7, SD2DAT0, SALT11); +GROUP_DECL(SALT11G0, C21); + +#define A22 51 +SIG_EXPR_LIST_DECL_SESG(A22, RXD7, UART7, SIG_DESC_SET(SCU414, 19)); +SIG_EXPR_LIST_DECL_SESG(A22, SD2DAT1, SD2, SIG_DESC_SET(SCU4B4, 19), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(A22, SALT12, SALT12G0, SALT12, + SIG_DESC_SET(SCU694, 19)); +PIN_DECL_3(A22, GPIOG3, RXD7, SD2DAT1, SALT12); +GROUP_DECL(SALT12G0, A22); + +FUNC_GROUP_DECL(UART7, C21, A22); + +#define A21 52 +SIG_EXPR_LIST_DECL_SESG(A21, TXD8, UART8, SIG_DESC_SET(SCU414, 20)); +SIG_EXPR_LIST_DECL_SESG(A21, SD2DAT2, SD2, SIG_DESC_SET(SCU4B4, 20), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(A21, SALT13, SALT13G0, SALT13, + SIG_DESC_SET(SCU694, 20)); +PIN_DECL_3(A21, GPIOG4, TXD8, SD2DAT2, SALT13); +GROUP_DECL(SALT13G0, A21); + +#define E20 53 +SIG_EXPR_LIST_DECL_SESG(E20, RXD8, UART8, SIG_DESC_SET(SCU414, 21)); +SIG_EXPR_LIST_DECL_SESG(E20, SD2DAT3, SD2, SIG_DESC_SET(SCU4B4, 21), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(E20, SALT14, SALT14G0, SALT14, + SIG_DESC_SET(SCU694, 21)); +PIN_DECL_3(E20, GPIOG5, RXD8, SD2DAT3, SALT14); +GROUP_DECL(SALT14G0, E20); + +FUNC_GROUP_DECL(UART8, A21, E20); + +#define D21 54 +SIG_EXPR_LIST_DECL_SESG(D21, TXD9, UART9, SIG_DESC_SET(SCU414, 22)); +SIG_EXPR_LIST_DECL_SESG(D21, SD2CD, SD2, SIG_DESC_SET(SCU4B4, 22), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(D21, SALT15, SALT15G0, SALT15, + SIG_DESC_SET(SCU694, 22)); +PIN_DECL_3(D21, GPIOG6, TXD9, SD2CD, SALT15); +GROUP_DECL(SALT15G0, D21); + +#define B21 55 +SIG_EXPR_LIST_DECL_SESG(B21, RXD9, UART9, SIG_DESC_SET(SCU414, 23)); +SIG_EXPR_LIST_DECL_SESG(B21, SD2WP, SD2, SIG_DESC_SET(SCU4B4, 23), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(B21, SALT16, SALT16G0, SALT16, + SIG_DESC_SET(SCU694, 23)); +PIN_DECL_3(B21, GPIOG7, RXD9, SD2WP, SALT16); +GROUP_DECL(SALT16G0, B21); + +FUNC_GROUP_DECL(UART9, D21, B21); + +FUNC_GROUP_DECL(SD2, E21, B22, C21, A22, A21, E20, D21, B21); + +#define A18 56 +SIG_EXPR_LIST_DECL_SESG(A18, SGPM1CLK, SGPM1, SIG_DESC_SET(SCU414, 24)); +PIN_DECL_1(A18, GPIOH0, SGPM1CLK); + +#define B18 57 +SIG_EXPR_LIST_DECL_SESG(B18, SGPM1LD, SGPM1, SIG_DESC_SET(SCU414, 25)); +PIN_DECL_1(B18, GPIOH1, SGPM1LD); + +#define C18 58 +SIG_EXPR_LIST_DECL_SESG(C18, SGPM1O, SGPM1, SIG_DESC_SET(SCU414, 26)); +PIN_DECL_1(C18, GPIOH2, SGPM1O); + +#define A17 59 +SIG_EXPR_LIST_DECL_SESG(A17, SGPM1I, SGPM1, SIG_DESC_SET(SCU414, 27)); +PIN_DECL_1(A17, GPIOH3, SGPM1I); + +FUNC_GROUP_DECL(SGPM1, A18, B18, C18, A17); + +#define D18 60 +SIG_EXPR_LIST_DECL_SESG(D18, SGPS1CK, SGPS1, SIG_DESC_SET(SCU414, 28)); +SIG_EXPR_LIST_DECL_SESG(D18, SCL15, I2C15, SIG_DESC_SET(SCU4B4, 28)); +PIN_DECL_2(D18, GPIOH4, SGPS1CK, SCL15); + +#define B17 61 +SIG_EXPR_LIST_DECL_SESG(B17, SGPS1LD, SGPS1, SIG_DESC_SET(SCU414, 29)); +SIG_EXPR_LIST_DECL_SESG(B17, SDA15, I2C15, SIG_DESC_SET(SCU4B4, 29)); +PIN_DECL_2(B17, GPIOH5, SGPS1LD, SDA15); + +FUNC_GROUP_DECL(I2C15, D18, B17); + +#define C17 62 +SIG_EXPR_LIST_DECL_SESG(C17, SGPS1O, SGPS1, SIG_DESC_SET(SCU414, 30)); +SIG_EXPR_LIST_DECL_SESG(C17, SCL16, I2C16, SIG_DESC_SET(SCU4B4, 30)); +PIN_DECL_2(C17, GPIOH6, SGPS1O, SCL16); + +#define E18 63 +SIG_EXPR_LIST_DECL_SESG(E18, SGPS1I, SGPS1, SIG_DESC_SET(SCU414, 31)); +SIG_EXPR_LIST_DECL_SESG(E18, SDA16, I2C16, SIG_DESC_SET(SCU4B4, 31)); +PIN_DECL_2(E18, GPIOH7, SGPS1I, SDA16); + +FUNC_GROUP_DECL(I2C16, C17, E18); +FUNC_GROUP_DECL(SGPS1, D18, B17, C17, E18); + +#define D17 64 +SIG_EXPR_LIST_DECL_SESG(D17, MTRSTN, JTAGM, SIG_DESC_SET(SCU418, 0)); +SIG_EXPR_LIST_DECL_SEMG(D17, TXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 0)); +PIN_DECL_2(D17, GPIOI0, MTRSTN, TXD12); + +#define A16 65 +SIG_EXPR_LIST_DECL_SESG(A16, MTDI, JTAGM, SIG_DESC_SET(SCU418, 1)); +SIG_EXPR_LIST_DECL_SEMG(A16, RXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 1)); +PIN_DECL_2(A16, GPIOI1, MTDI, RXD12); + +GROUP_DECL(UART12G0, D17, A16); + +#define E17 66 +SIG_EXPR_LIST_DECL_SESG(E17, MTCK, JTAGM, SIG_DESC_SET(SCU418, 2)); +SIG_EXPR_LIST_DECL_SEMG(E17, TXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 2)); +PIN_DECL_2(E17, GPIOI2, MTCK, TXD13); + +#define D16 67 +SIG_EXPR_LIST_DECL_SESG(D16, MTMS, JTAGM, SIG_DESC_SET(SCU418, 3)); +SIG_EXPR_LIST_DECL_SEMG(D16, RXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 3)); +PIN_DECL_2(D16, GPIOI3, MTMS, RXD13); + +GROUP_DECL(UART13G0, E17, D16); + +#define C16 68 +SIG_EXPR_LIST_DECL_SESG(C16, MTDO, JTAGM, SIG_DESC_SET(SCU418, 4)); +PIN_DECL_1(C16, GPIOI4, MTDO); + +FUNC_GROUP_DECL(JTAGM, D17, A16, E17, D16, C16); + +#define E16 69 +SIG_EXPR_LIST_DECL_SESG(E16, SIOPBO, SIOPBO, SIG_DESC_SET(SCU418, 5)); +PIN_DECL_1(E16, GPIOI5, SIOPBO); +FUNC_GROUP_DECL(SIOPBO, E16); + +#define B16 70 +SIG_EXPR_LIST_DECL_SESG(B16, SIOPBI, SIOPBI, SIG_DESC_SET(SCU418, 6)); +PIN_DECL_1(B16, GPIOI6, SIOPBI); +FUNC_GROUP_DECL(SIOPBI, B16); + +#define A15 71 +SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7)); +SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7)); +PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI); +FUNC_GROUP_DECL(BMCINT, A15); +FUNC_GROUP_DECL(SIOSCI, A15); + +#define B20 72 +SIG_EXPR_LIST_DECL_SEMG(B20, I3C3SCL, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 8)); +SIG_EXPR_LIST_DECL_SESG(B20, SCL1, I2C1, SIG_DESC_SET(SCU4B8, 8)); +PIN_DECL_2(B20, GPIOJ0, I3C3SCL, SCL1); + +#define A20 73 +SIG_EXPR_LIST_DECL_SEMG(A20, I3C3SDA, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 9)); +SIG_EXPR_LIST_DECL_SESG(A20, SDA1, I2C1, SIG_DESC_SET(SCU4B8, 9)); +PIN_DECL_2(A20, GPIOJ1, I3C3SDA, SDA1); + +GROUP_DECL(HVI3C3, B20, A20); +FUNC_GROUP_DECL(I2C1, B20, A20); + +#define E19 74 +SIG_EXPR_LIST_DECL_SEMG(E19, I3C4SCL, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 10)); +SIG_EXPR_LIST_DECL_SESG(E19, SCL2, I2C2, SIG_DESC_SET(SCU4B8, 10)); +PIN_DECL_2(E19, GPIOJ2, I3C4SCL, SCL2); + +#define D20 75 +SIG_EXPR_LIST_DECL_SEMG(D20, I3C4SDA, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 11)); +SIG_EXPR_LIST_DECL_SESG(D20, SDA2, I2C2, SIG_DESC_SET(SCU4B8, 11)); +PIN_DECL_2(D20, GPIOJ3, I3C4SDA, SDA2); + +GROUP_DECL(HVI3C4, E19, D20); +FUNC_GROUP_DECL(I2C2, E19, D20); + +#define C19 76 +SIG_EXPR_LIST_DECL_SESG(C19, I3C5SCL, I3C5, SIG_DESC_SET(SCU418, 12)); +SIG_EXPR_LIST_DECL_SESG(C19, SCL3, I2C3, SIG_DESC_SET(SCU4B8, 12)); +PIN_DECL_2(C19, GPIOJ4, I3C5SCL, SCL3); + +#define A19 77 +SIG_EXPR_LIST_DECL_SESG(A19, I3C5SDA, I3C5, SIG_DESC_SET(SCU418, 13)); +SIG_EXPR_LIST_DECL_SESG(A19, SDA3, I2C3, SIG_DESC_SET(SCU4B8, 13)); +PIN_DECL_2(A19, GPIOJ5, I3C5SDA, SDA3); + +FUNC_GROUP_DECL(I3C5, C19, A19); +FUNC_GROUP_DECL(I2C3, C19, A19); + +#define C20 78 +SIG_EXPR_LIST_DECL_SESG(C20, I3C6SCL, I3C6, SIG_DESC_SET(SCU418, 14)); +SIG_EXPR_LIST_DECL_SESG(C20, SCL4, I2C4, SIG_DESC_SET(SCU4B8, 14)); +PIN_DECL_2(C20, GPIOJ6, I3C6SCL, SCL4); + +#define D19 79 +SIG_EXPR_LIST_DECL_SESG(D19, I3C6SDA, I3C6, SIG_DESC_SET(SCU418, 15)); +SIG_EXPR_LIST_DECL_SESG(D19, SDA4, I2C4, SIG_DESC_SET(SCU4B8, 15)); +PIN_DECL_2(D19, GPIOJ7, I3C6SDA, SDA4); + +FUNC_GROUP_DECL(I3C6, C20, D19); +FUNC_GROUP_DECL(I2C4, C20, D19); + +#define A11 80 +SIG_EXPR_LIST_DECL_SESG(A11, SCL5, I2C5, SIG_DESC_SET(SCU418, 16)); +PIN_DECL_1(A11, GPIOK0, SCL5); + +#define C11 81 +SIG_EXPR_LIST_DECL_SESG(C11, SDA5, I2C5, SIG_DESC_SET(SCU418, 17)); +PIN_DECL_1(C11, GPIOK1, SDA5); + +FUNC_GROUP_DECL(I2C5, A11, C11); + +#define D12 82 +SIG_EXPR_LIST_DECL_SESG(D12, SCL6, I2C6, SIG_DESC_SET(SCU418, 18)); +PIN_DECL_1(D12, GPIOK2, SCL6); + +#define E13 83 +SIG_EXPR_LIST_DECL_SESG(E13, SDA6, I2C6, SIG_DESC_SET(SCU418, 19)); +PIN_DECL_1(E13, GPIOK3, SDA6); + +FUNC_GROUP_DECL(I2C6, D12, E13); + +#define D11 84 +SIG_EXPR_LIST_DECL_SESG(D11, SCL7, I2C7, SIG_DESC_SET(SCU418, 20)); +PIN_DECL_1(D11, GPIOK4, SCL7); + +#define E11 85 +SIG_EXPR_LIST_DECL_SESG(E11, SDA7, I2C7, SIG_DESC_SET(SCU418, 21)); +PIN_DECL_1(E11, GPIOK5, SDA7); + +FUNC_GROUP_DECL(I2C7, D11, E11); + +#define F13 86 +SIG_EXPR_LIST_DECL_SESG(F13, SCL8, I2C8, SIG_DESC_SET(SCU418, 22)); +PIN_DECL_1(F13, GPIOK6, SCL8); + +#define E12 87 +SIG_EXPR_LIST_DECL_SESG(E12, SDA8, I2C8, SIG_DESC_SET(SCU418, 23)); +PIN_DECL_1(E12, GPIOK7, SDA8); + +FUNC_GROUP_DECL(I2C8, F13, E12); + +#define D15 88 +SIG_EXPR_LIST_DECL_SESG(D15, SCL9, I2C9, SIG_DESC_SET(SCU418, 24)); +PIN_DECL_1(D15, GPIOL0, SCL9); + +#define A14 89 +SIG_EXPR_LIST_DECL_SESG(A14, SDA9, I2C9, SIG_DESC_SET(SCU418, 25)); +PIN_DECL_1(A14, GPIOL1, SDA9); + +FUNC_GROUP_DECL(I2C9, D15, A14); + +#define E15 90 +SIG_EXPR_LIST_DECL_SESG(E15, SCL10, I2C10, SIG_DESC_SET(SCU418, 26)); +PIN_DECL_1(E15, GPIOL2, SCL10); + +#define A13 91 +SIG_EXPR_LIST_DECL_SESG(A13, SDA10, I2C10, SIG_DESC_SET(SCU418, 27)); +PIN_DECL_1(A13, GPIOL3, SDA10); + +FUNC_GROUP_DECL(I2C10, E15, A13); + +#define C15 92 +SSSF_PIN_DECL(C15, GPIOL4, TXD3, SIG_DESC_SET(SCU418, 28)); + +#define F15 93 +SSSF_PIN_DECL(F15, GPIOL5, RXD3, SIG_DESC_SET(SCU418, 29)); + +#define B14 94 +SSSF_PIN_DECL(B14, GPIOL6, VGAHS, SIG_DESC_SET(SCU418, 30)); + +#define C14 95 +SSSF_PIN_DECL(C14, GPIOL7, VGAVS, SIG_DESC_SET(SCU418, 31)); + +#define D14 96 +SSSF_PIN_DECL(D14, GPIOM0, NCTS1, SIG_DESC_SET(SCU41C, 0)); + +#define B13 97 +SSSF_PIN_DECL(B13, GPIOM1, NDCD1, SIG_DESC_SET(SCU41C, 1)); + +#define A12 98 +SSSF_PIN_DECL(A12, GPIOM2, NDSR1, SIG_DESC_SET(SCU41C, 2)); + +#define E14 99 +SSSF_PIN_DECL(E14, GPIOM3, NRI1, SIG_DESC_SET(SCU41C, 3)); + +#define B12 100 +SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4)); + +#define C12 101 +SSSF_PIN_DECL(C12, GPIOM5, NRTS1, SIG_DESC_SET(SCU41C, 5)); + +#define C13 102 +SSSF_PIN_DECL(C13, GPIOM6, TXD1, SIG_DESC_SET(SCU41C, 6)); + +#define D13 103 +SSSF_PIN_DECL(D13, GPIOM7, RXD1, SIG_DESC_SET(SCU41C, 7)); + +#define P25 104 +SSSF_PIN_DECL(P25, GPION0, NCTS2, SIG_DESC_SET(SCU41C, 8)); + +#define N23 105 +SSSF_PIN_DECL(N23, GPION1, NDCD2, SIG_DESC_SET(SCU41C, 9)); + +#define N25 106 +SSSF_PIN_DECL(N25, GPION2, NDSR2, SIG_DESC_SET(SCU41C, 10)); + +#define N24 107 +SSSF_PIN_DECL(N24, GPION3, NRI2, SIG_DESC_SET(SCU41C, 11)); + +#define P26 108 +SSSF_PIN_DECL(P26, GPION4, NDTR2, SIG_DESC_SET(SCU41C, 12)); + +#define M23 109 +SSSF_PIN_DECL(M23, GPION5, NRTS2, SIG_DESC_SET(SCU41C, 13)); + +#define N26 110 +SSSF_PIN_DECL(N26, GPION6, TXD2, SIG_DESC_SET(SCU41C, 14)); + +#define M26 111 +SSSF_PIN_DECL(M26, GPION7, RXD2, SIG_DESC_SET(SCU41C, 15)); + +#define AD26 112 +SSSF_PIN_DECL(AD26, GPIOO0, PWM0, SIG_DESC_SET(SCU41C, 16)); + +#define AD22 113 +SSSF_PIN_DECL(AD22, GPIOO1, PWM1, SIG_DESC_SET(SCU41C, 17)); + +#define AD23 114 +SSSF_PIN_DECL(AD23, GPIOO2, PWM2, SIG_DESC_SET(SCU41C, 18)); + +#define AD24 115 +SSSF_PIN_DECL(AD24, GPIOO3, PWM3, SIG_DESC_SET(SCU41C, 19)); + +#define AD25 116 +SSSF_PIN_DECL(AD25, GPIOO4, PWM4, SIG_DESC_SET(SCU41C, 20)); + +#define AC22 117 +SSSF_PIN_DECL(AC22, GPIOO5, PWM5, SIG_DESC_SET(SCU41C, 21)); + +#define AC24 118 +SSSF_PIN_DECL(AC24, GPIOO6, PWM6, SIG_DESC_SET(SCU41C, 22)); + +#define AC23 119 +SSSF_PIN_DECL(AC23, GPIOO7, PWM7, SIG_DESC_SET(SCU41C, 23)); + +#define AB22 120 +SIG_EXPR_LIST_DECL_SEMG(AB22, PWM8, PWM8G1, PWM8, SIG_DESC_SET(SCU41C, 24)); +SIG_EXPR_LIST_DECL_SESG(AB22, THRUIN0, THRU0, SIG_DESC_SET(SCU4BC, 24)); +PIN_DECL_2(AB22, GPIOP0, PWM8, THRUIN0); +GROUP_DECL(PWM8G1, AB22); +FUNC_DECL_2(PWM8, PWM8G0, PWM8G1); + +#define W24 121 +SIG_EXPR_LIST_DECL_SEMG(W24, PWM9, PWM9G1, PWM9, SIG_DESC_SET(SCU41C, 25)); +SIG_EXPR_LIST_DECL_SESG(W24, THRUOUT0, THRU0, SIG_DESC_SET(SCU4BC, 25)); +PIN_DECL_2(W24, GPIOP1, PWM9, THRUOUT0); + +FUNC_GROUP_DECL(THRU0, AB22, W24); + +GROUP_DECL(PWM9G1, W24); +FUNC_DECL_2(PWM9, PWM9G0, PWM9G1); + +#define AA23 122 +SIG_EXPR_LIST_DECL_SEMG(AA23, PWM10, PWM10G1, PWM10, SIG_DESC_SET(SCU41C, 26)); +SIG_EXPR_LIST_DECL_SESG(AA23, THRUIN1, THRU1, SIG_DESC_SET(SCU4BC, 26)); +PIN_DECL_2(AA23, GPIOP2, PWM10, THRUIN1); +GROUP_DECL(PWM10G1, AA23); +FUNC_DECL_2(PWM10, PWM10G0, PWM10G1); + +#define AA24 123 +SIG_EXPR_LIST_DECL_SEMG(AA24, PWM11, PWM11G1, PWM11, SIG_DESC_SET(SCU41C, 27)); +SIG_EXPR_LIST_DECL_SESG(AA24, THRUOUT1, THRU1, SIG_DESC_SET(SCU4BC, 27)); +PIN_DECL_2(AA24, GPIOP3, PWM11, THRUOUT1); +GROUP_DECL(PWM11G1, AA24); +FUNC_DECL_2(PWM11, PWM11G0, PWM11G1); + +FUNC_GROUP_DECL(THRU1, AA23, AA24); + +#define W23 124 +SIG_EXPR_LIST_DECL_SEMG(W23, PWM12, PWM12G1, PWM12, SIG_DESC_SET(SCU41C, 28)); +SIG_EXPR_LIST_DECL_SESG(W23, THRUIN2, THRU2, SIG_DESC_SET(SCU4BC, 28)); +PIN_DECL_2(W23, GPIOP4, PWM12, THRUIN2); +GROUP_DECL(PWM12G1, W23); +FUNC_DECL_2(PWM12, PWM12G0, PWM12G1); + +#define AB23 125 +SIG_EXPR_LIST_DECL_SEMG(AB23, PWM13, PWM13G1, PWM13, SIG_DESC_SET(SCU41C, 29)); +SIG_EXPR_LIST_DECL_SESG(AB23, THRUOUT2, THRU2, SIG_DESC_SET(SCU4BC, 29)); +PIN_DECL_2(AB23, GPIOP5, PWM13, THRUOUT2); +GROUP_DECL(PWM13G1, AB23); +FUNC_DECL_2(PWM13, PWM13G0, PWM13G1); + +FUNC_GROUP_DECL(THRU2, W23, AB23); + +#define AB24 126 +SIG_EXPR_LIST_DECL_SEMG(AB24, PWM14, PWM14G1, PWM14, SIG_DESC_SET(SCU41C, 30)); +SIG_EXPR_LIST_DECL_SESG(AB24, THRUIN3, THRU3, SIG_DESC_SET(SCU4BC, 30)); +PIN_DECL_2(AB24, GPIOP6, PWM14, THRUIN3); +GROUP_DECL(PWM14G1, AB24); +FUNC_DECL_2(PWM14, PWM14G0, PWM14G1); + +#define Y23 127 +SIG_EXPR_LIST_DECL_SEMG(Y23, PWM15, PWM15G1, PWM15, SIG_DESC_SET(SCU41C, 31)); +SIG_EXPR_LIST_DECL_SESG(Y23, THRUOUT3, THRU3, SIG_DESC_SET(SCU4BC, 31)); +PIN_DECL_2(Y23, GPIOP7, PWM15, THRUOUT3); +GROUP_DECL(PWM15G1, Y23); +FUNC_DECL_2(PWM15, PWM15G0, PWM15G1); + +FUNC_GROUP_DECL(THRU3, AB24, Y23); + +#define AA25 128 +SSSF_PIN_DECL(AA25, GPIOQ0, TACH0, SIG_DESC_SET(SCU430, 0)); + +#define AB25 129 +SSSF_PIN_DECL(AB25, GPIOQ1, TACH1, SIG_DESC_SET(SCU430, 1)); + +#define Y24 130 +SSSF_PIN_DECL(Y24, GPIOQ2, TACH2, SIG_DESC_SET(SCU430, 2)); + +#define AB26 131 +SSSF_PIN_DECL(AB26, GPIOQ3, TACH3, SIG_DESC_SET(SCU430, 3)); + +#define Y26 132 +SSSF_PIN_DECL(Y26, GPIOQ4, TACH4, SIG_DESC_SET(SCU430, 4)); + +#define AC26 133 +SSSF_PIN_DECL(AC26, GPIOQ5, TACH5, SIG_DESC_SET(SCU430, 5)); + +#define Y25 134 +SSSF_PIN_DECL(Y25, GPIOQ6, TACH6, SIG_DESC_SET(SCU430, 6)); + +#define AA26 135 +SSSF_PIN_DECL(AA26, GPIOQ7, TACH7, SIG_DESC_SET(SCU430, 7)); + +#define V25 136 +SSSF_PIN_DECL(V25, GPIOR0, TACH8, SIG_DESC_SET(SCU430, 8)); + +#define U24 137 +SSSF_PIN_DECL(U24, GPIOR1, TACH9, SIG_DESC_SET(SCU430, 9)); + +#define V24 138 +SSSF_PIN_DECL(V24, GPIOR2, TACH10, SIG_DESC_SET(SCU430, 10)); + +#define V26 139 +SSSF_PIN_DECL(V26, GPIOR3, TACH11, SIG_DESC_SET(SCU430, 11)); + +#define U25 140 +SSSF_PIN_DECL(U25, GPIOR4, TACH12, SIG_DESC_SET(SCU430, 12)); + +#define T23 141 +SSSF_PIN_DECL(T23, GPIOR5, TACH13, SIG_DESC_SET(SCU430, 13)); + +#define W26 142 +SSSF_PIN_DECL(W26, GPIOR6, TACH14, SIG_DESC_SET(SCU430, 14)); + +#define U26 143 +SSSF_PIN_DECL(U26, GPIOR7, TACH15, SIG_DESC_SET(SCU430, 15)); + +#define R23 144 +SIG_EXPR_LIST_DECL_SESG(R23, MDC1, MDIO1, SIG_DESC_SET(SCU430, 16)); +PIN_DECL_1(R23, GPIOS0, MDC1); + +#define T25 145 +SIG_EXPR_LIST_DECL_SESG(T25, MDIO1, MDIO1, SIG_DESC_SET(SCU430, 17)); +PIN_DECL_1(T25, GPIOS1, MDIO1); + +FUNC_GROUP_DECL(MDIO1, R23, T25); + +#define T26 146 +SSSF_PIN_DECL(T26, GPIOS2, PEWAKE, SIG_DESC_SET(SCU430, 18)); + +#define R24 147 +SSSF_PIN_DECL(R24, GPIOS3, OSCCLK, SIG_DESC_SET(SCU430, 19)); + +#define R26 148 +SIG_EXPR_LIST_DECL_SESG(R26, TXD10, UART10, SIG_DESC_SET(SCU430, 20)); +PIN_DECL_1(R26, GPIOS4, TXD10); + +#define P24 149 +SIG_EXPR_LIST_DECL_SESG(P24, RXD10, UART10, SIG_DESC_SET(SCU430, 21)); +PIN_DECL_1(P24, GPIOS5, RXD10); + +FUNC_GROUP_DECL(UART10, R26, P24); + +#define P23 150 +SIG_EXPR_LIST_DECL_SESG(P23, TXD11, UART11, SIG_DESC_SET(SCU430, 22)); +PIN_DECL_1(P23, GPIOS6, TXD11); + +#define T24 151 +SIG_EXPR_LIST_DECL_SESG(T24, RXD11, UART11, SIG_DESC_SET(SCU430, 23)); +PIN_DECL_1(T24, GPIOS7, RXD11); + +FUNC_GROUP_DECL(UART11, P23, T24); + +#define AD20 152 +SIG_EXPR_LIST_DECL_SESG(AD20, GPIT0, GPIT0, SIG_DESC_SET(SCU430, 24)); +SIG_EXPR_LIST_DECL_SESG(AD20, ADC0, ADC0); +PIN_DECL_(AD20, SIG_EXPR_LIST_PTR(AD20, GPIT0), SIG_EXPR_LIST_PTR(AD20, ADC0)); +FUNC_GROUP_DECL(GPIT0, AD20); +FUNC_GROUP_DECL(ADC0, AD20); + +#define AC18 153 +SIG_EXPR_LIST_DECL_SESG(AC18, GPIT1, GPIT1, SIG_DESC_SET(SCU430, 25)); +SIG_EXPR_LIST_DECL_SESG(AC18, ADC1, ADC1); +PIN_DECL_(AC18, SIG_EXPR_LIST_PTR(AC18, GPIT1), SIG_EXPR_LIST_PTR(AC18, ADC1)); +FUNC_GROUP_DECL(GPIT1, AC18); +FUNC_GROUP_DECL(ADC1, AC18); + +#define AE19 154 +SIG_EXPR_LIST_DECL_SESG(AE19, GPIT2, GPIT2, SIG_DESC_SET(SCU430, 26)); +SIG_EXPR_LIST_DECL_SESG(AE19, ADC2, ADC2); +PIN_DECL_(AE19, SIG_EXPR_LIST_PTR(AE19, GPIT2), SIG_EXPR_LIST_PTR(AE19, ADC2)); +FUNC_GROUP_DECL(GPIT2, AE19); +FUNC_GROUP_DECL(ADC2, AE19); + +#define AD19 155 +SIG_EXPR_LIST_DECL_SESG(AD19, GPIT3, GPIT3, SIG_DESC_SET(SCU430, 27)); +SIG_EXPR_LIST_DECL_SESG(AD19, ADC3, ADC3); +PIN_DECL_(AD19, SIG_EXPR_LIST_PTR(AD19, GPIT3), SIG_EXPR_LIST_PTR(AD19, ADC3)); +FUNC_GROUP_DECL(GPIT3, AD19); +FUNC_GROUP_DECL(ADC3, AD19); + +#define AC19 156 +SIG_EXPR_LIST_DECL_SESG(AC19, GPIT4, GPIT4, SIG_DESC_SET(SCU430, 28)); +SIG_EXPR_LIST_DECL_SESG(AC19, ADC4, ADC4); +PIN_DECL_(AC19, SIG_EXPR_LIST_PTR(AC19, GPIT4), SIG_EXPR_LIST_PTR(AC19, ADC4)); +FUNC_GROUP_DECL(GPIT4, AC19); +FUNC_GROUP_DECL(ADC4, AC19); + +#define AB19 157 +SIG_EXPR_LIST_DECL_SESG(AB19, GPIT5, GPIT5, SIG_DESC_SET(SCU430, 29)); +SIG_EXPR_LIST_DECL_SESG(AB19, ADC5, ADC5); +PIN_DECL_(AB19, SIG_EXPR_LIST_PTR(AB19, GPIT5), SIG_EXPR_LIST_PTR(AB19, ADC5)); +FUNC_GROUP_DECL(GPIT5, AB19); +FUNC_GROUP_DECL(ADC5, AB19); + +#define AB18 158 +SIG_EXPR_LIST_DECL_SESG(AB18, GPIT6, GPIT6, SIG_DESC_SET(SCU430, 30)); +SIG_EXPR_LIST_DECL_SESG(AB18, ADC6, ADC6); +PIN_DECL_(AB18, SIG_EXPR_LIST_PTR(AB18, GPIT6), SIG_EXPR_LIST_PTR(AB18, ADC6)); +FUNC_GROUP_DECL(GPIT6, AB18); +FUNC_GROUP_DECL(ADC6, AB18); + +#define AE18 159 +SIG_EXPR_LIST_DECL_SESG(AE18, GPIT7, GPIT7, SIG_DESC_SET(SCU430, 31)); +SIG_EXPR_LIST_DECL_SESG(AE18, ADC7, ADC7); +PIN_DECL_(AE18, SIG_EXPR_LIST_PTR(AE18, GPIT7), SIG_EXPR_LIST_PTR(AE18, ADC7)); +FUNC_GROUP_DECL(GPIT7, AE18); +FUNC_GROUP_DECL(ADC7, AE18); + +#define AB16 160 +SIG_EXPR_LIST_DECL_SEMG(AB16, SALT9, SALT9G1, SALT9, SIG_DESC_SET(SCU434, 0), + SIG_DESC_CLEAR(SCU694, 16)); +SIG_EXPR_LIST_DECL_SESG(AB16, GPIU0, GPIU0, SIG_DESC_SET(SCU434, 0), + SIG_DESC_SET(SCU694, 16)); +SIG_EXPR_LIST_DECL_SESG(AB16, ADC8, ADC8); +PIN_DECL_(AB16, SIG_EXPR_LIST_PTR(AB16, SALT9), SIG_EXPR_LIST_PTR(AB16, GPIU0), + SIG_EXPR_LIST_PTR(AB16, ADC8)); +GROUP_DECL(SALT9G1, AB16); +FUNC_DECL_2(SALT9, SALT9G0, SALT9G1); +FUNC_GROUP_DECL(GPIU0, AB16); +FUNC_GROUP_DECL(ADC8, AB16); + +#define AA17 161 +SIG_EXPR_LIST_DECL_SEMG(AA17, SALT10, SALT10G1, SALT10, SIG_DESC_SET(SCU434, 1), + SIG_DESC_CLEAR(SCU694, 17)); +SIG_EXPR_LIST_DECL_SESG(AA17, GPIU1, GPIU1, SIG_DESC_SET(SCU434, 1), + SIG_DESC_SET(SCU694, 17)); +SIG_EXPR_LIST_DECL_SESG(AA17, ADC9, ADC9); +PIN_DECL_(AA17, SIG_EXPR_LIST_PTR(AA17, SALT10), SIG_EXPR_LIST_PTR(AA17, GPIU1), + SIG_EXPR_LIST_PTR(AA17, ADC9)); +GROUP_DECL(SALT10G1, AA17); +FUNC_DECL_2(SALT10, SALT10G0, SALT10G1); +FUNC_GROUP_DECL(GPIU1, AA17); +FUNC_GROUP_DECL(ADC9, AA17); + +#define AB17 162 +SIG_EXPR_LIST_DECL_SEMG(AB17, SALT11, SALT11G1, SALT11, SIG_DESC_SET(SCU434, 2), + SIG_DESC_CLEAR(SCU694, 18)); +SIG_EXPR_LIST_DECL_SESG(AB17, GPIU2, GPIU2, SIG_DESC_SET(SCU434, 2), + SIG_DESC_SET(SCU694, 18)); +SIG_EXPR_LIST_DECL_SESG(AB17, ADC10, ADC10); +PIN_DECL_(AB17, SIG_EXPR_LIST_PTR(AB17, SALT11), SIG_EXPR_LIST_PTR(AB17, GPIU2), + SIG_EXPR_LIST_PTR(AB17, ADC10)); +GROUP_DECL(SALT11G1, AB17); +FUNC_DECL_2(SALT11, SALT11G0, SALT11G1); +FUNC_GROUP_DECL(GPIU2, AB17); +FUNC_GROUP_DECL(ADC10, AB17); + +#define AE16 163 +SIG_EXPR_LIST_DECL_SEMG(AE16, SALT12, SALT12G1, SALT12, SIG_DESC_SET(SCU434, 3), + SIG_DESC_CLEAR(SCU694, 19)); +SIG_EXPR_LIST_DECL_SESG(AE16, GPIU3, GPIU3, SIG_DESC_SET(SCU434, 3), + SIG_DESC_SET(SCU694, 19)); +SIG_EXPR_LIST_DECL_SESG(AE16, ADC11, ADC11); +PIN_DECL_(AE16, SIG_EXPR_LIST_PTR(AE16, SALT12), SIG_EXPR_LIST_PTR(AE16, GPIU3), + SIG_EXPR_LIST_PTR(AE16, ADC11)); +GROUP_DECL(SALT12G1, AE16); +FUNC_DECL_2(SALT12, SALT12G0, SALT12G1); +FUNC_GROUP_DECL(GPIU3, AE16); +FUNC_GROUP_DECL(ADC11, AE16); + +#define AC16 164 +SIG_EXPR_LIST_DECL_SEMG(AC16, SALT13, SALT13G1, SALT13, SIG_DESC_SET(SCU434, 4), + SIG_DESC_CLEAR(SCU694, 20)); +SIG_EXPR_LIST_DECL_SESG(AC16, GPIU4, GPIU4, SIG_DESC_SET(SCU434, 4), + SIG_DESC_SET(SCU694, 20)); +SIG_EXPR_LIST_DECL_SESG(AC16, ADC12, ADC12); +PIN_DECL_(AC16, SIG_EXPR_LIST_PTR(AC16, SALT13), SIG_EXPR_LIST_PTR(AC16, GPIU4), + SIG_EXPR_LIST_PTR(AC16, ADC12)); +GROUP_DECL(SALT13G1, AC16); +FUNC_DECL_2(SALT13, SALT13G0, SALT13G1); +FUNC_GROUP_DECL(GPIU4, AC16); +FUNC_GROUP_DECL(ADC12, AC16); + +#define AA16 165 +SIG_EXPR_LIST_DECL_SEMG(AA16, SALT14, SALT14G1, SALT14, SIG_DESC_SET(SCU434, 5), + SIG_DESC_CLEAR(SCU694, 21)); +SIG_EXPR_LIST_DECL_SESG(AA16, GPIU5, GPIU5, SIG_DESC_SET(SCU434, 5), + SIG_DESC_SET(SCU694, 21)); +SIG_EXPR_LIST_DECL_SESG(AA16, ADC13, ADC13); +PIN_DECL_(AA16, SIG_EXPR_LIST_PTR(AA16, SALT14), SIG_EXPR_LIST_PTR(AA16, GPIU5), + SIG_EXPR_LIST_PTR(AA16, ADC13)); +GROUP_DECL(SALT14G1, AA16); +FUNC_DECL_2(SALT14, SALT14G0, SALT14G1); +FUNC_GROUP_DECL(GPIU5, AA16); +FUNC_GROUP_DECL(ADC13, AA16); + +#define AD16 166 +SIG_EXPR_LIST_DECL_SEMG(AD16, SALT15, SALT15G1, SALT15, SIG_DESC_SET(SCU434, 6), + SIG_DESC_CLEAR(SCU694, 22)); +SIG_EXPR_LIST_DECL_SESG(AD16, GPIU6, GPIU6, SIG_DESC_SET(SCU434, 6), + SIG_DESC_SET(SCU694, 22)); +SIG_EXPR_LIST_DECL_SESG(AD16, ADC14, ADC14); +PIN_DECL_(AD16, SIG_EXPR_LIST_PTR(AD16, SALT15), SIG_EXPR_LIST_PTR(AD16, GPIU6), + SIG_EXPR_LIST_PTR(AD16, ADC14)); +GROUP_DECL(SALT15G1, AD16); +FUNC_DECL_2(SALT15, SALT15G0, SALT15G1); +FUNC_GROUP_DECL(GPIU6, AD16); +FUNC_GROUP_DECL(ADC14, AD16); + +#define AC17 167 +SIG_EXPR_LIST_DECL_SEMG(AC17, SALT16, SALT16G1, SALT16, SIG_DESC_SET(SCU434, 7), + SIG_DESC_CLEAR(SCU694, 23)); +SIG_EXPR_LIST_DECL_SESG(AC17, GPIU7, GPIU7, SIG_DESC_SET(SCU434, 7), + SIG_DESC_SET(SCU694, 23)); +SIG_EXPR_LIST_DECL_SESG(AC17, ADC15, ADC15); +PIN_DECL_(AC17, SIG_EXPR_LIST_PTR(AC17, SALT16), SIG_EXPR_LIST_PTR(AC17, GPIU7), + SIG_EXPR_LIST_PTR(AC17, ADC15)); +GROUP_DECL(SALT16G1, AC17); +FUNC_DECL_2(SALT16, SALT16G0, SALT16G1); +FUNC_GROUP_DECL(GPIU7, AC17); +FUNC_GROUP_DECL(ADC15, AC17); + +#define AB15 168 +SSSF_PIN_DECL(AB15, GPIOV0, SIOS3, SIG_DESC_SET(SCU434, 8)); + +#define AF14 169 +SSSF_PIN_DECL(AF14, GPIOV1, SIOS5, SIG_DESC_SET(SCU434, 9)); + +#define AD14 170 +SSSF_PIN_DECL(AD14, GPIOV2, SIOPWREQ, SIG_DESC_SET(SCU434, 10)); + +#define AC15 171 +SSSF_PIN_DECL(AC15, GPIOV3, SIOONCTRL, SIG_DESC_SET(SCU434, 11)); + +#define AE15 172 +SSSF_PIN_DECL(AE15, GPIOV4, SIOPWRGD, SIG_DESC_SET(SCU434, 12)); + +#define AE14 173 +SIG_EXPR_LIST_DECL_SESG(AE14, LPCPD, LPCPD, SIG_DESC_SET(SCU434, 13)); +SIG_EXPR_LIST_DECL_SESG(AE14, LHPD, LHPD, SIG_DESC_SET(SCU4D4, 13)); +PIN_DECL_2(AE14, GPIOV5, LPCPD, LHPD); +FUNC_GROUP_DECL(LPCPD, AE14); +FUNC_GROUP_DECL(LHPD, AE14); + +#define AD15 174 +SSSF_PIN_DECL(AD15, GPIOV6, LPCPME, SIG_DESC_SET(SCU434, 14)); + +#define AF15 175 +SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15)); + +#define AB7 176 +SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 16)); +SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16)); +PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0); + +#define AB8 177 +SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 17)); +SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17)); +PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1); + +#define AC8 178 +SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 18)); +SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18)); +PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2); + +#define AC7 179 +SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 19)); +SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19)); +PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3); + +#define AE7 180 +SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 20)); +SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20)); +PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK); + +#define AF7 181 +SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 21)); +SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21)); +PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS); + +#define AD7 182 +SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 22)); +SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22)); +PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT); +FUNC_GROUP_DECL(LSIRQ, AD7); +FUNC_GROUP_DECL(ESPIALT, AD7); + +#define AD8 183 +SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU510, 6), + SIG_DESC_SET(SCU434, 23)); +SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23)); +PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST); + +FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8); +FUNC_GROUP_DECL(ESPI, AB7, AB8, AC8, AC7, AE7, AF7, AD8); + +#define AE8 184 +SIG_EXPR_LIST_DECL_SEMG(AE8, SPI2CS0, SPI2, SPI2, SIG_DESC_SET(SCU434, 24)); +PIN_DECL_1(AE8, GPIOX0, SPI2CS0); + +#define AA9 185 +SSSF_PIN_DECL(AA9, GPIOX1, SPI2CS1, SIG_DESC_SET(SCU434, 25)); + +#define AC9 186 +SSSF_PIN_DECL(AC9, GPIOX2, SPI2CS2, SIG_DESC_SET(SCU434, 26)); + +#define AF8 187 +SIG_EXPR_LIST_DECL_SEMG(AF8, SPI2CK, SPI2, SPI2, SIG_DESC_SET(SCU434, 27)); +PIN_DECL_1(AF8, GPIOX3, SPI2CK); + +#define AB9 188 +SIG_EXPR_LIST_DECL_SEMG(AB9, SPI2MOSI, SPI2, SPI2, SIG_DESC_SET(SCU434, 28)); +PIN_DECL_1(AB9, GPIOX4, SPI2MOSI); + +#define AD9 189 +SIG_EXPR_LIST_DECL_SEMG(AD9, SPI2MISO, SPI2, SPI2, SIG_DESC_SET(SCU434, 29)); +PIN_DECL_1(AD9, GPIOX5, SPI2MISO); + +GROUP_DECL(SPI2, AE8, AF8, AB9, AD9); + +#define AF9 190 +SIG_EXPR_LIST_DECL_SEMG(AF9, SPI2DQ2, QSPI2, SPI2, SIG_DESC_SET(SCU434, 30)); +SIG_EXPR_LIST_DECL_SEMG(AF9, TXD12, UART12G1, UART12, SIG_DESC_SET(SCU4D4, 30)); +PIN_DECL_2(AF9, GPIOX6, SPI2DQ2, TXD12); + +#define AB10 191 +SIG_EXPR_LIST_DECL_SEMG(AB10, SPI2DQ3, QSPI2, SPI2, SIG_DESC_SET(SCU434, 31)); +SIG_EXPR_LIST_DECL_SEMG(AB10, RXD12, UART12G1, UART12, + SIG_DESC_SET(SCU4D4, 31)); +PIN_DECL_2(AB10, GPIOX7, SPI2DQ3, RXD12); + +GROUP_DECL(QSPI2, AE8, AF8, AB9, AD9, AF9, AB10); +FUNC_DECL_2(SPI2, SPI2, QSPI2); + +GROUP_DECL(UART12G1, AF9, AB10); +FUNC_DECL_2(UART12, UART12G0, UART12G1); + +#define AF11 192 +SIG_EXPR_LIST_DECL_SESG(AF11, SALT5, SALT5, SIG_DESC_SET(SCU438, 0)); +SIG_EXPR_LIST_DECL_SESG(AF11, WDTRST1, WDTRST1, SIG_DESC_SET(SCU4D8, 0)); +PIN_DECL_2(AF11, GPIOY0, SALT5, WDTRST1); +FUNC_GROUP_DECL(SALT5, AF11); +FUNC_GROUP_DECL(WDTRST1, AF11); + +#define AD12 193 +SIG_EXPR_LIST_DECL_SESG(AD12, SALT6, SALT6, SIG_DESC_SET(SCU438, 1)); +SIG_EXPR_LIST_DECL_SESG(AD12, WDTRST2, WDTRST2, SIG_DESC_SET(SCU4D8, 1)); +PIN_DECL_2(AD12, GPIOY1, SALT6, WDTRST2); +FUNC_GROUP_DECL(SALT6, AD12); +FUNC_GROUP_DECL(WDTRST2, AD12); + +#define AE11 194 +SIG_EXPR_LIST_DECL_SESG(AE11, SALT7, SALT7, SIG_DESC_SET(SCU438, 2)); +SIG_EXPR_LIST_DECL_SESG(AE11, WDTRST3, WDTRST3, SIG_DESC_SET(SCU4D8, 2)); +PIN_DECL_2(AE11, GPIOY2, SALT7, WDTRST3); +FUNC_GROUP_DECL(SALT7, AE11); +FUNC_GROUP_DECL(WDTRST3, AE11); + +#define AA12 195 +SIG_EXPR_LIST_DECL_SESG(AA12, SALT8, SALT8, SIG_DESC_SET(SCU438, 3)); +SIG_EXPR_LIST_DECL_SESG(AA12, WDTRST4, WDTRST4, SIG_DESC_SET(SCU4D8, 3)); +PIN_DECL_2(AA12, GPIOY3, SALT8, WDTRST4); +FUNC_GROUP_DECL(SALT8, AA12); +FUNC_GROUP_DECL(WDTRST4, AA12); + +#define AE12 196 +SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, + SIG_DESC_SET(SCU438, 4)); +SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), + SIG_EXPR_LIST_PTR(AE12, GPIOY4)); + +#define AF12 197 +SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, + SIG_DESC_SET(SCU438, 5)); +SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), + SIG_EXPR_LIST_PTR(AF12, GPIOY5)); + +#define AC12 198 +SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); + +#define AB12 199 +SSSF_PIN_DECL(AB12, GPIOY7, FWSPIWP, SIG_DESC_SET(SCU438, 7)); + +#define AC10 200 +SSSF_PIN_DECL(AC10, GPIOZ0, SPI1CS1, SIG_DESC_SET(SCU438, 8)); + +#define AD10 201 +SSSF_PIN_DECL(AD10, GPIOZ1, SPI1ABR, SIG_DESC_SET(SCU438, 9)); + +#define AE10 202 +SSSF_PIN_DECL(AE10, GPIOZ2, SPI1WP, SIG_DESC_SET(SCU438, 10)); + +#define AB11 203 +SIG_EXPR_LIST_DECL_SEMG(AB11, SPI1CK, SPI1, SPI1, SIG_DESC_SET(SCU438, 11)); +PIN_DECL_1(AB11, GPIOZ3, SPI1CK); + +#define AC11 204 +SIG_EXPR_LIST_DECL_SEMG(AC11, SPI1MOSI, SPI1, SPI1, SIG_DESC_SET(SCU438, 12)); +PIN_DECL_1(AC11, GPIOZ4, SPI1MOSI); + +#define AA11 205 +SIG_EXPR_LIST_DECL_SEMG(AA11, SPI1MISO, SPI1, SPI1, SIG_DESC_SET(SCU438, 13)); +PIN_DECL_1(AA11, GPIOZ5, SPI1MISO); + +GROUP_DECL(SPI1, AB11, AC11, AA11); + +#define AD11 206 +SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14)); +SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13, + SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14)); +PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13); + +#define AF10 207 +SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15)); +SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13, + SIG_DESC_CLEAR(SCU4B8, 3), SIG_DESC_SET(SCU4D8, 15)); +PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13); + +GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10); +FUNC_DECL_2(SPI1, SPI1, QSPI1); + +GROUP_DECL(UART13G1, AD11, AF10); +FUNC_DECL_2(UART13, UART13G0, UART13G1); + +#define C6 208 +SIG_EXPR_LIST_DECL_SESG(C6, RGMII1TXCK, RGMII1, SIG_DESC_SET(SCU400, 0), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(C6, RMII1RCLKO, RMII1, SIG_DESC_SET(SCU400, 0), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(C6, GPIO18A0, RGMII1TXCK, RMII1RCLKO); + +#define D6 209 +SIG_EXPR_LIST_DECL_SESG(D6, RGMII1TXCTL, RGMII1, SIG_DESC_SET(SCU400, 1), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(D6, RMII1TXEN, RMII1, SIG_DESC_SET(SCU400, 1), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(D6, GPIO18A1, RGMII1TXCTL, RMII1TXEN); + +#define D5 210 +SIG_EXPR_LIST_DECL_SESG(D5, RGMII1TXD0, RGMII1, SIG_DESC_SET(SCU400, 2), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(D5, RMII1TXD0, RMII1, SIG_DESC_SET(SCU400, 2), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(D5, GPIO18A2, RGMII1TXD0, RMII1TXD0); + +#define A3 211 +SIG_EXPR_LIST_DECL_SESG(A3, RGMII1TXD1, RGMII1, SIG_DESC_SET(SCU400, 3), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(A3, RMII1TXD1, RMII1, SIG_DESC_SET(SCU400, 3), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(A3, GPIO18A3, RGMII1TXD1, RMII1TXD1); + +#define C5 212 +SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4), + SIG_DESC_SET(SCU500, 6)); +PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2); + +#define E6 213 +SIG_EXPR_LIST_DECL_SESG(E6, RGMII1TXD3, RGMII1, SIG_DESC_SET(SCU400, 5), + SIG_DESC_SET(SCU500, 6)); +PIN_DECL_1(E6, GPIO18A5, RGMII1TXD3); + +#define B3 214 +SIG_EXPR_LIST_DECL_SESG(B3, RGMII1RXCK, RGMII1, SIG_DESC_SET(SCU400, 6), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(B3, RMII1RCLKI, RMII1, SIG_DESC_SET(SCU400, 6), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(B3, GPIO18A6, RGMII1RXCK, RMII1RCLKI); + +#define A2 215 +SIG_EXPR_LIST_DECL_SESG(A2, RGMII1RXCTL, RGMII1, SIG_DESC_SET(SCU400, 7), + SIG_DESC_SET(SCU500, 6)); +PIN_DECL_1(A2, GPIO18A7, RGMII1RXCTL); + +#define B2 216 +SIG_EXPR_LIST_DECL_SESG(B2, RGMII1RXD0, RGMII1, SIG_DESC_SET(SCU400, 8), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(B2, RMII1RXD0, RMII1, SIG_DESC_SET(SCU400, 8), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(B2, GPIO18B0, RGMII1RXD0, RMII1RXD0); + +#define B1 217 +SIG_EXPR_LIST_DECL_SESG(B1, RGMII1RXD1, RGMII1, SIG_DESC_SET(SCU400, 9), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(B1, RMII1RXD1, RMII1, SIG_DESC_SET(SCU400, 9), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(B1, GPIO18B1, RGMII1RXD1, RMII1RXD1); + +#define C4 218 +SIG_EXPR_LIST_DECL_SESG(C4, RGMII1RXD2, RGMII1, SIG_DESC_SET(SCU400, 10), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(C4, RMII1CRSDV, RMII1, SIG_DESC_SET(SCU400, 10), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(C4, GPIO18B2, RGMII1RXD2, RMII1CRSDV); + +#define E5 219 +SIG_EXPR_LIST_DECL_SESG(E5, RGMII1RXD3, RGMII1, SIG_DESC_SET(SCU400, 11), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(E5, RMII1RXER, RMII1, SIG_DESC_SET(SCU400, 11), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(E5, GPIO18B3, RGMII1RXD3, RMII1RXER); + +FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5); +FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5); + +#define D4 220 +SIG_EXPR_LIST_DECL_SESG(D4, RGMII2TXCK, RGMII2, SIG_DESC_SET(SCU400, 12), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D4, RMII2RCLKO, RMII2, SIG_DESC_SET(SCU400, 12), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D4, GPIO18B4, RGMII2TXCK, RMII2RCLKO); + +#define C2 221 +SIG_EXPR_LIST_DECL_SESG(C2, RGMII2TXCTL, RGMII2, SIG_DESC_SET(SCU400, 13), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(C2, RMII2TXEN, RMII2, SIG_DESC_SET(SCU400, 13), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(C2, GPIO18B5, RGMII2TXCTL, RMII2TXEN); + +#define C1 222 +SIG_EXPR_LIST_DECL_SESG(C1, RGMII2TXD0, RGMII2, SIG_DESC_SET(SCU400, 14), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(C1, RMII2TXD0, RMII2, SIG_DESC_SET(SCU400, 14), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(C1, GPIO18B6, RGMII2TXD0, RMII2TXD0); + +#define D3 223 +SIG_EXPR_LIST_DECL_SESG(D3, RGMII2TXD1, RGMII2, SIG_DESC_SET(SCU400, 15), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D3, RMII2TXD1, RMII2, SIG_DESC_SET(SCU400, 15), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D3, GPIO18B7, RGMII2TXD1, RMII2TXD1); + +#define E4 224 +SIG_EXPR_LIST_DECL_SESG(E4, RGMII2TXD2, RGMII2, SIG_DESC_SET(SCU400, 16), + SIG_DESC_SET(SCU500, 7)); +PIN_DECL_1(E4, GPIO18C0, RGMII2TXD2); + +#define F5 225 +SIG_EXPR_LIST_DECL_SESG(F5, RGMII2TXD3, RGMII2, SIG_DESC_SET(SCU400, 17), + SIG_DESC_SET(SCU500, 7)); +PIN_DECL_1(F5, GPIO18C1, RGMII2TXD3); + +#define D2 226 +SIG_EXPR_LIST_DECL_SESG(D2, RGMII2RXCK, RGMII2, SIG_DESC_SET(SCU400, 18), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D2, RMII2RCLKI, RMII2, SIG_DESC_SET(SCU400, 18), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D2, GPIO18C2, RGMII2RXCK, RMII2RCLKI); + +#define E3 227 +SIG_EXPR_LIST_DECL_SESG(E3, RGMII2RXCTL, RGMII2, SIG_DESC_SET(SCU400, 19), + SIG_DESC_SET(SCU500, 7)); +PIN_DECL_1(E3, GPIO18C3, RGMII2RXCTL); + +#define D1 228 +SIG_EXPR_LIST_DECL_SESG(D1, RGMII2RXD0, RGMII2, SIG_DESC_SET(SCU400, 20), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D1, RMII2RXD0, RMII2, SIG_DESC_SET(SCU400, 20), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D1, GPIO18C4, RGMII2RXD0, RMII2RXD0); + +#define F4 229 +SIG_EXPR_LIST_DECL_SESG(F4, RGMII2RXD1, RGMII2, SIG_DESC_SET(SCU400, 21), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(F4, RMII2RXD1, RMII2, SIG_DESC_SET(SCU400, 21), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(F4, GPIO18C5, RGMII2RXD1, RMII2RXD1); + +#define E2 230 +SIG_EXPR_LIST_DECL_SESG(E2, RGMII2RXD2, RGMII2, SIG_DESC_SET(SCU400, 22), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(E2, RMII2CRSDV, RMII2, SIG_DESC_SET(SCU400, 22), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(E2, GPIO18C6, RGMII2RXD2, RMII2CRSDV); + +#define E1 231 +SIG_EXPR_LIST_DECL_SESG(E1, RGMII2RXD3, RGMII2, SIG_DESC_SET(SCU400, 23), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(E1, RMII2RXER, RMII2, SIG_DESC_SET(SCU400, 23), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(E1, GPIO18C7, RGMII2RXD3, RMII2RXER); + +FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1); +FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1); + +#define AB4 232 +SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24)); +PIN_DECL_1(AB4, GPIO18D0, EMMCCLK); + +#define AA4 233 +SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25)); +PIN_DECL_1(AA4, GPIO18D1, EMMCCMD); + +#define AC4 234 +SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26)); +PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0); + +#define AA5 235 +SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27)); +PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1); + +#define Y5 236 +SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28)); +PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2); + +#define AB5 237 +SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29)); +PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3); + +#define AB6 238 +SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30)); +PIN_DECL_1(AB6, GPIO18D6, EMMCCD); + +#define AC5 239 +SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31)); +PIN_DECL_1(AC5, GPIO18D7, EMMCWP); + +GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5); +GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); + +#define Y1 240 +SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0)); +PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4); + +#define Y2 241 +SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1)); +PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5); + +#define Y3 242 +SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID, + SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2)); +PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6); + +#define Y4 243 +SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID, + SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3)); +PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); + +GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); +GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); +GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4); +FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); +FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); +FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); +/* + * FIXME: Confirm bits and priorities are the right way around for the + * following 4 pins + */ +#define AF25 244 +SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20)); +SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20)); +PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL), + SIG_EXPR_LIST_PTR(AF25, FSI1CLK)); + +#define AE26 245 +SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21)); +SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21)); +PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA), + SIG_EXPR_LIST_PTR(AE26, FSI1DATA)); + +GROUP_DECL(I3C3, AF25, AE26); +FUNC_DECL_2(I3C3, HVI3C3, I3C3); +FUNC_GROUP_DECL(FSI1, AF25, AE26); + +#define AE25 246 +SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22)); +SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22)); +PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL), + SIG_EXPR_LIST_PTR(AE25, FSI2CLK)); + +#define AF24 247 +SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23)); +SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23)); +PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA), + SIG_EXPR_LIST_PTR(AF24, FSI2DATA)); + +GROUP_DECL(I3C4, AE25, AF24); +FUNC_DECL_2(I3C4, HVI3C4, I3C4); +FUNC_GROUP_DECL(FSI2, AE25, AF24); + +#define AF23 248 +SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16)); +PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL)); + +#define AE24 249 +SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17)); +PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA)); + +FUNC_GROUP_DECL(I3C1, AF23, AE24); + +#define AF22 250 +SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18)); +PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL)); + +#define AE22 251 +SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19)); +PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA)); + +FUNC_GROUP_DECL(I3C2, AF22, AE22); + +#define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 } +#define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 } +#define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 } +#define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 } +#define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 } +#define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 } +#define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 } + +#define A4 252 +SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC, + SIG_DESC_SET(SCUC20, 16)); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC); +PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP), + SIG_EXPR_LIST_PTR(A4, USB2AHDP)); + +#define B4 253 +SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC); +PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN), + SIG_EXPR_LIST_PTR(B4, USB2AHDN)); + +GROUP_DECL(USBA, A4, B4); + +FUNC_DECL_1(USB2ADP, USBA); +FUNC_DECL_1(USB2AD, USBA); +FUNC_DECL_1(USB2AH, USBA); +FUNC_DECL_1(USB2AHP, USBA); + +#define A6 254 +SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC); +SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC); +PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP), + SIG_EXPR_LIST_PTR(A6, USB2BHDP)); + +#define B6 255 +SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC); +SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC); +PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN), + SIG_EXPR_LIST_PTR(B6, USB2BHDN)); + +GROUP_DECL(USBB, A6, B6); + +FUNC_DECL_1(USB11BHID, USBB); +FUNC_DECL_1(USB2BD, USBB); +FUNC_DECL_1(USB2BH, USBB); + +/* Pins, groups and functions are sort(1):ed alphabetically for sanity */ + +static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { + ASPEED_PINCTRL_PIN(A11), + ASPEED_PINCTRL_PIN(A12), + ASPEED_PINCTRL_PIN(A13), + ASPEED_PINCTRL_PIN(A14), + ASPEED_PINCTRL_PIN(A15), + ASPEED_PINCTRL_PIN(A16), + ASPEED_PINCTRL_PIN(A17), + ASPEED_PINCTRL_PIN(A18), + ASPEED_PINCTRL_PIN(A19), + ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A20), + ASPEED_PINCTRL_PIN(A21), + ASPEED_PINCTRL_PIN(A22), + ASPEED_PINCTRL_PIN(A23), + ASPEED_PINCTRL_PIN(A24), + ASPEED_PINCTRL_PIN(A25), + ASPEED_PINCTRL_PIN(A3), + ASPEED_PINCTRL_PIN(A4), + ASPEED_PINCTRL_PIN(A6), + ASPEED_PINCTRL_PIN(AA11), + ASPEED_PINCTRL_PIN(AA12), + ASPEED_PINCTRL_PIN(AA16), + ASPEED_PINCTRL_PIN(AA17), + ASPEED_PINCTRL_PIN(AA23), + ASPEED_PINCTRL_PIN(AA24), + ASPEED_PINCTRL_PIN(AA25), + ASPEED_PINCTRL_PIN(AA26), + ASPEED_PINCTRL_PIN(AA4), + ASPEED_PINCTRL_PIN(AA5), + ASPEED_PINCTRL_PIN(AA9), + ASPEED_PINCTRL_PIN(AB10), + ASPEED_PINCTRL_PIN(AB11), + ASPEED_PINCTRL_PIN(AB12), + ASPEED_PINCTRL_PIN(AB15), + ASPEED_PINCTRL_PIN(AB16), + ASPEED_PINCTRL_PIN(AB17), + ASPEED_PINCTRL_PIN(AB18), + ASPEED_PINCTRL_PIN(AB19), + ASPEED_PINCTRL_PIN(AB22), + ASPEED_PINCTRL_PIN(AB23), + ASPEED_PINCTRL_PIN(AB24), + ASPEED_PINCTRL_PIN(AB25), + ASPEED_PINCTRL_PIN(AB26), + ASPEED_PINCTRL_PIN(AB4), + ASPEED_PINCTRL_PIN(AB5), + ASPEED_PINCTRL_PIN(AB6), + ASPEED_PINCTRL_PIN(AB7), + ASPEED_PINCTRL_PIN(AB8), + ASPEED_PINCTRL_PIN(AB9), + ASPEED_PINCTRL_PIN(AC10), + ASPEED_PINCTRL_PIN(AC11), + ASPEED_PINCTRL_PIN(AC12), + ASPEED_PINCTRL_PIN(AC15), + ASPEED_PINCTRL_PIN(AC16), + ASPEED_PINCTRL_PIN(AC17), + ASPEED_PINCTRL_PIN(AC18), + ASPEED_PINCTRL_PIN(AC19), + ASPEED_PINCTRL_PIN(AC22), + ASPEED_PINCTRL_PIN(AC23), + ASPEED_PINCTRL_PIN(AC24), + ASPEED_PINCTRL_PIN(AC26), + ASPEED_PINCTRL_PIN(AC4), + ASPEED_PINCTRL_PIN(AC5), + ASPEED_PINCTRL_PIN(AC7), + ASPEED_PINCTRL_PIN(AC8), + ASPEED_PINCTRL_PIN(AC9), + ASPEED_PINCTRL_PIN(AD10), + ASPEED_PINCTRL_PIN(AD11), + ASPEED_PINCTRL_PIN(AD12), + ASPEED_PINCTRL_PIN(AD14), + ASPEED_PINCTRL_PIN(AD15), + ASPEED_PINCTRL_PIN(AD16), + ASPEED_PINCTRL_PIN(AD19), + ASPEED_PINCTRL_PIN(AD20), + ASPEED_PINCTRL_PIN(AD22), + ASPEED_PINCTRL_PIN(AD23), + ASPEED_PINCTRL_PIN(AD24), + ASPEED_PINCTRL_PIN(AD25), + ASPEED_PINCTRL_PIN(AD26), + ASPEED_PINCTRL_PIN(AD7), + ASPEED_PINCTRL_PIN(AD8), + ASPEED_PINCTRL_PIN(AD9), + ASPEED_PINCTRL_PIN(AE10), + ASPEED_PINCTRL_PIN(AE11), + ASPEED_PINCTRL_PIN(AE12), + ASPEED_PINCTRL_PIN(AE14), + ASPEED_PINCTRL_PIN(AE15), + ASPEED_PINCTRL_PIN(AE16), + ASPEED_PINCTRL_PIN(AE18), + ASPEED_PINCTRL_PIN(AE19), + ASPEED_PINCTRL_PIN(AE22), + ASPEED_PINCTRL_PIN(AE24), + ASPEED_PINCTRL_PIN(AE25), + ASPEED_PINCTRL_PIN(AE26), + ASPEED_PINCTRL_PIN(AE7), + ASPEED_PINCTRL_PIN(AE8), + ASPEED_PINCTRL_PIN(AF10), + ASPEED_PINCTRL_PIN(AF11), + ASPEED_PINCTRL_PIN(AF12), + ASPEED_PINCTRL_PIN(AF14), + ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF22), + ASPEED_PINCTRL_PIN(AF23), + ASPEED_PINCTRL_PIN(AF24), + ASPEED_PINCTRL_PIN(AF25), + ASPEED_PINCTRL_PIN(AF7), + ASPEED_PINCTRL_PIN(AF8), + ASPEED_PINCTRL_PIN(AF9), + ASPEED_PINCTRL_PIN(B1), + ASPEED_PINCTRL_PIN(B12), + ASPEED_PINCTRL_PIN(B13), + ASPEED_PINCTRL_PIN(B14), + ASPEED_PINCTRL_PIN(B16), + ASPEED_PINCTRL_PIN(B17), + ASPEED_PINCTRL_PIN(B18), + ASPEED_PINCTRL_PIN(B2), + ASPEED_PINCTRL_PIN(B20), + ASPEED_PINCTRL_PIN(B21), + ASPEED_PINCTRL_PIN(B22), + ASPEED_PINCTRL_PIN(B24), + ASPEED_PINCTRL_PIN(B25), + ASPEED_PINCTRL_PIN(B26), + ASPEED_PINCTRL_PIN(B3), + ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(B6), + ASPEED_PINCTRL_PIN(C1), + ASPEED_PINCTRL_PIN(C11), + ASPEED_PINCTRL_PIN(C12), + ASPEED_PINCTRL_PIN(C13), + ASPEED_PINCTRL_PIN(C14), + ASPEED_PINCTRL_PIN(C15), + ASPEED_PINCTRL_PIN(C16), + ASPEED_PINCTRL_PIN(C17), + ASPEED_PINCTRL_PIN(C18), + ASPEED_PINCTRL_PIN(C19), + ASPEED_PINCTRL_PIN(C2), + ASPEED_PINCTRL_PIN(C20), + ASPEED_PINCTRL_PIN(C21), + ASPEED_PINCTRL_PIN(C22), + ASPEED_PINCTRL_PIN(C23), + ASPEED_PINCTRL_PIN(C24), + ASPEED_PINCTRL_PIN(C25), + ASPEED_PINCTRL_PIN(C26), + ASPEED_PINCTRL_PIN(C4), + ASPEED_PINCTRL_PIN(C5), + ASPEED_PINCTRL_PIN(C6), + ASPEED_PINCTRL_PIN(D1), + ASPEED_PINCTRL_PIN(D11), + ASPEED_PINCTRL_PIN(D12), + ASPEED_PINCTRL_PIN(D13), + ASPEED_PINCTRL_PIN(D14), + ASPEED_PINCTRL_PIN(D15), + ASPEED_PINCTRL_PIN(D16), + ASPEED_PINCTRL_PIN(D17), + ASPEED_PINCTRL_PIN(D18), + ASPEED_PINCTRL_PIN(D19), + ASPEED_PINCTRL_PIN(D2), + ASPEED_PINCTRL_PIN(D20), + ASPEED_PINCTRL_PIN(D21), + ASPEED_PINCTRL_PIN(D22), + ASPEED_PINCTRL_PIN(D23), + ASPEED_PINCTRL_PIN(D24), + ASPEED_PINCTRL_PIN(D26), + ASPEED_PINCTRL_PIN(D3), + ASPEED_PINCTRL_PIN(D4), + ASPEED_PINCTRL_PIN(D5), + ASPEED_PINCTRL_PIN(D6), + ASPEED_PINCTRL_PIN(E1), + ASPEED_PINCTRL_PIN(E11), + ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(E13), + ASPEED_PINCTRL_PIN(E14), + ASPEED_PINCTRL_PIN(E15), + ASPEED_PINCTRL_PIN(E16), + ASPEED_PINCTRL_PIN(E17), + ASPEED_PINCTRL_PIN(E18), + ASPEED_PINCTRL_PIN(E19), + ASPEED_PINCTRL_PIN(E2), + ASPEED_PINCTRL_PIN(E20), + ASPEED_PINCTRL_PIN(E21), + ASPEED_PINCTRL_PIN(E22), + ASPEED_PINCTRL_PIN(E23), + ASPEED_PINCTRL_PIN(E24), + ASPEED_PINCTRL_PIN(E25), + ASPEED_PINCTRL_PIN(E26), + ASPEED_PINCTRL_PIN(E3), + ASPEED_PINCTRL_PIN(E4), + ASPEED_PINCTRL_PIN(E5), + ASPEED_PINCTRL_PIN(E6), + ASPEED_PINCTRL_PIN(F13), + ASPEED_PINCTRL_PIN(F15), + ASPEED_PINCTRL_PIN(F22), + ASPEED_PINCTRL_PIN(F23), + ASPEED_PINCTRL_PIN(F24), + ASPEED_PINCTRL_PIN(F25), + ASPEED_PINCTRL_PIN(F26), + ASPEED_PINCTRL_PIN(F4), + ASPEED_PINCTRL_PIN(F5), + ASPEED_PINCTRL_PIN(G22), + ASPEED_PINCTRL_PIN(G23), + ASPEED_PINCTRL_PIN(G24), + ASPEED_PINCTRL_PIN(G26), + ASPEED_PINCTRL_PIN(H22), + ASPEED_PINCTRL_PIN(H23), + ASPEED_PINCTRL_PIN(H24), + ASPEED_PINCTRL_PIN(H25), + ASPEED_PINCTRL_PIN(H26), + ASPEED_PINCTRL_PIN(J22), + ASPEED_PINCTRL_PIN(J23), + ASPEED_PINCTRL_PIN(J24), + ASPEED_PINCTRL_PIN(J25), + ASPEED_PINCTRL_PIN(J26), + ASPEED_PINCTRL_PIN(K23), + ASPEED_PINCTRL_PIN(K24), + ASPEED_PINCTRL_PIN(K25), + ASPEED_PINCTRL_PIN(K26), + ASPEED_PINCTRL_PIN(L23), + ASPEED_PINCTRL_PIN(L24), + ASPEED_PINCTRL_PIN(L26), + ASPEED_PINCTRL_PIN(M23), + ASPEED_PINCTRL_PIN(M24), + ASPEED_PINCTRL_PIN(M25), + ASPEED_PINCTRL_PIN(M26), + ASPEED_PINCTRL_PIN(N23), + ASPEED_PINCTRL_PIN(N24), + ASPEED_PINCTRL_PIN(N25), + ASPEED_PINCTRL_PIN(N26), + ASPEED_PINCTRL_PIN(P23), + ASPEED_PINCTRL_PIN(P24), + ASPEED_PINCTRL_PIN(P25), + ASPEED_PINCTRL_PIN(P26), + ASPEED_PINCTRL_PIN(R23), + ASPEED_PINCTRL_PIN(R24), + ASPEED_PINCTRL_PIN(R26), + ASPEED_PINCTRL_PIN(T23), + ASPEED_PINCTRL_PIN(T24), + ASPEED_PINCTRL_PIN(T25), + ASPEED_PINCTRL_PIN(T26), + ASPEED_PINCTRL_PIN(U24), + ASPEED_PINCTRL_PIN(U25), + ASPEED_PINCTRL_PIN(U26), + ASPEED_PINCTRL_PIN(V24), + ASPEED_PINCTRL_PIN(V25), + ASPEED_PINCTRL_PIN(V26), + ASPEED_PINCTRL_PIN(W23), + ASPEED_PINCTRL_PIN(W24), + ASPEED_PINCTRL_PIN(W26), + ASPEED_PINCTRL_PIN(Y1), + ASPEED_PINCTRL_PIN(Y2), + ASPEED_PINCTRL_PIN(Y23), + ASPEED_PINCTRL_PIN(Y24), + ASPEED_PINCTRL_PIN(Y25), + ASPEED_PINCTRL_PIN(Y26), + ASPEED_PINCTRL_PIN(Y3), + ASPEED_PINCTRL_PIN(Y4), + ASPEED_PINCTRL_PIN(Y5), +}; + +static const struct aspeed_pin_group aspeed_g6_groups[] = { + ASPEED_PINCTRL_GROUP(ADC0), + ASPEED_PINCTRL_GROUP(ADC1), + ASPEED_PINCTRL_GROUP(ADC10), + ASPEED_PINCTRL_GROUP(ADC11), + ASPEED_PINCTRL_GROUP(ADC12), + ASPEED_PINCTRL_GROUP(ADC13), + ASPEED_PINCTRL_GROUP(ADC14), + ASPEED_PINCTRL_GROUP(ADC15), + ASPEED_PINCTRL_GROUP(ADC2), + ASPEED_PINCTRL_GROUP(ADC3), + ASPEED_PINCTRL_GROUP(ADC4), + ASPEED_PINCTRL_GROUP(ADC5), + ASPEED_PINCTRL_GROUP(ADC6), + ASPEED_PINCTRL_GROUP(ADC7), + ASPEED_PINCTRL_GROUP(ADC8), + ASPEED_PINCTRL_GROUP(ADC9), + ASPEED_PINCTRL_GROUP(BMCINT), + ASPEED_PINCTRL_GROUP(ESPI), + ASPEED_PINCTRL_GROUP(ESPIALT), + ASPEED_PINCTRL_GROUP(FSI1), + ASPEED_PINCTRL_GROUP(FSI2), + ASPEED_PINCTRL_GROUP(FWSPIABR), + ASPEED_PINCTRL_GROUP(FWSPID), + ASPEED_PINCTRL_GROUP(FWQSPID), + ASPEED_PINCTRL_GROUP(FWSPIWP), + ASPEED_PINCTRL_GROUP(GPIT0), + ASPEED_PINCTRL_GROUP(GPIT1), + ASPEED_PINCTRL_GROUP(GPIT2), + ASPEED_PINCTRL_GROUP(GPIT3), + ASPEED_PINCTRL_GROUP(GPIT4), + ASPEED_PINCTRL_GROUP(GPIT5), + ASPEED_PINCTRL_GROUP(GPIT6), + ASPEED_PINCTRL_GROUP(GPIT7), + ASPEED_PINCTRL_GROUP(GPIU0), + ASPEED_PINCTRL_GROUP(GPIU1), + ASPEED_PINCTRL_GROUP(GPIU2), + ASPEED_PINCTRL_GROUP(GPIU3), + ASPEED_PINCTRL_GROUP(GPIU4), + ASPEED_PINCTRL_GROUP(GPIU5), + ASPEED_PINCTRL_GROUP(GPIU6), + ASPEED_PINCTRL_GROUP(GPIU7), + ASPEED_PINCTRL_GROUP(HVI3C3), + ASPEED_PINCTRL_GROUP(HVI3C4), + ASPEED_PINCTRL_GROUP(I2C1), + ASPEED_PINCTRL_GROUP(I2C10), + ASPEED_PINCTRL_GROUP(I2C11), + ASPEED_PINCTRL_GROUP(I2C12), + ASPEED_PINCTRL_GROUP(I2C13), + ASPEED_PINCTRL_GROUP(I2C14), + ASPEED_PINCTRL_GROUP(I2C15), + ASPEED_PINCTRL_GROUP(I2C16), + ASPEED_PINCTRL_GROUP(I2C2), + ASPEED_PINCTRL_GROUP(I2C3), + ASPEED_PINCTRL_GROUP(I2C4), + ASPEED_PINCTRL_GROUP(I2C5), + ASPEED_PINCTRL_GROUP(I2C6), + ASPEED_PINCTRL_GROUP(I2C7), + ASPEED_PINCTRL_GROUP(I2C8), + ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(I3C1), + ASPEED_PINCTRL_GROUP(I3C2), + ASPEED_PINCTRL_GROUP(I3C3), + ASPEED_PINCTRL_GROUP(I3C4), + ASPEED_PINCTRL_GROUP(I3C5), + ASPEED_PINCTRL_GROUP(I3C6), + ASPEED_PINCTRL_GROUP(JTAGM), + ASPEED_PINCTRL_GROUP(LHPD), + ASPEED_PINCTRL_GROUP(LHSIRQ), + ASPEED_PINCTRL_GROUP(LPC), + ASPEED_PINCTRL_GROUP(LPCHC), + ASPEED_PINCTRL_GROUP(LPCPD), + ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCSMI), + ASPEED_PINCTRL_GROUP(LSIRQ), + ASPEED_PINCTRL_GROUP(MACLINK1), + ASPEED_PINCTRL_GROUP(MACLINK2), + ASPEED_PINCTRL_GROUP(MACLINK3), + ASPEED_PINCTRL_GROUP(MACLINK4), + ASPEED_PINCTRL_GROUP(MDIO1), + ASPEED_PINCTRL_GROUP(MDIO2), + ASPEED_PINCTRL_GROUP(MDIO3), + ASPEED_PINCTRL_GROUP(MDIO4), + ASPEED_PINCTRL_GROUP(NCTS1), + ASPEED_PINCTRL_GROUP(NCTS2), + ASPEED_PINCTRL_GROUP(NCTS3), + ASPEED_PINCTRL_GROUP(NCTS4), + ASPEED_PINCTRL_GROUP(NDCD1), + ASPEED_PINCTRL_GROUP(NDCD2), + ASPEED_PINCTRL_GROUP(NDCD3), + ASPEED_PINCTRL_GROUP(NDCD4), + ASPEED_PINCTRL_GROUP(NDSR1), + ASPEED_PINCTRL_GROUP(NDSR2), + ASPEED_PINCTRL_GROUP(NDSR3), + ASPEED_PINCTRL_GROUP(NDSR4), + ASPEED_PINCTRL_GROUP(NDTR1), + ASPEED_PINCTRL_GROUP(NDTR2), + ASPEED_PINCTRL_GROUP(NDTR3), + ASPEED_PINCTRL_GROUP(NDTR4), + ASPEED_PINCTRL_GROUP(NRI1), + ASPEED_PINCTRL_GROUP(NRI2), + ASPEED_PINCTRL_GROUP(NRI3), + ASPEED_PINCTRL_GROUP(NRI4), + ASPEED_PINCTRL_GROUP(NRTS1), + ASPEED_PINCTRL_GROUP(NRTS2), + ASPEED_PINCTRL_GROUP(NRTS3), + ASPEED_PINCTRL_GROUP(NRTS4), + ASPEED_PINCTRL_GROUP(OSCCLK), + ASPEED_PINCTRL_GROUP(PEWAKE), + ASPEED_PINCTRL_GROUP(PWM0), + ASPEED_PINCTRL_GROUP(PWM1), + ASPEED_PINCTRL_GROUP(PWM10G0), + ASPEED_PINCTRL_GROUP(PWM10G1), + ASPEED_PINCTRL_GROUP(PWM11G0), + ASPEED_PINCTRL_GROUP(PWM11G1), + ASPEED_PINCTRL_GROUP(PWM12G0), + ASPEED_PINCTRL_GROUP(PWM12G1), + ASPEED_PINCTRL_GROUP(PWM13G0), + ASPEED_PINCTRL_GROUP(PWM13G1), + ASPEED_PINCTRL_GROUP(PWM14G0), + ASPEED_PINCTRL_GROUP(PWM14G1), + ASPEED_PINCTRL_GROUP(PWM15G0), + ASPEED_PINCTRL_GROUP(PWM15G1), + ASPEED_PINCTRL_GROUP(PWM2), + ASPEED_PINCTRL_GROUP(PWM3), + ASPEED_PINCTRL_GROUP(PWM4), + ASPEED_PINCTRL_GROUP(PWM5), + ASPEED_PINCTRL_GROUP(PWM6), + ASPEED_PINCTRL_GROUP(PWM7), + ASPEED_PINCTRL_GROUP(PWM8G0), + ASPEED_PINCTRL_GROUP(PWM8G1), + ASPEED_PINCTRL_GROUP(PWM9G0), + ASPEED_PINCTRL_GROUP(PWM9G1), + ASPEED_PINCTRL_GROUP(QSPI1), + ASPEED_PINCTRL_GROUP(QSPI2), + ASPEED_PINCTRL_GROUP(RGMII1), + ASPEED_PINCTRL_GROUP(RGMII2), + ASPEED_PINCTRL_GROUP(RGMII3), + ASPEED_PINCTRL_GROUP(RGMII4), + ASPEED_PINCTRL_GROUP(RMII1), + ASPEED_PINCTRL_GROUP(RMII2), + ASPEED_PINCTRL_GROUP(RMII3), + ASPEED_PINCTRL_GROUP(RMII4), + ASPEED_PINCTRL_GROUP(RXD1), + ASPEED_PINCTRL_GROUP(RXD2), + ASPEED_PINCTRL_GROUP(RXD3), + ASPEED_PINCTRL_GROUP(RXD4), + ASPEED_PINCTRL_GROUP(SALT1), + ASPEED_PINCTRL_GROUP(SALT10G0), + ASPEED_PINCTRL_GROUP(SALT10G1), + ASPEED_PINCTRL_GROUP(SALT11G0), + ASPEED_PINCTRL_GROUP(SALT11G1), + ASPEED_PINCTRL_GROUP(SALT12G0), + ASPEED_PINCTRL_GROUP(SALT12G1), + ASPEED_PINCTRL_GROUP(SALT13G0), + ASPEED_PINCTRL_GROUP(SALT13G1), + ASPEED_PINCTRL_GROUP(SALT14G0), + ASPEED_PINCTRL_GROUP(SALT14G1), + ASPEED_PINCTRL_GROUP(SALT15G0), + ASPEED_PINCTRL_GROUP(SALT15G1), + ASPEED_PINCTRL_GROUP(SALT16G0), + ASPEED_PINCTRL_GROUP(SALT16G1), + ASPEED_PINCTRL_GROUP(SALT2), + ASPEED_PINCTRL_GROUP(SALT3), + ASPEED_PINCTRL_GROUP(SALT4), + ASPEED_PINCTRL_GROUP(SALT5), + ASPEED_PINCTRL_GROUP(SALT6), + ASPEED_PINCTRL_GROUP(SALT7), + ASPEED_PINCTRL_GROUP(SALT8), + ASPEED_PINCTRL_GROUP(SALT9G0), + ASPEED_PINCTRL_GROUP(SALT9G1), + ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SD2), + ASPEED_PINCTRL_GROUP(EMMCG1), + ASPEED_PINCTRL_GROUP(EMMCG4), + ASPEED_PINCTRL_GROUP(EMMCG8), + ASPEED_PINCTRL_GROUP(SGPM1), + ASPEED_PINCTRL_GROUP(SGPS1), + ASPEED_PINCTRL_GROUP(SIOONCTRL), + ASPEED_PINCTRL_GROUP(SIOPBI), + ASPEED_PINCTRL_GROUP(SIOPBO), + ASPEED_PINCTRL_GROUP(SIOPWREQ), + ASPEED_PINCTRL_GROUP(SIOPWRGD), + ASPEED_PINCTRL_GROUP(SIOS3), + ASPEED_PINCTRL_GROUP(SIOS5), + ASPEED_PINCTRL_GROUP(SIOSCI), + ASPEED_PINCTRL_GROUP(SPI1), + ASPEED_PINCTRL_GROUP(SPI1ABR), + ASPEED_PINCTRL_GROUP(SPI1CS1), + ASPEED_PINCTRL_GROUP(SPI1WP), + ASPEED_PINCTRL_GROUP(SPI2), + ASPEED_PINCTRL_GROUP(SPI2CS1), + ASPEED_PINCTRL_GROUP(SPI2CS2), + ASPEED_PINCTRL_GROUP(TACH0), + ASPEED_PINCTRL_GROUP(TACH1), + ASPEED_PINCTRL_GROUP(TACH10), + ASPEED_PINCTRL_GROUP(TACH11), + ASPEED_PINCTRL_GROUP(TACH12), + ASPEED_PINCTRL_GROUP(TACH13), + ASPEED_PINCTRL_GROUP(TACH14), + ASPEED_PINCTRL_GROUP(TACH15), + ASPEED_PINCTRL_GROUP(TACH2), + ASPEED_PINCTRL_GROUP(TACH3), + ASPEED_PINCTRL_GROUP(TACH4), + ASPEED_PINCTRL_GROUP(TACH5), + ASPEED_PINCTRL_GROUP(TACH6), + ASPEED_PINCTRL_GROUP(TACH7), + ASPEED_PINCTRL_GROUP(TACH8), + ASPEED_PINCTRL_GROUP(TACH9), + ASPEED_PINCTRL_GROUP(THRU0), + ASPEED_PINCTRL_GROUP(THRU1), + ASPEED_PINCTRL_GROUP(THRU2), + ASPEED_PINCTRL_GROUP(THRU3), + ASPEED_PINCTRL_GROUP(TXD1), + ASPEED_PINCTRL_GROUP(TXD2), + ASPEED_PINCTRL_GROUP(TXD3), + ASPEED_PINCTRL_GROUP(TXD4), + ASPEED_PINCTRL_GROUP(UART10), + ASPEED_PINCTRL_GROUP(UART11), + ASPEED_PINCTRL_GROUP(UART12G0), + ASPEED_PINCTRL_GROUP(UART12G1), + ASPEED_PINCTRL_GROUP(UART13G0), + ASPEED_PINCTRL_GROUP(UART13G1), + ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(UART7), + ASPEED_PINCTRL_GROUP(UART8), + ASPEED_PINCTRL_GROUP(UART9), + ASPEED_PINCTRL_GROUP(USBA), + ASPEED_PINCTRL_GROUP(USBB), + ASPEED_PINCTRL_GROUP(VB), + ASPEED_PINCTRL_GROUP(VGAHS), + ASPEED_PINCTRL_GROUP(VGAVS), + ASPEED_PINCTRL_GROUP(WDTRST1), + ASPEED_PINCTRL_GROUP(WDTRST2), + ASPEED_PINCTRL_GROUP(WDTRST3), + ASPEED_PINCTRL_GROUP(WDTRST4), +}; + +static const struct aspeed_pin_function aspeed_g6_functions[] = { + ASPEED_PINCTRL_FUNC(ADC0), + ASPEED_PINCTRL_FUNC(ADC1), + ASPEED_PINCTRL_FUNC(ADC10), + ASPEED_PINCTRL_FUNC(ADC11), + ASPEED_PINCTRL_FUNC(ADC12), + ASPEED_PINCTRL_FUNC(ADC13), + ASPEED_PINCTRL_FUNC(ADC14), + ASPEED_PINCTRL_FUNC(ADC15), + ASPEED_PINCTRL_FUNC(ADC2), + ASPEED_PINCTRL_FUNC(ADC3), + ASPEED_PINCTRL_FUNC(ADC4), + ASPEED_PINCTRL_FUNC(ADC5), + ASPEED_PINCTRL_FUNC(ADC6), + ASPEED_PINCTRL_FUNC(ADC7), + ASPEED_PINCTRL_FUNC(ADC8), + ASPEED_PINCTRL_FUNC(ADC9), + ASPEED_PINCTRL_FUNC(BMCINT), + ASPEED_PINCTRL_FUNC(EMMC), + ASPEED_PINCTRL_FUNC(ESPI), + ASPEED_PINCTRL_FUNC(ESPIALT), + ASPEED_PINCTRL_FUNC(FSI1), + ASPEED_PINCTRL_FUNC(FSI2), + ASPEED_PINCTRL_FUNC(FWSPIABR), + ASPEED_PINCTRL_FUNC(FWSPID), + ASPEED_PINCTRL_FUNC(FWSPIWP), + ASPEED_PINCTRL_FUNC(GPIT0), + ASPEED_PINCTRL_FUNC(GPIT1), + ASPEED_PINCTRL_FUNC(GPIT2), + ASPEED_PINCTRL_FUNC(GPIT3), + ASPEED_PINCTRL_FUNC(GPIT4), + ASPEED_PINCTRL_FUNC(GPIT5), + ASPEED_PINCTRL_FUNC(GPIT6), + ASPEED_PINCTRL_FUNC(GPIT7), + ASPEED_PINCTRL_FUNC(GPIU0), + ASPEED_PINCTRL_FUNC(GPIU1), + ASPEED_PINCTRL_FUNC(GPIU2), + ASPEED_PINCTRL_FUNC(GPIU3), + ASPEED_PINCTRL_FUNC(GPIU4), + ASPEED_PINCTRL_FUNC(GPIU5), + ASPEED_PINCTRL_FUNC(GPIU6), + ASPEED_PINCTRL_FUNC(GPIU7), + ASPEED_PINCTRL_FUNC(I2C1), + ASPEED_PINCTRL_FUNC(I2C10), + ASPEED_PINCTRL_FUNC(I2C11), + ASPEED_PINCTRL_FUNC(I2C12), + ASPEED_PINCTRL_FUNC(I2C13), + ASPEED_PINCTRL_FUNC(I2C14), + ASPEED_PINCTRL_FUNC(I2C15), + ASPEED_PINCTRL_FUNC(I2C16), + ASPEED_PINCTRL_FUNC(I2C2), + ASPEED_PINCTRL_FUNC(I2C3), + ASPEED_PINCTRL_FUNC(I2C4), + ASPEED_PINCTRL_FUNC(I2C5), + ASPEED_PINCTRL_FUNC(I2C6), + ASPEED_PINCTRL_FUNC(I2C7), + ASPEED_PINCTRL_FUNC(I2C8), + ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(I3C1), + ASPEED_PINCTRL_FUNC(I3C2), + ASPEED_PINCTRL_FUNC(I3C3), + ASPEED_PINCTRL_FUNC(I3C4), + ASPEED_PINCTRL_FUNC(I3C5), + ASPEED_PINCTRL_FUNC(I3C6), + ASPEED_PINCTRL_FUNC(JTAGM), + ASPEED_PINCTRL_FUNC(LHPD), + ASPEED_PINCTRL_FUNC(LHSIRQ), + ASPEED_PINCTRL_FUNC(LPC), + ASPEED_PINCTRL_FUNC(LPCHC), + ASPEED_PINCTRL_FUNC(LPCPD), + ASPEED_PINCTRL_FUNC(LPCPME), + ASPEED_PINCTRL_FUNC(LPCSMI), + ASPEED_PINCTRL_FUNC(LSIRQ), + ASPEED_PINCTRL_FUNC(MACLINK1), + ASPEED_PINCTRL_FUNC(MACLINK2), + ASPEED_PINCTRL_FUNC(MACLINK3), + ASPEED_PINCTRL_FUNC(MACLINK4), + ASPEED_PINCTRL_FUNC(MDIO1), + ASPEED_PINCTRL_FUNC(MDIO2), + ASPEED_PINCTRL_FUNC(MDIO3), + ASPEED_PINCTRL_FUNC(MDIO4), + ASPEED_PINCTRL_FUNC(NCTS1), + ASPEED_PINCTRL_FUNC(NCTS2), + ASPEED_PINCTRL_FUNC(NCTS3), + ASPEED_PINCTRL_FUNC(NCTS4), + ASPEED_PINCTRL_FUNC(NDCD1), + ASPEED_PINCTRL_FUNC(NDCD2), + ASPEED_PINCTRL_FUNC(NDCD3), + ASPEED_PINCTRL_FUNC(NDCD4), + ASPEED_PINCTRL_FUNC(NDSR1), + ASPEED_PINCTRL_FUNC(NDSR2), + ASPEED_PINCTRL_FUNC(NDSR3), + ASPEED_PINCTRL_FUNC(NDSR4), + ASPEED_PINCTRL_FUNC(NDTR1), + ASPEED_PINCTRL_FUNC(NDTR2), + ASPEED_PINCTRL_FUNC(NDTR3), + ASPEED_PINCTRL_FUNC(NDTR4), + ASPEED_PINCTRL_FUNC(NRI1), + ASPEED_PINCTRL_FUNC(NRI2), + ASPEED_PINCTRL_FUNC(NRI3), + ASPEED_PINCTRL_FUNC(NRI4), + ASPEED_PINCTRL_FUNC(NRTS1), + ASPEED_PINCTRL_FUNC(NRTS2), + ASPEED_PINCTRL_FUNC(NRTS3), + ASPEED_PINCTRL_FUNC(NRTS4), + ASPEED_PINCTRL_FUNC(OSCCLK), + ASPEED_PINCTRL_FUNC(PEWAKE), + ASPEED_PINCTRL_FUNC(PWM0), + ASPEED_PINCTRL_FUNC(PWM1), + ASPEED_PINCTRL_FUNC(PWM10), + ASPEED_PINCTRL_FUNC(PWM11), + ASPEED_PINCTRL_FUNC(PWM12), + ASPEED_PINCTRL_FUNC(PWM13), + ASPEED_PINCTRL_FUNC(PWM14), + ASPEED_PINCTRL_FUNC(PWM15), + ASPEED_PINCTRL_FUNC(PWM2), + ASPEED_PINCTRL_FUNC(PWM3), + ASPEED_PINCTRL_FUNC(PWM4), + ASPEED_PINCTRL_FUNC(PWM5), + ASPEED_PINCTRL_FUNC(PWM6), + ASPEED_PINCTRL_FUNC(PWM7), + ASPEED_PINCTRL_FUNC(PWM8), + ASPEED_PINCTRL_FUNC(PWM9), + ASPEED_PINCTRL_FUNC(RGMII1), + ASPEED_PINCTRL_FUNC(RGMII2), + ASPEED_PINCTRL_FUNC(RGMII3), + ASPEED_PINCTRL_FUNC(RGMII4), + ASPEED_PINCTRL_FUNC(RMII1), + ASPEED_PINCTRL_FUNC(RMII2), + ASPEED_PINCTRL_FUNC(RMII3), + ASPEED_PINCTRL_FUNC(RMII4), + ASPEED_PINCTRL_FUNC(RXD1), + ASPEED_PINCTRL_FUNC(RXD2), + ASPEED_PINCTRL_FUNC(RXD3), + ASPEED_PINCTRL_FUNC(RXD4), + ASPEED_PINCTRL_FUNC(SALT1), + ASPEED_PINCTRL_FUNC(SALT10), + ASPEED_PINCTRL_FUNC(SALT11), + ASPEED_PINCTRL_FUNC(SALT12), + ASPEED_PINCTRL_FUNC(SALT13), + ASPEED_PINCTRL_FUNC(SALT14), + ASPEED_PINCTRL_FUNC(SALT15), + ASPEED_PINCTRL_FUNC(SALT16), + ASPEED_PINCTRL_FUNC(SALT2), + ASPEED_PINCTRL_FUNC(SALT3), + ASPEED_PINCTRL_FUNC(SALT4), + ASPEED_PINCTRL_FUNC(SALT5), + ASPEED_PINCTRL_FUNC(SALT6), + ASPEED_PINCTRL_FUNC(SALT7), + ASPEED_PINCTRL_FUNC(SALT8), + ASPEED_PINCTRL_FUNC(SALT9), + ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SD2), + ASPEED_PINCTRL_FUNC(SGPM1), + ASPEED_PINCTRL_FUNC(SGPS1), + ASPEED_PINCTRL_FUNC(SIOONCTRL), + ASPEED_PINCTRL_FUNC(SIOPBI), + ASPEED_PINCTRL_FUNC(SIOPBO), + ASPEED_PINCTRL_FUNC(SIOPWREQ), + ASPEED_PINCTRL_FUNC(SIOPWRGD), + ASPEED_PINCTRL_FUNC(SIOS3), + ASPEED_PINCTRL_FUNC(SIOS5), + ASPEED_PINCTRL_FUNC(SIOSCI), + ASPEED_PINCTRL_FUNC(SPI1), + ASPEED_PINCTRL_FUNC(SPI1ABR), + ASPEED_PINCTRL_FUNC(SPI1CS1), + ASPEED_PINCTRL_FUNC(SPI1WP), + ASPEED_PINCTRL_FUNC(SPI2), + ASPEED_PINCTRL_FUNC(SPI2CS1), + ASPEED_PINCTRL_FUNC(SPI2CS2), + ASPEED_PINCTRL_FUNC(TACH0), + ASPEED_PINCTRL_FUNC(TACH1), + ASPEED_PINCTRL_FUNC(TACH10), + ASPEED_PINCTRL_FUNC(TACH11), + ASPEED_PINCTRL_FUNC(TACH12), + ASPEED_PINCTRL_FUNC(TACH13), + ASPEED_PINCTRL_FUNC(TACH14), + ASPEED_PINCTRL_FUNC(TACH15), + ASPEED_PINCTRL_FUNC(TACH2), + ASPEED_PINCTRL_FUNC(TACH3), + ASPEED_PINCTRL_FUNC(TACH4), + ASPEED_PINCTRL_FUNC(TACH5), + ASPEED_PINCTRL_FUNC(TACH6), + ASPEED_PINCTRL_FUNC(TACH7), + ASPEED_PINCTRL_FUNC(TACH8), + ASPEED_PINCTRL_FUNC(TACH9), + ASPEED_PINCTRL_FUNC(THRU0), + ASPEED_PINCTRL_FUNC(THRU1), + ASPEED_PINCTRL_FUNC(THRU2), + ASPEED_PINCTRL_FUNC(THRU3), + ASPEED_PINCTRL_FUNC(TXD1), + ASPEED_PINCTRL_FUNC(TXD2), + ASPEED_PINCTRL_FUNC(TXD3), + ASPEED_PINCTRL_FUNC(TXD4), + ASPEED_PINCTRL_FUNC(UART10), + ASPEED_PINCTRL_FUNC(UART11), + ASPEED_PINCTRL_FUNC(UART12), + ASPEED_PINCTRL_FUNC(UART13), + ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(UART7), + ASPEED_PINCTRL_FUNC(UART8), + ASPEED_PINCTRL_FUNC(UART9), + ASPEED_PINCTRL_FUNC(USB11BHID), + ASPEED_PINCTRL_FUNC(USB2AD), + ASPEED_PINCTRL_FUNC(USB2ADP), + ASPEED_PINCTRL_FUNC(USB2AH), + ASPEED_PINCTRL_FUNC(USB2AHP), + ASPEED_PINCTRL_FUNC(USB2BD), + ASPEED_PINCTRL_FUNC(USB2BH), + ASPEED_PINCTRL_FUNC(VB), + ASPEED_PINCTRL_FUNC(VGAHS), + ASPEED_PINCTRL_FUNC(VGAVS), + ASPEED_PINCTRL_FUNC(WDTRST1), + ASPEED_PINCTRL_FUNC(WDTRST2), + ASPEED_PINCTRL_FUNC(WDTRST3), + ASPEED_PINCTRL_FUNC(WDTRST4), +}; + +static struct aspeed_pin_config aspeed_g6_configs[] = { + /* GPIOB7 */ + ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15), + /* GPIOB6 */ + ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14), + /* GPIOB5 */ + ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13), + /* GPIOB4 */ + ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12), + /* GPIOB3 */ + ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11), + /* GPIOB2 */ + ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10), + /* GPIOB1 */ + ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9), + /* GPIOB0 */ + ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8), + + /* GPIOH3 */ + ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27), + /* GPIOH2 */ + ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26), + /* GPIOH1 */ + ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25), + /* GPIOH0 */ + ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24), + + /* GPIOL7 */ + ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31), + /* GPIOL6 */ + ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30), + /* GPIOL5 */ + ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29), + /* GPIOL4 */ + ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28), + + /* GPIOJ7 */ + ASPEED_PULL_UP_PINCONF(D19, SCU618, 15), + /* GPIOJ6 */ + ASPEED_PULL_UP_PINCONF(C20, SCU618, 14), + /* GPIOJ5 */ + ASPEED_PULL_UP_PINCONF(A19, SCU618, 13), + /* GPIOJ4 */ + ASPEED_PULL_UP_PINCONF(C19, SCU618, 12), + /* GPIOJ3 */ + ASPEED_PULL_UP_PINCONF(D20, SCU618, 11), + /* GPIOJ2 */ + ASPEED_PULL_UP_PINCONF(E19, SCU618, 10), + /* GPIOJ1 */ + ASPEED_PULL_UP_PINCONF(A20, SCU618, 9), + /* GPIOJ0 */ + ASPEED_PULL_UP_PINCONF(B20, SCU618, 8), + + /* GPIOI7 */ + ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7), + /* GPIOI6 */ + ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6), + /* GPIOI5 */ + ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5), + /* GPIOI4 */ + ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4), + /* GPIOI3 */ + ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3), + /* GPIOI2 */ + ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2), + /* GPIOI1 */ + ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1), + /* GPIOI0 */ + ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0), + + /* GPIOP7 */ + ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31), + /* GPIOP6 */ + ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30), + /* GPIOP5 */ + ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29), + /* GPIOP4 */ + ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28), + /* GPIOP3 */ + ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27), + /* GPIOP2 */ + ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26), + /* GPIOP1 */ + ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25), + /* GPIOP0 */ + ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24), + + /* GPIOO7 */ + ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23), + /* GPIOO6 */ + ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22), + /* GPIOO5 */ + ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21), + /* GPIOO4 */ + ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20), + /* GPIOO3 */ + ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19), + /* GPIOO2 */ + ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18), + /* GPIOO1 */ + ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17), + /* GPIOO0 */ + ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16), + + /* GPION7 */ + ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15), + /* GPION6 */ + ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14), + /* GPION5 */ + ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13), + /* GPION4 */ + ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12), + /* GPION3 */ + ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11), + /* GPION2 */ + ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10), + /* GPION1 */ + ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9), + /* GPION0 */ + ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8), + + /* GPIOM7 */ + ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7), + /* GPIOM6 */ + ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6), + /* GPIOM5 */ + ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5), + /* GPIOM4 */ + ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4), + /* GPIOM3 */ + ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3), + /* GPIOM2 */ + ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2), + /* GPIOM1 */ + ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1), + /* GPIOM0 */ + ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0), + + /* GPIOS7 */ + ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23), + /* GPIOS6 */ + ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22), + /* GPIOS5 */ + ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21), + /* GPIOS4 */ + ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20), + /* GPIOS3*/ + ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19), + /* GPIOS2 */ + ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18), + /* GPIOS1 */ + ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17), + /* GPIOS0 */ + ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16), + + /* GPIOR7 */ + ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15), + /* GPIOR6 */ + ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14), + /* GPIOR5 */ + ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13), + /* GPIOR4 */ + ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12), + /* GPIOR3*/ + ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11), + /* GPIOR2 */ + ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10), + /* GPIOR1 */ + ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9), + /* GPIOR0 */ + ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8), + + /* GPIOX7 */ + ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31), + /* GPIOX6 */ + ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30), + /* GPIOX5 */ + ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29), + /* GPIOX4 */ + ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28), + /* GPIOX3*/ + ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27), + /* GPIOX2 */ + ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26), + /* GPIOX1 */ + ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25), + /* GPIOX0 */ + ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24), + + /* GPIOV7 */ + ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15), + /* GPIOV6 */ + ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14), + /* GPIOV5 */ + ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13), + /* GPIOV4 */ + ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12), + /* GPIOV3*/ + ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11), + /* GPIOV2 */ + ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10), + /* GPIOV1 */ + ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9), + /* GPIOV0 */ + ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8), + + /* GPIOZ7 */ + ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15), + /* GPIOZ6 */ + ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14), + /* GPIOZ5 */ + ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13), + /* GPIOZ4 */ + ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12), + /* GPIOZ3*/ + ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11), + + /* GPIOZ1 */ + ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9), + /* GPIOZ0 */ + ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8), + + /* GPIOY6 */ + ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6), + /* GPIOY5 */ + ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5), + /* GPIOY4 */ + ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4), + /* GPIOY3 */ + ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3), + /* GPIOY2 */ + ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2), + /* GPIOY1 */ + ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1), + /* GPIOY0 */ + ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0), + + /* LAD3 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)}, + /* LAD2 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)}, + /* LAD1 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)}, + /* LAD0 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)}, + + /* MAC3 */ + { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)}, + { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)}, + /* MAC4 */ + { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)}, + { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)}, +}; + +/** + * Configure a pin's signal by applying an expression's descriptor state for + * all descriptors in the expression. + * + * @ctx: The pinmux context + * @expr: The expression associated with the function whose signal is to be + * configured + * @enable: true to enable an function's signal through a pin's signal + * expression, false to disable the function's signal + * + * Return: 0 if the expression is configured as requested and a negative error + * code otherwise + */ +static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx, + const struct aspeed_sig_expr *expr, + bool enable) +{ + int ret; + int i; + + for (i = 0; i < expr->ndescs; i++) { + const struct aspeed_sig_desc *desc = &expr->descs[i]; + u32 pattern = enable ? desc->enable : desc->disable; + u32 val = (pattern << __ffs(desc->mask)); + bool is_strap; + + if (!ctx->maps[desc->ip]) + return -ENODEV; + + WARN_ON(desc->ip != ASPEED_IP_SCU); + is_strap = desc->reg == SCU500 || desc->reg == SCU510; + + if (is_strap) { + /* + * The AST2600 has write protection mask registers for + * the hardware strapping in SCU508 and SCU518. Assume + * that if the platform doesn't want the strapping + * values changed that it has set the write mask. + * + * The strapping registers implement write-1-clear + * behaviour. SCU500 is paired with clear writes on + * SCU504, likewise SCU510 is paired with SCU514. + */ + u32 clear = ~val & desc->mask; + u32 w1c = desc->reg + 4; + + if (clear) + ret = regmap_update_bits(ctx->maps[desc->ip], + w1c, desc->mask, + clear); + } + + ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, + desc->mask, val); + if (ret) + return ret; + } + + ret = aspeed_sig_expr_eval(ctx, expr, enable); + if (ret < 0) + return ret; + + if (!ret) + return -EPERM; + return 0; +} + +static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)}, + { PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)}, + { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)}, +}; + +static const struct aspeed_pinmux_ops aspeed_g5_ops = { + .set = aspeed_g6_sig_expr_set, +}; + +static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = { + .pins = aspeed_g6_pins, + .npins = ARRAY_SIZE(aspeed_g6_pins), + .pinmux = { + .ops = &aspeed_g5_ops, + .groups = aspeed_g6_groups, + .ngroups = ARRAY_SIZE(aspeed_g6_groups), + .functions = aspeed_g6_functions, + .nfunctions = ARRAY_SIZE(aspeed_g6_functions), + }, + .configs = aspeed_g6_configs, + .nconfigs = ARRAY_SIZE(aspeed_g6_configs), + .confmaps = aspeed_g6_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map), +}; + +static const struct pinmux_ops aspeed_g6_pinmux_ops = { + .get_functions_count = aspeed_pinmux_get_fn_count, + .get_function_name = aspeed_pinmux_get_fn_name, + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, + .strict = true, +}; + +static const struct pinctrl_ops aspeed_g6_pinctrl_ops = { + .get_groups_count = aspeed_pinctrl_get_groups_count, + .get_group_name = aspeed_pinctrl_get_group_name, + .get_group_pins = aspeed_pinctrl_get_group_pins, + .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +static const struct pinconf_ops aspeed_g6_conf_ops = { + .is_generic = true, + .pin_config_get = aspeed_pin_config_get, + .pin_config_set = aspeed_pin_config_set, + .pin_config_group_get = aspeed_pin_config_group_get, + .pin_config_group_set = aspeed_pin_config_group_set, +}; + +static struct pinctrl_desc aspeed_g6_pinctrl_desc = { + .name = "aspeed-g6-pinctrl", + .pins = aspeed_g6_pins, + .npins = ARRAY_SIZE(aspeed_g6_pins), + .pctlops = &aspeed_g6_pinctrl_ops, + .pmxops = &aspeed_g6_pinmux_ops, + .confops = &aspeed_g6_conf_ops, +}; + +static int aspeed_g6_pinctrl_probe(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aspeed_g6_pins); i++) + aspeed_g6_pins[i].number = i; + + return aspeed_pinctrl_probe(pdev, &aspeed_g6_pinctrl_desc, + &aspeed_g6_pinctrl_data); +} + +static const struct of_device_id aspeed_g6_pinctrl_of_match[] = { + { .compatible = "aspeed,ast2600-pinctrl", }, + { }, +}; + +static struct platform_driver aspeed_g6_pinctrl_driver = { + .probe = aspeed_g6_pinctrl_probe, + .driver = { + .name = "aspeed-g6-pinctrl", + .of_match_table = aspeed_g6_pinctrl_of_match, + }, +}; + +static int aspeed_g6_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g6_pinctrl_driver); +} + +arch_initcall(aspeed_g6_pinctrl_init); diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 54933665b5f8..53f3f8aec695 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -76,6 +76,9 @@ static int aspeed_sig_expr_enable(struct aspeed_pinmux_data *ctx, { int ret; + pr_debug("Enabling signal %s for %s\n", expr->signal, + expr->function); + ret = aspeed_sig_expr_eval(ctx, expr, true); if (ret < 0) return ret; @@ -91,6 +94,9 @@ static int aspeed_sig_expr_disable(struct aspeed_pinmux_data *ctx, { int ret; + pr_debug("Disabling signal %s for %s\n", expr->signal, + expr->function); + ret = aspeed_sig_expr_eval(ctx, expr, true); if (ret < 0) return ret; @@ -229,7 +235,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, const struct aspeed_sig_expr **funcs; const struct aspeed_sig_expr ***prios; - pr_debug("Muxing pin %d for %s\n", pin, pfunc->name); + pr_debug("Muxing pin %s for %s\n", pdesc->name, pfunc->name); if (!pdesc) return -EINVAL; @@ -269,6 +275,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, ret = aspeed_sig_expr_enable(&pdata->pinmux, expr); if (ret) return ret; + + pr_debug("Muxed pin %s as %s for %s\n", pdesc->name, expr->signal, + expr->function); } return 0; @@ -317,6 +326,8 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, if (!prios) return -ENXIO; + pr_debug("Muxing pin %s for GPIO\n", pdesc->name); + /* Disable any functions of higher priority than GPIO */ while ((funcs = *prios)) { if (aspeed_gpio_in_exprs(funcs)) @@ -346,14 +357,22 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, * lowest-priority signal type. As such it has no associated * expression. */ - if (!expr) + if (!expr) { + pr_debug("Muxed pin %s as GPIO\n", pdesc->name); return 0; + } /* * If GPIO is not the lowest priority signal type, assume there is only * one expression defined to enable the GPIO function */ - return aspeed_sig_expr_enable(&pdata->pinmux, expr); + ret = aspeed_sig_expr_enable(&pdata->pinmux, expr); + if (ret) + return ret; + + pr_debug("Muxed pin %s as %s\n", pdesc->name, expr->signal); + + return 0; } int aspeed_pinctrl_probe(struct platform_device *pdev, @@ -411,49 +430,21 @@ static inline const struct aspeed_pin_config *find_pinconf_config( return NULL; } -/* - * Aspeed pin configuration description. - * - * @param: pinconf configuration parameter - * @arg: The supported argument for @param, or -1 if any value is supported - * @val: The register value to write to configure @arg for @param - * - * The map is to be used in conjunction with the configuration array supplied - * by the driver implementation. - */ -struct aspeed_pin_config_map { - enum pin_config_param param; - s32 arg; - u32 val; -}; - enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL }; -/* Aspeed consistently both: - * - * 1. Defines "disable bits" for internal pull-downs - * 2. Uses 8mA or 16mA drive strengths - */ -static const struct aspeed_pin_config_map pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1 }, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0 }, - { PIN_CONFIG_BIAS_DISABLE, -1, 1 }, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0 }, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1 }, -}; - static const struct aspeed_pin_config_map *find_pinconf_map( + const struct aspeed_pinctrl_data *pdata, enum pin_config_param param, enum aspeed_pin_config_map_type type, s64 value) { int i; - for (i = 0; i < ARRAY_SIZE(pin_config_map); i++) { + for (i = 0; i < pdata->nconfmaps; i++) { const struct aspeed_pin_config_map *elem; bool match; - elem = &pin_config_map[i]; + elem = &pdata->confmaps[i]; switch (type) { case MAP_TYPE_ARG: @@ -491,8 +482,8 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, if (rc < 0) return rc; - pmap = find_pinconf_map(param, MAP_TYPE_VAL, - (val & BIT(pconf->bit)) >> pconf->bit); + pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL, + (val & pconf->mask) >> __ffs(pconf->mask)); if (!pmap) return -EINVAL; @@ -535,22 +526,22 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, if (!pconf) return -ENOTSUPP; - pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg); + pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg); if (WARN_ON(!pmap)) return -EINVAL; - val = pmap->val << pconf->bit; + val = pmap->val << __ffs(pconf->mask); rc = regmap_update_bits(pdata->scu, pconf->reg, - BIT(pconf->bit), val); + pmap->mask, val); if (rc < 0) return rc; - pr_debug("%s: Set SCU%02X[%d]=%d for param %d(=%d) on pin %d\n", - __func__, pconf->reg, pconf->bit, pmap->val, - param, arg, offset); + pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n", + __func__, pconf->reg, __ffs(pconf->mask), + pmap->val, param, arg, offset); } return 0; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index a5d83986f32e..4dcde3bc29c8 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -24,8 +24,7 @@ struct aspeed_pin_config { enum pin_config_param param; unsigned int pins[2]; unsigned int reg; - u8 bit; - u8 value; + u32 mask; }; #define ASPEED_PINCTRL_PIN(name_) \ @@ -35,6 +34,38 @@ struct aspeed_pin_config { .drv_data = (void *) &(PIN_SYM(name_)) \ } +#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \ + .param = param_, \ + .pins = {pin0_, pin1_}, \ + .reg = reg_, \ + .mask = BIT_MASK(bit_) \ +} + +#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) + +#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) +/* + * Aspeed pin configuration description. + * + * @param: pinconf configuration parameter + * @arg: The supported argument for @param, or -1 if any value is supported + * @val: The register value to write to configure @arg for @param + * @mask: The bitfield mask for @val + * + * The map is to be used in conjunction with the configuration array supplied + * by the driver implementation. + */ +struct aspeed_pin_config_map { + enum pin_config_param param; + s32 arg; + u32 val; + u32 mask; +}; + struct aspeed_pinctrl_data { struct regmap *scu; @@ -45,6 +76,9 @@ struct aspeed_pinctrl_data { const unsigned int nconfigs; struct aspeed_pinmux_data pinmux; + + const struct aspeed_pin_config_map *confmaps; + const unsigned int nconfmaps; }; /* Aspeed pinctrl helpers */ diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index db3457c86f48..f86739e800c3 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -162,10 +162,11 @@ * * Enabling lower priority signals requires higher priority signals be * disabled * - * * A function represents a set of signals; functions are distinct if their - * sets of signals are not equal + * * A function represents a set of signals; functions are distinct if they + * do not share a subset of signals (and may be distinct if they are a + * strict subset). * - * * Signals participate in one or more functions + * * Signals participate in one or more functions or groups * * * A function is described by an expression of one or more signal * descriptors, which compare bit values in a register @@ -507,20 +508,21 @@ struct aspeed_pin_desc { * @idx: The bit index in the register */ #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) +#define SIG_DESC_CLEAR(reg, idx) { ASPEED_IP_SCU, reg, BIT_MASK(idx), 0, 0 } -#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func -#define SIG_DESC_LIST_DECL(sig, func, ...) \ - static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \ +#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group +#define SIG_DESC_LIST_DECL(sig, group, ...) \ + static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \ { __VA_ARGS__ } -#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func -#define SIG_EXPR_DECL_(sig, func) \ - static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \ +#define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group +#define SIG_EXPR_DECL_(sig, group, func) \ + static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \ { \ .signal = #sig, \ .function = #func, \ - .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \ - .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \ + .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \ + .descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \ } /** @@ -533,16 +535,16 @@ struct aspeed_pin_desc { * * For example, the following declares the ROMD8 signal for the ROM16 function: * - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6)); * * And with multiple signal descriptors: * - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); */ -#define SIG_EXPR_DECL(sig, func, ...) \ - SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ - SIG_EXPR_DECL_(sig, func) +#define SIG_EXPR_DECL(sig, group, func, ...) \ + SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \ + SIG_EXPR_DECL_(sig, group, func) /** * Declare a pointer to a signal expression @@ -550,9 +552,9 @@ struct aspeed_pin_desc { * @sig: The macro symbol name for the signal (subjected to token pasting) * @func: The macro symbol name for the function (subjected to token pasting) */ -#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func)) +#define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group)) -#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig +#define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group /** * Declare a signal expression list for reference in a struct aspeed_pin_prio. @@ -563,80 +565,101 @@ struct aspeed_pin_desc { * For example, the 16-bit ROM bus can be enabled by one of two possible signal * expressions: * - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), * SIG_EXPR_PTR(ROMD8, ROM16S)); */ -#define SIG_EXPR_LIST_DECL(sig, ...) \ - static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \ +#define SIG_EXPR_LIST_DECL(sig, group, ...) \ + static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\ { __VA_ARGS__, NULL } +#define stringify(x) #x +#define istringify(x) stringify(x) + +/** + * Create an expression symbol alias from (signal, group) to (pin, signal). + * + * @pin: The pin number + * @sig: The signal name + * @group: The name of the group of which the pin is a member that is + * associated with the function's signal + * + * Using an alias in this way enables detection of copy/paste errors (defining + * the signal for a group multiple times) whilst enabling multiple pin groups + * to exist for a signal without intrusive side-effects on defining the list of + * signals available on a pin. + */ +#define SIG_EXPR_LIST_ALIAS(pin, sig, group) \ + static const struct aspeed_sig_expr *\ + SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \ + __attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group))))) + /** * A short-hand macro for declaring a function expression and an expression - * list with a single function. + * list with a single expression (SE) and a single group (SG) of pins. * - * @func: A macro symbol name for the function (is subjected to token pasting) + * @pin: The pin the signal will be routed to + * @sig: The signal that will be routed to the pin for the function + * @func: A macro symbol name for the function * @...: Function descriptors that define the function expression * * For example, signal NCTS6 participates in its own function with one group: * - * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); + * SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); */ -#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \ +#define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \ SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ - SIG_EXPR_DECL_(sig, func); \ - SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func)) + SIG_EXPR_DECL_(sig, func, func); \ + SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \ + SIG_EXPR_LIST_ALIAS(pin, sig, func) + +/** + * Similar to the above, but for pins with a single expression (SE) and + * multiple groups (MG) of pins. + * + * @pin: The pin the signal will be routed to + * @sig: The signal that will be routed to the pin for the function + * @group: The name of the function's pin group in which the pin participates + * @func: A macro symbol name for the function + * @...: Function descriptors that define the function expression + */ +#define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \ + SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \ + SIG_EXPR_DECL_(sig, group, func); \ + SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \ + SIG_EXPR_LIST_ALIAS(pin, sig, group) -#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \ - SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1)) +/** + * Similar to the above, but for pins with a dual expressions (DE) and + * and a single group (SG) of pins. + * + * @pin: The pin the signal will be routed to + * @sig: The signal that will be routed to the pin for the function + * @group: The name of the function's pin group in which the pin participates + * @func: A macro symbol name for the function + * @...: Function descriptors that define the function expression + */ +#define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \ + SIG_EXPR_LIST_DECL(sig, f0, \ + SIG_EXPR_PTR(sig, f0), \ + SIG_EXPR_PTR(sig, f1)); \ + SIG_EXPR_LIST_ALIAS(pin, sig, f0) -#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0]) +#define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group) #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) #define PIN_SYM(pin) pin_ ## pin -#define MS_PIN_DECL_(pin, ...) \ +#define PIN_DECL_(pin, ...) \ static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \ { __VA_ARGS__, NULL }; \ static const struct aspeed_pin_desc PIN_SYM(pin) = \ { #pin, PIN_EXPRS_PTR(pin) } /** - * Declare a multi-signal pin - * - * @pin: The pin number - * @other: Macro name for "other" functionality (subjected to stringification) - * @high: Macro name for the highest priority signal functions - * @low: Macro name for the low signal functions - * - * For example: - * - * #define A8 56 - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), - * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); - * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), - * SIG_EXPR_PTR(ROMD8, ROM16S)); - * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); - * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); - */ -#define MS_PIN_DECL(pin, other, high, low) \ - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ - MS_PIN_DECL_(pin, \ - SIG_EXPR_LIST_PTR(high), \ - SIG_EXPR_LIST_PTR(low), \ - SIG_EXPR_LIST_PTR(other)) - -#define PIN_GROUP_SYM(func) pins_ ## func -#define FUNC_GROUP_SYM(func) groups_ ## func -#define FUNC_GROUP_DECL(func, ...) \ - static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \ - static const char *FUNC_GROUP_SYM(func)[] = { #func } - -/** * Declare a single signal pin * * @pin: The pin number @@ -647,11 +670,12 @@ struct aspeed_pin_desc { * * #define E3 80 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); - * SS_PIN_DECL(E3, GPIOK0, SCL5); + * PIN_DECL_1(E3, GPIOK0, SCL5); */ -#define SS_PIN_DECL(pin, other, sig) \ - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)) +#define PIN_DECL_1(pin, other, sig) \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \ + SIG_EXPR_LIST_PTR(pin, other)) /** * Single signal, single function pin declaration @@ -666,14 +690,65 @@ struct aspeed_pin_desc { * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); */ #define SSSF_PIN_DECL(pin, other, sig, ...) \ - SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \ - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \ + SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \ + SIG_EXPR_LIST_PTR(pin, other)); \ FUNC_GROUP_DECL(sig, pin) +/** + * Declare a two-signal pin + * + * @pin: The pin number + * @other: Macro name for "other" functionality (subjected to stringification) + * @high: Macro name for the highest priority signal functions + * @low: Macro name for the low signal functions + * + * For example: + * + * #define A8 56 + * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); + * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), + * SIG_EXPR_PTR(ROMD8, ROM16S)); + * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); + * PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6); + */ +#define PIN_DECL_2(pin, other, high, low) \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, \ + SIG_EXPR_LIST_PTR(pin, high), \ + SIG_EXPR_LIST_PTR(pin, low), \ + SIG_EXPR_LIST_PTR(pin, other)) + +#define PIN_DECL_3(pin, other, high, medium, low) \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, \ + SIG_EXPR_LIST_PTR(pin, high), \ + SIG_EXPR_LIST_PTR(pin, medium), \ + SIG_EXPR_LIST_PTR(pin, low), \ + SIG_EXPR_LIST_PTR(pin, other)) + +#define GROUP_SYM(group) group_pins_ ## group +#define GROUP_DECL(group, ...) \ + static const int GROUP_SYM(group)[] = { __VA_ARGS__ } + +#define FUNC_SYM(func) func_groups_ ## func +#define FUNC_DECL_(func, ...) \ + static const char *FUNC_SYM(func)[] = { __VA_ARGS__ } + +#define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group) +#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two) +#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three) + +#define FUNC_GROUP_DECL(func, ...) \ + GROUP_DECL(func, __VA_ARGS__); \ + FUNC_DECL_(func, #func) + #define GPIO_PIN_DECL(pin, gpio) \ - SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \ - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) + SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \ + PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio)) struct aspeed_pin_group { const char *name; @@ -683,8 +758,8 @@ struct aspeed_pin_group { #define ASPEED_PINCTRL_GROUP(name_) { \ .name = #name_, \ - .pins = &(PIN_GROUP_SYM(name_))[0], \ - .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \ + .pins = &(GROUP_SYM(name_))[0], \ + .npins = ARRAY_SIZE(GROUP_SYM(name_)), \ } struct aspeed_pin_function { @@ -695,8 +770,8 @@ struct aspeed_pin_function { #define ASPEED_PINCTRL_FUNC(name_, ...) { \ .name = #name_, \ - .groups = &FUNC_GROUP_SYM(name_)[0], \ - .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \ + .groups = &FUNC_SYM(name_)[0], \ + .ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \ } struct aspeed_pinmux_data; diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index e5a112a8e067..297b7b5fcb28 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1455,6 +1455,20 @@ static void byt_gpio_irq_handler(struct irq_desc *desc) chip->irq_eoi(data); } +static void byt_init_irq_valid_mask(struct gpio_chip *chip, + unsigned long *valid_mask, + unsigned int ngpios) +{ + /* + * FIXME: currently the valid_mask is filled in as part of + * initializing the irq_chip below in byt_gpio_irq_init_hw(). + * when converting this driver to the new way of passing the + * gpio_irq_chip along when adding the gpio_chip, move the + * mask initialization into this callback instead. Right now + * this callback is here to make sure the mask gets allocated. + */ +} + static void byt_gpio_irq_init_hw(struct byt_gpio *vg) { struct gpio_chip *gc = &vg->chip; @@ -1525,7 +1539,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) gc->can_sleep = false; gc->parent = &vg->pdev->dev; gc->ngpio = vg->soc_data->npins; - gc->irq.need_valid_mask = true; + gc->irq.init_valid_mask = byt_init_irq_valid_mask; #ifdef CONFIG_PM_SLEEP vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio, diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 8dfaf8e8c3a0..cb91e213e829 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1531,6 +1531,30 @@ static const struct dmi_system_id chv_no_valid_mask[] = { {} }; +static void chv_init_irq_valid_mask(struct gpio_chip *chip, + unsigned long *valid_mask, + unsigned int ngpios) +{ + struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + const struct chv_community *community = pctrl->community; + int i; + + /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ + for (i = 0; i < community->npins; i++) { + const struct pinctrl_pin_desc *desc; + u32 intsel; + + desc = &community->pins[i]; + + intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); + intsel &= CHV_PADCTRL0_INTSEL_MASK; + intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; + + if (intsel >= community->nirqs) + clear_bit(i, valid_mask); + } +} + static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) { const struct chv_gpio_pinrange *range; @@ -1545,7 +1569,8 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) chip->label = dev_name(pctrl->dev); chip->parent = pctrl->dev; chip->base = -1; - chip->irq.need_valid_mask = need_valid_mask; + if (need_valid_mask) + chip->irq.init_valid_mask = chv_init_irq_valid_mask; ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); if (ret) { @@ -1564,21 +1589,6 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } } - /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ - for (i = 0; i < community->npins; i++) { - const struct pinctrl_pin_desc *desc; - u32 intsel; - - desc = &community->pins[i]; - - intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0)); - intsel &= CHV_PADCTRL0_INTSEL_MASK; - intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; - - if (need_valid_mask && intsel >= community->nirqs) - clear_bit(desc->number, chip->irq.valid_mask); - } - /* * The same set of machines in chv_no_valid_mask[] have incorrectly * configured GPIOs that generate spurious interrupts so we use diff --git a/drivers/platform/x86/intel_int0002_vgpio.c b/drivers/platform/x86/intel_int0002_vgpio.c index 9ea1a2a19f86..97adebc622da 100644 --- a/drivers/platform/x86/intel_int0002_vgpio.c +++ b/drivers/platform/x86/intel_int0002_vgpio.c @@ -153,6 +153,13 @@ static const struct x86_cpu_id int0002_cpu_ids[] = { {} }; +static void int0002_init_irq_valid_mask(struct gpio_chip *chip, + unsigned long *valid_mask, + unsigned int ngpios) +{ + bitmap_clear(valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN); +} + static int int0002_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -185,7 +192,7 @@ static int int0002_probe(struct platform_device *pdev) chip->direction_output = int0002_gpio_direction_output; chip->base = -1; chip->ngpio = GPE0A_PME_B0_VIRT_GPIO_PIN + 1; - chip->irq.need_valid_mask = true; + chip->irq.init_valid_mask = int0002_init_irq_valid_mask; ret = devm_gpiochip_add_data(&pdev->dev, chip, NULL); if (ret) { @@ -193,8 +200,6 @@ static int int0002_probe(struct platform_device *pdev) return ret; } - bitmap_clear(chip->irq.valid_mask, 0, GPE0A_PME_B0_VIRT_GPIO_PIN); - /* * We manually request the irq here instead of passing a flow-handler * to gpiochip_set_chained_irqchip, because the irq is shared. diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 1154f7b1f4dd..2fe9c889a75a 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -125,6 +125,7 @@ static const struct of_device_id reset_simple_dt_ids[] = { .data = &reset_simple_active_low }, { .compatible = "aspeed,ast2400-lpc-reset" }, { .compatible = "aspeed,ast2500-lpc-reset" }, + { .compatible = "aspeed,ast2600-lpc-reset" }, { .compatible = "bitmain,bm1880-reset", .data = &reset_simple_active_low }, { /* sentinel */ }, diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index 323e177aa74d..78dd74c49ddb 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -5,6 +5,14 @@ config SOC_ASPEED def_bool y depends on ARCH_ASPEED || COMPILE_TEST +config ASPEED_BMC_MISC + bool "Miscellaneous ASPEED BMC interfaces" + depends on ARCH_ASPEED || COMPILE_TEST + default ARCH_ASPEED + help + Say yes to expose VGA and LPC scratch registers, and other + miscellaneous control interfaces specific to the ASPEED BMC SoCs + config ASPEED_LPC_CTRL depends on SOC_ASPEED && REGMAP && MFD_SYSCON tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control" diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile index b64be47f2b1f..e631b23d519b 100644 --- a/drivers/soc/aspeed/Makefile +++ b/drivers/soc/aspeed/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_ASPEED_BMC_MISC) += aspeed-bmc-misc.o obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o diff --git a/drivers/soc/aspeed/aspeed-bmc-misc.c b/drivers/soc/aspeed/aspeed-bmc-misc.c new file mode 100644 index 000000000000..314007bad74f --- /dev/null +++ b/drivers/soc/aspeed/aspeed-bmc-misc.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2018 IBM Corp. + +#include <linux/kobject.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> + +#define DEVICE_NAME "aspeed-bmc-misc" + +struct aspeed_bmc_ctrl { + const char *name; + u32 offset; + u32 mask; + u32 shift; + struct regmap *map; + struct kobj_attribute attr; +}; + +struct aspeed_bmc_misc { + struct device *dev; + struct regmap *map; + struct aspeed_bmc_ctrl *ctrls; + int nr_ctrls; +}; + +static int aspeed_bmc_misc_parse_dt_child(struct device_node *child, + struct aspeed_bmc_ctrl *ctrl) +{ + int rc; + + /* Example child: + * + * ilpc2ahb { + * offset = <0x80>; + * bit-mask = <0x1>; + * bit-shift = <6>; + * label = "foo"; + * } + */ + if (of_property_read_string(child, "label", &ctrl->name)) + ctrl->name = child->name; + + rc = of_property_read_u32(child, "offset", &ctrl->offset); + if (rc < 0) + return rc; + + rc = of_property_read_u32(child, "bit-mask", &ctrl->mask); + if (rc < 0) + return rc; + + rc = of_property_read_u32(child, "bit-shift", &ctrl->shift); + if (rc < 0) + return rc; + + ctrl->mask <<= ctrl->shift; + + return 0; +} + +static int aspeed_bmc_misc_parse_dt(struct aspeed_bmc_misc *bmc, + struct device_node *parent) +{ + struct aspeed_bmc_ctrl *ctrl; + struct device_node *child; + int rc; + + bmc->nr_ctrls = of_get_child_count(parent); + bmc->ctrls = devm_kcalloc(bmc->dev, bmc->nr_ctrls, sizeof(*bmc->ctrls), + GFP_KERNEL); + if (!bmc->ctrls) + return -ENOMEM; + + ctrl = bmc->ctrls; + for_each_child_of_node(parent, child) { + rc = aspeed_bmc_misc_parse_dt_child(child, ctrl++); + if (rc < 0) { + of_node_put(child); + return rc; + } + } + + return 0; +} + +static ssize_t aspeed_bmc_misc_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + struct aspeed_bmc_ctrl *ctrl; + unsigned int val; + int rc; + + ctrl = container_of(attr, struct aspeed_bmc_ctrl, attr); + rc = regmap_read(ctrl->map, ctrl->offset, &val); + if (rc) + return rc; + + val &= ctrl->mask; + val >>= ctrl->shift; + + return sprintf(buf, "%u\n", val); +} + +static ssize_t aspeed_bmc_misc_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t count) +{ + struct aspeed_bmc_ctrl *ctrl; + long val; + int rc; + + rc = kstrtol(buf, 0, &val); + if (rc) + return rc; + + ctrl = container_of(attr, struct aspeed_bmc_ctrl, attr); + val <<= ctrl->shift; + rc = regmap_update_bits(ctrl->map, ctrl->offset, ctrl->mask, val); + + return rc < 0 ? rc : count; +} + +static int aspeed_bmc_misc_add_sysfs_attr(struct aspeed_bmc_misc *bmc, + struct aspeed_bmc_ctrl *ctrl) +{ + ctrl->map = bmc->map; + + sysfs_attr_init(&ctrl->attr.attr); + ctrl->attr.attr.name = ctrl->name; + ctrl->attr.attr.mode = 0664; + ctrl->attr.show = aspeed_bmc_misc_show; + ctrl->attr.store = aspeed_bmc_misc_store; + + return sysfs_create_file(&bmc->dev->kobj, &ctrl->attr.attr); +} + +static int aspeed_bmc_misc_populate_sysfs(struct aspeed_bmc_misc *bmc) +{ + int rc; + int i; + + for (i = 0; i < bmc->nr_ctrls; i++) { + rc = aspeed_bmc_misc_add_sysfs_attr(bmc, &bmc->ctrls[i]); + if (rc < 0) + return rc; + } + + return 0; +} + +static int aspeed_bmc_misc_probe(struct platform_device *pdev) +{ + struct aspeed_bmc_misc *bmc; + int rc; + + bmc = devm_kzalloc(&pdev->dev, sizeof(*bmc), GFP_KERNEL); + if (!bmc) + return -ENOMEM; + + bmc->dev = &pdev->dev; + bmc->map = syscon_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(bmc->map)) + return PTR_ERR(bmc->map); + + rc = aspeed_bmc_misc_parse_dt(bmc, pdev->dev.of_node); + if (rc < 0) + return rc; + + return aspeed_bmc_misc_populate_sysfs(bmc); +} + +static const struct of_device_id aspeed_bmc_misc_match[] = { + { .compatible = "aspeed,bmc-misc" }, + { }, +}; + +static struct platform_driver aspeed_bmc_misc = { + .driver = { + .name = DEVICE_NAME, + .of_match_table = aspeed_bmc_misc_match, + }, + .probe = aspeed_bmc_misc_probe, +}; + +module_platform_driver(aspeed_bmc_misc); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Andrew Jeffery <andrew@aj.id.au>"); diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index 01ed21e8bfee..f4ac14c40518 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -4,6 +4,7 @@ */ #include <linux/clk.h> +#include <linux/log2.h> #include <linux/mfd/syscon.h> #include <linux/miscdevice.h> #include <linux/mm.h> @@ -241,6 +242,18 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev) lpc_ctrl->mem_size = resource_size(&resm); lpc_ctrl->mem_base = resm.start; + + if (!is_power_of_2(lpc_ctrl->mem_size)) { + dev_err(dev, "Reserved memory size must be a power of 2, got %zu\n", + lpc_ctrl->mem_size); + return -EINVAL; + } + + if (!IS_ALIGNED(lpc_ctrl->mem_base, lpc_ctrl->mem_size)) { + dev_err(dev, "Reserved memory must be naturally aligned for size %zu\n", + lpc_ctrl->mem_size); + return -EINVAL; + } } lpc_ctrl->regmap = syscon_node_to_regmap( @@ -291,6 +304,7 @@ static int aspeed_lpc_ctrl_remove(struct platform_device *pdev) static const struct of_device_id aspeed_lpc_ctrl_match[] = { { .compatible = "aspeed,ast2400-lpc-ctrl" }, { .compatible = "aspeed,ast2500-lpc-ctrl" }, + { .compatible = "aspeed,ast2600-lpc-ctrl" }, { }, }; diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c index 48f7ac238861..c7b4ac066b40 100644 --- a/drivers/soc/aspeed/aspeed-lpc-snoop.c +++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c @@ -325,6 +325,8 @@ static const struct of_device_id aspeed_lpc_snoop_match[] = { .data = &ast2400_model_data }, { .compatible = "aspeed,ast2500-lpc-snoop", .data = &ast2500_model_data }, + { .compatible = "aspeed,ast2600-lpc-snoop", + .data = &ast2500_model_data }, { }, }; diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 3a1d8f1170de..6ee514fd0920 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -433,6 +433,16 @@ config SPI_MT7621 help This selects a driver for the MediaTek MT7621 SPI Controller. +config SPI_NPCM_FIU + tristate "Nuvoton NPCM FLASH Interface Unit" + depends on ARCH_NPCM || COMPILE_TEST + depends on OF && HAS_IOMEM + help + This enables support for the Flash Interface Unit SPI controller + in master mode. + This driver does not support generic SPI. The implementation only + supports spi-mem interface. + config SPI_NPCM_PSPI tristate "Nuvoton NPCM PSPI Controller" depends on ARCH_NPCM || COMPILE_TEST diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 63dcab552bcb..adbebee93a75 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o obj-$(CONFIG_SPI_MXIC) += spi-mxic.o obj-$(CONFIG_SPI_MXS) += spi-mxs.o +obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c new file mode 100644 index 000000000000..3ea1ec68147e --- /dev/null +++ b/drivers/spi/spi-npcm-fiu.c @@ -0,0 +1,771 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019 Nuvoton Technology corporation. + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/device.h> +#include <linux/module.h> +#include <linux/ioport.h> +#include <linux/clk.h> +#include <linux/platform_device.h> +#include <linux/io.h> +#include <linux/vmalloc.h> +#include <linux/regmap.h> +#include <linux/of_device.h> +#include <linux/spi/spi-mem.h> +#include <linux/mfd/syscon.h> + +/* NPCM7xx GCR module */ +#define NPCM7XX_INTCR3_OFFSET 0x9C +#define NPCM7XX_INTCR3_FIU_FIX BIT(6) + +/* Flash Interface Unit (FIU) Registers */ +#define NPCM_FIU_DRD_CFG 0x00 +#define NPCM_FIU_DWR_CFG 0x04 +#define NPCM_FIU_UMA_CFG 0x08 +#define NPCM_FIU_UMA_CTS 0x0C +#define NPCM_FIU_UMA_CMD 0x10 +#define NPCM_FIU_UMA_ADDR 0x14 +#define NPCM_FIU_PRT_CFG 0x18 +#define NPCM_FIU_UMA_DW0 0x20 +#define NPCM_FIU_UMA_DW1 0x24 +#define NPCM_FIU_UMA_DW2 0x28 +#define NPCM_FIU_UMA_DW3 0x2C +#define NPCM_FIU_UMA_DR0 0x30 +#define NPCM_FIU_UMA_DR1 0x34 +#define NPCM_FIU_UMA_DR2 0x38 +#define NPCM_FIU_UMA_DR3 0x3C +#define NPCM_FIU_MAX_REG_LIMIT 0x80 + +/* FIU Direct Read Configuration Register */ +#define NPCM_FIU_DRD_CFG_LCK BIT(31) +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24) +#define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16) +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12) +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8) +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0) +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DRD_DBW_SHIFT 12 +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8 + +/* FIU Direct Write Configuration Register */ +#define NPCM_FIU_DWR_CFG_LCK BIT(31) +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24) +#define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16) +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10) +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8) +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0) +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16 +#define NPCM_FIU_DWR_ABPCK_SHIFT 10 +#define NPCM_FIU_DWR_DBPCK_SHIFT 8 + +/* FIU UMA Configuration Register */ +#define NPCM_FIU_UMA_CFG_LCK BIT(31) +#define NPCM_FIU_UMA_CFG_CMMLCK BIT(30) +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24) +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21) +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16) +#define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11) +#define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10) +#define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8) +#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6) +#define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4) +#define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2) +#define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0) +#define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2 +#define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4 +#define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6 +#define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8 +#define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11 +#define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16 +#define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21 +#define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24 + +/* FIU UMA Control and Status Register */ +#define NPCM_FIU_UMA_CTS_RDYIE BIT(25) +#define NPCM_FIU_UMA_CTS_RDYST BIT(24) +#define NPCM_FIU_UMA_CTS_SW_CS BIT(16) +#define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8) +#define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0) +#define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8 + +/* FIU UMA Command Register */ +#define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24) +#define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16) +#define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8) +#define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0) + +/* FIU UMA Address Register */ +#define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0) +#define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24) +#define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16) +#define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8) +#define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0) + +/* FIU UMA Write Data Bytes 0-3 Register */ +#define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24) +#define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16) +#define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8) +#define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0) + +/* FIU UMA Write Data Bytes 4-7 Register */ +#define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24) +#define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16) +#define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8) +#define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0) + +/* FIU UMA Write Data Bytes 8-11 Register */ +#define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24) +#define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16) +#define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8) +#define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0) + +/* FIU UMA Write Data Bytes 12-15 Register */ +#define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24) +#define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16) +#define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8) +#define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0) + +/* FIU UMA Read Data Bytes 0-3 Register */ +#define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24) +#define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16) +#define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8) +#define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0) + +/* FIU UMA Read Data Bytes 4-7 Register */ +#define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24) +#define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16) +#define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8) +#define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0) + +/* FIU UMA Read Data Bytes 8-11 Register */ +#define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24) +#define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16) +#define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8) +#define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0) + +/* FIU UMA Read Data Bytes 12-15 Register */ +#define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24) +#define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16) +#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8) +#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0) + +/* FIU Read Mode */ +enum { + DRD_SINGLE_WIRE_MODE = 0, + DRD_DUAL_IO_MODE = 1, + DRD_QUAD_IO_MODE = 2, + DRD_SPI_X_MODE = 3, +}; + +enum { + DWR_ABPCK_BIT_PER_CLK = 0, + DWR_ABPCK_2_BIT_PER_CLK = 1, + DWR_ABPCK_4_BIT_PER_CLK = 2, +}; + +enum { + DWR_DBPCK_BIT_PER_CLK = 0, + DWR_DBPCK_2_BIT_PER_CLK = 1, + DWR_DBPCK_4_BIT_PER_CLK = 2, +}; + +#define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000 +#define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000 + +#define MAP_SIZE_128MB 0x8000000 +#define MAP_SIZE_16MB 0x1000000 +#define MAP_SIZE_8MB 0x800000 + +#define NUM_BITS_IN_BYTE 8 +#define FIU_DRD_MAX_DUMMY_NUMBER 3 +#define NPCM_MAX_CHIP_NUM 4 +#define CHUNK_SIZE 16 +#define UMA_MICRO_SEC_TIMEOUT 150 + +enum { + FIU0 = 0, + FIU3, + FIUX, +}; + +struct npcm_fiu_info { + char *name; + u32 fiu_id; + u32 max_map_size; + u32 max_cs; +}; + +struct fiu_data { + const struct npcm_fiu_info *npcm_fiu_data_info; + int fiu_max; +}; + +static const struct npcm_fiu_info npxm7xx_fiu_info[] = { + {.name = "FIU0", .fiu_id = FIU0, + .max_map_size = MAP_SIZE_128MB, .max_cs = 2}, + {.name = "FIU3", .fiu_id = FIU3, + .max_map_size = MAP_SIZE_128MB, .max_cs = 4}, + {.name = "FIUX", .fiu_id = FIUX, + .max_map_size = MAP_SIZE_16MB, .max_cs = 2} }; + +static const struct fiu_data npxm7xx_fiu_data = { + .npcm_fiu_data_info = npxm7xx_fiu_info, + .fiu_max = 3, +}; + +struct npcm_fiu_spi; + +struct npcm_fiu_chip { + void __iomem *flash_region_mapped_ptr; + struct npcm_fiu_spi *fiu; + unsigned long clkrate; + u32 chipselect; +}; + +struct npcm_fiu_spi { + struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM]; + const struct npcm_fiu_info *info; + struct spi_mem_op drd_op; + struct resource *res_mem; + struct regmap *regmap; + unsigned long clkrate; + struct device *dev; + struct clk *clk; + bool spix_mode; +}; + +static const struct regmap_config npcm_mtd_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = NPCM_FIU_MAX_REG_LIMIT, +}; + +static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu, + const struct spi_mem_op *op) +{ + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, + NPCM_FIU_DRD_CFG_ACCTYPE, + ilog2(op->addr.buswidth) << + NPCM_FIU_DRD_ACCTYPE_SHIFT); + fiu->drd_op.addr.buswidth = op->addr.buswidth; + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, + NPCM_FIU_DRD_CFG_DBW, + ((op->dummy.nbytes * ilog2(op->addr.buswidth)) + / NUM_BITS_IN_BYTE) << NPCM_FIU_DRD_DBW_SHIFT); + fiu->drd_op.dummy.nbytes = op->dummy.nbytes; + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, + NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode); + fiu->drd_op.cmd.opcode = op->cmd.opcode; + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, + NPCM_FIU_DRD_CFG_ADDSIZ, + (op->addr.nbytes - 3) << NPCM_FIU_DRD_ADDSIZ_SHIFT); + fiu->drd_op.addr.nbytes = op->addr.nbytes; +} + +static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc, + u64 offs, size_t len, void *buf) +{ + struct npcm_fiu_spi *fiu = + spi_controller_get_devdata(desc->mem->spi->master); + struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; + void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr + + offs); + u8 *buf_rx = buf; + u32 i; + + if (fiu->spix_mode) { + for (i = 0 ; i < len ; i++) + *(buf_rx + i) = ioread8(src + i); + } else { + if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth || + desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes || + desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode || + desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes) + npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); + + memcpy_fromio(buf_rx, src, len); + } + + return len; +} + +static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc, + u64 offs, size_t len, const void *buf) +{ + struct npcm_fiu_spi *fiu = + spi_controller_get_devdata(desc->mem->spi->master); + struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; + void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr + + offs); + const u8 *buf_tx = buf; + u32 i; + + if (fiu->spix_mode) + for (i = 0 ; i < len ; i++) + iowrite8(*(buf_tx + i), dst + i); + else + memcpy_toio(dst, buf_tx, len); + + return len; +} + +static int npcm_fiu_uma_read(struct spi_mem *mem, + const struct spi_mem_op *op, u32 addr, + bool is_address_size, u8 *data, u32 data_size) +{ + struct npcm_fiu_spi *fiu = + spi_controller_get_devdata(mem->spi->master); + u32 uma_cfg = BIT(10); + u32 data_reg[4]; + int ret; + u32 val; + u32 i; + + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, + NPCM_FIU_UMA_CTS_DEV_NUM, + (mem->spi->chip_select << + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, + NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode); + + if (is_address_size) { + uma_cfg |= ilog2(op->cmd.buswidth); + uma_cfg |= ilog2(op->addr.buswidth) + << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT; + uma_cfg |= ilog2(op->dummy.buswidth) + << NPCM_FIU_UMA_CFG_DBPCK_SHIFT; + uma_cfg |= ilog2(op->data.buswidth) + << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT; + uma_cfg |= op->dummy.nbytes << NPCM_FIU_UMA_CFG_DBSIZ_SHIFT; + uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr); + } else { + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); + } + + uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT; + regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); + regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, + NPCM_FIU_UMA_CTS_EXEC_DONE, + NPCM_FIU_UMA_CTS_EXEC_DONE); + ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, + (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, + UMA_MICRO_SEC_TIMEOUT); + if (ret) + return ret; + + if (data_size) { + for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++) + regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i * 4), + &data_reg[i]); + memcpy(data, data_reg, data_size); + } + + return 0; +} + +static int npcm_fiu_uma_write(struct spi_mem *mem, + const struct spi_mem_op *op, u8 cmd, + bool is_address_size, u8 *data, u32 data_size) +{ + struct npcm_fiu_spi *fiu = + spi_controller_get_devdata(mem->spi->master); + u32 uma_cfg = BIT(10); + u32 data_reg[4] = {0}; + u32 val; + u32 i; + + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, + NPCM_FIU_UMA_CTS_DEV_NUM, + (mem->spi->chip_select << + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); + + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD, + NPCM_FIU_UMA_CMD_CMD, cmd); + + if (data_size) { + memcpy(data_reg, data, data_size); + for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++) + regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i * 4), + data_reg[i]); + } + + if (is_address_size) { + uma_cfg |= ilog2(op->cmd.buswidth); + uma_cfg |= ilog2(op->addr.buswidth) << + NPCM_FIU_UMA_CFG_ADBPCK_SHIFT; + uma_cfg |= ilog2(op->data.buswidth) << + NPCM_FIU_UMA_CFG_WDBPCK_SHIFT; + uma_cfg |= op->addr.nbytes << NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT; + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, op->addr.val); + } else { + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0); + } + + uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT); + regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg); + + regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS, + NPCM_FIU_UMA_CTS_EXEC_DONE, + NPCM_FIU_UMA_CTS_EXEC_DONE); + + return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS, val, + (!(val & NPCM_FIU_UMA_CTS_EXEC_DONE)), 0, + UMA_MICRO_SEC_TIMEOUT); +} + +static int npcm_fiu_manualwrite(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct npcm_fiu_spi *fiu = + spi_controller_get_devdata(mem->spi->master); + u8 *data = (u8 *)op->data.buf.out; + u32 num_data_chunks; + u32 remain_data; + u32 idx = 0; + int ret; + + num_data_chunks = op->data.nbytes / CHUNK_SIZE; + remain_data = op->data.nbytes % CHUNK_SIZE; + + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, + NPCM_FIU_UMA_CTS_DEV_NUM, + (mem->spi->chip_select << + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT)); + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, + NPCM_FIU_UMA_CTS_SW_CS, 0); + + ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0); + if (ret) + return ret; + + /* Starting the data writing loop in multiples of 8 */ + for (idx = 0; idx < num_data_chunks; ++idx) { + ret = npcm_fiu_uma_write(mem, op, data[0], false, + &data[1], CHUNK_SIZE - 1); + if (ret) + return ret; + + data += CHUNK_SIZE; + } + + /* Handling chunk remains */ + if (remain_data > 0) { + ret = npcm_fiu_uma_write(mem, op, data[0], false, + &data[1], remain_data - 1); + if (ret) + return ret; + } + + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS, + NPCM_FIU_UMA_CTS_SW_CS, NPCM_FIU_UMA_CTS_SW_CS); + + return 0; +} + +static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op *op) +{ + u8 *data = op->data.buf.in; + int i, readlen, currlen; + size_t retlen = 0; + u8 *buf_ptr; + u32 addr; + int ret; + + i = 0; + currlen = op->data.nbytes; + + do { + addr = ((u32)op->addr.val + i); + if (currlen < 16) + readlen = currlen; + else + readlen = 16; + + buf_ptr = data + i; + ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr, + readlen); + if (ret) + return ret; + + i += readlen; + currlen -= 16; + } while (currlen > 0); + + retlen = i; + + return 0; +} + +static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu) +{ + regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG, + NPCM_FIU_DWR_16_BYTE_BURST); + regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, + NPCM_FIU_DWR_CFG_ABPCK, + DWR_ABPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_ABPCK_SHIFT); + regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG, + NPCM_FIU_DWR_CFG_DBPCK, + DWR_DBPCK_4_BIT_PER_CLK << NPCM_FIU_DWR_DBPCK_SHIFT); +} + +static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu) +{ + u32 rx_dummy = 0; + + regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG, + NPCM_FIU_DRD_16_BYTE_BURST); + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, + NPCM_FIU_DRD_CFG_ACCTYPE, + DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT); + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG, + NPCM_FIU_DRD_CFG_DBW, + rx_dummy << NPCM_FIU_DRD_DBW_SHIFT); +} + +static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) +{ + struct npcm_fiu_spi *fiu = + spi_controller_get_devdata(mem->spi->master); + struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select]; + int ret = 0; + u8 *buf; + + dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", + op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, + op->dummy.buswidth, op->data.buswidth, op->addr.val, + op->data.nbytes); + + if (fiu->spix_mode || op->addr.nbytes > 4) + return -ENOTSUPP; + + if (fiu->clkrate != chip->clkrate) { + ret = clk_set_rate(fiu->clk, chip->clkrate); + if (ret < 0) + dev_warn(fiu->dev, "Failed setting %lu frequancy, stay at %lu frequancy\n", chip->clkrate, fiu->clkrate); + else + fiu->clkrate = chip->clkrate; + } + + if (op->data.dir == SPI_MEM_DATA_IN) { + if (!op->addr.nbytes) { + buf = op->data.buf.in; + ret = npcm_fiu_uma_read(mem, op, op->addr.val, false, + buf, op->data.nbytes); + } else { + ret = npcm_fiu_read(mem, op); + } + } else { + if (!op->addr.nbytes && !op->data.nbytes) + ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, + NULL, 0); + if (op->addr.nbytes && !op->data.nbytes) { + int i; + u8 buf_addr[4]; + u32 addr = op->addr.val; + + for (i = op->addr.nbytes - 1; i >= 0; i--) { + buf_addr[i] = addr & 0xff; + addr >>= 8; + } + ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, + buf_addr, op->addr.nbytes); + } + if (!op->addr.nbytes && op->data.nbytes) + ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, false, + (u8 *)op->data.buf.out, + op->data.nbytes); + if (op->addr.nbytes && op->data.nbytes) + ret = npcm_fiu_manualwrite(mem, op); + } + + return ret; +} + +static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc) +{ + struct npcm_fiu_spi *fiu = + spi_controller_get_devdata(desc->mem->spi->master); + struct npcm_fiu_chip *chip = &fiu->chip[desc->mem->spi->chip_select]; + struct regmap *gcr_regmap; + + if (!fiu->res_mem) { + dev_warn(fiu->dev, "Reserved memory not defined, direct read disabled\n"); + desc->nodirmap = true; + return 0; + } + + if (!fiu->spix_mode && + desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { + desc->nodirmap = true; + return 0; + } + + if (!chip->flash_region_mapped_ptr) { + chip->flash_region_mapped_ptr = + devm_ioremap_nocache(fiu->dev, (fiu->res_mem->start + + (fiu->info->max_map_size * + desc->mem->spi->chip_select)), + (u32)desc->info.length); + if (!chip->flash_region_mapped_ptr) { + dev_warn(fiu->dev, "Error mapping memory region, direct read disabled\n"); + desc->nodirmap = true; + return 0; + } + } + + if (of_device_is_compatible(fiu->dev->of_node, "nuvoton,npcm750-fiu")) { + gcr_regmap = + syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); + if (IS_ERR(gcr_regmap)) { + dev_warn(fiu->dev, "Didn't find nuvoton,npcm750-gcr, direct read disabled\n"); + desc->nodirmap = true; + return 0; + } + regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET, + NPCM7XX_INTCR3_FIU_FIX, + NPCM7XX_INTCR3_FIU_FIX); + } + + if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) { + if (!fiu->spix_mode) + npcm_fiu_set_drd(fiu, &desc->info.op_tmpl); + else + npcm_fiux_set_direct_rd(fiu); + + } else { + npcm_fiux_set_direct_wr(fiu); + } + + return 0; +} + +static int npcm_fiu_setup(struct spi_device *spi) +{ + struct spi_controller *ctrl = spi->master; + struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl); + struct npcm_fiu_chip *chip; + + chip = &fiu->chip[spi->chip_select]; + chip->fiu = fiu; + chip->chipselect = spi->chip_select; + chip->clkrate = spi->max_speed_hz; + + fiu->clkrate = clk_get_rate(fiu->clk); + + return 0; +} + +static const struct spi_controller_mem_ops npcm_fiu_mem_ops = { + .exec_op = npcm_fiu_exec_op, + .dirmap_create = npcm_fiu_dirmap_create, + .dirmap_read = npcm_fiu_direct_read, + .dirmap_write = npcm_fiu_direct_write, +}; + +static const struct of_device_id npcm_fiu_dt_ids[] = { + { .compatible = "nuvoton,npcm750-fiu", .data = &npxm7xx_fiu_data }, + { /* sentinel */ } +}; + +static int npcm_fiu_probe(struct platform_device *pdev) +{ + const struct fiu_data *fiu_data_match; + const struct of_device_id *match; + struct device *dev = &pdev->dev; + struct spi_controller *ctrl; + struct npcm_fiu_spi *fiu; + void __iomem *regbase; + struct resource *res; + int ret; + int id; + + ctrl = spi_alloc_master(dev, sizeof(*fiu)); + if (!ctrl) + return -ENOMEM; + + fiu = spi_controller_get_devdata(ctrl); + + match = of_match_device(npcm_fiu_dt_ids, dev); + if (!match || !match->data) { + dev_err(dev, "No compatible OF match\n"); + return -ENODEV; + } + + fiu_data_match = match->data; + id = of_alias_get_id(dev->of_node, "fiu"); + if (id < 0 || id >= fiu_data_match->fiu_max) { + dev_err(dev, "Invalid platform device id: %d\n", id); + return -EINVAL; + } + + fiu->info = &fiu_data_match->npcm_fiu_data_info[id]; + + platform_set_drvdata(pdev, fiu); + fiu->dev = dev; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "control"); + regbase = devm_ioremap_resource(dev, res); + if (IS_ERR(regbase)) + return PTR_ERR(regbase); + + fiu->regmap = devm_regmap_init_mmio(dev, regbase, + &npcm_mtd_regmap_config); + if (IS_ERR(fiu->regmap)) { + dev_err(dev, "Failed to create regmap\n"); + return PTR_ERR(fiu->regmap); + } + + fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "memory"); + fiu->clk = devm_clk_get(dev, NULL); + if (IS_ERR(fiu->clk)) + return PTR_ERR(fiu->clk); + + fiu->spix_mode = of_property_read_bool(dev->of_node, + "nuvoton,spix-mode"); + + platform_set_drvdata(pdev, fiu); + clk_prepare_enable(fiu->clk); + + ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD + | SPI_TX_DUAL | SPI_TX_QUAD; + ctrl->setup = npcm_fiu_setup; + ctrl->bus_num = -1; + ctrl->mem_ops = &npcm_fiu_mem_ops; + ctrl->num_chipselect = fiu->info->max_cs; + ctrl->dev.of_node = dev->of_node; + + ret = devm_spi_register_master(dev, ctrl); + if (ret) + return ret; + + return 0; +} + +static int npcm_fiu_remove(struct platform_device *pdev) +{ + struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev); + + clk_disable_unprepare(fiu->clk); + return 0; +} + +MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids); + +static struct platform_driver npcm_fiu_driver = { + .driver = { + .name = "NPCM-FIU", + .bus = &platform_bus_type, + .of_match_table = npcm_fiu_dt_ids, + }, + .probe = npcm_fiu_probe, + .remove = npcm_fiu_remove, +}; +module_platform_driver(npcm_fiu_driver); + +MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller Driver"); +MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index c8ae07cd6fbf..b86e015b31e6 100644 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -780,9 +780,9 @@ static int set_config(struct usb_composite_dev *cdev, result = 0; } - INFO(cdev, "%s config #%d: %s\n", - usb_speed_string(gadget->speed), - number, c ? c->label : "unconfigured"); + DBG(cdev, "%s config #%d: %s\n", + usb_speed_string(gadget->speed), + number, c ? c->label : "unconfigured"); if (!c) goto done; diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index 5b64bc2e8788..7e00960651fa 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -54,6 +54,8 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_CTRL_ENABLE BIT(0) #define WDT_TIMEOUT_STATUS 0x10 #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_CLEAR_TIMEOUT_STATUS 0x14 +#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) /* * WDT_RESET_WIDTH controls the characteristics of the external pulse (if @@ -166,6 +168,60 @@ static int aspeed_wdt_restart(struct watchdog_device *wdd, return 0; } +/* access_cs0 shows if cs0 is accessible, hence the reverted bit */ +static ssize_t access_cs0_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct aspeed_wdt *wdt = dev_get_drvdata(dev); + u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS); + + return sprintf(buf, "%u\n", + !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)); +} + +static ssize_t access_cs0_store(struct device *dev, + struct device_attribute *attr, const char *buf, + size_t size) +{ + struct aspeed_wdt *wdt = dev_get_drvdata(dev); + unsigned long val; + + if (kstrtoul(buf, 10, &val)) + return -EINVAL; + + if (val) + writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION, + wdt->base + WDT_CLEAR_TIMEOUT_STATUS); + + return size; +} + +/* + * This attribute exists only if the system has booted from the alternate + * flash with 'alt-boot' option. + * + * At alternate flash the 'access_cs0' sysfs node provides: + * ast2400: a way to get access to the primary SPI flash chip at CS0 + * after booting from the alternate chip at CS1. + * ast2500: a way to restore the normal address mapping from + * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1). + * + * Clearing the boot code selection and timeout counter also resets to the + * initial state the chip select line mapping. When the SoC is in normal + * mapping state (i.e. booted from CS0), clearing those bits does nothing for + * both versions of the SoC. For alternate boot mode (booted from CS1 due to + * wdt2 expiration) the behavior differs as described above. + * + * This option can be used with wdt2 (watchdog1) only. + */ +static DEVICE_ATTR_RW(access_cs0); + +static struct attribute *bswitch_attrs[] = { + &dev_attr_access_cs0.attr, + NULL +}; +ATTRIBUTE_GROUPS(bswitch); + static const struct watchdog_ops aspeed_wdt_ops = { .start = aspeed_wdt_start, .stop = aspeed_wdt_stop, @@ -202,11 +258,6 @@ static int aspeed_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->base)) return PTR_ERR(wdt->base); - /* - * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only - * runs at 1MHz. We chose to always run at 1MHz, as there's no - * good reason to have a faster watchdog counter. - */ wdt->wdd.info = &aspeed_wdt_info; wdt->wdd.ops = &aspeed_wdt_ops; wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS; @@ -222,7 +273,16 @@ static int aspeed_wdt_probe(struct platform_device *pdev) return -EINVAL; config = ofdid->data; - wdt->ctrl = WDT_CTRL_1MHZ_CLK; + /* + * On clock rates: + * - ast2400 wdt can run at PCLK, or 1MHz + * - ast2500 only runs at 1MHz, hard coding bit 4 to 1 + * - ast2600 always runs at 1MHz + * + * Set the ast2400 to run at 1MHz as it simplifies the driver. + */ + if (of_device_is_compatible(np, "aspeed,ast2400-wdt")) + wdt->ctrl = WDT_CTRL_1MHZ_CLK; /* * Control reset on a per-device basis to ensure the @@ -308,9 +368,16 @@ static int aspeed_wdt_probe(struct platform_device *pdev) } status = readl(wdt->base + WDT_TIMEOUT_STATUS); - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) + if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) { wdt->wdd.bootstatus = WDIOF_CARDRESET; + if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || + of_device_is_compatible(np, "aspeed,ast2500-wdt")) + wdt->wdd.groups = bswitch_groups; + } + + dev_set_drvdata(dev, wdt); + return devm_watchdog_register_device(dev, &wdt->wdd); } diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index f43738607d77..64e245fb113f 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -39,6 +39,8 @@ #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_24M 35 +#define ASPEED_CLK_GATE_MAC1RCLK 36 +#define ASPEED_CLK_GATE_MAC2RCLK 37 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h new file mode 100644 index 000000000000..ac567fc84a87 --- /dev/null +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +#ifndef DT_BINDINGS_AST2600_CLOCK_H +#define DT_BINDINGS_AST2600_CLOCK_H + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 + +#define ASPEED_CLK_GATE_MCLK 2 + +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 + +#define ASPEED_CLK_GATE_LCLK 6 +#define ASPEED_CLK_GATE_LHCCLK 7 + +#define ASPEED_CLK_GATE_D1CLK 8 +#define ASPEED_CLK_GATE_YCLK 9 + +#define ASPEED_CLK_GATE_REF0CLK 10 +#define ASPEED_CLK_GATE_REF1CLK 11 + +#define ASPEED_CLK_GATE_ESPICLK 12 + +#define ASPEED_CLK_GATE_USBUHCICLK 13 +#define ASPEED_CLK_GATE_USBPORT1CLK 14 +#define ASPEED_CLK_GATE_USBPORT2CLK 15 + +#define ASPEED_CLK_GATE_RSACLK 16 +#define ASPEED_CLK_GATE_RVASCLK 17 + +#define ASPEED_CLK_GATE_MAC1CLK 18 +#define ASPEED_CLK_GATE_MAC2CLK 19 +#define ASPEED_CLK_GATE_MAC3CLK 20 +#define ASPEED_CLK_GATE_MAC4CLK 21 + +#define ASPEED_CLK_GATE_UART1CLK 22 +#define ASPEED_CLK_GATE_UART2CLK 23 +#define ASPEED_CLK_GATE_UART3CLK 24 +#define ASPEED_CLK_GATE_UART4CLK 25 +#define ASPEED_CLK_GATE_UART5CLK 26 +#define ASPEED_CLK_GATE_UART6CLK 27 +#define ASPEED_CLK_GATE_UART7CLK 28 +#define ASPEED_CLK_GATE_UART8CLK 29 +#define ASPEED_CLK_GATE_UART9CLK 30 +#define ASPEED_CLK_GATE_UART10CLK 31 +#define ASPEED_CLK_GATE_UART11CLK 32 +#define ASPEED_CLK_GATE_UART12CLK 33 +#define ASPEED_CLK_GATE_UART13CLK 34 + +#define ASPEED_CLK_GATE_SDCLK 35 +#define ASPEED_CLK_GATE_EMMCCLK 36 + +#define ASPEED_CLK_GATE_I3C0CLK 37 +#define ASPEED_CLK_GATE_I3C1CLK 38 +#define ASPEED_CLK_GATE_I3C2CLK 39 +#define ASPEED_CLK_GATE_I3C3CLK 40 +#define ASPEED_CLK_GATE_I3C4CLK 41 +#define ASPEED_CLK_GATE_I3C5CLK 42 +#define ASPEED_CLK_GATE_I3C6CLK 43 +#define ASPEED_CLK_GATE_I3C7CLK 44 + +#define ASPEED_CLK_GATE_FSICLK 45 + +#define ASPEED_CLK_HPLL 46 +#define ASPEED_CLK_MPLL 47 +#define ASPEED_CLK_DPLL 48 +#define ASPEED_CLK_EPLL 49 +#define ASPEED_CLK_APLL 50 +#define ASPEED_CLK_AHB 51 +#define ASPEED_CLK_APB1 52 +#define ASPEED_CLK_APB2 53 +#define ASPEED_CLK_BCLK 54 +#define ASPEED_CLK_D1CLK 55 +#define ASPEED_CLK_VCLK 56 +#define ASPEED_CLK_LHCLK 57 +#define ASPEED_CLK_UART 58 +#define ASPEED_CLK_UARTX 59 +#define ASPEED_CLK_SDIO 60 +#define ASPEED_CLK_EMMC 61 +#define ASPEED_CLK_ECLK 62 +#define ASPEED_CLK_ECLK_MUX 63 +#define ASPEED_CLK_MAC12 64 +#define ASPEED_CLK_MAC34 65 +#define ASPEED_CLK_USBPHY_40M 66 + +#define ASPEED_CLK_GATE_MAC1RCLK 67 +#define ASPEED_CLK_GATE_MAC2RCLK 68 +#define ASPEED_CLK_GATE_MAC3RCLK 69 +#define ASPEED_CLK_GATE_MAC4RCLK 70 + +/* Only list resets here that are not part of a gate */ +#define ASPEED_RESET_ADC 55 +#define ASPEED_RESET_JTAG_MASTER2 54 +#define ASPEED_RESET_I3C_DMA 39 +#define ASPEED_RESET_PWM 37 +#define ASPEED_RESET_PECI 36 +#define ASPEED_RESET_MII 35 +#define ASPEED_RESET_I2C 34 +#define ASPEED_RESET_H2X 31 +#define ASPEED_RESET_GP_MCU 30 +#define ASPEED_RESET_DP_MCU 29 +#define ASPEED_RESET_DP 28 +#define ASPEED_RESET_RC_XDMA 27 +#define ASPEED_RESET_GRAPHICS 26 +#define ASPEED_RESET_DEV_XDMA 25 +#define ASPEED_RESET_DEV_MCTP 24 +#define ASPEED_RESET_RC_MCTP 23 +#define ASPEED_RESET_JTAG_MASTER 22 +#define ASPEED_RESET_PCIE_DEV_O 21 +#define ASPEED_RESET_PCIE_DEV_OEN 20 +#define ASPEED_RESET_PCIE_RC_O 19 +#define ASPEED_RESET_PCIE_RC_OEN 18 +#define ASPEED_RESET_PCI_DP 5 +#define ASPEED_RESET_AHB 1 +#define ASPEED_RESET_SDRAM 0 + +#endif diff --git a/include/linux/clk/nuvoton.h b/include/linux/clk/nuvoton.h new file mode 100644 index 000000000000..9a474d691786 --- /dev/null +++ b/include/linux/clk/nuvoton.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2014-2019 Nuvoton Technology corporation. */ + +#ifndef __LINUX_CLK_NUVOTON_H_ +#define __LINUX_CLK_NUVOTON_H_ + +void nuvoton_npcm750_clock_init(void); + +#endif diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h index 6a0e420915a3..3efb372ecf73 100644 --- a/include/linux/gpio/driver.h +++ b/include/linux/gpio/driver.h @@ -125,11 +125,17 @@ struct gpio_irq_chip { bool threaded; /** - * @need_valid_mask: - * - * If set core allocates @valid_mask with all bits set to one. + * @init_valid_mask: optional routine to initialize @valid_mask, to be + * used if not all GPIO lines are valid interrupts. Sometimes some + * lines just cannot fire interrupts, and this routine, when defined, + * is passed a bitmap in "valid_mask" and it will have ngpios + * bits from 0..(ngpios-1) set to "1" as in valid. The callback can + * then directly set some bits to "0" if they cannot be used for + * interrupts. */ - bool need_valid_mask; + void (*init_valid_mask)(struct gpio_chip *chip, + unsigned long *valid_mask, + unsigned int ngpios); /** * @valid_mask: diff --git a/include/linux/mfd/intel-peci-client.h b/include/linux/mfd/intel-peci-client.h new file mode 100644 index 000000000000..8f6d823a59cd --- /dev/null +++ b/include/linux/mfd/intel-peci-client.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Intel Corporation */ + +#ifndef __LINUX_MFD_INTEL_PECI_CLIENT_H +#define __LINUX_MFD_INTEL_PECI_CLIENT_H + +#include <linux/peci.h> + +#if IS_ENABLED(CONFIG_X86) +#include <asm/intel-family.h> +#else +/** + * Architectures other than x86 cannot include the header file so define these + * at here. These are needed for detecting type of client x86 CPUs behind a PECI + * connection. + */ +#define INTEL_FAM6_HASWELL_X 0x3F +#define INTEL_FAM6_BROADWELL_X 0x4F +#define INTEL_FAM6_SKYLAKE_X 0x55 +#endif + +#define CORE_MAX_ON_HSX 18 /* Max number of cores on Haswell */ +#define CHAN_RANK_MAX_ON_HSX 8 /* Max number of channel ranks on Haswell */ +#define DIMM_IDX_MAX_ON_HSX 3 /* Max DIMM index per channel on Haswell */ + +#define CORE_MAX_ON_BDX 24 /* Max number of cores on Broadwell */ +#define CHAN_RANK_MAX_ON_BDX 4 /* Max number of channel ranks on Broadwell */ +#define DIMM_IDX_MAX_ON_BDX 3 /* Max DIMM index per channel on Broadwell */ + +#define CORE_MAX_ON_SKX 28 /* Max number of cores on Skylake */ +#define CHAN_RANK_MAX_ON_SKX 6 /* Max number of channel ranks on Skylake */ +#define DIMM_IDX_MAX_ON_SKX 2 /* Max DIMM index per channel on Skylake */ + +#define CORE_NUMS_MAX CORE_MAX_ON_SKX +#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX +#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX +#define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX) + +/** + * struct cpu_gen_info - CPU generation specific information + * @family: CPU family ID + * @model: CPU model + * @core_max: max number of cores + * @chan_rank_max: max number of channel ranks + * @dimm_idx_max: max number of DIMM indices + * + * CPU generation specific information to identify maximum number of cores and + * DIMM slots. + */ +struct cpu_gen_info { + u16 family; + u8 model; + uint core_max; + uint chan_rank_max; + uint dimm_idx_max; +}; + +/** + * struct peci_client_manager - PECI client manager information + * @client; pointer to the PECI client + * @dev: pointer to the struct device + * @name: PECI client manager name + * @gen_info: CPU generation info of the detected CPU + * + * PECI client manager information for managing PECI sideband functions on a CPU + * client. + */ +struct peci_client_manager { + struct peci_client *client; + struct device *dev; + char name[PECI_NAME_SIZE]; + const struct cpu_gen_info *gen_info; +}; + +/** + * peci_client_read_package_config - read from the Package Configuration Space + * @priv: driver private data structure + * @index: encoding index for the requested service + * @param: parameter to specify the exact data being requested + * @data: data buffer to store the result + * Context: can sleep + * + * A generic PECI command that provides read access to the + * "Package Configuration Space" that is maintained by the PCU, including + * various power and thermal management functions. Typical PCS read services + * supported by the processor may include access to temperature data, energy + * status, run time information, DIMM temperatures and so on. + * + * Return: zero on success, else a negative error code. + */ +static inline int +peci_client_read_package_config(struct peci_client_manager *priv, + u8 index, u16 param, u8 *data) +{ + struct peci_rd_pkg_cfg_msg msg; + int rc; + + msg.addr = priv->client->addr; + msg.index = index; + msg.param = param; + msg.rx_len = 4; + + rc = peci_command(priv->client->adapter, PECI_CMD_RD_PKG_CFG, &msg); + if (!rc) + memcpy(data, msg.pkg_config, 4); + + return rc; +} + +#endif /* __LINUX_MFD_INTEL_PECI_CLIENT_H */ diff --git a/include/linux/peci.h b/include/linux/peci.h new file mode 100644 index 000000000000..d0e47d45d1d0 --- /dev/null +++ b/include/linux/peci.h @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Intel Corporation */ + +#ifndef __LINUX_PECI_H +#define __LINUX_PECI_H + +#include <linux/cdev.h> +#include <linux/device.h> +#include <linux/peci-ioctl.h> +#include <linux/rtmutex.h> + +#define PECI_NAME_SIZE 32 + +struct peci_board_info { + char type[PECI_NAME_SIZE]; + unsigned short addr; /* CPU client address */ + struct device_node *of_node; +}; + +/** + * struct peci_adapter - represent a PECI adapter + * @owner: owner module of the PECI adpater + * @bus_lock: mutex for exclusion of multiple callers + * @dev: device interface to this driver + * @cdev: character device object to create character device + * @nr: the bus number to map + * @name: name of the adapter + * @userspace_clients_lock: mutex for exclusion of clients handling + * @userspace_clients: list of registered clients + * @xfer: low-level transfer function pointer of the adapter + * @cmd_mask: mask for supportable PECI commands + * + * Each PECI adapter can communicate with one or more PECI client children. + * These make a small bus, sharing a single wired PECI connection. + */ +struct peci_adapter { + struct module *owner; + struct rt_mutex bus_lock; + struct device dev; + struct cdev cdev; + int nr; + char name[PECI_NAME_SIZE]; + struct mutex userspace_clients_lock; /* clients list mutex */ + struct list_head userspace_clients; + int (*xfer)(struct peci_adapter *adapter, + struct peci_xfer_msg *msg); + uint cmd_mask; +}; + +static inline struct peci_adapter *to_peci_adapter(void *d) +{ + return container_of(d, struct peci_adapter, dev); +} + +static inline void *peci_get_adapdata(const struct peci_adapter *adapter) +{ + return dev_get_drvdata(&adapter->dev); +} + +static inline void peci_set_adapdata(struct peci_adapter *adapter, void *data) +{ + dev_set_drvdata(&adapter->dev, data); +} + +/** + * struct peci_client - represent a PECI client device + * @dev: driver model device node for the client + * @adapter: manages the bus segment hosting this PECI device + * @addr: address used on the PECI bus connected to the parent adapter + * @name: indicates the type of the device + * @detected: detected PECI clients list + * + * A peci_client identifies a single device (i.e. CPU) connected to a peci bus. + * The behaviour exposed to Linux is defined by the driver managing the device. + */ +struct peci_client { + struct device dev; + struct peci_adapter *adapter; + u8 addr; + char name[PECI_NAME_SIZE]; + struct list_head detected; +}; + +static inline struct peci_client *to_peci_client(void *d) +{ + return container_of(d, struct peci_client, dev); +} + +struct peci_device_id { + char name[PECI_NAME_SIZE]; + unsigned long driver_data; /* Data private to the driver */ +}; + +/** + * struct peci_driver - represent a PECI device driver + * @probe: callback for device binding + * @remove: callback for device unbinding + * @shutdown: callback for device shutdown + * @driver: device driver model driver + * @id_table: list of PECI devices supported by this driver + * + * The driver.owner field should be set to the module owner of this driver. + * The driver.name field should be set to the name of this driver. + */ +struct peci_driver { + int (*probe)(struct peci_client *client); + int (*remove)(struct peci_client *client); + void (*shutdown)(struct peci_client *client); + struct device_driver driver; + const struct peci_device_id *id_table; +}; + +static inline struct peci_driver *to_peci_driver(void *d) +{ + return container_of(d, struct peci_driver, driver); +} + +/** + * module_peci_driver - Helper macro for registering a modular PECI driver + * @__peci_driver: peci_driver struct + * + * Helper macro for PECI drivers which do not do anything special in module + * init/exit. This eliminates a lot of boilerplate. Each module may only + * use this macro once, and calling it replaces module_init() and module_exit() + */ +#define module_peci_driver(__peci_driver) \ + module_driver(__peci_driver, peci_add_driver, peci_del_driver) + +/* use a define to avoid include chaining to get THIS_MODULE */ +#define peci_add_driver(driver) peci_register_driver(THIS_MODULE, driver) + +int peci_register_driver(struct module *owner, struct peci_driver *drv); +void peci_del_driver(struct peci_driver *driver); +struct peci_client *peci_verify_client(struct device *dev); +struct peci_adapter *peci_alloc_adapter(struct device *dev, unsigned int size); +int peci_add_adapter(struct peci_adapter *adapter); +void peci_del_adapter(struct peci_adapter *adapter); +struct peci_adapter *peci_verify_adapter(struct device *dev); +int peci_command(struct peci_adapter *adpater, enum peci_cmd cmd, void *vmsg); +int peci_get_cpu_id(struct peci_adapter *adapter, u8 addr, u32 *cpu_id); + +#endif /* __LINUX_PECI_H */ diff --git a/include/trace/events/fsi.h b/include/trace/events/fsi.h index 92e5e89e52ed..9832cb8e0eb0 100644 --- a/include/trace/events/fsi.h +++ b/include/trace/events/fsi.h @@ -26,7 +26,7 @@ TRACE_EVENT(fsi_master_read, __entry->addr = addr; __entry->size = size; ), - TP_printk("fsi%d:%02d:%02d %08x[%zd]", + TP_printk("fsi%d:%02d:%02d %08x[%zu]", __entry->master_idx, __entry->link, __entry->id, @@ -56,7 +56,7 @@ TRACE_EVENT(fsi_master_write, __entry->data = 0; memcpy(&__entry->data, data, size); ), - TP_printk("fsi%d:%02d:%02d %08x[%zd] <= {%*ph}", + TP_printk("fsi%d:%02d:%02d %08x[%zu] <= {%*ph}", __entry->master_idx, __entry->link, __entry->id, @@ -93,7 +93,7 @@ TRACE_EVENT(fsi_master_rw_result, if (__entry->write || !__entry->ret) memcpy(&__entry->data, data, size); ), - TP_printk("fsi%d:%02d:%02d %08x[%zd] %s {%*ph} ret %d", + TP_printk("fsi%d:%02d:%02d %08x[%zu] %s {%*ph} ret %d", __entry->master_idx, __entry->link, __entry->id, diff --git a/include/trace/events/fsi_master_aspeed.h b/include/trace/events/fsi_master_aspeed.h new file mode 100644 index 000000000000..8e47637c5fb7 --- /dev/null +++ b/include/trace/events/fsi_master_aspeed.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM fsi_master_aspeed + +#if !defined(_TRACE_FSI_MASTER_ASPEED_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_FSI_MASTER_ASPEED_H + +#include <linux/tracepoint.h> + +TRACE_EVENT(fsi_master_aspeed_opb_read, + TP_PROTO(uint32_t addr, size_t size, uint32_t result, uint32_t status, uint32_t irq_status), + TP_ARGS(addr, size, result, status, irq_status), + TP_STRUCT__entry( + __field(uint32_t, addr) + __field(size_t, size) + __field(uint32_t, result) + __field(uint32_t, status) + __field(uint32_t, irq_status) + ), + TP_fast_assign( + __entry->addr = addr; + __entry->size = size; + __entry->result = result; + __entry->status = status; + __entry->irq_status = irq_status; + ), + TP_printk("fsi: opb read: addr %08x size %zu: result %08x status: %08x irq_status: %08x", + __entry->addr, __entry->size, __entry->result, + __entry->status, __entry->irq_status + ) +); + +TRACE_EVENT(fsi_master_aspeed_opb_write, + TP_PROTO(uint32_t addr, uint32_t val, size_t size, uint32_t status, uint32_t irq_status), + TP_ARGS(addr, val, size, status, irq_status), + TP_STRUCT__entry( + __field(uint32_t, addr) + __field(uint32_t, val) + __field(size_t, size) + __field(uint32_t, status) + __field(uint32_t, irq_status) + ), + TP_fast_assign( + __entry->addr = addr; + __entry->val = val; + __entry->size = size; + __entry->status = status; + __entry->irq_status = irq_status; + ), + TP_printk("fsi: opb write: addr %08x val %08x size %zu status: %08x irq_status: %08x", + __entry->addr, __entry->val, __entry->size, + __entry->status, __entry->irq_status + ) + ); + +TRACE_EVENT(fsi_master_aspeed_opb_error, + TP_PROTO(uint32_t mresp0, uint32_t mstap0, uint32_t mesrb0), + TP_ARGS(mresp0, mstap0, mesrb0), + TP_STRUCT__entry( + __field(uint32_t, mresp0) + __field(uint32_t, mstap0) + __field(uint32_t, mesrb0) + ), + TP_fast_assign( + __entry->mresp0 = mresp0; + __entry->mstap0 = mstap0; + __entry->mesrb0 = mesrb0; + ), + TP_printk("mresp0 %08x mstap0 %08x mesrb0 %08x", + __entry->mresp0, __entry->mstap0, __entry->mesrb0 + ) + ); + +#endif + +#include <trace/define_trace.h> diff --git a/include/uapi/linux/peci-ioctl.h b/include/uapi/linux/peci-ioctl.h new file mode 100644 index 000000000000..a6dae71cbff5 --- /dev/null +++ b/include/uapi/linux/peci-ioctl.h @@ -0,0 +1,403 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Intel Corporation */ + +#ifndef __PECI_IOCTL_H +#define __PECI_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +/* Base Address of 48d */ +#define PECI_BASE_ADDR 0x30 /* The PECI client's default address of 0x30 */ +#define PECI_OFFSET_MAX 8 /* Max numver of CPU clients */ + +/* PCI Access */ +#define MAX_PCI_READ_LEN 24 /* Number of bytes of the PCI Space read */ + +#define PCI_BUS0_CPU0 0x00 +#define PCI_BUS0_CPU1 0x80 +#define PCI_CPUBUSNO_BUS 0x00 +#define PCI_CPUBUSNO_DEV 0x08 +#define PCI_CPUBUSNO_FUNC 0x02 +#define PCI_CPUBUSNO 0xcc +#define PCI_CPUBUSNO_1 0xd0 +#define PCI_CPUBUSNO_VALID 0xd4 + +/* Package Identifier Read Parameter Value */ +#define PKG_ID_CPU_ID 0x0000 /* CPUID Info */ +#define PKG_ID_PLATFORM_ID 0x0001 /* Platform ID */ +#define PKG_ID_UNCORE_ID 0x0002 /* Uncore Device ID */ +#define PKG_ID_MAX_THREAD_ID 0x0003 /* Max Thread ID */ +#define PKG_ID_MICROCODE_REV 0x0004 /* CPU Microcode Update Revision */ +#define PKG_ID_MACHINE_CHECK_STATUS 0x0005 /* Machine Check Status */ + +/* RdPkgConfig Index */ +#define MBX_INDEX_CPU_ID 0 /* Package Identifier Read */ +#define MBX_INDEX_VR_DEBUG 1 /* VR Debug */ +#define MBX_INDEX_PKG_TEMP_READ 2 /* Package Temperature Read */ +#define MBX_INDEX_ENERGY_COUNTER 3 /* Energy counter */ +#define MBX_INDEX_ENERGY_STATUS 4 /* DDR Energy Status */ +#define MBX_INDEX_WAKE_MODE_BIT 5 /* "Wake on PECI" Mode bit */ +#define MBX_INDEX_EPI 6 /* Efficient Performance Indication */ +#define MBX_INDEX_PKG_RAPL_PERF 8 /* Pkg RAPL Performance Status Read */ +#define MBX_INDEX_PER_CORE_DTS_TEMP 9 /* Per Core DTS Temperature Read */ +#define MBX_INDEX_DTS_MARGIN 10 /* DTS thermal margin */ +#define MBX_INDEX_SKT_PWR_THRTL_DUR 11 /* Socket Power Throttled Duration */ +#define MBX_INDEX_CFG_TDP_CONTROL 12 /* TDP Config Control */ +#define MBX_INDEX_CFG_TDP_LEVELS 13 /* TDP Config Levels */ +#define MBX_INDEX_DDR_DIMM_TEMP 14 /* DDR DIMM Temperature */ +#define MBX_INDEX_CFG_ICCMAX 15 /* Configurable ICCMAX */ +#define MBX_INDEX_TEMP_TARGET 16 /* Temperature Target Read */ +#define MBX_INDEX_CURR_CFG_LIMIT 17 /* Current Config Limit */ +#define MBX_INDEX_DIMM_TEMP_READ 20 /* Package Thermal Status Read */ +#define MBX_INDEX_DRAM_IMC_TMP_READ 22 /* DRAM IMC Temperature Read */ +#define MBX_INDEX_DDR_CH_THERM_STAT 23 /* DDR Channel Thermal Status */ +#define MBX_INDEX_PKG_POWER_LIMIT1 26 /* Package Power Limit1 */ +#define MBX_INDEX_PKG_POWER_LIMIT2 27 /* Package Power Limit2 */ +#define MBX_INDEX_TDP 28 /* Thermal design power minimum */ +#define MBX_INDEX_TDP_HIGH 29 /* Thermal design power maximum */ +#define MBX_INDEX_TDP_UNITS 30 /* Units for power/energy registers */ +#define MBX_INDEX_RUN_TIME 31 /* Accumulated Run Time */ +#define MBX_INDEX_CONSTRAINED_TIME 32 /* Thermally Constrained Time Read */ +#define MBX_INDEX_TURBO_RATIO 33 /* Turbo Activation Ratio */ +#define MBX_INDEX_DDR_RAPL_PL1 34 /* DDR RAPL PL1 */ +#define MBX_INDEX_DDR_PWR_INFO_HIGH 35 /* DRAM Power Info Read (high) */ +#define MBX_INDEX_DDR_PWR_INFO_LOW 36 /* DRAM Power Info Read (low) */ +#define MBX_INDEX_DDR_RAPL_PL2 37 /* DDR RAPL PL2 */ +#define MBX_INDEX_DDR_RAPL_STATUS 38 /* DDR RAPL Performance Status */ +#define MBX_INDEX_DDR_HOT_ABSOLUTE 43 /* DDR Hottest Dimm Absolute Temp */ +#define MBX_INDEX_DDR_HOT_RELATIVE 44 /* DDR Hottest Dimm Relative Temp */ +#define MBX_INDEX_DDR_THROTTLE_TIME 45 /* DDR Throttle Time */ +#define MBX_INDEX_DDR_THERM_STATUS 46 /* DDR Thermal Status */ +#define MBX_INDEX_TIME_AVG_TEMP 47 /* Package time-averaged temperature */ +#define MBX_INDEX_TURBO_RATIO_LIMIT 49 /* Turbo Ratio Limit Read */ +#define MBX_INDEX_HWP_AUTO_OOB 53 /* HWP Autonomous Out-of-band */ +#define MBX_INDEX_DDR_WARM_BUDGET 55 /* DDR Warm Power Budget */ +#define MBX_INDEX_DDR_HOT_BUDGET 56 /* DDR Hot Power Budget */ +#define MBX_INDEX_PKG_PSYS_PWR_LIM3 57 /* Package/Psys Power Limit3 */ +#define MBX_INDEX_PKG_PSYS_PWR_LIM1 58 /* Package/Psys Power Limit1 */ +#define MBX_INDEX_PKG_PSYS_PWR_LIM2 59 /* Package/Psys Power Limit2 */ +#define MBX_INDEX_PKG_PSYS_PWR_LIM4 60 /* Package/Psys Power Limit4 */ +#define MBX_INDEX_PERF_LIMIT_REASON 65 /* Performance Limit Reasons */ + +/* WrPkgConfig Index */ +#define MBX_INDEX_DIMM_AMBIENT 19 +#define MBX_INDEX_DIMM_TEMP 24 + +/* Device Specific Completion Code (CC) Definition */ +#define DEV_PECI_CC_SUCCESS 0x40 +#define DEV_PECI_CC_TIMEOUT 0x80 +#define DEV_PECI_CC_OUT_OF_RESOURCE 0x81 +#define DEV_PECI_CC_UNAVAIL_RESOURCE 0x82 +#define DEV_PECI_CC_INVALID_REQ 0x90 + +/* Completion Code mask to check retry needs */ +#define DEV_PECI_CC_RETRY_CHECK_MASK 0xf0 +#define DEV_PECI_CC_NEED_RETRY 0x80 + +/* Skylake EDS says to retry for 250ms */ +#define DEV_PECI_RETRY_TIME_MS 250 +#define DEV_PECI_RETRY_INTERVAL_USEC 10000 +#define DEV_PECI_RETRY_BIT 0x01 + +#define GET_TEMP_WR_LEN 1 +#define GET_TEMP_RD_LEN 2 +#define GET_TEMP_PECI_CMD 0x01 + +#define GET_DIB_WR_LEN 1 +#define GET_DIB_RD_LEN 8 +#define GET_DIB_PECI_CMD 0xf7 + +#define RDPKGCFG_WRITE_LEN 5 +#define RDPKGCFG_READ_LEN_BASE 1 +#define RDPKGCFG_PECI_CMD 0xa1 + +#define WRPKGCFG_WRITE_LEN_BASE 6 +#define WRPKGCFG_READ_LEN 1 +#define WRPKGCFG_PECI_CMD 0xa5 + +#define RDIAMSR_WRITE_LEN 5 +#define RDIAMSR_READ_LEN 9 +#define RDIAMSR_PECI_CMD 0xb1 + +#define WRIAMSR_PECI_CMD 0xb5 + +#define RDPCICFG_WRITE_LEN 6 +#define RDPCICFG_READ_LEN 5 +#define RDPCICFG_PECI_CMD 0x61 + +#define WRPCICFG_PECI_CMD 0x65 + +#define RDPCICFGLOCAL_WRITE_LEN 5 +#define RDPCICFGLOCAL_READ_LEN_BASE 1 +#define RDPCICFGLOCAL_PECI_CMD 0xe1 + +#define WRPCICFGLOCAL_WRITE_LEN_BASE 6 +#define WRPCICFGLOCAL_READ_LEN 1 +#define WRPCICFGLOCAL_PECI_CMD 0xe5 + +#define PECI_BUFFER_SIZE 32 + +/** + * enum peci_cmd - PECI client commands + * @PECI_CMD_XFER: raw PECI transfer + * @PECI_CMD_PING: ping, a required message for all PECI devices + * @PECI_CMD_GET_DIB: get DIB (Device Info Byte) + * @PECI_CMD_GET_TEMP: get maximum die temperature + * @PECI_CMD_RD_PKG_CFG: read access to the PCS (Package Configuration Space) + * @PECI_CMD_WR_PKG_CFG: write access to the PCS (Package Configuration Space) + * @PECI_CMD_RD_IA_MSR: read access to MSRs (Model Specific Registers) + * @PECI_CMD_WR_IA_MSR: write access to MSRs (Model Specific Registers) + * @PECI_CMD_RD_PCI_CFG: sideband read access to the PCI configuration space + * maintained in downstream devices external to the processor + * @PECI_CMD_WR_PCI_CFG: sideband write access to the PCI configuration space + * maintained in downstream devices external to the processor + * @PECI_CMD_RD_PCI_CFG_LOCAL: sideband read access to the PCI configuration + * space that resides within the processor + * @PECI_CMD_WR_PCI_CFG_LOCAL: sideband write access to the PCI configuration + * space that resides within the processor + * + * Available commands depend on client's PECI revision. + */ +enum peci_cmd { + PECI_CMD_XFER = 0, + PECI_CMD_PING, + PECI_CMD_GET_DIB, + PECI_CMD_GET_TEMP, + PECI_CMD_RD_PKG_CFG, + PECI_CMD_WR_PKG_CFG, + PECI_CMD_RD_IA_MSR, + PECI_CMD_WR_IA_MSR, + PECI_CMD_RD_PCI_CFG, + PECI_CMD_WR_PCI_CFG, + PECI_CMD_RD_PCI_CFG_LOCAL, + PECI_CMD_WR_PCI_CFG_LOCAL, + PECI_CMD_MAX +}; + +/** + * struct peci_xfer_msg - raw PECI transfer command + * @addr; address of the client + * @tx_len: number of data to be written in bytes + * @rx_len: number of data to be read in bytes + * @tx_buf: data to be written, or NULL + * @rx_buf: data to be read, or NULL + * + * raw PECI transfer + */ +struct peci_xfer_msg { + __u8 addr; + __u8 tx_len; + __u8 rx_len; + __u8 tx_buf[PECI_BUFFER_SIZE]; + __u8 rx_buf[PECI_BUFFER_SIZE]; +} __attribute__((__packed__)); + +/** + * struct peci_ping_msg - ping command + * @addr: address of the client + * + * Ping() is a required message for all PECI devices. This message is used to + * enumerate devices or determine if a device has been removed, been + * powered-off, etc. + */ +struct peci_ping_msg { + __u8 addr; +} __attribute__((__packed__)); + +/** + * struct peci_get_dib_msg - GetDIB command + * @addr: address of the client + * @dib: DIB data to be read + * + * The processor PECI client implementation of GetDIB() includes an 8-byte + * response and provides information regarding client revision number and the + * number of supported domains. All processor PECI clients support the GetDIB() + * command. + */ +struct peci_get_dib_msg { + __u8 addr; + __u64 dib; +} __attribute__((__packed__)); + +/** + * struct peci_get_temp_msg - GetTemp command + * @addr: address of the client + * @temp_raw: raw temperature data to be read + * + * The GetTemp() command is used to retrieve the maximum die temperature from a + * target PECI address. The temperature is used by the external thermal + * management system to regulate the temperature on the die. The data is + * returned as a negative value representing the number of degrees centigrade + * below the maximum processor junction temperature. + */ +struct peci_get_temp_msg { + __u8 addr; + __s16 temp_raw; +} __attribute__((__packed__)); + +/** + * struct peci_rd_pkg_cfg_msg - RdPkgConfig command + * @addr: address of the client + * @index: encoding index for the requested service + * @param: specific data being requested + * @rx_len: number of data to be read in bytes + * @pkg_config: package config data to be read + * + * The RdPkgConfig() command provides read access to the Package Configuration + * Space (PCS) within the processor, including various power and thermal + * management functions. Typical PCS read services supported by the processor + * may include access to temperature data, energy status, run time information, + * DIMM temperatures and so on. + */ +struct peci_rd_pkg_cfg_msg { + __u8 addr; + __u8 index; + __u16 param; + __u8 rx_len; + __u8 pkg_config[4]; +} __attribute__((__packed__)); + +/** + * struct peci_wr_pkg_cfg_msg - WrPkgConfig command + * @addr: address of the client + * @index: encoding index for the requested service + * @param: specific data being requested + * @tx_len: number of data to be written in bytes + * @value: package config data to be written + * + * The WrPkgConfig() command provides write access to the Package Configuration + * Space (PCS) within the processor, including various power and thermal + * management functions. Typical PCS write services supported by the processor + * may include power limiting, thermal averaging constant programming and so on. + */ +struct peci_wr_pkg_cfg_msg { + __u8 addr; + __u8 index; + __u16 param; + __u8 tx_len; + __u32 value; +} __attribute__((__packed__)); + +/** + * struct peci_rd_ia_msr_msg - RdIAMSR command + * @addr: address of the client + * @thread_id: ID of the specific logical processor + * @address: address of MSR to read from + * @value: data to be read + * + * The RdIAMSR() PECI command provides read access to Model Specific Registers + * (MSRs) defined in the processor's Intel Architecture (IA). + */ +struct peci_rd_ia_msr_msg { + __u8 addr; + __u8 thread_id; + __u16 address; + __u64 value; +} __attribute__((__packed__)); + +/** + * struct peci_rd_pci_cfg_msg - RdPCIConfig command + * @addr: address of the client + * @bus: PCI bus number + * @device: PCI device number + * @function: specific function to read from + * @reg: specific register to read from + * @pci_config: config data to be read + * + * The RdPCIConfig() command provides sideband read access to the PCI + * configuration space maintained in downstream devices external to the + * processor. + */ +struct peci_rd_pci_cfg_msg { + __u8 addr; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + __u8 pci_config[4]; +} __attribute__((__packed__)); + +/** + * struct peci_rd_pci_cfg_local_msg - RdPCIConfigLocal command + * @addr: address of the client + * @bus: PCI bus number + * @device: PCI device number + * @function: specific function to read from + * @reg: specific register to read from + * @rx_len: number of data to be read in bytes + * @pci_config: config data to be read + * + * The RdPCIConfigLocal() command provides sideband read access to the PCI + * configuration space that resides within the processor. This includes all + * processor IIO and uncore registers within the PCI configuration space. + */ +struct peci_rd_pci_cfg_local_msg { + __u8 addr; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + __u8 rx_len; + __u8 pci_config[4]; +} __attribute__((__packed__)); + +/** + * struct peci_wr_pci_cfg_local_msg - WrPCIConfigLocal command + * @addr: address of the client + * @bus: PCI bus number + * @device: PCI device number + * @function: specific function to read from + * @reg: specific register to read from + * @tx_len: number of data to be written in bytes + * @value: config data to be written + * + * The WrPCIConfigLocal() command provides sideband write access to the PCI + * configuration space that resides within the processor. PECI originators can + * access this space even before BIOS enumeration of the system buses. + */ +struct peci_wr_pci_cfg_local_msg { + __u8 addr; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + __u8 tx_len; + __u32 value; +} __attribute__((__packed__)); + +#define PECI_IOC_BASE 0xb7 + +#define PECI_IOC_XFER \ + _IOWR(PECI_IOC_BASE, PECI_CMD_XFER, struct peci_xfer_msg) + +#define PECI_IOC_PING \ + _IOWR(PECI_IOC_BASE, PECI_CMD_PING, struct peci_ping_msg) + +#define PECI_IOC_GET_DIB \ + _IOWR(PECI_IOC_BASE, PECI_CMD_GET_DIB, struct peci_get_dib_msg) + +#define PECI_IOC_GET_TEMP \ + _IOWR(PECI_IOC_BASE, PECI_CMD_GET_TEMP, struct peci_get_temp_msg) + +#define PECI_IOC_RD_PKG_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PKG_CFG, struct peci_rd_pkg_cfg_msg) + +#define PECI_IOC_WR_PKG_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PKG_CFG, struct peci_wr_pkg_cfg_msg) + +#define PECI_IOC_RD_IA_MSR \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSR, struct peci_rd_ia_msr_msg) + +#define PECI_IOC_RD_PCI_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG, struct peci_rd_pci_cfg_msg) + +#define PECI_IOC_RD_PCI_CFG_LOCAL \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG_LOCAL, \ + struct peci_rd_pci_cfg_local_msg) + +#define PECI_IOC_WR_PCI_CFG_LOCAL \ + _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG_LOCAL, \ + struct peci_wr_pci_cfg_local_msg) + +#endif /* __PECI_IOCTL_H */ |