diff options
Diffstat (limited to 'Documentation/devicetree/bindings/mailbox')
5 files changed, 120 insertions, 51 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml new file mode 100644 index 000000000000..319280563648 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 BayLibre, SAS +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Amlogic Meson Message-Handling-Unit Controller + +maintainers: + - Neil Armstrong <narmstrong@baylibre.com> + +description: | + The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller + that has 3 independent channels/links to communicate with remote processor(s). + MHU links are hardwired on a platform. A link raises interrupt for any + received data. However, there is no specified way of knowing if the sent + data has been read by the remote. This driver assumes the sender polls + STAT register and the remote clears it after having read the data. + +properties: + compatible: + enum: + - amlogic,meson-gxbb-mhu + + reg: + maxItems: 1 + + interrupts: + minItems: 3 + description: + Contains the interrupt information corresponding to each of the 3 links + of MHU. + + "#mbox-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +examples: + - | + mailbox@c883c404 { + compatible = "amlogic,meson-gxbb-mhu"; + reg = <0xc883c404 0x4c>; + interrupts = <208>, <209>, <210>; + #mbox-cells = <1>; + }; + diff --git a/Documentation/devicetree/bindings/mailbox/meson-mhu.txt b/Documentation/devicetree/bindings/mailbox/meson-mhu.txt deleted file mode 100644 index a530310772b9..000000000000 --- a/Documentation/devicetree/bindings/mailbox/meson-mhu.txt +++ /dev/null @@ -1,34 +0,0 @@ -Amlogic Meson MHU Mailbox Driver -================================ - -The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller -that has 3 independent channels/links to communicate with remote processor(s). -MHU links are hardwired on a platform. A link raises interrupt for any -received data. However, there is no specified way of knowing if the sent -data has been read by the remote. This driver assumes the sender polls -STAT register and the remote clears it after having read the data. - -Mailbox Device Node: -==================== - -Required properties: --------------------- -- compatible: Shall be "amlogic,meson-gxbb-mhu" -- reg: Contains the mailbox register address range (base - address and length) -- #mbox-cells Shall be 1 - the index of the channel needed. -- interrupts: Contains the interrupt information corresponding to - each of the 2 links of MHU. - -Example: --------- - - mailbox: mailbox@c883c404 { - #mbox-cells = <1>; - compatible = "amlogic,meson-gxbb-mhu"; - reg = <0 0xc883c404 0 0x4c>; - interrupts = <0 208 IRQ_TYPE_EDGE_RISING>, - <0 209 IRQ_TYPE_EDGE_RISING>, - <0 210 IRQ_TYPE_EDGE_RISING>; - #mbox-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt index 7d72b21c9e94..7b13787ab13d 100644 --- a/Documentation/devicetree/bindings/mailbox/mtk-gce.txt +++ b/Documentation/devicetree/bindings/mailbox/mtk-gce.txt @@ -9,7 +9,7 @@ CMDQ driver uses mailbox framework for communication. Please refer to mailbox.txt for generic information about mailbox device-tree bindings. Required properties: -- compatible: Must be "mediatek,mt8173-gce" +- compatible: can be "mediatek,mt8173-gce" or "mediatek,mt8183-gce" - reg: Address range of the GCE unit - interrupts: The interrupt signal from the GCE block - clock: Clocks according to the common clock binding @@ -25,11 +25,19 @@ Required properties: Required properties for a client device: - mboxes: Client use mailbox to communicate with GCE, it should have this property and list of phandle, mailbox specifiers. -- mediatek,gce-subsys: u32, specify the sub-system id which is corresponding - to the register address. +Optional properties for a client device: +- mediatek,gce-client-reg: Specify the sub-system id which is corresponding + to the register address, it should have this property and list of phandle, + sub-system specifiers. + <&phandle subsys_number start_offset size> + phandle: Label name of a gce node. + subsys_number: specify the sub-system id which is corresponding + to the register address. + start_offset: the start offset of register address that GCE can access. + size: the total size of register address that GCE can access. -Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h'. Such as -sub-system ids, thread priority, event ids. +Some vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h' +or 'dt-binding/gce/mt8183-gce.h'. Such as sub-system ids, thread priority, event ids. Example: @@ -39,7 +47,6 @@ Example: interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; clocks = <&infracfg CLK_INFRA_GCE>; clock-names = "gce"; - thread-num = CMDQ_THR_MAX_COUNT; #mbox-cells = <3>; }; @@ -49,9 +56,9 @@ Example for a client device: compatible = "mediatek,mt8173-mmsys"; mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST 1>, <&gce 1 CMDQ_THR_PRIO_LOWEST 1>; - mediatek,gce-subsys = <SUBSYS_1400XXXX>; mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF CMDQ_EVENT_MUTEX1_STREAM_EOF>; - + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>, + <&gce SUBSYS_1401XXXX 0x2000 0x100>; ... }; diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt index 0ef372656a3e..35c3f56b7f7b 100644 --- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt +++ b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt @@ -1,4 +1,4 @@ -OMAP2+ Mailbox Driver +OMAP2+ and K3 Mailbox ===================== The OMAP mailbox hardware facilitates communication between different processors @@ -7,7 +7,7 @@ various processor subsystems and is connected on an interconnect bus. The communication is achieved through a set of registers for message storage and interrupt configuration registers. -Each mailbox IP block has a certain number of h/w fifo queues and output +Each mailbox IP block/cluster has a certain number of h/w fifo queues and output interrupt lines. An output interrupt line is routed to an interrupt controller within a processor subsystem, and there can be more than one line going to a specific processor's interrupt controller. The interrupt line connections are @@ -23,12 +23,16 @@ All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP instance. DRA7xx has multiple instances with different number of h/w fifo queues and interrupt lines between different instances. The interrupt lines can also be routed to different processor sub-systems on DRA7xx as they are routed through -the Crossbar, a kind of interrupt router/multiplexer. +the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E +SoCs has each of these instances form a cluster and combine multiple clusters +into a single IP block present within the Main NavSS. The interrupt lines from +all these clusters are multiplexed and routed to different processor subsystems +over a limited number of common interrupt output lines of an Interrupt Router. Mailbox Device Node: ==================== -A Mailbox device node is used to represent a Mailbox IP instance within a SoC. -The sub-mailboxes are represented as child nodes of this parent node. +A Mailbox device node is used to represent a Mailbox IP instance/cluster within +a SoC. The sub-mailboxes are represented as child nodes of this parent node. Required properties: -------------------- @@ -37,12 +41,12 @@ Required properties: "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs + "ti,am654-mailbox" for K3 AM65x and J721E SoCs - reg: Contains the mailbox register address range (base address and length) - interrupts: Contains the interrupt information for the mailbox device. The format is dependent on which interrupt - controller the OMAP device uses -- ti,hwmods: Name of the hwmod associated with the mailbox + controller the Mailbox device uses - #mbox-cells: Common mailbox binding property to identify the number of cells required for the mailbox specifier. Should be 1 @@ -50,6 +54,23 @@ Required properties: device can interrupt - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block +SoC-specific Required properties: +--------------------------------- +The following are mandatory properties for the OMAP architecture based SoCs +only: +- ti,hwmods: Name of the hwmod associated with the mailbox. This + should be defined in the mailbox node only if the node + is not defined as a child node of a corresponding sysc + interconnect node. + +The following are mandatory properties for the K3 AM65x and J721E SoCs only: +- interrupt-parent: Should contain a phandle to the TI-SCI interrupt + controller node that is used to dynamically program + the interrupt routes between the IP and the main GIC + controllers. See the following binding for additional + details, + Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt + Child Nodes: ============ A child node is used for representing the actual sub-mailbox device that is @@ -98,7 +119,7 @@ to be used by the client user. Example: -------- -/* OMAP4 */ +1. /* OMAP4 */ mailbox: mailbox@4a0f4000 { compatible = "ti,omap4-mailbox"; reg = <0x4a0f4000 0x200>; @@ -123,7 +144,7 @@ dsp { ... }; -/* AM33xx */ +2. /* AM33xx */ mailbox: mailbox@480c8000 { compatible = "ti,omap4-mailbox"; reg = <0x480C8000 0x200>; @@ -137,3 +158,23 @@ mailbox: mailbox@480c8000 { ti,mbox-rx = <0 0 3>; }; }; + +3. /* AM65x */ +&cbass_main { + cbass_main_navss: interconnect0 { + mailbox0_cluster0: mailbox@31f80000 { + compatible = "ti,am654-mailbox"; + reg = <0x00 0x31f80000 0x00 0x200>; + #mbox-cells = <1>; + ti,mbox-num-users = <4>; + ti,mbox-num-fifos = <16>; + interrupt-parent = <&intr_main_navss>; + interrupts = <164 0>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx = <1 0 0>; + ti,mbox-rx = <0 0 0>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index 1232fc9fc709..0278482af65c 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -12,7 +12,10 @@ platforms. "qcom,msm8996-apcs-hmss-global" "qcom,msm8998-apcs-hmss-global" "qcom,qcs404-apcs-apps-global" + "qcom,sc7180-apss-shared" "qcom,sdm845-apss-shared" + "qcom,sm8150-apss-shared" + "qcom,ipq8074-apcs-apps-global" - reg: Usage: required |