diff options
Diffstat (limited to 'Documentation')
28 files changed, 1538 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/jtag-dev b/Documentation/ABI/testing/jtag-dev new file mode 100644 index 000000000000..423baab18761 --- /dev/null +++ b/Documentation/ABI/testing/jtag-dev @@ -0,0 +1,23 @@ +What: /dev/jtag[0-9]+ +Date: July 2018 +KernelVersion: 4.20 +Contact: oleksandrs@mellanox.com +Description: + The misc device files /dev/jtag* are the interface + between JTAG master interface and userspace. + + The ioctl(2)-based ABI is defined and documented in + [include/uapi]<linux/jtag.h>. + + The following file operations are supported: + + open(2) + Opens and allocates file descriptor. + + ioctl(2) + Initiate various actions. + See the inline documentation in [include/uapi]<linux/jtag.h> + for descriptions of all ioctls. + +Users: + userspace tools which wants to access to JTAG bus diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml index ea643e6c3ef5..e334ad7f80c0 100644 --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml @@ -49,6 +49,33 @@ properties: description: states that there is another master active on this bus + bus-timeout-ms: + default: 1000 + description: + bus timeout in milliseconds defaults to 1 second when not specified + + #retries: + description: + Number of retries for master transfer + + aspeed,dma-buf-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + size of DMA buffer (from 2 to 4095 in case of AST2500) + Only AST2500/2600 support DMA mode. + Limitations on AST2500 - I2C is sharing the DMA H/W with UHCI host + controller and MCTP controller. Since those controllers operate with DMA + mode only, I2C has to use buffer mode or byte mode instead if one of + those controllers is enabled. Also make sure that if SD/eMMC or Port80 + snoop uses DMA mode instead of PIO or FIFO respectively, I2C can't use + DMA mode. IF both DMA and buffer modes are enabled, DMA mode will be + selected. + + general-call: + type: boolean + description: + enables general call receiving + required: - reg - compatible diff --git a/Documentation/devicetree/bindings/i2c/i2c.txt b/Documentation/devicetree/bindings/i2c/i2c.txt index fc3dd7ec0445..1f9c8d0e3d62 100644 --- a/Documentation/devicetree/bindings/i2c/i2c.txt +++ b/Documentation/devicetree/bindings/i2c/i2c.txt @@ -137,6 +137,12 @@ wants to support one of the below features, it should adapt these bindings. - wakeup-source device can be used as a wakeup source. +- bus-timeout-ms + Bus timeout in milliseconds. + +- #retries + Number of retries for master transfer. + Binding may contain optional "interrupts" property, describing interrupts used by the device. I2C core will assign "irq" interrupt (or the very first interrupt if not using interrupt names) as primary interrupt for the slave. diff --git a/Documentation/devicetree/bindings/i3c/i3c.yaml b/Documentation/devicetree/bindings/i3c/i3c.yaml index 1f82fc923799..b220a3a90bc5 100644 --- a/Documentation/devicetree/bindings/i3c/i3c.yaml +++ b/Documentation/devicetree/bindings/i3c/i3c.yaml @@ -55,6 +55,24 @@ properties: May not be supported by all controllers. + initial-role: + enum: + - primary + - secondary + - target + description: | + If it is not specified, by default the initial I3C device role will be "primary". + + pid: + $ref: '/schemas/types.yaml#/definitions/uint64' + description: | + Target Device Provisioned ID + + dcr: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: | + Target Device Characteristic Register value + required: - "#address-cells" - "#size-cells" diff --git a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt index 07f35f36085d..1409ea495e79 100644 --- a/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt +++ b/Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.txt @@ -20,6 +20,21 @@ Documentation/devicetree/bindings/i3c/i3c.yaml for more details): - i2c-scl-hz - i3c-scl-hz +Optional properties specific for this driver: + +- i3c-od-scl-low-ns: SCL low period for Open-Drain phase. Expressed in + nanoseconds. It is validated by the driver. Minimum value is 200. +- i3c-od-scl-high-ns: SCL high period for Open-Drain phase. Expressed in + nanoseconds. It is validated by the driver. Minimum value is 25. +- i3c-pp-scl-low-ns: SCL low period for Push-Pull phase. Expressed in + nanoseconds. It is validated by the driver. Minimum value is 25. +- i3c-pp-scl-high-ns: SCL high period for Push-Pull phase. It is expressed in + nanoseconds. It is validated by the driver. Minimum value is 25. +- sda-tx-hold-ns: SDA Hold Time (Thd_dat). Expressed in nanoseconds. It is not + validated by driver. Minimum value is 5. Maximum value is 35. Other + values will be trimmed to the range. This parameter is not supported by + old IP versions. + I3C device connected on the bus follow the generic description (see Documentation/devicetree/bindings/i3c/i3c.yaml for more details). diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml index 4ff6fabfcb30..6a6e4f6a772c 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml @@ -40,6 +40,9 @@ properties: - description: ODR register - description: STR register + clocks: + minItems: 1 + aspeed,lpc-io-reg: $ref: '/schemas/types.yaml#/definitions/uint32-array' minItems: 1 @@ -74,6 +77,7 @@ properties: required: - compatible - interrupts + - clocks additionalProperties: false @@ -103,4 +107,5 @@ examples: aspeed,lpc-io-reg = <0xca2>; aspeed,lpc-interrupts = <11 IRQ_TYPE_LEVEL_LOW>; interrupts = <8>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; }; diff --git a/Documentation/devicetree/bindings/jtag/aspeed-jtag.yaml b/Documentation/devicetree/bindings/jtag/aspeed-jtag.yaml new file mode 100644 index 000000000000..26faec29a5fb --- /dev/null +++ b/Documentation/devicetree/bindings/jtag/aspeed-jtag.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/jtag/aspeed-jtag.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed JTAG driver for ast2400, ast2500 and ast2600 SoC + +description: + Driver adds support of Aspeed 24/25/2600 series SOC JTAG master controller. + Driver implements the following jtag ops + freq_get + freq_set + status_get + status_set + xfer + mode_set + bitbang + enable + disable + + It has been tested on Mellanox system with BMC equipped with + Aspeed 2520 SoC for programming CPLD devices. + + It has also been tested on Intel system using Aspeed 25xx SoC + for JTAG communication. + + Tested on Intel system using Aspeed 26xx SoC for JTAG communication. + +maintainers: + - Oleksandr Shamray <oleksandrs@mellanox.com> + - Jiri Pirko <jiri@mellanox.com> + - Ernesto Corona<ernesto.corona@intel.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - aspeed,ast2400-jtag + - aspeed,ast2500-jtag + - aspeed,ast2600-jtag + + + reg: + items: + - description: JTAG Master controller register range + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + + jtag: jtag@1e6e4000 { + compatible = "aspeed,ast2500-jtag"; + reg = <0x1e6e4000 0x1c>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_JTAG_MASTER>; + interrupts = <43>; + }; + - | + #include <dt-bindings/clock/aspeed-clock.h> + #include <dt-bindings/interrupt-controller/irq.h> + + jtag1: jtag@1e6e4100 { + compatible = "aspeed,ast2600-jtag"; + reg = <0x1e6e4100 0x40>; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_JTAG_MASTER2>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + }; + +... diff --git a/Documentation/devicetree/bindings/mfd/intel,peci-client.yaml b/Documentation/devicetree/bindings/mfd/intel,peci-client.yaml new file mode 100644 index 000000000000..7baddce0a92c --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/intel,peci-client.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/intel,peci-client.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel PECI Client Device Tree Bindings + +maintainers: + - Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +description: | + PECI (Platform Environment Control Interface) is a one-wire bus interface + that provides a communication channel from PECI clients in Intel processors + and chipset components to external monitoring or control devices. PECI is + designed to support the following sideband functions: + - Processor and DRAM thermal management + - Platform Manageability + - Processor Interface Tuning and Diagnostics + - Failure Analysis + +properties: + compatible: + const: intel,peci-client + + reg: + description: | + Address of a client CPU. According to the PECI specification, client + addresses start from 0x30. + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + peci: bus@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + + peci0: peci-bus@0 { + compatible = "aspeed,ast2600-peci"; + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + + peci-client@30 { + compatible = "intel,peci-client"; + reg = <0x30>; + }; + + peci-client@31 { + compatible = "intel,peci-client"; + reg = <0x31>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/peci/peci-aspeed.yaml b/Documentation/devicetree/bindings/peci/peci-aspeed.yaml new file mode 100644 index 000000000000..0f5c2993fe9b --- /dev/null +++ b/Documentation/devicetree/bindings/peci/peci-aspeed.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/peci/peci-aspeed.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed PECI Bus Device Tree Bindings + +maintainers: + - Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +properties: + compatible: + enum: + - aspeed,ast2400-peci + - aspeed,ast2500-peci + - aspeed,ast2600-peci + + reg: + maxItems: 1 + + "#address-cells": + # Required to define a client address. + const: 1 + + "#size-cells": + # Required to define a client address. + const: 0 + + interrupts: + maxItems: 1 + + clocks: + description: | + Clock source for PECI controller. Should reference the external + oscillator clock. + maxItems: 1 + + resets: + maxItems: 1 + + clock-frequency: + # Operation frequency of PECI controller in units of Hz. + minimum: 187500 + maximum: 24000000 + + msg-timing: + description: | + Message timing negotiation period. This value will determine the period + of message timing negotiation to be issued by PECI controller. The unit + of the programmed value is four times of PECI clock period. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 255 + default: 1 + + addr-timing: + description: | + Address timing negotiation period. This value will determine the period + of address timing negotiation to be issued by PECI controller. The unit + of the programmed value is four times of PECI clock period. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 255 + default: 1 + + rd-sampling-point: + description: | + Read sampling point selection. The whole period of a bit time will be + divided into 16 time frames. This value will determine the time frame + in which the controller will sample PECI signal for data read back. + Usually in the middle of a bit time is the best. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 15 + default: 8 + + cmd-timeout-ms: + # Command timeout in units of ms. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + maximum: 60000 + default: 1000 + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + - clocks + - resets + - clock-frequency + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + peci: bus@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + + peci0: peci-bus@0 { + compatible = "aspeed,ast2600-peci"; + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + msg-timing = <1>; + addr-timing = <1>; + rd-sampling-point = <8>; + cmd-timeout-ms = <1000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/peci/peci-bus.yaml b/Documentation/devicetree/bindings/peci/peci-bus.yaml new file mode 100644 index 000000000000..b085e67089cf --- /dev/null +++ b/Documentation/devicetree/bindings/peci/peci-bus.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/peci/peci-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Device Tree Bindings for PECI bus + +maintainers: + - Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +description: | + PECI (Platform Environment Control Interface) is a one-wire bus interface that + provides a communication channel from Intel processors and chipset components + to external monitoring or control devices. PECI is designed to support the + following sideband functions: + + * Processor and DRAM thermal management + - Processor fan speed control is managed by comparing Digital Thermal + Sensor (DTS) thermal readings acquired via PECI against the + processor-specific fan speed control reference point, or TCONTROL. Both + TCONTROL and DTS thermal readings are accessible via the processor PECI + client. These variables are referenced to a common temperature, the TCC + activation point, and are both defined as negative offsets from that + reference. + - PECI based access to the processor package configuration space provides + a means for Baseboard Management Controllers (BMC) or other platform + management devices to actively manage the processor and memory power + and thermal features. + + * Platform Manageability + - Platform manageability functions including thermal, power, and error + monitoring. Note that platform 'power' management includes monitoring + and control for both the processor and DRAM subsystem to assist with + data center power limiting. + - PECI allows read access to certain error registers in the processor MSR + space and status monitoring registers in the PCI configuration space + within the processor and downstream devices. + - PECI permits writes to certain registers in the processor PCI + configuration space. + + * Processor Interface Tuning and Diagnostics + - Processor interface tuning and diagnostics capabilities + (Intel Interconnect BIST). The processors Intel Interconnect Built In + Self Test (Intel IBIST) allows for infield diagnostic capabilities in + the Intel UPI and memory controller interfaces. PECI provides a port to + execute these diagnostics via its PCI Configuration read and write + capabilities. + + * Failure Analysis + - Output the state of the processor after a failure for analysis via + Crashdump. + + PECI uses a single wire for self-clocking and data transfer. The bus + requires no additional control lines. The physical layer is a self-clocked + one-wire bus that begins each bit with a driven, rising edge from an idle + level near zero volts. The duration of the signal driven high depends on + whether the bit value is a logic '0' or logic '1'. PECI also includes + variable data transfer rate established with every message. In this way, it + is highly flexible even though underlying logic is simple. + + The interface design was optimized for interfacing between an Intel + processor and chipset components in both single processor and multiple + processor environments. The single wire interface provides low board + routing overhead for the multiple load connections in the congested routing + area near the processor and chipset components. Bus speed, error checking, + and low protocol overhead provides adequate link bandwidth and reliability + to transfer critical device operating conditions and configuration + information. + + PECI subsystem provides single or multiple bus nodes support so each bus can + have one adapter node and multiple device specific client nodes that can be + attached to the PECI bus so each processor client's features can be supported + by the client node through an adapter connection in the bus. + +properties: + compatible: + const: simple-bus + + "#address-cells": + # Required to define bus device control resource address. + const: 1 + + "#size-cells": + # Required to define bus device control resource address. + const: 1 + + ranges: true + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + peci: bus@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x200>; + + peci0: peci-bus@0 { + compatible = "aspeed,ast2600-peci"; + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + }; + + // Just an example. ast2600 doesn't have a second PECI module actually. + peci1: peci-bus@100 { + compatible = "aspeed,ast2600-peci"; + reg = <0x100 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/peci/peci-client.yaml b/Documentation/devicetree/bindings/peci/peci-client.yaml new file mode 100644 index 000000000000..fc7c4110e929 --- /dev/null +++ b/Documentation/devicetree/bindings/peci/peci-client.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/peci/peci-client.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic Device Tree Bindings for PECI clients + +maintainers: + - Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +properties: + compatible: + enum: + - intel,peci-client + + reg: + description: | + Address of a client CPU. According to the PECI specification, client + addresses start from 0x30. + maxItems: 1 + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/ast2600-clock.h> + peci: bus@1e78b000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x1e78b000 0x60>; + + peci0: peci-bus@0 { + compatible = "aspeed,ast2600-peci"; + reg = <0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&syscon ASPEED_CLK_GATE_REF0CLK>; + resets = <&syscon ASPEED_RESET_PECI>; + clock-frequency = <24000000>; + + peci-client@30 { + compatible = "intel,peci-client"; + reg = <0x30>; + }; + + peci-client@31 { + compatible = "intel,peci-client"; + reg = <0x31>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/peci/peci-npcm.yaml b/Documentation/devicetree/bindings/peci/peci-npcm.yaml new file mode 100644 index 000000000000..bcd5626e68e7 --- /dev/null +++ b/Documentation/devicetree/bindings/peci/peci-npcm.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/peci/peci-npcm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM PECI Bus Device Tree Bindings + +maintainers: + - Tomer Maimon <tmaimon77@gmail.com> + +properties: + compatible: + const: nuvoton,npcm750-peci # for the NPCM7XX BMC. + + reg: + maxItems: 1 + + "#address-cells": + # Required to define a client address. + const: 1 + + "#size-cells": + # Required to define a client address. + const: 0 + + interrupts: + maxItems: 1 + + clocks: + # PECI reference clock. + maxItems: 1 + + cmd-timeout-ms: + # Command timeout in units of ms. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + maximum: 60000 + default: 1000 + + pull-down: + description: | + Defines the PECI I/O internal pull down operation. + 0: pull down always enable + 1: pull down only during transactions. + 2: pull down always disable. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + maximum: 2 + default: 0 + + host-neg-bit-rate: + description: | + Define host negotiation bit rate divider. + the host negotiation bit rate calculate with formula: + clock frequency[Hz] / [4 x {host-neg-bit-rate + 1}] + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 7 + maximum: 31 + default: 15 + + high-volt-range: + description: | + Adapts PECI I/O interface to voltage range. + 0: PECI I/O interface voltage range of 0.8-1.06V (default) + 1: PECI I/O interface voltage range of 0.95-1.26V + type: boolean + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - interrupts + - clocks + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + peci: bus@100000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100000 0x200>; + + peci0: peci-bus@0 { + compatible = "nuvoton,npcm750-peci"; + reg = <0x0 0x200>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk NPCM7XX_CLK_APB3>; + cmd-timeout-ms = <1000>; + pull-down = <0>; + host-neg-bit-rate = <15>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed-espi-slave.txt b/Documentation/devicetree/bindings/soc/aspeed/aspeed-espi-slave.txt new file mode 100644 index 000000000000..f72d9ae32f3e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed-espi-slave.txt @@ -0,0 +1,20 @@ +ASPEED eSPI Slave Controller + +Required properties: + - compatible: must be one of: + - "aspeed,ast2500-espi-slave" + - "aspeed,ast2600-espi-slave" + + - reg: physical base address of the controller and length of memory mapped + region + + - interrupts: interrupt generated by the controller + +Example: + + espi: espi@1e6ee000 { + compatible = "aspeed,ast2500-espi-slave"; + reg = <0x1e6ee000 0x100>; + interrupts = <23>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed-lpc-sio.txt b/Documentation/devicetree/bindings/soc/aspeed/aspeed-lpc-sio.txt new file mode 100644 index 000000000000..c74ea3a4e5ac --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed-lpc-sio.txt @@ -0,0 +1,17 @@ +* Aspeed LPC SIO driver. + +Required properties: +- compatible : Should be one of: + "aspeed,ast2400-lpc-sio" + "aspeed,ast2500-lpc-sio" +- reg : Should contain lpc-sio registers location and length +- clocks: contains a phandle to the syscon node describing the clocks. + There should then be one cell representing the clock to use. + +Example: +lpc_sio: lpc-sio@100 { + compatible = "aspeed,ast2500-lpc-sio"; + reg = <0x100 0x20>; + clocks = <&syscon ASPEED_CLK_GATE_LCLK>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed-mctp.txt b/Documentation/devicetree/bindings/soc/aspeed/aspeed-mctp.txt new file mode 100644 index 000000000000..5dc30fdfc53a --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed-mctp.txt @@ -0,0 +1,25 @@ +* Aspeed AST2600 MCTP PCIe VDM Controller + +Required properties: +- compatible : must be "aspeed,ast2600-mctp" +- reg : contains the address and size of the memory region + associated with the MCTP controller +- resets : reset specifier for the syscon reset associated with + the MCTP controller +- interrupts-extended : two interrupt cells; the first specifies the global + interrupt for MCTP controller and the second + specifies the PCIe reset or PERST interrupt +- aspeed,pcieh : a phandle to the PCIe Host Controller node to be + used in conjunction with the PCIe reset or PERST + interrupt +Example: + +mctp: mctp@1e6e8000 { + compatible = "aspeed,ast2600-mctp"; + reg = <0x1e6e8000 0x1000>; + interrupts-extended = <&gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <&scu_ic0 ASPEED_AST2600_SCU_IC0_PCIE_PERST_LO_TO_HI>; + resets = <&syscon ASPEED_RESET_DEV_MCTP>; + aspeed,pcieh = <&pcieh>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/soc/aspeed/aspeed-vga-sharedmem.txt b/Documentation/devicetree/bindings/soc/aspeed/aspeed-vga-sharedmem.txt new file mode 100644 index 000000000000..03f57c53e844 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/aspeed/aspeed-vga-sharedmem.txt @@ -0,0 +1,20 @@ +* Aspeed VGA shared memory driver + +Aspeed VGA shared memory driver allow user to read data from AST2500 +VGA memory. This driver is required by ManagedDataRegionlV2 +specification. In the spec, BIOS will transfer whole SMBIOS table to +VGA memroy and BMC get the table from VGA memory. 0penBMC project do +not allow to use /dev/mem for security concerns. To get the data in +VGA shared memory in user space, implement this driver only allowed +user to mmap limited memory area. + +Required properties: +- compatible: "aspeed,ast2500-vga-sharedmem" + - aspeed,ast2500-vga-sharedmem: Aspeed AST2500 family +- reg: Should contain VGA shared memory start address and length + +Example: +vga-shared-memory { + compatible = "aspeed,ast2500-vga-sharedmem"; + reg = <0x9ff00000 0x100000>; +}; diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index f790f1260c33..7257214e5408 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -153,6 +153,10 @@ Hardware Monitoring Kernel Drivers pc87360 pc87427 pcf8591 + peci-cputemp + peci-dimmtemp + peci-cpupower + peci-dimmpower pim4328 pm6764tr pmbus diff --git a/Documentation/hwmon/peci-cpupower.rst b/Documentation/hwmon/peci-cpupower.rst new file mode 100644 index 000000000000..d3b6a666f076 --- /dev/null +++ b/Documentation/hwmon/peci-cpupower.rst @@ -0,0 +1,65 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver peci-cpupower +========================== + +:Copyright: |copy| 2018-2020 Intel Corporation + +Supported chips: + One of Intel server CPUs listed below which is connected to a PECI bus. + * Intel Xeon E5/E7 v3 server processors + Intel Xeon E5-14xx v3 family + Intel Xeon E5-24xx v3 family + Intel Xeon E5-16xx v3 family + Intel Xeon E5-26xx v3 family + Intel Xeon E5-46xx v3 family + Intel Xeon E7-48xx v3 family + Intel Xeon E7-88xx v3 family + * Intel Xeon E5/E7 v4 server processors + Intel Xeon E5-16xx v4 family + Intel Xeon E5-26xx v4 family + Intel Xeon E5-46xx v4 family + Intel Xeon E7-48xx v4 family + Intel Xeon E7-88xx v4 family + * Intel Xeon Scalable server processors + Intel Xeon D family + Intel Xeon Bronze family + Intel Xeon Silver family + Intel Xeon Gold family + Intel Xeon Platinum family + + Addresses scanned: PECI client address 0x30 - 0x37 + Datasheet: Available from http://www.intel.com/design/literature.htm + +Author: + Zhikui Ren <zhikui.ren@.intel.com> + +Description +----------- + +This driver implements a generic PECI hwmon feature which provides +average power and energy consumption readings of the CPU package based on +energy counter. + +Power values are average power since last measure given in milli Watt and +will be measurable only when the target CPU is powered on. + +Energy values are energy consumption in micro Joules. + +Driver provides current package power limit, maximal (TDP) and minimal power +setting as well. + +All needed processor registers are accessible using the PECI Client Command +Suite via the processor PECI client. + +``sysfs`` interface +------------------- +======================= ======================================================= +power1_label Provides string "cpu power". +power1_average Provides average power since last read in milli Watt. +power1_cap Provides current package power limit 1 (PPL1). +power1_cap_max Provides maximal (TDP) package power setting. +power1_cap_min Provides minimal package power setting. +energy1_label Provides string "cpu energy". +energy1_input Provides energy consumption in micro Joules. +======================= ======================================================= diff --git a/Documentation/hwmon/peci-cputemp.rst b/Documentation/hwmon/peci-cputemp.rst new file mode 100644 index 000000000000..bf08e16dd989 --- /dev/null +++ b/Documentation/hwmon/peci-cputemp.rst @@ -0,0 +1,95 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver peci-cputemp +========================== + +:Copyright: |copy| 2018-2019 Intel Corporation + +Supported chips: + One of Intel server CPUs listed below which is connected to a PECI bus. + * Intel Xeon E5/E7 v3 server processors + Intel Xeon E5-14xx v3 family + Intel Xeon E5-24xx v3 family + Intel Xeon E5-16xx v3 family + Intel Xeon E5-26xx v3 family + Intel Xeon E5-46xx v3 family + Intel Xeon E7-48xx v3 family + Intel Xeon E7-88xx v3 family + * Intel Xeon E5/E7 v4 server processors + Intel Xeon E5-16xx v4 family + Intel Xeon E5-26xx v4 family + Intel Xeon E5-46xx v4 family + Intel Xeon E7-48xx v4 family + Intel Xeon E7-88xx v4 family + * Intel Xeon Scalable server processors + Intel Xeon D family + Intel Xeon Bronze family + Intel Xeon Silver family + Intel Xeon Gold family + Intel Xeon Platinum family + + Addresses scanned: PECI client address 0x30 - 0x37 + Datasheet: Available from http://www.intel.com/design/literature.htm + +Author: + Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +Description +----------- + +This driver implements a generic PECI hwmon feature which provides Digital +Thermal Sensor (DTS) thermal readings of the CPU package and CPU cores that are +accessible using the PECI Client Command Suite via the processor PECI client. + +All temperature values are given in millidegree Celsius and will be measurable +only when the target CPU is powered on. + +``sysfs`` interface +------------------- +======================= ======================================================= +temp1_label "Die" +temp1_input Provides current die temperature of the CPU package. +temp1_max Provides thermal control temperature of the CPU package + which is also known as Tcontrol. +temp1_crit Provides shutdown temperature of the CPU package which + is also known as the maximum processor junction + temperature, Tjmax or Tprochot. +temp1_crit_hyst Provides the hysteresis value from Tcontrol to Tjmax of + the CPU package. + +temp2_label "DTS" +temp2_input Provides current DTS temperature of the CPU package. +temp2_max Provides thermal control temperature of the CPU package + which is also known as Tcontrol. +temp2_crit Provides shutdown temperature of the CPU package which + is also known as the maximum processor junction + temperature, Tjmax or Tprochot. +temp2_crit_hyst Provides the hysteresis value from Tcontrol to Tjmax of + the CPU package. + +temp3_label "Tcontrol" +temp3_input Provides current Tcontrol temperature of the CPU + package which is also known as Fan Temperature target. + Indicates the relative value from thermal monitor trip + temperature at which fans should be engaged. +temp3_crit Provides Tcontrol critical value of the CPU package + which is same to Tjmax. + +temp4_label "Tthrottle" +temp4_input Provides current Tthrottle temperature of the CPU + package. Used for throttling temperature. If this value + is allowed and lower than Tjmax - the throttle will + occur and reported at lower than Tjmax. + +temp5_label "Tjmax" +temp5_input Provides the maximum junction temperature, Tjmax of the + CPU package. + +temp[6-N]_label Provides string "Core X", where X is resolved core + number. +temp[6-N]_input Provides current temperature of each core. +temp[6-N]_max Provides thermal control temperature of the core. +temp[6-N]_crit Provides shutdown temperature of the core. +temp[6-N]_crit_hyst Provides the hysteresis value from Tcontrol to Tjmax of + the core. +======================= =======================================================
\ No newline at end of file diff --git a/Documentation/hwmon/peci-dimmpower.rst b/Documentation/hwmon/peci-dimmpower.rst new file mode 100644 index 000000000000..0d9c58fdaf9c --- /dev/null +++ b/Documentation/hwmon/peci-dimmpower.rst @@ -0,0 +1,57 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver peci-dimmpower +========================== + +:Copyright: |copy| 2020 Intel Corporation + +Supported chips: + One of Intel server CPUs listed below which is connected to a PECI bus. + * Intel Xeon E5/E7 v3 server processors + Intel Xeon E5-14xx v3 family + Intel Xeon E5-24xx v3 family + Intel Xeon E5-16xx v3 family + Intel Xeon E5-26xx v3 family + Intel Xeon E5-46xx v3 family + Intel Xeon E7-48xx v3 family + Intel Xeon E7-88xx v3 family + * Intel Xeon E5/E7 v4 server processors + Intel Xeon E5-16xx v4 family + Intel Xeon E5-26xx v4 family + Intel Xeon E5-46xx v4 family + Intel Xeon E7-48xx v4 family + Intel Xeon E7-88xx v4 family + * Intel Xeon Scalable server processors + Intel Xeon D family + Intel Xeon Bronze family + Intel Xeon Silver family + Intel Xeon Gold family + Intel Xeon Platinum family + + Addresses scanned: PECI client address 0x30 - 0x37 + Datasheet: Available from http://www.intel.com/design/literature.htm + +Author: + Zbigniew Lukwinski <zbigniew.lukwinski@linux.intel.com> + +Description +----------- + +This driver implements a generic PECI hwmon feature which provides +average power consumption readings of the memory basing on energy counter. +Power value is average power since last measure given in milli Watt and +will be measurable only when the target CPU is powered on. +Driver provides current plane power limit, maximal and minimal power setting +as well. +All needed processor registers are accessible using the PECI Client Command +Suite via the processor PECI client. + +``sysfs`` interface +------------------- +======================= ======================================================= +power1_label Provides string "dimm power". +power1_average Provides average DRAM power since last read in milli Watt. +power1_cap Provides current DRAM plane power limit. +power1_cap_max Provides maximal DRAM power setting. +power1_cap_min Provides minimal DRAM power setting. +======================= ======================================================= diff --git a/Documentation/hwmon/peci-dimmtemp.rst b/Documentation/hwmon/peci-dimmtemp.rst new file mode 100644 index 000000000000..e3581811de2d --- /dev/null +++ b/Documentation/hwmon/peci-dimmtemp.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver peci-dimmtemp +=========================== + +:Copyright: |copy| 2018-2019 Intel Corporation + +Supported chips: + One of Intel server CPUs listed below which is connected to a PECI bus. + * Intel Xeon E5/E7 v3 server processors + Intel Xeon E5-14xx v3 family + Intel Xeon E5-24xx v3 family + Intel Xeon E5-16xx v3 family + Intel Xeon E5-26xx v3 family + Intel Xeon E5-46xx v3 family + Intel Xeon E7-48xx v3 family + Intel Xeon E7-88xx v3 family + * Intel Xeon E5/E7 v4 server processors + Intel Xeon E5-16xx v4 family + Intel Xeon E5-26xx v4 family + Intel Xeon E5-46xx v4 family + Intel Xeon E7-48xx v4 family + Intel Xeon E7-88xx v4 family + * Intel Xeon Scalable server processors + Intel Xeon D family + Intel Xeon Bronze family + Intel Xeon Silver family + Intel Xeon Gold family + Intel Xeon Platinum family + + Addresses scanned: PECI client address 0x30 - 0x37 + Datasheet: Available from http://www.intel.com/design/literature.htm + +Author: + Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> + +Description +----------- + +This driver implements a generic PECI hwmon feature which provides Digital +Thermal Sensor (DTS) thermal readings of DIMM components that are accessible +using the PECI Client Command Suite via the processor PECI client. + +All temperature values are given in millidegree Celsius and will be measurable +only when the target CPU is powered on. + +``sysfs`` interface +------------------- +======================= ======================================================= + +temp[N]_label Provides string "DIMM CI", where C is DIMM channel and + I is DIMM index of the populated DIMM. +temp[N]_input Provides current temperature of the populated DIMM. +temp[N]_max Provides thermal control temperature of the DIMM. +temp[N]_crit Provides shutdown temperature of the DIMM. +======================= ======================================================= + +Note: + DIMM temperature attributes will appear when the client CPU's BIOS + completes memory training and testing. diff --git a/Documentation/i2c/slave-mqueue-backend.rst b/Documentation/i2c/slave-mqueue-backend.rst new file mode 100644 index 000000000000..2d0d06d8df9d --- /dev/null +++ b/Documentation/i2c/slave-mqueue-backend.rst @@ -0,0 +1,124 @@ +.. SPDX-License-Identifier: GPL-2.0 + +===================================== +Linux I2C slave message queue backend +===================================== + +:Author: Haiyue Wang <haiyue.wang@linux.intel.com> + +Some protocols over I2C/SMBus are designed for bi-directional transferring +messages by using I2C Master Write protocol. This requires that both sides +of the communication have slave addresses. + +Like MCTP (Management Component Transport Protocol) and IPMB (Intelligent +Platform Management Bus), they both require that the userspace can receive +messages from i2c dirvers under slave mode. + +This I2C slave mqueue (message queue) backend is used to receive and queue +messages from the remote i2c intelligent device; and it will add the target +slave address (with R/W# bit is always 0) into the message at the first byte, +so that userspace can use this byte to dispatch the messages into different +handling modules. Also, like IPMB, the address byte is in its message format, +it needs it to do checksum. + +For messages are time related, so this backend will flush the oldest message +to queue the newest one. + +Link +---- +`Intelligent Platform Management Bus +Communications Protocol Specification +<https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmp-spec-v1.0.pdf>`_ + +`Management Component Transport Protocol (MCTP) +SMBus/I2C Transport Binding Specification +<https://www.dmtf.org/sites/default/files/standards/documents/DSP0237_1.1.0.pdf>`_ + +How to use +---------- +For example, the I2C5 bus has slave address 0x10, the below command will create +the related message queue interface: + + echo slave-mqueue 0x1010 > /sys/bus/i2c/devices/i2c-5/new_device + +Then you can dump the messages like this: + + hexdump -C /sys/bus/i2c/devices/5-1010/slave-mqueue + +Code Example +------------ +*Note: call 'lseek' before 'read', this is a requirement from kernfs' design.* + +:: + + #include <sys/types.h> + #include <sys/stat.h> + #include <unistd.h> + #include <poll.h> + #include <time.h> + #include <fcntl.h> + #include <stdio.h> + + int main(int argc, char *argv[]) + { + int i, r; + struct pollfd pfd; + struct timespec ts; + unsigned char data[256]; + + pfd.fd = open(argv[1], O_RDONLY | O_NONBLOCK); + if (pfd.fd < 0) + return -1; + + pfd.events = POLLPRI; + + while (1) { + r = poll(&pfd, 1, 5000); + + if (r < 0) + break; + + if (r == 0 || !(pfd.revents & POLLPRI)) + continue; + + lseek(pfd.fd, 0, SEEK_SET); + r = read(pfd.fd, data, sizeof(data)); + if (r <= 0) + continue; + + clock_gettime(CLOCK_MONOTONIC, &ts); + printf("[%ld.%.9ld] :", ts.tv_sec, ts.tv_nsec); + for (i = 0; i < r; i++) + printf(" %02x", data[i]); + printf("\n"); + } + + close(pfd.fd); + + return 0; + } + +Result +------ +*./a.out "/sys/bus/i2c/devices/5-1010/slave-mqueue"* + +:: + + [10183.232500449] : 20 18 c8 2c 78 01 5b + [10183.479358348] : 20 18 c8 2c 78 01 5b + [10183.726556812] : 20 18 c8 2c 78 01 5b + [10183.972605863] : 20 18 c8 2c 78 01 5b + [10184.220124772] : 20 18 c8 2c 78 01 5b + [10184.467764166] : 20 18 c8 2c 78 01 5b + [10193.233421784] : 20 18 c8 2c 7c 01 57 + [10193.480273460] : 20 18 c8 2c 7c 01 57 + [10193.726788733] : 20 18 c8 2c 7c 01 57 + [10193.972781945] : 20 18 c8 2c 7c 01 57 + [10194.220487360] : 20 18 c8 2c 7c 01 57 + [10194.468089259] : 20 18 c8 2c 7c 01 57 + [10203.233433099] : 20 18 c8 2c 80 01 53 + [10203.481058715] : 20 18 c8 2c 80 01 53 + [10203.727610472] : 20 18 c8 2c 80 01 53 + [10203.974044856] : 20 18 c8 2c 80 01 53 + [10204.220734634] : 20 18 c8 2c 80 01 53 + [10204.468461664] : 20 18 c8 2c 80 01 53 diff --git a/Documentation/index.rst b/Documentation/index.rst index 54ce34fd6fbd..91f4f7923359 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -111,6 +111,7 @@ needed). iio/index isdn/index infiniband/index + jtag/index leds/index netlabel/index networking/index diff --git a/Documentation/jtag/index.rst b/Documentation/jtag/index.rst new file mode 100644 index 000000000000..8a2761d1c17e --- /dev/null +++ b/Documentation/jtag/index.rst @@ -0,0 +1,18 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================== +Joint Test Action Group (JTAG) +============================== + +.. toctree:: + :maxdepth: 1 + + jtag-summary + jtagdev + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/jtag/jtag-summary.rst b/Documentation/jtag/jtag-summary.rst new file mode 100644 index 000000000000..050b16a9f801 --- /dev/null +++ b/Documentation/jtag/jtag-summary.rst @@ -0,0 +1,47 @@ +.. SPDX-License-Identifier: GPL-2.0 + +==================================== +Linux kernel JTAG support +==================================== + +Introduction to JTAG +==================== + +JTAG is an industry standard for verifying hardware. JTAG provides access to +many logic signals of a complex integrated circuit, including the device pins. + +A JTAG interface is a special interface added to a chip. +Depending on the version of JTAG, two, four, or five pins are added. + +The connector pins are: + * TDI (Test Data In) + * TDO (Test Data Out) + * TCK (Test Clock) + * TMS (Test Mode Select) + * TRST (Test Reset) optional + +JTAG interface is designed to have two parts - basic core driver and +hardware specific driver. The basic driver introduces a general interface +which is not dependent of specific hardware. It provides communication +between user space and hardware specific driver. +Each JTAG device is represented as a char device from (jtag0, jtag1, ...). +Access to a JTAG device is performed through IOCTL calls. + +Call flow example: +:: + + User: open -> /dev/jatgX -> JTAG core driver -> JTAG hardware specific driver + User: ioctl -> /dev/jtagX -> JTAG core driver -> JTAG hardware specific driver + User: close -> /dev/jatgX -> JTAG core driver -> JTAG hardware specific driver + + +THANKS TO +--------- +Contributors to Linux-JTAG discussions include (in alphabetical order, +by last name): + +- Ernesto Corona +- Steven Filary +- Vadim Pasternak +- Jiri Pirko +- Oleksandr Shamray diff --git a/Documentation/jtag/jtagdev.rst b/Documentation/jtag/jtagdev.rst new file mode 100644 index 000000000000..c50ed2b85a07 --- /dev/null +++ b/Documentation/jtag/jtagdev.rst @@ -0,0 +1,207 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================== +JTAG userspace API +================== +JTAG master devices can be accessed through a character misc-device. + +Each JTAG master interface can be accessed by using /dev/jtagN. + +JTAG system calls set: + * SIR (Scan Instruction Register, IEEE 1149.1 Instruction Register scan); + * SDR (Scan Data Register, IEEE 1149.1 Data Register scan); + * RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified number of clocks. + +open(), close() +--------------- +Open/Close device: +:: + + jtag_fd = open("/dev/jtag0", O_RDWR); + close(jtag_fd); + +ioctl() +------- +All access operations to JTAG devices are performed through ioctl interface. +The IOCTL interface supports these requests: +:: + + JTAG_SIOCSTATE - Force JTAG state machine to go into a TAPC state + JTAG_SIOCFREQ - Set JTAG TCK frequency + JTAG_GIOCFREQ - Get JTAG TCK frequency + JTAG_IOCXFER - send/receive JTAG data Xfer + JTAG_GIOCSTATUS - get current JTAG TAP state + JTAG_SIOCMODE - set JTAG mode flags. + JTAG_IOCBITBANG - JTAG bitbang low level control. + +JTAG_SIOCFREQ +~~~~~~~~~~~~~ +Set JTAG clock speed: +:: + + unsigned int jtag_fd; + ioctl(jtag_fd, JTAG_SIOCFREQ, &frq); + +JTAG_GIOCFREQ +~~~~~~~~~~~~~ +Get JTAG clock speed: +:: + + unsigned int jtag_fd; + ioctl(jtag_fd, JTAG_GIOCFREQ, &frq); + +JTAG_SIOCSTATE +~~~~~~~~~~~~~~ +Force JTAG state machine to go into a TAPC state +:: + + struct jtag_tap_state { + __u8 reset; + __u8 from; + __u8 endstate; + __u8 tck; + }; + +reset: one of below options +:: + + JTAG_NO_RESET - go through selected endstate from current state + JTAG_FORCE_RESET - go through TEST_LOGIC/RESET state before selected endstate + +endstate: any state listed in jtag_tapstate enum +:: + + enum jtag_tapstate { + JTAG_STATE_TLRESET, + JTAG_STATE_IDLE, + JTAG_STATE_SELECTDR, + JTAG_STATE_CAPTUREDR, + JTAG_STATE_SHIFTDR, + JTAG_STATE_EXIT1DR, + JTAG_STATE_PAUSEDR, + JTAG_STATE_EXIT2DR, + JTAG_STATE_UPDATEDR, + JTAG_STATE_SELECTIR, + JTAG_STATE_CAPTUREIR, + JTAG_STATE_SHIFTIR, + JTAG_STATE_EXIT1IR, + JTAG_STATE_PAUSEIR, + JTAG_STATE_EXIT2IR, + JTAG_STATE_UPDATEIR + }; + +tck: clock counter + +Example: +:: + + struct jtag_tap_state tap_state; + + tap_state.endstate = JTAG_STATE_IDLE; + tap_state.reset = 0; + tap_state.tck = data_p->tck; + usleep(25 * 1000); + ioctl(jtag_fd, JTAG_SIOCSTATE, &tap_state); + +JTAG_GIOCSTATUS +~~~~~~~~~~~~~~~ +Get JTAG TAPC current machine state +:: + + unsigned int jtag_fd; + jtag_tapstate tapstate; + ioctl(jtag_fd, JTAG_GIOCSTATUS, &tapstate); + +JTAG_IOCXFER +~~~~~~~~~~~~ +Send SDR/SIR transaction +:: + + struct jtag_xfer { + __u8 type; + __u8 direction; + __u8 from; + __u8 endstate; + __u32 padding; + __u32 length; + __u64 tdio; + }; + +type: transfer type - JTAG_SIR_XFER/JTAG_SDR_XFER + +direction: xfer direction - JTAG_READ_XFER/JTAG_WRITE_XFER/JTAG_READ_WRITE_XFER + +from: jtag_tapstate enum representing the initial tap state of the chain before xfer. + +endstate: end state after transaction finish any of jtag_tapstate enum + +padding: padding configuration. See the following table with bitfield descriptions. + +=============== ========= ======= ===================================================== +Bit Field Bit begin Bit end Description +=============== ========= ======= ===================================================== +rsvd 25 31 Reserved, not used +pad data 24 24 Value used for pre and post padding. Either 1 or 0. +post pad count 12 23 Number of padding bits to be executed after transfer. +pre pad count 0 11 Number of padding bit to be executed before transfer. +=============== ========= ======= ===================================================== + +length: xfer data length in bits + +tdio : xfer data array + +Example: +:: + + struct jtag_xfer xfer; + static char buf[64]; + static unsigned int buf_len = 0; + [...] + xfer.type = JTAG_SDR_XFER; + xfer.tdio = (__u64)buf; + xfer.length = buf_len; + xfer.from = JTAG_STATE_TLRESET; + xfer.endstate = JTAG_STATE_IDLE; + + if (is_read) + xfer.direction = JTAG_READ_XFER; + else if (is_write) + xfer.direction = JTAG_WRITE_XFER; + else + xfer.direction = JTAG_READ_WRITE_XFER; + + ioctl(jtag_fd, JTAG_IOCXFER, &xfer); + +JTAG_SIOCMODE +~~~~~~~~~~~~~ +If hardware driver can support different running modes you can change it. + +Example: +:: + + struct jtag_mode mode; + mode.feature = JTAG_XFER_MODE; + mode.mode = JTAG_XFER_HW_MODE; + ioctl(jtag_fd, JTAG_SIOCMODE, &mode); + +JTAG_IOCBITBANG +~~~~~~~~~~~~~~~ +JTAG Bitbang low level operation. + +Example: +:: + + struct tck_bitbang bitbang + bitbang.tms = 1; + bitbang.tdi = 0; + ioctl(jtag_fd, JTAG_IOCBITBANG, &bitbang); + tdo = bitbang.tdo; + + +THANKS TO +--------- +Contributors to Linux-JTAG discussions include (in alphabetical order, +by last name): + +- Ernesto Corona +- Jiri Pirko diff --git a/Documentation/misc-devices/aspeed-espi-slave.rst b/Documentation/misc-devices/aspeed-espi-slave.rst new file mode 100644 index 000000000000..887a69a7130a --- /dev/null +++ b/Documentation/misc-devices/aspeed-espi-slave.rst @@ -0,0 +1,118 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========== +eSPI Slave +========== + +:Author: Haiyue Wang <haiyue.wang@linux.intel.com> + +The PCH (**eSPI master**) provides the eSPI to support connection of a +BMC (**eSPI slave**) to the platform. + +The LPC and eSPI interfaces are mutually exclusive. Both use the same +pins, but on power-up, a HW strap determines if the eSPI or the LPC bus +is operational. Once selected, it’s not possible to change to the other +interface. + +``eSPI Channels and Supported Transactions`` + +------+---------------------+----------------------+--------------------+ + | CH # | Channel | Posted Cycles | Non-Posted Cycles | + +======+=====================+======================+====================+ + | 0 | Peripheral | Memory Write, | Memory Read, | + | | | Completions | I/O Read/Write | + +------+---------------------+----------------------+--------------------+ + | 1 | Virtual Wire | Virtual Wire GET/PUT | N/A | + +------+---------------------+----------------------+--------------------+ + | 2 | Out-of-Band Message | SMBus Packet GET/PUT | N/A | + +------+---------------------+----------------------+--------------------+ + | 3 | Flash Access | N/A | Flash Read, Write, | + | | | | Erase | + +------+---------------------+----------------------+--------------------+ + | N/A | General | Register Accesses | N/A | + +------+---------------------+----------------------+--------------------+ + +Virtual Wire Channel (Channel 1) Overview +----------------------------------------- + +The Virtual Wire channel uses a standard message format to communicate +several types of signals between the components on the platform:: + + - Sideband and GPIO Pins: System events and other dedicated signals + between the PCH and eSPI slave. These signals are tunneled between the + two components over eSPI. + + - Serial IRQ Interrupts: Interrupts are tunneled from the eSPI slave to + the PCH. Both edge and triggered interrupts are supported. + +When PCH runs on eSPI mode, from BMC side, the following VW messages are +done in firmware:: + + 1. SLAVE_BOOT_LOAD_DONE / SLAVE_BOOT_LOAD_STATUS + 2. SUS_ACK + 3. OOB_RESET_ACK + 4. HOST_RESET_ACK + +``eSPI Virtual Wires (VW)`` + +----------------------+---------+---------------------------------------+ + |Virtual Wire |PCH Pin |Comments | + | |Direction| | + +======================+=========+=======================================+ + |SUS_WARN# |Output |PCH pin is a GPIO when eSPI is enabled.| + | | |eSPI controller receives as VW message.| + +----------------------+---------+---------------------------------------+ + |SUS_ACK# |Input |PCH pin is a GPIO when eSPI is enabled.| + | | |eSPI controller receives as VW message.| + +----------------------+---------+---------------------------------------+ + |SLAVE_BOOT_LOAD_DONE |Input |Sent when the BMC has completed its | + | | |boot process as an indication to | + | | |eSPI-MC to continue with the G3 to S0 | + | | |exit. | + | | |The eSPI Master waits for the assertion| + | | |of this virtual wire before proceeding | + | | |with the SLP_S5# deassertion. | + | | |The intent is that it is never changed | + | | |except on a G3 exit - it is reset on a | + | | |G3 entry. | + +----------------------+---------+---------------------------------------+ + |SLAVE_BOOT_LOAD_STATUS|Input |Sent upon completion of the Slave Boot | + | | |Load from the attached flash. A stat of| + | | |1 indicates that the boot code load was| + | | |successful and that the integrity of | + | | |the image is intact. | + +----------------------+---------+---------------------------------------+ + |HOST_RESET_WARN |Output |Sent from the MC just before the Host | + | | |is about to enter reset. Upon receiving| + | | |, the BMC must flush and quiesce its | + | | |upstream Peripheral Channel request | + | | |queues and assert HOST_RESET_ACK VWire.| + | | |The MC subsequently completes any | + | | |outstanding posted transactions or | + | | |completions and then disables the | + | | |Peripheral Channel via a write to | + | | |the Slave's Configuration Register. | + +----------------------+---------+---------------------------------------+ + |HOST_RESET_ACK |Input |ACK for the HOST_RESET_WARN message | + +----------------------+---------+---------------------------------------+ + |OOB_RESET_WARN |Output |Sent from the MC just before the OOB | + | | |processor is about to enter reset. Upon| + | | |receiving, the BMC must flush and | + | | |quiesce its OOB Channel upstream | + | | |request queues and assert OOB_RESET_ACK| + | | |VWire. The-MC subsequently completes | + | | |any outstanding posted transactions or | + | | |completions and then disables the OOB | + | | |Channel via a write to the Slave's | + | | |Configuration Register. | + +----------------------+---------+---------------------------------------+ + |OOB_RESET_ACK |Input |ACK for OOB_RESET_WARN message | + +----------------------+---------+---------------------------------------+ + +`Intel C620 Series Chipset Platform Controller Hub +<https://www.intel.com/content/www/us/en/chipsets/c620-series-chipset-datasheet.html>`_ + + -- 17. Enhanced Serial Peripheral Interface + + +`Enhanced Serial Peripheral Interface (eSPI) +- Interface Base Specification (for Client and Server Platforms) +<https://www.intel.com/content/dam/support/us/en/documents/software/chipset-software/327432-004_espi_base_specification_rev1.0.pdf>`_ diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst index 6655d929a351..fa1a8521a09a 100644 --- a/Documentation/userspace-api/ioctl/ioctl-number.rst +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -321,6 +321,7 @@ Code Seq# Include File Comments <mailto:kenji@bitgate.com> 0xA1 0 linux/vtpm_proxy.h TPM Emulator Proxy Driver 0xA2 all uapi/linux/acrn.h ACRN hypervisor +0xA3 00 include/uapi/linux/aspeed-lpc-mbox.h 0xA3 80-8F Port ACL in development: <mailto:tlewis@mindspring.com> 0xA3 90-9F linux/dtlk.h @@ -345,12 +346,16 @@ Code Seq# Include File Comments <mailto:vgo@ratio.de> 0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca> +0xB2 00-0F linux/jtag.h JTAG driver + <mailto:oleksandrs@mellanox.com> 0xB3 00 linux/mmc/ioctl.h 0xB4 00-0F linux/gpio.h <mailto:linux-gpio@vger.kernel.org> 0xB5 00-0F uapi/linux/rpmsg.h <mailto:linux-remoteproc@vger.kernel.org> 0xB6 all linux/fpga-dfl.h 0xB7 all uapi/linux/remoteproc_cdev.h <mailto:linux-remoteproc@vger.kernel.org> 0xB7 all uapi/linux/nsfs.h <mailto:Andrei Vagin <avagin@openvz.org>> +0xB8 all uapi/linux/peci-ioctl.h PECI subsystem + <mailto:jae.hyun.yoo@linux.intel.com> 0xC0 00-0F linux/usb/iowarrior.h 0xCA 00-0F uapi/misc/cxl.h 0xCA 10-2F uapi/misc/ocxl.h |