diff options
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach')
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/SA-1100.h | 16 | ||||
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/hardware.h | 18 | ||||
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/ide.h | 75 | ||||
| -rw-r--r-- | arch/arm/mach-sa1100/include/mach/memory.h | 16 |
4 files changed, 25 insertions, 100 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h index 62aaf04a3906..4f7ea012e1e5 100644 --- a/arch/arm/mach-sa1100/include/mach/SA-1100.h +++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h @@ -2054,19 +2054,3 @@ /* active display mode) */ #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */ #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */ - -#ifndef __ASSEMBLY__ -extern unsigned int processor_id; -#endif - -#define CPU_REVISION (processor_id & 15) -#define CPU_SA1110_A0 (0) -#define CPU_SA1110_B0 (4) -#define CPU_SA1110_B1 (5) -#define CPU_SA1110_B2 (6) -#define CPU_SA1110_B4 (8) - -#define CPU_SA1100_ID (0x4401a110) -#define CPU_SA1100_MASK (0xfffffff0) -#define CPU_SA1110_ID (0x6901b110) -#define CPU_SA1110_MASK (0xfffffff0) diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h index 5976435f42c2..b70846c096aa 100644 --- a/arch/arm/mach-sa1100/include/mach/hardware.h +++ b/arch/arm/mach-sa1100/include/mach/hardware.h @@ -36,8 +36,26 @@ #define io_v2p( x ) \ ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) +#define CPU_SA1110_A0 (0) +#define CPU_SA1110_B0 (4) +#define CPU_SA1110_B1 (5) +#define CPU_SA1110_B2 (6) +#define CPU_SA1110_B4 (8) + +#define CPU_SA1100_ID (0x4401a110) +#define CPU_SA1100_MASK (0xfffffff0) +#define CPU_SA1110_ID (0x6901b110) +#define CPU_SA1110_MASK (0xfffffff0) + #ifndef __ASSEMBLY__ +#include <asm/cputype.h> + +#define CPU_REVISION (read_cpuid_id() & 15) + +#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID) +#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID) + # define __REG(x) (*((volatile unsigned long *)io_p2v(x))) # define __PREG(x) (io_v2p((unsigned long)&(x))) diff --git a/arch/arm/mach-sa1100/include/mach/ide.h b/arch/arm/mach-sa1100/include/mach/ide.h deleted file mode 100644 index 4c99c8f5e617..000000000000 --- a/arch/arm/mach-sa1100/include/mach/ide.h +++ /dev/null @@ -1,75 +0,0 @@ -/* - * arch/arm/mach-sa1100/include/mach/ide.h - * - * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre - * - * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * Get rid of the special ide_init_hwif_ports() functions - * and make a generalised function that can be used by all - * architectures. - */ - -#include <asm/irq.h> -#include <mach/hardware.h> -#include <asm/mach-types.h> - -#error "This code is broken and needs update to match with current ide support" - - -/* - * Set up a hw structure for a specified data port, control port and IRQ. - * This should follow whatever the default interface uses. - */ -static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, - unsigned long ctrl_port, int *irq) -{ - unsigned long reg = data_port; - int i; - int regincr = 1; - - /* The Empeg board has the first two address lines unused */ - if (machine_is_empeg()) - regincr = 1 << 2; - - /* The LART doesn't use A0 for IDE */ - if (machine_is_lart()) - regincr = 1 << 1; - - memset(hw, 0, sizeof(*hw)); - - for (i = 0; i <= 7; i++) { - hw->io_ports_array[i] = reg; - reg += regincr; - } - - hw->io_ports.ctl_addr = ctrl_port; - - if (irq) - *irq = 0; -} - -/* - * This registers the standard ports for this architecture with the IDE - * driver. - */ -static __inline__ void -ide_init_default_hwifs(void) -{ - if (machine_is_lart()) { -#ifdef CONFIG_SA1100_LART - hw_regs_t hw; - - /* Enable GPIO as interrupt line */ - GPDR &= ~LART_GPIO_IDE; - set_irq_type(LART_IRQ_IDE, IRQ_TYPE_EDGE_RISING); - - /* set PCMCIA interface timing */ - MECR = 0x00060006; - - /* init the interface */ - ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL); - hw.irq = LART_IRQ_IDE; - ide_register_hw(&hw); -#endif - } -} diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h index 29f639e2afc6..1c127b68581d 100644 --- a/arch/arm/mach-sa1100/include/mach/memory.h +++ b/arch/arm/mach-sa1100/include/mach/memory.h @@ -40,23 +40,21 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes); #define __bus_to_virt(x) __phys_to_virt(x) /* - * Because of the wide memory address space between physical RAM banks on the - * SA1100, it's much convenient to use Linux's NUMA support to implement our - * memory map representation. Assuming all memory nodes have equal access + * Because of the wide memory address space between physical RAM banks on the + * SA1100, it's much convenient to use Linux's SparseMEM support to implement + * our memory map representation. Assuming all memory nodes have equal access * characteristics, we then have generic discontiguous memory support. * - * Of course, all this isn't mandatory for SA1100 implementations with only - * one used memory bank. For those, simply undefine CONFIG_DISCONTIGMEM. - * - * The nodes are matched with the physical memory bank addresses which are - * incidentally the same as virtual addresses. + * The sparsemem banks are matched with the physical memory bank addresses + * which are incidentally the same as virtual addresses. * * node 0: 0xc0000000 - 0xc7ffffff * node 1: 0xc8000000 - 0xcfffffff * node 2: 0xd0000000 - 0xd7ffffff * node 3: 0xd8000000 - 0xdfffffff */ -#define NODE_MEM_SIZE_BITS 27 +#define MAX_PHYSMEM_BITS 32 +#define SECTION_SIZE_BITS 27 /* * Cache flushing area - SA1100 zero bank |