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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3765d97b8512..ba67d1023264 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2455,8 +2455,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
/* disable CG */
WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
- adev->gfx.rlc.funcs->reset(adev);
-
gfx_v9_0_init_pg(adev);
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
@@ -3568,7 +3566,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
int r;
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) {
- amdgpu_ras_feature_enable(adev, &ras_block, 0);
+ amdgpu_ras_feature_enable_on_boot(adev, &ras_block, 0);
return 0;
}
@@ -3581,7 +3579,7 @@ static int gfx_v9_0_ecc_late_init(void *handle)
**ras_if = ras_block;
- r = amdgpu_ras_feature_enable(adev, *ras_if, 1);
+ r = amdgpu_ras_feature_enable_on_boot(adev, *ras_if, 1);
if (r)
goto feature;
@@ -4840,10 +4838,16 @@ static int gfx_v9_0_cp_ecc_error_irq(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
struct amdgpu_iv_entry *entry)
{
+ struct ras_common_if *ras_if = adev->gfx.ras_if;
struct ras_dispatch_if ih_data = {
- .head = *adev->gfx.ras_if,
.entry = entry,
};
+
+ if (!ras_if)
+ return 0;
+
+ ih_data.head = *ras_if;
+
DRM_ERROR("CP ECC ERROR IRQ\n");
amdgpu_ras_interrupt_dispatch(adev, &ih_data);
return 0;