diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h | 81 |
1 files changed, 79 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h index 7c2559c9ae23..69d903d68661 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h @@ -119,6 +119,28 @@ struct dcn_hubbub_registers { uint32_t DCN_VM_AGP_BOT; uint32_t DCN_VM_AGP_TOP; uint32_t DCN_VM_AGP_BASE; + uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB; + uint32_t DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB; +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_A; + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_B; + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_C; + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_NOM_D; + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A; + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B; + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C; + uint32_t DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D; + uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A; + uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B; + uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C; + uint32_t DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D; + uint32_t DCHUBBUB_ARB_HOSTVM_CNTL; + uint32_t DCHVM_CTRL0; + uint32_t DCHVM_MEM_CTRL; + uint32_t DCHVM_CLK_CTRL; + uint32_t DCHVM_RIOMMU_CTRL0; + uint32_t DCHVM_RIOMMU_STAT0; +#endif }; /* set field name */ @@ -196,7 +218,9 @@ struct dcn_hubbub_registers { type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ - type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D + type DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ + type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB;\ + type DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\ @@ -208,15 +232,68 @@ struct dcn_hubbub_registers { type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C;\ type DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) +#define HUBBUB_HVM_REG_FIELD_LIST(type) \ + type DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD;\ + type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_A;\ + type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_B;\ + type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_C;\ + type DCHUBBUB_ARB_VM_ROW_URGENCY_WATERMARK_D;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_A;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_B;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_C;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_ENTER_WATERMARK_D;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_A;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_B;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_C;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_SR_EXIT_WATERMARK_D;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C;\ + type DCHUBBUB_ARB_VM_ROW_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D;\ + type DCHUBBUB_ARB_FRAC_URG_BW_NOM_A;\ + type DCHUBBUB_ARB_FRAC_URG_BW_NOM_B;\ + type DCHUBBUB_ARB_FRAC_URG_BW_NOM_C;\ + type DCHUBBUB_ARB_FRAC_URG_BW_NOM_D;\ + type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A;\ + type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B;\ + type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C;\ + type DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D;\ + type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A;\ + type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B;\ + type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C;\ + type DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D;\ + type DCHUBBUB_ARB_MAX_QOS_COMMIT_THRESHOLD;\ + type HOSTVM_INIT_REQ; \ + type HVM_GPUVMRET_PWR_REQ_DIS; \ + type HVM_GPUVMRET_FORCE_REQ; \ + type HVM_GPUVMRET_POWER_STATUS; \ + type HVM_DISPCLK_R_GATE_DIS; \ + type HVM_DISPCLK_G_GATE_DIS; \ + type HVM_DCFCLK_R_GATE_DIS; \ + type HVM_DCFCLK_G_GATE_DIS; \ + type TR_REQ_REQCLKREQ_MODE; \ + type TW_RSP_COMPCLKREQ_MODE; \ + type HOSTVM_PREFETCH_REQ; \ + type HOSTVM_POWERSTATUS; \ + type RIOMMU_ACTIVE; \ + type HOSTVM_PREFETCH_DONE +#endif struct dcn_hubbub_shift { DCN_HUBBUB_REG_FIELD_LIST(uint8_t); HUBBUB_STUTTER_REG_FIELD_LIST(uint8_t); +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) + HUBBUB_HVM_REG_FIELD_LIST(uint8_t); +#endif }; struct dcn_hubbub_mask { DCN_HUBBUB_REG_FIELD_LIST(uint32_t); HUBBUB_STUTTER_REG_FIELD_LIST(uint32_t); +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) + HUBBUB_HVM_REG_FIELD_LIST(uint32_t); +#endif }; struct dc; @@ -247,7 +324,7 @@ void hubbub1_program_watermarks( void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow); -bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub); +bool hubbub1_is_allow_self_refresh_enabled(struct hubbub *hubub); void hubbub1_toggle_watermark_change_req( struct hubbub *hubbub); |