diff options
Diffstat (limited to 'drivers/gpu/drm')
360 files changed, 42884 insertions, 5749 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig index 1a0a8df2eed8..c4bf9a1cf4a6 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig @@ -264,3 +264,5 @@ source "drivers/gpu/drm/sti/Kconfig" source "drivers/gpu/drm/amd/amdkfd/Kconfig" source "drivers/gpu/drm/imx/Kconfig" + +source "drivers/gpu/drm/vc4/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile index 45e7719846b1..1e9ff4c3e3db 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile @@ -6,7 +6,7 @@ drm-y := drm_auth.o drm_bufs.o drm_cache.o \ drm_context.o drm_dma.o \ drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \ drm_lock.o drm_memory.o drm_drv.o drm_vm.o \ - drm_agpsupport.o drm_scatter.o drm_pci.o \ + drm_scatter.o drm_pci.o \ drm_platform.o drm_sysfs.o drm_hashtab.o drm_mm.o \ drm_crtc.o drm_modes.o drm_edid.o \ drm_info.o drm_debugfs.o drm_encoder_slave.o \ @@ -19,6 +19,9 @@ drm-$(CONFIG_DRM_GEM_CMA_HELPER) += drm_gem_cma_helper.o drm-$(CONFIG_PCI) += ati_pcigart.o drm-$(CONFIG_DRM_PANEL) += drm_panel.o drm-$(CONFIG_OF) += drm_of.o +drm-$(CONFIG_AGP) += drm_agpsupport.o + +drm-y += $(drm-m) drm_kms_helper-y := drm_crtc_helper.o drm_dp_helper.o drm_probe_helper.o \ drm_plane_helper.o drm_dp_mst_topology.o drm_atomic_helper.o @@ -42,6 +45,7 @@ obj-$(CONFIG_DRM_MGA) += mga/ obj-$(CONFIG_DRM_I810) += i810/ obj-$(CONFIG_DRM_I915) += i915/ obj-$(CONFIG_DRM_MGAG200) += mgag200/ +obj-$(CONFIG_DRM_VC4) += vc4/ obj-$(CONFIG_DRM_CIRRUS_QEMU) += cirrus/ obj-$(CONFIG_DRM_SIS) += sis/ obj-$(CONFIG_DRM_SAVAGE)+= savage/ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6647fb26ef25..de9312c02185 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -79,6 +79,8 @@ extern int amdgpu_bapm; extern int amdgpu_deep_color; extern int amdgpu_vm_size; extern int amdgpu_vm_block_size; +extern int amdgpu_vm_fault_stop; +extern int amdgpu_vm_debug; extern int amdgpu_enable_scheduler; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; @@ -343,7 +345,6 @@ struct amdgpu_ring_funcs { /* testing functions */ int (*test_ring)(struct amdgpu_ring *ring); int (*test_ib)(struct amdgpu_ring *ring); - bool (*is_lockup)(struct amdgpu_ring *ring); /* insert NOP packets */ void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); }; @@ -404,7 +405,6 @@ struct amdgpu_fence_driver { /* some special values for the owner field */ #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) -#define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) #define AMDGPU_FENCE_FLAG_INT (1 << 1) @@ -446,58 +446,11 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring); int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); -signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, - struct fence **array, - uint32_t count, - bool intr, - signed long t); -struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence); -void amdgpu_fence_unref(struct amdgpu_fence **fence); - bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, struct amdgpu_ring *ring); void amdgpu_fence_note_sync(struct amdgpu_fence *fence, struct amdgpu_ring *ring); -static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a, - struct amdgpu_fence *b) -{ - if (!a) { - return b; - } - - if (!b) { - return a; - } - - BUG_ON(a->ring != b->ring); - - if (a->seq > b->seq) { - return a; - } else { - return b; - } -} - -static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a, - struct amdgpu_fence *b) -{ - if (!a) { - return false; - } - - if (!b) { - return true; - } - - BUG_ON(a->ring != b->ring); - - return a->seq < b->seq; -} - -int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, - void *owner, struct amdgpu_fence **fence); - /* * TTM. */ @@ -708,7 +661,7 @@ void amdgpu_semaphore_free(struct amdgpu_device *adev, */ struct amdgpu_sync { struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; - struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS]; + struct fence *sync_to[AMDGPU_MAX_RINGS]; DECLARE_HASHTABLE(fences, 4); struct fence *last_vm_update; }; @@ -905,8 +858,6 @@ struct amdgpu_ring { unsigned ring_size; unsigned ring_free_dw; int count_dw; - atomic_t last_rptr; - atomic64_t last_activity; uint64_t gpu_addr; uint32_t align_mask; uint32_t ptr_mask; @@ -960,6 +911,11 @@ struct amdgpu_ring { #define AMDGPU_PTE_FRAG_64KB (4 << 7) #define AMDGPU_LOG2_PAGES_PER_FRAG 4 +/* How to programm VM fault handling */ +#define AMDGPU_VM_FAULT_STOP_NEVER 0 +#define AMDGPU_VM_FAULT_STOP_FIRST 1 +#define AMDGPU_VM_FAULT_STOP_ALWAYS 2 + struct amdgpu_vm_pt { struct amdgpu_bo *bo; uint64_t addr; @@ -971,7 +927,7 @@ struct amdgpu_vm_id { /* last flushed PD/PT update */ struct fence *flushed_updates; /* last use of vmid */ - struct amdgpu_fence *last_id_use; + struct fence *last_id_use; }; struct amdgpu_vm { @@ -1004,7 +960,7 @@ struct amdgpu_vm { }; struct amdgpu_vm_manager { - struct amdgpu_fence *active[AMDGPU_NUM_VM]; + struct fence *active[AMDGPU_NUM_VM]; uint32_t max_pfn; /* number of VMIDs */ unsigned nvm; @@ -1223,8 +1179,6 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring); void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); void amdgpu_ring_undo(struct amdgpu_ring *ring); void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); -void amdgpu_ring_lockup_update(struct amdgpu_ring *ring); -bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring); unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, uint32_t **data); int amdgpu_ring_restore(struct amdgpu_ring *ring, @@ -1234,6 +1188,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, struct amdgpu_irq_src *irq_src, unsigned irq_type, enum amdgpu_ring_type ring_type); void amdgpu_ring_fini(struct amdgpu_ring *ring); +struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); /* * CS. @@ -1708,7 +1663,7 @@ struct amdgpu_vce { /* * SDMA */ -struct amdgpu_sdma { +struct amdgpu_sdma_instance { /* SDMA firmware */ const struct firmware *fw; uint32_t fw_version; @@ -1718,6 +1673,13 @@ struct amdgpu_sdma { bool burst_nop; }; +struct amdgpu_sdma { + struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; + struct amdgpu_irq_src trap_irq; + struct amdgpu_irq_src illegal_inst_irq; + int num_instances; +}; + /* * Firmware */ @@ -1750,11 +1712,11 @@ void amdgpu_test_syncing(struct amdgpu_device *adev); int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); void amdgpu_mn_unregister(struct amdgpu_bo *bo); #else -static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) { return -ENODEV; } -static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} #endif /* @@ -1946,7 +1908,6 @@ struct amdgpu_device { struct device *dev; struct drm_device *ddev; struct pci_dev *pdev; - struct rw_semaphore exclusive_lock; /* ASIC */ enum amd_asic_type asic_type; @@ -1960,7 +1921,6 @@ struct amdgpu_device { bool suspend; bool need_dma32; bool accel_working; - bool needs_reset; struct work_struct reset_work; struct notifier_block acpi_nb; struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; @@ -2064,9 +2024,7 @@ struct amdgpu_device { struct amdgpu_gfx gfx; /* sdma */ - struct amdgpu_sdma sdma[AMDGPU_MAX_SDMA_INSTANCES]; - struct amdgpu_irq_src sdma_trap_irq; - struct amdgpu_irq_src sdma_illegal_inst_irq; + struct amdgpu_sdma sdma; /* uvd */ bool has_uvd; @@ -2203,17 +2161,18 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) ring->ring_free_dw--; } -static inline struct amdgpu_sdma * amdgpu_get_sdma_instance(struct amdgpu_ring *ring) +static inline struct amdgpu_sdma_instance * +amdgpu_get_sdma_instance(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; int i; - for (i = 0; i < AMDGPU_MAX_SDMA_INSTANCES; i++) - if (&adev->sdma[i].ring == ring) + for (i = 0; i < adev->sdma.num_instances; i++) + if (&adev->sdma.instance[i].ring == ring) break; if (i < AMDGPU_MAX_SDMA_INSTANCES) - return &adev->sdma[i]; + return &adev->sdma.instance[i]; else return NULL; } @@ -2240,7 +2199,6 @@ static inline struct amdgpu_sdma * amdgpu_get_sdma_instance(struct amdgpu_ring * #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) -#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r)) #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) @@ -2349,10 +2307,10 @@ void amdgpu_driver_preclose_kms(struct drm_device *dev, struct drm_file *file_priv); int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); -u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc); -int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc); -void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc); -int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, +u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); +int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); +void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); +int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, unsigned flags); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index aef4a7aac0f7..a142d5ae148d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -25,7 +25,6 @@ #include <linux/acpi.h> #include <linux/slab.h> #include <linux/power_supply.h> -#include <linux/vga_switcheroo.h> #include <acpi/video.h> #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c index dd2037bc0b4a..0e1376317683 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c @@ -649,12 +649,12 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) case KGD_ENGINE_SDMA1: hdr = (const union amdgpu_firmware_header *) - adev->sdma[0].fw->data; + adev->sdma.instance[0].fw->data; break; case KGD_ENGINE_SDMA2: hdr = (const union amdgpu_firmware_header *) - adev->sdma[1].fw->data; + adev->sdma.instance[1].fw->data; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c index dfd1d503bccf..79fa5c7de856 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c @@ -523,12 +523,12 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) case KGD_ENGINE_SDMA1: hdr = (const union amdgpu_firmware_header *) - adev->sdma[0].fw->data; + adev->sdma.instance[0].fw->data; break; case KGD_ENGINE_SDMA2: hdr = (const union amdgpu_firmware_header *) - adev->sdma[1].fw->data; + adev->sdma.instance[1].fw->data; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index 3f7aaa45bf8e..5a8fbadbd27b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -501,7 +501,7 @@ static int amdgpu_atpx_get_client_id(struct pci_dev *pdev) return VGA_SWITCHEROO_DIS; } -static struct vga_switcheroo_handler amdgpu_atpx_handler = { +static const struct vga_switcheroo_handler amdgpu_atpx_handler = { .switchto = amdgpu_atpx_switchto, .power_state = amdgpu_atpx_power_state, .init = amdgpu_atpx_init, @@ -536,7 +536,7 @@ static bool amdgpu_atpx_detect(void) if (has_atpx && vga_count == 2) { acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer); - printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n", + printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n", acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; return true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 02add0a508cb..c44c0c6afd1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -29,7 +29,6 @@ #include "amdgpu.h" #include "atom.h" -#include <linux/vga_switcheroo.h> #include <linux/slab.h> #include <linux/acpi.h> /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index 1c3fc99c5465..8e995148f56e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -208,44 +208,6 @@ static int amdgpu_cgs_alloc_gpu_mem(void *cgs_device, return ret; } -static int amdgpu_cgs_import_gpu_mem(void *cgs_device, int dmabuf_fd, - cgs_handle_t *handle) -{ - CGS_FUNC_ADEV; - int r; - uint32_t dma_handle; - struct drm_gem_object *obj; - struct amdgpu_bo *bo; - struct drm_device *dev = adev->ddev; - struct drm_file *file_priv = NULL, *priv; - - mutex_lock(&dev->struct_mutex); - list_for_each_entry(priv, &dev->filelist, lhead) { - rcu_read_lock(); - if (priv->pid == get_pid(task_pid(current))) - file_priv = priv; - rcu_read_unlock(); - if (file_priv) - break; - } - mutex_unlock(&dev->struct_mutex); - r = dev->driver->prime_fd_to_handle(dev, - file_priv, dmabuf_fd, - &dma_handle); - spin_lock(&file_priv->table_lock); - - /* Check if we currently have a reference on the object */ - obj = idr_find(&file_priv->object_idr, dma_handle); - if (obj == NULL) { - spin_unlock(&file_priv->table_lock); - return -EINVAL; - } - spin_unlock(&file_priv->table_lock); - bo = gem_to_amdgpu_bo(obj); - *handle = (cgs_handle_t)bo; - return 0; -} - static int amdgpu_cgs_free_gpu_mem(void *cgs_device, cgs_handle_t handle) { struct amdgpu_bo *obj = (struct amdgpu_bo *)handle; @@ -810,7 +772,6 @@ static const struct cgs_ops amdgpu_cgs_ops = { }; static const struct cgs_os_ops amdgpu_cgs_os_ops = { - amdgpu_cgs_import_gpu_mem, amdgpu_cgs_add_irq_source, amdgpu_cgs_irq_get, amdgpu_cgs_irq_put diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 749420f1ea6f..dfc4d02c7a38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -104,10 +104,11 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, } break; case AMDGPU_HW_IP_DMA: - if (ring < 2) { - *out_ring = &adev->sdma[ring].ring; + if (ring < adev->sdma.num_instances) { + *out_ring = &adev->sdma.instance[ring].ring; } else { - DRM_ERROR("only two SDMA rings are supported\n"); + DRM_ERROR("only %d SDMA rings are supported\n", + adev->sdma.num_instances); return -EINVAL; } break; @@ -156,7 +157,8 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) uint64_t *chunk_array_user; uint64_t *chunk_array; struct amdgpu_fpriv *fpriv = p->filp->driver_priv; - unsigned size, i; + unsigned size; + int i; int ret; if (cs->in.num_chunks == 0) @@ -176,7 +178,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) /* get chunks */ INIT_LIST_HEAD(&p->validated); - chunk_array_user = (uint64_t __user *)(cs->in.chunks); + chunk_array_user = (uint64_t __user *)(unsigned long)(cs->in.chunks); if (copy_from_user(chunk_array, chunk_array_user, sizeof(uint64_t)*cs->in.num_chunks)) { ret = -EFAULT; @@ -196,7 +198,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) struct drm_amdgpu_cs_chunk user_chunk; uint32_t __user *cdata; - chunk_ptr = (void __user *)chunk_array[i]; + chunk_ptr = (void __user *)(unsigned long)chunk_array[i]; if (copy_from_user(&user_chunk, chunk_ptr, sizeof(struct drm_amdgpu_cs_chunk))) { ret = -EFAULT; @@ -207,7 +209,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data) p->chunks[i].length_dw = user_chunk.length_dw; size = p->chunks[i].length_dw; - cdata = (void __user *)user_chunk.chunk_data; + cdata = (void __user *)(unsigned long)user_chunk.chunk_data; p->chunks[i].user_ptr = cdata; p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t)); @@ -566,9 +568,24 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p, if (r) return r; } + + } + + r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); + + if (amdgpu_vm_debug && p->bo_list) { + /* Invalidate all BOs to test for userspace bugs */ + for (i = 0; i < p->bo_list->num_entries; i++) { + /* ignore duplicates */ + bo = p->bo_list->array[i].robj; + if (!bo) + continue; + + amdgpu_vm_bo_invalidate(adev, bo); + } } - return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync); + return r; } static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, @@ -592,7 +609,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, } } - mutex_lock(&vm->mutex); r = amdgpu_bo_vm_update_pte(parser, vm); if (r) { goto out; @@ -603,7 +619,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev, parser->filp); out: - mutex_unlock(&vm->mutex); return r; } @@ -811,15 +826,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) { struct amdgpu_device *adev = dev->dev_private; union drm_amdgpu_cs *cs = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_cs_parser *parser; bool reserved_buffers = false; int i, r; - down_read(&adev->exclusive_lock); - if (!adev->accel_working) { - up_read(&adev->exclusive_lock); + if (!adev->accel_working) return -EBUSY; - } parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0); if (!parser) @@ -827,12 +841,11 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) r = amdgpu_cs_parser_init(parser, data); if (r) { DRM_ERROR("Failed to initialize parser !\n"); - kfree(parser); - up_read(&adev->exclusive_lock); + amdgpu_cs_parser_fini(parser, r, false); r = amdgpu_cs_handle_lockup(adev, r); return r; } - + mutex_lock(&vm->mutex); r = amdgpu_cs_parser_relocs(parser); if (r == -ENOMEM) DRM_ERROR("Not enough memory for command submission!\n"); @@ -863,8 +876,10 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) struct amdgpu_job *job; struct amdgpu_ring * ring = parser->ibs->ring; job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL); - if (!job) - return -ENOMEM; + if (!job) { + r = -ENOMEM; + goto out; + } job->base.sched = &ring->sched; job->base.s_entity = &parser->ctx->rings[ring->idx].entity; job->adev = parser->adev; @@ -899,14 +914,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) mutex_unlock(&job->job_lock); amdgpu_cs_parser_fini_late(parser); - up_read(&adev->exclusive_lock); + mutex_unlock(&vm->mutex); return 0; } cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence; out: amdgpu_cs_parser_fini(parser, r, reserved_buffers); - up_read(&adev->exclusive_lock); + mutex_unlock(&vm->mutex); r = amdgpu_cs_handle_lockup(adev, r); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index e0b80ccdfe8a..fec65f01c031 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -69,6 +69,9 @@ void amdgpu_ctx_fini(struct amdgpu_ctx *ctx) struct amdgpu_device *adev = ctx->adev; unsigned i, j; + if (!adev) + return; + for (i = 0; i < AMDGPU_MAX_RINGS; ++i) for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j) fence_put(ctx->rings[i].fences[j]); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6068d8207d10..d5b421330145 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -57,6 +57,7 @@ static const char *amdgpu_asic_name[] = { "TONGA", "FIJI", "CARRIZO", + "STONEY", "LAST", }; @@ -1022,7 +1023,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) * amdgpu_switcheroo_set_state - set switcheroo state * * @pdev: pci dev pointer - * @state: vga switcheroo state + * @state: vga_switcheroo state * * Callback for the switcheroo driver. Suspends or resumes the * the asics before or after it is powered up using ACPI methods. @@ -1165,7 +1166,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) case CHIP_TONGA: case CHIP_FIJI: case CHIP_CARRIZO: - if (adev->asic_type == CHIP_CARRIZO) + case CHIP_STONEY: + if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) adev->family = AMDGPU_FAMILY_CZ; else adev->family = AMDGPU_FAMILY_VI; @@ -1418,7 +1420,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->gfx.gpu_clock_mutex); mutex_init(&adev->srbm_mutex); mutex_init(&adev->grbm_idx_mutex); - init_rwsem(&adev->exclusive_lock); mutex_init(&adev->mn_lock); hash_init(adev->mn_hash); @@ -1657,11 +1658,21 @@ int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) } drm_modeset_unlock_all(dev); - /* unpin the front buffers */ + /* unpin the front buffers and cursors */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb); struct amdgpu_bo *robj; + if (amdgpu_crtc->cursor_bo) { + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + r = amdgpu_bo_reserve(aobj, false); + if (r == 0) { + amdgpu_bo_unpin(aobj); + amdgpu_bo_unreserve(aobj); + } + } + if (rfb == NULL || rfb->obj == NULL) { continue; } @@ -1713,6 +1724,7 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon) { struct drm_connector *connector; struct amdgpu_device *adev = dev->dev_private; + struct drm_crtc *crtc; int r; if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) @@ -1746,6 +1758,24 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon) if (r) return r; + /* pin cursors */ + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (amdgpu_crtc->cursor_bo) { + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + r = amdgpu_bo_reserve(aobj, false); + if (r == 0) { + r = amdgpu_bo_pin(aobj, + AMDGPU_GEM_DOMAIN_VRAM, + &amdgpu_crtc->cursor_addr); + if (r != 0) + DRM_ERROR("Failed to pin cursor BO (%d)\n", r); + amdgpu_bo_unreserve(aobj); + } + } + } + /* blat the mode back in */ if (fbcon) { drm_helper_resume_force_mode(dev); @@ -1785,14 +1815,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev) int i, r; int resched; - down_write(&adev->exclusive_lock); - - if (!adev->needs_reset) { - up_write(&adev->exclusive_lock); - return 0; - } - - adev->needs_reset = false; atomic_inc(&adev->gpu_reset_counter); /* block TTM */ @@ -1856,7 +1878,6 @@ retry: dev_info(adev->dev, "GPU reset failed\n"); } - up_write(&adev->exclusive_lock); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 9b34a3410c32..d747fca59669 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -47,11 +47,8 @@ static void amdgpu_flip_wait_fence(struct amdgpu_device *adev, fence = to_amdgpu_fence(*f); if (fence) { r = fence_wait(&fence->base, false); - if (r == -EDEADLK) { - up_read(&adev->exclusive_lock); + if (r == -EDEADLK) r = amdgpu_gpu_reset(adev); - down_read(&adev->exclusive_lock); - } } else r = fence_wait(*f, false); @@ -77,7 +74,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work) unsigned long flags; unsigned i; - down_read(&adev->exclusive_lock); amdgpu_flip_wait_fence(adev, &work->excl); for (i = 0; i < work->shared_count; ++i) amdgpu_flip_wait_fence(adev, &work->shared[i]); @@ -93,7 +89,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work) amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - up_read(&adev->exclusive_lock); } /* @@ -721,7 +716,7 @@ bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, * an optional accurate timestamp of when query happened. * * \param dev Device to query. - * \param crtc Crtc to query. + * \param pipe Crtc to query. * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). * \param *vpos Location where vertical scanout position should be stored. * \param *hpos Location where horizontal scanout position should go. @@ -744,8 +739,9 @@ bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, * unknown small number of scanlines wrt. real scanout position. * */ -int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, - int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, +int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode) { u32 vbl = 0, position = 0; @@ -760,7 +756,7 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl if (stime) *stime = ktime_get(); - if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0) + if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) ret |= DRM_SCANOUTPOS_VALID; /* Get optional system timestamp after query. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index adb48353f2e1..0508c5cd103a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -73,13 +73,15 @@ int amdgpu_hard_reset = 0; unsigned amdgpu_ip_block_mask = 0xffffffff; int amdgpu_bapm = -1; int amdgpu_deep_color = 0; -int amdgpu_vm_size = 8; +int amdgpu_vm_size = 64; int amdgpu_vm_block_size = -1; +int amdgpu_vm_fault_stop = 0; +int amdgpu_vm_debug = 0; int amdgpu_exp_hw_support = 0; -int amdgpu_enable_scheduler = 0; +int amdgpu_enable_scheduler = 1; int amdgpu_sched_jobs = 16; int amdgpu_sched_hw_submission = 2; -int amdgpu_enable_semaphores = 1; +int amdgpu_enable_semaphores = 0; MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); @@ -135,16 +137,22 @@ module_param_named(bapm, amdgpu_bapm, int, 0444); MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); module_param_named(deep_color, amdgpu_deep_color, int, 0444); -MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)"); +MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); module_param_named(vm_size, amdgpu_vm_size, int, 0444); MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); +MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); +module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); + +MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); +module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); + MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); -MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable, 0 = disable ((default))"); +MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)"); module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444); MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)"); @@ -153,7 +161,7 @@ module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); -MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable (default), 0 = disable)"); +MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))"); module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644); static struct pci_device_id pciidlist[] = { @@ -242,11 +250,11 @@ static struct pci_device_id pciidlist[] = { {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, #endif /* topaz */ - {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, - {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, - {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, - {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, - {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, + {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, + {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ|AMD_EXP_HW_SUPPORT}, /* tonga */ {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, @@ -265,6 +273,8 @@ static struct pci_device_id pciidlist[] = { {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, + /* stoney */ + {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, {0, 0, 0} }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 8a122b1b7786..093a8c618931 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -207,6 +207,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, } info->par = rfbdev; + info->skip_vt_switch = true; ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj); if (ret) { @@ -402,3 +403,19 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; return false; } + +void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev) +{ + struct amdgpu_fbdev *afbdev = adev->mode_info.rfbdev; + struct drm_fb_helper *fb_helper; + int ret; + + if (!afbdev) + return; + + fb_helper = &afbdev->helper; + + ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); + if (ret) + DRM_DEBUG("failed to restore crtc mode\n"); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index b3fc26c59787..257d72205bb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -137,42 +137,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, } /** - * amdgpu_fence_check_signaled - callback from fence_queue - * - * this function is called with fence_queue lock held, which is also used - * for the fence locking itself, so unlocked variants are used for - * fence_signal, and remove_wait_queue. - */ -static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key) -{ - struct amdgpu_fence *fence; - struct amdgpu_device *adev; - u64 seq; - int ret; - - fence = container_of(wait, struct amdgpu_fence, fence_wake); - adev = fence->ring->adev; - - /* - * We cannot use amdgpu_fence_process here because we're already - * in the waitqueue, in a call from wake_up_all. - */ - seq = atomic64_read(&fence->ring->fence_drv.last_seq); - if (seq >= fence->seq) { - ret = fence_signal_locked(&fence->base); - if (!ret) - FENCE_TRACE(&fence->base, "signaled from irq context\n"); - else - FENCE_TRACE(&fence->base, "was already signaled\n"); - - __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake); - fence_put(&fence->base); - } else - FENCE_TRACE(&fence->base, "pending\n"); - return 0; -} - -/** * amdgpu_fence_activity - check for fence activity * * @ring: pointer to struct amdgpu_ring @@ -260,27 +224,8 @@ static void amdgpu_fence_check_lockup(struct work_struct *work) lockup_work.work); ring = fence_drv->ring; - if (!down_read_trylock(&ring->adev->exclusive_lock)) { - /* just reschedule the check if a reset is going on */ - amdgpu_fence_schedule_check(ring); - return; - } - - if (amdgpu_fence_activity(ring)) { - wake_up_all(&ring->fence_drv.fence_queue); - } - else if (amdgpu_ring_is_lockup(ring)) { - /* good news we believe it's a lockup */ - dev_warn(ring->adev->dev, "GPU lockup (current fence id " - "0x%016llx last fence id 0x%016llx on ring %d)\n", - (uint64_t)atomic64_read(&fence_drv->last_seq), - fence_drv->sync_seq[ring->idx], ring->idx); - - /* remember that we need an reset */ - ring->adev->needs_reset = true; + if (amdgpu_fence_activity(ring)) wake_up_all(&ring->fence_drv.fence_queue); - } - up_read(&ring->adev->exclusive_lock); } /** @@ -324,50 +269,6 @@ static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq) return false; } -static bool amdgpu_fence_is_signaled(struct fence *f) -{ - struct amdgpu_fence *fence = to_amdgpu_fence(f); - struct amdgpu_ring *ring = fence->ring; - struct amdgpu_device *adev = ring->adev; - - if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) - return true; - - if (down_read_trylock(&adev->exclusive_lock)) { - amdgpu_fence_process(ring); - up_read(&adev->exclusive_lock); - - if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) - return true; - } - return false; -} - -/** - * amdgpu_fence_enable_signaling - enable signalling on fence - * @fence: fence - * - * This function is called with fence_queue lock held, and adds a callback - * to fence_queue that checks if this fence is signaled, and if so it - * signals the fence and removes itself. - */ -static bool amdgpu_fence_enable_signaling(struct fence *f) -{ - struct amdgpu_fence *fence = to_amdgpu_fence(f); - struct amdgpu_ring *ring = fence->ring; - - if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) - return false; - - fence->fence_wake.flags = 0; - fence->fence_wake.private = NULL; - fence->fence_wake.func = amdgpu_fence_check_signaled; - __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake); - fence_get(f); - FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); - return true; -} - /* * amdgpu_ring_wait_seq_timeout - wait for seq of the specific ring to signal * @ring: ring to wait on for the seq number @@ -380,7 +281,6 @@ static bool amdgpu_fence_enable_signaling(struct fence *f) */ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) { - struct amdgpu_device *adev = ring->adev; bool signaled = false; BUG_ON(!ring); @@ -390,9 +290,9 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq) if (atomic64_read(&ring->fence_drv.last_seq) >= seq) return 0; + amdgpu_fence_schedule_check(ring); wait_event(ring->fence_drv.fence_queue, ( - (signaled = amdgpu_fence_seq_signaled(ring, seq)) - || adev->needs_reset)); + (signaled = amdgpu_fence_seq_signaled(ring, seq)))); if (signaled) return 0; @@ -441,36 +341,6 @@ int amdgpu_fence_wait_empty(struct amdgpu_ring *ring) } /** - * amdgpu_fence_ref - take a ref on a fence - * - * @fence: amdgpu fence object - * - * Take a reference on a fence (all asics). - * Returns the fence. - */ -struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence) -{ - fence_get(&fence->base); - return fence; -} - -/** - * amdgpu_fence_unref - remove a ref on a fence - * - * @fence: amdgpu fence object - * - * Remove a reference on a fence (all asics). - */ -void amdgpu_fence_unref(struct amdgpu_fence **fence) -{ - struct amdgpu_fence *tmp = *fence; - - *fence = NULL; - if (tmp) - fence_put(&tmp->base); -} - -/** * amdgpu_fence_count_emitted - get the count of emitted fences * * @ring: ring the fence is associated with @@ -628,8 +498,20 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) init_waitqueue_head(&ring->fence_drv.fence_queue); if (amdgpu_enable_scheduler) { + long timeout = msecs_to_jiffies(amdgpu_lockup_timeout); + if (timeout == 0) { + /* + * FIXME: + * Delayed workqueue cannot use it directly, + * so the scheduler will not use delayed workqueue if + * MAX_SCHEDULE_TIMEOUT is set. + * Currently keep it simple and silly. + */ + timeout = MAX_SCHEDULE_TIMEOUT; + } r = amd_sched_init(&ring->sched, &amdgpu_sched_ops, - amdgpu_sched_hw_submission, ring->name); + amdgpu_sched_hw_submission, + timeout, ring->name); if (r) { DRM_ERROR("Failed to create scheduler on ring %s.\n", ring->name); @@ -773,6 +655,115 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev) } } +/* + * Common fence implementation + */ + +static const char *amdgpu_fence_get_driver_name(struct fence *fence) +{ + return "amdgpu"; +} + +static const char *amdgpu_fence_get_timeline_name(struct fence *f) +{ + struct amdgpu_fence *fence = to_amdgpu_fence(f); + return (const char *)fence->ring->name; +} + +/** + * amdgpu_fence_is_signaled - test if fence is signaled + * + * @f: fence to test + * + * Test the fence sequence number if it is already signaled. If it isn't + * signaled start fence processing. Returns True if the fence is signaled. + */ +static bool amdgpu_fence_is_signaled(struct fence *f) +{ + struct amdgpu_fence *fence = to_amdgpu_fence(f); + struct amdgpu_ring *ring = fence->ring; + + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) + return true; + + amdgpu_fence_process(ring); + + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) + return true; + + return false; +} + +/** + * amdgpu_fence_check_signaled - callback from fence_queue + * + * this function is called with fence_queue lock held, which is also used + * for the fence locking itself, so unlocked variants are used for + * fence_signal, and remove_wait_queue. + */ +static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key) +{ + struct amdgpu_fence *fence; + struct amdgpu_device *adev; + u64 seq; + int ret; + + fence = container_of(wait, struct amdgpu_fence, fence_wake); + adev = fence->ring->adev; + + /* + * We cannot use amdgpu_fence_process here because we're already + * in the waitqueue, in a call from wake_up_all. + */ + seq = atomic64_read(&fence->ring->fence_drv.last_seq); + if (seq >= fence->seq) { + ret = fence_signal_locked(&fence->base); + if (!ret) + FENCE_TRACE(&fence->base, "signaled from irq context\n"); + else + FENCE_TRACE(&fence->base, "was already signaled\n"); + + __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake); + fence_put(&fence->base); + } else + FENCE_TRACE(&fence->base, "pending\n"); + return 0; +} + +/** + * amdgpu_fence_enable_signaling - enable signalling on fence + * @fence: fence + * + * This function is called with fence_queue lock held, and adds a callback + * to fence_queue that checks if this fence is signaled, and if so it + * signals the fence and removes itself. + */ +static bool amdgpu_fence_enable_signaling(struct fence *f) +{ + struct amdgpu_fence *fence = to_amdgpu_fence(f); + struct amdgpu_ring *ring = fence->ring; + + if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq) + return false; + + fence->fence_wake.flags = 0; + fence->fence_wake.private = NULL; + fence->fence_wake.func = amdgpu_fence_check_signaled; + __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake); + fence_get(f); + amdgpu_fence_schedule_check(ring); + FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx); + return true; +} + +const struct fence_ops amdgpu_fence_ops = { + .get_driver_name = amdgpu_fence_get_driver_name, + .get_timeline_name = amdgpu_fence_get_timeline_name, + .enable_signaling = amdgpu_fence_enable_signaling, + .signaled = amdgpu_fence_is_signaled, + .wait = fence_default_wait, + .release = NULL, +}; /* * Fence debugfs @@ -823,141 +814,3 @@ int amdgpu_debugfs_fence_init(struct amdgpu_device *adev) #endif } -static const char *amdgpu_fence_get_driver_name(struct fence *fence) -{ - return "amdgpu"; -} - -static const char *amdgpu_fence_get_timeline_name(struct fence *f) -{ - struct amdgpu_fence *fence = to_amdgpu_fence(f); - return (const char *)fence->ring->name; -} - -static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence) -{ - return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags); -} - -static bool amdgpu_test_signaled_any(struct fence **fences, uint32_t count) -{ - int idx; - struct fence *fence; - - for (idx = 0; idx < count; ++idx) { - fence = fences[idx]; - if (fence) { - if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags)) - return true; - } - } - return false; -} - -struct amdgpu_wait_cb { - struct fence_cb base; - struct task_struct *task; -}; - -static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb) -{ - struct amdgpu_wait_cb *wait = - container_of(cb, struct amdgpu_wait_cb, base); - wake_up_process(wait->task); -} - -static signed long amdgpu_fence_default_wait(struct fence *f, bool intr, - signed long t) -{ - struct amdgpu_fence *fence = to_amdgpu_fence(f); - struct amdgpu_device *adev = fence->ring->adev; - - return amdgpu_fence_wait_any(adev, &f, 1, intr, t); -} - -/** - * Wait the fence array with timeout - * - * @adev: amdgpu device - * @array: the fence array with amdgpu fence pointer - * @count: the number of the fence array - * @intr: when sleep, set the current task interruptable or not - * @t: timeout to wait - * - * It will return when any fence is signaled or timeout. - */ -signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, - struct fence **array, uint32_t count, - bool intr, signed long t) -{ - struct amdgpu_wait_cb *cb; - struct fence *fence; - unsigned idx; - - BUG_ON(!array); - - cb = kcalloc(count, sizeof(struct amdgpu_wait_cb), GFP_KERNEL); - if (cb == NULL) { - t = -ENOMEM; - goto err_free_cb; - } - - for (idx = 0; idx < count; ++idx) { - fence = array[idx]; - if (fence) { - cb[idx].task = current; - if (fence_add_callback(fence, - &cb[idx].base, amdgpu_fence_wait_cb)) { - /* The fence is already signaled */ - goto fence_rm_cb; - } - } - } - - while (t > 0) { - if (intr) - set_current_state(TASK_INTERRUPTIBLE); - else - set_current_state(TASK_UNINTERRUPTIBLE); - - /* - * amdgpu_test_signaled_any must be called after - * set_current_state to prevent a race with wake_up_process - */ - if (amdgpu_test_signaled_any(array, count)) - break; - - if (adev->needs_reset) { - t = -EDEADLK; - break; - } - - t = schedule_timeout(t); - - if (t > 0 && intr && signal_pending(current)) - t = -ERESTARTSYS; - } - - __set_current_state(TASK_RUNNING); - -fence_rm_cb: - for (idx = 0; idx < count; ++idx) { - fence = array[idx]; - if (fence && cb[idx].base.func) - fence_remove_callback(fence, &cb[idx].base); - } - -err_free_cb: - kfree(cb); - - return t; -} - -const struct fence_ops amdgpu_fence_ops = { - .get_driver_name = amdgpu_fence_get_driver_name, - .get_timeline_name = amdgpu_fence_get_timeline_name, - .enable_signaling = amdgpu_fence_enable_signaling, - .signaled = amdgpu_fence_is_signaled, - .wait = amdgpu_fence_default_wait, - .release = NULL, -}; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 7297ca3a0ba7..087332858853 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -115,9 +115,10 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; int r; - + mutex_lock(&vm->mutex); r = amdgpu_bo_reserve(rbo, false); if (r) { + mutex_unlock(&vm->mutex); return r; } @@ -128,7 +129,7 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri ++bo_va->ref_count; } amdgpu_bo_unreserve(rbo); - + mutex_unlock(&vm->mutex); return 0; } @@ -141,9 +142,10 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct amdgpu_vm *vm = &fpriv->vm; struct amdgpu_bo_va *bo_va; int r; - + mutex_lock(&vm->mutex); r = amdgpu_bo_reserve(rbo, true); if (r) { + mutex_unlock(&vm->mutex); dev_err(adev->dev, "leaking bo va because " "we fail to reserve bo (%d)\n", r); return; @@ -155,6 +157,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, } } amdgpu_bo_unreserve(rbo); + mutex_unlock(&vm->mutex); } static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) @@ -181,7 +184,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, bool kernel = false; int r; - down_read(&adev->exclusive_lock); /* create a gem object to contain this object in */ if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { @@ -214,11 +216,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, memset(args, 0, sizeof(*args)); args->out.handle = handle; - up_read(&adev->exclusive_lock); return 0; error_unlock: - up_read(&adev->exclusive_lock); r = amdgpu_gem_handle_lockup(adev, r); return r; } @@ -250,8 +250,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return -EACCES; } - down_read(&adev->exclusive_lock); - /* create a gem object to contain this object in */ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 0, @@ -293,14 +291,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, goto handle_lockup; args->handle = handle; - up_read(&adev->exclusive_lock); return 0; release_object: drm_gem_object_unreference_unlocked(gobj); handle_lockup: - up_read(&adev->exclusive_lock); r = amdgpu_gem_handle_lockup(adev, r); return r; @@ -488,18 +484,13 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, goto error_unreserve; } - mutex_lock(&bo_va->vm->mutex); r = amdgpu_vm_clear_freed(adev, bo_va->vm); if (r) - goto error_unlock; - + goto error_unreserve; if (operation == AMDGPU_VA_OP_MAP) r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); -error_unlock: - mutex_unlock(&bo_va->vm->mutex); - error_unreserve: ttm_eu_backoff_reservation(&ticket, &list); @@ -556,10 +547,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, gobj = drm_gem_object_lookup(dev, filp, args->handle); if (gobj == NULL) return -ENOENT; - + mutex_lock(&fpriv->vm.mutex); rbo = gem_to_amdgpu_bo(gobj); r = amdgpu_bo_reserve(rbo, false); if (r) { + mutex_unlock(&fpriv->vm.mutex); drm_gem_object_unreference_unlocked(gobj); return r; } @@ -567,6 +559,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); if (!bo_va) { amdgpu_bo_unreserve(rbo); + mutex_unlock(&fpriv->vm.mutex); return -ENOENT; } @@ -591,7 +584,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) amdgpu_gem_va_update_vm(adev, bo_va, args->operation); - + mutex_unlock(&fpriv->vm.mutex); drm_gem_object_unreference_unlocked(gobj); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index c439735ee670..e65987743871 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -95,7 +95,8 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib) { amdgpu_sync_free(adev, &ib->sync, &ib->fence->base); amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base); - amdgpu_fence_unref(&ib->fence); + if (ib->fence) + fence_put(&ib->fence->base); } /** @@ -298,7 +299,6 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev) r = amdgpu_ring_test_ib(ring); if (r) { ring->ready = false; - adev->needs_reset = false; if (ring == &adev->gfx.gfx_ring[0]) { /* oh, oh, that's really bad */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 275f1c3dbba0..1618e2294a16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -218,8 +218,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file break; case AMDGPU_HW_IP_DMA: type = AMD_IP_BLOCK_TYPE_SDMA; - ring_mask = adev->sdma[0].ring.ready ? 1 : 0; - ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1); + for (i = 0; i < adev->sdma.num_instances; i++) + ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; ib_size_alignment = 1; break; @@ -341,10 +341,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file fw_info.feature = 0; break; case AMDGPU_INFO_FW_SDMA: - if (info->query_fw.index >= 2) + if (info->query_fw.index >= adev->sdma.num_instances) return -EINVAL; - fw_info.ver = adev->sdma[info->query_fw.index].fw_version; - fw_info.feature = adev->sdma[info->query_fw.index].feature_version; + fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version; + fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version; break; default: return -EINVAL; @@ -485,14 +485,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file * Outdated mess for old drm with Xorg being in charge (void function now). */ /** - * amdgpu_driver_firstopen_kms - drm callback for last close + * amdgpu_driver_lastclose_kms - drm callback for last close * * @dev: drm dev pointer * - * Switch vga switcheroo state after last close (all asics). + * Switch vga_switcheroo state after last close (all asics). */ void amdgpu_driver_lastclose_kms(struct drm_device *dev) { + struct amdgpu_device *adev = dev->dev_private; + + amdgpu_fbdev_restore_mode(adev); vga_switcheroo_process_delayed_switch(); } @@ -600,36 +603,36 @@ void amdgpu_driver_preclose_kms(struct drm_device *dev, * amdgpu_get_vblank_counter_kms - get frame count * * @dev: drm dev pointer - * @crtc: crtc to get the frame count from + * @pipe: crtc to get the frame count from * * Gets the frame count on the requested crtc (all asics). * Returns frame count on success, -EINVAL on failure. */ -u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc) +u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) { struct amdgpu_device *adev = dev->dev_private; - if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { - DRM_ERROR("Invalid crtc %d\n", crtc); + if (pipe >= adev->mode_info.num_crtc) { + DRM_ERROR("Invalid crtc %u\n", pipe); return -EINVAL; } - return amdgpu_display_vblank_get_counter(adev, crtc); + return amdgpu_display_vblank_get_counter(adev, pipe); } /** * amdgpu_enable_vblank_kms - enable vblank interrupt * * @dev: drm dev pointer - * @crtc: crtc to enable vblank interrupt for + * @pipe: crtc to enable vblank interrupt for * * Enable the interrupt on the requested crtc (all asics). * Returns 0 on success, -EINVAL on failure. */ -int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) +int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) { struct amdgpu_device *adev = dev->dev_private; - int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc); + int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); return amdgpu_irq_get(adev, &adev->crtc_irq, idx); } @@ -638,14 +641,14 @@ int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) * amdgpu_disable_vblank_kms - disable vblank interrupt * * @dev: drm dev pointer - * @crtc: crtc to disable vblank interrupt for + * @pipe: crtc to disable vblank interrupt for * * Disable the interrupt on the requested crtc (all asics). */ -void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) +void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) { struct amdgpu_device *adev = dev->dev_private; - int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc); + int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); amdgpu_irq_put(adev, &adev->crtc_irq, idx); } @@ -663,41 +666,41 @@ void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) * scanout position. (all asics). * Returns postive status flags on success, negative error on failure. */ -int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, +int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, unsigned flags) { - struct drm_crtc *drmcrtc; + struct drm_crtc *crtc; struct amdgpu_device *adev = dev->dev_private; - if (crtc < 0 || crtc >= dev->num_crtcs) { - DRM_ERROR("Invalid crtc %d\n", crtc); + if (pipe >= dev->num_crtcs) { + DRM_ERROR("Invalid crtc %u\n", pipe); return -EINVAL; } /* Get associated drm_crtc: */ - drmcrtc = &adev->mode_info.crtcs[crtc]->base; + crtc = &adev->mode_info.crtcs[pipe]->base; /* Helper routine in DRM core does all the work: */ - return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error, + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, flags, - &drmcrtc->hwmode); + &crtc->hwmode); } const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), /* KMS */ - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), }; int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 2b03425f9740..b62c1710cab6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -373,6 +373,10 @@ struct amdgpu_crtc { uint32_t crtc_offset; struct drm_gem_object *cursor_bo; uint64_t cursor_addr; + int cursor_x; + int cursor_y; + int cursor_hot_x; + int cursor_hot_y; int cursor_width; int cursor_height; int max_cursor_width; @@ -540,11 +544,10 @@ bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux); void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); -int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, - unsigned int flags, - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime, - const struct drm_display_mode *mode); +int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode); int amdgpu_framebuffer_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, @@ -568,6 +571,7 @@ void amdgpu_fbdev_fini(struct amdgpu_device *adev); void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); int amdgpu_fbdev_total_size(struct amdgpu_device *adev); bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); +void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 1a7708f365f3..0d524384ff79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -132,6 +132,8 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, placements[c].fpfn = 0; placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM; + if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) + placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN; } if (domain & AMDGPU_GEM_DOMAIN_GTT) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 30dce235ddeb..78e9b0f14661 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -67,8 +67,6 @@ void amdgpu_ring_free_size(struct amdgpu_ring *ring) if (!ring->ring_free_dw) { /* this is an empty ring */ ring->ring_free_dw = ring->ring_size / 4; - /* update lockup info to avoid false positive */ - amdgpu_ring_lockup_update(ring); } } @@ -209,46 +207,6 @@ void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring) } /** - * amdgpu_ring_lockup_update - update lockup variables - * - * @ring: amdgpu_ring structure holding ring information - * - * Update the last rptr value and timestamp (all asics). - */ -void amdgpu_ring_lockup_update(struct amdgpu_ring *ring) -{ - atomic_set(&ring->last_rptr, amdgpu_ring_get_rptr(ring)); - atomic64_set(&ring->last_activity, jiffies_64); -} - -/** - * amdgpu_ring_test_lockup() - check if ring is lockedup by recording information - * @ring: amdgpu_ring structure holding ring information - * - */ -bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring) -{ - uint32_t rptr = amdgpu_ring_get_rptr(ring); - uint64_t last = atomic64_read(&ring->last_activity); - uint64_t elapsed; - - if (rptr != atomic_read(&ring->last_rptr)) { - /* ring is still working, no lockup */ - amdgpu_ring_lockup_update(ring); - return false; - } - - elapsed = jiffies_to_msecs(jiffies_64 - last); - if (amdgpu_lockup_timeout && elapsed >= amdgpu_lockup_timeout) { - dev_err(ring->adev->dev, "ring %d stalled for more than %llumsec\n", - ring->idx, elapsed); - return true; - } - /* give a chance to the GPU ... */ - return false; -} - -/** * amdgpu_ring_backup - Back up the content of a ring * * @ring: the ring we want to back up @@ -436,7 +394,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, if (amdgpu_debugfs_ring_init(adev, ring)) { DRM_ERROR("Failed to register debugfs file for rings !\n"); } - amdgpu_ring_lockup_update(ring); return 0; } @@ -479,6 +436,30 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring) } } +/** + * amdgpu_ring_from_fence - get ring from fence + * + * @f: fence structure + * + * Extract the ring a fence belongs to. Handles both scheduler as + * well as hardware fences. + */ +struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f) +{ + struct amdgpu_fence *a_fence; + struct amd_sched_fence *s_fence; + + s_fence = to_amd_sched_fence(f); + if (s_fence) + return container_of(s_fence->sched, struct amdgpu_ring, sched); + + a_fence = to_amdgpu_fence(f); + if (a_fence) + return a_fence->ring; + + return NULL; +} + /* * Debugfs info */ @@ -540,8 +521,8 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data) static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]); static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]); static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]); -static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma[0].ring); -static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma[1].ring); +static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma.instance[0].ring); +static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma.instance[1].ring); static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring); static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]); static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c index e90712443fe9..0212b31dc194 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c @@ -139,25 +139,6 @@ int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, return r; } -static uint32_t amdgpu_sa_get_ring_from_fence(struct fence *f) -{ - struct amdgpu_fence *a_fence; - struct amd_sched_fence *s_fence; - - s_fence = to_amd_sched_fence(f); - if (s_fence) { - struct amdgpu_ring *ring; - - ring = container_of(s_fence->sched, struct amdgpu_ring, sched); - return ring->idx; - } - - a_fence = to_amdgpu_fence(f); - if (a_fence) - return a_fence->ring->idx; - return 0; -} - static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo) { struct amdgpu_sa_manager *sa_manager = sa_bo->manager; @@ -318,7 +299,7 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager, } if (best_bo) { - uint32_t idx = amdgpu_sa_get_ring_from_fence(best_bo->fence); + uint32_t idx = amdgpu_ring_from_fence(best_bo->fence)->idx; ++tries[idx]; sa_manager->hole = best_bo->olist.prev; @@ -337,6 +318,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev, { struct fence *fences[AMDGPU_MAX_RINGS]; unsigned tries[AMDGPU_MAX_RINGS]; + unsigned count; int i, r; signed long t; @@ -371,13 +353,18 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev, /* see if we can skip over some allocations */ } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries)); - spin_unlock(&sa_manager->wq.lock); - t = amdgpu_fence_wait_any(adev, fences, AMDGPU_MAX_RINGS, - false, MAX_SCHEDULE_TIMEOUT); - r = (t > 0) ? 0 : t; - spin_lock(&sa_manager->wq.lock); - /* if we have nothing to wait for block */ - if (r == -ENOENT) { + for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i) + if (fences[i]) + fences[count++] = fences[i]; + + if (count) { + spin_unlock(&sa_manager->wq.lock); + t = fence_wait_any_timeout(fences, count, false, + MAX_SCHEDULE_TIMEOUT); + r = (t > 0) ? 0 : t; + spin_lock(&sa_manager->wq.lock); + } else { + /* if we have nothing to wait for block */ r = wait_event_interruptible_locked( sa_manager->wq, amdgpu_sa_event(sa_manager, size, align) @@ -406,7 +393,7 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo, if (fence && !fence_is_signaled(fence)) { uint32_t idx; (*sa_bo)->fence = fence_get(fence); - idx = amdgpu_sa_get_ring_from_fence(fence); + idx = amdgpu_ring_from_fence(fence)->idx; list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]); } else { amdgpu_sa_bo_remove_locked(*sa_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 2e946b2cad88..dcf4a8aca680 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -54,7 +54,8 @@ static struct fence *amdgpu_sched_run_job(struct amd_sched_job *sched_job) goto err; } - fence = amdgpu_fence_ref(job->ibs[job->num_ibs - 1].fence); + fence = job->ibs[job->num_ibs - 1].fence; + fence_get(&fence->base); err: if (job->free_job) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 4921de15b451..a6697fd05217 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -87,6 +87,15 @@ static bool amdgpu_sync_test_owner(struct fence *f, void *owner) return false; } +static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence) +{ + if (*keep && fence_is_later(*keep, fence)) + return; + + fence_put(*keep); + *keep = fence_get(fence); +} + /** * amdgpu_sync_fence - remember to sync to this fence * @@ -99,35 +108,21 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, { struct amdgpu_sync_entry *e; struct amdgpu_fence *fence; - struct amdgpu_fence *other; - struct fence *tmp, *later; if (!f) return 0; if (amdgpu_sync_same_dev(adev, f) && - amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) { - if (sync->last_vm_update) { - tmp = sync->last_vm_update; - BUG_ON(f->context != tmp->context); - later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp; - sync->last_vm_update = fence_get(later); - fence_put(tmp); - } else - sync->last_vm_update = fence_get(f); - } + amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) + amdgpu_sync_keep_later(&sync->last_vm_update, f); fence = to_amdgpu_fence(f); if (!fence || fence->ring->adev != adev) { hash_for_each_possible(sync->fences, e, node, f->context) { - struct fence *new; if (unlikely(e->fence->context != f->context)) continue; - new = fence_get(fence_later(e->fence, f)); - if (new) { - fence_put(e->fence); - e->fence = new; - } + + amdgpu_sync_keep_later(&e->fence, f); return 0; } @@ -140,10 +135,7 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, return 0; } - other = sync->sync_to[fence->ring->idx]; - sync->sync_to[fence->ring->idx] = amdgpu_fence_ref( - amdgpu_fence_later(fence, other)); - amdgpu_fence_unref(&other); + amdgpu_sync_keep_later(&sync->sync_to[fence->ring->idx], f); return 0; } @@ -199,8 +191,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, * for other VM updates and moves. */ fence_owner = amdgpu_sync_get_owner(f); - if ((owner != AMDGPU_FENCE_OWNER_MOVE) && - (fence_owner != AMDGPU_FENCE_OWNER_MOVE) && + if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) && + (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) && ((owner == AMDGPU_FENCE_OWNER_VM) != (fence_owner == AMDGPU_FENCE_OWNER_VM))) continue; @@ -262,11 +254,11 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync) return 0; for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - struct amdgpu_fence *fence = sync->sync_to[i]; + struct fence *fence = sync->sync_to[i]; if (!fence) continue; - r = fence_wait(&fence->base, false); + r = fence_wait(fence, false); if (r) return r; } @@ -291,9 +283,14 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync, int i, r; for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { - struct amdgpu_fence *fence = sync->sync_to[i]; - struct amdgpu_semaphore *semaphore; struct amdgpu_ring *other = adev->rings[i]; + struct amdgpu_semaphore *semaphore; + struct amdgpu_fence *fence; + + if (!sync->sync_to[i]) + continue; + + fence = to_amdgpu_fence(sync->sync_to[i]); /* check if we really need to sync */ if (!amdgpu_fence_need_sync(fence, ring)) @@ -378,7 +375,7 @@ void amdgpu_sync_free(struct amdgpu_device *adev, amdgpu_semaphore_free(adev, &sync->semaphores[i], fence); for (i = 0; i < AMDGPU_MAX_RINGS; ++i) - amdgpu_fence_unref(&sync->sync_to[i]); + fence_put(sync->sync_to[i]); fence_put(sync->last_vm_update); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 961d7265c286..76ecbaf72a2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -111,7 +111,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap, __entry->offset, __entry->flags) ); -TRACE_EVENT(amdgpu_vm_bo_update, +DECLARE_EVENT_CLASS(amdgpu_vm_mapping, TP_PROTO(struct amdgpu_bo_va_mapping *mapping), TP_ARGS(mapping), TP_STRUCT__entry( @@ -129,6 +129,16 @@ TRACE_EVENT(amdgpu_vm_bo_update, __entry->soffset, __entry->eoffset, __entry->flags) ); +DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_update, + TP_PROTO(struct amdgpu_bo_va_mapping *mapping), + TP_ARGS(mapping) +); + +DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_mapping, + TP_PROTO(struct amdgpu_bo_va_mapping *mapping), + TP_ARGS(mapping) +); + TRACE_EVENT(amdgpu_vm_set_page, TP_PROTO(uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint32_t flags), diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 364cbe975332..81bb8e9fc26d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1041,7 +1041,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, WARN_ON(ib->length_dw > num_dw); r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1, &amdgpu_vm_free_job, - AMDGPU_FENCE_OWNER_MOVE, + AMDGPU_FENCE_OWNER_UNDEFINED, fence); if (r) goto error_free; @@ -1072,6 +1072,11 @@ static int amdgpu_mm_dump_table(struct seq_file *m, void *data) spin_lock(&glob->lru_lock); ret = drm_mm_dump_table(m, mm); spin_unlock(&glob->lru_lock); + if (ttm_pl == TTM_PL_VRAM) + seq_printf(m, "man size:%llu pages, ram usage:%luMB, vis usage:%luMB\n", + adev->mman.bdev.man[ttm_pl].size, + atomic64_read(&adev->vram_usage) >> 20, + atomic64_read(&adev->vram_vis_usage) >> 20); return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index d0312364d950..53f987aeeacf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -53,6 +53,7 @@ #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" +#define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" /** * amdgpu_uvd_cs_ctx - Command submission parser context @@ -83,6 +84,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS); MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); +MODULE_FIRMWARE(FIRMWARE_STONEY); static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); static void amdgpu_uvd_idle_work_handler(struct work_struct *work); @@ -124,6 +126,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) case CHIP_CARRIZO: fw_name = FIRMWARE_CARRIZO; break; + case CHIP_STONEY: + fw_name = FIRMWARE_STONEY; + break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 74f2038ac747..03f0c3bae516 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -49,6 +49,7 @@ #define FIRMWARE_TONGA "amdgpu/tonga_vce.bin" #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin" +#define FIRMWARE_STONEY "amdgpu/stoney_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); @@ -60,6 +61,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS); MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); +MODULE_FIRMWARE(FIRMWARE_STONEY); static void amdgpu_vce_idle_work_handler(struct work_struct *work); @@ -106,6 +108,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) case CHIP_FIJI: fw_name = FIRMWARE_FIJI; break; + case CHIP_STONEY: + fw_name = FIRMWARE_STONEY; + break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 1e14531353e0..633a32a48560 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -90,11 +90,9 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, struct amdgpu_bo_list_entry *list; unsigned i, idx; - mutex_lock(&vm->mutex); list = drm_malloc_ab(vm->max_pde_used + 2, sizeof(struct amdgpu_bo_list_entry)); if (!list) { - mutex_unlock(&vm->mutex); return NULL; } @@ -119,7 +117,6 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, list[idx].tv.shared = true; list_add(&list[idx++].tv.head, head); } - mutex_unlock(&vm->mutex); return list; } @@ -138,7 +135,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync) { - struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {}; + struct fence *best[AMDGPU_MAX_RINGS] = {}; struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx]; struct amdgpu_device *adev = ring->adev; @@ -147,15 +144,18 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, /* check if the id is still valid */ if (vm_id->id && vm_id->last_id_use && - vm_id->last_id_use == adev->vm_manager.active[vm_id->id]) + vm_id->last_id_use == adev->vm_manager.active[vm_id->id]) { + trace_amdgpu_vm_grab_id(vm_id->id, ring->idx); return 0; + } /* we definately need to flush */ vm_id->pd_gpu_addr = ~0ll; /* skip over VMID 0, since it is the system VM */ for (i = 1; i < adev->vm_manager.nvm; ++i) { - struct amdgpu_fence *fence = adev->vm_manager.active[i]; + struct fence *fence = adev->vm_manager.active[i]; + struct amdgpu_ring *fring; if (fence == NULL) { /* found a free one */ @@ -164,21 +164,23 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, return 0; } - if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) { - best[fence->ring->idx] = fence; - choices[fence->ring == ring ? 0 : 1] = i; + fring = amdgpu_ring_from_fence(fence); + if (best[fring->idx] == NULL || + fence_is_later(best[fring->idx], fence)) { + best[fring->idx] = fence; + choices[fring == ring ? 0 : 1] = i; } } for (i = 0; i < 2; ++i) { if (choices[i]) { - struct amdgpu_fence *fence; + struct fence *fence; fence = adev->vm_manager.active[choices[i]]; vm_id->id = choices[i]; trace_amdgpu_vm_grab_id(choices[i], ring->idx); - return amdgpu_sync_fence(ring->adev, sync, &fence->base); + return amdgpu_sync_fence(ring->adev, sync, fence); } } @@ -247,11 +249,11 @@ void amdgpu_vm_fence(struct amdgpu_device *adev, unsigned ridx = fence->ring->idx; unsigned vm_id = vm->ids[ridx].id; - amdgpu_fence_unref(&adev->vm_manager.active[vm_id]); - adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence); + fence_put(adev->vm_manager.active[vm_id]); + adev->vm_manager.active[vm_id] = fence_get(&fence->base); - amdgpu_fence_unref(&vm->ids[ridx].last_id_use); - vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence); + fence_put(vm->ids[ridx].last_id_use); + vm->ids[ridx].last_id_use = fence_get(&fence->base); } /** @@ -455,8 +457,10 @@ int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, return -ENOMEM; r = amdgpu_ib_get(ring, NULL, ndw * 4, ib); - if (r) + if (r) { + kfree(ib); return r; + } ib->length_dw = 0; /* walk over the address space and update the page directory */ @@ -850,6 +854,14 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, return r; } + if (trace_amdgpu_vm_bo_mapping_enabled()) { + list_for_each_entry(mapping, &bo_va->valids, list) + trace_amdgpu_vm_bo_mapping(mapping); + + list_for_each_entry(mapping, &bo_va->invalids, list) + trace_amdgpu_vm_bo_mapping(mapping); + } + spin_lock(&vm->status_lock); list_splice_init(&bo_va->invalids, &bo_va->valids); list_del_init(&bo_va->vm_status); @@ -960,9 +972,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, INIT_LIST_HEAD(&bo_va->invalids); INIT_LIST_HEAD(&bo_va->vm_status); - mutex_lock(&vm->mutex); list_add_tail(&bo_va->bo_list, &bo->va); - mutex_unlock(&vm->mutex); return bo_va; } @@ -1015,8 +1025,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, return -EINVAL; } - mutex_lock(&vm->mutex); - saddr /= AMDGPU_GPU_PAGE_SIZE; eaddr /= AMDGPU_GPU_PAGE_SIZE; @@ -1030,14 +1038,14 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, tmp->it.start, tmp->it.last + 1); amdgpu_bo_unreserve(bo_va->bo); r = -EINVAL; - goto error_unlock; + goto error; } mapping = kmalloc(sizeof(*mapping), GFP_KERNEL); if (!mapping) { amdgpu_bo_unreserve(bo_va->bo); r = -ENOMEM; - goto error_unlock; + goto error; } INIT_LIST_HEAD(&mapping->list); @@ -1069,9 +1077,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, if (vm->page_tables[pt_idx].bo) continue; - /* drop mutex to allocate and clear page table */ - mutex_unlock(&vm->mutex); - ww_mutex_lock(&resv->lock, NULL); r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8, AMDGPU_GPU_PAGE_SIZE, true, @@ -1088,32 +1093,19 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev, goto error_free; } - /* aquire mutex again */ - mutex_lock(&vm->mutex); - if (vm->page_tables[pt_idx].bo) { - /* someone else allocated the pt in the meantime */ - mutex_unlock(&vm->mutex); - amdgpu_bo_unref(&pt); - mutex_lock(&vm->mutex); - continue; - } - vm->page_tables[pt_idx].addr = 0; vm->page_tables[pt_idx].bo = pt; } - mutex_unlock(&vm->mutex); return 0; error_free: - mutex_lock(&vm->mutex); list_del(&mapping->list); interval_tree_remove(&mapping->it, &vm->va); trace_amdgpu_vm_bo_unmap(bo_va, mapping); kfree(mapping); -error_unlock: - mutex_unlock(&vm->mutex); +error: return r; } @@ -1158,7 +1150,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, } } - mutex_lock(&vm->mutex); list_del(&mapping->list); interval_tree_remove(&mapping->it, &vm->va); trace_amdgpu_vm_bo_unmap(bo_va, mapping); @@ -1167,7 +1158,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, list_add(&mapping->list, &vm->freed); else kfree(mapping); - mutex_unlock(&vm->mutex); amdgpu_bo_unreserve(bo_va->bo); return 0; @@ -1191,8 +1181,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, list_del(&bo_va->bo_list); - mutex_lock(&vm->mutex); - spin_lock(&vm->status_lock); list_del(&bo_va->vm_status); spin_unlock(&vm->status_lock); @@ -1211,8 +1199,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, fence_put(bo_va->last_pt_update); kfree(bo_va); - - mutex_unlock(&vm->mutex); } /** @@ -1330,7 +1316,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { fence_put(vm->ids[i].flushed_updates); - amdgpu_fence_unref(&vm->ids[i].last_id_use); + fence_put(vm->ids[i].last_id_use); } mutex_destroy(&vm->mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c index a0346a90d805..1b50e6c13fb3 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.c +++ b/drivers/gpu/drm/amd/amdgpu/atom.c @@ -685,6 +685,27 @@ static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) } } +static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg) +{ + uint64_t val64; + uint8_t attr = U8((*ptr)++); + uint32_t dst, src; + SDEBUG(" src1: "); + dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); + SDEBUG(" src2: "); + src = atom_get_src(ctx, attr, ptr); + if (src != 0) { + val64 = dst; + val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; + do_div(val64, src); + ctx->ctx->divmul[0] = lower_32_bits(val64); + ctx->ctx->divmul[1] = upper_32_bits(val64); + } else { + ctx->ctx->divmul[0] = 0; + ctx->ctx->divmul[1] = 0; + } +} + static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) { /* functionally, a nop */ @@ -788,6 +809,20 @@ static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) ctx->ctx->divmul[0] = dst * src; } +static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg) +{ + uint64_t val64; + uint8_t attr = U8((*ptr)++); + uint32_t dst, src; + SDEBUG(" src1: "); + dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); + SDEBUG(" src2: "); + src = atom_get_src(ctx, attr, ptr); + val64 = (uint64_t)dst * (uint64_t)src; + ctx->ctx->divmul[0] = lower_32_bits(val64); + ctx->ctx->divmul[1] = upper_32_bits(val64); +} + static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) { /* nothing */ @@ -1022,7 +1057,15 @@ static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) { - printk(KERN_INFO "unimplemented!\n"); + uint8_t val = U8((*ptr)++); + SDEBUG("DEBUG output: 0x%02X\n", val); +} + +static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg) +{ + uint16_t val = U16(*ptr); + (*ptr) += val + 2; + SDEBUG("PROCESSDS output: 0x%02X\n", val); } static struct { @@ -1151,7 +1194,13 @@ static struct { atom_op_shr, ATOM_ARG_FB}, { atom_op_shr, ATOM_ARG_PLL}, { atom_op_shr, ATOM_ARG_MC}, { -atom_op_debug, 0},}; + atom_op_debug, 0}, { + atom_op_processds, 0}, { + atom_op_mul32, ATOM_ARG_PS}, { + atom_op_mul32, ATOM_ARG_WS}, { + atom_op_div32, ATOM_ARG_PS}, { + atom_op_div32, ATOM_ARG_WS}, +}; static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) { diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h index 09d0f8230708..fece8f45dc7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/atom.h +++ b/drivers/gpu/drm/amd/amdgpu/atom.h @@ -60,7 +60,7 @@ #define ATOM_CT_PS_MASK 0x7F #define ATOM_CT_CODE_PTR 6 -#define ATOM_OP_CNT 123 +#define ATOM_OP_CNT 127 #define ATOM_OP_EOT 91 #define ATOM_CASE_MAGIC 0x63 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index cd6edc40c9cd..1e0bba29e167 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -1279,8 +1279,7 @@ amdgpu_atombios_encoder_setup_dig(struct drm_encoder *encoder, int action) amdgpu_atombios_encoder_setup_dig_encoder(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); } if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) - amdgpu_atombios_encoder_setup_dig_transmitter(encoder, - ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); + amdgpu_atombios_encoder_set_backlight_level(amdgpu_encoder, dig->backlight_level); if (ext_encoder) amdgpu_atombios_encoder_setup_external_encoder(encoder, ext_encoder, ATOM_ENABLE); } else { diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c index 82e8d0730517..a1a35a5df8e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c @@ -6185,6 +6185,11 @@ static int ci_dpm_late_init(void *handle) if (!amdgpu_dpm) return 0; + /* init the sysfs and debugfs files late */ + ret = amdgpu_pm_sysfs_init(adev); + if (ret) + return ret; + ret = ci_set_temperature_range(adev); if (ret) return ret; @@ -6232,9 +6237,6 @@ static int ci_dpm_sw_init(void *handle) adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; if (amdgpu_dpm == 1) amdgpu_pm_print_power_states(adev); - ret = amdgpu_pm_sysfs_init(adev); - if (ret) - goto dpm_failed; mutex_unlock(&adev->pm.mutex); DRM_INFO("amdgpu: dpm initialized\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 4b6ce74753cd..484710cfdf82 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1567,6 +1567,9 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) int ret, i; u16 tmp16; + if (pci_is_root_bus(adev->pdev->bus)) + return; + if (amdgpu_pcie_gen2 == 0) return; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 9ea9de457da3..5f712ceddf08 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -96,7 +96,7 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev) { const char *chip_name; char fw_name[30]; - int err, i; + int err = 0, i; DRM_DEBUG("\n"); @@ -119,24 +119,24 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev) default: BUG(); } - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { if (i == 0) snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); else snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); - err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); + err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); if (err) goto out; - err = amdgpu_ucode_validate(adev->sdma[i].fw); + err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); } out: if (err) { printk(KERN_ERR "cik_sdma: Failed to load firmware \"%s\"\n", fw_name); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - release_firmware(adev->sdma[i].fw); - adev->sdma[i].fw = NULL; + for (i = 0; i < adev->sdma.num_instances; i++) { + release_firmware(adev->sdma.instance[i].fw); + adev->sdma.instance[i].fw = NULL; } } return err; @@ -168,7 +168,7 @@ static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1; + u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; } @@ -183,14 +183,14 @@ static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1; + u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); } static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) { - struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring); + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); int i; for (i = 0; i < count; i++) @@ -248,7 +248,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ u32 ref_and_mask; - if (ring == &ring->adev->sdma[0].ring) + if (ring == &ring->adev->sdma.instance[0].ring) ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; else ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; @@ -327,8 +327,8 @@ static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring, */ static void cik_sdma_gfx_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; - struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; + struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; + struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; u32 rb_cntl; int i; @@ -336,7 +336,7 @@ static void cik_sdma_gfx_stop(struct amdgpu_device *adev) (adev->mman.buffer_funcs_ring == sdma1)) amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); @@ -376,7 +376,7 @@ static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) cik_sdma_rlc_stop(adev); } - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); if (enable) me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; @@ -402,8 +402,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev) u32 wb_offset; int i, j, r; - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - ring = &adev->sdma[i].ring; + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; wb_offset = (ring->rptr_offs * 4); mutex_lock(&adev->srbm_mutex); @@ -502,26 +502,25 @@ static int cik_sdma_load_microcode(struct amdgpu_device *adev) u32 fw_size; int i, j; - if (!adev->sdma[0].fw || !adev->sdma[1].fw) - return -EINVAL; - /* halt the MEs */ cik_sdma_enable(adev, false); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; + for (i = 0; i < adev->sdma.num_instances; i++) { + if (!adev->sdma.instance[i].fw) + return -EINVAL; + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; amdgpu_ucode_print_sdma_hdr(&hdr->header); fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; - adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); - adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); - if (adev->sdma[i].feature_version >= 20) - adev->sdma[i].burst_nop = true; + adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); + adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); + if (adev->sdma.instance[i].feature_version >= 20) + adev->sdma.instance[i].burst_nop = true; fw_data = (const __le32 *) - (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); for (j = 0; j < fw_size; j++) WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); - WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); } return 0; @@ -830,7 +829,7 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, */ static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib) { - struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring); + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring); u32 pad_count; int i; @@ -934,6 +933,8 @@ static int cik_sdma_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->sdma.num_instances = SDMA_MAX_INSTANCE; + cik_sdma_set_ring_funcs(adev); cik_sdma_set_irq_funcs(adev); cik_sdma_set_buffer_funcs(adev); @@ -946,7 +947,7 @@ static int cik_sdma_sw_init(void *handle) { struct amdgpu_ring *ring; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - int r; + int r, i; r = cik_sdma_init_microcode(adev); if (r) { @@ -955,43 +956,33 @@ static int cik_sdma_sw_init(void *handle) } /* SDMA trap event */ - r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); + r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); + r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); + r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); if (r) return r; - ring = &adev->sdma[0].ring; - ring->ring_obj = NULL; - - ring = &adev->sdma[1].ring; - ring->ring_obj = NULL; - - ring = &adev->sdma[0].ring; - sprintf(ring->name, "sdma0"); - r = amdgpu_ring_init(adev, ring, 256 * 1024, - SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, - &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, - AMDGPU_RING_TYPE_SDMA); - if (r) - return r; - - ring = &adev->sdma[1].ring; - sprintf(ring->name, "sdma1"); - r = amdgpu_ring_init(adev, ring, 256 * 1024, - SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, - &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); - if (r) - return r; + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; + ring->ring_obj = NULL; + sprintf(ring->name, "sdma%d", i); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, + &adev->sdma.trap_irq, + (i == 0) ? + AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + } return r; } @@ -999,9 +990,10 @@ static int cik_sdma_sw_init(void *handle) static int cik_sdma_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; - amdgpu_ring_fini(&adev->sdma[0].ring); - amdgpu_ring_fini(&adev->sdma[1].ring); + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ring_fini(&adev->sdma.instance[i].ring); return 0; } @@ -1078,7 +1070,7 @@ static void cik_sdma_print_status(void *handle) dev_info(adev->dev, "CIK SDMA registers\n"); dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", RREG32(mmSRBM_STATUS2)); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n", @@ -1223,7 +1215,7 @@ static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, case 0: switch (queue_id) { case 0: - amdgpu_fence_process(&adev->sdma[0].ring); + amdgpu_fence_process(&adev->sdma.instance[0].ring); break; case 1: /* XXX compute */ @@ -1236,7 +1228,7 @@ static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, case 1: switch (queue_id) { case 0: - amdgpu_fence_process(&adev->sdma[1].ring); + amdgpu_fence_process(&adev->sdma.instance[1].ring); break; case 1: /* XXX compute */ @@ -1298,24 +1290,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { .set_powergating_state = cik_sdma_set_powergating_state, }; -/** - * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up - * - * @ring: amdgpu_ring structure holding ring information - * - * Check if the async DMA engine is locked up (CIK). - * Returns true if the engine appears to be locked up, false if not. - */ -static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring) -{ - - if (cik_sdma_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, @@ -1328,14 +1302,15 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, .test_ring = cik_sdma_ring_test_ring, .test_ib = cik_sdma_ring_test_ib, - .is_lockup = cik_sdma_ring_is_lockup, .insert_nop = cik_sdma_ring_insert_nop, }; static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) { - adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs; - adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) + adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; } static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { @@ -1349,9 +1324,9 @@ static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) { - adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; - adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs; - adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; + adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; + adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; } /** @@ -1416,7 +1391,7 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) { if (adev->mman.buffer_funcs == NULL) { adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } } @@ -1431,7 +1406,7 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) { if (adev->vm_manager.vm_pte_funcs == NULL) { adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; - adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; + adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring; adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true; } } diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c index 44fa96ad4709..8035d4d6a4f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c @@ -596,6 +596,12 @@ static int cz_dpm_late_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_dpm) { + int ret; + /* init the sysfs and debugfs files late */ + ret = amdgpu_pm_sysfs_init(adev); + if (ret) + return ret; + /* powerdown unused blocks for now */ cz_dpm_powergate_uvd(adev, true); cz_dpm_powergate_vce(adev, true); @@ -632,10 +638,6 @@ static int cz_dpm_sw_init(void *handle) if (amdgpu_dpm == 1) amdgpu_pm_print_power_states(adev); - ret = amdgpu_pm_sysfs_init(adev); - if (ret) - goto dpm_init_failed; - mutex_unlock(&adev->pm.mutex); DRM_INFO("amdgpu: dpm initialized\n"); @@ -1262,6 +1264,7 @@ static void cz_apply_state_adjust_rules(struct amdgpu_device *adev, static int cz_dpm_enable(struct amdgpu_device *adev) { + const char *chip_name; int ret = 0; /* renable will hang up SMU, so check first */ @@ -1270,21 +1273,33 @@ static int cz_dpm_enable(struct amdgpu_device *adev) cz_program_voting_clients(adev); + switch (adev->asic_type) { + case CHIP_CARRIZO: + chip_name = "carrizo"; + break; + case CHIP_STONEY: + chip_name = "stoney"; + break; + default: + BUG(); + } + + ret = cz_start_dpm(adev); if (ret) { - DRM_ERROR("Carrizo DPM enable failed\n"); + DRM_ERROR("%s DPM enable failed\n", chip_name); return -EINVAL; } ret = cz_program_bootup_state(adev); if (ret) { - DRM_ERROR("Carrizo bootup state program failed\n"); + DRM_ERROR("%s bootup state program failed\n", chip_name); return -EINVAL; } ret = cz_enable_didt(adev, true); if (ret) { - DRM_ERROR("Carrizo enable di/dt failed\n"); + DRM_ERROR("%s enable di/dt failed\n", chip_name); return -EINVAL; } @@ -1351,7 +1366,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev) ret = cz_enable_didt(adev, false); if (ret) { - DRM_ERROR("Carrizo disable di/dt failed\n"); + DRM_ERROR("disable di/dt failed\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smc.c b/drivers/gpu/drm/amd/amdgpu/cz_smc.c index e33180d3314a..ac7fee7b7eca 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_smc.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_smc.c @@ -312,13 +312,16 @@ int cz_smu_start(struct amdgpu_device *adev) UCODE_ID_CP_MEC_JT1_MASK | UCODE_ID_CP_MEC_JT2_MASK; + if (adev->asic_type == CHIP_STONEY) + fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK); + cz_smu_request_load_fw(adev); ret = cz_smu_check_fw_load_finish(adev, fw_to_check); if (ret) return ret; /* manually load MEC firmware for CZ */ - if (adev->asic_type == CHIP_CARRIZO) { + if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { ret = cz_load_mec_firmware(adev); if (ret) { dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret); @@ -336,6 +339,9 @@ int cz_smu_start(struct amdgpu_device *adev) AMDGPU_CPMEC2_UCODE_LOADED | AMDGPU_CPRLC_UCODE_LOADED; + if (adev->asic_type == CHIP_STONEY) + adev->smu.fw_flags &= ~(AMDGPU_SDMA1_UCODE_LOADED | AMDGPU_CPMEC2_UCODE_LOADED); + return ret; } @@ -601,8 +607,13 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); - cz_smu_populate_single_ucode_load_task(adev, + if (adev->asic_type == CHIP_STONEY) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); + } else { + cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); + } cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false); } @@ -642,8 +653,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev) if (adev->firmware.smu_load) { cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); - cz_smu_populate_single_ucode_load_task(adev, + if (adev->asic_type == CHIP_STONEY) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false); + } else { + cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false); + } cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false); cz_smu_populate_single_ucode_load_task(adev, @@ -652,8 +668,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false); cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); - cz_smu_populate_single_ucode_load_task(adev, + if (adev->asic_type == CHIP_STONEY) { + cz_smu_populate_single_ucode_load_task(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false); + } else { + cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false); + } cz_smu_populate_single_ucode_load_task(adev, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true); } @@ -888,10 +909,18 @@ int cz_smu_init(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, &priv->driver_buffer[priv->driver_buffer_length++])) goto smu_init_failed; - if (cz_smu_populate_single_firmware_entry(adev, - CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, - &priv->driver_buffer[priv->driver_buffer_length++])) - goto smu_init_failed; + + if (adev->asic_type == CHIP_STONEY) { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } else { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } if (cz_smu_populate_single_firmware_entry(adev, CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, &priv->driver_buffer[priv->driver_buffer_length++])) @@ -908,10 +937,17 @@ int cz_smu_init(struct amdgpu_device *adev) CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, &priv->driver_buffer[priv->driver_buffer_length++])) goto smu_init_failed; - if (cz_smu_populate_single_firmware_entry(adev, - CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, - &priv->driver_buffer[priv->driver_buffer_length++])) - goto smu_init_failed; + if (adev->asic_type == CHIP_STONEY) { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } else { + if (cz_smu_populate_single_firmware_entry(adev, + CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, + &priv->driver_buffer[priv->driver_buffer_length++])) + goto smu_init_failed; + } if (cz_smu_populate_single_firmware_entry(adev, CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, &priv->driver_buffer[priv->driver_buffer_length++])) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index e4d101b1252a..61320511c479 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -262,46 +262,22 @@ static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) * @crtc_id: crtc to cleanup pageflip on * @crtc_base: new address of the crtc (GPU MC address) * - * Does the actual pageflip (evergreen+). - * During vblank we take the crtc lock and wait for the update_pending - * bit to go high, when it does, we release the lock, and allow the - * double buffered update to take place. - * Returns the current update pending status. + * Triggers the actual pageflip by updating the primary + * surface base address. */ static void dce_v10_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base) { struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); - int i; - - /* Lock the graphics update lock */ - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); - WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); - - /* update the scanout addresses */ - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(crtc_base)); - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - lower_32_bits(crtc_base)); + /* update the primary scanout address */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); + /* writing to the low address triggers the update */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, lower_32_bits(crtc_base)); - - /* Wait for update_pending to go high. */ - for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & - GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) - break; - udelay(1); - } - DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); - - /* Unlock the lock, so double-buffering can take place inside vblank */ - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); - WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); + /* post the write */ + RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); } static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, @@ -2499,26 +2475,19 @@ static void dce_v10_0_show_cursor(struct drm_crtc *crtc) struct amdgpu_device *adev = crtc->dev->dev_private; u32 tmp; + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(amdgpu_crtc->cursor_addr)); + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(amdgpu_crtc->cursor_addr)); + tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); } -static void dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, - uint64_t gpu_addr) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_device *adev = crtc->dev->dev_private; - - WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(gpu_addr)); - WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - lower_32_bits(gpu_addr)); -} - -static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, - int x, int y) +static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, + int x, int y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; @@ -2538,26 +2507,40 @@ static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, y = 0; } - dce_v10_0_lock_cursor(crtc, true); WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); - dce_v10_0_lock_cursor(crtc, false); + + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; return 0; } -static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc, - struct drm_file *file_priv, - uint32_t handle, - uint32_t width, - uint32_t height) +static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + int ret; + + dce_v10_0_lock_cursor(crtc, true); + ret = dce_v10_0_cursor_move_locked(crtc, x, y); + dce_v10_0_lock_cursor(crtc, false); + + return ret; +} + +static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height, + int32_t hot_x, + int32_t hot_y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_gem_object *obj; - struct amdgpu_bo *robj; - uint64_t gpu_addr; + struct amdgpu_bo *aobj; int ret; if (!handle) { @@ -2579,41 +2562,71 @@ static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc, return -ENOENT; } - robj = gem_to_amdgpu_bo(obj); - ret = amdgpu_bo_reserve(robj, false); - if (unlikely(ret != 0)) - goto fail; - ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, - 0, 0, &gpu_addr); - amdgpu_bo_unreserve(robj); - if (ret) - goto fail; + aobj = gem_to_amdgpu_bo(obj); + ret = amdgpu_bo_reserve(aobj, false); + if (ret != 0) { + drm_gem_object_unreference_unlocked(obj); + return ret; + } + + ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); + amdgpu_bo_unreserve(aobj); + if (ret) { + DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); + drm_gem_object_unreference_unlocked(obj); + return ret; + } amdgpu_crtc->cursor_width = width; amdgpu_crtc->cursor_height = height; dce_v10_0_lock_cursor(crtc, true); - dce_v10_0_set_cursor(crtc, obj, gpu_addr); + + if (hot_x != amdgpu_crtc->cursor_hot_x || + hot_y != amdgpu_crtc->cursor_hot_y) { + int x, y; + + x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; + y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; + + dce_v10_0_cursor_move_locked(crtc, x, y); + + amdgpu_crtc->cursor_hot_x = hot_x; + amdgpu_crtc->cursor_hot_y = hot_y; + } + dce_v10_0_show_cursor(crtc); dce_v10_0_lock_cursor(crtc, false); unpin: if (amdgpu_crtc->cursor_bo) { - robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); - ret = amdgpu_bo_reserve(robj, false); + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + ret = amdgpu_bo_reserve(aobj, false); if (likely(ret == 0)) { - amdgpu_bo_unpin(robj); - amdgpu_bo_unreserve(robj); + amdgpu_bo_unpin(aobj); + amdgpu_bo_unreserve(aobj); } drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); } amdgpu_crtc->cursor_bo = obj; return 0; -fail: - drm_gem_object_unreference_unlocked(obj); +} - return ret; +static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (amdgpu_crtc->cursor_bo) { + dce_v10_0_lock_cursor(crtc, true); + + dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, + amdgpu_crtc->cursor_y); + + dce_v10_0_show_cursor(crtc); + + dce_v10_0_lock_cursor(crtc, false); + } } static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, @@ -2641,7 +2654,7 @@ static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) } static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { - .cursor_set = dce_v10_0_crtc_cursor_set, + .cursor_set2 = dce_v10_0_crtc_cursor_set2, .cursor_move = dce_v10_0_crtc_cursor_move, .gamma_set = dce_v10_0_crtc_gamma_set, .set_config = amdgpu_crtc_set_config, @@ -2774,6 +2787,7 @@ static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); + dce_v10_0_cursor_reset(crtc); /* update the hw version fpr dpm */ amdgpu_crtc->hw_mode = *adjusted_mode; @@ -3048,22 +3062,18 @@ static int dce_v10_0_suspend(void *handle) amdgpu_atombios_scratch_regs_save(adev); - dce_v10_0_hpd_fini(adev); - - return 0; + return dce_v10_0_hw_fini(handle); } static int dce_v10_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; - dce_v10_0_init_golden_registers(adev); + ret = dce_v10_0_hw_init(handle); amdgpu_atombios_scratch_regs_restore(adev); - /* init dig PHYs, disp eng pll */ - amdgpu_atombios_encoder_init_dig(adev); - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); /* turn on the BL */ if (adev->mode_info.bl_encoder) { u8 bl_level = amdgpu_display_backlight_get_level(adev, @@ -3072,10 +3082,7 @@ static int dce_v10_0_resume(void *handle) bl_level); } - /* initialize hpd */ - dce_v10_0_hpd_init(adev); - - return 0; + return ret; } static bool dce_v10_0_is_idle(void *handle) @@ -3267,37 +3274,20 @@ static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { - u32 reg, reg_block; - /* now deal with page flip IRQ */ - switch (type) { - case AMDGPU_PAGEFLIP_IRQ_D1: - reg_block = CRTC0_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D2: - reg_block = CRTC1_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D3: - reg_block = CRTC2_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D4: - reg_block = CRTC3_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D5: - reg_block = CRTC4_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D6: - reg_block = CRTC5_REGISTER_OFFSET; - break; - default: - DRM_ERROR("invalid pageflip crtc %d\n", type); - return -EINVAL; + u32 reg; + + if (type >= adev->mode_info.num_crtc) { + DRM_ERROR("invalid pageflip crtc %d\n", type); + return -EINVAL; } - reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); if (state == AMDGPU_IRQ_STATE_DISABLE) - WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], + reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); else - WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], + reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); return 0; } @@ -3306,7 +3296,6 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - int reg_block; unsigned long flags; unsigned crtc_id; struct amdgpu_crtc *amdgpu_crtc; @@ -3315,33 +3304,15 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, crtc_id = (entry->src_id - 8) >> 1; amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - /* ack the interrupt */ - switch(crtc_id){ - case AMDGPU_PAGEFLIP_IRQ_D1: - reg_block = CRTC0_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D2: - reg_block = CRTC1_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D3: - reg_block = CRTC2_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D4: - reg_block = CRTC3_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D5: - reg_block = CRTC4_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D6: - reg_block = CRTC5_REGISTER_OFFSET; - break; - default: - DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); - return -EINVAL; + if (crtc_id >= adev->mode_info.num_crtc) { + DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); + return -EINVAL; } - if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) - WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & + GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) + WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], + GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); /* IRQ could occur when in initial stage */ if (amdgpu_crtc == NULL) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 6411e8244671..3506c5b42106 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -126,6 +126,13 @@ static const u32 cz_mgcg_cgcg_init[] = mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, }; +static const u32 stoney_golden_settings_a11[] = +{ + mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, + mmFBC_MISC, 0x1f311fff, 0x14302000, +}; + + static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { @@ -137,6 +144,11 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_golden_settings_a11, + (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + break; default: break; } @@ -240,46 +252,22 @@ static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) * @crtc_id: crtc to cleanup pageflip on * @crtc_base: new address of the crtc (GPU MC address) * - * Does the actual pageflip (evergreen+). - * During vblank we take the crtc lock and wait for the update_pending - * bit to go high, when it does, we release the lock, and allow the - * double buffered update to take place. - * Returns the current update pending status. + * Triggers the actual pageflip by updating the primary + * surface base address. */ static void dce_v11_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base) { struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); - int i; - - /* Lock the graphics update lock */ - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); - WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); /* update the scanout addresses */ - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(crtc_base)); - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - lower_32_bits(crtc_base)); - WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); + /* writing to the low address triggers the update */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, lower_32_bits(crtc_base)); - - /* Wait for update_pending to go high. */ - for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & - GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) - break; - udelay(1); - } - DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); - - /* Unlock the lock, so double-buffering can take place inside vblank */ - tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); - WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); + /* post the write */ + RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); } static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, @@ -2425,7 +2413,7 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) /* XXX need to determine what plls are available on each DCE11 part */ pll_in_use = amdgpu_pll_get_use_mask(crtc); - if (adev->asic_type == CHIP_CARRIZO) { + if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { if (!(pll_in_use & (1 << ATOM_PPLL1))) return ATOM_PPLL1; if (!(pll_in_use & (1 << ATOM_PPLL0))) @@ -2476,26 +2464,19 @@ static void dce_v11_0_show_cursor(struct drm_crtc *crtc) struct amdgpu_device *adev = crtc->dev->dev_private; u32 tmp; + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(amdgpu_crtc->cursor_addr)); + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(amdgpu_crtc->cursor_addr)); + tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); } -static void dce_v11_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, - uint64_t gpu_addr) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_device *adev = crtc->dev->dev_private; - - WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(gpu_addr)); - WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - lower_32_bits(gpu_addr)); -} - -static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, - int x, int y) +static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, + int x, int y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; @@ -2515,26 +2496,40 @@ static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, y = 0; } - dce_v11_0_lock_cursor(crtc, true); WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); - dce_v11_0_lock_cursor(crtc, false); + + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; return 0; } -static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc, - struct drm_file *file_priv, - uint32_t handle, - uint32_t width, - uint32_t height) +static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + int ret; + + dce_v11_0_lock_cursor(crtc, true); + ret = dce_v11_0_cursor_move_locked(crtc, x, y); + dce_v11_0_lock_cursor(crtc, false); + + return ret; +} + +static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height, + int32_t hot_x, + int32_t hot_y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_gem_object *obj; - struct amdgpu_bo *robj; - uint64_t gpu_addr; + struct amdgpu_bo *aobj; int ret; if (!handle) { @@ -2556,41 +2551,71 @@ static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc, return -ENOENT; } - robj = gem_to_amdgpu_bo(obj); - ret = amdgpu_bo_reserve(robj, false); - if (unlikely(ret != 0)) - goto fail; - ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, - 0, 0, &gpu_addr); - amdgpu_bo_unreserve(robj); - if (ret) - goto fail; + aobj = gem_to_amdgpu_bo(obj); + ret = amdgpu_bo_reserve(aobj, false); + if (ret != 0) { + drm_gem_object_unreference_unlocked(obj); + return ret; + } + + ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); + amdgpu_bo_unreserve(aobj); + if (ret) { + DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); + drm_gem_object_unreference_unlocked(obj); + return ret; + } amdgpu_crtc->cursor_width = width; amdgpu_crtc->cursor_height = height; dce_v11_0_lock_cursor(crtc, true); - dce_v11_0_set_cursor(crtc, obj, gpu_addr); + + if (hot_x != amdgpu_crtc->cursor_hot_x || + hot_y != amdgpu_crtc->cursor_hot_y) { + int x, y; + + x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; + y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; + + dce_v11_0_cursor_move_locked(crtc, x, y); + + amdgpu_crtc->cursor_hot_x = hot_x; + amdgpu_crtc->cursor_hot_y = hot_y; + } + dce_v11_0_show_cursor(crtc); dce_v11_0_lock_cursor(crtc, false); unpin: if (amdgpu_crtc->cursor_bo) { - robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); - ret = amdgpu_bo_reserve(robj, false); + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + ret = amdgpu_bo_reserve(aobj, false); if (likely(ret == 0)) { - amdgpu_bo_unpin(robj); - amdgpu_bo_unreserve(robj); + amdgpu_bo_unpin(aobj); + amdgpu_bo_unreserve(aobj); } drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); } amdgpu_crtc->cursor_bo = obj; return 0; -fail: - drm_gem_object_unreference_unlocked(obj); +} - return ret; +static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (amdgpu_crtc->cursor_bo) { + dce_v11_0_lock_cursor(crtc, true); + + dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, + amdgpu_crtc->cursor_y); + + dce_v11_0_show_cursor(crtc); + + dce_v11_0_lock_cursor(crtc, false); + } } static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, @@ -2618,7 +2643,7 @@ static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) } static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { - .cursor_set = dce_v11_0_crtc_cursor_set, + .cursor_set2 = dce_v11_0_crtc_cursor_set2, .cursor_move = dce_v11_0_crtc_cursor_move, .gamma_set = dce_v11_0_crtc_gamma_set, .set_config = amdgpu_crtc_set_config, @@ -2751,6 +2776,7 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); + dce_v11_0_cursor_reset(crtc); /* update the hw version fpr dpm */ amdgpu_crtc->hw_mode = *adjusted_mode; @@ -2888,7 +2914,12 @@ static int dce_v11_0_early_init(void *handle) switch (adev->asic_type) { case CHIP_CARRIZO: - adev->mode_info.num_crtc = 4; + adev->mode_info.num_crtc = 3; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; + break; + case CHIP_STONEY: + adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; break; @@ -2990,6 +3021,7 @@ static int dce_v11_0_hw_init(void *handle) dce_v11_0_init_golden_registers(adev); /* init dig PHYs, disp eng pll */ + amdgpu_atombios_crtc_powergate_init(adev); amdgpu_atombios_encoder_init_dig(adev); amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); @@ -3023,23 +3055,18 @@ static int dce_v11_0_suspend(void *handle) amdgpu_atombios_scratch_regs_save(adev); - dce_v11_0_hpd_fini(adev); - - return 0; + return dce_v11_0_hw_fini(handle); } static int dce_v11_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; - dce_v11_0_init_golden_registers(adev); + ret = dce_v11_0_hw_init(handle); amdgpu_atombios_scratch_regs_restore(adev); - /* init dig PHYs, disp eng pll */ - amdgpu_atombios_crtc_powergate_init(adev); - amdgpu_atombios_encoder_init_dig(adev); - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); /* turn on the BL */ if (adev->mode_info.bl_encoder) { u8 bl_level = amdgpu_display_backlight_get_level(adev, @@ -3048,10 +3075,7 @@ static int dce_v11_0_resume(void *handle) bl_level); } - /* initialize hpd */ - dce_v11_0_hpd_init(adev); - - return 0; + return ret; } static bool dce_v11_0_is_idle(void *handle) @@ -3243,37 +3267,20 @@ static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { - u32 reg, reg_block; - /* now deal with page flip IRQ */ - switch (type) { - case AMDGPU_PAGEFLIP_IRQ_D1: - reg_block = CRTC0_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D2: - reg_block = CRTC1_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D3: - reg_block = CRTC2_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D4: - reg_block = CRTC3_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D5: - reg_block = CRTC4_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D6: - reg_block = CRTC5_REGISTER_OFFSET; - break; - default: - DRM_ERROR("invalid pageflip crtc %d\n", type); - return -EINVAL; + u32 reg; + + if (type >= adev->mode_info.num_crtc) { + DRM_ERROR("invalid pageflip crtc %d\n", type); + return -EINVAL; } - reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); if (state == AMDGPU_IRQ_STATE_DISABLE) - WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], + reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); else - WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], + reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); return 0; } @@ -3282,7 +3289,6 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - int reg_block; unsigned long flags; unsigned crtc_id; struct amdgpu_crtc *amdgpu_crtc; @@ -3291,33 +3297,15 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, crtc_id = (entry->src_id - 8) >> 1; amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - /* ack the interrupt */ - switch(crtc_id){ - case AMDGPU_PAGEFLIP_IRQ_D1: - reg_block = CRTC0_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D2: - reg_block = CRTC1_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D3: - reg_block = CRTC2_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D4: - reg_block = CRTC3_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D5: - reg_block = CRTC4_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D6: - reg_block = CRTC5_REGISTER_OFFSET; - break; - default: - DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); - return -EINVAL; + if (crtc_id >= adev->mode_info.num_crtc) { + DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); + return -EINVAL; } - if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) - WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & + GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) + WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], + GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); /* IRQ could occur when in initial stage */ if(amdgpu_crtc == NULL) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index c86911c2ea2a..b17abbe1be99 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -211,46 +211,22 @@ static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) * @crtc_id: crtc to cleanup pageflip on * @crtc_base: new address of the crtc (GPU MC address) * - * Does the actual pageflip (evergreen+). - * During vblank we take the crtc lock and wait for the update_pending - * bit to go high, when it does, we release the lock, and allow the - * double buffered update to take place. - * Returns the current update pending status. + * Triggers the actual pageflip by updating the primary + * surface base address. */ static void dce_v8_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base) { struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); - int i; - - /* Lock the graphics update lock */ - tmp |= GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; - WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); - - /* update the scanout addresses */ - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(crtc_base)); - WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32)crtc_base); + /* update the primary scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); + /* writing to the low address triggers the update */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - (u32)crtc_base); - - /* Wait for update_pending to go high. */ - for (i = 0; i < adev->usec_timeout; i++) { - if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & - GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) - break; - udelay(1); - } - DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); - - /* Unlock the lock, so double-buffering can take place inside vblank */ - tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; - WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); + lower_32_bits(crtc_base)); + /* post the write */ + RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); } static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, @@ -2411,26 +2387,19 @@ static void dce_v8_0_show_cursor(struct drm_crtc *crtc) struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; + WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, + upper_32_bits(amdgpu_crtc->cursor_addr)); + WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, + lower_32_bits(amdgpu_crtc->cursor_addr)); + WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, CUR_CONTROL__CURSOR_EN_MASK | (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); } -static void dce_v8_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, - uint64_t gpu_addr) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_device *adev = crtc->dev->dev_private; - - WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, - upper_32_bits(gpu_addr)); - WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, - gpu_addr & 0xffffffff); -} - -static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, - int x, int y) +static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, + int x, int y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct amdgpu_device *adev = crtc->dev->dev_private; @@ -2450,26 +2419,40 @@ static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, y = 0; } - dce_v8_0_lock_cursor(crtc, true); WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); - dce_v8_0_lock_cursor(crtc, false); + + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; return 0; } -static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc, - struct drm_file *file_priv, - uint32_t handle, - uint32_t width, - uint32_t height) +static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + int ret; + + dce_v8_0_lock_cursor(crtc, true); + ret = dce_v8_0_cursor_move_locked(crtc, x, y); + dce_v8_0_lock_cursor(crtc, false); + + return ret; +} + +static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, + struct drm_file *file_priv, + uint32_t handle, + uint32_t width, + uint32_t height, + int32_t hot_x, + int32_t hot_y) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); struct drm_gem_object *obj; - struct amdgpu_bo *robj; - uint64_t gpu_addr; + struct amdgpu_bo *aobj; int ret; if (!handle) { @@ -2491,41 +2474,71 @@ static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc, return -ENOENT; } - robj = gem_to_amdgpu_bo(obj); - ret = amdgpu_bo_reserve(robj, false); - if (unlikely(ret != 0)) - goto fail; - ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, - 0, 0, &gpu_addr); - amdgpu_bo_unreserve(robj); - if (ret) - goto fail; + aobj = gem_to_amdgpu_bo(obj); + ret = amdgpu_bo_reserve(aobj, false); + if (ret != 0) { + drm_gem_object_unreference_unlocked(obj); + return ret; + } + + ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); + amdgpu_bo_unreserve(aobj); + if (ret) { + DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); + drm_gem_object_unreference_unlocked(obj); + return ret; + } amdgpu_crtc->cursor_width = width; amdgpu_crtc->cursor_height = height; dce_v8_0_lock_cursor(crtc, true); - dce_v8_0_set_cursor(crtc, obj, gpu_addr); + + if (hot_x != amdgpu_crtc->cursor_hot_x || + hot_y != amdgpu_crtc->cursor_hot_y) { + int x, y; + + x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; + y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; + + dce_v8_0_cursor_move_locked(crtc, x, y); + + amdgpu_crtc->cursor_hot_x = hot_x; + amdgpu_crtc->cursor_hot_y = hot_y; + } + dce_v8_0_show_cursor(crtc); dce_v8_0_lock_cursor(crtc, false); unpin: if (amdgpu_crtc->cursor_bo) { - robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); - ret = amdgpu_bo_reserve(robj, false); + struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); + ret = amdgpu_bo_reserve(aobj, false); if (likely(ret == 0)) { - amdgpu_bo_unpin(robj); - amdgpu_bo_unreserve(robj); + amdgpu_bo_unpin(aobj); + amdgpu_bo_unreserve(aobj); } drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); } amdgpu_crtc->cursor_bo = obj; return 0; -fail: - drm_gem_object_unreference_unlocked(obj); +} - return ret; +static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (amdgpu_crtc->cursor_bo) { + dce_v8_0_lock_cursor(crtc, true); + + dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, + amdgpu_crtc->cursor_y); + + dce_v8_0_show_cursor(crtc); + + dce_v8_0_lock_cursor(crtc, false); + } } static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, @@ -2553,7 +2566,7 @@ static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) } static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { - .cursor_set = dce_v8_0_crtc_cursor_set, + .cursor_set2 = dce_v8_0_crtc_cursor_set2, .cursor_move = dce_v8_0_crtc_cursor_move, .gamma_set = dce_v8_0_crtc_gamma_set, .set_config = amdgpu_crtc_set_config, @@ -2693,6 +2706,7 @@ static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); amdgpu_atombios_crtc_scaler_setup(crtc); + dce_v8_0_cursor_reset(crtc); /* update the hw version fpr dpm */ amdgpu_crtc->hw_mode = *adjusted_mode; @@ -2956,20 +2970,18 @@ static int dce_v8_0_suspend(void *handle) amdgpu_atombios_scratch_regs_save(adev); - dce_v8_0_hpd_fini(adev); - - return 0; + return dce_v8_0_hw_fini(handle); } static int dce_v8_0_resume(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; + + ret = dce_v8_0_hw_init(handle); amdgpu_atombios_scratch_regs_restore(adev); - /* init dig PHYs, disp eng pll */ - amdgpu_atombios_encoder_init_dig(adev); - amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); /* turn on the BL */ if (adev->mode_info.bl_encoder) { u8 bl_level = amdgpu_display_backlight_get_level(adev, @@ -2978,10 +2990,7 @@ static int dce_v8_0_resume(void *handle) bl_level); } - /* initialize hpd */ - dce_v8_0_hpd_init(adev); - - return 0; + return ret; } static bool dce_v8_0_is_idle(void *handle) @@ -3274,37 +3283,20 @@ static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, unsigned type, enum amdgpu_interrupt_state state) { - u32 reg, reg_block; - /* now deal with page flip IRQ */ - switch (type) { - case AMDGPU_PAGEFLIP_IRQ_D1: - reg_block = CRTC0_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D2: - reg_block = CRTC1_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D3: - reg_block = CRTC2_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D4: - reg_block = CRTC3_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D5: - reg_block = CRTC4_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D6: - reg_block = CRTC5_REGISTER_OFFSET; - break; - default: - DRM_ERROR("invalid pageflip crtc %d\n", type); - return -EINVAL; + u32 reg; + + if (type >= adev->mode_info.num_crtc) { + DRM_ERROR("invalid pageflip crtc %d\n", type); + return -EINVAL; } - reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); + reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); if (state == AMDGPU_IRQ_STATE_DISABLE) - WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], + reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); else - WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); + WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], + reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); return 0; } @@ -3313,7 +3305,6 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, struct amdgpu_irq_src *source, struct amdgpu_iv_entry *entry) { - int reg_block; unsigned long flags; unsigned crtc_id; struct amdgpu_crtc *amdgpu_crtc; @@ -3322,33 +3313,15 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, crtc_id = (entry->src_id - 8) >> 1; amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; - /* ack the interrupt */ - switch(crtc_id){ - case AMDGPU_PAGEFLIP_IRQ_D1: - reg_block = CRTC0_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D2: - reg_block = CRTC1_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D3: - reg_block = CRTC2_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D4: - reg_block = CRTC3_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D5: - reg_block = CRTC4_REGISTER_OFFSET; - break; - case AMDGPU_PAGEFLIP_IRQ_D6: - reg_block = CRTC5_REGISTER_OFFSET; - break; - default: - DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); - return -EINVAL; + if (crtc_id >= adev->mode_info.num_crtc) { + DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); + return -EINVAL; } - if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) - WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); + if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & + GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) + WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], + GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); /* IRQ could occur when in initial stage */ if (amdgpu_crtc == NULL) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index e992bf2ff66c..72793f93e2fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -5542,24 +5542,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { .set_powergating_state = gfx_v7_0_set_powergating_state, }; -/** - * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up - * - * @adev: amdgpu_device pointer - * @ring: amdgpu_ring structure holding ring information - * - * Check if the 3D engine is locked up (CIK). - * Returns true if the engine is locked, false if not. - */ -static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring) -{ - if (gfx_v7_0_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .get_rptr = gfx_v7_0_ring_get_rptr_gfx, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, @@ -5573,7 +5555,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, .test_ring = gfx_v7_0_ring_test_ring, .test_ib = gfx_v7_0_ring_test_ib, - .is_lockup = gfx_v7_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; @@ -5590,7 +5571,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, .test_ring = gfx_v7_0_ring_test_ring, .test_ib = gfx_v7_0_ring_test_ib, - .is_lockup = gfx_v7_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index cb4f68f53f24..6776cf756d40 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -73,6 +73,12 @@ MODULE_FIRMWARE("amdgpu/carrizo_mec.bin"); MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin"); MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin"); +MODULE_FIRMWARE("amdgpu/stoney_ce.bin"); +MODULE_FIRMWARE("amdgpu/stoney_pfp.bin"); +MODULE_FIRMWARE("amdgpu/stoney_me.bin"); +MODULE_FIRMWARE("amdgpu/stoney_mec.bin"); +MODULE_FIRMWARE("amdgpu/stoney_rlc.bin"); + MODULE_FIRMWARE("amdgpu/tonga_ce.bin"); MODULE_FIRMWARE("amdgpu/tonga_pfp.bin"); MODULE_FIRMWARE("amdgpu/tonga_me.bin"); @@ -229,11 +235,13 @@ static const u32 fiji_golden_common_all[] = mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a, mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e, - mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, + mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003, mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, - mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009, }; static const u32 golden_settings_fiji_a10[] = @@ -241,24 +249,26 @@ static const u32 golden_settings_fiji_a10[] = mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, mmDB_DEBUG2, 0xf00fffff, 0x00000400, mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, - mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, + mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd, mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, - mmTCC_CTRL, 0x00100000, 0xf30fff7f, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff, - mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4, - mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0, + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, }; static const u32 fiji_mgcg_cgcg_init[] = { - mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0, + mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100, mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100, + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100, mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, @@ -286,6 +296,10 @@ static const u32 fiji_mgcg_cgcg_init[] = mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200, mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c, + mmPCIE_INDEX, 0xffffffff, 0x0140001c, + mmPCIE_DATA, 0x000f0000, 0x00000000, + mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, + mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, }; @@ -493,6 +507,42 @@ static const u32 cz_mgcg_cgcg_init[] = mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, }; +static const u32 stoney_golden_settings_a11[] = +{ + mmDB_DEBUG2, 0xf00fffff, 0x00000400, + mmGB_GPU_ID, 0x0000000f, 0x00000000, + mmPA_SC_ENHANCE, 0xffffffff, 0x20000001, + mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, + mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c, + mmTA_CNTL_AUX, 0x000f000f, 0x000b0000, + mmTCC_CTRL, 0x00100000, 0xf31fff7f, + mmTCC_EXE_DISABLE, 0x00000002, 0x00000002, + mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1, + mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010, +}; + +static const u32 stoney_golden_common_all[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000, + mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000, + mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001, + mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800, + mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF, + mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, +}; + +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, + mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, + mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201, + mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201, + mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, + mmATC_MISC_CG, 0xffffffff, 0x000c0200, +}; + static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev); static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev); static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev); @@ -545,6 +595,17 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) cz_golden_common_all, (const u32)ARRAY_SIZE(cz_golden_common_all)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + stoney_golden_settings_a11, + (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + amdgpu_program_register_sequence(adev, + stoney_golden_common_all, + (const u32)ARRAY_SIZE(stoney_golden_common_all)); + break; default: break; } @@ -691,6 +752,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; + case CHIP_STONEY: + chip_name = "stoney"; + break; default: BUG(); } @@ -748,21 +812,23 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); - snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); - err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); - if (!err) { - err = amdgpu_ucode_validate(adev->gfx.mec2_fw); - if (err) - goto out; - cp_hdr = (const struct gfx_firmware_header_v1_0 *) - adev->gfx.mec2_fw->data; - adev->gfx.mec2_fw_version = le32_to_cpu( - cp_hdr->header.ucode_version); - adev->gfx.mec2_feature_version = le32_to_cpu( - cp_hdr->ucode_feature_version); - } else { - err = 0; - adev->gfx.mec2_fw = NULL; + if (adev->asic_type != CHIP_STONEY) { + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); + err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); + if (!err) { + err = amdgpu_ucode_validate(adev->gfx.mec2_fw); + if (err) + goto out; + cp_hdr = (const struct gfx_firmware_header_v1_0 *) + adev->gfx.mec2_fw->data; + adev->gfx.mec2_fw_version = + le32_to_cpu(cp_hdr->header.ucode_version); + adev->gfx.mec2_feature_version = + le32_to_cpu(cp_hdr->ucode_feature_version); + } else { + err = 0; + adev->gfx.mec2_fw = NULL; + } } if (adev->firmware.smu_load) { @@ -903,6 +969,232 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev) return 0; } +static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) +{ + u32 gb_addr_config; + u32 mc_shared_chmap, mc_arb_ramcfg; + u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; + u32 tmp; + + switch (adev->asic_type) { + case CHIP_TOPAZ: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 2; + adev->gfx.config.max_cu_per_sh = 6; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 2; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_FIJI: + adev->gfx.config.max_shader_engines = 4; + adev->gfx.config.max_tile_pipes = 16; + adev->gfx.config.max_cu_per_sh = 16; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 4; + adev->gfx.config.max_texture_channel_caches = 8; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_TONGA: + adev->gfx.config.max_shader_engines = 4; + adev->gfx.config.max_tile_pipes = 8; + adev->gfx.config.max_cu_per_sh = 8; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 8; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_CARRIZO: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 2; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + + switch (adev->pdev->revision) { + case 0xc4: + case 0x84: + case 0xc8: + case 0xcc: + case 0xe1: + case 0xe3: + /* B10 */ + adev->gfx.config.max_cu_per_sh = 8; + break; + case 0xc5: + case 0x81: + case 0x85: + case 0xc9: + case 0xcd: + case 0xe2: + case 0xe4: + /* B8 */ + adev->gfx.config.max_cu_per_sh = 6; + break; + case 0xc6: + case 0xca: + case 0xce: + case 0x88: + /* B6 */ + adev->gfx.config.max_cu_per_sh = 6; + break; + case 0xc7: + case 0x87: + case 0xcb: + case 0xe5: + case 0x89: + default: + /* B4 */ + adev->gfx.config.max_cu_per_sh = 4; + break; + } + + adev->gfx.config.max_texture_channel_caches = 2; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; + break; + case CHIP_STONEY: + adev->gfx.config.max_shader_engines = 1; + adev->gfx.config.max_tile_pipes = 2; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 1; + + switch (adev->pdev->revision) { + case 0xc0: + case 0xc1: + case 0xc2: + case 0xc4: + case 0xc8: + case 0xc9: + adev->gfx.config.max_cu_per_sh = 3; + break; + case 0xd0: + case 0xd1: + case 0xd2: + default: + adev->gfx.config.max_cu_per_sh = 2; + break; + } + + adev->gfx.config.max_texture_channel_caches = 2; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 16; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; + break; + default: + adev->gfx.config.max_shader_engines = 2; + adev->gfx.config.max_tile_pipes = 4; + adev->gfx.config.max_cu_per_sh = 2; + adev->gfx.config.max_sh_per_se = 1; + adev->gfx.config.max_backends_per_se = 2; + adev->gfx.config.max_texture_channel_caches = 4; + adev->gfx.config.max_gprs = 256; + adev->gfx.config.max_gs_threads = 32; + adev->gfx.config.max_hw_contexts = 8; + + adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; + adev->gfx.config.sc_prim_fifo_size_backend = 0x100; + adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; + gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; + break; + } + + mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); + adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); + mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; + + adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; + adev->gfx.config.mem_max_burst_length_bytes = 256; + if (adev->flags & AMD_IS_APU) { + /* Get memory bank mapping mode. */ + tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); + dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); + dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); + + tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); + dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); + dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); + + /* Validate settings in case only one DIMM installed. */ + if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) + dimm00_addr_map = 0; + if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) + dimm01_addr_map = 0; + if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) + dimm10_addr_map = 0; + if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) + dimm11_addr_map = 0; + + /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ + /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ + if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) + adev->gfx.config.mem_row_size_in_kb = 2; + else + adev->gfx.config.mem_row_size_in_kb = 1; + } else { + tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); + adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; + if (adev->gfx.config.mem_row_size_in_kb > 4) + adev->gfx.config.mem_row_size_in_kb = 4; + } + + adev->gfx.config.shader_engine_tile_size = 32; + adev->gfx.config.num_gpus = 1; + adev->gfx.config.multi_gpu_tile_size = 64; + + /* fix up row size */ + switch (adev->gfx.config.mem_row_size_in_kb) { + case 1: + default: + gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); + break; + case 2: + gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); + break; + case 4: + gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); + break; + } + adev->gfx.config.gb_addr_config = gb_addr_config; +} + static int gfx_v8_0_sw_init(void *handle) { int i, r; @@ -1010,6 +1302,8 @@ static int gfx_v8_0_sw_init(void *handle) adev->gfx.ce_ram_size = 0x8000; + gfx_v8_0_gpu_early_init(adev); + return 0; } @@ -1610,6 +1904,273 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); } break; + case CHIP_STONEY: + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 1: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 2: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 3: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 4: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 5: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 6: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)); + break; + case 8: + gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | + PIPE_CONFIG(ADDR_SURF_P2)); + break; + case 9: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 10: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 11: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 13: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 14: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 15: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 16: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 18: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 19: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 20: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 21: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 22: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 24: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 25: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 26: + gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1)); + break; + case 27: + gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 28: + gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2)); + break; + case 29: + gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | + PIPE_CONFIG(ADDR_SURF_P2) | + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) | + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8)); + break; + case 7: + case 12: + case 17: + case 23: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden); + } + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) { + switch (reg_offset) { + case 0: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 1: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 2: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 3: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 4: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 5: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 6: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 8: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 9: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 10: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 11: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 12: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 13: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) | + NUM_BANKS(ADDR_SURF_16_BANK)); + break; + case 14: + gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) | + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) | + NUM_BANKS(ADDR_SURF_8_BANK)); + break; + case 7: + /* unused idx */ + continue; + default: + gb_tile_moden = 0; + break; + }; + adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden; + WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden); + } + break; case CHIP_CARRIZO: default: for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { @@ -2043,203 +2604,23 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev) static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) { - u32 gb_addr_config; - u32 mc_shared_chmap, mc_arb_ramcfg; - u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map; u32 tmp; int i; - switch (adev->asic_type) { - case CHIP_TOPAZ: - adev->gfx.config.max_shader_engines = 1; - adev->gfx.config.max_tile_pipes = 2; - adev->gfx.config.max_cu_per_sh = 6; - adev->gfx.config.max_sh_per_se = 1; - adev->gfx.config.max_backends_per_se = 2; - adev->gfx.config.max_texture_channel_caches = 2; - adev->gfx.config.max_gprs = 256; - adev->gfx.config.max_gs_threads = 32; - adev->gfx.config.max_hw_contexts = 8; - - adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; - adev->gfx.config.sc_prim_fifo_size_backend = 0x100; - adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; - adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN; - break; - case CHIP_FIJI: - adev->gfx.config.max_shader_engines = 4; - adev->gfx.config.max_tile_pipes = 16; - adev->gfx.config.max_cu_per_sh = 16; - adev->gfx.config.max_sh_per_se = 1; - adev->gfx.config.max_backends_per_se = 4; - adev->gfx.config.max_texture_channel_caches = 8; - adev->gfx.config.max_gprs = 256; - adev->gfx.config.max_gs_threads = 32; - adev->gfx.config.max_hw_contexts = 8; - - adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; - adev->gfx.config.sc_prim_fifo_size_backend = 0x100; - adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; - adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; - break; - case CHIP_TONGA: - adev->gfx.config.max_shader_engines = 4; - adev->gfx.config.max_tile_pipes = 8; - adev->gfx.config.max_cu_per_sh = 8; - adev->gfx.config.max_sh_per_se = 1; - adev->gfx.config.max_backends_per_se = 2; - adev->gfx.config.max_texture_channel_caches = 8; - adev->gfx.config.max_gprs = 256; - adev->gfx.config.max_gs_threads = 32; - adev->gfx.config.max_hw_contexts = 8; - - adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; - adev->gfx.config.sc_prim_fifo_size_backend = 0x100; - adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; - adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; - break; - case CHIP_CARRIZO: - adev->gfx.config.max_shader_engines = 1; - adev->gfx.config.max_tile_pipes = 2; - adev->gfx.config.max_sh_per_se = 1; - adev->gfx.config.max_backends_per_se = 2; - - switch (adev->pdev->revision) { - case 0xc4: - case 0x84: - case 0xc8: - case 0xcc: - /* B10 */ - adev->gfx.config.max_cu_per_sh = 8; - break; - case 0xc5: - case 0x81: - case 0x85: - case 0xc9: - case 0xcd: - /* B8 */ - adev->gfx.config.max_cu_per_sh = 6; - break; - case 0xc6: - case 0xca: - case 0xce: - /* B6 */ - adev->gfx.config.max_cu_per_sh = 6; - break; - case 0xc7: - case 0x87: - case 0xcb: - default: - /* B4 */ - adev->gfx.config.max_cu_per_sh = 4; - break; - } - - adev->gfx.config.max_texture_channel_caches = 2; - adev->gfx.config.max_gprs = 256; - adev->gfx.config.max_gs_threads = 32; - adev->gfx.config.max_hw_contexts = 8; - - adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; - adev->gfx.config.sc_prim_fifo_size_backend = 0x100; - adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; - adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN; - break; - default: - adev->gfx.config.max_shader_engines = 2; - adev->gfx.config.max_tile_pipes = 4; - adev->gfx.config.max_cu_per_sh = 2; - adev->gfx.config.max_sh_per_se = 1; - adev->gfx.config.max_backends_per_se = 2; - adev->gfx.config.max_texture_channel_caches = 4; - adev->gfx.config.max_gprs = 256; - adev->gfx.config.max_gs_threads = 32; - adev->gfx.config.max_hw_contexts = 8; - - adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; - adev->gfx.config.sc_prim_fifo_size_backend = 0x100; - adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; - adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; - break; - } - tmp = RREG32(mmGRBM_CNTL); tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff); WREG32(mmGRBM_CNTL, tmp); - mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP); - adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG); - mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg; - - adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; - adev->gfx.config.mem_max_burst_length_bytes = 256; - if (adev->flags & AMD_IS_APU) { - /* Get memory bank mapping mode. */ - tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); - dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); - dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP); - - tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING); - dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP); - dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP); - - /* Validate settings in case only one DIMM installed. */ - if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12)) - dimm00_addr_map = 0; - if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12)) - dimm01_addr_map = 0; - if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12)) - dimm10_addr_map = 0; - if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12)) - dimm11_addr_map = 0; - - /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */ - /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */ - if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11)) - adev->gfx.config.mem_row_size_in_kb = 2; - else - adev->gfx.config.mem_row_size_in_kb = 1; - } else { - tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS); - adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; - if (adev->gfx.config.mem_row_size_in_kb > 4) - adev->gfx.config.mem_row_size_in_kb = 4; - } - - adev->gfx.config.shader_engine_tile_size = 32; - adev->gfx.config.num_gpus = 1; - adev->gfx.config.multi_gpu_tile_size = 64; - - /* fix up row size */ - switch (adev->gfx.config.mem_row_size_in_kb) { - case 1: - default: - gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0); - break; - case 2: - gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1); - break; - case 4: - gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2); - break; - } - adev->gfx.config.gb_addr_config = gb_addr_config; - - WREG32(mmGB_ADDR_CONFIG, gb_addr_config); - WREG32(mmHDP_ADDR_CONFIG, gb_addr_config); - WREG32(mmDMIF_ADDR_CALC, gb_addr_config); + WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config); WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, - gb_addr_config & 0x70); + adev->gfx.config.gb_addr_config & 0x70); WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, - gb_addr_config & 0x70); - WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config); - WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); - WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); + adev->gfx.config.gb_addr_config & 0x70); + WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config); + WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config); gfx_v8_0_tiling_mode_table_init(adev); @@ -2256,13 +2637,13 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev) if (i == 0) { tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC); tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, SH_MEM_ALIGNMENT_MODE_UNALIGNED); WREG32(mmSH_MEM_CONFIG, tmp); } else { tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC); tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC); - tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, + tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, SH_MEM_ALIGNMENT_MODE_UNALIGNED); WREG32(mmSH_MEM_CONFIG, tmp); } @@ -2377,7 +2758,7 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device *adev) WREG32(mmRLC_CNTL, tmp); /* carrizo do enable cp interrupt after cp inited */ - if (adev->asic_type != CHIP_CARRIZO) + if (!(adev->flags & AMD_IS_APU)) gfx_v8_0_enable_gui_idle_interrupt(adev, true); udelay(50); @@ -2599,6 +2980,10 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, 0x00000002); amdgpu_ring_write(ring, 0x00000000); break; + case CHIP_STONEY: + amdgpu_ring_write(ring, 0x00000000); + amdgpu_ring_write(ring, 0x00000000); + break; default: BUG(); } @@ -3233,7 +3618,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) /* enable the doorbell if requested */ if (use_doorbell) { if ((adev->asic_type == CHIP_CARRIZO) || - (adev->asic_type == CHIP_FIJI)) { + (adev->asic_type == CHIP_FIJI) || + (adev->asic_type == CHIP_STONEY)) { WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, @@ -3305,7 +3691,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev) { int r; - if (adev->asic_type != CHIP_CARRIZO) + if (!(adev->flags & AMD_IS_APU)) gfx_v8_0_enable_gui_idle_interrupt(adev, false); if (!adev->firmware.smu_load) { @@ -4068,15 +4454,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, } } -static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring) -{ - if (gfx_v8_0_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring) { return ring->adev->wb.wb[ring->rptr_offs]; @@ -4107,6 +4484,7 @@ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | + EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5))); amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); @@ -4357,7 +4735,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, .test_ring = gfx_v8_0_ring_test_ring, .test_ib = gfx_v8_0_ring_test_ib, - .is_lockup = gfx_v8_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; @@ -4374,7 +4751,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, .test_ring = gfx_v8_0_ring_test_ring, .test_ib = gfx_v8_0_ring_test_ib, - .is_lockup = gfx_v8_0_ring_is_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 774528ab8704..85bbcdc73fff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -436,6 +436,33 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev, } /** + * gmc_v8_0_set_fault_enable_default - update VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev, + bool value) +{ + u32 tmp; + + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + WREG32(mmVM_CONTEXT1_CNTL, tmp); +} + +/** * gmc_v7_0_gart_enable - gart enable * * @adev: amdgpu_device pointer @@ -523,15 +550,13 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev) tmp = RREG32(mmVM_CONTEXT1_CNTL); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1); - tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1); tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, amdgpu_vm_block_size - 9); WREG32(mmVM_CONTEXT1_CNTL, tmp); + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) + gmc_v7_0_set_fault_enable_default(adev, false); + else + gmc_v7_0_set_fault_enable_default(adev, true); if (adev->asic_type == CHIP_KAVERI) { tmp = RREG32(mmCHUB_CONTROL); @@ -940,7 +965,7 @@ static int gmc_v7_0_sw_fini(void *handle) if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) - amdgpu_fence_unref(&adev->vm_manager.active[i]); + fence_put(adev->vm_manager.active[i]); gmc_v7_0_vm_fini(adev); adev->vm_manager.enabled = false; } @@ -990,7 +1015,7 @@ static int gmc_v7_0_suspend(void *handle) if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) - amdgpu_fence_unref(&adev->vm_manager.active[i]); + fence_put(adev->vm_manager.active[i]); gmc_v7_0_vm_fini(adev); adev->vm_manager.enabled = false; } @@ -1262,6 +1287,15 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); + /* reset addr and status */ + WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); + + if (!addr && !status) + return 0; + + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) + gmc_v7_0_set_fault_enable_default(adev, false); + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", entry->src_id, entry->src_data); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", @@ -1269,8 +1303,6 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", status); gmc_v7_0_vm_decode_fault(adev, status, addr, mc_client); - /* reset addr and status */ - WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 9a07742620d0..1bcc4e74e3b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -93,6 +93,12 @@ static const u32 cz_mgcg_cgcg_init[] = mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 }; +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 +}; + + static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) { switch (adev->asic_type) { @@ -125,6 +131,11 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + break; default: break; } @@ -228,6 +239,7 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) chip_name = "fiji"; break; case CHIP_CARRIZO: + case CHIP_STONEY: return 0; default: BUG(); } @@ -550,6 +562,35 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev, } /** + * gmc_v8_0_set_fault_enable_default - update VM fault handling + * + * @adev: amdgpu_device pointer + * @value: true redirects VM faults to the default page + */ +static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev, + bool value) +{ + u32 tmp; + + tmp = RREG32(mmVM_CONTEXT1_CNTL); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + READ_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, + EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value); + WREG32(mmVM_CONTEXT1_CNTL, tmp); +} + +/** * gmc_v8_0_gart_enable - gart enable * * @adev: amdgpu_device pointer @@ -663,6 +704,10 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev) tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE, amdgpu_vm_block_size - 9); WREG32(mmVM_CONTEXT1_CNTL, tmp); + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) + gmc_v8_0_set_fault_enable_default(adev, false); + else + gmc_v8_0_set_fault_enable_default(adev, true); gmc_v8_0_gart_flush_gpu_tlb(adev, 0); DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", @@ -939,7 +984,7 @@ static int gmc_v8_0_sw_fini(void *handle) if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) - amdgpu_fence_unref(&adev->vm_manager.active[i]); + fence_put(adev->vm_manager.active[i]); gmc_v8_0_vm_fini(adev); adev->vm_manager.enabled = false; } @@ -991,7 +1036,7 @@ static int gmc_v8_0_suspend(void *handle) if (adev->vm_manager.enabled) { for (i = 0; i < AMDGPU_NUM_VM; ++i) - amdgpu_fence_unref(&adev->vm_manager.active[i]); + fence_put(adev->vm_manager.active[i]); gmc_v8_0_vm_fini(adev); adev->vm_manager.enabled = false; } @@ -1262,6 +1307,15 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR); status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); mc_client = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); + /* reset addr and status */ + WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); + + if (!addr && !status) + return 0; + + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) + gmc_v8_0_set_fault_enable_default(adev, false); + dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n", entry->src_id, entry->src_data); dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", @@ -1269,8 +1323,6 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", status); gmc_v8_0_vm_decode_fault(adev, status, addr, mc_client); - /* reset addr and status */ - WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c index 94ec04a9c4d5..9745ed3a9aef 100644 --- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c @@ -2995,6 +2995,12 @@ static int kv_dpm_late_init(void *handle) { /* powerdown unused blocks for now */ struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int ret; + + /* init the sysfs and debugfs files late */ + ret = amdgpu_pm_sysfs_init(adev); + if (ret) + return ret; kv_dpm_powergate_acp(adev, true); kv_dpm_powergate_samu(adev, true); @@ -3038,9 +3044,6 @@ static int kv_dpm_sw_init(void *handle) adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps; if (amdgpu_dpm == 1) amdgpu_pm_print_power_states(adev); - ret = amdgpu_pm_sysfs_init(adev); - if (ret) - goto dpm_failed; mutex_unlock(&adev->pm.mutex); DRM_INFO("amdgpu: dpm initialized\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 14e87234171a..2cf50180cc51 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -118,7 +118,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) { const char *chip_name; char fw_name[30]; - int err, i; + int err = 0, i; struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; const struct sdma_firmware_header_v1_0 *hdr; @@ -132,27 +132,27 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev) default: BUG(); } - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { if (i == 0) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); - err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); + err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); if (err) goto out; - err = amdgpu_ucode_validate(adev->sdma[i].fw); + err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); if (err) goto out; - hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; - adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); - adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); - if (adev->sdma[i].feature_version >= 20) - adev->sdma[i].burst_nop = true; + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; + adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); + adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); + if (adev->sdma.instance[i].feature_version >= 20) + adev->sdma.instance[i].burst_nop = true; if (adev->firmware.smu_load) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; - info->fw = adev->sdma[i].fw; + info->fw = adev->sdma.instance[i].fw; header = (const struct common_firmware_header *)info->fw->data; adev->firmware.fw_size += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); @@ -164,9 +164,9 @@ out: printk(KERN_ERR "sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - release_firmware(adev->sdma[i].fw); - adev->sdma[i].fw = NULL; + for (i = 0; i < adev->sdma.num_instances; i++) { + release_firmware(adev->sdma.instance[i].fw); + adev->sdma.instance[i].fw = NULL; } } return err; @@ -199,7 +199,7 @@ static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring) static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; return wptr; @@ -215,14 +215,14 @@ static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring) static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); } static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) { - struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring); + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); int i; for (i = 0; i < count; i++) @@ -284,7 +284,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask = 0; - if (ring == &ring->adev->sdma[0].ring) + if (ring == &ring->adev->sdma.instance[0].ring) ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); else ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); @@ -368,8 +368,8 @@ static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring, */ static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; - struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; + struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; + struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; u32 rb_cntl, ib_cntl; int i; @@ -377,7 +377,7 @@ static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev) (adev->mman.buffer_funcs_ring == sdma1)) amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); @@ -419,7 +419,7 @@ static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable) sdma_v2_4_rlc_stop(adev); } - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); if (enable) f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); @@ -445,8 +445,8 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev) u32 wb_offset; int i, j, r; - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - ring = &adev->sdma[i].ring; + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; wb_offset = (ring->rptr_offs * 4); mutex_lock(&adev->srbm_mutex); @@ -545,29 +545,23 @@ static int sdma_v2_4_load_microcode(struct amdgpu_device *adev) const __le32 *fw_data; u32 fw_size; int i, j; - bool smc_loads_fw = false; /* XXX fix me */ - - if (!adev->sdma[0].fw || !adev->sdma[1].fw) - return -EINVAL; /* halt the MEs */ sdma_v2_4_enable(adev, false); - if (smc_loads_fw) { - /* XXX query SMC for fw load complete */ - } else { - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; - amdgpu_ucode_print_sdma_hdr(&hdr->header); - fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; - fw_data = (const __le32 *) - (adev->sdma[i].fw->data + - le32_to_cpu(hdr->header.ucode_array_offset_bytes)); - WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); - for (j = 0; j < fw_size; j++) - WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); - WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); - } + for (i = 0; i < adev->sdma.num_instances; i++) { + if (!adev->sdma.instance[i].fw) + return -EINVAL; + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; + amdgpu_ucode_print_sdma_hdr(&hdr->header); + fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; + fw_data = (const __le32 *) + (adev->sdma.instance[i].fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); + for (j = 0; j < fw_size; j++) + WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); } return 0; @@ -894,7 +888,7 @@ static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, */ static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib) { - struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring); + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring); u32 pad_count; int i; @@ -952,6 +946,8 @@ static int sdma_v2_4_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->sdma.num_instances = SDMA_MAX_INSTANCE; + sdma_v2_4_set_ring_funcs(adev); sdma_v2_4_set_buffer_funcs(adev); sdma_v2_4_set_vm_pte_funcs(adev); @@ -963,21 +959,21 @@ static int sdma_v2_4_early_init(void *handle) static int sdma_v2_4_sw_init(void *handle) { struct amdgpu_ring *ring; - int r; + int r, i; struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* SDMA trap event */ - r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); + r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); + r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); + r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); if (r) return r; @@ -987,31 +983,20 @@ static int sdma_v2_4_sw_init(void *handle) return r; } - ring = &adev->sdma[0].ring; - ring->ring_obj = NULL; - ring->use_doorbell = false; - - ring = &adev->sdma[1].ring; - ring->ring_obj = NULL; - ring->use_doorbell = false; - - ring = &adev->sdma[0].ring; - sprintf(ring->name, "sdma0"); - r = amdgpu_ring_init(adev, ring, 256 * 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, - &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, - AMDGPU_RING_TYPE_SDMA); - if (r) - return r; - - ring = &adev->sdma[1].ring; - sprintf(ring->name, "sdma1"); - r = amdgpu_ring_init(adev, ring, 256 * 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, - &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); - if (r) - return r; + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; + ring->ring_obj = NULL; + ring->use_doorbell = false; + sprintf(ring->name, "sdma%d", i); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, + &adev->sdma.trap_irq, + (i == 0) ? + AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + } return r; } @@ -1019,9 +1004,10 @@ static int sdma_v2_4_sw_init(void *handle) static int sdma_v2_4_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; - amdgpu_ring_fini(&adev->sdma[0].ring); - amdgpu_ring_fini(&adev->sdma[1].ring); + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ring_fini(&adev->sdma.instance[i].ring); return 0; } @@ -1100,7 +1086,7 @@ static void sdma_v2_4_print_status(void *handle) dev_info(adev->dev, "VI SDMA registers\n"); dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", RREG32(mmSRBM_STATUS2)); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", @@ -1243,7 +1229,7 @@ static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, case 0: switch (queue_id) { case 0: - amdgpu_fence_process(&adev->sdma[0].ring); + amdgpu_fence_process(&adev->sdma.instance[0].ring); break; case 1: /* XXX compute */ @@ -1256,7 +1242,7 @@ static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev, case 1: switch (queue_id) { case 0: - amdgpu_fence_process(&adev->sdma[1].ring); + amdgpu_fence_process(&adev->sdma.instance[1].ring); break; case 1: /* XXX compute */ @@ -1309,24 +1295,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { .set_powergating_state = sdma_v2_4_set_powergating_state, }; -/** - * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up - * - * @ring: amdgpu_ring structure holding ring information - * - * Check if the async DMA engine is locked up (VI). - * Returns true if the engine appears to be locked up, false if not. - */ -static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring) -{ - - if (sdma_v2_4_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, @@ -1339,14 +1307,15 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, .test_ring = sdma_v2_4_ring_test_ring, .test_ib = sdma_v2_4_ring_test_ib, - .is_lockup = sdma_v2_4_ring_is_lockup, .insert_nop = sdma_v2_4_ring_insert_nop, }; static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) { - adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs; - adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) + adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs; } static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = { @@ -1360,9 +1329,9 @@ static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = { static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev) { - adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; - adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; - adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; + adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs; + adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs; } /** @@ -1428,7 +1397,7 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev) { if (adev->mman.buffer_funcs == NULL) { adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } } @@ -1443,7 +1412,7 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev) { if (adev->vm_manager.vm_pte_funcs == NULL) { adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs; - adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; + adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring; adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true; } } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 9bfe92df15f7..7253132f04b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -55,6 +55,7 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin"); MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { @@ -122,6 +123,19 @@ static const u32 cz_mgcg_cgcg_init[] = mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; +static const u32 stoney_golden_settings_a11[] = +{ + mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, + mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100, + mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100, +}; + +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100, +}; + /* * sDMA - System DMA * Starting with CIK, the GPU has new asynchronous @@ -166,6 +180,14 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + amdgpu_program_register_sequence(adev, + stoney_golden_settings_a11, + (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + break; default: break; } @@ -184,7 +206,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) { const char *chip_name; char fw_name[30]; - int err, i; + int err = 0, i; struct amdgpu_firmware_info *info = NULL; const struct common_firmware_header *header = NULL; const struct sdma_firmware_header_v1_0 *hdr; @@ -201,30 +223,33 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) case CHIP_CARRIZO: chip_name = "carrizo"; break; + case CHIP_STONEY: + chip_name = "stoney"; + break; default: BUG(); } - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { if (i == 0) snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name); else snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name); - err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev); + err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); if (err) goto out; - err = amdgpu_ucode_validate(adev->sdma[i].fw); + err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); if (err) goto out; - hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; - adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version); - adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); - if (adev->sdma[i].feature_version >= 20) - adev->sdma[i].burst_nop = true; + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; + adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); + adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); + if (adev->sdma.instance[i].feature_version >= 20) + adev->sdma.instance[i].burst_nop = true; if (adev->firmware.smu_load) { info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i]; info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i; - info->fw = adev->sdma[i].fw; + info->fw = adev->sdma.instance[i].fw; header = (const struct common_firmware_header *)info->fw->data; adev->firmware.fw_size += ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); @@ -235,9 +260,9 @@ out: printk(KERN_ERR "sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - release_firmware(adev->sdma[i].fw); - adev->sdma[i].fw = NULL; + for (i = 0; i < adev->sdma.num_instances; i++) { + release_firmware(adev->sdma.instance[i].fw); + adev->sdma.instance[i].fw = NULL; } } return err; @@ -276,7 +301,7 @@ static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring) /* XXX check if swapping is necessary on BE */ wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; } else { - int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2; } @@ -300,7 +325,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) adev->wb.wb[ring->wptr_offs] = ring->wptr << 2; WDOORBELL32(ring->doorbell_index, ring->wptr << 2); } else { - int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1; + int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1; WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2); } @@ -308,7 +333,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring) static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) { - struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring); + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); int i; for (i = 0; i < count; i++) @@ -369,7 +394,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask = 0; - if (ring == &ring->adev->sdma[0].ring) + if (ring == &ring->adev->sdma.instance[0].ring) ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); else ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); @@ -454,8 +479,8 @@ static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring, */ static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *sdma0 = &adev->sdma[0].ring; - struct amdgpu_ring *sdma1 = &adev->sdma[1].ring; + struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; + struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; u32 rb_cntl, ib_cntl; int i; @@ -463,7 +488,7 @@ static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev) (adev->mman.buffer_funcs_ring == sdma1)) amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); @@ -500,7 +525,7 @@ static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable) u32 f32_cntl; int i; - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); if (enable) f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, @@ -530,7 +555,7 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable) sdma_v3_0_rlc_stop(adev); } - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); if (enable) f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); @@ -557,8 +582,8 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) u32 doorbell; int i, j, r; - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - ring = &adev->sdma[i].ring; + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; wb_offset = (ring->rptr_offs * 4); mutex_lock(&adev->srbm_mutex); @@ -669,23 +694,22 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) u32 fw_size; int i, j; - if (!adev->sdma[0].fw || !adev->sdma[1].fw) - return -EINVAL; - /* halt the MEs */ sdma_v3_0_enable(adev, false); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { - hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data; + for (i = 0; i < adev->sdma.num_instances; i++) { + if (!adev->sdma.instance[i].fw) + return -EINVAL; + hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; amdgpu_ucode_print_sdma_hdr(&hdr->header); fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; fw_data = (const __le32 *) - (adev->sdma[i].fw->data + + (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); for (j = 0; j < fw_size; j++) WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); - WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version); + WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); } return 0; @@ -701,21 +725,21 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev) */ static int sdma_v3_0_start(struct amdgpu_device *adev) { - int r; + int r, i; if (!adev->firmware.smu_load) { r = sdma_v3_0_load_microcode(adev); if (r) return r; } else { - r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, - AMDGPU_UCODE_ID_SDMA0); - if (r) - return -EINVAL; - r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, - AMDGPU_UCODE_ID_SDMA1); - if (r) - return -EINVAL; + for (i = 0; i < adev->sdma.num_instances; i++) { + r = adev->smu.smumgr_funcs->check_fw_load_finish(adev, + (i == 0) ? + AMDGPU_UCODE_ID_SDMA0 : + AMDGPU_UCODE_ID_SDMA1); + if (r) + return -EINVAL; + } } /* unhalt the MEs */ @@ -1013,7 +1037,7 @@ static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, */ static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib) { - struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring); + struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring); u32 pad_count; int i; @@ -1071,6 +1095,15 @@ static int sdma_v3_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + switch (adev->asic_type) { + case CHIP_STONEY: + adev->sdma.num_instances = 1; + break; + default: + adev->sdma.num_instances = SDMA_MAX_INSTANCE; + break; + } + sdma_v3_0_set_ring_funcs(adev); sdma_v3_0_set_buffer_funcs(adev); sdma_v3_0_set_vm_pte_funcs(adev); @@ -1082,21 +1115,21 @@ static int sdma_v3_0_early_init(void *handle) static int sdma_v3_0_sw_init(void *handle) { struct amdgpu_ring *ring; - int r; + int r, i; struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* SDMA trap event */ - r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq); + r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq); + r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq); if (r) return r; /* SDMA Privileged inst */ - r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq); + r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq); if (r) return r; @@ -1106,33 +1139,23 @@ static int sdma_v3_0_sw_init(void *handle) return r; } - ring = &adev->sdma[0].ring; - ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0; - - ring = &adev->sdma[1].ring; - ring->ring_obj = NULL; - ring->use_doorbell = true; - ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1; - - ring = &adev->sdma[0].ring; - sprintf(ring->name, "sdma0"); - r = amdgpu_ring_init(adev, ring, 256 * 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, - &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0, - AMDGPU_RING_TYPE_SDMA); - if (r) - return r; - - ring = &adev->sdma[1].ring; - sprintf(ring->name, "sdma1"); - r = amdgpu_ring_init(adev, ring, 256 * 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, - &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); - if (r) - return r; + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; + ring->ring_obj = NULL; + ring->use_doorbell = true; + ring->doorbell_index = (i == 0) ? + AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1; + + sprintf(ring->name, "sdma%d", i); + r = amdgpu_ring_init(adev, ring, 256 * 1024, + SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, + &adev->sdma.trap_irq, + (i == 0) ? + AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, + AMDGPU_RING_TYPE_SDMA); + if (r) + return r; + } return r; } @@ -1140,9 +1163,10 @@ static int sdma_v3_0_sw_init(void *handle) static int sdma_v3_0_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i; - amdgpu_ring_fini(&adev->sdma[0].ring); - amdgpu_ring_fini(&adev->sdma[1].ring); + for (i = 0; i < adev->sdma.num_instances; i++) + amdgpu_ring_fini(&adev->sdma.instance[i].ring); return 0; } @@ -1222,7 +1246,7 @@ static void sdma_v3_0_print_status(void *handle) dev_info(adev->dev, "VI SDMA registers\n"); dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", RREG32(mmSRBM_STATUS2)); - for (i = 0; i < SDMA_MAX_INSTANCE; i++) { + for (i = 0; i < adev->sdma.num_instances; i++) { dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n", i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i])); dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n", @@ -1367,7 +1391,7 @@ static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, case 0: switch (queue_id) { case 0: - amdgpu_fence_process(&adev->sdma[0].ring); + amdgpu_fence_process(&adev->sdma.instance[0].ring); break; case 1: /* XXX compute */ @@ -1380,7 +1404,7 @@ static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev, case 1: switch (queue_id) { case 0: - amdgpu_fence_process(&adev->sdma[1].ring); + amdgpu_fence_process(&adev->sdma.instance[1].ring); break; case 1: /* XXX compute */ @@ -1432,24 +1456,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { .set_powergating_state = sdma_v3_0_set_powergating_state, }; -/** - * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up - * - * @ring: amdgpu_ring structure holding ring information - * - * Check if the async DMA engine is locked up (VI). - * Returns true if the engine appears to be locked up, false if not. - */ -static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring) -{ - - if (sdma_v3_0_is_idle(ring->adev)) { - amdgpu_ring_lockup_update(ring); - return false; - } - return amdgpu_ring_test_lockup(ring); -} - static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, @@ -1462,14 +1468,15 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, .test_ring = sdma_v3_0_ring_test_ring, .test_ib = sdma_v3_0_ring_test_ib, - .is_lockup = sdma_v3_0_ring_is_lockup, .insert_nop = sdma_v3_0_ring_insert_nop, }; static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) { - adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs; - adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs; + int i; + + for (i = 0; i < adev->sdma.num_instances; i++) + adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs; } static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = { @@ -1483,9 +1490,9 @@ static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = { static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev) { - adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; - adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; - adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; + adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; + adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs; + adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs; } /** @@ -1551,7 +1558,7 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev) { if (adev->mman.buffer_funcs == NULL) { adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs; - adev->mman.buffer_funcs_ring = &adev->sdma[0].ring; + adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; } } @@ -1566,7 +1573,7 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev) { if (adev->vm_manager.vm_pte_funcs == NULL) { adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs; - adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring; + adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring; adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true; } } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index ed50dd725788..5e9f73af83a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -885,7 +885,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .emit_semaphore = uvd_v4_2_ring_emit_semaphore, .test_ring = uvd_v4_2_ring_test_ring, .test_ib = uvd_v4_2_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 9ad8b9906c0b..38864f562981 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -824,7 +824,6 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .emit_semaphore = uvd_v5_0_ring_emit_semaphore, .test_ring = uvd_v5_0_ring_test_ring, .test_ib = uvd_v5_0_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 7e9934fa4193..121915bbc3b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -808,7 +808,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = { .emit_semaphore = uvd_v6_0_ring_emit_semaphore, .test_ring = uvd_v6_0_ring_test_ring, .test_ib = uvd_v6_0_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index cd16df543f64..52ac7a8f1e58 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -642,7 +642,6 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { .emit_semaphore = amdgpu_vce_ring_emit_semaphore, .test_ring = amdgpu_vce_ring_test_ring, .test_ib = amdgpu_vce_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index f0656dfb53f3..6a52db6ad8d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -205,8 +205,9 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) u32 tmp; unsigned ret; - /* Fiji is single pipe */ - if (adev->asic_type == CHIP_FIJI) { + /* Fiji, Stoney are single pipe */ + if ((adev->asic_type == CHIP_FIJI) || + (adev->asic_type == CHIP_STONEY)){ ret = AMDGPU_VCE_HARVEST_VCE1; return ret; } @@ -643,7 +644,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = { .emit_semaphore = amdgpu_vce_ring_emit_semaphore, .test_ring = amdgpu_vce_ring_test_ring, .test_ib = amdgpu_vce_ring_test_ib, - .is_lockup = amdgpu_ring_test_lockup, .insert_nop = amdgpu_ring_insert_nop, }; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index b55ceb14fdcd..2adc1c855e85 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -232,6 +232,13 @@ static const u32 cz_mgcg_cgcg_init[] = mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, }; +static const u32 stoney_mgcg_cgcg_init[] = +{ + mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100, + mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104, + mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027, +}; + static void vi_init_golden_registers(struct amdgpu_device *adev) { /* Some of the registers might be dependent on GRBM_GFX_INDEX */ @@ -258,6 +265,11 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); break; + case CHIP_STONEY: + amdgpu_program_register_sequence(adev, + stoney_mgcg_cgcg_init, + (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); + break; default: break; } @@ -488,6 +500,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, case CHIP_FIJI: case CHIP_TONGA: case CHIP_CARRIZO: + case CHIP_STONEY: asic_register_table = cz_allowed_read_registers; size = ARRAY_SIZE(cz_allowed_read_registers); break; @@ -543,8 +556,10 @@ static void vi_print_gpu_status_regs(struct amdgpu_device *adev) RREG32(mmSRBM_STATUS2)); dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); - dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", - RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); + if (adev->sdma.num_instances > 1) { + dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", + RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); + } dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", RREG32(mmCP_STALLED_STAT1)); @@ -639,9 +654,11 @@ u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev) reset_mask |= AMDGPU_RESET_DMA; /* SDMA1_STATUS_REG */ - tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); - if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) - reset_mask |= AMDGPU_RESET_DMA1; + if (adev->sdma.num_instances > 1) { + tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); + if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) + reset_mask |= AMDGPU_RESET_DMA1; + } #if 0 /* VCE_STATUS */ if (adev->asic_type != CHIP_TOPAZ) { @@ -1005,6 +1022,9 @@ static void vi_pcie_gen3_enable(struct amdgpu_device *adev) u32 mask; int ret; + if (pci_is_root_bus(adev->pdev->bus)) + return; + if (amdgpu_pcie_gen2 == 0) return; @@ -1316,6 +1336,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); break; case CHIP_CARRIZO: + case CHIP_STONEY: adev->ip_blocks = cz_ip_blocks; adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks); break; @@ -1327,11 +1348,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) return 0; } +#define ATI_REV_ID_FUSE_MACRO__ADDRESS 0xC0014044 +#define ATI_REV_ID_FUSE_MACRO__SHIFT 9 +#define ATI_REV_ID_FUSE_MACRO__MASK 0x00001E00 + static uint32_t vi_get_rev_id(struct amdgpu_device *adev) { if (adev->asic_type == CHIP_TOPAZ) return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK) >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT; + else if (adev->flags & AMD_IS_APU) + return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) + >> ATI_REV_ID_FUSE_MACRO__SHIFT; else return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; @@ -1385,32 +1413,35 @@ static int vi_common_early_init(void *handle) adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = 0x1; - if (amdgpu_smc_load_fw && smc_enabled) - adev->firmware.smu_load = true; break; case CHIP_FIJI: + adev->has_uvd = true; + adev->cg_flags = 0; + adev->pg_flags = 0; + adev->external_rev_id = adev->rev_id + 0x3c; + break; case CHIP_TONGA: adev->has_uvd = true; adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x14; - if (amdgpu_smc_load_fw && smc_enabled) - adev->firmware.smu_load = true; break; case CHIP_CARRIZO: + case CHIP_STONEY: adev->has_uvd = true; adev->cg_flags = 0; /* Disable UVD pg */ adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE; adev->external_rev_id = adev->rev_id + 0x1; - if (amdgpu_smc_load_fw && smc_enabled) - adev->firmware.smu_load = true; break; default: /* FIXME: not supported yet */ return -EINVAL; } + if (amdgpu_smc_load_fw && smc_enabled) + adev->firmware.smu_load = true; + return 0; } diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 68a8eaa1b7d0..fe28fb353fab 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -47,6 +47,7 @@ enum amd_asic_type { CHIP_TONGA, CHIP_FIJI, CHIP_CARRIZO, + CHIP_STONEY, CHIP_LAST, }; diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h new file mode 100644 index 000000000000..2d672b3d2fed --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_d.h @@ -0,0 +1,2791 @@ +/* + * GFX_8_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_8_1_D_H +#define GFX_8_1_D_H + +#define mmCB_BLEND_RED 0xa105 +#define mmCB_BLEND_GREEN 0xa106 +#define mmCB_BLEND_BLUE 0xa107 +#define mmCB_BLEND_ALPHA 0xa108 +#define mmCB_DCC_CONTROL 0xa109 +#define mmCB_COLOR_CONTROL 0xa202 +#define mmCB_BLEND0_CONTROL 0xa1e0 +#define mmCB_BLEND1_CONTROL 0xa1e1 +#define mmCB_BLEND2_CONTROL 0xa1e2 +#define mmCB_BLEND3_CONTROL 0xa1e3 +#define mmCB_BLEND4_CONTROL 0xa1e4 +#define mmCB_BLEND5_CONTROL 0xa1e5 +#define mmCB_BLEND6_CONTROL 0xa1e6 +#define mmCB_BLEND7_CONTROL 0xa1e7 +#define mmCB_COLOR0_BASE 0xa318 +#define mmCB_COLOR1_BASE 0xa327 +#define mmCB_COLOR2_BASE 0xa336 +#define mmCB_COLOR3_BASE 0xa345 +#define mmCB_COLOR4_BASE 0xa354 +#define mmCB_COLOR5_BASE 0xa363 +#define mmCB_COLOR6_BASE 0xa372 +#define mmCB_COLOR7_BASE 0xa381 +#define mmCB_COLOR0_PITCH 0xa319 +#define mmCB_COLOR1_PITCH 0xa328 +#define mmCB_COLOR2_PITCH 0xa337 +#define mmCB_COLOR3_PITCH 0xa346 +#define mmCB_COLOR4_PITCH 0xa355 +#define mmCB_COLOR5_PITCH 0xa364 +#define mmCB_COLOR6_PITCH 0xa373 +#define mmCB_COLOR7_PITCH 0xa382 +#define mmCB_COLOR0_SLICE 0xa31a +#define mmCB_COLOR1_SLICE 0xa329 +#define mmCB_COLOR2_SLICE 0xa338 +#define mmCB_COLOR3_SLICE 0xa347 +#define mmCB_COLOR4_SLICE 0xa356 +#define mmCB_COLOR5_SLICE 0xa365 +#define mmCB_COLOR6_SLICE 0xa374 +#define mmCB_COLOR7_SLICE 0xa383 +#define mmCB_COLOR0_VIEW 0xa31b +#define mmCB_COLOR1_VIEW 0xa32a +#define mmCB_COLOR2_VIEW 0xa339 +#define mmCB_COLOR3_VIEW 0xa348 +#define mmCB_COLOR4_VIEW 0xa357 +#define mmCB_COLOR5_VIEW 0xa366 +#define mmCB_COLOR6_VIEW 0xa375 +#define mmCB_COLOR7_VIEW 0xa384 +#define mmCB_COLOR0_INFO 0xa31c +#define mmCB_COLOR1_INFO 0xa32b +#define mmCB_COLOR2_INFO 0xa33a +#define mmCB_COLOR3_INFO 0xa349 +#define mmCB_COLOR4_INFO 0xa358 +#define mmCB_COLOR5_INFO 0xa367 +#define mmCB_COLOR6_INFO 0xa376 +#define mmCB_COLOR7_INFO 0xa385 +#define mmCB_COLOR0_ATTRIB 0xa31d +#define mmCB_COLOR1_ATTRIB 0xa32c +#define mmCB_COLOR2_ATTRIB 0xa33b +#define mmCB_COLOR3_ATTRIB 0xa34a +#define mmCB_COLOR4_ATTRIB 0xa359 +#define mmCB_COLOR5_ATTRIB 0xa368 +#define mmCB_COLOR6_ATTRIB 0xa377 +#define mmCB_COLOR7_ATTRIB 0xa386 +#define mmCB_COLOR0_DCC_CONTROL 0xa31e +#define mmCB_COLOR1_DCC_CONTROL 0xa32d +#define mmCB_COLOR2_DCC_CONTROL 0xa33c +#define mmCB_COLOR3_DCC_CONTROL 0xa34b +#define mmCB_COLOR4_DCC_CONTROL 0xa35a +#define mmCB_COLOR5_DCC_CONTROL 0xa369 +#define mmCB_COLOR6_DCC_CONTROL 0xa378 +#define mmCB_COLOR7_DCC_CONTROL 0xa387 +#define mmCB_COLOR0_CMASK 0xa31f +#define mmCB_COLOR1_CMASK 0xa32e +#define mmCB_COLOR2_CMASK 0xa33d +#define mmCB_COLOR3_CMASK 0xa34c +#define mmCB_COLOR4_CMASK 0xa35b +#define mmCB_COLOR5_CMASK 0xa36a +#define mmCB_COLOR6_CMASK 0xa379 +#define mmCB_COLOR7_CMASK 0xa388 +#define mmCB_COLOR0_CMASK_SLICE 0xa320 +#define mmCB_COLOR1_CMASK_SLICE 0xa32f +#define mmCB_COLOR2_CMASK_SLICE 0xa33e +#define mmCB_COLOR3_CMASK_SLICE 0xa34d +#define mmCB_COLOR4_CMASK_SLICE 0xa35c +#define mmCB_COLOR5_CMASK_SLICE 0xa36b +#define mmCB_COLOR6_CMASK_SLICE 0xa37a +#define mmCB_COLOR7_CMASK_SLICE 0xa389 +#define mmCB_COLOR0_FMASK 0xa321 +#define mmCB_COLOR1_FMASK 0xa330 +#define mmCB_COLOR2_FMASK 0xa33f +#define mmCB_COLOR3_FMASK 0xa34e +#define mmCB_COLOR4_FMASK 0xa35d +#define mmCB_COLOR5_FMASK 0xa36c +#define mmCB_COLOR6_FMASK 0xa37b +#define mmCB_COLOR7_FMASK 0xa38a +#define mmCB_COLOR0_FMASK_SLICE 0xa322 +#define mmCB_COLOR1_FMASK_SLICE 0xa331 +#define mmCB_COLOR2_FMASK_SLICE 0xa340 +#define mmCB_COLOR3_FMASK_SLICE 0xa34f +#define mmCB_COLOR4_FMASK_SLICE 0xa35e +#define mmCB_COLOR5_FMASK_SLICE 0xa36d +#define mmCB_COLOR6_FMASK_SLICE 0xa37c +#define mmCB_COLOR7_FMASK_SLICE 0xa38b +#define mmCB_COLOR0_CLEAR_WORD0 0xa323 +#define mmCB_COLOR1_CLEAR_WORD0 0xa332 +#define mmCB_COLOR2_CLEAR_WORD0 0xa341 +#define mmCB_COLOR3_CLEAR_WORD0 0xa350 +#define mmCB_COLOR4_CLEAR_WORD0 0xa35f +#define mmCB_COLOR5_CLEAR_WORD0 0xa36e +#define mmCB_COLOR6_CLEAR_WORD0 0xa37d +#define mmCB_COLOR7_CLEAR_WORD0 0xa38c +#define mmCB_COLOR0_CLEAR_WORD1 0xa324 +#define mmCB_COLOR1_CLEAR_WORD1 0xa333 +#define mmCB_COLOR2_CLEAR_WORD1 0xa342 +#define mmCB_COLOR3_CLEAR_WORD1 0xa351 +#define mmCB_COLOR4_CLEAR_WORD1 0xa360 +#define mmCB_COLOR5_CLEAR_WORD1 0xa36f +#define mmCB_COLOR6_CLEAR_WORD1 0xa37e +#define mmCB_COLOR7_CLEAR_WORD1 0xa38d +#define mmCB_COLOR0_DCC_BASE 0xa325 +#define mmCB_COLOR1_DCC_BASE 0xa334 +#define mmCB_COLOR2_DCC_BASE 0xa343 +#define mmCB_COLOR3_DCC_BASE 0xa352 +#define mmCB_COLOR4_DCC_BASE 0xa361 +#define mmCB_COLOR5_DCC_BASE 0xa370 +#define mmCB_COLOR6_DCC_BASE 0xa37f +#define mmCB_COLOR7_DCC_BASE 0xa38e +#define mmCB_TARGET_MASK 0xa08e +#define mmCB_SHADER_MASK 0xa08f +#define mmCB_HW_CONTROL 0x2684 +#define mmCB_HW_CONTROL_1 0x2685 +#define mmCB_HW_CONTROL_2 0x2686 +#define mmCB_HW_CONTROL_3 0x2683 +#define mmCB_DCC_CONFIG 0x2687 +#define mmCB_PERFCOUNTER_FILTER 0xdc00 +#define mmCB_PERFCOUNTER0_SELECT 0xdc01 +#define mmCB_PERFCOUNTER0_SELECT1 0xdc02 +#define mmCB_PERFCOUNTER1_SELECT 0xdc03 +#define mmCB_PERFCOUNTER2_SELECT 0xdc04 +#define mmCB_PERFCOUNTER3_SELECT 0xdc05 +#define mmCB_PERFCOUNTER0_LO 0xd406 +#define mmCB_PERFCOUNTER1_LO 0xd408 +#define mmCB_PERFCOUNTER2_LO 0xd40a +#define mmCB_PERFCOUNTER3_LO 0xd40c +#define mmCB_PERFCOUNTER0_HI 0xd407 +#define mmCB_PERFCOUNTER1_HI 0xd409 +#define mmCB_PERFCOUNTER2_HI 0xd40b +#define mmCB_PERFCOUNTER3_HI 0xd40d +#define mmCB_CGTT_SCLK_CTRL 0xf0a8 +#define mmCB_DEBUG_BUS_1 0x2699 +#define mmCB_DEBUG_BUS_2 0x269a +#define mmCB_DEBUG_BUS_3 0x269b +#define mmCB_DEBUG_BUS_4 0x269c +#define mmCB_DEBUG_BUS_5 0x269d +#define mmCB_DEBUG_BUS_6 0x269e +#define mmCB_DEBUG_BUS_7 0x269f +#define mmCB_DEBUG_BUS_8 0x26a0 +#define mmCB_DEBUG_BUS_9 0x26a1 +#define mmCB_DEBUG_BUS_10 0x26a2 +#define mmCB_DEBUG_BUS_11 0x26a3 +#define mmCB_DEBUG_BUS_12 0x26a4 +#define mmCB_DEBUG_BUS_13 0x26a5 +#define mmCB_DEBUG_BUS_14 0x26a6 +#define mmCB_DEBUG_BUS_15 0x26a7 +#define mmCB_DEBUG_BUS_16 0x26a8 +#define mmCB_DEBUG_BUS_17 0x26a9 +#define mmCB_DEBUG_BUS_18 0x26aa +#define mmCB_DEBUG_BUS_19 0x26ab +#define mmCB_DEBUG_BUS_20 0x26ac +#define mmCB_DEBUG_BUS_21 0x26ad +#define mmCB_DEBUG_BUS_22 0x26ae +#define mmCP_DFY_CNTL 0x3020 +#define mmCP_DFY_STAT 0x3021 +#define mmCP_DFY_ADDR_HI 0x3022 +#define mmCP_DFY_ADDR_LO 0x3023 +#define mmCP_DFY_DATA_0 0x3024 +#define mmCP_DFY_DATA_1 0x3025 +#define mmCP_DFY_DATA_2 0x3026 +#define mmCP_DFY_DATA_3 0x3027 +#define mmCP_DFY_DATA_4 0x3028 +#define mmCP_DFY_DATA_5 0x3029 +#define mmCP_DFY_DATA_6 0x302a +#define mmCP_DFY_DATA_7 0x302b +#define mmCP_DFY_DATA_8 0x302c +#define mmCP_DFY_DATA_9 0x302d +#define mmCP_DFY_DATA_10 0x302e +#define mmCP_DFY_DATA_11 0x302f +#define mmCP_DFY_DATA_12 0x3030 +#define mmCP_DFY_DATA_13 0x3031 +#define mmCP_DFY_DATA_14 0x3032 +#define mmCP_DFY_DATA_15 0x3033 +#define mmCP_DFY_CMD 0x3034 +#define mmCP_CPC_MGCG_SYNC_CNTL 0x3036 +#define mmCP_ATCL1_CNTL 0x303c +#define mmCP_RB0_BASE 0x3040 +#define mmCP_RB0_BASE_HI 0x30b1 +#define mmCP_RB_BASE 0x3040 +#define mmCP_RB1_BASE 0x3060 +#define mmCP_RB1_BASE_HI 0x30b2 +#define mmCP_RB2_BASE 0x3065 +#define mmCP_RB0_CNTL 0x3041 +#define mmCP_RB_CNTL 0x3041 +#define mmCP_RB1_CNTL 0x3061 +#define mmCP_RB2_CNTL 0x3066 +#define mmCP_RB_RPTR_WR 0x3042 +#define mmCP_RB0_RPTR_ADDR 0x3043 +#define mmCP_RB_RPTR_ADDR 0x3043 +#define mmCP_RB1_RPTR_ADDR 0x3062 +#define mmCP_RB2_RPTR_ADDR 0x3067 +#define mmCP_RB0_RPTR_ADDR_HI 0x3044 +#define mmCP_RB_RPTR_ADDR_HI 0x3044 +#define mmCP_RB1_RPTR_ADDR_HI 0x3063 +#define mmCP_RB2_RPTR_ADDR_HI 0x3068 +#define mmCP_RB0_WPTR 0x3045 +#define mmCP_RB_WPTR 0x3045 +#define mmCP_RB1_WPTR 0x3064 +#define mmCP_RB2_WPTR 0x3069 +#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 +#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 +#define mmGC_PRIV_MODE 0x3048 +#define mmCP_INT_CNTL 0x3049 +#define mmCP_INT_CNTL_RING0 0x306a +#define mmCP_INT_CNTL_RING1 0x306b +#define mmCP_INT_CNTL_RING2 0x306c +#define mmCP_INT_STATUS 0x304a +#define mmCP_INT_STATUS_RING0 0x306d +#define mmCP_INT_STATUS_RING1 0x306e +#define mmCP_INT_STATUS_RING2 0x306f +#define mmCP_DEVICE_ID 0x304b +#define mmCP_RING_PRIORITY_CNTS 0x304c +#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c +#define mmCP_RING0_PRIORITY 0x304d +#define mmCP_ME0_PIPE0_PRIORITY 0x304d +#define mmCP_RING1_PRIORITY 0x304e +#define mmCP_ME0_PIPE1_PRIORITY 0x304e +#define mmCP_RING2_PRIORITY 0x304f +#define mmCP_ME0_PIPE2_PRIORITY 0x304f +#define mmCP_ENDIAN_SWAP 0x3050 +#define mmCP_RB_VMID 0x3051 +#define mmCP_ME0_PIPE0_VMID 0x3052 +#define mmCP_ME0_PIPE1_VMID 0x3053 +#define mmCP_RB_DOORBELL_CONTROL 0x3059 +#define mmCP_RB_DOORBELL_RANGE_LOWER 0x305a +#define mmCP_RB_DOORBELL_RANGE_UPPER 0x305b +#define mmCP_MEC_DOORBELL_RANGE_LOWER 0x305c +#define mmCP_MEC_DOORBELL_RANGE_UPPER 0x305d +#define mmCP_PFP_UCODE_ADDR 0xf814 +#define mmCP_PFP_UCODE_DATA 0xf815 +#define mmCP_ME_RAM_RADDR 0xf816 +#define mmCP_ME_RAM_WADDR 0xf816 +#define mmCP_ME_RAM_DATA 0xf817 +#define mmCGTT_CPC_CLK_CTRL 0xf0b2 +#define mmCGTT_CPF_CLK_CTRL 0xf0b1 +#define mmCGTT_CP_CLK_CTRL 0xf0b0 +#define mmCP_CE_UCODE_ADDR 0xf818 +#define mmCP_CE_UCODE_DATA 0xf819 +#define mmCP_MEC_ME1_UCODE_ADDR 0xf81a +#define mmCP_MEC_ME1_UCODE_DATA 0xf81b +#define mmCP_MEC_ME2_UCODE_ADDR 0xf81c +#define mmCP_MEC_ME2_UCODE_DATA 0xf81d +#define mmCP_MEC1_F32_INT_DIS 0x30bd +#define mmCP_MEC2_F32_INT_DIS 0x30be +#define mmCP_PWR_CNTL 0x3078 +#define mmCP_MEM_SLP_CNTL 0x3079 +#define mmCP_ECC_FIRSTOCCURRENCE 0x307a +#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b +#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c +#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d +#define mmCP_CPF_DEBUG 0x3080 +#define mmCP_PQ_WPTR_POLL_CNTL 0x3083 +#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 +#define mmCPC_INT_CNTL 0x30b4 +#define mmCP_ME1_PIPE0_INT_CNTL 0x3085 +#define mmCP_ME1_PIPE1_INT_CNTL 0x3086 +#define mmCP_ME1_PIPE2_INT_CNTL 0x3087 +#define mmCP_ME1_PIPE3_INT_CNTL 0x3088 +#define mmCP_ME2_PIPE0_INT_CNTL 0x3089 +#define mmCP_ME2_PIPE1_INT_CNTL 0x308a +#define mmCP_ME2_PIPE2_INT_CNTL 0x308b +#define mmCP_ME2_PIPE3_INT_CNTL 0x308c +#define mmCPC_INT_STATUS 0x30b5 +#define mmCP_ME1_PIPE0_INT_STATUS 0x308d +#define mmCP_ME1_PIPE1_INT_STATUS 0x308e +#define mmCP_ME1_PIPE2_INT_STATUS 0x308f +#define mmCP_ME1_PIPE3_INT_STATUS 0x3090 +#define mmCP_ME2_PIPE0_INT_STATUS 0x3091 +#define mmCP_ME2_PIPE1_INT_STATUS 0x3092 +#define mmCP_ME2_PIPE2_INT_STATUS 0x3093 +#define mmCP_ME2_PIPE3_INT_STATUS 0x3094 +#define mmCP_ME1_INT_STAT_DEBUG 0x3095 +#define mmCP_ME2_INT_STAT_DEBUG 0x3096 +#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 +#define mmCP_ME1_PIPE0_PRIORITY 0x309a +#define mmCP_ME1_PIPE1_PRIORITY 0x309b +#define mmCP_ME1_PIPE2_PRIORITY 0x309c +#define mmCP_ME1_PIPE3_PRIORITY 0x309d +#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e +#define mmCP_ME2_PIPE0_PRIORITY 0x309f +#define mmCP_ME2_PIPE1_PRIORITY 0x30a0 +#define mmCP_ME2_PIPE2_PRIORITY 0x30a1 +#define mmCP_ME2_PIPE3_PRIORITY 0x30a2 +#define mmCP_CE_PRGRM_CNTR_START 0x30a3 +#define mmCP_PFP_PRGRM_CNTR_START 0x30a4 +#define mmCP_ME_PRGRM_CNTR_START 0x30a5 +#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 +#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 +#define mmCP_CE_INTR_ROUTINE_START 0x30a8 +#define mmCP_PFP_INTR_ROUTINE_START 0x30a9 +#define mmCP_ME_INTR_ROUTINE_START 0x30aa +#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab +#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac +#define mmCP_CONTEXT_CNTL 0x30ad +#define mmCP_MAX_CONTEXT 0x30ae +#define mmCP_IQ_WAIT_TIME1 0x30af +#define mmCP_IQ_WAIT_TIME2 0x30b0 +#define mmCP_VMID_RESET 0x30b3 +#define mmCP_VMID_PREEMPT 0x30b6 +#define mmCP_VMID_STATUS 0x30bf +#define mmCPC_INT_CNTX_ID 0x30b7 +#define mmCP_PQ_STATUS 0x30b8 +#define mmCP_CPC_IC_BASE_LO 0x30b9 +#define mmCP_CPC_IC_BASE_HI 0x30ba +#define mmCP_CPC_IC_BASE_CNTL 0x30bb +#define mmCP_CPC_IC_OP_CNTL 0x30bc +#define mmCP_CPC_STATUS 0x2084 +#define mmCP_CPC_BUSY_STAT 0x2085 +#define mmCP_CPC_STALLED_STAT1 0x2086 +#define mmCP_CPF_STATUS 0x2087 +#define mmCP_CPF_BUSY_STAT 0x2088 +#define mmCP_CPF_STALLED_STAT1 0x2089 +#define mmCP_CPC_GRBM_FREE_COUNT 0x208b +#define mmCP_MEC_CNTL 0x208d +#define mmCP_MEC_ME1_HEADER_DUMP 0x208e +#define mmCP_MEC_ME2_HEADER_DUMP 0x208f +#define mmCP_CPC_SCRATCH_INDEX 0x2090 +#define mmCP_CPC_SCRATCH_DATA 0x2091 +#define mmCPG_PERFCOUNTER1_SELECT 0xd800 +#define mmCPG_PERFCOUNTER1_LO 0xd000 +#define mmCPG_PERFCOUNTER1_HI 0xd001 +#define mmCPG_PERFCOUNTER0_SELECT1 0xd801 +#define mmCPG_PERFCOUNTER0_SELECT 0xd802 +#define mmCPG_PERFCOUNTER0_LO 0xd002 +#define mmCPG_PERFCOUNTER0_HI 0xd003 +#define mmCPC_PERFCOUNTER1_SELECT 0xd803 +#define mmCPC_PERFCOUNTER1_LO 0xd004 +#define mmCPC_PERFCOUNTER1_HI 0xd005 +#define mmCPC_PERFCOUNTER0_SELECT1 0xd804 +#define mmCPC_PERFCOUNTER0_SELECT 0xd809 +#define mmCPC_PERFCOUNTER0_LO 0xd006 +#define mmCPC_PERFCOUNTER0_HI 0xd007 +#define mmCPF_PERFCOUNTER1_SELECT 0xd805 +#define mmCPF_PERFCOUNTER1_LO 0xd008 +#define mmCPF_PERFCOUNTER1_HI 0xd009 +#define mmCPF_PERFCOUNTER0_SELECT1 0xd806 +#define mmCPF_PERFCOUNTER0_SELECT 0xd807 +#define mmCPF_PERFCOUNTER0_LO 0xd00a +#define mmCPF_PERFCOUNTER0_HI 0xd00b +#define mmCP_CPC_HALT_HYST_COUNT 0x20a7 +#define mmCP_DRAW_OBJECT 0xd810 +#define mmCP_DRAW_OBJECT_COUNTER 0xd811 +#define mmCP_DRAW_WINDOW_MASK_HI 0xd812 +#define mmCP_DRAW_WINDOW_HI 0xd813 +#define mmCP_DRAW_WINDOW_LO 0xd814 +#define mmCP_DRAW_WINDOW_CNTL 0xd815 +#define mmCP_PRT_LOD_STATS_CNTL0 0x20ad +#define mmCP_PRT_LOD_STATS_CNTL1 0x20ae +#define mmCP_PRT_LOD_STATS_CNTL2 0x20af +#define mmCP_CE_COMPARE_COUNT 0x20c0 +#define mmCP_CE_DE_COUNT 0x20c1 +#define mmCP_DE_CE_COUNT 0x20c2 +#define mmCP_DE_LAST_INVAL_COUNT 0x20c3 +#define mmCP_DE_DE_COUNT 0x20c4 +#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 +#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 +#define mmCP_EOP_DONE_CNTX_ID 0xc0d7 +#define mmCP_EOP_DONE_ADDR_LO 0xc000 +#define mmCP_EOP_DONE_ADDR_HI 0xc001 +#define mmCP_EOP_DONE_DATA_LO 0xc002 +#define mmCP_EOP_DONE_DATA_HI 0xc003 +#define mmCP_EOP_LAST_FENCE_LO 0xc004 +#define mmCP_EOP_LAST_FENCE_HI 0xc005 +#define mmCP_STREAM_OUT_ADDR_LO 0xc006 +#define mmCP_STREAM_OUT_ADDR_HI 0xc007 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 +#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 +#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a +#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c +#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d +#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e +#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 +#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 +#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 +#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 +#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 +#define mmCP_PIPE_STATS_ADDR_LO 0xc018 +#define mmCP_PIPE_STATS_ADDR_HI 0xc019 +#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a +#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b +#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c +#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d +#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e +#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f +#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 +#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 +#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 +#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 +#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 +#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 +#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 +#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 +#define mmCP_PA_CINVOC_COUNT_LO 0xc028 +#define mmCP_PA_CINVOC_COUNT_HI 0xc029 +#define mmCP_PA_CPRIM_COUNT_LO 0xc02a +#define mmCP_PA_CPRIM_COUNT_HI 0xc02b +#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c +#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d +#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e +#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f +#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 +#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 +#define mmCP_PIPE_STATS_CONTROL 0xc03d +#define mmCP_STREAM_OUT_CONTROL 0xc03e +#define mmCP_STRMOUT_CNTL 0xc03f +#define mmSCRATCH_REG0 0xc040 +#define mmSCRATCH_REG1 0xc041 +#define mmSCRATCH_REG2 0xc042 +#define mmSCRATCH_REG3 0xc043 +#define mmSCRATCH_REG4 0xc044 +#define mmSCRATCH_REG5 0xc045 +#define mmSCRATCH_REG6 0xc046 +#define mmSCRATCH_REG7 0xc047 +#define mmSCRATCH_UMSK 0xc050 +#define mmSCRATCH_ADDR 0xc051 +#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 +#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 +#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 +#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 +#define mmCP_APPEND_ADDR_LO 0xc058 +#define mmCP_APPEND_ADDR_HI 0xc059 +#define mmCP_APPEND_DATA 0xc05a +#define mmCP_APPEND_LAST_CS_FENCE 0xc05b +#define mmCP_APPEND_LAST_PS_FENCE 0xc05c +#define mmCP_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d +#define mmCP_ATOMIC_PREOP_HI 0xc05e +#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e +#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f +#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 +#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 +#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 +#define mmCP_ME_MC_WADDR_LO 0xc069 +#define mmCP_ME_MC_WADDR_HI 0xc06a +#define mmCP_ME_MC_WDATA_LO 0xc06b +#define mmCP_ME_MC_WDATA_HI 0xc06c +#define mmCP_ME_MC_RADDR_LO 0xc06d +#define mmCP_ME_MC_RADDR_HI 0xc06e +#define mmCP_SEM_WAIT_TIMER 0xc06f +#define mmCP_SIG_SEM_ADDR_LO 0xc070 +#define mmCP_SIG_SEM_ADDR_HI 0xc071 +#define mmCP_WAIT_SEM_ADDR_LO 0xc075 +#define mmCP_WAIT_SEM_ADDR_HI 0xc076 +#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 +#define mmCP_COHER_START_DELAY 0xc07b +#define mmCP_COHER_CNTL 0xc07c +#define mmCP_COHER_SIZE 0xc07d +#define mmCP_COHER_SIZE_HI 0xc08c +#define mmCP_COHER_BASE 0xc07e +#define mmCP_COHER_BASE_HI 0xc079 +#define mmCP_COHER_STATUS 0xc07f +#define mmCOHER_DEST_BASE_0 0xa092 +#define mmCOHER_DEST_BASE_1 0xa093 +#define mmCOHER_DEST_BASE_2 0xa07e +#define mmCOHER_DEST_BASE_3 0xa07f +#define mmCOHER_DEST_BASE_HI_0 0xa07a +#define mmCOHER_DEST_BASE_HI_1 0xa07b +#define mmCOHER_DEST_BASE_HI_2 0xa07c +#define mmCOHER_DEST_BASE_HI_3 0xa07d +#define mmCP_DMA_ME_SRC_ADDR 0xc080 +#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 +#define mmCP_DMA_ME_DST_ADDR 0xc082 +#define mmCP_DMA_ME_DST_ADDR_HI 0xc083 +#define mmCP_DMA_ME_CONTROL 0xc078 +#define mmCP_DMA_ME_COMMAND 0xc084 +#define mmCP_DMA_PFP_SRC_ADDR 0xc085 +#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 +#define mmCP_DMA_PFP_DST_ADDR 0xc087 +#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 +#define mmCP_DMA_PFP_CONTROL 0xc077 +#define mmCP_DMA_PFP_COMMAND 0xc089 +#define mmCP_DMA_CNTL 0xc08a +#define mmCP_DMA_READ_TAGS 0xc08b +#define mmCP_PFP_IB_CONTROL 0xc08d +#define mmCP_PFP_LOAD_CONTROL 0xc08e +#define mmCP_SCRATCH_INDEX 0xc08f +#define mmCP_SCRATCH_DATA 0xc090 +#define mmCP_RB_OFFSET 0xc091 +#define mmCP_IB1_OFFSET 0xc092 +#define mmCP_IB2_OFFSET 0xc093 +#define mmCP_IB1_PREAMBLE_BEGIN 0xc094 +#define mmCP_IB1_PREAMBLE_END 0xc095 +#define mmCP_IB2_PREAMBLE_BEGIN 0xc096 +#define mmCP_IB2_PREAMBLE_END 0xc097 +#define mmCP_CE_IB1_OFFSET 0xc098 +#define mmCP_CE_IB2_OFFSET 0xc099 +#define mmCP_CE_COUNTER 0xc09a +#define mmCP_CE_RB_OFFSET 0xc09b +#define mmCP_PFP_COMPLETION_STATUS 0xc0ec +#define mmCP_CE_COMPLETION_STATUS 0xc0ed +#define mmCP_PRED_NOT_VISIBLE 0xc0ee +#define mmCP_PFP_METADATA_BASE_ADDR 0xc0f0 +#define mmCP_PFP_METADATA_BASE_ADDR_HI 0xc0f1 +#define mmCP_CE_METADATA_BASE_ADDR 0xc0f2 +#define mmCP_CE_METADATA_BASE_ADDR_HI 0xc0f3 +#define mmCP_DRAW_INDX_INDR_ADDR 0xc0f4 +#define mmCP_DRAW_INDX_INDR_ADDR_HI 0xc0f5 +#define mmCP_DISPATCH_INDR_ADDR 0xc0f6 +#define mmCP_DISPATCH_INDR_ADDR_HI 0xc0f7 +#define mmCP_INDEX_BASE_ADDR 0xc0f8 +#define mmCP_INDEX_BASE_ADDR_HI 0xc0f9 +#define mmCP_INDEX_TYPE 0xc0fa +#define mmCP_GDS_BKUP_ADDR 0xc0fb +#define mmCP_GDS_BKUP_ADDR_HI 0xc0fc +#define mmCP_SAMPLE_STATUS 0xc0fd +#define mmCP_STALLED_STAT1 0x219d +#define mmCP_STALLED_STAT2 0x219e +#define mmCP_STALLED_STAT3 0x219c +#define mmCP_BUSY_STAT 0x219f +#define mmCP_STAT 0x21a0 +#define mmCP_ME_HEADER_DUMP 0x21a1 +#define mmCP_PFP_HEADER_DUMP 0x21a2 +#define mmCP_GRBM_FREE_COUNT 0x21a3 +#define mmCP_CE_HEADER_DUMP 0x21a4 +#define mmCP_CSF_STAT 0x21b4 +#define mmCP_CSF_CNTL 0x21b5 +#define mmCP_ME_CNTL 0x21b6 +#define mmCP_CNTX_STAT 0x21b8 +#define mmCP_ME_PREEMPTION 0x21b9 +#define mmCP_RB0_RPTR 0x21c0 +#define mmCP_RB_RPTR 0x21c0 +#define mmCP_RB1_RPTR 0x21bf +#define mmCP_RB2_RPTR 0x21be +#define mmCP_RB_WPTR_DELAY 0x21c1 +#define mmCP_RB_WPTR_POLL_CNTL 0x21c2 +#define mmCP_CE_INIT_BASE_LO 0xc0c3 +#define mmCP_CE_INIT_BASE_HI 0xc0c4 +#define mmCP_CE_INIT_BUFSZ 0xc0c5 +#define mmCP_CE_IB1_BASE_LO 0xc0c6 +#define mmCP_CE_IB1_BASE_HI 0xc0c7 +#define mmCP_CE_IB1_BUFSZ 0xc0c8 +#define mmCP_CE_IB2_BASE_LO 0xc0c9 +#define mmCP_CE_IB2_BASE_HI 0xc0ca +#define mmCP_CE_IB2_BUFSZ 0xc0cb +#define mmCP_IB1_BASE_LO 0xc0cc +#define mmCP_IB1_BASE_HI 0xc0cd +#define mmCP_IB1_BUFSZ 0xc0ce +#define mmCP_IB2_BASE_LO 0xc0cf +#define mmCP_IB2_BASE_HI 0xc0d0 +#define mmCP_IB2_BUFSZ 0xc0d1 +#define mmCP_ST_BASE_LO 0xc0d2 +#define mmCP_ST_BASE_HI 0xc0d3 +#define mmCP_ST_BUFSZ 0xc0d4 +#define mmCP_ROQ_THRESHOLDS 0x21bc +#define mmCP_MEQ_STQ_THRESHOLD 0x21bd +#define mmCP_ROQ1_THRESHOLDS 0x21d5 +#define mmCP_ROQ2_THRESHOLDS 0x21d6 +#define mmCP_STQ_THRESHOLDS 0x21d7 +#define mmCP_QUEUE_THRESHOLDS 0x21d8 +#define mmCP_MEQ_THRESHOLDS 0x21d9 +#define mmCP_ROQ_AVAIL 0x21da +#define mmCP_STQ_AVAIL 0x21db +#define mmCP_ROQ2_AVAIL 0x21dc +#define mmCP_MEQ_AVAIL 0x21dd +#define mmCP_CMD_INDEX 0x21de +#define mmCP_CMD_DATA 0x21df +#define mmCP_ROQ_RB_STAT 0x21e0 +#define mmCP_ROQ_IB1_STAT 0x21e1 +#define mmCP_ROQ_IB2_STAT 0x21e2 +#define mmCP_STQ_STAT 0x21e3 +#define mmCP_STQ_WR_STAT 0x21e4 +#define mmCP_MEQ_STAT 0x21e5 +#define mmCP_CEQ1_AVAIL 0x21e6 +#define mmCP_CEQ2_AVAIL 0x21e7 +#define mmCP_CE_ROQ_RB_STAT 0x21e8 +#define mmCP_CE_ROQ_IB1_STAT 0x21e9 +#define mmCP_CE_ROQ_IB2_STAT 0x21ea +#define mmCP_INT_STAT_DEBUG 0x21f7 +#define mmCP_PERFMON_CNTL 0xd808 +#define mmCP_PERFMON_CNTX_CNTL 0xa0d8 +#define mmCP_RINGID 0xa0d9 +#define mmCP_PIPEID 0xa0d9 +#define mmCP_VMID 0xa0da +#define mmCP_HPD_ROQ_OFFSETS 0x3240 +#define mmCP_HPD_STATUS0 0x3241 +#define mmCP_MQD_BASE_ADDR 0x3245 +#define mmCP_MQD_BASE_ADDR_HI 0x3246 +#define mmCP_HQD_ACTIVE 0x3247 +#define mmCP_HQD_VMID 0x3248 +#define mmCP_HQD_PERSISTENT_STATE 0x3249 +#define mmCP_HQD_PIPE_PRIORITY 0x324a +#define mmCP_HQD_QUEUE_PRIORITY 0x324b +#define mmCP_HQD_QUANTUM 0x324c +#define mmCP_HQD_PQ_BASE 0x324d +#define mmCP_HQD_PQ_BASE_HI 0x324e +#define mmCP_HQD_PQ_RPTR 0x324f +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 +#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 +#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 +#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 +#define mmCP_HQD_PQ_WPTR 0x3255 +#define mmCP_HQD_PQ_CONTROL 0x3256 +#define mmCP_HQD_IB_BASE_ADDR 0x3257 +#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 +#define mmCP_HQD_IB_RPTR 0x3259 +#define mmCP_HQD_IB_CONTROL 0x325a +#define mmCP_HQD_IQ_TIMER 0x325b +#define mmCP_HQD_IQ_RPTR 0x325c +#define mmCP_HQD_DEQUEUE_REQUEST 0x325d +#define mmCP_HQD_DMA_OFFLOAD 0x325e +#define mmCP_HQD_OFFLOAD 0x325e +#define mmCP_HQD_SEMA_CMD 0x325f +#define mmCP_HQD_MSG_TYPE 0x3260 +#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 +#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 +#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 +#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 +#define mmCP_HQD_HQ_SCHEDULER0 0x3265 +#define mmCP_HQD_HQ_STATUS0 0x3265 +#define mmCP_HQD_HQ_SCHEDULER1 0x3266 +#define mmCP_HQD_HQ_CONTROL0 0x3266 +#define mmCP_MQD_CONTROL 0x3267 +#define mmCP_HQD_HQ_STATUS1 0x3268 +#define mmCP_HQD_HQ_CONTROL1 0x3269 +#define mmCP_HQD_EOP_BASE_ADDR 0x326a +#define mmCP_HQD_EOP_BASE_ADDR_HI 0x326b +#define mmCP_HQD_EOP_CONTROL 0x326c +#define mmCP_HQD_EOP_RPTR 0x326d +#define mmCP_HQD_EOP_WPTR 0x326e +#define mmCP_HQD_EOP_EVENTS 0x326f +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_LO 0x3270 +#define mmCP_HQD_CTX_SAVE_BASE_ADDR_HI 0x3271 +#define mmCP_HQD_CTX_SAVE_CONTROL 0x3272 +#define mmCP_HQD_CNTL_STACK_OFFSET 0x3273 +#define mmCP_HQD_CNTL_STACK_SIZE 0x3274 +#define mmCP_HQD_WG_STATE_OFFSET 0x3275 +#define mmCP_HQD_CTX_SAVE_SIZE 0x3276 +#define mmCP_HQD_GDS_RESOURCE_STATE 0x3277 +#define mmCP_HQD_ERROR 0x3278 +#define mmCP_HQD_EOP_WPTR_MEM 0x3279 +#define mmCP_HQD_EOP_DONES 0x327a +#define mmDB_Z_READ_BASE 0xa012 +#define mmDB_STENCIL_READ_BASE 0xa013 +#define mmDB_Z_WRITE_BASE 0xa014 +#define mmDB_STENCIL_WRITE_BASE 0xa015 +#define mmDB_DEPTH_INFO 0xa00f +#define mmDB_Z_INFO 0xa010 +#define mmDB_STENCIL_INFO 0xa011 +#define mmDB_DEPTH_SIZE 0xa016 +#define mmDB_DEPTH_SLICE 0xa017 +#define mmDB_DEPTH_VIEW 0xa002 +#define mmDB_RENDER_CONTROL 0xa000 +#define mmDB_COUNT_CONTROL 0xa001 +#define mmDB_RENDER_OVERRIDE 0xa003 +#define mmDB_RENDER_OVERRIDE2 0xa004 +#define mmDB_EQAA 0xa201 +#define mmDB_SHADER_CONTROL 0xa203 +#define mmDB_DEPTH_BOUNDS_MIN 0xa008 +#define mmDB_DEPTH_BOUNDS_MAX 0xa009 +#define mmDB_STENCIL_CLEAR 0xa00a +#define mmDB_DEPTH_CLEAR 0xa00b +#define mmDB_HTILE_DATA_BASE 0xa005 +#define mmDB_HTILE_SURFACE 0xa2af +#define mmDB_PRELOAD_CONTROL 0xa2b2 +#define mmDB_STENCILREFMASK 0xa10c +#define mmDB_STENCILREFMASK_BF 0xa10d +#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 +#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 +#define mmDB_DEPTH_CONTROL 0xa200 +#define mmDB_STENCIL_CONTROL 0xa10b +#define mmDB_ALPHA_TO_MASK 0xa2dc +#define mmDB_PERFCOUNTER0_SELECT 0xdc40 +#define mmDB_PERFCOUNTER1_SELECT 0xdc42 +#define mmDB_PERFCOUNTER2_SELECT 0xdc44 +#define mmDB_PERFCOUNTER3_SELECT 0xdc46 +#define mmDB_PERFCOUNTER0_SELECT1 0xdc41 +#define mmDB_PERFCOUNTER1_SELECT1 0xdc43 +#define mmDB_PERFCOUNTER0_LO 0xd440 +#define mmDB_PERFCOUNTER1_LO 0xd442 +#define mmDB_PERFCOUNTER2_LO 0xd444 +#define mmDB_PERFCOUNTER3_LO 0xd446 +#define mmDB_PERFCOUNTER0_HI 0xd441 +#define mmDB_PERFCOUNTER1_HI 0xd443 +#define mmDB_PERFCOUNTER2_HI 0xd445 +#define mmDB_PERFCOUNTER3_HI 0xd447 +#define mmDB_DEBUG 0x260c +#define mmDB_DEBUG2 0x260d +#define mmDB_DEBUG3 0x260e +#define mmDB_DEBUG4 0x260f +#define mmDB_CREDIT_LIMIT 0x2614 +#define mmDB_WATERMARKS 0x2615 +#define mmDB_SUBTILE_CONTROL 0x2616 +#define mmDB_FREE_CACHELINES 0x2617 +#define mmDB_FIFO_DEPTH1 0x2618 +#define mmDB_FIFO_DEPTH2 0x2619 +#define mmDB_CGTT_CLK_CTRL_0 0xf0a4 +#define mmDB_ZPASS_COUNT_LOW 0xc3fe +#define mmDB_ZPASS_COUNT_HI 0xc3ff +#define mmDB_RING_CONTROL 0x261b +#define mmDB_READ_DEBUG_0 0x2620 +#define mmDB_READ_DEBUG_1 0x2621 +#define mmDB_READ_DEBUG_2 0x2622 +#define mmDB_READ_DEBUG_3 0x2623 +#define mmDB_READ_DEBUG_4 0x2624 +#define mmDB_READ_DEBUG_5 0x2625 +#define mmDB_READ_DEBUG_6 0x2626 +#define mmDB_READ_DEBUG_7 0x2627 +#define mmDB_READ_DEBUG_8 0x2628 +#define mmDB_READ_DEBUG_9 0x2629 +#define mmDB_READ_DEBUG_A 0x262a +#define mmDB_READ_DEBUG_B 0x262b +#define mmDB_READ_DEBUG_C 0x262c +#define mmDB_READ_DEBUG_D 0x262d +#define mmDB_READ_DEBUG_E 0x262e +#define mmDB_READ_DEBUG_F 0x262f +#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 +#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 +#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 +#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 +#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 +#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 +#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 +#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 +#define mmCC_RB_REDUNDANCY 0x263c +#define mmCC_RB_BACKEND_DISABLE 0x263d +#define mmGC_USER_RB_REDUNDANCY 0x26de +#define mmGC_USER_RB_BACKEND_DISABLE 0x26df +#define mmGB_ADDR_CONFIG 0x263e +#define mmGB_BACKEND_MAP 0x263f +#define mmGB_GPU_ID 0x2640 +#define mmCC_RB_DAISY_CHAIN 0x2641 +#define mmGB_TILE_MODE0 0x2644 +#define mmGB_TILE_MODE1 0x2645 +#define mmGB_TILE_MODE2 0x2646 +#define mmGB_TILE_MODE3 0x2647 +#define mmGB_TILE_MODE4 0x2648 +#define mmGB_TILE_MODE5 0x2649 +#define mmGB_TILE_MODE6 0x264a +#define mmGB_TILE_MODE7 0x264b +#define mmGB_TILE_MODE8 0x264c +#define mmGB_TILE_MODE9 0x264d +#define mmGB_TILE_MODE10 0x264e +#define mmGB_TILE_MODE11 0x264f +#define mmGB_TILE_MODE12 0x2650 +#define mmGB_TILE_MODE13 0x2651 +#define mmGB_TILE_MODE14 0x2652 +#define mmGB_TILE_MODE15 0x2653 +#define mmGB_TILE_MODE16 0x2654 +#define mmGB_TILE_MODE17 0x2655 +#define mmGB_TILE_MODE18 0x2656 +#define mmGB_TILE_MODE19 0x2657 +#define mmGB_TILE_MODE20 0x2658 +#define mmGB_TILE_MODE21 0x2659 +#define mmGB_TILE_MODE22 0x265a +#define mmGB_TILE_MODE23 0x265b +#define mmGB_TILE_MODE24 0x265c +#define mmGB_TILE_MODE25 0x265d +#define mmGB_TILE_MODE26 0x265e +#define mmGB_TILE_MODE27 0x265f +#define mmGB_TILE_MODE28 0x2660 +#define mmGB_TILE_MODE29 0x2661 +#define mmGB_TILE_MODE30 0x2662 +#define mmGB_TILE_MODE31 0x2663 +#define mmGB_MACROTILE_MODE0 0x2664 +#define mmGB_MACROTILE_MODE1 0x2665 +#define mmGB_MACROTILE_MODE2 0x2666 +#define mmGB_MACROTILE_MODE3 0x2667 +#define mmGB_MACROTILE_MODE4 0x2668 +#define mmGB_MACROTILE_MODE5 0x2669 +#define mmGB_MACROTILE_MODE6 0x266a +#define mmGB_MACROTILE_MODE7 0x266b +#define mmGB_MACROTILE_MODE8 0x266c +#define mmGB_MACROTILE_MODE9 0x266d +#define mmGB_MACROTILE_MODE10 0x266e +#define mmGB_MACROTILE_MODE11 0x266f +#define mmGB_MACROTILE_MODE12 0x2670 +#define mmGB_MACROTILE_MODE13 0x2671 +#define mmGB_MACROTILE_MODE14 0x2672 +#define mmGB_MACROTILE_MODE15 0x2673 +#define mmGB_EDC_MODE 0x307e +#define mmCC_GC_EDC_CONFIG 0x3098 +#define mmRAS_SIGNATURE_CONTROL 0x3380 +#define mmRAS_SIGNATURE_MASK 0x3381 +#define mmRAS_SX_SIGNATURE0 0x3382 +#define mmRAS_SX_SIGNATURE1 0x3383 +#define mmRAS_SX_SIGNATURE2 0x3384 +#define mmRAS_SX_SIGNATURE3 0x3385 +#define mmRAS_DB_SIGNATURE0 0x338b +#define mmRAS_PA_SIGNATURE0 0x338c +#define mmRAS_VGT_SIGNATURE0 0x338d +#define mmRAS_SC_SIGNATURE0 0x338f +#define mmRAS_SC_SIGNATURE1 0x3390 +#define mmRAS_SC_SIGNATURE2 0x3391 +#define mmRAS_SC_SIGNATURE3 0x3392 +#define mmRAS_SC_SIGNATURE4 0x3393 +#define mmRAS_SC_SIGNATURE5 0x3394 +#define mmRAS_SC_SIGNATURE6 0x3395 +#define mmRAS_SC_SIGNATURE7 0x3396 +#define mmRAS_IA_SIGNATURE0 0x3397 +#define mmRAS_IA_SIGNATURE1 0x3398 +#define mmRAS_SPI_SIGNATURE0 0x3399 +#define mmRAS_SPI_SIGNATURE1 0x339a +#define mmRAS_TA_SIGNATURE0 0x339b +#define mmRAS_TD_SIGNATURE0 0x339c +#define mmRAS_CB_SIGNATURE0 0x339d +#define mmRAS_BCI_SIGNATURE0 0x339e +#define mmRAS_BCI_SIGNATURE1 0x339f +#define mmRAS_TA_SIGNATURE1 0x33a0 +#define mmGRBM_HYP_CAM_INDEX 0xf83e +#define mmGRBM_CAM_INDEX 0xf83e +#define mmGRBM_HYP_CAM_DATA 0xf83f +#define mmGRBM_CAM_DATA 0xf83f +#define mmGRBM_CNTL 0x2000 +#define mmGRBM_SKEW_CNTL 0x2001 +#define mmGRBM_PWR_CNTL 0x2003 +#define mmGRBM_STATUS 0x2004 +#define mmGRBM_STATUS2 0x2002 +#define mmGRBM_STATUS_SE0 0x2005 +#define mmGRBM_STATUS_SE1 0x2006 +#define mmGRBM_STATUS_SE2 0x200e +#define mmGRBM_STATUS_SE3 0x200f +#define mmGRBM_SOFT_RESET 0x2008 +#define mmGRBM_DEBUG_CNTL 0x2009 +#define mmGRBM_DEBUG_DATA 0x200a +#define mmGRBM_CGTT_CLK_CNTL 0x200b +#define mmGRBM_GFX_INDEX 0xc200 +#define mmGRBM_GFX_CLKEN_CNTL 0x200c +#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d +#define mmGRBM_DEBUG 0x2014 +#define mmGRBM_DEBUG_SNAPSHOT 0x2015 +#define mmGRBM_READ_ERROR 0x2016 +#define mmGRBM_READ_ERROR2 0x2017 +#define mmGRBM_INT_CNTL 0x2018 +#define mmGRBM_TRAP_OP 0x2019 +#define mmGRBM_TRAP_ADDR 0x201a +#define mmGRBM_TRAP_ADDR_MSK 0x201b +#define mmGRBM_TRAP_WD 0x201c +#define mmGRBM_TRAP_WD_MSK 0x201d +#define mmGRBM_DSM_BYPASS 0x201e +#define mmGRBM_WRITE_ERROR 0x201f +#define mmGRBM_PERFCOUNTER0_SELECT 0xd840 +#define mmGRBM_PERFCOUNTER1_SELECT 0xd841 +#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 +#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 +#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 +#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 +#define mmGRBM_PERFCOUNTER0_LO 0xd040 +#define mmGRBM_PERFCOUNTER0_HI 0xd041 +#define mmGRBM_PERFCOUNTER1_LO 0xd043 +#define mmGRBM_PERFCOUNTER1_HI 0xd044 +#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 +#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 +#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 +#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 +#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 +#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a +#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b +#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c +#define mmGRBM_SCRATCH_REG0 0x2040 +#define mmGRBM_SCRATCH_REG1 0x2041 +#define mmGRBM_SCRATCH_REG2 0x2042 +#define mmGRBM_SCRATCH_REG3 0x2043 +#define mmGRBM_SCRATCH_REG4 0x2044 +#define mmGRBM_SCRATCH_REG5 0x2045 +#define mmGRBM_SCRATCH_REG6 0x2046 +#define mmGRBM_SCRATCH_REG7 0x2047 +#define mmDEBUG_INDEX 0x203c +#define mmDEBUG_DATA 0x203d +#define mmGRBM_NOWHERE 0x203f +#define mmPA_CL_VPORT_XSCALE 0xa10f +#define mmPA_CL_VPORT_XOFFSET 0xa110 +#define mmPA_CL_VPORT_YSCALE 0xa111 +#define mmPA_CL_VPORT_YOFFSET 0xa112 +#define mmPA_CL_VPORT_ZSCALE 0xa113 +#define mmPA_CL_VPORT_ZOFFSET 0xa114 +#define mmPA_CL_VPORT_XSCALE_1 0xa115 +#define mmPA_CL_VPORT_XSCALE_2 0xa11b +#define mmPA_CL_VPORT_XSCALE_3 0xa121 +#define mmPA_CL_VPORT_XSCALE_4 0xa127 +#define mmPA_CL_VPORT_XSCALE_5 0xa12d +#define mmPA_CL_VPORT_XSCALE_6 0xa133 +#define mmPA_CL_VPORT_XSCALE_7 0xa139 +#define mmPA_CL_VPORT_XSCALE_8 0xa13f +#define mmPA_CL_VPORT_XSCALE_9 0xa145 +#define mmPA_CL_VPORT_XSCALE_10 0xa14b +#define mmPA_CL_VPORT_XSCALE_11 0xa151 +#define mmPA_CL_VPORT_XSCALE_12 0xa157 +#define mmPA_CL_VPORT_XSCALE_13 0xa15d +#define mmPA_CL_VPORT_XSCALE_14 0xa163 +#define mmPA_CL_VPORT_XSCALE_15 0xa169 +#define mmPA_CL_VPORT_XOFFSET_1 0xa116 +#define mmPA_CL_VPORT_XOFFSET_2 0xa11c +#define mmPA_CL_VPORT_XOFFSET_3 0xa122 +#define mmPA_CL_VPORT_XOFFSET_4 0xa128 +#define mmPA_CL_VPORT_XOFFSET_5 0xa12e +#define mmPA_CL_VPORT_XOFFSET_6 0xa134 +#define mmPA_CL_VPORT_XOFFSET_7 0xa13a +#define mmPA_CL_VPORT_XOFFSET_8 0xa140 +#define mmPA_CL_VPORT_XOFFSET_9 0xa146 +#define mmPA_CL_VPORT_XOFFSET_10 0xa14c +#define mmPA_CL_VPORT_XOFFSET_11 0xa152 +#define mmPA_CL_VPORT_XOFFSET_12 0xa158 +#define mmPA_CL_VPORT_XOFFSET_13 0xa15e +#define mmPA_CL_VPORT_XOFFSET_14 0xa164 +#define mmPA_CL_VPORT_XOFFSET_15 0xa16a +#define mmPA_CL_VPORT_YSCALE_1 0xa117 +#define mmPA_CL_VPORT_YSCALE_2 0xa11d +#define mmPA_CL_VPORT_YSCALE_3 0xa123 +#define mmPA_CL_VPORT_YSCALE_4 0xa129 +#define mmPA_CL_VPORT_YSCALE_5 0xa12f +#define mmPA_CL_VPORT_YSCALE_6 0xa135 +#define mmPA_CL_VPORT_YSCALE_7 0xa13b +#define mmPA_CL_VPORT_YSCALE_8 0xa141 +#define mmPA_CL_VPORT_YSCALE_9 0xa147 +#define mmPA_CL_VPORT_YSCALE_10 0xa14d +#define mmPA_CL_VPORT_YSCALE_11 0xa153 +#define mmPA_CL_VPORT_YSCALE_12 0xa159 +#define mmPA_CL_VPORT_YSCALE_13 0xa15f +#define mmPA_CL_VPORT_YSCALE_14 0xa165 +#define mmPA_CL_VPORT_YSCALE_15 0xa16b +#define mmPA_CL_VPORT_YOFFSET_1 0xa118 +#define mmPA_CL_VPORT_YOFFSET_2 0xa11e +#define mmPA_CL_VPORT_YOFFSET_3 0xa124 +#define mmPA_CL_VPORT_YOFFSET_4 0xa12a +#define mmPA_CL_VPORT_YOFFSET_5 0xa130 +#define mmPA_CL_VPORT_YOFFSET_6 0xa136 +#define mmPA_CL_VPORT_YOFFSET_7 0xa13c +#define mmPA_CL_VPORT_YOFFSET_8 0xa142 +#define mmPA_CL_VPORT_YOFFSET_9 0xa148 +#define mmPA_CL_VPORT_YOFFSET_10 0xa14e +#define mmPA_CL_VPORT_YOFFSET_11 0xa154 +#define mmPA_CL_VPORT_YOFFSET_12 0xa15a +#define mmPA_CL_VPORT_YOFFSET_13 0xa160 +#define mmPA_CL_VPORT_YOFFSET_14 0xa166 +#define mmPA_CL_VPORT_YOFFSET_15 0xa16c +#define mmPA_CL_VPORT_ZSCALE_1 0xa119 +#define mmPA_CL_VPORT_ZSCALE_2 0xa11f +#define mmPA_CL_VPORT_ZSCALE_3 0xa125 +#define mmPA_CL_VPORT_ZSCALE_4 0xa12b +#define mmPA_CL_VPORT_ZSCALE_5 0xa131 +#define mmPA_CL_VPORT_ZSCALE_6 0xa137 +#define mmPA_CL_VPORT_ZSCALE_7 0xa13d +#define mmPA_CL_VPORT_ZSCALE_8 0xa143 +#define mmPA_CL_VPORT_ZSCALE_9 0xa149 +#define mmPA_CL_VPORT_ZSCALE_10 0xa14f +#define mmPA_CL_VPORT_ZSCALE_11 0xa155 +#define mmPA_CL_VPORT_ZSCALE_12 0xa15b +#define mmPA_CL_VPORT_ZSCALE_13 0xa161 +#define mmPA_CL_VPORT_ZSCALE_14 0xa167 +#define mmPA_CL_VPORT_ZSCALE_15 0xa16d +#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a +#define mmPA_CL_VPORT_ZOFFSET_2 0xa120 +#define mmPA_CL_VPORT_ZOFFSET_3 0xa126 +#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c +#define mmPA_CL_VPORT_ZOFFSET_5 0xa132 +#define mmPA_CL_VPORT_ZOFFSET_6 0xa138 +#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e +#define mmPA_CL_VPORT_ZOFFSET_8 0xa144 +#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a +#define mmPA_CL_VPORT_ZOFFSET_10 0xa150 +#define mmPA_CL_VPORT_ZOFFSET_11 0xa156 +#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c +#define mmPA_CL_VPORT_ZOFFSET_13 0xa162 +#define mmPA_CL_VPORT_ZOFFSET_14 0xa168 +#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e +#define mmPA_CL_VTE_CNTL 0xa206 +#define mmPA_CL_VS_OUT_CNTL 0xa207 +#define mmPA_CL_NANINF_CNTL 0xa208 +#define mmPA_CL_CLIP_CNTL 0xa204 +#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa +#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb +#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc +#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd +#define mmPA_CL_UCP_0_X 0xa16f +#define mmPA_CL_UCP_0_Y 0xa170 +#define mmPA_CL_UCP_0_Z 0xa171 +#define mmPA_CL_UCP_0_W 0xa172 +#define mmPA_CL_UCP_1_X 0xa173 +#define mmPA_CL_UCP_1_Y 0xa174 +#define mmPA_CL_UCP_1_Z 0xa175 +#define mmPA_CL_UCP_1_W 0xa176 +#define mmPA_CL_UCP_2_X 0xa177 +#define mmPA_CL_UCP_2_Y 0xa178 +#define mmPA_CL_UCP_2_Z 0xa179 +#define mmPA_CL_UCP_2_W 0xa17a +#define mmPA_CL_UCP_3_X 0xa17b +#define mmPA_CL_UCP_3_Y 0xa17c +#define mmPA_CL_UCP_3_Z 0xa17d +#define mmPA_CL_UCP_3_W 0xa17e +#define mmPA_CL_UCP_4_X 0xa17f +#define mmPA_CL_UCP_4_Y 0xa180 +#define mmPA_CL_UCP_4_Z 0xa181 +#define mmPA_CL_UCP_4_W 0xa182 +#define mmPA_CL_UCP_5_X 0xa183 +#define mmPA_CL_UCP_5_Y 0xa184 +#define mmPA_CL_UCP_5_Z 0xa185 +#define mmPA_CL_UCP_5_W 0xa186 +#define mmPA_CL_POINT_X_RAD 0xa1f5 +#define mmPA_CL_POINT_Y_RAD 0xa1f6 +#define mmPA_CL_POINT_SIZE 0xa1f7 +#define mmPA_CL_POINT_CULL_RAD 0xa1f8 +#define mmPA_CL_ENHANCE 0x2285 +#define mmPA_CL_RESET_DEBUG 0x2286 +#define mmPA_SU_VTX_CNTL 0xa2f9 +#define mmPA_SU_POINT_SIZE 0xa280 +#define mmPA_SU_POINT_MINMAX 0xa281 +#define mmPA_SU_LINE_CNTL 0xa282 +#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 +#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a +#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b +#define mmPA_SU_SC_MODE_CNTL 0xa205 +#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de +#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df +#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 +#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 +#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 +#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 +#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d +#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 +#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 +#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 +#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 +#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 +#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 +#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 +#define mmPA_SU_PERFCOUNTER0_LO 0xd100 +#define mmPA_SU_PERFCOUNTER0_HI 0xd101 +#define mmPA_SU_PERFCOUNTER1_LO 0xd102 +#define mmPA_SU_PERFCOUNTER1_HI 0xd103 +#define mmPA_SU_PERFCOUNTER2_LO 0xd104 +#define mmPA_SU_PERFCOUNTER2_HI 0xd105 +#define mmPA_SU_PERFCOUNTER3_LO 0xd106 +#define mmPA_SU_PERFCOUNTER3_HI 0xd107 +#define mmPA_SC_AA_CONFIG 0xa2f8 +#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e +#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f +#define mmPA_SC_SHADER_CONTROL 0xa310 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c +#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d +#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 +#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 +#define mmPA_SC_CLIPRECT_0_TL 0xa084 +#define mmPA_SC_CLIPRECT_0_BR 0xa085 +#define mmPA_SC_CLIPRECT_1_TL 0xa086 +#define mmPA_SC_CLIPRECT_1_BR 0xa087 +#define mmPA_SC_CLIPRECT_2_TL 0xa088 +#define mmPA_SC_CLIPRECT_2_BR 0xa089 +#define mmPA_SC_CLIPRECT_3_TL 0xa08a +#define mmPA_SC_CLIPRECT_3_BR 0xa08b +#define mmPA_SC_CLIPRECT_RULE 0xa083 +#define mmPA_SC_EDGERULE 0xa08c +#define mmPA_SC_LINE_CNTL 0xa2f7 +#define mmPA_SC_LINE_STIPPLE 0xa283 +#define mmPA_SC_MODE_CNTL_0 0xa292 +#define mmPA_SC_MODE_CNTL_1 0xa293 +#define mmPA_SC_RASTER_CONFIG 0xa0d4 +#define mmPA_SC_RASTER_CONFIG_1 0xa0d5 +#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 +#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 +#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 +#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c +#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d +#define mmPA_SC_WINDOW_OFFSET 0xa080 +#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 +#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 +#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 +#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 +#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 +#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a +#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c +#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e +#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 +#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 +#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 +#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 +#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 +#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa +#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac +#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae +#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 +#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 +#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 +#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 +#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 +#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b +#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d +#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f +#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 +#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 +#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 +#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 +#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 +#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab +#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad +#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af +#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 +#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 +#define mmPA_SC_VPORT_ZMIN_0 0xa0b4 +#define mmPA_SC_VPORT_ZMIN_1 0xa0b6 +#define mmPA_SC_VPORT_ZMIN_2 0xa0b8 +#define mmPA_SC_VPORT_ZMIN_3 0xa0ba +#define mmPA_SC_VPORT_ZMIN_4 0xa0bc +#define mmPA_SC_VPORT_ZMIN_5 0xa0be +#define mmPA_SC_VPORT_ZMIN_6 0xa0c0 +#define mmPA_SC_VPORT_ZMIN_7 0xa0c2 +#define mmPA_SC_VPORT_ZMIN_8 0xa0c4 +#define mmPA_SC_VPORT_ZMIN_9 0xa0c6 +#define mmPA_SC_VPORT_ZMIN_10 0xa0c8 +#define mmPA_SC_VPORT_ZMIN_11 0xa0ca +#define mmPA_SC_VPORT_ZMIN_12 0xa0cc +#define mmPA_SC_VPORT_ZMIN_13 0xa0ce +#define mmPA_SC_VPORT_ZMIN_14 0xa0d0 +#define mmPA_SC_VPORT_ZMIN_15 0xa0d2 +#define mmPA_SC_VPORT_ZMAX_0 0xa0b5 +#define mmPA_SC_VPORT_ZMAX_1 0xa0b7 +#define mmPA_SC_VPORT_ZMAX_2 0xa0b9 +#define mmPA_SC_VPORT_ZMAX_3 0xa0bb +#define mmPA_SC_VPORT_ZMAX_4 0xa0bd +#define mmPA_SC_VPORT_ZMAX_5 0xa0bf +#define mmPA_SC_VPORT_ZMAX_6 0xa0c1 +#define mmPA_SC_VPORT_ZMAX_7 0xa0c3 +#define mmPA_SC_VPORT_ZMAX_8 0xa0c5 +#define mmPA_SC_VPORT_ZMAX_9 0xa0c7 +#define mmPA_SC_VPORT_ZMAX_10 0xa0c9 +#define mmPA_SC_VPORT_ZMAX_11 0xa0cb +#define mmPA_SC_VPORT_ZMAX_12 0xa0cd +#define mmPA_SC_VPORT_ZMAX_13 0xa0cf +#define mmPA_SC_VPORT_ZMAX_14 0xa0d1 +#define mmPA_SC_VPORT_ZMAX_15 0xa0d3 +#define mmPA_SC_ENHANCE 0x22fc +#define mmPA_SC_ENHANCE_1 0x22fd +#define mmPA_SC_DSM_CNTL 0x22fe +#define mmPA_SC_FIFO_SIZE 0x22f3 +#define mmPA_SC_IF_FIFO_SIZE 0x22f5 +#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 +#define mmPA_SC_LINE_STIPPLE_STATE 0xc281 +#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 +#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 +#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 +#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b +#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 +#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 +#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 +#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 +#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 +#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 +#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 +#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 +#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 +#define mmPA_SC_PERFCOUNTER0_LO 0xd140 +#define mmPA_SC_PERFCOUNTER0_HI 0xd141 +#define mmPA_SC_PERFCOUNTER1_LO 0xd142 +#define mmPA_SC_PERFCOUNTER1_HI 0xd143 +#define mmPA_SC_PERFCOUNTER2_LO 0xd144 +#define mmPA_SC_PERFCOUNTER2_HI 0xd145 +#define mmPA_SC_PERFCOUNTER3_LO 0xd146 +#define mmPA_SC_PERFCOUNTER3_HI 0xd147 +#define mmPA_SC_PERFCOUNTER4_LO 0xd148 +#define mmPA_SC_PERFCOUNTER4_HI 0xd149 +#define mmPA_SC_PERFCOUNTER5_LO 0xd14a +#define mmPA_SC_PERFCOUNTER5_HI 0xd14b +#define mmPA_SC_PERFCOUNTER6_LO 0xd14c +#define mmPA_SC_PERFCOUNTER6_HI 0xd14d +#define mmPA_SC_PERFCOUNTER7_LO 0xd14e +#define mmPA_SC_PERFCOUNTER7_HI 0xd14f +#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 +#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 +#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 +#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 +#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 +#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 +#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa +#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab +#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac +#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 +#define mmPA_SC_TRAP_SCREEN_H 0xc2b1 +#define mmPA_SC_TRAP_SCREEN_V 0xc2b2 +#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 +#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 +#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 +#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 +#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 +#define mmPA_CL_CNTL_STATUS 0x2284 +#define mmPA_SU_CNTL_STATUS 0x2294 +#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 +#define mmCGTT_PA_CLK_CTRL 0xf088 +#define mmCGTT_SC_CLK_CTRL 0xf089 +#define mmPA_SU_DEBUG_CNTL 0x2280 +#define mmPA_SU_DEBUG_DATA 0x2281 +#define mmPA_SC_DEBUG_CNTL 0x22f6 +#define mmPA_SC_DEBUG_DATA 0x22f7 +#define ixCLIPPER_DEBUG_REG00 0x0 +#define ixCLIPPER_DEBUG_REG01 0x1 +#define ixCLIPPER_DEBUG_REG02 0x2 +#define ixCLIPPER_DEBUG_REG03 0x3 +#define ixCLIPPER_DEBUG_REG04 0x4 +#define ixCLIPPER_DEBUG_REG05 0x5 +#define ixCLIPPER_DEBUG_REG06 0x6 +#define ixCLIPPER_DEBUG_REG07 0x7 +#define ixCLIPPER_DEBUG_REG08 0x8 +#define ixCLIPPER_DEBUG_REG09 0x9 +#define ixCLIPPER_DEBUG_REG10 0xa +#define ixCLIPPER_DEBUG_REG11 0xb +#define ixCLIPPER_DEBUG_REG12 0xc +#define ixCLIPPER_DEBUG_REG13 0xd +#define ixCLIPPER_DEBUG_REG14 0xe +#define ixCLIPPER_DEBUG_REG15 0xf +#define ixCLIPPER_DEBUG_REG16 0x10 +#define ixCLIPPER_DEBUG_REG17 0x11 +#define ixCLIPPER_DEBUG_REG18 0x12 +#define ixCLIPPER_DEBUG_REG19 0x13 +#define ixSXIFCCG_DEBUG_REG0 0x14 +#define ixSXIFCCG_DEBUG_REG1 0x15 +#define ixSXIFCCG_DEBUG_REG2 0x16 +#define ixSXIFCCG_DEBUG_REG3 0x17 +#define ixSETUP_DEBUG_REG0 0x18 +#define ixSETUP_DEBUG_REG1 0x19 +#define ixSETUP_DEBUG_REG2 0x1a +#define ixSETUP_DEBUG_REG3 0x1b +#define ixSETUP_DEBUG_REG4 0x1c +#define ixSETUP_DEBUG_REG5 0x1d +#define ixPA_SC_DEBUG_REG0 0x0 +#define ixPA_SC_DEBUG_REG1 0x1 +#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 +#define mmCOMPUTE_DIM_X 0x2e01 +#define mmCOMPUTE_DIM_Y 0x2e02 +#define mmCOMPUTE_DIM_Z 0x2e03 +#define mmCOMPUTE_START_X 0x2e04 +#define mmCOMPUTE_START_Y 0x2e05 +#define mmCOMPUTE_START_Z 0x2e06 +#define mmCOMPUTE_NUM_THREAD_X 0x2e07 +#define mmCOMPUTE_NUM_THREAD_Y 0x2e08 +#define mmCOMPUTE_NUM_THREAD_Z 0x2e09 +#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a +#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b +#define mmCOMPUTE_PGM_LO 0x2e0c +#define mmCOMPUTE_PGM_HI 0x2e0d +#define mmCOMPUTE_TBA_LO 0x2e0e +#define mmCOMPUTE_TBA_HI 0x2e0f +#define mmCOMPUTE_TMA_LO 0x2e10 +#define mmCOMPUTE_TMA_HI 0x2e11 +#define mmCOMPUTE_PGM_RSRC1 0x2e12 +#define mmCOMPUTE_PGM_RSRC2 0x2e13 +#define mmCOMPUTE_VMID 0x2e14 +#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 +#define mmCOMPUTE_TMPRING_SIZE 0x2e18 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 +#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a +#define mmCOMPUTE_RESTART_X 0x2e1b +#define mmCOMPUTE_RESTART_Y 0x2e1c +#define mmCOMPUTE_RESTART_Z 0x2e1d +#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e +#define mmCOMPUTE_MISC_RESERVED 0x2e1f +#define mmCOMPUTE_DISPATCH_ID 0x2e20 +#define mmCOMPUTE_THREADGROUP_ID 0x2e21 +#define mmCOMPUTE_RELAUNCH 0x2e22 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_LO 0x2e23 +#define mmCOMPUTE_WAVE_RESTORE_ADDR_HI 0x2e24 +#define mmCOMPUTE_WAVE_RESTORE_CONTROL 0x2e25 +#define mmCOMPUTE_USER_DATA_0 0x2e40 +#define mmCOMPUTE_USER_DATA_1 0x2e41 +#define mmCOMPUTE_USER_DATA_2 0x2e42 +#define mmCOMPUTE_USER_DATA_3 0x2e43 +#define mmCOMPUTE_USER_DATA_4 0x2e44 +#define mmCOMPUTE_USER_DATA_5 0x2e45 +#define mmCOMPUTE_USER_DATA_6 0x2e46 +#define mmCOMPUTE_USER_DATA_7 0x2e47 +#define mmCOMPUTE_USER_DATA_8 0x2e48 +#define mmCOMPUTE_USER_DATA_9 0x2e49 +#define mmCOMPUTE_USER_DATA_10 0x2e4a +#define mmCOMPUTE_USER_DATA_11 0x2e4b +#define mmCOMPUTE_USER_DATA_12 0x2e4c +#define mmCOMPUTE_USER_DATA_13 0x2e4d +#define mmCOMPUTE_USER_DATA_14 0x2e4e +#define mmCOMPUTE_USER_DATA_15 0x2e4f +#define mmCOMPUTE_NOWHERE 0x2e7f +#define mmCSPRIV_CONNECT 0x0 +#define mmCSPRIV_THREAD_TRACE_TG0 0x1e +#define mmCSPRIV_THREAD_TRACE_TG1 0x1e +#define mmCSPRIV_THREAD_TRACE_TG2 0x1e +#define mmCSPRIV_THREAD_TRACE_TG3 0x1e +#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f +#define mmRLC_CNTL 0xec00 +#define mmRLC_DEBUG_SELECT 0xec01 +#define mmRLC_DEBUG 0xec02 +#define mmRLC_MC_CNTL 0xec03 +#define mmRLC_STAT 0xec04 +#define mmRLC_SAFE_MODE 0xec05 +#define mmRLC_MEM_SLP_CNTL 0xec06 +#define mmSMU_RLC_RESPONSE 0xec07 +#define mmRLC_RLCV_SAFE_MODE 0xec08 +#define mmRLC_SMU_SAFE_MODE 0xec09 +#define mmRLC_RLCV_COMMAND 0xec0a +#define mmRLC_CLK_CNTL 0xec0b +#define mmRLC_PERFMON_CLK_CNTL 0xdcbf +#define mmRLC_PERFMON_CNTL 0xdcc0 +#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 +#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 +#define mmRLC_PERFCOUNTER0_LO 0xd480 +#define mmRLC_PERFCOUNTER1_LO 0xd482 +#define mmRLC_PERFCOUNTER0_HI 0xd481 +#define mmRLC_PERFCOUNTER1_HI 0xd483 +#define mmCGTT_RLC_CLK_CTRL 0xf0b8 +#define mmRLC_LB_CNTL 0xec19 +#define mmRLC_LB_CNTR_MAX 0xec12 +#define mmRLC_LB_CNTR_INIT 0xec1b +#define mmRLC_LOAD_BALANCE_CNTR 0xec1c +#define mmRLC_JUMP_TABLE_RESTORE 0xec1e +#define mmRLC_PG_DELAY_2 0xec1f +#define mmRLC_GPM_DEBUG_SELECT 0xec20 +#define mmRLC_GPM_DEBUG 0xec21 +#define mmRLC_GPM_DEBUG_INST_A 0xec22 +#define mmRLC_GPM_DEBUG_INST_B 0xec23 +#define mmRLC_GPM_DEBUG_INST_ADDR 0xec1d +#define mmRLC_GPM_UCODE_ADDR 0xf83c +#define mmRLC_GPM_UCODE_DATA 0xf83d +#define mmGPU_BIST_CONTROL 0xf835 +#define mmRLC_ROM_CNTL 0xf836 +#define mmRLC_GPU_CLOCK_COUNT_LSB 0xec24 +#define mmRLC_GPU_CLOCK_COUNT_MSB 0xec25 +#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0xec26 +#define mmRLC_UCODE_CNTL 0xec27 +#define mmRLC_GPM_STAT 0xec40 +#define mmRLC_GPU_CLOCK_32_RES_SEL 0xec41 +#define mmRLC_GPU_CLOCK_32 0xec42 +#define mmRLC_PG_CNTL 0xec43 +#define mmRLC_GPM_THREAD_PRIORITY 0xec44 +#define mmRLC_GPM_THREAD_ENABLE 0xec45 +#define mmRLC_GPM_VMID_THREAD0 0xec46 +#define mmRLC_GPM_VMID_THREAD1 0xec47 +#define mmRLC_CGTT_MGCG_OVERRIDE 0xec48 +#define mmRLC_CGCG_CGLS_CTRL 0xec49 +#define mmRLC_CGCG_RAMP_CTRL 0xec4a +#define mmRLC_DYN_PG_STATUS 0xec4b +#define mmRLC_DYN_PG_REQUEST 0xec4c +#define mmRLC_PG_DELAY 0xec4d +#define mmRLC_CU_STATUS 0xec4e +#define mmRLC_LB_INIT_CU_MASK 0xec4f +#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0xec50 +#define mmRLC_LB_PARAMS 0xec51 +#define mmRLC_THREAD1_DELAY 0xec52 +#define mmRLC_PG_ALWAYS_ON_CU_MASK 0xec53 +#define mmRLC_MAX_PG_CU 0xec54 +#define mmRLC_AUTO_PG_CTRL 0xec55 +#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0xec56 +#define mmRLC_SERDES_RD_MASTER_INDEX 0xec59 +#define mmRLC_SERDES_RD_DATA_0 0xec5a +#define mmRLC_SERDES_RD_DATA_1 0xec5b +#define mmRLC_SERDES_RD_DATA_2 0xec5c +#define mmRLC_SERDES_WR_CU_MASTER_MASK 0xec5d +#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0xec5e +#define mmRLC_SERDES_WR_CTRL 0xec5f +#define mmRLC_SERDES_WR_DATA 0xec60 +#define mmRLC_SERDES_CU_MASTER_BUSY 0xec61 +#define mmRLC_SERDES_NONCU_MASTER_BUSY 0xec62 +#define mmRLC_GPM_GENERAL_0 0xec63 +#define mmRLC_GPM_GENERAL_1 0xec64 +#define mmRLC_GPM_GENERAL_2 0xec65 +#define mmRLC_GPM_GENERAL_3 0xec66 +#define mmRLC_GPM_GENERAL_4 0xec67 +#define mmRLC_GPM_GENERAL_5 0xec68 +#define mmRLC_GPM_GENERAL_6 0xec69 +#define mmRLC_GPM_GENERAL_7 0xec6a +#define mmRLC_GPM_SCRATCH_ADDR 0xec6c +#define mmRLC_GPM_SCRATCH_DATA 0xec6d +#define mmRLC_STATIC_PG_STATUS 0xec6e +#define mmRLC_GPM_PERF_COUNT_0 0xec6f +#define mmRLC_GPM_PERF_COUNT_1 0xec70 +#define mmRLC_GPR_REG1 0xec79 +#define mmRLC_GPR_REG2 0xec7a +#define mmRLC_MGCG_CTRL 0xec1a +#define mmRLC_GPM_THREAD_RESET 0xec28 +#define mmRLC_SPM_VMID 0xec71 +#define mmRLC_SPM_INT_CNTL 0xec72 +#define mmRLC_SPM_INT_STATUS 0xec73 +#define mmRLC_SPM_DEBUG_SELECT 0xec74 +#define mmRLC_SPM_DEBUG 0xec75 +#define mmRLC_SMU_MESSAGE 0xec76 +#define mmRLC_GPM_LOG_SIZE 0xec77 +#define mmRLC_GPM_LOG_CONT 0xec7b +#define mmRLC_PG_DELAY_3 0xec78 +#define mmRLC_GPM_INT_DISABLE_TH0 0xec7c +#define mmRLC_GPM_INT_DISABLE_TH1 0xec7d +#define mmRLC_GPM_INT_FORCE_TH0 0xec7e +#define mmRLC_GPM_INT_FORCE_TH1 0xec7f +#define mmRLC_SRM_CNTL 0xec80 +#define mmRLC_SRM_DEBUG_SELECT 0xec81 +#define mmRLC_SRM_DEBUG 0xec82 +#define mmRLC_SRM_ARAM_ADDR 0xec83 +#define mmRLC_SRM_ARAM_DATA 0xec84 +#define mmRLC_SRM_DRAM_ADDR 0xec85 +#define mmRLC_SRM_DRAM_DATA 0xec86 +#define mmRLC_SRM_GPM_COMMAND 0xec87 +#define mmRLC_SRM_GPM_COMMAND_STATUS 0xec88 +#define mmRLC_SRM_RLCV_COMMAND 0xec89 +#define mmRLC_SRM_RLCV_COMMAND_STATUS 0xec8a +#define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b +#define mmRLC_SRM_INDEX_CNTL_ADDR_1 0xec8c +#define mmRLC_SRM_INDEX_CNTL_ADDR_2 0xec8d +#define mmRLC_SRM_INDEX_CNTL_ADDR_3 0xec8e +#define mmRLC_SRM_INDEX_CNTL_ADDR_4 0xec8f +#define mmRLC_SRM_INDEX_CNTL_ADDR_5 0xec90 +#define mmRLC_SRM_INDEX_CNTL_ADDR_6 0xec91 +#define mmRLC_SRM_INDEX_CNTL_ADDR_7 0xec92 +#define mmRLC_SRM_INDEX_CNTL_DATA_0 0xec93 +#define mmRLC_SRM_INDEX_CNTL_DATA_1 0xec94 +#define mmRLC_SRM_INDEX_CNTL_DATA_2 0xec95 +#define mmRLC_SRM_INDEX_CNTL_DATA_3 0xec96 +#define mmRLC_SRM_INDEX_CNTL_DATA_4 0xec97 +#define mmRLC_SRM_INDEX_CNTL_DATA_5 0xec98 +#define mmRLC_SRM_INDEX_CNTL_DATA_6 0xec99 +#define mmRLC_SRM_INDEX_CNTL_DATA_7 0xec9a +#define mmRLC_SRM_STAT 0xec9b +#define mmRLC_SRM_GPM_ABORT 0xec9c +#define mmRLC_CSIB_ADDR_LO 0xeca2 +#define mmRLC_CSIB_ADDR_HI 0xeca3 +#define mmRLC_CSIB_LENGTH 0xeca4 +#define mmRLC_CP_RESPONSE0 0xeca5 +#define mmRLC_CP_RESPONSE1 0xeca6 +#define mmRLC_CP_RESPONSE2 0xeca7 +#define mmRLC_CP_RESPONSE3 0xeca8 +#define mmRLC_SMU_COMMAND 0xeca9 +#define mmRLC_CP_SCHEDULERS 0xecaa +#define mmRLC_SMU_ARGUMENT_1 0xecab +#define mmRLC_SMU_ARGUMENT_2 0xecac +#define mmRLC_GPM_GENERAL_8 0xecad +#define mmRLC_GPM_GENERAL_9 0xecae +#define mmRLC_GPM_GENERAL_10 0xecaf +#define mmRLC_GPM_GENERAL_11 0xecb0 +#define mmRLC_GPM_GENERAL_12 0xecb1 +#define mmRLC_SPM_PERFMON_CNTL 0xdc80 +#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 +#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 +#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 +#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 +#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 +#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 +#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 +#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 +#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 +#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a +#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b +#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c +#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d +#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e +#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 +#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 +#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 +#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 +#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 +#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 +#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 +#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 +#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 +#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a +#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b +#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c +#define mmRLC_SPM_RING_RDPTR 0xdc9d +#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e +#define mmRLC_GPU_IOV_VF_ENABLE 0xfb00 +#define mmRLC_GPU_IOV_RLC_RESPONSE 0xfb4d +#define mmRLC_GPU_IOV_ACTIVE_FCN_ID 0xfb40 +#define mmSPI_PS_INPUT_CNTL_0 0xa191 +#define mmSPI_PS_INPUT_CNTL_1 0xa192 +#define mmSPI_PS_INPUT_CNTL_2 0xa193 +#define mmSPI_PS_INPUT_CNTL_3 0xa194 +#define mmSPI_PS_INPUT_CNTL_4 0xa195 +#define mmSPI_PS_INPUT_CNTL_5 0xa196 +#define mmSPI_PS_INPUT_CNTL_6 0xa197 +#define mmSPI_PS_INPUT_CNTL_7 0xa198 +#define mmSPI_PS_INPUT_CNTL_8 0xa199 +#define mmSPI_PS_INPUT_CNTL_9 0xa19a +#define mmSPI_PS_INPUT_CNTL_10 0xa19b +#define mmSPI_PS_INPUT_CNTL_11 0xa19c +#define mmSPI_PS_INPUT_CNTL_12 0xa19d +#define mmSPI_PS_INPUT_CNTL_13 0xa19e +#define mmSPI_PS_INPUT_CNTL_14 0xa19f +#define mmSPI_PS_INPUT_CNTL_15 0xa1a0 +#define mmSPI_PS_INPUT_CNTL_16 0xa1a1 +#define mmSPI_PS_INPUT_CNTL_17 0xa1a2 +#define mmSPI_PS_INPUT_CNTL_18 0xa1a3 +#define mmSPI_PS_INPUT_CNTL_19 0xa1a4 +#define mmSPI_PS_INPUT_CNTL_20 0xa1a5 +#define mmSPI_PS_INPUT_CNTL_21 0xa1a6 +#define mmSPI_PS_INPUT_CNTL_22 0xa1a7 +#define mmSPI_PS_INPUT_CNTL_23 0xa1a8 +#define mmSPI_PS_INPUT_CNTL_24 0xa1a9 +#define mmSPI_PS_INPUT_CNTL_25 0xa1aa +#define mmSPI_PS_INPUT_CNTL_26 0xa1ab +#define mmSPI_PS_INPUT_CNTL_27 0xa1ac +#define mmSPI_PS_INPUT_CNTL_28 0xa1ad +#define mmSPI_PS_INPUT_CNTL_29 0xa1ae +#define mmSPI_PS_INPUT_CNTL_30 0xa1af +#define mmSPI_PS_INPUT_CNTL_31 0xa1b0 +#define mmSPI_VS_OUT_CONFIG 0xa1b1 +#define mmSPI_PS_INPUT_ENA 0xa1b3 +#define mmSPI_PS_INPUT_ADDR 0xa1b4 +#define mmSPI_INTERP_CONTROL_0 0xa1b5 +#define mmSPI_PS_IN_CONTROL 0xa1b6 +#define mmSPI_BARYC_CNTL 0xa1b8 +#define mmSPI_TMPRING_SIZE 0xa1ba +#define mmSPI_SHADER_POS_FORMAT 0xa1c3 +#define mmSPI_SHADER_Z_FORMAT 0xa1c4 +#define mmSPI_SHADER_COL_FORMAT 0xa1c5 +#define mmSPI_ARB_PRIORITY 0x31c0 +#define mmSPI_ARB_CYCLES_0 0x31c1 +#define mmSPI_ARB_CYCLES_1 0x31c2 +#define mmSPI_CDBG_SYS_GFX 0x31c3 +#define mmSPI_CDBG_SYS_HP3D 0x31c4 +#define mmSPI_CDBG_SYS_CS0 0x31c5 +#define mmSPI_CDBG_SYS_CS1 0x31c6 +#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 +#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 +#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 +#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca +#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb +#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc +#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd +#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce +#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf +#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 +#define mmSPI_GDBG_WAVE_CNTL 0x31d1 +#define mmSPI_GDBG_TRAP_CONFIG 0x31d2 +#define mmSPI_GDBG_TRAP_MASK 0x31d3 +#define mmSPI_GDBG_TBA_LO 0x31d4 +#define mmSPI_GDBG_TBA_HI 0x31d5 +#define mmSPI_GDBG_TMA_LO 0x31d6 +#define mmSPI_GDBG_TMA_HI 0x31d7 +#define mmSPI_GDBG_TRAP_DATA0 0x31d8 +#define mmSPI_GDBG_TRAP_DATA1 0x31d9 +#define mmSPI_RESET_DEBUG 0x31da +#define mmSPI_COMPUTE_QUEUE_RESET 0x31db +#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc +#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd +#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de +#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df +#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 +#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 +#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 +#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 +#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 +#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 +#define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0 +#define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1 +#define mmSPI_RESOURCE_RESERVE_CU_12 0x31f4 +#define mmSPI_RESOURCE_RESERVE_CU_13 0x31f5 +#define mmSPI_RESOURCE_RESERVE_CU_14 0x31f6 +#define mmSPI_RESOURCE_RESERVE_CU_15 0x31f7 +#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 +#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 +#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea +#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb +#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec +#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed +#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee +#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef +#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2 +#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3 +#define mmSPI_RESOURCE_RESERVE_EN_CU_12 0x31f8 +#define mmSPI_RESOURCE_RESERVE_EN_CU_13 0x31f9 +#define mmSPI_RESOURCE_RESERVE_EN_CU_14 0x31fa +#define mmSPI_RESOURCE_RESERVE_EN_CU_15 0x31fb +#define mmSPI_COMPUTE_WF_CTX_SAVE 0x31fc +#define mmSPI_PS_MAX_WAVE_ID 0x243a +#define mmSPI_START_PHASE 0x243b +#define mmSPI_GFX_CNTL 0x243c +#define mmSPI_CONFIG_CNTL 0x2440 +#define mmSPI_DEBUG_CNTL 0x2441 +#define mmSPI_DEBUG_READ 0x2442 +#define mmSPI_DSM_CNTL 0x2443 +#define mmSPI_EDC_CNT 0x2444 +#define mmSPI_PERFCOUNTER0_SELECT 0xd980 +#define mmSPI_PERFCOUNTER1_SELECT 0xd981 +#define mmSPI_PERFCOUNTER2_SELECT 0xd982 +#define mmSPI_PERFCOUNTER3_SELECT 0xd983 +#define mmSPI_PERFCOUNTER0_SELECT1 0xd984 +#define mmSPI_PERFCOUNTER1_SELECT1 0xd985 +#define mmSPI_PERFCOUNTER2_SELECT1 0xd986 +#define mmSPI_PERFCOUNTER3_SELECT1 0xd987 +#define mmSPI_PERFCOUNTER4_SELECT 0xd988 +#define mmSPI_PERFCOUNTER5_SELECT 0xd989 +#define mmSPI_PERFCOUNTER_BINS 0xd98a +#define mmSPI_PERFCOUNTER0_HI 0xd180 +#define mmSPI_PERFCOUNTER0_LO 0xd181 +#define mmSPI_PERFCOUNTER1_HI 0xd182 +#define mmSPI_PERFCOUNTER1_LO 0xd183 +#define mmSPI_PERFCOUNTER2_HI 0xd184 +#define mmSPI_PERFCOUNTER2_LO 0xd185 +#define mmSPI_PERFCOUNTER3_HI 0xd186 +#define mmSPI_PERFCOUNTER3_LO 0xd187 +#define mmSPI_PERFCOUNTER4_HI 0xd188 +#define mmSPI_PERFCOUNTER4_LO 0xd189 +#define mmSPI_PERFCOUNTER5_HI 0xd18a +#define mmSPI_PERFCOUNTER5_LO 0xd18b +#define mmSPI_CONFIG_CNTL_1 0x244f +#define mmSPI_DEBUG_BUSY 0x2450 +#define mmSPI_CONFIG_CNTL_2 0x2451 +#define mmCGTS_SM_CTRL_REG 0xf000 +#define mmCGTS_RD_CTRL_REG 0xf001 +#define mmCGTS_RD_REG 0xf002 +#define mmCGTS_TCC_DISABLE 0xf003 +#define mmCGTS_USER_TCC_DISABLE 0xf004 +#define mmCGTS_CU0_SP0_CTRL_REG 0xf008 +#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 +#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a +#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b +#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c +#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d +#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e +#define mmCGTS_CU1_TA_CTRL_REG 0xf00f +#define mmCGTS_CU1_SP1_CTRL_REG 0xf010 +#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 +#define mmCGTS_CU2_SP0_CTRL_REG 0xf012 +#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 +#define mmCGTS_CU2_TA_CTRL_REG 0xf014 +#define mmCGTS_CU2_SP1_CTRL_REG 0xf015 +#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 +#define mmCGTS_CU3_SP0_CTRL_REG 0xf017 +#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 +#define mmCGTS_CU3_TA_CTRL_REG 0xf019 +#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a +#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b +#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c +#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d +#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e +#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f +#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 +#define mmCGTS_CU5_SP0_CTRL_REG 0xf021 +#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 +#define mmCGTS_CU5_TA_CTRL_REG 0xf023 +#define mmCGTS_CU5_SP1_CTRL_REG 0xf024 +#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 +#define mmCGTS_CU6_SP0_CTRL_REG 0xf026 +#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 +#define mmCGTS_CU6_TA_CTRL_REG 0xf028 +#define mmCGTS_CU6_SP1_CTRL_REG 0xf029 +#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a +#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b +#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c +#define mmCGTS_CU7_TA_CTRL_REG 0xf02d +#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e +#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f +#define mmCGTS_CU8_SP0_CTRL_REG 0xf030 +#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 +#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 +#define mmCGTS_CU8_SP1_CTRL_REG 0xf033 +#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 +#define mmCGTS_CU9_SP0_CTRL_REG 0xf035 +#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 +#define mmCGTS_CU9_TA_CTRL_REG 0xf037 +#define mmCGTS_CU9_SP1_CTRL_REG 0xf038 +#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 +#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a +#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b +#define mmCGTS_CU10_TA_CTRL_REG 0xf03c +#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d +#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e +#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f +#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 +#define mmCGTS_CU11_TA_CTRL_REG 0xf041 +#define mmCGTS_CU11_SP1_CTRL_REG 0xf042 +#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 +#define mmCGTS_CU12_SP0_CTRL_REG 0xf044 +#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 +#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 +#define mmCGTS_CU12_SP1_CTRL_REG 0xf047 +#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 +#define mmCGTS_CU13_SP0_CTRL_REG 0xf049 +#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a +#define mmCGTS_CU13_TA_CTRL_REG 0xf04b +#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c +#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d +#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e +#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f +#define mmCGTS_CU14_TA_CTRL_REG 0xf050 +#define mmCGTS_CU14_SP1_CTRL_REG 0xf051 +#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 +#define mmCGTS_CU15_SP0_CTRL_REG 0xf053 +#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 +#define mmCGTS_CU15_TA_CTRL_REG 0xf055 +#define mmCGTS_CU15_SP1_CTRL_REG 0xf056 +#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 +#define mmCGTT_SPI_CLK_CTRL 0xf080 +#define mmCGTT_PC_CLK_CTRL 0xf081 +#define mmCGTT_BCI_CLK_CTRL 0xf082 +#define mmSPI_WF_LIFETIME_CNTL 0x24aa +#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab +#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac +#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad +#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae +#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af +#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 +#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 +#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 +#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 +#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 +#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 +#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 +#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 +#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 +#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 +#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba +#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb +#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc +#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd +#define mmSPI_WF_LIFETIME_STATUS_9 0x24be +#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf +#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 +#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 +#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 +#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 +#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 +#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 +#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 +#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 +#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 +#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 +#define mmSPI_WF_LIFETIME_DEBUG 0x24ca +#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 +#define mmSPI_LB_CTR_CTRL 0x24d4 +#define mmSPI_LB_CU_MASK 0x24d5 +#define mmSPI_LB_DATA_REG 0x24d6 +#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 +#define mmSPI_GDS_CREDITS 0x24d8 +#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 +#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da +#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db +#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc +#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd +#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de +#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df +#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 +#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 +#define mmBCI_DEBUG_READ 0x24eb +#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec +#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed +#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee +#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef +#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 +#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 +#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 +#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 +#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 +#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 +#define mmSPI_SHADER_TBA_LO_PS 0x2c00 +#define mmSPI_SHADER_TBA_HI_PS 0x2c01 +#define mmSPI_SHADER_TMA_LO_PS 0x2c02 +#define mmSPI_SHADER_TMA_HI_PS 0x2c03 +#define mmSPI_SHADER_PGM_LO_PS 0x2c08 +#define mmSPI_SHADER_PGM_HI_PS 0x2c09 +#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a +#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b +#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 +#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c +#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d +#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e +#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f +#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 +#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 +#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 +#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 +#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 +#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 +#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 +#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 +#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 +#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 +#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a +#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b +#define mmSPI_SHADER_TBA_LO_VS 0x2c40 +#define mmSPI_SHADER_TBA_HI_VS 0x2c41 +#define mmSPI_SHADER_TMA_LO_VS 0x2c42 +#define mmSPI_SHADER_TMA_HI_VS 0x2c43 +#define mmSPI_SHADER_PGM_LO_VS 0x2c48 +#define mmSPI_SHADER_PGM_HI_VS 0x2c49 +#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a +#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b +#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 +#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 +#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c +#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d +#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e +#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f +#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 +#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 +#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 +#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 +#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 +#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 +#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 +#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 +#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 +#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 +#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a +#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b +#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c +#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d +#define mmSPI_SHADER_TBA_LO_GS 0x2c80 +#define mmSPI_SHADER_TBA_HI_GS 0x2c81 +#define mmSPI_SHADER_TMA_LO_GS 0x2c82 +#define mmSPI_SHADER_TMA_HI_GS 0x2c83 +#define mmSPI_SHADER_PGM_LO_GS 0x2c88 +#define mmSPI_SHADER_PGM_HI_GS 0x2c89 +#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a +#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b +#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 +#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c +#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d +#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e +#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f +#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 +#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 +#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 +#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 +#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 +#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 +#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 +#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 +#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 +#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 +#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a +#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b +#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc +#define mmSPI_SHADER_TBA_LO_ES 0x2cc0 +#define mmSPI_SHADER_TBA_HI_ES 0x2cc1 +#define mmSPI_SHADER_TMA_LO_ES 0x2cc2 +#define mmSPI_SHADER_TMA_HI_ES 0x2cc3 +#define mmSPI_SHADER_PGM_LO_ES 0x2cc8 +#define mmSPI_SHADER_PGM_HI_ES 0x2cc9 +#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca +#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb +#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 +#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc +#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd +#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce +#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf +#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 +#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 +#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 +#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 +#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 +#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 +#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 +#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 +#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 +#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 +#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda +#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb +#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd +#define mmSPI_SHADER_TBA_LO_HS 0x2d00 +#define mmSPI_SHADER_TBA_HI_HS 0x2d01 +#define mmSPI_SHADER_TMA_LO_HS 0x2d02 +#define mmSPI_SHADER_TMA_HI_HS 0x2d03 +#define mmSPI_SHADER_PGM_LO_HS 0x2d08 +#define mmSPI_SHADER_PGM_HI_HS 0x2d09 +#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a +#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b +#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 +#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c +#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d +#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e +#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f +#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 +#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 +#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 +#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 +#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 +#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 +#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 +#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 +#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 +#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 +#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a +#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b +#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d +#define mmSPI_SHADER_TBA_LO_LS 0x2d40 +#define mmSPI_SHADER_TBA_HI_LS 0x2d41 +#define mmSPI_SHADER_TMA_LO_LS 0x2d42 +#define mmSPI_SHADER_TMA_HI_LS 0x2d43 +#define mmSPI_SHADER_PGM_LO_LS 0x2d48 +#define mmSPI_SHADER_PGM_HI_LS 0x2d49 +#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a +#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b +#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 +#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c +#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d +#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e +#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f +#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 +#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 +#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 +#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 +#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 +#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 +#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 +#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 +#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 +#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 +#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a +#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b +#define mmSQ_CONFIG 0x2300 +#define mmSQC_CONFIG 0x2301 +#define mmSQC_CACHES 0xc348 +#define mmSQC_WRITEBACK 0xc349 +#define mmSQC_DSM_CNTL 0x230f +#define mmSQ_RANDOM_WAVE_PRI 0x2303 +#define mmSQ_REG_CREDITS 0x2304 +#define mmSQ_FIFO_SIZES 0x2305 +#define mmSQ_DSM_CNTL 0x2306 +#define mmCC_GC_SHADER_RATE_CONFIG 0x2312 +#define mmGC_USER_SHADER_RATE_CONFIG 0x2313 +#define mmSQ_INTERRUPT_AUTO_MASK 0x2314 +#define mmSQ_INTERRUPT_MSG_CTRL 0x2315 +#define mmSQ_PERFCOUNTER_CTRL 0xd9e0 +#define mmSQ_PERFCOUNTER_MASK 0xd9e1 +#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 +#define mmCC_SQC_BANK_DISABLE 0x2307 +#define mmUSER_SQC_BANK_DISABLE 0x2308 +#define mmSQ_PERFCOUNTER0_LO 0xd1c0 +#define mmSQ_PERFCOUNTER1_LO 0xd1c2 +#define mmSQ_PERFCOUNTER2_LO 0xd1c4 +#define mmSQ_PERFCOUNTER3_LO 0xd1c6 +#define mmSQ_PERFCOUNTER4_LO 0xd1c8 +#define mmSQ_PERFCOUNTER5_LO 0xd1ca +#define mmSQ_PERFCOUNTER6_LO 0xd1cc +#define mmSQ_PERFCOUNTER7_LO 0xd1ce +#define mmSQ_PERFCOUNTER8_LO 0xd1d0 +#define mmSQ_PERFCOUNTER9_LO 0xd1d2 +#define mmSQ_PERFCOUNTER10_LO 0xd1d4 +#define mmSQ_PERFCOUNTER11_LO 0xd1d6 +#define mmSQ_PERFCOUNTER12_LO 0xd1d8 +#define mmSQ_PERFCOUNTER13_LO 0xd1da +#define mmSQ_PERFCOUNTER14_LO 0xd1dc +#define mmSQ_PERFCOUNTER15_LO 0xd1de +#define mmSQ_PERFCOUNTER0_HI 0xd1c1 +#define mmSQ_PERFCOUNTER1_HI 0xd1c3 +#define mmSQ_PERFCOUNTER2_HI 0xd1c5 +#define mmSQ_PERFCOUNTER3_HI 0xd1c7 +#define mmSQ_PERFCOUNTER4_HI 0xd1c9 +#define mmSQ_PERFCOUNTER5_HI 0xd1cb +#define mmSQ_PERFCOUNTER6_HI 0xd1cd +#define mmSQ_PERFCOUNTER7_HI 0xd1cf +#define mmSQ_PERFCOUNTER8_HI 0xd1d1 +#define mmSQ_PERFCOUNTER9_HI 0xd1d3 +#define mmSQ_PERFCOUNTER10_HI 0xd1d5 +#define mmSQ_PERFCOUNTER11_HI 0xd1d7 +#define mmSQ_PERFCOUNTER12_HI 0xd1d9 +#define mmSQ_PERFCOUNTER13_HI 0xd1db +#define mmSQ_PERFCOUNTER14_HI 0xd1dd +#define mmSQ_PERFCOUNTER15_HI 0xd1df +#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 +#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 +#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 +#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 +#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 +#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 +#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 +#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 +#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 +#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 +#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca +#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb +#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc +#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd +#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce +#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf +#define mmCGTT_SQ_CLK_CTRL 0xf08c +#define mmCGTT_SQG_CLK_CTRL 0xf08d +#define mmSQ_ALU_CLK_CTRL 0xf08e +#define mmSQ_TEX_CLK_CTRL 0xf08f +#define mmSQ_LDS_CLK_CTRL 0xf090 +#define mmSQ_POWER_THROTTLE 0xf091 +#define mmSQ_POWER_THROTTLE2 0xf092 +#define mmSQ_TIME_HI 0x237c +#define mmSQ_TIME_LO 0x237d +#define mmSQ_THREAD_TRACE_BASE 0xc330 +#define mmSQ_THREAD_TRACE_BASE2 0xc337 +#define mmSQ_THREAD_TRACE_SIZE 0xc331 +#define mmSQ_THREAD_TRACE_MASK 0xc332 +#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 +#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 +#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 +#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 +#define mmSQ_THREAD_TRACE_MODE 0xc336 +#define mmSQ_THREAD_TRACE_CTRL 0xc335 +#define mmSQ_THREAD_TRACE_TOKEN_MASK 0xc333 +#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0xc338 +#define mmSQ_THREAD_TRACE_PERF_MASK 0xc334 +#define mmSQ_THREAD_TRACE_WPTR 0xc339 +#define mmSQ_THREAD_TRACE_STATUS 0xc33a +#define mmSQ_THREAD_TRACE_CNTR 0x2390 +#define mmSQ_THREAD_TRACE_HIWATER 0xc33b +#define mmSQ_LB_CTR_CTRL 0x2398 +#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 +#define mmSQ_LB_DATA_TEX_CYCLES 0x239a +#define mmSQ_LB_DATA_ALU_STALLS 0x239b +#define mmSQ_LB_DATA_TEX_STALLS 0x239c +#define mmSQC_EDC_CNT 0x23a0 +#define mmSQ_EDC_SEC_CNT 0x23a1 +#define mmSQ_EDC_DED_CNT 0x23a2 +#define mmSQ_EDC_INFO 0x23a3 +#define mmSQ_BUF_RSRC_WORD0 0x23c0 +#define mmSQ_BUF_RSRC_WORD1 0x23c1 +#define mmSQ_BUF_RSRC_WORD2 0x23c2 +#define mmSQ_BUF_RSRC_WORD3 0x23c3 +#define mmSQ_IMG_RSRC_WORD0 0x23c4 +#define mmSQ_IMG_RSRC_WORD1 0x23c5 +#define mmSQ_IMG_RSRC_WORD2 0x23c6 +#define mmSQ_IMG_RSRC_WORD3 0x23c7 +#define mmSQ_IMG_RSRC_WORD4 0x23c8 +#define mmSQ_IMG_RSRC_WORD5 0x23c9 +#define mmSQ_IMG_RSRC_WORD6 0x23ca +#define mmSQ_IMG_RSRC_WORD7 0x23cb +#define mmSQ_IMG_SAMP_WORD0 0x23cc +#define mmSQ_IMG_SAMP_WORD1 0x23cd +#define mmSQ_IMG_SAMP_WORD2 0x23ce +#define mmSQ_IMG_SAMP_WORD3 0x23cf +#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 +#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 +#define mmSQ_M0_GPR_IDX_WORD 0x23d2 +#define mmSQ_IND_INDEX 0x2378 +#define mmSQ_CMD 0x237b +#define mmSQ_IND_DATA 0x2379 +#define mmSQ_REG_TIMESTAMP 0x2374 +#define mmSQ_CMD_TIMESTAMP 0x2375 +#define mmSQ_HV_VMID_CTRL 0xf840 +#define ixSQ_WAVE_INST_DW0 0x1a +#define ixSQ_WAVE_INST_DW1 0x1b +#define ixSQ_WAVE_PC_LO 0x18 +#define ixSQ_WAVE_PC_HI 0x19 +#define ixSQ_WAVE_IB_DBG0 0x1c +#define ixSQ_WAVE_IB_DBG1 0x1d +#define ixSQ_WAVE_EXEC_LO 0x27e +#define ixSQ_WAVE_EXEC_HI 0x27f +#define ixSQ_WAVE_STATUS 0x12 +#define ixSQ_WAVE_MODE 0x11 +#define ixSQ_WAVE_TRAPSTS 0x13 +#define ixSQ_WAVE_HW_ID 0x14 +#define ixSQ_WAVE_GPR_ALLOC 0x15 +#define ixSQ_WAVE_LDS_ALLOC 0x16 +#define ixSQ_WAVE_IB_STS 0x17 +#define ixSQ_WAVE_M0 0x27c +#define ixSQ_WAVE_TBA_LO 0x26c +#define ixSQ_WAVE_TBA_HI 0x26d +#define ixSQ_WAVE_TMA_LO 0x26e +#define ixSQ_WAVE_TMA_HI 0x26f +#define ixSQ_WAVE_TTMP0 0x270 +#define ixSQ_WAVE_TTMP1 0x271 +#define ixSQ_WAVE_TTMP2 0x272 +#define ixSQ_WAVE_TTMP3 0x273 +#define ixSQ_WAVE_TTMP4 0x274 +#define ixSQ_WAVE_TTMP5 0x275 +#define ixSQ_WAVE_TTMP6 0x276 +#define ixSQ_WAVE_TTMP7 0x277 +#define ixSQ_WAVE_TTMP8 0x278 +#define ixSQ_WAVE_TTMP9 0x279 +#define ixSQ_WAVE_TTMP10 0x27a +#define ixSQ_WAVE_TTMP11 0x27b +#define mmSQ_DEBUG_STS_GLOBAL 0x2309 +#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 +#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 +#define ixSQ_DEBUG_STS_LOCAL 0x8 +#define ixSQ_DEBUG_CTRL_LOCAL 0x9 +#define mmSH_MEM_BASES 0x230a +#define mmSH_MEM_APE1_BASE 0x230b +#define mmSH_MEM_APE1_LIMIT 0x230c +#define mmSH_MEM_CONFIG 0x230d +#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 +#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 +#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 +#define mmSQ_WREXEC_EXEC_LO 0x23b1 +#define mmSQ_WREXEC_EXEC_HI 0x23b1 +#define mmSQC_GATCL1_CNTL 0x23b2 +#define mmSQC_ATC_EDC_GATCL1_CNT 0x23b3 +#define ixSQ_INTERRUPT_WORD_CMN 0x20c0 +#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 +#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 +#define mmSQ_SOP2 0x237f +#define mmSQ_VOP1 0x237f +#define mmSQ_MTBUF_1 0x237f +#define mmSQ_EXP_1 0x237f +#define mmSQ_MUBUF_1 0x237f +#define mmSQ_SMEM_1 0x237f +#define mmSQ_INST 0x237f +#define mmSQ_EXP_0 0x237f +#define mmSQ_MUBUF_0 0x237f +#define mmSQ_VOP_SDWA 0x237f +#define mmSQ_VOP3_0 0x237f +#define mmSQ_VOP2 0x237f +#define mmSQ_MTBUF_0 0x237f +#define mmSQ_SOPP 0x237f +#define mmSQ_FLAT_0 0x237f +#define mmSQ_VOP3_0_SDST_ENC 0x237f +#define mmSQ_MIMG_1 0x237f +#define mmSQ_SOP1 0x237f +#define mmSQ_SOPC 0x237f +#define mmSQ_FLAT_1 0x237f +#define mmSQ_DS_1 0x237f +#define mmSQ_VOP3_1 0x237f +#define mmSQ_SMEM_0 0x237f +#define mmSQ_MIMG_0 0x237f +#define mmSQ_SOPK 0x237f +#define mmSQ_DS_0 0x237f +#define mmSQ_VOP_DPP 0x237f +#define mmSQ_VOPC 0x237f +#define mmSQ_VINTRP 0x237f +#define mmCGTT_SX_CLK_CTRL0 0xf094 +#define mmCGTT_SX_CLK_CTRL1 0xf095 +#define mmCGTT_SX_CLK_CTRL2 0xf096 +#define mmCGTT_SX_CLK_CTRL3 0xf097 +#define mmCGTT_SX_CLK_CTRL4 0xf098 +#define mmSX_DEBUG_BUSY 0x2414 +#define mmSX_DEBUG_BUSY_2 0x2415 +#define mmSX_DEBUG_BUSY_3 0x2416 +#define mmSX_DEBUG_BUSY_4 0x2417 +#define mmSX_DEBUG_1 0x2418 +#define mmSX_PERFCOUNTER0_SELECT 0xda40 +#define mmSX_PERFCOUNTER1_SELECT 0xda41 +#define mmSX_PERFCOUNTER2_SELECT 0xda42 +#define mmSX_PERFCOUNTER3_SELECT 0xda43 +#define mmSX_PERFCOUNTER0_SELECT1 0xda44 +#define mmSX_PERFCOUNTER1_SELECT1 0xda45 +#define mmSX_PERFCOUNTER0_LO 0xd240 +#define mmSX_PERFCOUNTER0_HI 0xd241 +#define mmSX_PERFCOUNTER1_LO 0xd242 +#define mmSX_PERFCOUNTER1_HI 0xd243 +#define mmSX_PERFCOUNTER2_LO 0xd244 +#define mmSX_PERFCOUNTER2_HI 0xd245 +#define mmSX_PERFCOUNTER3_LO 0xd246 +#define mmSX_PERFCOUNTER3_HI 0xd247 +#define mmSX_PS_DOWNCONVERT 0xa1d5 +#define mmSX_BLEND_OPT_EPSILON 0xa1d6 +#define mmSX_BLEND_OPT_CONTROL 0xa1d7 +#define mmSX_MRT0_BLEND_OPT 0xa1d8 +#define mmSX_MRT1_BLEND_OPT 0xa1d9 +#define mmSX_MRT2_BLEND_OPT 0xa1da +#define mmSX_MRT3_BLEND_OPT 0xa1db +#define mmSX_MRT4_BLEND_OPT 0xa1dc +#define mmSX_MRT5_BLEND_OPT 0xa1dd +#define mmSX_MRT6_BLEND_OPT 0xa1de +#define mmSX_MRT7_BLEND_OPT 0xa1df +#define mmTCC_CTRL 0x2b80 +#define mmTCC_EDC_CNT 0x2b82 +#define mmTCC_REDUNDANCY 0x2b83 +#define mmTCC_EXE_DISABLE 0x2b84 +#define mmTCC_DSM_CNTL 0x2b85 +#define mmTCC_CGTT_SCLK_CTRL 0xf0ac +#define mmTCA_CGTT_SCLK_CTRL 0xf0ad +#define mmTCC_PERFCOUNTER0_SELECT 0xdb80 +#define mmTCC_PERFCOUNTER1_SELECT 0xdb82 +#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 +#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 +#define mmTCC_PERFCOUNTER2_SELECT 0xdb84 +#define mmTCC_PERFCOUNTER3_SELECT 0xdb85 +#define mmTCC_PERFCOUNTER0_LO 0xd380 +#define mmTCC_PERFCOUNTER1_LO 0xd382 +#define mmTCC_PERFCOUNTER2_LO 0xd384 +#define mmTCC_PERFCOUNTER3_LO 0xd386 +#define mmTCC_PERFCOUNTER0_HI 0xd381 +#define mmTCC_PERFCOUNTER1_HI 0xd383 +#define mmTCC_PERFCOUNTER2_HI 0xd385 +#define mmTCC_PERFCOUNTER3_HI 0xd387 +#define mmTCA_CTRL 0x2bc0 +#define mmTCA_PERFCOUNTER0_SELECT 0xdb90 +#define mmTCA_PERFCOUNTER1_SELECT 0xdb92 +#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 +#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 +#define mmTCA_PERFCOUNTER2_SELECT 0xdb94 +#define mmTCA_PERFCOUNTER3_SELECT 0xdb95 +#define mmTCA_PERFCOUNTER0_LO 0xd390 +#define mmTCA_PERFCOUNTER1_LO 0xd392 +#define mmTCA_PERFCOUNTER2_LO 0xd394 +#define mmTCA_PERFCOUNTER3_LO 0xd396 +#define mmTCA_PERFCOUNTER0_HI 0xd391 +#define mmTCA_PERFCOUNTER1_HI 0xd393 +#define mmTCA_PERFCOUNTER2_HI 0xd395 +#define mmTCA_PERFCOUNTER3_HI 0xd397 +#define mmTA_BC_BASE_ADDR 0xa020 +#define mmTA_BC_BASE_ADDR_HI 0xa021 +#define mmTD_CNTL 0x2525 +#define mmTD_STATUS 0x2526 +#define mmTD_DEBUG_INDEX 0x2528 +#define mmTD_DEBUG_DATA 0x2529 +#define mmTD_DSM_CNTL 0x252f +#define mmTD_PERFCOUNTER0_SELECT 0xdb00 +#define mmTD_PERFCOUNTER1_SELECT 0xdb02 +#define mmTD_PERFCOUNTER0_SELECT1 0xdb01 +#define mmTD_PERFCOUNTER0_LO 0xd300 +#define mmTD_PERFCOUNTER1_LO 0xd302 +#define mmTD_PERFCOUNTER0_HI 0xd301 +#define mmTD_PERFCOUNTER1_HI 0xd303 +#define mmTD_SCRATCH 0x2533 +#define mmTA_CNTL 0x2541 +#define mmTA_CNTL_AUX 0x2542 +#define mmTA_RESERVED_010C 0x2543 +#define mmTA_CS_BC_BASE_ADDR 0xc380 +#define mmTA_CS_BC_BASE_ADDR_HI 0xc381 +#define mmTA_STATUS 0x2548 +#define mmTA_DEBUG_INDEX 0x254c +#define mmTA_DEBUG_DATA 0x254d +#define mmTA_PERFCOUNTER0_SELECT 0xdac0 +#define mmTA_PERFCOUNTER1_SELECT 0xdac2 +#define mmTA_PERFCOUNTER0_SELECT1 0xdac1 +#define mmTA_PERFCOUNTER0_LO 0xd2c0 +#define mmTA_PERFCOUNTER1_LO 0xd2c2 +#define mmTA_PERFCOUNTER0_HI 0xd2c1 +#define mmTA_PERFCOUNTER1_HI 0xd2c3 +#define mmTA_SCRATCH 0x2564 +#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 +#define mmSH_STATIC_MEM_CONFIG 0x2581 +#define mmTCP_INVALIDATE 0x2b00 +#define mmTCP_STATUS 0x2b01 +#define mmTCP_CNTL 0x2b02 +#define mmTCP_CHAN_STEER_LO 0x2b03 +#define mmTCP_CHAN_STEER_HI 0x2b04 +#define mmTCP_ADDR_CONFIG 0x2b05 +#define mmTCP_CREDIT 0x2b06 +#define mmTCP_PERFCOUNTER0_SELECT 0xdb40 +#define mmTCP_PERFCOUNTER1_SELECT 0xdb42 +#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 +#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 +#define mmTCP_PERFCOUNTER2_SELECT 0xdb44 +#define mmTCP_PERFCOUNTER3_SELECT 0xdb45 +#define mmTCP_PERFCOUNTER0_LO 0xd340 +#define mmTCP_PERFCOUNTER1_LO 0xd342 +#define mmTCP_PERFCOUNTER2_LO 0xd344 +#define mmTCP_PERFCOUNTER3_LO 0xd346 +#define mmTCP_PERFCOUNTER0_HI 0xd341 +#define mmTCP_PERFCOUNTER1_HI 0xd343 +#define mmTCP_PERFCOUNTER2_HI 0xd345 +#define mmTCP_PERFCOUNTER3_HI 0xd347 +#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 +#define mmTCP_EDC_CNT 0x2b17 +#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a +#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b +#define mmTC_CFG_L1_STORE_POLICY 0x2b1c +#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d +#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e +#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f +#define mmTC_CFG_L2_STORE_POLICY1 0x2b20 +#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 +#define mmTC_CFG_L1_VOLATILE 0x2b22 +#define mmTC_CFG_L2_VOLATILE 0x2b23 +#define mmTCP_WATCH0_ADDR_H 0x32a0 +#define mmTCP_WATCH1_ADDR_H 0x32a3 +#define mmTCP_WATCH2_ADDR_H 0x32a6 +#define mmTCP_WATCH3_ADDR_H 0x32a9 +#define mmTCP_WATCH0_ADDR_L 0x32a1 +#define mmTCP_WATCH1_ADDR_L 0x32a4 +#define mmTCP_WATCH2_ADDR_L 0x32a7 +#define mmTCP_WATCH3_ADDR_L 0x32aa +#define mmTCP_WATCH0_CNTL 0x32a2 +#define mmTCP_WATCH1_CNTL 0x32a5 +#define mmTCP_WATCH2_CNTL 0x32a8 +#define mmTCP_WATCH3_CNTL 0x32ab +#define mmTCP_GATCL1_CNTL 0x32b0 +#define mmTCP_ATC_EDC_GATCL1_CNT 0x32b1 +#define mmTCP_GATCL1_DSM_CNTL 0x32b2 +#define mmTCP_DSM_CNTL 0x32b3 +#define mmTCP_CNTL2 0x32b4 +#define mmTD_CGTT_CTRL 0xf09c +#define mmTA_CGTT_CTRL 0xf09d +#define mmCGTT_TCP_CLK_CTRL 0xf09e +#define mmCGTT_TCI_CLK_CTRL 0xf09f +#define mmTCI_STATUS 0x2b61 +#define mmTCI_CNTL_1 0x2b62 +#define mmTCI_CNTL_2 0x2b63 +#define mmGDS_CONFIG 0x25c0 +#define mmGDS_CNTL_STATUS 0x25c1 +#define mmGDS_ENHANCE2 0x25c2 +#define mmGDS_PROTECTION_FAULT 0x25c3 +#define mmGDS_VM_PROTECTION_FAULT 0x25c4 +#define mmGDS_EDC_CNT 0x25c5 +#define mmGDS_EDC_GRBM_CNT 0x25c6 +#define mmGDS_EDC_OA_DED 0x25c7 +#define mmGDS_DEBUG_CNTL 0x25c8 +#define mmGDS_DEBUG_DATA 0x25c9 +#define mmGDS_DSM_CNTL 0x25ca +#define mmCGTT_GDS_CLK_CTRL 0xf0a0 +#define mmGDS_RD_ADDR 0xc400 +#define mmGDS_RD_DATA 0xc401 +#define mmGDS_RD_BURST_ADDR 0xc402 +#define mmGDS_RD_BURST_COUNT 0xc403 +#define mmGDS_RD_BURST_DATA 0xc404 +#define mmGDS_WR_ADDR 0xc405 +#define mmGDS_WR_DATA 0xc406 +#define mmGDS_WR_BURST_ADDR 0xc407 +#define mmGDS_WR_BURST_DATA 0xc408 +#define mmGDS_WRITE_COMPLETE 0xc409 +#define mmGDS_ATOM_CNTL 0xc40a +#define mmGDS_ATOM_COMPLETE 0xc40b +#define mmGDS_ATOM_BASE 0xc40c +#define mmGDS_ATOM_SIZE 0xc40d +#define mmGDS_ATOM_OFFSET0 0xc40e +#define mmGDS_ATOM_OFFSET1 0xc40f +#define mmGDS_ATOM_DST 0xc410 +#define mmGDS_ATOM_OP 0xc411 +#define mmGDS_ATOM_SRC0 0xc412 +#define mmGDS_ATOM_SRC0_U 0xc413 +#define mmGDS_ATOM_SRC1 0xc414 +#define mmGDS_ATOM_SRC1_U 0xc415 +#define mmGDS_ATOM_READ0 0xc416 +#define mmGDS_ATOM_READ0_U 0xc417 +#define mmGDS_ATOM_READ1 0xc418 +#define mmGDS_ATOM_READ1_U 0xc419 +#define mmGDS_GWS_RESOURCE_CNTL 0xc41a +#define mmGDS_GWS_RESOURCE 0xc41b +#define mmGDS_GWS_RESOURCE_CNT 0xc41c +#define mmGDS_OA_CNTL 0xc41d +#define mmGDS_OA_COUNTER 0xc41e +#define mmGDS_OA_ADDRESS 0xc41f +#define mmGDS_OA_INCDEC 0xc420 +#define mmGDS_OA_RING_SIZE 0xc421 +#define ixGDS_DEBUG_REG0 0x0 +#define ixGDS_DEBUG_REG1 0x1 +#define ixGDS_DEBUG_REG2 0x2 +#define ixGDS_DEBUG_REG3 0x3 +#define ixGDS_DEBUG_REG4 0x4 +#define ixGDS_DEBUG_REG5 0x5 +#define ixGDS_DEBUG_REG6 0x6 +#define mmGDS_PERFCOUNTER0_SELECT 0xda80 +#define mmGDS_PERFCOUNTER1_SELECT 0xda81 +#define mmGDS_PERFCOUNTER2_SELECT 0xda82 +#define mmGDS_PERFCOUNTER3_SELECT 0xda83 +#define mmGDS_PERFCOUNTER0_LO 0xd280 +#define mmGDS_PERFCOUNTER1_LO 0xd282 +#define mmGDS_PERFCOUNTER2_LO 0xd284 +#define mmGDS_PERFCOUNTER3_LO 0xd286 +#define mmGDS_PERFCOUNTER0_HI 0xd281 +#define mmGDS_PERFCOUNTER1_HI 0xd283 +#define mmGDS_PERFCOUNTER2_HI 0xd285 +#define mmGDS_PERFCOUNTER3_HI 0xd287 +#define mmGDS_PERFCOUNTER0_SELECT1 0xda84 +#define mmGDS_VMID0_BASE 0x3300 +#define mmGDS_VMID1_BASE 0x3302 +#define mmGDS_VMID2_BASE 0x3304 +#define mmGDS_VMID3_BASE 0x3306 +#define mmGDS_VMID4_BASE 0x3308 +#define mmGDS_VMID5_BASE 0x330a +#define mmGDS_VMID6_BASE 0x330c +#define mmGDS_VMID7_BASE 0x330e +#define mmGDS_VMID8_BASE 0x3310 +#define mmGDS_VMID9_BASE 0x3312 +#define mmGDS_VMID10_BASE 0x3314 +#define mmGDS_VMID11_BASE 0x3316 +#define mmGDS_VMID12_BASE 0x3318 +#define mmGDS_VMID13_BASE 0x331a +#define mmGDS_VMID14_BASE 0x331c +#define mmGDS_VMID15_BASE 0x331e +#define mmGDS_VMID0_SIZE 0x3301 +#define mmGDS_VMID1_SIZE 0x3303 +#define mmGDS_VMID2_SIZE 0x3305 +#define mmGDS_VMID3_SIZE 0x3307 +#define mmGDS_VMID4_SIZE 0x3309 +#define mmGDS_VMID5_SIZE 0x330b +#define mmGDS_VMID6_SIZE 0x330d +#define mmGDS_VMID7_SIZE 0x330f +#define mmGDS_VMID8_SIZE 0x3311 +#define mmGDS_VMID9_SIZE 0x3313 +#define mmGDS_VMID10_SIZE 0x3315 +#define mmGDS_VMID11_SIZE 0x3317 +#define mmGDS_VMID12_SIZE 0x3319 +#define mmGDS_VMID13_SIZE 0x331b +#define mmGDS_VMID14_SIZE 0x331d +#define mmGDS_VMID15_SIZE 0x331f +#define mmGDS_GWS_VMID0 0x3320 +#define mmGDS_GWS_VMID1 0x3321 +#define mmGDS_GWS_VMID2 0x3322 +#define mmGDS_GWS_VMID3 0x3323 +#define mmGDS_GWS_VMID4 0x3324 +#define mmGDS_GWS_VMID5 0x3325 +#define mmGDS_GWS_VMID6 0x3326 +#define mmGDS_GWS_VMID7 0x3327 +#define mmGDS_GWS_VMID8 0x3328 +#define mmGDS_GWS_VMID9 0x3329 +#define mmGDS_GWS_VMID10 0x332a +#define mmGDS_GWS_VMID11 0x332b +#define mmGDS_GWS_VMID12 0x332c +#define mmGDS_GWS_VMID13 0x332d +#define mmGDS_GWS_VMID14 0x332e +#define mmGDS_GWS_VMID15 0x332f +#define mmGDS_OA_VMID0 0x3330 +#define mmGDS_OA_VMID1 0x3331 +#define mmGDS_OA_VMID2 0x3332 +#define mmGDS_OA_VMID3 0x3333 +#define mmGDS_OA_VMID4 0x3334 +#define mmGDS_OA_VMID5 0x3335 +#define mmGDS_OA_VMID6 0x3336 +#define mmGDS_OA_VMID7 0x3337 +#define mmGDS_OA_VMID8 0x3338 +#define mmGDS_OA_VMID9 0x3339 +#define mmGDS_OA_VMID10 0x333a +#define mmGDS_OA_VMID11 0x333b +#define mmGDS_OA_VMID12 0x333c +#define mmGDS_OA_VMID13 0x333d +#define mmGDS_OA_VMID14 0x333e +#define mmGDS_OA_VMID15 0x333f +#define mmGDS_GWS_RESET0 0x3344 +#define mmGDS_GWS_RESET1 0x3345 +#define mmGDS_GWS_RESOURCE_RESET 0x3346 +#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 +#define mmGDS_OA_RESET_MASK 0x3349 +#define mmGDS_OA_RESET 0x334a +#define mmGDS_ENHANCE 0x334b +#define mmGDS_OA_CGPG_RESTORE 0x334c +#define mmGDS_CS_CTXSW_STATUS 0x334d +#define mmGDS_CS_CTXSW_CNT0 0x334e +#define mmGDS_CS_CTXSW_CNT1 0x334f +#define mmGDS_CS_CTXSW_CNT2 0x3350 +#define mmGDS_CS_CTXSW_CNT3 0x3351 +#define mmGDS_GFX_CTXSW_STATUS 0x3352 +#define mmGDS_VS_CTXSW_CNT0 0x3353 +#define mmGDS_VS_CTXSW_CNT1 0x3354 +#define mmGDS_VS_CTXSW_CNT2 0x3355 +#define mmGDS_VS_CTXSW_CNT3 0x3356 +#define mmGDS_PS0_CTXSW_CNT0 0x3357 +#define mmGDS_PS1_CTXSW_CNT0 0x335b +#define mmGDS_PS2_CTXSW_CNT0 0x335f +#define mmGDS_PS3_CTXSW_CNT0 0x3363 +#define mmGDS_PS4_CTXSW_CNT0 0x3367 +#define mmGDS_PS5_CTXSW_CNT0 0x336b +#define mmGDS_PS6_CTXSW_CNT0 0x336f +#define mmGDS_PS7_CTXSW_CNT0 0x3373 +#define mmGDS_PS0_CTXSW_CNT1 0x3358 +#define mmGDS_PS1_CTXSW_CNT1 0x335c +#define mmGDS_PS2_CTXSW_CNT1 0x3360 +#define mmGDS_PS3_CTXSW_CNT1 0x3364 +#define mmGDS_PS4_CTXSW_CNT1 0x3368 +#define mmGDS_PS5_CTXSW_CNT1 0x336c +#define mmGDS_PS6_CTXSW_CNT1 0x3370 +#define mmGDS_PS7_CTXSW_CNT1 0x3374 +#define mmGDS_PS0_CTXSW_CNT2 0x3359 +#define mmGDS_PS1_CTXSW_CNT2 0x335d +#define mmGDS_PS2_CTXSW_CNT2 0x3361 +#define mmGDS_PS3_CTXSW_CNT2 0x3365 +#define mmGDS_PS4_CTXSW_CNT2 0x3369 +#define mmGDS_PS5_CTXSW_CNT2 0x336d +#define mmGDS_PS6_CTXSW_CNT2 0x3371 +#define mmGDS_PS7_CTXSW_CNT2 0x3375 +#define mmGDS_PS0_CTXSW_CNT3 0x335a +#define mmGDS_PS1_CTXSW_CNT3 0x335e +#define mmGDS_PS2_CTXSW_CNT3 0x3362 +#define mmGDS_PS3_CTXSW_CNT3 0x3366 +#define mmGDS_PS4_CTXSW_CNT3 0x336a +#define mmGDS_PS5_CTXSW_CNT3 0x336e +#define mmGDS_PS6_CTXSW_CNT3 0x3372 +#define mmGDS_PS7_CTXSW_CNT3 0x3376 +#define mmCS_COPY_STATE 0xa1f3 +#define mmGFX_COPY_STATE 0xa1f4 +#define mmVGT_DRAW_INITIATOR 0xa1fc +#define mmVGT_EVENT_INITIATOR 0xa2a4 +#define mmVGT_EVENT_ADDRESS_REG 0xa1fe +#define mmVGT_DMA_BASE_HI 0xa1f9 +#define mmVGT_DMA_BASE 0xa1fa +#define mmVGT_DMA_INDEX_TYPE 0xa29f +#define mmVGT_DMA_NUM_INSTANCES 0xa2a2 +#define mmIA_ENHANCE 0xa29c +#define mmVGT_DMA_SIZE 0xa29d +#define mmVGT_DMA_MAX_SIZE 0xa29e +#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 +#define mmVGT_DMA_CONTROL 0x2272 +#define mmVGT_IMMED_DATA 0xa1fd +#define mmVGT_INDEX_TYPE 0xc243 +#define mmVGT_NUM_INDICES 0xc24c +#define mmVGT_NUM_INSTANCES 0xc24d +#define mmVGT_PRIMITIVE_TYPE 0xc242 +#define mmVGT_PRIMITIVEID_EN 0xa2a1 +#define mmVGT_PRIMITIVEID_RESET 0xa2a3 +#define mmVGT_VTX_CNT_EN 0xa2ae +#define mmVGT_REUSE_OFF 0xa2ad +#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 +#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 +#define mmVGT_MAX_VTX_INDX 0xa100 +#define mmVGT_MIN_VTX_INDX 0xa101 +#define mmVGT_INDX_OFFSET 0xa102 +#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 +#define mmVGT_OUT_DEALLOC_CNTL 0xa317 +#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 +#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 +#define mmVGT_ENHANCE 0xa294 +#define mmVGT_OUTPUT_PATH_CNTL 0xa284 +#define mmVGT_HOS_CNTL 0xa285 +#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 +#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 +#define mmVGT_HOS_REUSE_DEPTH 0xa288 +#define mmVGT_GROUP_PRIM_TYPE 0xa289 +#define mmVGT_GROUP_FIRST_DECR 0xa28a +#define mmVGT_GROUP_DECR 0xa28b +#define mmVGT_GROUP_VECT_0_CNTL 0xa28c +#define mmVGT_GROUP_VECT_1_CNTL 0xa28d +#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e +#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f +#define mmVGT_VTX_VECT_EJECT_REG 0x222c +#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d +#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e +#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f +#define mmVGT_LAST_COPY_STATE 0x2230 +#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f +#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 +#define mmVGT_GS_MODE 0xa290 +#define mmVGT_GS_ONCHIP_CNTL 0xa291 +#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b +#define mmVGT_CACHE_INVALIDATION 0x2231 +#define mmVGT_RESET_DEBUG 0x2232 +#define mmVGT_STRMOUT_DELAY 0x2233 +#define mmVGT_FIFO_DEPTHS 0x2234 +#define mmVGT_GS_PER_ES 0xa295 +#define mmVGT_ES_PER_GS 0xa296 +#define mmVGT_GS_PER_VS 0xa297 +#define mmVGT_GS_VERTEX_REUSE 0x2235 +#define mmVGT_MC_LAT_CNTL 0x2236 +#define mmIA_CNTL_STATUS 0x2237 +#define mmVGT_STRMOUT_CONFIG 0xa2e5 +#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 +#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 +#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc +#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 +#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 +#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb +#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf +#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 +#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 +#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 +#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd +#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 +#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 +#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 +#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca +#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb +#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc +#define mmVGT_GS_MAX_VERT_OUT 0xa2ce +#define mmVGT_SHADER_STAGES_EN 0xa2d5 +#define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd +#define mmVGT_LS_HS_CONFIG 0xa2d6 +#define mmVGT_DMA_LS_HS_CONFIG 0x2273 +#define mmVGT_TF_PARAM 0xa2db +#define mmVGT_TESS_DISTRIBUTION 0xa2d4 +#define mmVGT_TF_RING_SIZE 0xc24e +#define mmVGT_SYS_CONFIG 0x2263 +#define mmVGT_HS_OFFCHIP_PARAM 0xc24f +#define mmVGT_TF_MEMORY_BASE 0xc250 +#define mmVGT_GS_INSTANCE_CNT 0xa2e4 +#define mmIA_MULTI_VGT_PARAM 0xa2aa +#define mmVGT_VS_MAX_WAVE_ID 0x2268 +#define mmVGT_ESGS_RING_SIZE 0xc240 +#define mmVGT_GSVS_RING_SIZE 0xc241 +#define mmVGT_GSVS_RING_OFFSET_1 0xa298 +#define mmVGT_GSVS_RING_OFFSET_2 0xa299 +#define mmVGT_GSVS_RING_OFFSET_3 0xa29a +#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab +#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac +#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 +#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 +#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 +#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da +#define mmWD_CNTL_STATUS 0x223f +#define mmWD_ENHANCE 0xa2a0 +#define mmGFX_PIPE_CONTROL 0x226d +#define mmCGTT_VGT_CLK_CTRL 0xf084 +#define mmCGTT_IA_CLK_CTRL 0xf085 +#define mmCGTT_WD_CLK_CTRL 0xf086 +#define mmVGT_DEBUG_CNTL 0x2238 +#define mmVGT_DEBUG_DATA 0x2239 +#define mmIA_DEBUG_CNTL 0x223a +#define mmIA_DEBUG_DATA 0x223b +#define mmVGT_CNTL_STATUS 0x223c +#define mmWD_DEBUG_CNTL 0x223d +#define mmWD_DEBUG_DATA 0x223e +#define mmWD_QOS 0x2242 +#define mmCC_GC_PRIM_CONFIG 0x2240 +#define mmGC_USER_PRIM_CONFIG 0x2241 +#define ixWD_DEBUG_REG0 0x0 +#define ixWD_DEBUG_REG1 0x1 +#define ixWD_DEBUG_REG2 0x2 +#define ixWD_DEBUG_REG3 0x3 +#define ixWD_DEBUG_REG4 0x4 +#define ixWD_DEBUG_REG5 0x5 +#define ixWD_DEBUG_REG6 0x6 +#define ixWD_DEBUG_REG7 0x7 +#define ixWD_DEBUG_REG8 0x8 +#define ixWD_DEBUG_REG9 0x9 +#define ixWD_DEBUG_REG10 0xa +#define ixIA_DEBUG_REG0 0x0 +#define ixIA_DEBUG_REG1 0x1 +#define ixIA_DEBUG_REG2 0x2 +#define ixIA_DEBUG_REG3 0x3 +#define ixIA_DEBUG_REG4 0x4 +#define ixIA_DEBUG_REG5 0x5 +#define ixIA_DEBUG_REG6 0x6 +#define ixIA_DEBUG_REG7 0x7 +#define ixIA_DEBUG_REG8 0x8 +#define ixIA_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG0 0x0 +#define ixVGT_DEBUG_REG1 0x1 +#define ixVGT_DEBUG_REG2 0x1e +#define ixVGT_DEBUG_REG3 0x1f +#define ixVGT_DEBUG_REG4 0x20 +#define ixVGT_DEBUG_REG5 0x21 +#define ixVGT_DEBUG_REG6 0x22 +#define ixVGT_DEBUG_REG7 0x23 +#define ixVGT_DEBUG_REG8 0x8 +#define ixVGT_DEBUG_REG9 0x9 +#define ixVGT_DEBUG_REG10 0xa +#define ixVGT_DEBUG_REG11 0xb +#define ixVGT_DEBUG_REG12 0xc +#define ixVGT_DEBUG_REG13 0xd +#define ixVGT_DEBUG_REG14 0xe +#define ixVGT_DEBUG_REG15 0xf +#define ixVGT_DEBUG_REG16 0x10 +#define ixVGT_DEBUG_REG17 0x11 +#define ixVGT_DEBUG_REG18 0x7 +#define ixVGT_DEBUG_REG19 0x13 +#define ixVGT_DEBUG_REG20 0x14 +#define ixVGT_DEBUG_REG21 0x15 +#define ixVGT_DEBUG_REG22 0x16 +#define ixVGT_DEBUG_REG23 0x17 +#define ixVGT_DEBUG_REG24 0x18 +#define ixVGT_DEBUG_REG25 0x19 +#define ixVGT_DEBUG_REG26 0x24 +#define ixVGT_DEBUG_REG27 0x1b +#define ixVGT_DEBUG_REG28 0x1c +#define ixVGT_DEBUG_REG29 0x1d +#define ixVGT_DEBUG_REG31 0x26 +#define ixVGT_DEBUG_REG32 0x27 +#define ixVGT_DEBUG_REG33 0x28 +#define ixVGT_DEBUG_REG34 0x29 +#define ixVGT_DEBUG_REG36 0x2b +#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 +#define mmVGT_PERFCOUNTER0_SELECT 0xd88c +#define mmVGT_PERFCOUNTER1_SELECT 0xd88d +#define mmVGT_PERFCOUNTER2_SELECT 0xd88e +#define mmVGT_PERFCOUNTER3_SELECT 0xd88f +#define mmVGT_PERFCOUNTER0_SELECT1 0xd890 +#define mmVGT_PERFCOUNTER1_SELECT1 0xd891 +#define mmVGT_PERFCOUNTER0_LO 0xd090 +#define mmVGT_PERFCOUNTER1_LO 0xd092 +#define mmVGT_PERFCOUNTER2_LO 0xd094 +#define mmVGT_PERFCOUNTER3_LO 0xd096 +#define mmVGT_PERFCOUNTER0_HI 0xd091 +#define mmVGT_PERFCOUNTER1_HI 0xd093 +#define mmVGT_PERFCOUNTER2_HI 0xd095 +#define mmVGT_PERFCOUNTER3_HI 0xd097 +#define mmIA_PERFCOUNTER0_SELECT 0xd884 +#define mmIA_PERFCOUNTER1_SELECT 0xd885 +#define mmIA_PERFCOUNTER2_SELECT 0xd886 +#define mmIA_PERFCOUNTER3_SELECT 0xd887 +#define mmIA_PERFCOUNTER0_SELECT1 0xd888 +#define mmIA_PERFCOUNTER0_LO 0xd088 +#define mmIA_PERFCOUNTER1_LO 0xd08a +#define mmIA_PERFCOUNTER2_LO 0xd08c +#define mmIA_PERFCOUNTER3_LO 0xd08e +#define mmIA_PERFCOUNTER0_HI 0xd089 +#define mmIA_PERFCOUNTER1_HI 0xd08b +#define mmIA_PERFCOUNTER2_HI 0xd08d +#define mmIA_PERFCOUNTER3_HI 0xd08f +#define mmWD_PERFCOUNTER0_SELECT 0xd880 +#define mmWD_PERFCOUNTER1_SELECT 0xd881 +#define mmWD_PERFCOUNTER2_SELECT 0xd882 +#define mmWD_PERFCOUNTER3_SELECT 0xd883 +#define mmWD_PERFCOUNTER0_LO 0xd080 +#define mmWD_PERFCOUNTER1_LO 0xd082 +#define mmWD_PERFCOUNTER2_LO 0xd084 +#define mmWD_PERFCOUNTER3_LO 0xd086 +#define mmWD_PERFCOUNTER0_HI 0xd081 +#define mmWD_PERFCOUNTER1_HI 0xd083 +#define mmWD_PERFCOUNTER2_HI 0xd085 +#define mmWD_PERFCOUNTER3_HI 0xd087 +#define mmDIDT_IND_INDEX 0x3280 +#define mmDIDT_IND_DATA 0x3281 +#define ixDIDT_SQ_CTRL0 0x0 +#define ixDIDT_SQ_CTRL1 0x1 +#define ixDIDT_SQ_CTRL2 0x2 +#define ixDIDT_SQ_CTRL_OCP 0x3 +#define ixDIDT_SQ_WEIGHT0_3 0x10 +#define ixDIDT_SQ_WEIGHT4_7 0x11 +#define ixDIDT_SQ_WEIGHT8_11 0x12 +#define ixDIDT_DB_CTRL0 0x20 +#define ixDIDT_DB_CTRL1 0x21 +#define ixDIDT_DB_CTRL2 0x22 +#define ixDIDT_DB_CTRL_OCP 0x23 +#define ixDIDT_DB_WEIGHT0_3 0x30 +#define ixDIDT_DB_WEIGHT4_7 0x31 +#define ixDIDT_DB_WEIGHT8_11 0x32 +#define ixDIDT_TD_CTRL0 0x40 +#define ixDIDT_TD_CTRL1 0x41 +#define ixDIDT_TD_CTRL2 0x42 +#define ixDIDT_TD_CTRL_OCP 0x43 +#define ixDIDT_TD_WEIGHT0_3 0x50 +#define ixDIDT_TD_WEIGHT4_7 0x51 +#define ixDIDT_TD_WEIGHT8_11 0x52 +#define ixDIDT_TCP_CTRL0 0x60 +#define ixDIDT_TCP_CTRL1 0x61 +#define ixDIDT_TCP_CTRL2 0x62 +#define ixDIDT_TCP_CTRL_OCP 0x63 +#define ixDIDT_TCP_WEIGHT0_3 0x70 +#define ixDIDT_TCP_WEIGHT4_7 0x71 +#define ixDIDT_TCP_WEIGHT8_11 0x72 +#define ixDIDT_DBR_CTRL0 0x80 +#define ixDIDT_DBR_CTRL1 0x81 +#define ixDIDT_DBR_CTRL2 0x82 +#define ixDIDT_DBR_CTRL_OCP 0x83 +#define ixDIDT_DBR_WEIGHT0_3 0x90 +#define ixDIDT_DBR_WEIGHT4_7 0x91 +#define ixDIDT_DBR_WEIGHT8_11 0x92 + +#endif /* GFX_8_1_D_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h new file mode 100644 index 000000000000..f9022097fbe9 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_enum.h @@ -0,0 +1,6808 @@ +/* + * GFX_8_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_8_1_ENUM_H +#define GFX_8_1_ENUM_H + +typedef enum SurfaceNumber { + NUMBER_UNORM = 0x0, + NUMBER_SNORM = 0x1, + NUMBER_USCALED = 0x2, + NUMBER_SSCALED = 0x3, + NUMBER_UINT = 0x4, + NUMBER_SINT = 0x5, + NUMBER_SRGB = 0x6, + NUMBER_FLOAT = 0x7, +} SurfaceNumber; +typedef enum SurfaceSwap { + SWAP_STD = 0x0, + SWAP_ALT = 0x1, + SWAP_STD_REV = 0x2, + SWAP_ALT_REV = 0x3, +} SurfaceSwap; +typedef enum CBMode { + CB_DISABLE = 0x0, + CB_NORMAL = 0x1, + CB_ELIMINATE_FAST_CLEAR = 0x2, + CB_RESOLVE = 0x3, + CB_DECOMPRESS = 0x4, + CB_FMASK_DECOMPRESS = 0x5, + CB_DCC_DECOMPRESS = 0x6, +} CBMode; +typedef enum RoundMode { + ROUND_BY_HALF = 0x0, + ROUND_TRUNCATE = 0x1, +} RoundMode; +typedef enum SourceFormat { + EXPORT_4C_32BPC = 0x0, + EXPORT_4C_16BPC = 0x1, + EXPORT_2C_32BPC_GR = 0x2, + EXPORT_2C_32BPC_AR = 0x3, +} SourceFormat; +typedef enum BlendOp { + BLEND_ZERO = 0x0, + BLEND_ONE = 0x1, + BLEND_SRC_COLOR = 0x2, + BLEND_ONE_MINUS_SRC_COLOR = 0x3, + BLEND_SRC_ALPHA = 0x4, + BLEND_ONE_MINUS_SRC_ALPHA = 0x5, + BLEND_DST_ALPHA = 0x6, + BLEND_ONE_MINUS_DST_ALPHA = 0x7, + BLEND_DST_COLOR = 0x8, + BLEND_ONE_MINUS_DST_COLOR = 0x9, + BLEND_SRC_ALPHA_SATURATE = 0xa, + BLEND_BOTH_SRC_ALPHA = 0xb, + BLEND_BOTH_INV_SRC_ALPHA = 0xc, + BLEND_CONSTANT_COLOR = 0xd, + BLEND_ONE_MINUS_CONSTANT_COLOR = 0xe, + BLEND_SRC1_COLOR = 0xf, + BLEND_INV_SRC1_COLOR = 0x10, + BLEND_SRC1_ALPHA = 0x11, + BLEND_INV_SRC1_ALPHA = 0x12, + BLEND_CONSTANT_ALPHA = 0x13, + BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x14, +} BlendOp; +typedef enum CombFunc { + COMB_DST_PLUS_SRC = 0x0, + COMB_SRC_MINUS_DST = 0x1, + COMB_MIN_DST_SRC = 0x2, + COMB_MAX_DST_SRC = 0x3, + COMB_DST_MINUS_SRC = 0x4, +} CombFunc; +typedef enum BlendOpt { + FORCE_OPT_AUTO = 0x0, + FORCE_OPT_DISABLE = 0x1, + FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x2, + FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x3, + FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x4, + FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x5, + FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x6, + FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x7, +} BlendOpt; +typedef enum CmaskCode { + CMASK_CLR00_F0 = 0x0, + CMASK_CLR00_F1 = 0x1, + CMASK_CLR00_F2 = 0x2, + CMASK_CLR00_FX = 0x3, + CMASK_CLR01_F0 = 0x4, + CMASK_CLR01_F1 = 0x5, + CMASK_CLR01_F2 = 0x6, + CMASK_CLR01_FX = 0x7, + CMASK_CLR10_F0 = 0x8, + CMASK_CLR10_F1 = 0x9, + CMASK_CLR10_F2 = 0xa, + CMASK_CLR10_FX = 0xb, + CMASK_CLR11_F0 = 0xc, + CMASK_CLR11_F1 = 0xd, + CMASK_CLR11_F2 = 0xe, + CMASK_CLR11_FX = 0xf, +} CmaskCode; +typedef enum CmaskAddr { + CMASK_ADDR_TILED = 0x0, + CMASK_ADDR_LINEAR = 0x1, + CMASK_ADDR_COMPATIBLE = 0x2, +} CmaskAddr; +typedef enum CBPerfSel { + CB_PERF_SEL_NONE = 0x0, + CB_PERF_SEL_BUSY = 0x1, + CB_PERF_SEL_CORE_SCLK_VLD = 0x2, + CB_PERF_SEL_REG_SCLK0_VLD = 0x3, + CB_PERF_SEL_REG_SCLK1_VLD = 0x4, + CB_PERF_SEL_DRAWN_QUAD = 0x5, + CB_PERF_SEL_DRAWN_PIXEL = 0x6, + CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x7, + CB_PERF_SEL_DRAWN_TILE = 0x8, + CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x9, + CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0xa, + CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0xb, + CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0xc, + CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0xd, + CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0xe, + CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0xf, + CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x10, + CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x11, + CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x12, + CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x13, + CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x14, + CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x15, + CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x16, + CB_PERF_SEL_LQUAD_NO_TILE = 0x17, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x18, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x19, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x1a, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x1b, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x1c, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x1d, + CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR= 0x1e, + CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x1f, + CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x20, + CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK= 0x21, + CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x22, + CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x23, + CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x24, + CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x25, + CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x26, + CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x27, + CB_PERF_SEL_FOP_IN_VALID_READY = 0x28, + CB_PERF_SEL_FOP_IN_VALID_READYB = 0x29, + CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x2a, + CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x2b, + CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x2c, + CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x2d, + CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x2e, + CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x2f, + CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x30, + CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x31, + CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x32, + CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x33, + CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x34, + CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x35, + CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x36, + CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x37, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x38, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x39, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x3a, + CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x3b, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x3c, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x3d, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x3e, + CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x3f, + CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x40, + CB_PERF_SEL_CM_CACHE_HIT = 0x41, + CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x42, + CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x43, + CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x44, + CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x45, + CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x46, + CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x47, + CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x48, + CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x49, + CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x4a, + CB_PERF_SEL_CM_CACHE_STALL = 0x4b, + CB_PERF_SEL_CM_CACHE_FLUSH = 0x4c, + CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x4d, + CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x4e, + CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x4f, + CB_PERF_SEL_FC_CACHE_HIT = 0x50, + CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x51, + CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x52, + CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x53, + CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x54, + CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x55, + CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x56, + CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x57, + CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x58, + CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x59, + CB_PERF_SEL_FC_CACHE_STALL = 0x5a, + CB_PERF_SEL_FC_CACHE_FLUSH = 0x5b, + CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x5c, + CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x5d, + CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x5e, + CB_PERF_SEL_CC_CACHE_HIT = 0x5f, + CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x60, + CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x61, + CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x62, + CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0x63, + CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x64, + CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0x65, + CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x66, + CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x67, + CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x68, + CB_PERF_SEL_CC_CACHE_STALL = 0x69, + CB_PERF_SEL_CC_CACHE_FLUSH = 0x6a, + CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x6b, + CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x6c, + CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x6d, + CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x6e, + CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x6f, + CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x70, + CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x71, + CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x72, + CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x73, + CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x74, + CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x75, + CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x76, + CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x77, + CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x78, + CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x79, + CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x7a, + CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x7b, + CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x7c, + CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x7d, + CB_PERF_SEL_CM_MC_READ_REQUEST = 0x7e, + CB_PERF_SEL_FC_MC_READ_REQUEST = 0x7f, + CB_PERF_SEL_CC_MC_READ_REQUEST = 0x80, + CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x81, + CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x82, + CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x83, + CB_PERF_SEL_CM_TQ_FULL = 0x84, + CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x85, + CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x86, + CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x87, + CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x88, + CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x89, + CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x8a, + CB_PERF_SEL_CC_SF_FULL = 0x8b, + CB_PERF_SEL_CC_RB_FULL = 0x8c, + CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x8d, + CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x8e, + CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x8f, + CB_PERF_SEL_EVENT = 0x90, + CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x91, + CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x92, + CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x93, + CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x94, + CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x95, + CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x96, + CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x97, + CB_PERF_SEL_CC_SURFACE_SYNC = 0x98, + CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x99, + CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x9a, + CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x9b, + CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x9c, + CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x9d, + CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x9e, + CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x9f, + CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0xa0, + CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0xa1, + CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0xa2, + CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0xa3, + CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0xa4, + CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0xa5, + CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0xa6, + CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0xa7, + CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0xa8, + CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0xa9, + CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0xaa, + CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0xab, + CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0xac, + CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0xad, + CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0xae, + CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0xaf, + CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0xb0, + CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0xb1, + CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0xb2, + CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0xb3, + CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0xb4, + CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0xb5, + CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0xb6, + CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0xb7, + CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0xb8, + CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0xb9, + CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0xba, + CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0xbb, + CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0xbc, + CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0xbd, + CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0xbe, + CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0xbf, + CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0xc0, + CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0xc1, + CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0xc2, + CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0xc3, + CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0xc4, + CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0xc5, + CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0xc6, + CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0xc7, + CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0xc8, + CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0xc9, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0xca, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0xcb, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0xcc, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0xcd, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0xce, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0xcf, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0xd0, + CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0xd1, + CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0xd2, + CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0xd3, + CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0xd4, + CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED= 0xd5, + CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED= 0xd6, + CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0xd7, + CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0xd8, + CB_PERF_SEL_DRAWN_BUSY = 0xd9, + CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0xda, + CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0xdb, + CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0xdc, + CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0xdd, + CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED= 0xde, + CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0xdf, + CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0xe0, + CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0xe1, + CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE= 0xe2, + CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0xe3, + CB_PERF_SEL_FC_DOC_IS_STALLED = 0xe4, + CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0xe5, + CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0xe6, + CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0xe7, + CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0xe8, + CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0xe9, + CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0xea, + CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0xeb, + CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0xec, + CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0xed, + CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0xee, + CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0xef, + CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0xf0, + CB_PERF_SEL_FC_DCC_CACHE_HIT = 0xf1, + CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0xf2, + CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0xf3, + CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0xf4, + CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL= 0xf5, + CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL= 0xf6, + CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL= 0xf7, + CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0xf8, + CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0xf9, + CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0xfa, + CB_PERF_SEL_FC_DCC_CACHE_STALL = 0xfb, + CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0xfc, + CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0xfd, + CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0xfe, + CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0xff, + CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x100, + CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x101, + CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x102, + CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x103, + CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x104, + CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x105, + CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x106, + CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x107, + CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x108, + CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x109, + CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x10a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x10b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2= 0x10c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x10d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1= 0x10e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1= 0x10f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2= 0x110, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1= 0x111, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x112, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x113, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1= 0x114, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2= 0x115, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2= 0x116, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2= 0x117, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x118, + CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1= 0x119, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x11a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2= 0x11b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3= 0x11c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4= 0x11d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1= 0x11e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x11f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3= 0x120, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4= 0x121, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1= 0x122, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2= 0x123, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x124, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4= 0x125, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1= 0x126, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2= 0x127, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3= 0x128, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1= 0x129, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2= 0x12a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3= 0x12b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4= 0x12c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1= 0x12d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2= 0x12e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3= 0x12f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4= 0x130, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1= 0x131, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2= 0x132, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3= 0x133, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4= 0x134, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1= 0x135, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2= 0x136, + CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3= 0x137, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1= 0x138, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1= 0x139, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1= 0x13a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1= 0x13b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1= 0x13c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1= 0x13d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1= 0x13e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1= 0x13f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2= 0x140, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2= 0x141, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2= 0x142, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2= 0x143, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2= 0x144, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2= 0x145, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2= 0x146, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1= 0x147, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1= 0x148, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1= 0x149, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1= 0x14a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2= 0x14b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2= 0x14c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2= 0x14d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2= 0x14e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2= 0x14f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2= 0x150, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2= 0x151, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1= 0x152, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1= 0x153, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1= 0x154, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1= 0x155, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1= 0x156, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2= 0x157, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3= 0x158, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4= 0x159, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5= 0x15a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6= 0x15b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x15c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x15d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1= 0x15e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2= 0x15f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3= 0x160, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4= 0x161, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5= 0x162, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x163, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x164, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1= 0x165, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1= 0x166, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1= 0x167, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1= 0x168, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1= 0x169, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1= 0x16a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x16b, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x16c, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2= 0x16d, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2= 0x16e, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2= 0x16f, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2= 0x170, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2= 0x171, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x172, + CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x173, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x174, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x175, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x176, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x177, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x178, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x179, + CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x17a, + CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x17b, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x17c, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x17d, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x17e, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x17f, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x180, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x181, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x182, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x183, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x184, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x185, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x186, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x187, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x188, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x189, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x18a, + CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x18b, + CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x18c, + CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x18d, + CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x18e, + CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x18f, + CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x190, + CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x191, + CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x192, + CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x193, + CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x194, +} CBPerfSel; +typedef enum CBPerfOpFilterSel { + CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x0, + CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x1, + CB_PERF_OP_FILTER_SEL_RESOLVE = 0x2, + CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x3, + CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x4, + CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x5, +} CBPerfOpFilterSel; +typedef enum CBPerfClearFilterSel { + CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x0, + CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x1, +} CBPerfClearFilterSel; +typedef enum CP_RING_ID { + RINGID0 = 0x0, + RINGID1 = 0x1, + RINGID2 = 0x2, + RINGID3 = 0x3, +} CP_RING_ID; +typedef enum CP_PIPE_ID { + PIPE_ID0 = 0x0, + PIPE_ID1 = 0x1, + PIPE_ID2 = 0x2, + PIPE_ID3 = 0x3, +} CP_PIPE_ID; +typedef enum CP_ME_ID { + ME_ID0 = 0x0, + ME_ID1 = 0x1, + ME_ID2 = 0x2, + ME_ID3 = 0x3, +} CP_ME_ID; +typedef enum SPM_PERFMON_STATE { + STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x0, + STRM_PERFMON_STATE_START_COUNTING = 0x1, + STRM_PERFMON_STATE_STOP_COUNTING = 0x2, + STRM_PERFMON_STATE_RESERVED_3 = 0x3, + STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, + STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, +} SPM_PERFMON_STATE; +typedef enum CP_PERFMON_STATE { + CP_PERFMON_STATE_DISABLE_AND_RESET = 0x0, + CP_PERFMON_STATE_START_COUNTING = 0x1, + CP_PERFMON_STATE_STOP_COUNTING = 0x2, + CP_PERFMON_STATE_RESERVED_3 = 0x3, + CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x4, + CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x5, +} CP_PERFMON_STATE; +typedef enum CP_PERFMON_ENABLE_MODE { + CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x0, + CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x1, + CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x2, + CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x3, +} CP_PERFMON_ENABLE_MODE; +typedef enum CPG_PERFCOUNT_SEL { + CPG_PERF_SEL_ALWAYS_COUNT = 0x0, + CPG_PERF_SEL_RBIU_FIFO_FULL = 0x1, + CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x2, + CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x3, + CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x4, + CPG_PERF_SEL_ME_PARSER_BUSY = 0x5, + CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x6, + CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x7, + CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x8, + CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x9, + CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0xa, + CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0xb, + CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0xc, + CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0xd, + CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0xe, + CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0xf, + CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x10, + CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x11, + CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x12, + CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x13, + CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x14, + CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x15, + CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x16, + CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x17, + CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x18, + CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x19, + CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x1a, + CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x1b, + CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x1c, + CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x1d, + CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x1e, + CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x1f, + CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x20, + CPG_PERF_SEL_REGISTER_CLK_VALID = 0x21, + CPG_PERF_SEL_MIU_WRITE_REQUEST_SENT = 0x22, + CPG_PERF_SEL_MIU_READ_REQUEST_SENT = 0x23, + CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x24, + CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x25, + CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x26, + CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x27, + CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x28, + CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x29, + CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x2a, + CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x2b, + CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x2c, + CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x2d, + CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x2e, + CPG_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x2f, + CPG_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x30, +} CPG_PERFCOUNT_SEL; +typedef enum CPF_PERFCOUNT_SEL { + CPF_PERF_SEL_ALWAYS_COUNT = 0x0, + CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x1, + CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x2, + CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x3, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x4, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x5, + CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x6, + CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x7, + CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x8, + CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x9, + CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0xa, + CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0xb, + CPF_PERF_SEL_GRBM_DWORDS_SENT = 0xc, + CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0xd, + CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0xe, + CPF_PERF_SEL_MIU_WRITE_REQUEST_SEND = 0xf, + CPF_PERF_SEL_MIU_READ_REQUEST_SEND = 0x10, + CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x11, + CPF_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x12, + CPF_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x13, +} CPF_PERFCOUNT_SEL; +typedef enum CPC_PERFCOUNT_SEL { + CPC_PERF_SEL_ALWAYS_COUNT = 0x0, + CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x1, + CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x2, + CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x3, + CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x4, + CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x5, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x6, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x7, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x8, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_READ = 0x9, + CPC_PERF_SEL_ME1_STALL_WAIT_ON_MIU_WRITE = 0xa, + CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0xb, + CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0xc, + CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0xd, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0xe, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0xf, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x10, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_READ = 0x11, + CPC_PERF_SEL_ME2_STALL_WAIT_ON_MIU_WRITE = 0x12, + CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x13, + CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x14, + CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x15, + CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_FREE = 0x16, + CPC_PERF_SEL_ATCL2IU_STALL_WAIT_ON_TAGS = 0x17, + CPC_PERF_SEL_ATCL1_STALL_ON_TRANSLATION = 0x18, +} CPC_PERFCOUNT_SEL; +typedef enum CP_ALPHA_TAG_RAM_SEL { + CPG_TAG_RAM = 0x0, + CPC_TAG_RAM = 0x1, + CPF_TAG_RAM = 0x2, + RSV_TAG_RAM = 0x3, +} CP_ALPHA_TAG_RAM_SEL; +#define SEM_ECC_ERROR 0x0 +#define SEM_RESERVED 0x1 +#define SEM_FAILED 0x2 +#define SEM_PASSED 0x3 +#define IQ_QUEUE_SLEEP 0x0 +#define IQ_OFFLOAD_RETRY 0x1 +#define IQ_SCH_WAVE_MSG 0x2 +#define IQ_SEM_REARM 0x3 +#define IQ_DEQUEUE_RETRY 0x4 +#define IQ_INTR_TYPE_PQ 0x0 +#define IQ_INTR_TYPE_IB 0x1 +#define IQ_INTR_TYPE_MQD 0x2 +#define VMID_SZ 0x4 +#define CONFIG_SPACE_START 0x2000 +#define CONFIG_SPACE_END 0x9fff +#define CONFIG_SPACE1_START 0x2000 +#define CONFIG_SPACE1_END 0x2bff +#define CONFIG_SPACE2_START 0x3000 +#define CONFIG_SPACE2_END 0x9fff +#define UCONFIG_SPACE_START 0xc000 +#define UCONFIG_SPACE_END 0xffff +#define PERSISTENT_SPACE_START 0x2c00 +#define PERSISTENT_SPACE_END 0x2fff +#define CONTEXT_SPACE_START 0xa000 +#define CONTEXT_SPACE_END 0xbfff +typedef enum ForceControl { + FORCE_OFF = 0x0, + FORCE_ENABLE = 0x1, + FORCE_DISABLE = 0x2, + FORCE_RESERVED = 0x3, +} ForceControl; +typedef enum ZSamplePosition { + Z_SAMPLE_CENTER = 0x0, + Z_SAMPLE_CENTROID = 0x1, +} ZSamplePosition; +typedef enum ZOrder { + LATE_Z = 0x0, + EARLY_Z_THEN_LATE_Z = 0x1, + RE_Z = 0x2, + EARLY_Z_THEN_RE_Z = 0x3, +} ZOrder; +typedef enum ZpassControl { + ZPASS_DISABLE = 0x0, + ZPASS_SAMPLES = 0x1, + ZPASS_PIXELS = 0x2, +} ZpassControl; +typedef enum ZModeForce { + NO_FORCE = 0x0, + FORCE_EARLY_Z = 0x1, + FORCE_LATE_Z = 0x2, + FORCE_RE_Z = 0x3, +} ZModeForce; +typedef enum ZLimitSumm { + FORCE_SUMM_OFF = 0x0, + FORCE_SUMM_MINZ = 0x1, + FORCE_SUMM_MAXZ = 0x2, + FORCE_SUMM_BOTH = 0x3, +} ZLimitSumm; +typedef enum CompareFrag { + FRAG_NEVER = 0x0, + FRAG_LESS = 0x1, + FRAG_EQUAL = 0x2, + FRAG_LEQUAL = 0x3, + FRAG_GREATER = 0x4, + FRAG_NOTEQUAL = 0x5, + FRAG_GEQUAL = 0x6, + FRAG_ALWAYS = 0x7, +} CompareFrag; +typedef enum StencilOp { + STENCIL_KEEP = 0x0, + STENCIL_ZERO = 0x1, + STENCIL_ONES = 0x2, + STENCIL_REPLACE_TEST = 0x3, + STENCIL_REPLACE_OP = 0x4, + STENCIL_ADD_CLAMP = 0x5, + STENCIL_SUB_CLAMP = 0x6, + STENCIL_INVERT = 0x7, + STENCIL_ADD_WRAP = 0x8, + STENCIL_SUB_WRAP = 0x9, + STENCIL_AND = 0xa, + STENCIL_OR = 0xb, + STENCIL_XOR = 0xc, + STENCIL_NAND = 0xd, + STENCIL_NOR = 0xe, + STENCIL_XNOR = 0xf, +} StencilOp; +typedef enum ConservativeZExport { + EXPORT_ANY_Z = 0x0, + EXPORT_LESS_THAN_Z = 0x1, + EXPORT_GREATER_THAN_Z = 0x2, + EXPORT_RESERVED = 0x3, +} ConservativeZExport; +typedef enum DbPSLControl { + PSLC_AUTO = 0x0, + PSLC_ON_HANG_ONLY = 0x1, + PSLC_ASAP = 0x2, + PSLC_COUNTDOWN = 0x3, +} DbPSLControl; +typedef enum PerfCounter_Vals { + DB_PERF_SEL_SC_DB_tile_sends = 0x0, + DB_PERF_SEL_SC_DB_tile_busy = 0x1, + DB_PERF_SEL_SC_DB_tile_stalls = 0x2, + DB_PERF_SEL_SC_DB_tile_events = 0x3, + DB_PERF_SEL_SC_DB_tile_tiles = 0x4, + DB_PERF_SEL_SC_DB_tile_covered = 0x5, + DB_PERF_SEL_hiz_tc_read_starved = 0x6, + DB_PERF_SEL_hiz_tc_write_stall = 0x7, + DB_PERF_SEL_hiz_qtiles_culled = 0x8, + DB_PERF_SEL_his_qtiles_culled = 0x9, + DB_PERF_SEL_DB_SC_tile_sends = 0xa, + DB_PERF_SEL_DB_SC_tile_busy = 0xb, + DB_PERF_SEL_DB_SC_tile_stalls = 0xc, + DB_PERF_SEL_DB_SC_tile_df_stalls = 0xd, + DB_PERF_SEL_DB_SC_tile_tiles = 0xe, + DB_PERF_SEL_DB_SC_tile_culled = 0xf, + DB_PERF_SEL_DB_SC_tile_hier_kill = 0x10, + DB_PERF_SEL_DB_SC_tile_fast_ops = 0x11, + DB_PERF_SEL_DB_SC_tile_no_ops = 0x12, + DB_PERF_SEL_DB_SC_tile_tile_rate = 0x13, + DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x14, + DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x15, + DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x16, + DB_PERF_SEL_SC_DB_quad_sends = 0x17, + DB_PERF_SEL_SC_DB_quad_busy = 0x18, + DB_PERF_SEL_SC_DB_quad_squads = 0x19, + DB_PERF_SEL_SC_DB_quad_tiles = 0x1a, + DB_PERF_SEL_SC_DB_quad_pixels = 0x1b, + DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x1c, + DB_PERF_SEL_DB_SC_quad_sends = 0x1d, + DB_PERF_SEL_DB_SC_quad_busy = 0x1e, + DB_PERF_SEL_DB_SC_quad_stalls = 0x1f, + DB_PERF_SEL_DB_SC_quad_tiles = 0x20, + DB_PERF_SEL_DB_SC_quad_lit_quad = 0x21, + DB_PERF_SEL_DB_CB_tile_sends = 0x22, + DB_PERF_SEL_DB_CB_tile_busy = 0x23, + DB_PERF_SEL_DB_CB_tile_stalls = 0x24, + DB_PERF_SEL_SX_DB_quad_sends = 0x25, + DB_PERF_SEL_SX_DB_quad_busy = 0x26, + DB_PERF_SEL_SX_DB_quad_stalls = 0x27, + DB_PERF_SEL_SX_DB_quad_quads = 0x28, + DB_PERF_SEL_SX_DB_quad_pixels = 0x29, + DB_PERF_SEL_SX_DB_quad_exports = 0x2a, + DB_PERF_SEL_SH_quads_outstanding_sum = 0x2b, + DB_PERF_SEL_DB_CB_lquad_sends = 0x2c, + DB_PERF_SEL_DB_CB_lquad_busy = 0x2d, + DB_PERF_SEL_DB_CB_lquad_stalls = 0x2e, + DB_PERF_SEL_DB_CB_lquad_quads = 0x2f, + DB_PERF_SEL_tile_rd_sends = 0x30, + DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x31, + DB_PERF_SEL_quad_rd_sends = 0x32, + DB_PERF_SEL_quad_rd_busy = 0x33, + DB_PERF_SEL_quad_rd_mi_stall = 0x34, + DB_PERF_SEL_quad_rd_rw_collision = 0x35, + DB_PERF_SEL_quad_rd_tag_stall = 0x36, + DB_PERF_SEL_quad_rd_32byte_reqs = 0x37, + DB_PERF_SEL_quad_rd_panic = 0x38, + DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x39, + DB_PERF_SEL_quad_rdret_sends = 0x3a, + DB_PERF_SEL_quad_rdret_busy = 0x3b, + DB_PERF_SEL_tile_wr_sends = 0x3c, + DB_PERF_SEL_tile_wr_acks = 0x3d, + DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x3e, + DB_PERF_SEL_quad_wr_sends = 0x3f, + DB_PERF_SEL_quad_wr_busy = 0x40, + DB_PERF_SEL_quad_wr_mi_stall = 0x41, + DB_PERF_SEL_quad_wr_coherency_stall = 0x42, + DB_PERF_SEL_quad_wr_acks = 0x43, + DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x44, + DB_PERF_SEL_Tile_Cache_misses = 0x45, + DB_PERF_SEL_Tile_Cache_hits = 0x46, + DB_PERF_SEL_Tile_Cache_flushes = 0x47, + DB_PERF_SEL_Tile_Cache_surface_stall = 0x48, + DB_PERF_SEL_Tile_Cache_starves = 0x49, + DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x4a, + DB_PERF_SEL_tcp_dispatcher_reads = 0x4b, + DB_PERF_SEL_tcp_prefetcher_reads = 0x4c, + DB_PERF_SEL_tcp_preloader_reads = 0x4d, + DB_PERF_SEL_tcp_dispatcher_flushes = 0x4e, + DB_PERF_SEL_tcp_prefetcher_flushes = 0x4f, + DB_PERF_SEL_tcp_preloader_flushes = 0x50, + DB_PERF_SEL_Depth_Tile_Cache_sends = 0x51, + DB_PERF_SEL_Depth_Tile_Cache_busy = 0x52, + DB_PERF_SEL_Depth_Tile_Cache_starves = 0x53, + DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x54, + DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x55, + DB_PERF_SEL_Depth_Tile_Cache_misses = 0x56, + DB_PERF_SEL_Depth_Tile_Cache_hits = 0x57, + DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x58, + DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x59, + DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x5a, + DB_PERF_SEL_Depth_Tile_Cache_event = 0x5b, + DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x5c, + DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x5d, + DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x5e, + DB_PERF_SEL_Stencil_Cache_misses = 0x5f, + DB_PERF_SEL_Stencil_Cache_hits = 0x60, + DB_PERF_SEL_Stencil_Cache_flushes = 0x61, + DB_PERF_SEL_Stencil_Cache_starves = 0x62, + DB_PERF_SEL_Stencil_Cache_frees = 0x63, + DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x64, + DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x65, + DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x66, + DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x67, + DB_PERF_SEL_Z_Cache_pmask_misses = 0x68, + DB_PERF_SEL_Z_Cache_pmask_hits = 0x69, + DB_PERF_SEL_Z_Cache_pmask_flushes = 0x6a, + DB_PERF_SEL_Z_Cache_pmask_starves = 0x6b, + DB_PERF_SEL_Z_Cache_frees = 0x6c, + DB_PERF_SEL_Plane_Cache_misses = 0x6d, + DB_PERF_SEL_Plane_Cache_hits = 0x6e, + DB_PERF_SEL_Plane_Cache_flushes = 0x6f, + DB_PERF_SEL_Plane_Cache_starves = 0x70, + DB_PERF_SEL_Plane_Cache_frees = 0x71, + DB_PERF_SEL_flush_expanded_stencil = 0x72, + DB_PERF_SEL_flush_compressed_stencil = 0x73, + DB_PERF_SEL_flush_single_stencil = 0x74, + DB_PERF_SEL_planes_flushed = 0x75, + DB_PERF_SEL_flush_1plane = 0x76, + DB_PERF_SEL_flush_2plane = 0x77, + DB_PERF_SEL_flush_3plane = 0x78, + DB_PERF_SEL_flush_4plane = 0x79, + DB_PERF_SEL_flush_5plane = 0x7a, + DB_PERF_SEL_flush_6plane = 0x7b, + DB_PERF_SEL_flush_7plane = 0x7c, + DB_PERF_SEL_flush_8plane = 0x7d, + DB_PERF_SEL_flush_9plane = 0x7e, + DB_PERF_SEL_flush_10plane = 0x7f, + DB_PERF_SEL_flush_11plane = 0x80, + DB_PERF_SEL_flush_12plane = 0x81, + DB_PERF_SEL_flush_13plane = 0x82, + DB_PERF_SEL_flush_14plane = 0x83, + DB_PERF_SEL_flush_15plane = 0x84, + DB_PERF_SEL_flush_16plane = 0x85, + DB_PERF_SEL_flush_expanded_z = 0x86, + DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x87, + DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x88, + DB_PERF_SEL_dk_tile_sends = 0x89, + DB_PERF_SEL_dk_tile_busy = 0x8a, + DB_PERF_SEL_dk_tile_quad_starves = 0x8b, + DB_PERF_SEL_dk_tile_stalls = 0x8c, + DB_PERF_SEL_dk_squad_sends = 0x8d, + DB_PERF_SEL_dk_squad_busy = 0x8e, + DB_PERF_SEL_dk_squad_stalls = 0x8f, + DB_PERF_SEL_Op_Pipe_Busy = 0x90, + DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x91, + DB_PERF_SEL_qc_busy = 0x92, + DB_PERF_SEL_qc_xfc = 0x93, + DB_PERF_SEL_qc_conflicts = 0x94, + DB_PERF_SEL_qc_full_stall = 0x95, + DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x96, + DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x97, + DB_PERF_SEL_tsc_insert_summarize_stall = 0x98, + DB_PERF_SEL_tl_busy = 0x99, + DB_PERF_SEL_tl_dtc_read_starved = 0x9a, + DB_PERF_SEL_tl_z_fetch_stall = 0x9b, + DB_PERF_SEL_tl_stencil_stall = 0x9c, + DB_PERF_SEL_tl_z_decompress_stall = 0x9d, + DB_PERF_SEL_tl_stencil_locked_stall = 0x9e, + DB_PERF_SEL_tl_events = 0x9f, + DB_PERF_SEL_tl_summarize_squads = 0xa0, + DB_PERF_SEL_tl_flush_expand_squads = 0xa1, + DB_PERF_SEL_tl_expand_squads = 0xa2, + DB_PERF_SEL_tl_preZ_squads = 0xa3, + DB_PERF_SEL_tl_postZ_squads = 0xa4, + DB_PERF_SEL_tl_preZ_noop_squads = 0xa5, + DB_PERF_SEL_tl_postZ_noop_squads = 0xa6, + DB_PERF_SEL_tl_tile_ops = 0xa7, + DB_PERF_SEL_tl_in_xfc = 0xa8, + DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0xa9, + DB_PERF_SEL_tl_in_fast_z_stall = 0xaa, + DB_PERF_SEL_tl_out_xfc = 0xab, + DB_PERF_SEL_tl_out_squads = 0xac, + DB_PERF_SEL_zf_plane_multicycle = 0xad, + DB_PERF_SEL_PostZ_Samples_passing_Z = 0xae, + DB_PERF_SEL_PostZ_Samples_failing_Z = 0xaf, + DB_PERF_SEL_PostZ_Samples_failing_S = 0xb0, + DB_PERF_SEL_PreZ_Samples_passing_Z = 0xb1, + DB_PERF_SEL_PreZ_Samples_failing_Z = 0xb2, + DB_PERF_SEL_PreZ_Samples_failing_S = 0xb3, + DB_PERF_SEL_ts_tc_update_stall = 0xb4, + DB_PERF_SEL_sc_kick_start = 0xb5, + DB_PERF_SEL_sc_kick_end = 0xb6, + DB_PERF_SEL_clock_reg_active = 0xb7, + DB_PERF_SEL_clock_main_active = 0xb8, + DB_PERF_SEL_clock_mem_export_active = 0xb9, + DB_PERF_SEL_esr_ps_out_busy = 0xba, + DB_PERF_SEL_esr_ps_lqf_busy = 0xbb, + DB_PERF_SEL_esr_ps_lqf_stall = 0xbc, + DB_PERF_SEL_etr_out_send = 0xbd, + DB_PERF_SEL_etr_out_busy = 0xbe, + DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0xbf, + DB_PERF_SEL_etr_out_cb_tile_stall = 0xc0, + DB_PERF_SEL_etr_out_esr_stall = 0xc1, + DB_PERF_SEL_esr_ps_sqq_busy = 0xc2, + DB_PERF_SEL_esr_ps_sqq_stall = 0xc3, + DB_PERF_SEL_esr_eot_fwd_busy = 0xc4, + DB_PERF_SEL_esr_eot_fwd_holding_squad = 0xc5, + DB_PERF_SEL_esr_eot_fwd_forward = 0xc6, + DB_PERF_SEL_esr_sqq_zi_busy = 0xc7, + DB_PERF_SEL_esr_sqq_zi_stall = 0xc8, + DB_PERF_SEL_postzl_sq_pt_busy = 0xc9, + DB_PERF_SEL_postzl_sq_pt_stall = 0xca, + DB_PERF_SEL_postzl_se_busy = 0xcb, + DB_PERF_SEL_postzl_se_stall = 0xcc, + DB_PERF_SEL_postzl_partial_launch = 0xcd, + DB_PERF_SEL_postzl_full_launch = 0xce, + DB_PERF_SEL_postzl_partial_waiting = 0xcf, + DB_PERF_SEL_postzl_tile_mem_stall = 0xd0, + DB_PERF_SEL_postzl_tile_init_stall = 0xd1, + DB_PEFF_SEL_prezl_tile_mem_stall = 0xd2, + DB_PERF_SEL_prezl_tile_init_stall = 0xd3, + DB_PERF_SEL_dtt_sm_clash_stall = 0xd4, + DB_PERF_SEL_dtt_sm_slot_stall = 0xd5, + DB_PERF_SEL_dtt_sm_miss_stall = 0xd6, + DB_PERF_SEL_mi_rdreq_busy = 0xd7, + DB_PERF_SEL_mi_rdreq_stall = 0xd8, + DB_PERF_SEL_mi_wrreq_busy = 0xd9, + DB_PERF_SEL_mi_wrreq_stall = 0xda, + DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0xdb, + DB_PERF_SEL_dkg_tile_rate_tile = 0xdc, + DB_PERF_SEL_prezl_src_in_sends = 0xdd, + DB_PERF_SEL_prezl_src_in_stall = 0xde, + DB_PERF_SEL_prezl_src_in_squads = 0xdf, + DB_PERF_SEL_prezl_src_in_squads_unrolled = 0xe0, + DB_PERF_SEL_prezl_src_in_tile_rate = 0xe1, + DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0xe2, + DB_PERF_SEL_prezl_src_out_stall = 0xe3, + DB_PERF_SEL_postzl_src_in_sends = 0xe4, + DB_PERF_SEL_postzl_src_in_stall = 0xe5, + DB_PERF_SEL_postzl_src_in_squads = 0xe6, + DB_PERF_SEL_postzl_src_in_squads_unrolled = 0xe7, + DB_PERF_SEL_postzl_src_in_tile_rate = 0xe8, + DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0xe9, + DB_PERF_SEL_postzl_src_out_stall = 0xea, + DB_PERF_SEL_esr_ps_src_in_sends = 0xeb, + DB_PERF_SEL_esr_ps_src_in_stall = 0xec, + DB_PERF_SEL_esr_ps_src_in_squads = 0xed, + DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0xee, + DB_PERF_SEL_esr_ps_src_in_tile_rate = 0xef, + DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0xf0, + DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate= 0xf1, + DB_PERF_SEL_esr_ps_src_out_stall = 0xf2, + DB_PERF_SEL_depth_bounds_qtiles_culled = 0xf3, + DB_PERF_SEL_PreZ_Samples_failing_DB = 0xf4, + DB_PERF_SEL_PostZ_Samples_failing_DB = 0xf5, + DB_PERF_SEL_flush_compressed = 0xf6, + DB_PERF_SEL_flush_plane_le4 = 0xf7, + DB_PERF_SEL_tiles_z_fully_summarized = 0xf8, + DB_PERF_SEL_tiles_stencil_fully_summarized = 0xf9, + DB_PERF_SEL_tiles_z_clear_on_expclear = 0xfa, + DB_PERF_SEL_tiles_s_clear_on_expclear = 0xfb, + DB_PERF_SEL_tiles_decomp_on_expclear = 0xfc, + DB_PERF_SEL_tiles_compressed_to_decompressed = 0xfd, + DB_PERF_SEL_Op_Pipe_Prez_Busy = 0xfe, + DB_PERF_SEL_Op_Pipe_Postz_Busy = 0xff, + DB_PERF_SEL_di_dt_stall = 0x100, + DB_PERF_SEL_DB_SC_quad_double_quad = 0x101, + DB_PERF_SEL_SX_DB_quad_export_quads = 0x102, + DB_PERF_SEL_SX_DB_quad_double_format = 0x103, + DB_PERF_SEL_SX_DB_quad_fast_format = 0x104, + DB_PERF_SEL_SX_DB_quad_slow_format = 0x105, + DB_PERF_SEL_DB_CB_lquad_export_quads = 0x106, + DB_PERF_SEL_DB_CB_lquad_double_format = 0x107, + DB_PERF_SEL_DB_CB_lquad_fast_format = 0x108, + DB_PERF_SEL_DB_CB_lquad_slow_format = 0x109, +} PerfCounter_Vals; +typedef enum RingCounterControl { + COUNTER_RING_SPLIT = 0x0, + COUNTER_RING_0 = 0x1, + COUNTER_RING_1 = 0x2, +} RingCounterControl; +typedef enum PixelPipeCounterId { + PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x0, + PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x1, + PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x2, + PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x3, + PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x4, + PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x5, + PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x6, + PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x7, +} PixelPipeCounterId; +typedef enum PixelPipeStride { + PIXEL_PIPE_STRIDE_32_BITS = 0x0, + PIXEL_PIPE_STRIDE_64_BITS = 0x1, + PIXEL_PIPE_STRIDE_128_BITS = 0x2, + PIXEL_PIPE_STRIDE_256_BITS = 0x3, +} PixelPipeStride; +typedef enum GB_EDC_DED_MODE { + GB_EDC_DED_MODE_LOG = 0x0, + GB_EDC_DED_MODE_HALT = 0x1, + GB_EDC_DED_MODE_INT_HALT = 0x2, +} GB_EDC_DED_MODE; +#define GB_TILING_CONFIG_TABLE_SIZE 0x20 +#define GB_TILING_CONFIG_MACROTABLE_SIZE 0x10 +typedef enum GRBM_PERF_SEL { + GRBM_PERF_SEL_COUNT = 0x0, + GRBM_PERF_SEL_USER_DEFINED = 0x1, + GRBM_PERF_SEL_GUI_ACTIVE = 0x2, + GRBM_PERF_SEL_CP_BUSY = 0x3, + GRBM_PERF_SEL_CP_COHER_BUSY = 0x4, + GRBM_PERF_SEL_CP_DMA_BUSY = 0x5, + GRBM_PERF_SEL_CB_BUSY = 0x6, + GRBM_PERF_SEL_DB_BUSY = 0x7, + GRBM_PERF_SEL_PA_BUSY = 0x8, + GRBM_PERF_SEL_SC_BUSY = 0x9, + GRBM_PERF_SEL_RESERVED_6 = 0xa, + GRBM_PERF_SEL_SPI_BUSY = 0xb, + GRBM_PERF_SEL_SX_BUSY = 0xc, + GRBM_PERF_SEL_TA_BUSY = 0xd, + GRBM_PERF_SEL_CB_CLEAN = 0xe, + GRBM_PERF_SEL_DB_CLEAN = 0xf, + GRBM_PERF_SEL_RESERVED_5 = 0x10, + GRBM_PERF_SEL_VGT_BUSY = 0x11, + GRBM_PERF_SEL_RESERVED_4 = 0x12, + GRBM_PERF_SEL_RESERVED_3 = 0x13, + GRBM_PERF_SEL_RESERVED_2 = 0x14, + GRBM_PERF_SEL_RESERVED_1 = 0x15, + GRBM_PERF_SEL_RESERVED_0 = 0x16, + GRBM_PERF_SEL_IA_BUSY = 0x17, + GRBM_PERF_SEL_IA_NO_DMA_BUSY = 0x18, + GRBM_PERF_SEL_GDS_BUSY = 0x19, + GRBM_PERF_SEL_BCI_BUSY = 0x1a, + GRBM_PERF_SEL_RLC_BUSY = 0x1b, + GRBM_PERF_SEL_TC_BUSY = 0x1c, + GRBM_PERF_SEL_CPG_BUSY = 0x1d, + GRBM_PERF_SEL_CPC_BUSY = 0x1e, + GRBM_PERF_SEL_CPF_BUSY = 0x1f, + GRBM_PERF_SEL_WD_BUSY = 0x20, + GRBM_PERF_SEL_WD_NO_DMA_BUSY = 0x21, +} GRBM_PERF_SEL; +typedef enum GRBM_SE0_PERF_SEL { + GRBM_SE0_PERF_SEL_COUNT = 0x0, + GRBM_SE0_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE0_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE0_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE0_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE0_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE0_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE0_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE0_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE0_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE0_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE0_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE0_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE0_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE0_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE0_PERF_SEL; +typedef enum GRBM_SE1_PERF_SEL { + GRBM_SE1_PERF_SEL_COUNT = 0x0, + GRBM_SE1_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE1_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE1_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE1_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE1_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE1_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE1_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE1_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE1_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE1_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE1_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE1_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE1_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE1_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE1_PERF_SEL; +typedef enum GRBM_SE2_PERF_SEL { + GRBM_SE2_PERF_SEL_COUNT = 0x0, + GRBM_SE2_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE2_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE2_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE2_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE2_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE2_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE2_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE2_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE2_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE2_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE2_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE2_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE2_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE2_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE2_PERF_SEL; +typedef enum GRBM_SE3_PERF_SEL { + GRBM_SE3_PERF_SEL_COUNT = 0x0, + GRBM_SE3_PERF_SEL_USER_DEFINED = 0x1, + GRBM_SE3_PERF_SEL_CB_BUSY = 0x2, + GRBM_SE3_PERF_SEL_DB_BUSY = 0x3, + GRBM_SE3_PERF_SEL_SC_BUSY = 0x4, + GRBM_SE3_PERF_SEL_RESERVED_1 = 0x5, + GRBM_SE3_PERF_SEL_SPI_BUSY = 0x6, + GRBM_SE3_PERF_SEL_SX_BUSY = 0x7, + GRBM_SE3_PERF_SEL_TA_BUSY = 0x8, + GRBM_SE3_PERF_SEL_CB_CLEAN = 0x9, + GRBM_SE3_PERF_SEL_DB_CLEAN = 0xa, + GRBM_SE3_PERF_SEL_RESERVED_0 = 0xb, + GRBM_SE3_PERF_SEL_PA_BUSY = 0xc, + GRBM_SE3_PERF_SEL_VGT_BUSY = 0xd, + GRBM_SE3_PERF_SEL_BCI_BUSY = 0xe, +} GRBM_SE3_PERF_SEL; +typedef enum SU_PERFCNT_SEL { + PERF_PAPC_PASX_REQ = 0x0, + PERF_PAPC_PASX_DISABLE_PIPE = 0x1, + PERF_PAPC_PASX_FIRST_VECTOR = 0x2, + PERF_PAPC_PASX_SECOND_VECTOR = 0x3, + PERF_PAPC_PASX_FIRST_DEAD = 0x4, + PERF_PAPC_PASX_SECOND_DEAD = 0x5, + PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x6, + PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x7, + PERF_PAPC_PA_INPUT_PRIM = 0x8, + PERF_PAPC_PA_INPUT_NULL_PRIM = 0x9, + PERF_PAPC_PA_INPUT_EVENT_FLAG = 0xa, + PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0xb, + PERF_PAPC_PA_INPUT_END_OF_PACKET = 0xc, + PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0xd, + PERF_PAPC_CLPR_CULL_PRIM = 0xe, + PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0xf, + PERF_PAPC_CLPR_VV_CULL_PRIM = 0x10, + PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x11, + PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x12, + PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x13, + PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x14, + PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x15, + PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x16, + PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x17, + PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x18, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x19, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x1a, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x1b, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x1c, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x1d, + PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x1e, + PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x1f, + PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x20, + PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x21, + PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x22, + PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x23, + PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x24, + PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x25, + PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x26, + PERF_PAPC_CLSM_NULL_PRIM = 0x27, + PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x28, + PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x29, + PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x2a, + PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x2b, + PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x2c, + PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x2d, + PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x2e, + PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x2f, + PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x30, + PERF_PAPC_SU_INPUT_PRIM = 0x31, + PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x32, + PERF_PAPC_SU_INPUT_NULL_PRIM = 0x33, + PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x34, + PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x35, + PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x36, + PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x37, + PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x38, + PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x39, + PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x3a, + PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x3b, + PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x3c, + PERF_PAPC_SU_OUTPUT_PRIM = 0x3d, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x3e, + PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x3f, + PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x40, + PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x41, + PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x42, + PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x43, + PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x44, + PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x45, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x46, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x47, + PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x48, + PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x49, + PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x4a, + PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x4b, + PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x4c, + PERF_PAPC_PASX_REQ_IDLE = 0x4d, + PERF_PAPC_PASX_REQ_BUSY = 0x4e, + PERF_PAPC_PASX_REQ_STALLED = 0x4f, + PERF_PAPC_PASX_REC_IDLE = 0x50, + PERF_PAPC_PASX_REC_BUSY = 0x51, + PERF_PAPC_PASX_REC_STARVED_SX = 0x52, + PERF_PAPC_PASX_REC_STALLED = 0x53, + PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x54, + PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x55, + PERF_PAPC_CCGSM_IDLE = 0x56, + PERF_PAPC_CCGSM_BUSY = 0x57, + PERF_PAPC_CCGSM_STALLED = 0x58, + PERF_PAPC_CLPRIM_IDLE = 0x59, + PERF_PAPC_CLPRIM_BUSY = 0x5a, + PERF_PAPC_CLPRIM_STALLED = 0x5b, + PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x5c, + PERF_PAPC_CLIPSM_IDLE = 0x5d, + PERF_PAPC_CLIPSM_BUSY = 0x5e, + PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x5f, + PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x60, + PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x61, + PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x62, + PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x63, + PERF_PAPC_CLIPGA_IDLE = 0x64, + PERF_PAPC_CLIPGA_BUSY = 0x65, + PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x66, + PERF_PAPC_CLIPGA_STALLED = 0x67, + PERF_PAPC_CLIP_IDLE = 0x68, + PERF_PAPC_CLIP_BUSY = 0x69, + PERF_PAPC_SU_IDLE = 0x6a, + PERF_PAPC_SU_BUSY = 0x6b, + PERF_PAPC_SU_STARVED_CLIP = 0x6c, + PERF_PAPC_SU_STALLED_SC = 0x6d, + PERF_PAPC_CL_DYN_SCLK_VLD = 0x6e, + PERF_PAPC_SU_DYN_SCLK_VLD = 0x6f, + PERF_PAPC_PA_REG_SCLK_VLD = 0x70, + PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x71, + PERF_PAPC_PASX_SE0_REQ = 0x72, + PERF_PAPC_PASX_SE1_REQ = 0x73, + PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x74, + PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x75, + PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x76, + PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x77, + PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x78, + PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x79, + PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x7a, + PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x7b, + PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x7c, + PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x7d, + PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x7e, + PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x7f, + PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x80, + PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x81, + PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x82, + PERF_PAPC_SU_SE0_STALLED_SC = 0x83, + PERF_PAPC_SU_SE1_STALLED_SC = 0x84, + PERF_PAPC_SU_SE01_STALLED_SC = 0x85, + PERF_PAPC_CLSM_CLIPPING_PRIM = 0x86, + PERF_PAPC_SU_CULLED_PRIM = 0x87, + PERF_PAPC_SU_OUTPUT_EOPG = 0x88, + PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x89, + PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x8a, + PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x8b, + PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x8c, + PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x8d, + PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x8e, + PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x8f, + PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x90, + PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x91, + PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x92, + PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x93, + PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x94, + PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x95, + PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x96, + PERF_PAPC_SU_SE2_STALLED_SC = 0x97, + PERF_PAPC_SU_SE3_STALLED_SC = 0x98, +} SU_PERFCNT_SEL; +typedef enum SC_PERFCNT_SEL { + SC_SRPS_WINDOW_VALID = 0x0, + SC_PSSW_WINDOW_VALID = 0x1, + SC_TPQZ_WINDOW_VALID = 0x2, + SC_QZQP_WINDOW_VALID = 0x3, + SC_TRPK_WINDOW_VALID = 0x4, + SC_SRPS_WINDOW_VALID_BUSY = 0x5, + SC_PSSW_WINDOW_VALID_BUSY = 0x6, + SC_TPQZ_WINDOW_VALID_BUSY = 0x7, + SC_QZQP_WINDOW_VALID_BUSY = 0x8, + SC_TRPK_WINDOW_VALID_BUSY = 0x9, + SC_STARVED_BY_PA = 0xa, + SC_STALLED_BY_PRIMFIFO = 0xb, + SC_STALLED_BY_DB_TILE = 0xc, + SC_STARVED_BY_DB_TILE = 0xd, + SC_STALLED_BY_TILEORDERFIFO = 0xe, + SC_STALLED_BY_TILEFIFO = 0xf, + SC_STALLED_BY_DB_QUAD = 0x10, + SC_STARVED_BY_DB_QUAD = 0x11, + SC_STALLED_BY_QUADFIFO = 0x12, + SC_STALLED_BY_BCI = 0x13, + SC_STALLED_BY_SPI = 0x14, + SC_SCISSOR_DISCARD = 0x15, + SC_BB_DISCARD = 0x16, + SC_SUPERTILE_COUNT = 0x17, + SC_SUPERTILE_PER_PRIM_H0 = 0x18, + SC_SUPERTILE_PER_PRIM_H1 = 0x19, + SC_SUPERTILE_PER_PRIM_H2 = 0x1a, + SC_SUPERTILE_PER_PRIM_H3 = 0x1b, + SC_SUPERTILE_PER_PRIM_H4 = 0x1c, + SC_SUPERTILE_PER_PRIM_H5 = 0x1d, + SC_SUPERTILE_PER_PRIM_H6 = 0x1e, + SC_SUPERTILE_PER_PRIM_H7 = 0x1f, + SC_SUPERTILE_PER_PRIM_H8 = 0x20, + SC_SUPERTILE_PER_PRIM_H9 = 0x21, + SC_SUPERTILE_PER_PRIM_H10 = 0x22, + SC_SUPERTILE_PER_PRIM_H11 = 0x23, + SC_SUPERTILE_PER_PRIM_H12 = 0x24, + SC_SUPERTILE_PER_PRIM_H13 = 0x25, + SC_SUPERTILE_PER_PRIM_H14 = 0x26, + SC_SUPERTILE_PER_PRIM_H15 = 0x27, + SC_SUPERTILE_PER_PRIM_H16 = 0x28, + SC_TILE_PER_PRIM_H0 = 0x29, + SC_TILE_PER_PRIM_H1 = 0x2a, + SC_TILE_PER_PRIM_H2 = 0x2b, + SC_TILE_PER_PRIM_H3 = 0x2c, + SC_TILE_PER_PRIM_H4 = 0x2d, + SC_TILE_PER_PRIM_H5 = 0x2e, + SC_TILE_PER_PRIM_H6 = 0x2f, + SC_TILE_PER_PRIM_H7 = 0x30, + SC_TILE_PER_PRIM_H8 = 0x31, + SC_TILE_PER_PRIM_H9 = 0x32, + SC_TILE_PER_PRIM_H10 = 0x33, + SC_TILE_PER_PRIM_H11 = 0x34, + SC_TILE_PER_PRIM_H12 = 0x35, + SC_TILE_PER_PRIM_H13 = 0x36, + SC_TILE_PER_PRIM_H14 = 0x37, + SC_TILE_PER_PRIM_H15 = 0x38, + SC_TILE_PER_PRIM_H16 = 0x39, + SC_TILE_PER_SUPERTILE_H0 = 0x3a, + SC_TILE_PER_SUPERTILE_H1 = 0x3b, + SC_TILE_PER_SUPERTILE_H2 = 0x3c, + SC_TILE_PER_SUPERTILE_H3 = 0x3d, + SC_TILE_PER_SUPERTILE_H4 = 0x3e, + SC_TILE_PER_SUPERTILE_H5 = 0x3f, + SC_TILE_PER_SUPERTILE_H6 = 0x40, + SC_TILE_PER_SUPERTILE_H7 = 0x41, + SC_TILE_PER_SUPERTILE_H8 = 0x42, + SC_TILE_PER_SUPERTILE_H9 = 0x43, + SC_TILE_PER_SUPERTILE_H10 = 0x44, + SC_TILE_PER_SUPERTILE_H11 = 0x45, + SC_TILE_PER_SUPERTILE_H12 = 0x46, + SC_TILE_PER_SUPERTILE_H13 = 0x47, + SC_TILE_PER_SUPERTILE_H14 = 0x48, + SC_TILE_PER_SUPERTILE_H15 = 0x49, + SC_TILE_PER_SUPERTILE_H16 = 0x4a, + SC_TILE_PICKED_H1 = 0x4b, + SC_TILE_PICKED_H2 = 0x4c, + SC_TILE_PICKED_H3 = 0x4d, + SC_TILE_PICKED_H4 = 0x4e, + SC_QZ0_MULTI_GPU_TILE_DISCARD = 0x4f, + SC_QZ1_MULTI_GPU_TILE_DISCARD = 0x50, + SC_QZ2_MULTI_GPU_TILE_DISCARD = 0x51, + SC_QZ3_MULTI_GPU_TILE_DISCARD = 0x52, + SC_QZ0_TILE_COUNT = 0x53, + SC_QZ1_TILE_COUNT = 0x54, + SC_QZ2_TILE_COUNT = 0x55, + SC_QZ3_TILE_COUNT = 0x56, + SC_QZ0_TILE_COVERED_COUNT = 0x57, + SC_QZ1_TILE_COVERED_COUNT = 0x58, + SC_QZ2_TILE_COVERED_COUNT = 0x59, + SC_QZ3_TILE_COVERED_COUNT = 0x5a, + SC_QZ0_TILE_NOT_COVERED_COUNT = 0x5b, + SC_QZ1_TILE_NOT_COVERED_COUNT = 0x5c, + SC_QZ2_TILE_NOT_COVERED_COUNT = 0x5d, + SC_QZ3_TILE_NOT_COVERED_COUNT = 0x5e, + SC_QZ0_QUAD_PER_TILE_H0 = 0x5f, + SC_QZ0_QUAD_PER_TILE_H1 = 0x60, + SC_QZ0_QUAD_PER_TILE_H2 = 0x61, + SC_QZ0_QUAD_PER_TILE_H3 = 0x62, + SC_QZ0_QUAD_PER_TILE_H4 = 0x63, + SC_QZ0_QUAD_PER_TILE_H5 = 0x64, + SC_QZ0_QUAD_PER_TILE_H6 = 0x65, + SC_QZ0_QUAD_PER_TILE_H7 = 0x66, + SC_QZ0_QUAD_PER_TILE_H8 = 0x67, + SC_QZ0_QUAD_PER_TILE_H9 = 0x68, + SC_QZ0_QUAD_PER_TILE_H10 = 0x69, + SC_QZ0_QUAD_PER_TILE_H11 = 0x6a, + SC_QZ0_QUAD_PER_TILE_H12 = 0x6b, + SC_QZ0_QUAD_PER_TILE_H13 = 0x6c, + SC_QZ0_QUAD_PER_TILE_H14 = 0x6d, + SC_QZ0_QUAD_PER_TILE_H15 = 0x6e, + SC_QZ0_QUAD_PER_TILE_H16 = 0x6f, + SC_QZ1_QUAD_PER_TILE_H0 = 0x70, + SC_QZ1_QUAD_PER_TILE_H1 = 0x71, + SC_QZ1_QUAD_PER_TILE_H2 = 0x72, + SC_QZ1_QUAD_PER_TILE_H3 = 0x73, + SC_QZ1_QUAD_PER_TILE_H4 = 0x74, + SC_QZ1_QUAD_PER_TILE_H5 = 0x75, + SC_QZ1_QUAD_PER_TILE_H6 = 0x76, + SC_QZ1_QUAD_PER_TILE_H7 = 0x77, + SC_QZ1_QUAD_PER_TILE_H8 = 0x78, + SC_QZ1_QUAD_PER_TILE_H9 = 0x79, + SC_QZ1_QUAD_PER_TILE_H10 = 0x7a, + SC_QZ1_QUAD_PER_TILE_H11 = 0x7b, + SC_QZ1_QUAD_PER_TILE_H12 = 0x7c, + SC_QZ1_QUAD_PER_TILE_H13 = 0x7d, + SC_QZ1_QUAD_PER_TILE_H14 = 0x7e, + SC_QZ1_QUAD_PER_TILE_H15 = 0x7f, + SC_QZ1_QUAD_PER_TILE_H16 = 0x80, + SC_QZ2_QUAD_PER_TILE_H0 = 0x81, + SC_QZ2_QUAD_PER_TILE_H1 = 0x82, + SC_QZ2_QUAD_PER_TILE_H2 = 0x83, + SC_QZ2_QUAD_PER_TILE_H3 = 0x84, + SC_QZ2_QUAD_PER_TILE_H4 = 0x85, + SC_QZ2_QUAD_PER_TILE_H5 = 0x86, + SC_QZ2_QUAD_PER_TILE_H6 = 0x87, + SC_QZ2_QUAD_PER_TILE_H7 = 0x88, + SC_QZ2_QUAD_PER_TILE_H8 = 0x89, + SC_QZ2_QUAD_PER_TILE_H9 = 0x8a, + SC_QZ2_QUAD_PER_TILE_H10 = 0x8b, + SC_QZ2_QUAD_PER_TILE_H11 = 0x8c, + SC_QZ2_QUAD_PER_TILE_H12 = 0x8d, + SC_QZ2_QUAD_PER_TILE_H13 = 0x8e, + SC_QZ2_QUAD_PER_TILE_H14 = 0x8f, + SC_QZ2_QUAD_PER_TILE_H15 = 0x90, + SC_QZ2_QUAD_PER_TILE_H16 = 0x91, + SC_QZ3_QUAD_PER_TILE_H0 = 0x92, + SC_QZ3_QUAD_PER_TILE_H1 = 0x93, + SC_QZ3_QUAD_PER_TILE_H2 = 0x94, + SC_QZ3_QUAD_PER_TILE_H3 = 0x95, + SC_QZ3_QUAD_PER_TILE_H4 = 0x96, + SC_QZ3_QUAD_PER_TILE_H5 = 0x97, + SC_QZ3_QUAD_PER_TILE_H6 = 0x98, + SC_QZ3_QUAD_PER_TILE_H7 = 0x99, + SC_QZ3_QUAD_PER_TILE_H8 = 0x9a, + SC_QZ3_QUAD_PER_TILE_H9 = 0x9b, + SC_QZ3_QUAD_PER_TILE_H10 = 0x9c, + SC_QZ3_QUAD_PER_TILE_H11 = 0x9d, + SC_QZ3_QUAD_PER_TILE_H12 = 0x9e, + SC_QZ3_QUAD_PER_TILE_H13 = 0x9f, + SC_QZ3_QUAD_PER_TILE_H14 = 0xa0, + SC_QZ3_QUAD_PER_TILE_H15 = 0xa1, + SC_QZ3_QUAD_PER_TILE_H16 = 0xa2, + SC_QZ0_QUAD_COUNT = 0xa3, + SC_QZ1_QUAD_COUNT = 0xa4, + SC_QZ2_QUAD_COUNT = 0xa5, + SC_QZ3_QUAD_COUNT = 0xa6, + SC_P0_HIZ_TILE_COUNT = 0xa7, + SC_P1_HIZ_TILE_COUNT = 0xa8, + SC_P2_HIZ_TILE_COUNT = 0xa9, + SC_P3_HIZ_TILE_COUNT = 0xaa, + SC_P0_HIZ_QUAD_PER_TILE_H0 = 0xab, + SC_P0_HIZ_QUAD_PER_TILE_H1 = 0xac, + SC_P0_HIZ_QUAD_PER_TILE_H2 = 0xad, + SC_P0_HIZ_QUAD_PER_TILE_H3 = 0xae, + SC_P0_HIZ_QUAD_PER_TILE_H4 = 0xaf, + SC_P0_HIZ_QUAD_PER_TILE_H5 = 0xb0, + SC_P0_HIZ_QUAD_PER_TILE_H6 = 0xb1, + SC_P0_HIZ_QUAD_PER_TILE_H7 = 0xb2, + SC_P0_HIZ_QUAD_PER_TILE_H8 = 0xb3, + SC_P0_HIZ_QUAD_PER_TILE_H9 = 0xb4, + SC_P0_HIZ_QUAD_PER_TILE_H10 = 0xb5, + SC_P0_HIZ_QUAD_PER_TILE_H11 = 0xb6, + SC_P0_HIZ_QUAD_PER_TILE_H12 = 0xb7, + SC_P0_HIZ_QUAD_PER_TILE_H13 = 0xb8, + SC_P0_HIZ_QUAD_PER_TILE_H14 = 0xb9, + SC_P0_HIZ_QUAD_PER_TILE_H15 = 0xba, + SC_P0_HIZ_QUAD_PER_TILE_H16 = 0xbb, + SC_P1_HIZ_QUAD_PER_TILE_H0 = 0xbc, + SC_P1_HIZ_QUAD_PER_TILE_H1 = 0xbd, + SC_P1_HIZ_QUAD_PER_TILE_H2 = 0xbe, + SC_P1_HIZ_QUAD_PER_TILE_H3 = 0xbf, + SC_P1_HIZ_QUAD_PER_TILE_H4 = 0xc0, + SC_P1_HIZ_QUAD_PER_TILE_H5 = 0xc1, + SC_P1_HIZ_QUAD_PER_TILE_H6 = 0xc2, + SC_P1_HIZ_QUAD_PER_TILE_H7 = 0xc3, + SC_P1_HIZ_QUAD_PER_TILE_H8 = 0xc4, + SC_P1_HIZ_QUAD_PER_TILE_H9 = 0xc5, + SC_P1_HIZ_QUAD_PER_TILE_H10 = 0xc6, + SC_P1_HIZ_QUAD_PER_TILE_H11 = 0xc7, + SC_P1_HIZ_QUAD_PER_TILE_H12 = 0xc8, + SC_P1_HIZ_QUAD_PER_TILE_H13 = 0xc9, + SC_P1_HIZ_QUAD_PER_TILE_H14 = 0xca, + SC_P1_HIZ_QUAD_PER_TILE_H15 = 0xcb, + SC_P1_HIZ_QUAD_PER_TILE_H16 = 0xcc, + SC_P2_HIZ_QUAD_PER_TILE_H0 = 0xcd, + SC_P2_HIZ_QUAD_PER_TILE_H1 = 0xce, + SC_P2_HIZ_QUAD_PER_TILE_H2 = 0xcf, + SC_P2_HIZ_QUAD_PER_TILE_H3 = 0xd0, + SC_P2_HIZ_QUAD_PER_TILE_H4 = 0xd1, + SC_P2_HIZ_QUAD_PER_TILE_H5 = 0xd2, + SC_P2_HIZ_QUAD_PER_TILE_H6 = 0xd3, + SC_P2_HIZ_QUAD_PER_TILE_H7 = 0xd4, + SC_P2_HIZ_QUAD_PER_TILE_H8 = 0xd5, + SC_P2_HIZ_QUAD_PER_TILE_H9 = 0xd6, + SC_P2_HIZ_QUAD_PER_TILE_H10 = 0xd7, + SC_P2_HIZ_QUAD_PER_TILE_H11 = 0xd8, + SC_P2_HIZ_QUAD_PER_TILE_H12 = 0xd9, + SC_P2_HIZ_QUAD_PER_TILE_H13 = 0xda, + SC_P2_HIZ_QUAD_PER_TILE_H14 = 0xdb, + SC_P2_HIZ_QUAD_PER_TILE_H15 = 0xdc, + SC_P2_HIZ_QUAD_PER_TILE_H16 = 0xdd, + SC_P3_HIZ_QUAD_PER_TILE_H0 = 0xde, + SC_P3_HIZ_QUAD_PER_TILE_H1 = 0xdf, + SC_P3_HIZ_QUAD_PER_TILE_H2 = 0xe0, + SC_P3_HIZ_QUAD_PER_TILE_H3 = 0xe1, + SC_P3_HIZ_QUAD_PER_TILE_H4 = 0xe2, + SC_P3_HIZ_QUAD_PER_TILE_H5 = 0xe3, + SC_P3_HIZ_QUAD_PER_TILE_H6 = 0xe4, + SC_P3_HIZ_QUAD_PER_TILE_H7 = 0xe5, + SC_P3_HIZ_QUAD_PER_TILE_H8 = 0xe6, + SC_P3_HIZ_QUAD_PER_TILE_H9 = 0xe7, + SC_P3_HIZ_QUAD_PER_TILE_H10 = 0xe8, + SC_P3_HIZ_QUAD_PER_TILE_H11 = 0xe9, + SC_P3_HIZ_QUAD_PER_TILE_H12 = 0xea, + SC_P3_HIZ_QUAD_PER_TILE_H13 = 0xeb, + SC_P3_HIZ_QUAD_PER_TILE_H14 = 0xec, + SC_P3_HIZ_QUAD_PER_TILE_H15 = 0xed, + SC_P3_HIZ_QUAD_PER_TILE_H16 = 0xee, + SC_P0_HIZ_QUAD_COUNT = 0xef, + SC_P1_HIZ_QUAD_COUNT = 0xf0, + SC_P2_HIZ_QUAD_COUNT = 0xf1, + SC_P3_HIZ_QUAD_COUNT = 0xf2, + SC_P0_DETAIL_QUAD_COUNT = 0xf3, + SC_P1_DETAIL_QUAD_COUNT = 0xf4, + SC_P2_DETAIL_QUAD_COUNT = 0xf5, + SC_P3_DETAIL_QUAD_COUNT = 0xf6, + SC_P0_DETAIL_QUAD_WITH_1_PIX = 0xf7, + SC_P0_DETAIL_QUAD_WITH_2_PIX = 0xf8, + SC_P0_DETAIL_QUAD_WITH_3_PIX = 0xf9, + SC_P0_DETAIL_QUAD_WITH_4_PIX = 0xfa, + SC_P1_DETAIL_QUAD_WITH_1_PIX = 0xfb, + SC_P1_DETAIL_QUAD_WITH_2_PIX = 0xfc, + SC_P1_DETAIL_QUAD_WITH_3_PIX = 0xfd, + SC_P1_DETAIL_QUAD_WITH_4_PIX = 0xfe, + SC_P2_DETAIL_QUAD_WITH_1_PIX = 0xff, + SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x100, + SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x101, + SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x102, + SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x103, + SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x104, + SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x105, + SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x106, + SC_EARLYZ_QUAD_COUNT = 0x107, + SC_EARLYZ_QUAD_WITH_1_PIX = 0x108, + SC_EARLYZ_QUAD_WITH_2_PIX = 0x109, + SC_EARLYZ_QUAD_WITH_3_PIX = 0x10a, + SC_EARLYZ_QUAD_WITH_4_PIX = 0x10b, + SC_PKR_QUAD_PER_ROW_H1 = 0x10c, + SC_PKR_QUAD_PER_ROW_H2 = 0x10d, + SC_PKR_4X2_QUAD_SPLIT = 0x10e, + SC_PKR_4X2_FILL_QUAD = 0x10f, + SC_PKR_END_OF_VECTOR = 0x110, + SC_PKR_CONTROL_XFER = 0x111, + SC_PKR_DBHANG_FORCE_EOV = 0x112, + SC_REG_SCLK_BUSY = 0x113, + SC_GRP0_DYN_SCLK_BUSY = 0x114, + SC_GRP1_DYN_SCLK_BUSY = 0x115, + SC_GRP2_DYN_SCLK_BUSY = 0x116, + SC_GRP3_DYN_SCLK_BUSY = 0x117, + SC_GRP4_DYN_SCLK_BUSY = 0x118, + SC_PA0_SC_DATA_FIFO_RD = 0x119, + SC_PA0_SC_DATA_FIFO_WE = 0x11a, + SC_PA1_SC_DATA_FIFO_RD = 0x11b, + SC_PA1_SC_DATA_FIFO_WE = 0x11c, + SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x11d, + SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x11e, + SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x11f, + SC_PS_ARB_STALLED_FROM_BELOW = 0x120, + SC_PS_ARB_STARVED_FROM_ABOVE = 0x121, + SC_PS_ARB_SC_BUSY = 0x122, + SC_PS_ARB_PA_SC_BUSY = 0x123, + SC_PA2_SC_DATA_FIFO_RD = 0x124, + SC_PA2_SC_DATA_FIFO_WE = 0x125, + SC_PA3_SC_DATA_FIFO_RD = 0x126, + SC_PA3_SC_DATA_FIFO_WE = 0x127, + SC_PA_SC_DEALLOC_0_0_WE = 0x128, + SC_PA_SC_DEALLOC_0_1_WE = 0x129, + SC_PA_SC_DEALLOC_1_0_WE = 0x12a, + SC_PA_SC_DEALLOC_1_1_WE = 0x12b, + SC_PA_SC_DEALLOC_2_0_WE = 0x12c, + SC_PA_SC_DEALLOC_2_1_WE = 0x12d, + SC_PA_SC_DEALLOC_3_0_WE = 0x12e, + SC_PA_SC_DEALLOC_3_1_WE = 0x12f, + SC_PA0_SC_EOP_WE = 0x130, + SC_PA0_SC_EOPG_WE = 0x131, + SC_PA0_SC_EVENT_WE = 0x132, + SC_PA1_SC_EOP_WE = 0x133, + SC_PA1_SC_EOPG_WE = 0x134, + SC_PA1_SC_EVENT_WE = 0x135, + SC_PA2_SC_EOP_WE = 0x136, + SC_PA2_SC_EOPG_WE = 0x137, + SC_PA2_SC_EVENT_WE = 0x138, + SC_PA3_SC_EOP_WE = 0x139, + SC_PA3_SC_EOPG_WE = 0x13a, + SC_PA3_SC_EVENT_WE = 0x13b, + SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x13c, + SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x13d, + SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x13e, + SC_PS_ARB_EOP_POP_SYNC_POP = 0x13f, + SC_PS_ARB_EVENT_SYNC_POP = 0x140, + SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x141, + SC_PA0_SC_FPOV_WE = 0x142, + SC_PA1_SC_FPOV_WE = 0x143, + SC_PA2_SC_FPOV_WE = 0x144, + SC_PA3_SC_FPOV_WE = 0x145, + SC_PA0_SC_LPOV_WE = 0x146, + SC_PA1_SC_LPOV_WE = 0x147, + SC_PA2_SC_LPOV_WE = 0x148, + SC_PA3_SC_LPOV_WE = 0x149, + SC_SC_SPI_DEALLOC_0_0 = 0x14a, + SC_SC_SPI_DEALLOC_0_1 = 0x14b, + SC_SC_SPI_DEALLOC_0_2 = 0x14c, + SC_SC_SPI_DEALLOC_1_0 = 0x14d, + SC_SC_SPI_DEALLOC_1_1 = 0x14e, + SC_SC_SPI_DEALLOC_1_2 = 0x14f, + SC_SC_SPI_DEALLOC_2_0 = 0x150, + SC_SC_SPI_DEALLOC_2_1 = 0x151, + SC_SC_SPI_DEALLOC_2_2 = 0x152, + SC_SC_SPI_DEALLOC_3_0 = 0x153, + SC_SC_SPI_DEALLOC_3_1 = 0x154, + SC_SC_SPI_DEALLOC_3_2 = 0x155, + SC_SC_SPI_FPOV_0 = 0x156, + SC_SC_SPI_FPOV_1 = 0x157, + SC_SC_SPI_FPOV_2 = 0x158, + SC_SC_SPI_FPOV_3 = 0x159, + SC_SC_SPI_EVENT = 0x15a, + SC_PS_TS_EVENT_FIFO_PUSH = 0x15b, + SC_PS_TS_EVENT_FIFO_POP = 0x15c, + SC_PS_CTX_DONE_FIFO_PUSH = 0x15d, + SC_PS_CTX_DONE_FIFO_POP = 0x15e, + SC_MULTICYCLE_BUBBLE_FREEZE = 0x15f, + SC_EOP_SYNC_WINDOW = 0x160, + SC_PA0_SC_NULL_WE = 0x161, + SC_PA0_SC_NULL_DEALLOC_WE = 0x162, + SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x163, + SC_PA0_SC_DATA_FIFO_EOP_RD = 0x164, + SC_PA0_SC_DEALLOC_0_RD = 0x165, + SC_PA0_SC_DEALLOC_1_RD = 0x166, + SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x167, + SC_PA1_SC_DATA_FIFO_EOP_RD = 0x168, + SC_PA1_SC_DEALLOC_0_RD = 0x169, + SC_PA1_SC_DEALLOC_1_RD = 0x16a, + SC_PA1_SC_NULL_WE = 0x16b, + SC_PA1_SC_NULL_DEALLOC_WE = 0x16c, + SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x16d, + SC_PA2_SC_DATA_FIFO_EOP_RD = 0x16e, + SC_PA2_SC_DEALLOC_0_RD = 0x16f, + SC_PA2_SC_DEALLOC_1_RD = 0x170, + SC_PA2_SC_NULL_WE = 0x171, + SC_PA2_SC_NULL_DEALLOC_WE = 0x172, + SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x173, + SC_PA3_SC_DATA_FIFO_EOP_RD = 0x174, + SC_PA3_SC_DEALLOC_0_RD = 0x175, + SC_PA3_SC_DEALLOC_1_RD = 0x176, + SC_PA3_SC_NULL_WE = 0x177, + SC_PA3_SC_NULL_DEALLOC_WE = 0x178, + SC_PS_PA0_SC_FIFO_EMPTY = 0x179, + SC_PS_PA0_SC_FIFO_FULL = 0x17a, + SC_PA0_PS_DATA_SEND = 0x17b, + SC_PS_PA1_SC_FIFO_EMPTY = 0x17c, + SC_PS_PA1_SC_FIFO_FULL = 0x17d, + SC_PA1_PS_DATA_SEND = 0x17e, + SC_PS_PA2_SC_FIFO_EMPTY = 0x17f, + SC_PS_PA2_SC_FIFO_FULL = 0x180, + SC_PA2_PS_DATA_SEND = 0x181, + SC_PS_PA3_SC_FIFO_EMPTY = 0x182, + SC_PS_PA3_SC_FIFO_FULL = 0x183, + SC_PA3_PS_DATA_SEND = 0x184, + SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x185, + SC_BUSY_CNT_NOT_ZERO = 0x186, + SC_BM_BUSY = 0x187, + SC_BACKEND_BUSY = 0x188, + SC_SCF_SCB_INTERFACE_BUSY = 0x189, + SC_SCB_BUSY = 0x18a, + SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x18b, + SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x18c, +} SC_PERFCNT_SEL; +typedef enum SePairXsel { + RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x3, +} SePairXsel; +typedef enum SePairYsel { + RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x3, +} SePairYsel; +typedef enum SePairMap { + RASTER_CONFIG_SE_PAIR_MAP_0 = 0x0, + RASTER_CONFIG_SE_PAIR_MAP_1 = 0x1, + RASTER_CONFIG_SE_PAIR_MAP_2 = 0x2, + RASTER_CONFIG_SE_PAIR_MAP_3 = 0x3, +} SePairMap; +typedef enum SeXsel { + RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x3, +} SeXsel; +typedef enum SeYsel { + RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x3, +} SeYsel; +typedef enum SeMap { + RASTER_CONFIG_SE_MAP_0 = 0x0, + RASTER_CONFIG_SE_MAP_1 = 0x1, + RASTER_CONFIG_SE_MAP_2 = 0x2, + RASTER_CONFIG_SE_MAP_3 = 0x3, +} SeMap; +typedef enum ScXsel { + RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x3, +} ScXsel; +typedef enum ScYsel { + RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x0, + RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x1, + RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x2, + RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x3, +} ScYsel; +typedef enum ScMap { + RASTER_CONFIG_SC_MAP_0 = 0x0, + RASTER_CONFIG_SC_MAP_1 = 0x1, + RASTER_CONFIG_SC_MAP_2 = 0x2, + RASTER_CONFIG_SC_MAP_3 = 0x3, +} ScMap; +typedef enum PkrXsel2 { + RASTER_CONFIG_PKR_XSEL2_0 = 0x0, + RASTER_CONFIG_PKR_XSEL2_1 = 0x1, + RASTER_CONFIG_PKR_XSEL2_2 = 0x2, + RASTER_CONFIG_PKR_XSEL2_3 = 0x3, +} PkrXsel2; +typedef enum PkrXsel { + RASTER_CONFIG_PKR_XSEL_0 = 0x0, + RASTER_CONFIG_PKR_XSEL_1 = 0x1, + RASTER_CONFIG_PKR_XSEL_2 = 0x2, + RASTER_CONFIG_PKR_XSEL_3 = 0x3, +} PkrXsel; +typedef enum PkrYsel { + RASTER_CONFIG_PKR_YSEL_0 = 0x0, + RASTER_CONFIG_PKR_YSEL_1 = 0x1, + RASTER_CONFIG_PKR_YSEL_2 = 0x2, + RASTER_CONFIG_PKR_YSEL_3 = 0x3, +} PkrYsel; +typedef enum PkrMap { + RASTER_CONFIG_PKR_MAP_0 = 0x0, + RASTER_CONFIG_PKR_MAP_1 = 0x1, + RASTER_CONFIG_PKR_MAP_2 = 0x2, + RASTER_CONFIG_PKR_MAP_3 = 0x3, +} PkrMap; +typedef enum RbXsel { + RASTER_CONFIG_RB_XSEL_0 = 0x0, + RASTER_CONFIG_RB_XSEL_1 = 0x1, +} RbXsel; +typedef enum RbYsel { + RASTER_CONFIG_RB_YSEL_0 = 0x0, + RASTER_CONFIG_RB_YSEL_1 = 0x1, +} RbYsel; +typedef enum RbXsel2 { + RASTER_CONFIG_RB_XSEL2_0 = 0x0, + RASTER_CONFIG_RB_XSEL2_1 = 0x1, + RASTER_CONFIG_RB_XSEL2_2 = 0x2, + RASTER_CONFIG_RB_XSEL2_3 = 0x3, +} RbXsel2; +typedef enum RbMap { + RASTER_CONFIG_RB_MAP_0 = 0x0, + RASTER_CONFIG_RB_MAP_1 = 0x1, + RASTER_CONFIG_RB_MAP_2 = 0x2, + RASTER_CONFIG_RB_MAP_3 = 0x3, +} RbMap; +typedef enum CSDATA_TYPE { + CSDATA_TYPE_TG = 0x0, + CSDATA_TYPE_STATE = 0x1, + CSDATA_TYPE_EVENT = 0x2, + CSDATA_TYPE_PRIVATE = 0x3, +} CSDATA_TYPE; +#define CSDATA_TYPE_WIDTH 0x2 +#define CSDATA_ADDR_WIDTH 0x7 +#define CSDATA_DATA_WIDTH 0x20 +typedef enum SPI_SAMPLE_CNTL { + CENTROIDS_ONLY = 0x0, + CENTERS_ONLY = 0x1, + CENTROIDS_AND_CENTERS = 0x2, + UNDEF = 0x3, +} SPI_SAMPLE_CNTL; +typedef enum SPI_FOG_MODE { + SPI_FOG_NONE = 0x0, + SPI_FOG_EXP = 0x1, + SPI_FOG_EXP2 = 0x2, + SPI_FOG_LINEAR = 0x3, +} SPI_FOG_MODE; +typedef enum SPI_PNT_SPRITE_OVERRIDE { + SPI_PNT_SPRITE_SEL_0 = 0x0, + SPI_PNT_SPRITE_SEL_1 = 0x1, + SPI_PNT_SPRITE_SEL_S = 0x2, + SPI_PNT_SPRITE_SEL_T = 0x3, + SPI_PNT_SPRITE_SEL_NONE = 0x4, +} SPI_PNT_SPRITE_OVERRIDE; +typedef enum SPI_PERFCNT_SEL { + SPI_PERF_VS_WINDOW_VALID = 0x0, + SPI_PERF_VS_BUSY = 0x1, + SPI_PERF_VS_FIRST_WAVE = 0x2, + SPI_PERF_VS_LAST_WAVE = 0x3, + SPI_PERF_VS_LSHS_DEALLOC = 0x4, + SPI_PERF_VS_PC_STALL = 0x5, + SPI_PERF_VS_POS0_STALL = 0x6, + SPI_PERF_VS_POS1_STALL = 0x7, + SPI_PERF_VS_CRAWLER_STALL = 0x8, + SPI_PERF_VS_EVENT_WAVE = 0x9, + SPI_PERF_VS_WAVE = 0xa, + SPI_PERF_VS_PERS_UPD_FULL0 = 0xb, + SPI_PERF_VS_PERS_UPD_FULL1 = 0xc, + SPI_PERF_VS_LATE_ALLOC_FULL = 0xd, + SPI_PERF_VS_FIRST_SUBGRP = 0xe, + SPI_PERF_VS_LAST_SUBGRP = 0xf, + SPI_PERF_GS_WINDOW_VALID = 0x10, + SPI_PERF_GS_BUSY = 0x11, + SPI_PERF_GS_CRAWLER_STALL = 0x12, + SPI_PERF_GS_EVENT_WAVE = 0x13, + SPI_PERF_GS_WAVE = 0x14, + SPI_PERF_GS_PERS_UPD_FULL0 = 0x15, + SPI_PERF_GS_PERS_UPD_FULL1 = 0x16, + SPI_PERF_GS_FIRST_SUBGRP = 0x17, + SPI_PERF_GS_LAST_SUBGRP = 0x18, + SPI_PERF_ES_WINDOW_VALID = 0x19, + SPI_PERF_ES_BUSY = 0x1a, + SPI_PERF_ES_CRAWLER_STALL = 0x1b, + SPI_PERF_ES_FIRST_WAVE = 0x1c, + SPI_PERF_ES_LAST_WAVE = 0x1d, + SPI_PERF_ES_LSHS_DEALLOC = 0x1e, + SPI_PERF_ES_EVENT_WAVE = 0x1f, + SPI_PERF_ES_WAVE = 0x20, + SPI_PERF_ES_PERS_UPD_FULL0 = 0x21, + SPI_PERF_ES_PERS_UPD_FULL1 = 0x22, + SPI_PERF_ES_FIRST_SUBGRP = 0x23, + SPI_PERF_ES_LAST_SUBGRP = 0x24, + SPI_PERF_HS_WINDOW_VALID = 0x25, + SPI_PERF_HS_BUSY = 0x26, + SPI_PERF_HS_CRAWLER_STALL = 0x27, + SPI_PERF_HS_FIRST_WAVE = 0x28, + SPI_PERF_HS_LAST_WAVE = 0x29, + SPI_PERF_HS_LSHS_DEALLOC = 0x2a, + SPI_PERF_HS_EVENT_WAVE = 0x2b, + SPI_PERF_HS_WAVE = 0x2c, + SPI_PERF_HS_PERS_UPD_FULL0 = 0x2d, + SPI_PERF_HS_PERS_UPD_FULL1 = 0x2e, + SPI_PERF_LS_WINDOW_VALID = 0x2f, + SPI_PERF_LS_BUSY = 0x30, + SPI_PERF_LS_CRAWLER_STALL = 0x31, + SPI_PERF_LS_FIRST_WAVE = 0x32, + SPI_PERF_LS_LAST_WAVE = 0x33, + SPI_PERF_OFFCHIP_LDS_STALL_LS = 0x34, + SPI_PERF_LS_EVENT_WAVE = 0x35, + SPI_PERF_LS_WAVE = 0x36, + SPI_PERF_LS_PERS_UPD_FULL0 = 0x37, + SPI_PERF_LS_PERS_UPD_FULL1 = 0x38, + SPI_PERF_CSG_WINDOW_VALID = 0x39, + SPI_PERF_CSG_BUSY = 0x3a, + SPI_PERF_CSG_NUM_THREADGROUPS = 0x3b, + SPI_PERF_CSG_CRAWLER_STALL = 0x3c, + SPI_PERF_CSG_EVENT_WAVE = 0x3d, + SPI_PERF_CSG_WAVE = 0x3e, + SPI_PERF_CSN_WINDOW_VALID = 0x3f, + SPI_PERF_CSN_BUSY = 0x40, + SPI_PERF_CSN_NUM_THREADGROUPS = 0x41, + SPI_PERF_CSN_CRAWLER_STALL = 0x42, + SPI_PERF_CSN_EVENT_WAVE = 0x43, + SPI_PERF_CSN_WAVE = 0x44, + SPI_PERF_PS_CTL_WINDOW_VALID = 0x45, + SPI_PERF_PS_CTL_BUSY = 0x46, + SPI_PERF_PS_CTL_ACTIVE = 0x47, + SPI_PERF_PS_CTL_DEALLOC_BIN0 = 0x48, + SPI_PERF_PS_CTL_FPOS_BIN1_STALL = 0x49, + SPI_PERF_PS_CTL_EVENT_WAVE = 0x4a, + SPI_PERF_PS_CTL_WAVE = 0x4b, + SPI_PERF_PS_CTL_OPT_WAVE = 0x4c, + SPI_PERF_PS_CTL_PASS_BIN0 = 0x4d, + SPI_PERF_PS_CTL_PASS_BIN1 = 0x4e, + SPI_PERF_PS_CTL_FPOS_BIN2 = 0x4f, + SPI_PERF_PS_CTL_PRIM_BIN0 = 0x50, + SPI_PERF_PS_CTL_PRIM_BIN1 = 0x51, + SPI_PERF_PS_CTL_CNF_BIN2 = 0x52, + SPI_PERF_PS_CTL_CNF_BIN3 = 0x53, + SPI_PERF_PS_CTL_CRAWLER_STALL = 0x54, + SPI_PERF_PS_CTL_LDS_RES_FULL = 0x55, + SPI_PERF_PS_PERS_UPD_FULL0 = 0x56, + SPI_PERF_PS_PERS_UPD_FULL1 = 0x57, + SPI_PERF_PIX_ALLOC_PEND_CNT = 0x58, + SPI_PERF_PIX_ALLOC_SCB_STALL = 0x59, + SPI_PERF_PIX_ALLOC_DB0_STALL = 0x5a, + SPI_PERF_PIX_ALLOC_DB1_STALL = 0x5b, + SPI_PERF_PIX_ALLOC_DB2_STALL = 0x5c, + SPI_PERF_PIX_ALLOC_DB3_STALL = 0x5d, + SPI_PERF_LDS0_PC_VALID = 0x5e, + SPI_PERF_LDS1_PC_VALID = 0x5f, + SPI_PERF_RA_PIPE_REQ_BIN2 = 0x60, + SPI_PERF_RA_TASK_REQ_BIN3 = 0x61, + SPI_PERF_RA_WR_CTL_FULL = 0x62, + SPI_PERF_RA_REQ_NO_ALLOC = 0x63, + SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x64, + SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x65, + SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x66, + SPI_PERF_RA_REQ_NO_ALLOC_ES = 0x67, + SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x68, + SPI_PERF_RA_REQ_NO_ALLOC_LS = 0x69, + SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x6a, + SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x6b, + SPI_PERF_RA_RES_STALL_PS = 0x6c, + SPI_PERF_RA_RES_STALL_VS = 0x6d, + SPI_PERF_RA_RES_STALL_GS = 0x6e, + SPI_PERF_RA_RES_STALL_ES = 0x6f, + SPI_PERF_RA_RES_STALL_HS = 0x70, + SPI_PERF_RA_RES_STALL_LS = 0x71, + SPI_PERF_RA_RES_STALL_CSG = 0x72, + SPI_PERF_RA_RES_STALL_CSN = 0x73, + SPI_PERF_RA_TMP_STALL_PS = 0x74, + SPI_PERF_RA_TMP_STALL_VS = 0x75, + SPI_PERF_RA_TMP_STALL_GS = 0x76, + SPI_PERF_RA_TMP_STALL_ES = 0x77, + SPI_PERF_RA_TMP_STALL_HS = 0x78, + SPI_PERF_RA_TMP_STALL_LS = 0x79, + SPI_PERF_RA_TMP_STALL_CSG = 0x7a, + SPI_PERF_RA_TMP_STALL_CSN = 0x7b, + SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x7c, + SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x7d, + SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x7e, + SPI_PERF_RA_WAVE_SIMD_FULL_ES = 0x7f, + SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x80, + SPI_PERF_RA_WAVE_SIMD_FULL_LS = 0x81, + SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x82, + SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x83, + SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x84, + SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x85, + SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x86, + SPI_PERF_RA_VGPR_SIMD_FULL_ES = 0x87, + SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x88, + SPI_PERF_RA_VGPR_SIMD_FULL_LS = 0x89, + SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x8a, + SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x8b, + SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x8c, + SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x8d, + SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x8e, + SPI_PERF_RA_SGPR_SIMD_FULL_ES = 0x8f, + SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x90, + SPI_PERF_RA_SGPR_SIMD_FULL_LS = 0x91, + SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x92, + SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x93, + SPI_PERF_RA_LDS_CU_FULL_PS = 0x94, + SPI_PERF_RA_LDS_CU_FULL_LS = 0x95, + SPI_PERF_RA_LDS_CU_FULL_ES = 0x96, + SPI_PERF_RA_LDS_CU_FULL_CSG = 0x97, + SPI_PERF_RA_LDS_CU_FULL_CSN = 0x98, + SPI_PERF_RA_BAR_CU_FULL_HS = 0x99, + SPI_PERF_RA_BAR_CU_FULL_CSG = 0x9a, + SPI_PERF_RA_BAR_CU_FULL_CSN = 0x9b, + SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x9c, + SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x9d, + SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x9e, + SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x9f, + SPI_PERF_RA_WVLIM_STALL_PS = 0xa0, + SPI_PERF_RA_WVLIM_STALL_VS = 0xa1, + SPI_PERF_RA_WVLIM_STALL_GS = 0xa2, + SPI_PERF_RA_WVLIM_STALL_ES = 0xa3, + SPI_PERF_RA_WVLIM_STALL_HS = 0xa4, + SPI_PERF_RA_WVLIM_STALL_LS = 0xa5, + SPI_PERF_RA_WVLIM_STALL_CSG = 0xa6, + SPI_PERF_RA_WVLIM_STALL_CSN = 0xa7, + SPI_PERF_RA_PS_LOCK_NA = 0xa8, + SPI_PERF_RA_VS_LOCK = 0xa9, + SPI_PERF_RA_GS_LOCK = 0xaa, + SPI_PERF_RA_ES_LOCK = 0xab, + SPI_PERF_RA_HS_LOCK = 0xac, + SPI_PERF_RA_LS_LOCK = 0xad, + SPI_PERF_RA_CSG_LOCK = 0xae, + SPI_PERF_RA_CSN_LOCK = 0xaf, + SPI_PERF_RA_RSV_UPD = 0xb0, + SPI_PERF_EXP_ARB_COL_CNT = 0xb1, + SPI_PERF_EXP_ARB_PAR_CNT = 0xb2, + SPI_PERF_EXP_ARB_POS_CNT = 0xb3, + SPI_PERF_EXP_ARB_GDS_CNT = 0xb4, + SPI_PERF_CLKGATE_BUSY_STALL = 0xb5, + SPI_PERF_CLKGATE_ACTIVE_STALL = 0xb6, + SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0xb7, + SPI_PERF_CLKGATE_CGTT_DYN_ON = 0xb8, + SPI_PERF_CLKGATE_CGTT_REG_ON = 0xb9, + SPI_PERF_NUM_VS_POS_EXPORTS = 0xba, + SPI_PERF_NUM_VS_PARAM_EXPORTS = 0xbb, + SPI_PERF_NUM_PS_COL_EXPORTS = 0xbc, + SPI_PERF_ES_GRP_FIFO_FULL = 0xbd, + SPI_PERF_GS_GRP_FIFO_FULL = 0xbe, + SPI_PERF_HS_GRP_FIFO_FULL = 0xbf, + SPI_PERF_LS_GRP_FIFO_FULL = 0xc0, + SPI_PERF_VS_ALLOC_CNT = 0xc1, + SPI_PERF_VS_LATE_ALLOC_ACCUM = 0xc2, + SPI_PERF_PC_ALLOC_CNT = 0xc3, + SPI_PERF_PC_ALLOC_ACCUM = 0xc4, +} SPI_PERFCNT_SEL; +typedef enum SPI_SHADER_FORMAT { + SPI_SHADER_NONE = 0x0, + SPI_SHADER_1COMP = 0x1, + SPI_SHADER_2COMP = 0x2, + SPI_SHADER_4COMPRESS = 0x3, + SPI_SHADER_4COMP = 0x4, +} SPI_SHADER_FORMAT; +typedef enum SPI_SHADER_EX_FORMAT { + SPI_SHADER_ZERO = 0x0, + SPI_SHADER_32_R = 0x1, + SPI_SHADER_32_GR = 0x2, + SPI_SHADER_32_AR = 0x3, + SPI_SHADER_FP16_ABGR = 0x4, + SPI_SHADER_UNORM16_ABGR = 0x5, + SPI_SHADER_SNORM16_ABGR = 0x6, + SPI_SHADER_UINT16_ABGR = 0x7, + SPI_SHADER_SINT16_ABGR = 0x8, + SPI_SHADER_32_ABGR = 0x9, +} SPI_SHADER_EX_FORMAT; +typedef enum CLKGATE_SM_MODE { + ON_SEQ = 0x0, + OFF_SEQ = 0x1, + PROG_SEQ = 0x2, + READ_SEQ = 0x3, + SM_MODE_RESERVED = 0x4, +} CLKGATE_SM_MODE; +typedef enum CLKGATE_BASE_MODE { + MULT_8 = 0x0, + MULT_16 = 0x1, +} CLKGATE_BASE_MODE; +typedef enum SQ_TEX_CLAMP { + SQ_TEX_WRAP = 0x0, + SQ_TEX_MIRROR = 0x1, + SQ_TEX_CLAMP_LAST_TEXEL = 0x2, + SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x3, + SQ_TEX_CLAMP_HALF_BORDER = 0x4, + SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x5, + SQ_TEX_CLAMP_BORDER = 0x6, + SQ_TEX_MIRROR_ONCE_BORDER = 0x7, +} SQ_TEX_CLAMP; +typedef enum SQ_TEX_XY_FILTER { + SQ_TEX_XY_FILTER_POINT = 0x0, + SQ_TEX_XY_FILTER_BILINEAR = 0x1, + SQ_TEX_XY_FILTER_ANISO_POINT = 0x2, + SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x3, +} SQ_TEX_XY_FILTER; +typedef enum SQ_TEX_Z_FILTER { + SQ_TEX_Z_FILTER_NONE = 0x0, + SQ_TEX_Z_FILTER_POINT = 0x1, + SQ_TEX_Z_FILTER_LINEAR = 0x2, +} SQ_TEX_Z_FILTER; +typedef enum SQ_TEX_MIP_FILTER { + SQ_TEX_MIP_FILTER_NONE = 0x0, + SQ_TEX_MIP_FILTER_POINT = 0x1, + SQ_TEX_MIP_FILTER_LINEAR = 0x2, + SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x3, +} SQ_TEX_MIP_FILTER; +typedef enum SQ_TEX_ANISO_RATIO { + SQ_TEX_ANISO_RATIO_1 = 0x0, + SQ_TEX_ANISO_RATIO_2 = 0x1, + SQ_TEX_ANISO_RATIO_4 = 0x2, + SQ_TEX_ANISO_RATIO_8 = 0x3, + SQ_TEX_ANISO_RATIO_16 = 0x4, +} SQ_TEX_ANISO_RATIO; +typedef enum SQ_TEX_DEPTH_COMPARE { + SQ_TEX_DEPTH_COMPARE_NEVER = 0x0, + SQ_TEX_DEPTH_COMPARE_LESS = 0x1, + SQ_TEX_DEPTH_COMPARE_EQUAL = 0x2, + SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x3, + SQ_TEX_DEPTH_COMPARE_GREATER = 0x4, + SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x5, + SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x6, + SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x7, +} SQ_TEX_DEPTH_COMPARE; +typedef enum SQ_TEX_BORDER_COLOR { + SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x0, + SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x1, + SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x2, + SQ_TEX_BORDER_COLOR_REGISTER = 0x3, +} SQ_TEX_BORDER_COLOR; +typedef enum SQ_RSRC_BUF_TYPE { + SQ_RSRC_BUF = 0x0, + SQ_RSRC_BUF_RSVD_1 = 0x1, + SQ_RSRC_BUF_RSVD_2 = 0x2, + SQ_RSRC_BUF_RSVD_3 = 0x3, +} SQ_RSRC_BUF_TYPE; +typedef enum SQ_RSRC_IMG_TYPE { + SQ_RSRC_IMG_RSVD_0 = 0x0, + SQ_RSRC_IMG_RSVD_1 = 0x1, + SQ_RSRC_IMG_RSVD_2 = 0x2, + SQ_RSRC_IMG_RSVD_3 = 0x3, + SQ_RSRC_IMG_RSVD_4 = 0x4, + SQ_RSRC_IMG_RSVD_5 = 0x5, + SQ_RSRC_IMG_RSVD_6 = 0x6, + SQ_RSRC_IMG_RSVD_7 = 0x7, + SQ_RSRC_IMG_1D = 0x8, + SQ_RSRC_IMG_2D = 0x9, + SQ_RSRC_IMG_3D = 0xa, + SQ_RSRC_IMG_CUBE = 0xb, + SQ_RSRC_IMG_1D_ARRAY = 0xc, + SQ_RSRC_IMG_2D_ARRAY = 0xd, + SQ_RSRC_IMG_2D_MSAA = 0xe, + SQ_RSRC_IMG_2D_MSAA_ARRAY = 0xf, +} SQ_RSRC_IMG_TYPE; +typedef enum SQ_RSRC_FLAT_TYPE { + SQ_RSRC_FLAT_RSVD_0 = 0x0, + SQ_RSRC_FLAT = 0x1, + SQ_RSRC_FLAT_RSVD_2 = 0x2, + SQ_RSRC_FLAT_RSVD_3 = 0x3, +} SQ_RSRC_FLAT_TYPE; +typedef enum SQ_IMG_FILTER_TYPE { + SQ_IMG_FILTER_MODE_BLEND = 0x0, + SQ_IMG_FILTER_MODE_MIN = 0x1, + SQ_IMG_FILTER_MODE_MAX = 0x2, +} SQ_IMG_FILTER_TYPE; +typedef enum SQ_SEL_XYZW01 { + SQ_SEL_0 = 0x0, + SQ_SEL_1 = 0x1, + SQ_SEL_RESERVED_0 = 0x2, + SQ_SEL_RESERVED_1 = 0x3, + SQ_SEL_X = 0x4, + SQ_SEL_Y = 0x5, + SQ_SEL_Z = 0x6, + SQ_SEL_W = 0x7, +} SQ_SEL_XYZW01; +typedef enum SQ_WAVE_TYPE { + SQ_WAVE_TYPE_PS = 0x0, + SQ_WAVE_TYPE_VS = 0x1, + SQ_WAVE_TYPE_GS = 0x2, + SQ_WAVE_TYPE_ES = 0x3, + SQ_WAVE_TYPE_HS = 0x4, + SQ_WAVE_TYPE_LS = 0x5, + SQ_WAVE_TYPE_CS = 0x6, + SQ_WAVE_TYPE_PS1 = 0x7, +} SQ_WAVE_TYPE; +typedef enum SQ_THREAD_TRACE_TOKEN_TYPE { + SQ_THREAD_TRACE_TOKEN_MISC = 0x0, + SQ_THREAD_TRACE_TOKEN_TIMESTAMP = 0x1, + SQ_THREAD_TRACE_TOKEN_REG = 0x2, + SQ_THREAD_TRACE_TOKEN_WAVE_START = 0x3, + SQ_THREAD_TRACE_TOKEN_WAVE_ALLOC = 0x4, + SQ_THREAD_TRACE_TOKEN_REG_CSPRIV = 0x5, + SQ_THREAD_TRACE_TOKEN_WAVE_END = 0x6, + SQ_THREAD_TRACE_TOKEN_EVENT = 0x7, + SQ_THREAD_TRACE_TOKEN_EVENT_CS = 0x8, + SQ_THREAD_TRACE_TOKEN_EVENT_GFX1 = 0x9, + SQ_THREAD_TRACE_TOKEN_INST = 0xa, + SQ_THREAD_TRACE_TOKEN_INST_PC = 0xb, + SQ_THREAD_TRACE_TOKEN_INST_USERDATA = 0xc, + SQ_THREAD_TRACE_TOKEN_ISSUE = 0xd, + SQ_THREAD_TRACE_TOKEN_PERF = 0xe, + SQ_THREAD_TRACE_TOKEN_REG_CS = 0xf, +} SQ_THREAD_TRACE_TOKEN_TYPE; +typedef enum SQ_THREAD_TRACE_MISC_TOKEN_TYPE { + SQ_THREAD_TRACE_MISC_TOKEN_TIME = 0x0, + SQ_THREAD_TRACE_MISC_TOKEN_TIME_RESET = 0x1, + SQ_THREAD_TRACE_MISC_TOKEN_PACKET_LOST = 0x2, + SQ_THREAD_TRACE_MISC_TOKEN_SURF_SYNC = 0x3, + SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_BEGIN = 0x4, + SQ_THREAD_TRACE_MISC_TOKEN_TTRACE_STALL_END = 0x5, + SQ_THREAD_TRACE_MISC_TOKEN_SAVECTX = 0x6, + SQ_THREAD_TRACE_MISC_TOKEN_SHOOT_DOWN = 0x7, +} SQ_THREAD_TRACE_MISC_TOKEN_TYPE; +typedef enum SQ_THREAD_TRACE_INST_TYPE { + SQ_THREAD_TRACE_INST_TYPE_SMEM_RD = 0x0, + SQ_THREAD_TRACE_INST_TYPE_SALU_32 = 0x1, + SQ_THREAD_TRACE_INST_TYPE_VMEM_RD = 0x2, + SQ_THREAD_TRACE_INST_TYPE_VMEM_WR = 0x3, + SQ_THREAD_TRACE_INST_TYPE_FLAT_WR = 0x4, + SQ_THREAD_TRACE_INST_TYPE_VALU_32 = 0x5, + SQ_THREAD_TRACE_INST_TYPE_LDS = 0x6, + SQ_THREAD_TRACE_INST_TYPE_PC = 0x7, + SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GDS = 0x8, + SQ_THREAD_TRACE_INST_TYPE_EXPREQ_GFX = 0x9, + SQ_THREAD_TRACE_INST_TYPE_EXPGNT_PAR_COL = 0xa, + SQ_THREAD_TRACE_INST_TYPE_EXPGNT_POS_GDS = 0xb, + SQ_THREAD_TRACE_INST_TYPE_JUMP = 0xc, + SQ_THREAD_TRACE_INST_TYPE_NEXT = 0xd, + SQ_THREAD_TRACE_INST_TYPE_FLAT_RD = 0xe, + SQ_THREAD_TRACE_INST_TYPE_OTHER_MSG = 0xf, + SQ_THREAD_TRACE_INST_TYPE_SMEM_WR = 0x10, + SQ_THREAD_TRACE_INST_TYPE_SALU_64 = 0x11, + SQ_THREAD_TRACE_INST_TYPE_VALU_64 = 0x12, + SQ_THREAD_TRACE_INST_TYPE_SMEM_RD_REPLAY = 0x13, + SQ_THREAD_TRACE_INST_TYPE_SMEM_WR_REPLAY = 0x14, + SQ_THREAD_TRACE_INST_TYPE_VMEM_RD_REPLAY = 0x15, + SQ_THREAD_TRACE_INST_TYPE_VMEM_WR_REPLAY = 0x16, + SQ_THREAD_TRACE_INST_TYPE_FLAT_RD_REPLAY = 0x17, + SQ_THREAD_TRACE_INST_TYPE_FLAT_WR_REPLAY = 0x18, +} SQ_THREAD_TRACE_INST_TYPE; +typedef enum SQ_THREAD_TRACE_REG_TYPE { + SQ_THREAD_TRACE_REG_TYPE_EVENT = 0x0, + SQ_THREAD_TRACE_REG_TYPE_DRAW = 0x1, + SQ_THREAD_TRACE_REG_TYPE_DISPATCH = 0x2, + SQ_THREAD_TRACE_REG_TYPE_USERDATA = 0x3, + SQ_THREAD_TRACE_REG_TYPE_MARKER = 0x4, + SQ_THREAD_TRACE_REG_TYPE_GFXDEC = 0x5, + SQ_THREAD_TRACE_REG_TYPE_SHDEC = 0x6, + SQ_THREAD_TRACE_REG_TYPE_OTHER = 0x7, +} SQ_THREAD_TRACE_REG_TYPE; +typedef enum SQ_THREAD_TRACE_REG_OP { + SQ_THREAD_TRACE_REG_OP_READ = 0x0, + SQ_THREAD_TRACE_REG_OP_WRITE = 0x1, +} SQ_THREAD_TRACE_REG_OP; +typedef enum SQ_THREAD_TRACE_MODE_SEL { + SQ_THREAD_TRACE_MODE_OFF = 0x0, + SQ_THREAD_TRACE_MODE_ON = 0x1, +} SQ_THREAD_TRACE_MODE_SEL; +typedef enum SQ_THREAD_TRACE_CAPTURE_MODE { + SQ_THREAD_TRACE_CAPTURE_MODE_ALL = 0x0, + SQ_THREAD_TRACE_CAPTURE_MODE_SELECT = 0x1, + SQ_THREAD_TRACE_CAPTURE_MODE_SELECT_DETAIL = 0x2, +} SQ_THREAD_TRACE_CAPTURE_MODE; +typedef enum SQ_THREAD_TRACE_VM_ID_MASK { + SQ_THREAD_TRACE_VM_ID_MASK_SINGLE = 0x0, + SQ_THREAD_TRACE_VM_ID_MASK_ALL = 0x1, + SQ_THREAD_TRACE_VM_ID_MASK_SINGLE_DETAIL = 0x2, +} SQ_THREAD_TRACE_VM_ID_MASK; +typedef enum SQ_THREAD_TRACE_WAVE_MASK { + SQ_THREAD_TRACE_WAVE_MASK_NONE = 0x0, + SQ_THREAD_TRACE_WAVE_MASK_ALL = 0x1, +} SQ_THREAD_TRACE_WAVE_MASK; +typedef enum SQ_THREAD_TRACE_ISSUE { + SQ_THREAD_TRACE_ISSUE_NULL = 0x0, + SQ_THREAD_TRACE_ISSUE_STALL = 0x1, + SQ_THREAD_TRACE_ISSUE_INST = 0x2, + SQ_THREAD_TRACE_ISSUE_IMMED = 0x3, +} SQ_THREAD_TRACE_ISSUE; +typedef enum SQ_THREAD_TRACE_ISSUE_MASK { + SQ_THREAD_TRACE_ISSUE_MASK_ALL = 0x0, + SQ_THREAD_TRACE_ISSUE_MASK_STALLED = 0x1, + SQ_THREAD_TRACE_ISSUE_MASK_STALLED_AND_IMMED = 0x2, + SQ_THREAD_TRACE_ISSUE_MASK_IMMED = 0x3, +} SQ_THREAD_TRACE_ISSUE_MASK; +typedef enum SQ_PERF_SEL { + SQ_PERF_SEL_NONE = 0x0, + SQ_PERF_SEL_ACCUM_PREV = 0x1, + SQ_PERF_SEL_CYCLES = 0x2, + SQ_PERF_SEL_BUSY_CYCLES = 0x3, + SQ_PERF_SEL_WAVES = 0x4, + SQ_PERF_SEL_LEVEL_WAVES = 0x5, + SQ_PERF_SEL_WAVES_EQ_64 = 0x6, + SQ_PERF_SEL_WAVES_LT_64 = 0x7, + SQ_PERF_SEL_WAVES_LT_48 = 0x8, + SQ_PERF_SEL_WAVES_LT_32 = 0x9, + SQ_PERF_SEL_WAVES_LT_16 = 0xa, + SQ_PERF_SEL_WAVES_CU = 0xb, + SQ_PERF_SEL_LEVEL_WAVES_CU = 0xc, + SQ_PERF_SEL_BUSY_CU_CYCLES = 0xd, + SQ_PERF_SEL_ITEMS = 0xe, + SQ_PERF_SEL_QUADS = 0xf, + SQ_PERF_SEL_EVENTS = 0x10, + SQ_PERF_SEL_SURF_SYNCS = 0x11, + SQ_PERF_SEL_TTRACE_REQS = 0x12, + SQ_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x13, + SQ_PERF_SEL_TTRACE_STALL = 0x14, + SQ_PERF_SEL_MSG_CNTR = 0x15, + SQ_PERF_SEL_MSG_PERF = 0x16, + SQ_PERF_SEL_MSG_GSCNT = 0x17, + SQ_PERF_SEL_MSG_INTERRUPT = 0x18, + SQ_PERF_SEL_INSTS = 0x19, + SQ_PERF_SEL_INSTS_VALU = 0x1a, + SQ_PERF_SEL_INSTS_VMEM_WR = 0x1b, + SQ_PERF_SEL_INSTS_VMEM_RD = 0x1c, + SQ_PERF_SEL_INSTS_VMEM = 0x1d, + SQ_PERF_SEL_INSTS_SALU = 0x1e, + SQ_PERF_SEL_INSTS_SMEM = 0x1f, + SQ_PERF_SEL_INSTS_FLAT = 0x20, + SQ_PERF_SEL_INSTS_FLAT_LDS_ONLY = 0x21, + SQ_PERF_SEL_INSTS_LDS = 0x22, + SQ_PERF_SEL_INSTS_GDS = 0x23, + SQ_PERF_SEL_INSTS_EXP = 0x24, + SQ_PERF_SEL_INSTS_EXP_GDS = 0x25, + SQ_PERF_SEL_INSTS_BRANCH = 0x26, + SQ_PERF_SEL_INSTS_SENDMSG = 0x27, + SQ_PERF_SEL_INSTS_VSKIPPED = 0x28, + SQ_PERF_SEL_INST_LEVEL_VMEM = 0x29, + SQ_PERF_SEL_INST_LEVEL_SMEM = 0x2a, + SQ_PERF_SEL_INST_LEVEL_LDS = 0x2b, + SQ_PERF_SEL_INST_LEVEL_GDS = 0x2c, + SQ_PERF_SEL_INST_LEVEL_EXP = 0x2d, + SQ_PERF_SEL_WAVE_CYCLES = 0x2e, + SQ_PERF_SEL_WAVE_READY = 0x2f, + SQ_PERF_SEL_WAIT_CNT_VM = 0x30, + SQ_PERF_SEL_WAIT_CNT_LGKM = 0x31, + SQ_PERF_SEL_WAIT_CNT_EXP = 0x32, + SQ_PERF_SEL_WAIT_CNT_ANY = 0x33, + SQ_PERF_SEL_WAIT_BARRIER = 0x34, + SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x35, + SQ_PERF_SEL_WAIT_SLEEP = 0x36, + SQ_PERF_SEL_WAIT_OTHER = 0x37, + SQ_PERF_SEL_WAIT_ANY = 0x38, + SQ_PERF_SEL_WAIT_TTRACE = 0x39, + SQ_PERF_SEL_WAIT_IFETCH = 0x3a, + SQ_PERF_SEL_WAIT_INST_VMEM = 0x3b, + SQ_PERF_SEL_WAIT_INST_SCA = 0x3c, + SQ_PERF_SEL_WAIT_INST_LDS = 0x3d, + SQ_PERF_SEL_WAIT_INST_VALU = 0x3e, + SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x3f, + SQ_PERF_SEL_WAIT_INST_MISC = 0x40, + SQ_PERF_SEL_WAIT_INST_FLAT = 0x41, + SQ_PERF_SEL_ACTIVE_INST_ANY = 0x42, + SQ_PERF_SEL_ACTIVE_INST_VMEM = 0x43, + SQ_PERF_SEL_ACTIVE_INST_LDS = 0x44, + SQ_PERF_SEL_ACTIVE_INST_VALU = 0x45, + SQ_PERF_SEL_ACTIVE_INST_SCA = 0x46, + SQ_PERF_SEL_ACTIVE_INST_EXP_GDS = 0x47, + SQ_PERF_SEL_ACTIVE_INST_MISC = 0x48, + SQ_PERF_SEL_ACTIVE_INST_FLAT = 0x49, + SQ_PERF_SEL_INST_CYCLES_VMEM_WR = 0x4a, + SQ_PERF_SEL_INST_CYCLES_VMEM_RD = 0x4b, + SQ_PERF_SEL_INST_CYCLES_VMEM_ADDR = 0x4c, + SQ_PERF_SEL_INST_CYCLES_VMEM_DATA = 0x4d, + SQ_PERF_SEL_INST_CYCLES_VMEM_CMD = 0x4e, + SQ_PERF_SEL_INST_CYCLES_VMEM = 0x4f, + SQ_PERF_SEL_INST_CYCLES_LDS = 0x50, + SQ_PERF_SEL_INST_CYCLES_VALU = 0x51, + SQ_PERF_SEL_INST_CYCLES_EXP = 0x52, + SQ_PERF_SEL_INST_CYCLES_GDS = 0x53, + SQ_PERF_SEL_INST_CYCLES_SCA = 0x54, + SQ_PERF_SEL_INST_CYCLES_SMEM = 0x55, + SQ_PERF_SEL_INST_CYCLES_SALU = 0x56, + SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x57, + SQ_PERF_SEL_INST_CYCLES_MISC = 0x58, + SQ_PERF_SEL_THREAD_CYCLES_VALU = 0x59, + SQ_PERF_SEL_THREAD_CYCLES_VALU_MAX = 0x5a, + SQ_PERF_SEL_IFETCH = 0x5b, + SQ_PERF_SEL_IFETCH_LEVEL = 0x5c, + SQ_PERF_SEL_CBRANCH_FORK = 0x5d, + SQ_PERF_SEL_CBRANCH_FORK_SPLIT = 0x5e, + SQ_PERF_SEL_VALU_LDS_DIRECT_RD = 0x5f, + SQ_PERF_SEL_VALU_LDS_INTERP_OP = 0x60, + SQ_PERF_SEL_LDS_BANK_CONFLICT = 0x61, + SQ_PERF_SEL_LDS_ADDR_CONFLICT = 0x62, + SQ_PERF_SEL_LDS_UNALIGNED_STALL = 0x63, + SQ_PERF_SEL_LDS_MEM_VIOLATIONS = 0x64, + SQ_PERF_SEL_LDS_ATOMIC_RETURN = 0x65, + SQ_PERF_SEL_LDS_IDX_ACTIVE = 0x66, + SQ_PERF_SEL_VALU_DEP_STALL = 0x67, + SQ_PERF_SEL_VALU_STARVE = 0x68, + SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x69, + SQ_PERF_SEL_LDS_BACK2BACK_STALL = 0x6a, + SQ_PERF_SEL_LDS_DATA_FIFO_FULL = 0x6b, + SQ_PERF_SEL_LDS_CMD_FIFO_FULL = 0x6c, + SQ_PERF_SEL_VMEM_BACK2BACK_STALL = 0x6d, + SQ_PERF_SEL_VMEM_TA_ADDR_FIFO_FULL = 0x6e, + SQ_PERF_SEL_VMEM_TA_CMD_FIFO_FULL = 0x6f, + SQ_PERF_SEL_VMEM_EX_DATA_REG_BUSY = 0x70, + SQ_PERF_SEL_VMEM_WR_BACK2BACK_STALL = 0x71, + SQ_PERF_SEL_VMEM_WR_TA_DATA_FIFO_FULL = 0x72, + SQ_PERF_SEL_VALU_SRC_C_CONFLICT = 0x73, + SQ_PERF_SEL_VMEM_RD_SRC_CD_CONFLICT = 0x74, + SQ_PERF_SEL_VMEM_WR_SRC_CD_CONFLICT = 0x75, + SQ_PERF_SEL_FLAT_SRC_CD_CONFLICT = 0x76, + SQ_PERF_SEL_LDS_SRC_CD_CONFLICT = 0x77, + SQ_PERF_SEL_SRC_CD_BUSY = 0x78, + SQ_PERF_SEL_PT_POWER_STALL = 0x79, + SQ_PERF_SEL_USER0 = 0x7a, + SQ_PERF_SEL_USER1 = 0x7b, + SQ_PERF_SEL_USER2 = 0x7c, + SQ_PERF_SEL_USER3 = 0x7d, + SQ_PERF_SEL_USER4 = 0x7e, + SQ_PERF_SEL_USER5 = 0x7f, + SQ_PERF_SEL_USER6 = 0x80, + SQ_PERF_SEL_USER7 = 0x81, + SQ_PERF_SEL_USER8 = 0x82, + SQ_PERF_SEL_USER9 = 0x83, + SQ_PERF_SEL_USER10 = 0x84, + SQ_PERF_SEL_USER11 = 0x85, + SQ_PERF_SEL_USER12 = 0x86, + SQ_PERF_SEL_USER13 = 0x87, + SQ_PERF_SEL_USER14 = 0x88, + SQ_PERF_SEL_USER15 = 0x89, + SQ_PERF_SEL_USER_LEVEL0 = 0x8a, + SQ_PERF_SEL_USER_LEVEL1 = 0x8b, + SQ_PERF_SEL_USER_LEVEL2 = 0x8c, + SQ_PERF_SEL_USER_LEVEL3 = 0x8d, + SQ_PERF_SEL_USER_LEVEL4 = 0x8e, + SQ_PERF_SEL_USER_LEVEL5 = 0x8f, + SQ_PERF_SEL_USER_LEVEL6 = 0x90, + SQ_PERF_SEL_USER_LEVEL7 = 0x91, + SQ_PERF_SEL_USER_LEVEL8 = 0x92, + SQ_PERF_SEL_USER_LEVEL9 = 0x93, + SQ_PERF_SEL_USER_LEVEL10 = 0x94, + SQ_PERF_SEL_USER_LEVEL11 = 0x95, + SQ_PERF_SEL_USER_LEVEL12 = 0x96, + SQ_PERF_SEL_USER_LEVEL13 = 0x97, + SQ_PERF_SEL_USER_LEVEL14 = 0x98, + SQ_PERF_SEL_USER_LEVEL15 = 0x99, + SQ_PERF_SEL_POWER_VALU = 0x9a, + SQ_PERF_SEL_POWER_VALU0 = 0x9b, + SQ_PERF_SEL_POWER_VALU1 = 0x9c, + SQ_PERF_SEL_POWER_VALU2 = 0x9d, + SQ_PERF_SEL_POWER_GPR_RD = 0x9e, + SQ_PERF_SEL_POWER_GPR_WR = 0x9f, + SQ_PERF_SEL_POWER_LDS_BUSY = 0xa0, + SQ_PERF_SEL_POWER_ALU_BUSY = 0xa1, + SQ_PERF_SEL_POWER_TEX_BUSY = 0xa2, + SQ_PERF_SEL_ACCUM_PREV_HIRES = 0xa3, + SQ_PERF_SEL_WAVES_RESTORED = 0xa4, + SQ_PERF_SEL_WAVES_SAVED = 0xa5, + SQ_PERF_SEL_DUMMY_LAST = 0xa7, + SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0xa8, + SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0xa9, + SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0xaa, + SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0xab, + SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0xac, + SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0xad, + SQC_PERF_SEL_TC_REQ = 0xae, + SQC_PERF_SEL_TC_INST_REQ = 0xaf, + SQC_PERF_SEL_TC_DATA_READ_REQ = 0xb0, + SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0xb1, + SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0xb2, + SQC_PERF_SEL_TC_STALL = 0xb3, + SQC_PERF_SEL_TC_STARVE = 0xb4, + SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0xb5, + SQC_PERF_SEL_ICACHE_REQ = 0xb6, + SQC_PERF_SEL_ICACHE_HITS = 0xb7, + SQC_PERF_SEL_ICACHE_MISSES = 0xb8, + SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0xb9, + SQC_PERF_SEL_ICACHE_INVAL_INST = 0xba, + SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0xbb, + SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0xbc, + SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0xbd, + SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0xbe, + SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0xbf, + SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0xc0, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0xc1, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xc2, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xc3, + SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0xc4, + SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xc5, + SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0xc6, + SQC_PERF_SEL_DCACHE_REQ = 0xc7, + SQC_PERF_SEL_DCACHE_HITS = 0xc8, + SQC_PERF_SEL_DCACHE_MISSES = 0xc9, + SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0xca, + SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0xcb, + SQC_PERF_SEL_DCACHE_MISS_EVICT_READ = 0xcc, + SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0xcd, + SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0xce, + SQC_PERF_SEL_DCACHE_ATOMIC = 0xcf, + SQC_PERF_SEL_DCACHE_VOLATILE = 0xd0, + SQC_PERF_SEL_DCACHE_INVAL_INST = 0xd1, + SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0xd2, + SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_INST = 0xd3, + SQC_PERF_SEL_DCACHE_INVAL_VOLATILE_ASYNC = 0xd4, + SQC_PERF_SEL_DCACHE_WB_INST = 0xd5, + SQC_PERF_SEL_DCACHE_WB_ASYNC = 0xd6, + SQC_PERF_SEL_DCACHE_WB_VOLATILE_INST = 0xd7, + SQC_PERF_SEL_DCACHE_WB_VOLATILE_ASYNC = 0xd8, + SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0xd9, + SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0xda, + SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0xdb, + SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0xdc, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0xdd, + SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0xde, + SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0xdf, + SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE= 0xe0, + SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0xe1, + SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0xe2, + SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0xe3, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0xe4, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0xe5, + SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0xe6, + SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0xe7, + SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0xe8, + SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0xe9, + SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0xea, + SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0xeb, + SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0xec, + SQC_PERF_SEL_DCACHE_REQ_TIME = 0xed, + SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0xee, + SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0xef, + SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0xf0, + SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0xf1, + SQC_PERF_SEL_SQ_DCACHE_REQS = 0xf2, + SQC_PERF_SEL_DCACHE_FLAT_REQ = 0xf3, + SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0xf4, + SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0xf5, + SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0xf6, + SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0xf7, + SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0xf8, + SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0xf9, + SQC_PERF_SEL_ICACHE_GATCL1_TRANSLATION_MISS = 0xfa, + SQC_PERF_SEL_ICACHE_GATCL1_PERMISSION_MISS = 0xfb, + SQC_PERF_SEL_ICACHE_GATCL1_REQUEST = 0xfc, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_INFLIGHT_MAX = 0xfd, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_LRU_INFLIGHT = 0xfe, + SQC_PERF_SEL_ICACHE_GATCL1_LFIFO_FULL = 0xff, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x100, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x101, + SQC_PERF_SEL_ICACHE_GATCL1_ATCL2_INFLIGHT = 0x102, + SQC_PERF_SEL_ICACHE_GATCL1_STALL_MISSFIFO_FULL = 0x103, + SQC_PERF_SEL_DCACHE_GATCL1_TRANSLATION_MISS = 0x104, + SQC_PERF_SEL_DCACHE_GATCL1_PERMISSION_MISS = 0x105, + SQC_PERF_SEL_DCACHE_GATCL1_REQUEST = 0x106, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_INFLIGHT_MAX = 0x107, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_LRU_INFLIGHT = 0x108, + SQC_PERF_SEL_DCACHE_GATCL1_LFIFO_FULL = 0x109, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_LFIFO_NOT_RES = 0x10a, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0x10b, + SQC_PERF_SEL_DCACHE_GATCL1_ATCL2_INFLIGHT = 0x10c, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_MISSFIFO_FULL = 0x10d, + SQC_PERF_SEL_DCACHE_GATCL1_STALL_MULTI_MISS = 0x10e, + SQC_PERF_SEL_DCACHE_GATCL1_HIT_FIFO_FULL = 0x10f, + SQC_PERF_SEL_DUMMY_LAST = 0x110, + SQ_PERF_SEL_INSTS_SMEM_NORM = 0x111, + SQ_PERF_SEL_ATC_INSTS_VMEM = 0x112, + SQ_PERF_SEL_ATC_INST_LEVEL_VMEM = 0x113, + SQ_PERF_SEL_ATC_XNACK_FIRST = 0x114, + SQ_PERF_SEL_ATC_XNACK_ALL = 0x115, + SQ_PERF_SEL_ATC_XNACK_FIFO_FULL = 0x116, + SQ_PERF_SEL_ATC_INSTS_SMEM = 0x117, + SQ_PERF_SEL_ATC_INST_LEVEL_SMEM = 0x118, + SQ_PERF_SEL_IFETCH_XNACK = 0x119, + SQ_PERF_SEL_TLB_SHOOTDOWN = 0x11a, + SQ_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x11b, + SQ_PERF_SEL_INSTS_VMEM_WR_REPLAY = 0x11c, + SQ_PERF_SEL_INSTS_VMEM_RD_REPLAY = 0x11d, + SQ_PERF_SEL_INSTS_VMEM_REPLAY = 0x11e, + SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x11f, + SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x120, + SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x121, + SQ_PERF_SEL_ATC_INSTS_VMEM_REPLAY = 0x122, + SQ_PERF_SEL_ATC_INSTS_SMEM_REPLAY = 0x123, + SQ_PERF_SEL_DUMMY_LAST1 = 0x12a, +} SQ_PERF_SEL; +typedef enum SQ_CAC_POWER_SEL { + SQ_CAC_POWER_VALU = 0x0, + SQ_CAC_POWER_VALU0 = 0x1, + SQ_CAC_POWER_VALU1 = 0x2, + SQ_CAC_POWER_VALU2 = 0x3, + SQ_CAC_POWER_GPR_RD = 0x4, + SQ_CAC_POWER_GPR_WR = 0x5, + SQ_CAC_POWER_LDS_BUSY = 0x6, + SQ_CAC_POWER_ALU_BUSY = 0x7, + SQ_CAC_POWER_TEX_BUSY = 0x8, +} SQ_CAC_POWER_SEL; +typedef enum SQ_IND_CMD_CMD { + SQ_IND_CMD_CMD_NULL = 0x0, + SQ_IND_CMD_CMD_SETHALT = 0x1, + SQ_IND_CMD_CMD_SAVECTX = 0x2, + SQ_IND_CMD_CMD_KILL = 0x3, + SQ_IND_CMD_CMD_DEBUG = 0x4, + SQ_IND_CMD_CMD_TRAP = 0x5, + SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x6, +} SQ_IND_CMD_CMD; +typedef enum SQ_IND_CMD_MODE { + SQ_IND_CMD_MODE_SINGLE = 0x0, + SQ_IND_CMD_MODE_BROADCAST = 0x1, + SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x2, + SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x3, + SQ_IND_CMD_MODE_BROADCAST_ME = 0x4, +} SQ_IND_CMD_MODE; +typedef enum SQ_EDC_INFO_SOURCE { + SQ_EDC_INFO_SOURCE_INVALID = 0x0, + SQ_EDC_INFO_SOURCE_INST = 0x1, + SQ_EDC_INFO_SOURCE_SGPR = 0x2, + SQ_EDC_INFO_SOURCE_VGPR = 0x3, + SQ_EDC_INFO_SOURCE_LDS = 0x4, + SQ_EDC_INFO_SOURCE_GDS = 0x5, + SQ_EDC_INFO_SOURCE_TA = 0x6, +} SQ_EDC_INFO_SOURCE; +typedef enum SQ_ROUND_MODE { + SQ_ROUND_NEAREST_EVEN = 0x0, + SQ_ROUND_PLUS_INFINITY = 0x1, + SQ_ROUND_MINUS_INFINITY = 0x2, + SQ_ROUND_TO_ZERO = 0x3, +} SQ_ROUND_MODE; +typedef enum SQ_INTERRUPT_WORD_ENCODING { + SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x0, + SQ_INTERRUPT_WORD_ENCODING_INST = 0x1, + SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x2, +} SQ_INTERRUPT_WORD_ENCODING; +typedef enum ENUM_SQ_EXPORT_RAT_INST { + SQ_EXPORT_RAT_INST_NOP = 0x0, + SQ_EXPORT_RAT_INST_STORE_TYPED = 0x1, + SQ_EXPORT_RAT_INST_STORE_RAW = 0x2, + SQ_EXPORT_RAT_INST_STORE_RAW_FDENORM = 0x3, + SQ_EXPORT_RAT_INST_CMPXCHG_INT = 0x4, + SQ_EXPORT_RAT_INST_CMPXCHG_FLT = 0x5, + SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM = 0x6, + SQ_EXPORT_RAT_INST_ADD = 0x7, + SQ_EXPORT_RAT_INST_SUB = 0x8, + SQ_EXPORT_RAT_INST_RSUB = 0x9, + SQ_EXPORT_RAT_INST_MIN_INT = 0xa, + SQ_EXPORT_RAT_INST_MIN_UINT = 0xb, + SQ_EXPORT_RAT_INST_MAX_INT = 0xc, + SQ_EXPORT_RAT_INST_MAX_UINT = 0xd, + SQ_EXPORT_RAT_INST_AND = 0xe, + SQ_EXPORT_RAT_INST_OR = 0xf, + SQ_EXPORT_RAT_INST_XOR = 0x10, + SQ_EXPORT_RAT_INST_MSKOR = 0x11, + SQ_EXPORT_RAT_INST_INC_UINT = 0x12, + SQ_EXPORT_RAT_INST_DEC_UINT = 0x13, + SQ_EXPORT_RAT_INST_STORE_DWORD = 0x14, + SQ_EXPORT_RAT_INST_STORE_SHORT = 0x15, + SQ_EXPORT_RAT_INST_STORE_BYTE = 0x16, + SQ_EXPORT_RAT_INST_NOP_RTN = 0x20, + SQ_EXPORT_RAT_INST_XCHG_RTN = 0x22, + SQ_EXPORT_RAT_INST_XCHG_FDENORM_RTN = 0x23, + SQ_EXPORT_RAT_INST_CMPXCHG_INT_RTN = 0x24, + SQ_EXPORT_RAT_INST_CMPXCHG_FLT_RTN = 0x25, + SQ_EXPORT_RAT_INST_CMPXCHG_FDENORM_RTN = 0x26, + SQ_EXPORT_RAT_INST_ADD_RTN = 0x27, + SQ_EXPORT_RAT_INST_SUB_RTN = 0x28, + SQ_EXPORT_RAT_INST_RSUB_RTN = 0x29, + SQ_EXPORT_RAT_INST_MIN_INT_RTN = 0x2a, + SQ_EXPORT_RAT_INST_MIN_UINT_RTN = 0x2b, + SQ_EXPORT_RAT_INST_MAX_INT_RTN = 0x2c, + SQ_EXPORT_RAT_INST_MAX_UINT_RTN = 0x2d, + SQ_EXPORT_RAT_INST_AND_RTN = 0x2e, + SQ_EXPORT_RAT_INST_OR_RTN = 0x2f, + SQ_EXPORT_RAT_INST_XOR_RTN = 0x30, + SQ_EXPORT_RAT_INST_MSKOR_RTN = 0x31, + SQ_EXPORT_RAT_INST_INC_UINT_RTN = 0x32, + SQ_EXPORT_RAT_INST_DEC_UINT_RTN = 0x33, +} ENUM_SQ_EXPORT_RAT_INST; +typedef enum SQ_IBUF_ST { + SQ_IBUF_IB_IDLE = 0x0, + SQ_IBUF_IB_INI_WAIT_GNT = 0x1, + SQ_IBUF_IB_INI_WAIT_DRET = 0x2, + SQ_IBUF_IB_LE_4DW = 0x3, + SQ_IBUF_IB_WAIT_DRET = 0x4, + SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x5, + SQ_IBUF_IB_DRET = 0x6, + SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x7, +} SQ_IBUF_ST; +typedef enum SQ_INST_STR_ST { + SQ_INST_STR_IB_WAVE_NORML = 0x0, + SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x1, + SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x2, + SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x3, + SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x4, + SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x5, + SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x6, + SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x7, +} SQ_INST_STR_ST; +typedef enum SQ_WAVE_IB_ECC_ST { + SQ_WAVE_IB_ECC_CLEAN = 0x0, + SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x1, + SQ_WAVE_IB_ECC_ERR_HALT = 0x2, + SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x3, +} SQ_WAVE_IB_ECC_ST; +typedef enum SH_MEM_ADDRESS_MODE { + SH_MEM_ADDRESS_MODE_GPUVM64 = 0x0, + SH_MEM_ADDRESS_MODE_GPUVM32 = 0x1, + SH_MEM_ADDRESS_MODE_HSA64 = 0x2, + SH_MEM_ADDRESS_MODE_HSA32 = 0x3, +} SH_MEM_ADDRESS_MODE; +typedef enum SH_MEM_ALIGNMENT_MODE { + SH_MEM_ALIGNMENT_MODE_DWORD = 0x0, + SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x1, + SH_MEM_ALIGNMENT_MODE_STRICT = 0x2, + SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x3, +} SH_MEM_ALIGNMENT_MODE; +typedef enum SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX { + SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_WREXEC = 0x18, + SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX_RESTORE = 0x19, +} SQ_THREAD_TRACE_WAVE_START_COUNT_PREFIX; +#define SQ_WAVE_TYPE_PS0 0x0 +#define SQIND_GLOBAL_REGS_OFFSET 0x0 +#define SQIND_GLOBAL_REGS_SIZE 0x8 +#define SQIND_LOCAL_REGS_OFFSET 0x8 +#define SQIND_LOCAL_REGS_SIZE 0x8 +#define SQIND_WAVE_HWREGS_OFFSET 0x10 +#define SQIND_WAVE_HWREGS_SIZE 0x1f0 +#define SQIND_WAVE_SGPRS_OFFSET 0x200 +#define SQIND_WAVE_SGPRS_SIZE 0x200 +#define SQ_GFXDEC_BEGIN 0xa000 +#define SQ_GFXDEC_END 0xc000 +#define SQ_GFXDEC_STATE_ID_SHIFT 0xa +#define SQDEC_BEGIN 0x2300 +#define SQDEC_END 0x23ff +#define SQPERFSDEC_BEGIN 0xd9c0 +#define SQPERFSDEC_END 0xda40 +#define SQPERFDDEC_BEGIN 0xd1c0 +#define SQPERFDDEC_END 0xd240 +#define SQGFXUDEC_BEGIN 0xc330 +#define SQGFXUDEC_END 0xc380 +#define SQPWRDEC_BEGIN 0xf08c +#define SQPWRDEC_END 0xf094 +#define SQ_DISPATCHER_GFX_MIN 0x10 +#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x8 +#define SQ_MAX_PGM_SGPRS 0x68 +#define SQ_MAX_PGM_VGPRS 0x100 +#define SQ_THREAD_TRACE_TIME_UNIT 0x4 +#define SQ_EX_MODE_EXCP_VALU_BASE 0x0 +#define SQ_EX_MODE_EXCP_VALU_SIZE 0x7 +#define SQ_EX_MODE_EXCP_INVALID 0x0 +#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x1 +#define SQ_EX_MODE_EXCP_DIV0 0x2 +#define SQ_EX_MODE_EXCP_OVERFLOW 0x3 +#define SQ_EX_MODE_EXCP_UNDERFLOW 0x4 +#define SQ_EX_MODE_EXCP_INEXACT 0x5 +#define SQ_EX_MODE_EXCP_INT_DIV0 0x6 +#define SQ_EX_MODE_EXCP_ADDR_WATCH 0x7 +#define SQ_EX_MODE_EXCP_MEM_VIOL 0x8 +#define INST_ID_PRIV_START 0x80000000 +#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0 +#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1 +#define INST_ID_HW_TRAP 0xfffffff2 +#define INST_ID_KILL_SEQ 0xfffffff3 +#define INST_ID_SPI_WREXEC 0xfffffff4 +#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe +#define SQ_ENC_SOP1_BITS 0xbe800000 +#define SQ_ENC_SOP1_MASK 0xff800000 +#define SQ_ENC_SOP1_FIELD 0x17d +#define SQ_ENC_SOPC_BITS 0xbf000000 +#define SQ_ENC_SOPC_MASK 0xff800000 +#define SQ_ENC_SOPC_FIELD 0x17e +#define SQ_ENC_SOPP_BITS 0xbf800000 +#define SQ_ENC_SOPP_MASK 0xff800000 +#define SQ_ENC_SOPP_FIELD 0x17f +#define SQ_ENC_SOPK_BITS 0xb0000000 +#define SQ_ENC_SOPK_MASK 0xf0000000 +#define SQ_ENC_SOPK_FIELD 0xb +#define SQ_ENC_SOP2_BITS 0x80000000 +#define SQ_ENC_SOP2_MASK 0xc0000000 +#define SQ_ENC_SOP2_FIELD 0x2 +#define SQ_ENC_SMEM_BITS 0xc0000000 +#define SQ_ENC_SMEM_MASK 0xfc000000 +#define SQ_ENC_SMEM_FIELD 0x30 +#define SQ_ENC_VOP1_BITS 0x7e000000 +#define SQ_ENC_VOP1_MASK 0xfe000000 +#define SQ_ENC_VOP1_FIELD 0x3f +#define SQ_ENC_VOPC_BITS 0x7c000000 +#define SQ_ENC_VOPC_MASK 0xfe000000 +#define SQ_ENC_VOPC_FIELD 0x3e +#define SQ_ENC_VOP2_BITS 0x0 +#define SQ_ENC_VOP2_MASK 0x80000000 +#define SQ_ENC_VOP2_FIELD 0x0 +#define SQ_ENC_VINTRP_BITS 0xd4000000 +#define SQ_ENC_VINTRP_MASK 0xfc000000 +#define SQ_ENC_VINTRP_FIELD 0x35 +#define SQ_ENC_VOP3_BITS 0xd0000000 +#define SQ_ENC_VOP3_MASK 0xfc000000 +#define SQ_ENC_VOP3_FIELD 0x34 +#define SQ_ENC_DS_BITS 0xd8000000 +#define SQ_ENC_DS_MASK 0xfc000000 +#define SQ_ENC_DS_FIELD 0x36 +#define SQ_ENC_MUBUF_BITS 0xe0000000 +#define SQ_ENC_MUBUF_MASK 0xfc000000 +#define SQ_ENC_MUBUF_FIELD 0x38 +#define SQ_ENC_MTBUF_BITS 0xe8000000 +#define SQ_ENC_MTBUF_MASK 0xfc000000 +#define SQ_ENC_MTBUF_FIELD 0x3a +#define SQ_ENC_MIMG_BITS 0xf0000000 +#define SQ_ENC_MIMG_MASK 0xfc000000 +#define SQ_ENC_MIMG_FIELD 0x3c +#define SQ_ENC_EXP_BITS 0xc4000000 +#define SQ_ENC_EXP_MASK 0xfc000000 +#define SQ_ENC_EXP_FIELD 0x31 +#define SQ_ENC_FLAT_BITS 0xdc000000 +#define SQ_ENC_FLAT_MASK 0xfc000000 +#define SQ_ENC_FLAT_FIELD 0x37 +#define SQ_V_OP3_INTRP_OFFSET 0x274 +#define SQ_WAITCNT_VM_SHIFT 0x0 +#define SQ_SENDMSG_STREAMID_SIZE 0x2 +#define SQ_V_OPC_COUNT 0x100 +#define SQ_V_OP3_INTRP_COUNT 0xc +#define SQ_XLATE_VOP3_TO_VOP2_OFFSET 0x100 +#define SQ_HWREG_OFFSET_SIZE 0x5 +#define SQ_HWREG_OFFSET_SHIFT 0x6 +#define SQ_V_OP3_3IN_OFFSET 0x1c0 +#define SQ_NUM_ATTR 0x21 +#define SQ_NUM_VGPR 0x100 +#define SQ_XLATE_VOP3_TO_VINTRP_COUNT 0x4 +#define SQ_SENDMSG_MSG_SIZE 0x4 +#define SQ_NUM_TTMP 0xc +#define SQ_HWREG_ID_SIZE 0x6 +#define SQ_SENDMSG_GSOP_SIZE 0x2 +#define SQ_NUM_SGPR 0x66 +#define SQ_EXP_NUM_MRT 0x8 +#define SQ_SENDMSG_SYSTEM_SIZE 0x3 +#define SQ_WAITCNT_LGKM_SHIFT 0x8 +#define SQ_XLATE_VOP3_TO_VOP2_COUNT 0x40 +#define SQ_V_OP3_3IN_COUNT 0xb0 +#define SQ_V_INTRP_COUNT 0x4 +#define SQ_WAITCNT_EXP_SIZE 0x3 +#define SQ_SENDMSG_SYSTEM_SHIFT 0x4 +#define SQ_EXP_NUM_GDS 0x5 +#define SQ_HWREG_SIZE_SHIFT 0xb +#define SQ_XLATE_VOP3_TO_VOPC_OFFSET 0x0 +#define SQ_V_OP3_2IN_COUNT 0x80 +#define SQ_XLATE_VOP3_TO_VINTRP_OFFSET 0x270 +#define SQ_SENDMSG_MSG_SHIFT 0x0 +#define SQ_WAITCNT_EXP_SHIFT 0x4 +#define SQ_WAITCNT_VM_SIZE 0x4 +#define SQ_XLATE_VOP3_TO_VOP1_OFFSET 0x140 +#define SQ_SENDMSG_GSOP_SHIFT 0x4 +#define SQ_XLATE_VOP3_TO_VOP1_COUNT 0x80 +#define SQ_SRC_VGPR_BIT 0x100 +#define SQ_V_OP2_COUNT 0x40 +#define SQ_EXP_NUM_PARAM 0x20 +#define SQ_V_OP1_COUNT 0x80 +#define SQ_SENDMSG_STREAMID_SHIFT 0x8 +#define SQ_V_OP3_2IN_OFFSET 0x280 +#define SQ_WAITCNT_LGKM_SIZE 0x4 +#define SQ_XLATE_VOP3_TO_VOPC_COUNT 0x100 +#define SQ_EXP_NUM_POS 0x4 +#define SQ_HWREG_SIZE_SIZE 0x5 +#define SQ_HWREG_ID_SHIFT 0x0 +#define SQ_S_MOV_B32 0x0 +#define SQ_S_MOV_B64 0x1 +#define SQ_S_CMOV_B32 0x2 +#define SQ_S_CMOV_B64 0x3 +#define SQ_S_NOT_B32 0x4 +#define SQ_S_NOT_B64 0x5 +#define SQ_S_WQM_B32 0x6 +#define SQ_S_WQM_B64 0x7 +#define SQ_S_BREV_B32 0x8 +#define SQ_S_BREV_B64 0x9 +#define SQ_S_BCNT0_I32_B32 0xa +#define SQ_S_BCNT0_I32_B64 0xb +#define SQ_S_BCNT1_I32_B32 0xc +#define SQ_S_BCNT1_I32_B64 0xd +#define SQ_S_FF0_I32_B32 0xe +#define SQ_S_FF0_I32_B64 0xf +#define SQ_S_FF1_I32_B32 0x10 +#define SQ_S_FF1_I32_B64 0x11 +#define SQ_S_FLBIT_I32_B32 0x12 +#define SQ_S_FLBIT_I32_B64 0x13 +#define SQ_S_FLBIT_I32 0x14 +#define SQ_S_FLBIT_I32_I64 0x15 +#define SQ_S_SEXT_I32_I8 0x16 +#define SQ_S_SEXT_I32_I16 0x17 +#define SQ_S_BITSET0_B32 0x18 +#define SQ_S_BITSET0_B64 0x19 +#define SQ_S_BITSET1_B32 0x1a +#define SQ_S_BITSET1_B64 0x1b +#define SQ_S_GETPC_B64 0x1c +#define SQ_S_SETPC_B64 0x1d +#define SQ_S_SWAPPC_B64 0x1e +#define SQ_S_RFE_B64 0x1f +#define SQ_S_AND_SAVEEXEC_B64 0x20 +#define SQ_S_OR_SAVEEXEC_B64 0x21 +#define SQ_S_XOR_SAVEEXEC_B64 0x22 +#define SQ_S_ANDN2_SAVEEXEC_B64 0x23 +#define SQ_S_ORN2_SAVEEXEC_B64 0x24 +#define SQ_S_NAND_SAVEEXEC_B64 0x25 +#define SQ_S_NOR_SAVEEXEC_B64 0x26 +#define SQ_S_XNOR_SAVEEXEC_B64 0x27 +#define SQ_S_QUADMASK_B32 0x28 +#define SQ_S_QUADMASK_B64 0x29 +#define SQ_S_MOVRELS_B32 0x2a +#define SQ_S_MOVRELS_B64 0x2b +#define SQ_S_MOVRELD_B32 0x2c +#define SQ_S_MOVRELD_B64 0x2d +#define SQ_S_CBRANCH_JOIN 0x2e +#define SQ_S_MOV_REGRD_B32 0x2f +#define SQ_S_ABS_I32 0x30 +#define SQ_S_MOV_FED_B32 0x31 +#define SQ_S_SET_GPR_IDX_IDX 0x32 +#define SQ_ATTR0 0x0 +#define SQ_S_MOVK_I32 0x0 +#define SQ_S_CMOVK_I32 0x1 +#define SQ_S_CMPK_EQ_I32 0x2 +#define SQ_S_CMPK_LG_I32 0x3 +#define SQ_S_CMPK_GT_I32 0x4 +#define SQ_S_CMPK_GE_I32 0x5 +#define SQ_S_CMPK_LT_I32 0x6 +#define SQ_S_CMPK_LE_I32 0x7 +#define SQ_S_CMPK_EQ_U32 0x8 +#define SQ_S_CMPK_LG_U32 0x9 +#define SQ_S_CMPK_GT_U32 0xa +#define SQ_S_CMPK_GE_U32 0xb +#define SQ_S_CMPK_LT_U32 0xc +#define SQ_S_CMPK_LE_U32 0xd +#define SQ_S_ADDK_I32 0xe +#define SQ_S_MULK_I32 0xf +#define SQ_S_CBRANCH_I_FORK 0x10 +#define SQ_S_GETREG_B32 0x11 +#define SQ_S_SETREG_B32 0x12 +#define SQ_S_GETREG_REGRD_B32 0x13 +#define SQ_S_SETREG_IMM32_B32 0x14 +#define SQ_TBA_LO 0x6c +#define SQ_TBA_HI 0x6d +#define SQ_TMA_LO 0x6e +#define SQ_TMA_HI 0x6f +#define SQ_TTMP0 0x70 +#define SQ_TTMP1 0x71 +#define SQ_TTMP2 0x72 +#define SQ_TTMP3 0x73 +#define SQ_TTMP4 0x74 +#define SQ_TTMP5 0x75 +#define SQ_TTMP6 0x76 +#define SQ_TTMP7 0x77 +#define SQ_TTMP8 0x78 +#define SQ_TTMP9 0x79 +#define SQ_TTMP10 0x7a +#define SQ_TTMP11 0x7b +#define SQ_VGPR0 0x0 +#define SQ_EXP 0x0 +#define SQ_EXP_MRT0 0x0 +#define SQ_EXP_MRTZ 0x8 +#define SQ_EXP_NULL 0x9 +#define SQ_EXP_POS0 0xc +#define SQ_EXP_PARAM0 0x20 +#define SQ_CNT1 0x0 +#define SQ_CNT2 0x1 +#define SQ_CNT3 0x2 +#define SQ_CNT4 0x3 +#define SQ_S_LOAD_DWORD 0x0 +#define SQ_S_LOAD_DWORDX2 0x1 +#define SQ_S_LOAD_DWORDX4 0x2 +#define SQ_S_LOAD_DWORDX8 0x3 +#define SQ_S_LOAD_DWORDX16 0x4 +#define SQ_S_BUFFER_LOAD_DWORD 0x8 +#define SQ_S_BUFFER_LOAD_DWORDX2 0x9 +#define SQ_S_BUFFER_LOAD_DWORDX4 0xa +#define SQ_S_BUFFER_LOAD_DWORDX8 0xb +#define SQ_S_BUFFER_LOAD_DWORDX16 0xc +#define SQ_S_STORE_DWORD 0x10 +#define SQ_S_STORE_DWORDX2 0x11 +#define SQ_S_STORE_DWORDX4 0x12 +#define SQ_S_BUFFER_STORE_DWORD 0x18 +#define SQ_S_BUFFER_STORE_DWORDX2 0x19 +#define SQ_S_BUFFER_STORE_DWORDX4 0x1a +#define SQ_S_DCACHE_INV 0x20 +#define SQ_S_DCACHE_WB 0x21 +#define SQ_S_DCACHE_INV_VOL 0x22 +#define SQ_S_DCACHE_WB_VOL 0x23 +#define SQ_S_MEMTIME 0x24 +#define SQ_S_MEMREALTIME 0x25 +#define SQ_S_ATC_PROBE 0x26 +#define SQ_S_ATC_PROBE_BUFFER 0x27 +#define SQ_S_BUFFER_ATOMIC_SWAP 0x40 +#define SQ_S_BUFFER_ATOMIC_CMPSWAP 0x41 +#define SQ_S_BUFFER_ATOMIC_ADD 0x42 +#define SQ_S_BUFFER_ATOMIC_SUB 0x43 +#define SQ_S_BUFFER_ATOMIC_SMIN 0x44 +#define SQ_S_BUFFER_ATOMIC_UMIN 0x45 +#define SQ_S_BUFFER_ATOMIC_SMAX 0x46 +#define SQ_S_BUFFER_ATOMIC_UMAX 0x47 +#define SQ_S_BUFFER_ATOMIC_AND 0x48 +#define SQ_S_BUFFER_ATOMIC_OR 0x49 +#define SQ_S_BUFFER_ATOMIC_XOR 0x4a +#define SQ_S_BUFFER_ATOMIC_INC 0x4b +#define SQ_S_BUFFER_ATOMIC_DEC 0x4c +#define SQ_S_BUFFER_ATOMIC_SWAP_X2 0x60 +#define SQ_S_BUFFER_ATOMIC_CMPSWAP_X2 0x61 +#define SQ_S_BUFFER_ATOMIC_ADD_X2 0x62 +#define SQ_S_BUFFER_ATOMIC_SUB_X2 0x63 +#define SQ_S_BUFFER_ATOMIC_SMIN_X2 0x64 +#define SQ_S_BUFFER_ATOMIC_UMIN_X2 0x65 +#define SQ_S_BUFFER_ATOMIC_SMAX_X2 0x66 +#define SQ_S_BUFFER_ATOMIC_UMAX_X2 0x67 +#define SQ_S_BUFFER_ATOMIC_AND_X2 0x68 +#define SQ_S_BUFFER_ATOMIC_OR_X2 0x69 +#define SQ_S_BUFFER_ATOMIC_XOR_X2 0x6a +#define SQ_S_BUFFER_ATOMIC_INC_X2 0x6b +#define SQ_S_BUFFER_ATOMIC_DEC_X2 0x6c +#define SQ_F 0x0 +#define SQ_LT 0x1 +#define SQ_EQ 0x2 +#define SQ_LE 0x3 +#define SQ_GT 0x4 +#define SQ_LG 0x5 +#define SQ_GE 0x6 +#define SQ_O 0x7 +#define SQ_U 0x8 +#define SQ_NGE 0x9 +#define SQ_NLG 0xa +#define SQ_NGT 0xb +#define SQ_NLE 0xc +#define SQ_NEQ 0xd +#define SQ_NLT 0xe +#define SQ_TRU 0xf +#define SQ_V_CMP_CLASS_F32 0x10 +#define SQ_V_CMPX_CLASS_F32 0x11 +#define SQ_V_CMP_CLASS_F64 0x12 +#define SQ_V_CMPX_CLASS_F64 0x13 +#define SQ_V_CMP_CLASS_F16 0x14 +#define SQ_V_CMPX_CLASS_F16 0x15 +#define SQ_V_CMP_F_F16 0x20 +#define SQ_V_CMP_LT_F16 0x21 +#define SQ_V_CMP_EQ_F16 0x22 +#define SQ_V_CMP_LE_F16 0x23 +#define SQ_V_CMP_GT_F16 0x24 +#define SQ_V_CMP_LG_F16 0x25 +#define SQ_V_CMP_GE_F16 0x26 +#define SQ_V_CMP_O_F16 0x27 +#define SQ_V_CMP_U_F16 0x28 +#define SQ_V_CMP_NGE_F16 0x29 +#define SQ_V_CMP_NLG_F16 0x2a +#define SQ_V_CMP_NGT_F16 0x2b +#define SQ_V_CMP_NLE_F16 0x2c +#define SQ_V_CMP_NEQ_F16 0x2d +#define SQ_V_CMP_NLT_F16 0x2e +#define SQ_V_CMP_TRU_F16 0x2f +#define SQ_V_CMPX_F_F16 0x30 +#define SQ_V_CMPX_LT_F16 0x31 +#define SQ_V_CMPX_EQ_F16 0x32 +#define SQ_V_CMPX_LE_F16 0x33 +#define SQ_V_CMPX_GT_F16 0x34 +#define SQ_V_CMPX_LG_F16 0x35 +#define SQ_V_CMPX_GE_F16 0x36 +#define SQ_V_CMPX_O_F16 0x37 +#define SQ_V_CMPX_U_F16 0x38 +#define SQ_V_CMPX_NGE_F16 0x39 +#define SQ_V_CMPX_NLG_F16 0x3a +#define SQ_V_CMPX_NGT_F16 0x3b +#define SQ_V_CMPX_NLE_F16 0x3c +#define SQ_V_CMPX_NEQ_F16 0x3d +#define SQ_V_CMPX_NLT_F16 0x3e +#define SQ_V_CMPX_TRU_F16 0x3f +#define SQ_V_CMP_F_F32 0x40 +#define SQ_V_CMP_LT_F32 0x41 +#define SQ_V_CMP_EQ_F32 0x42 +#define SQ_V_CMP_LE_F32 0x43 +#define SQ_V_CMP_GT_F32 0x44 +#define SQ_V_CMP_LG_F32 0x45 +#define SQ_V_CMP_GE_F32 0x46 +#define SQ_V_CMP_O_F32 0x47 +#define SQ_V_CMP_U_F32 0x48 +#define SQ_V_CMP_NGE_F32 0x49 +#define SQ_V_CMP_NLG_F32 0x4a +#define SQ_V_CMP_NGT_F32 0x4b +#define SQ_V_CMP_NLE_F32 0x4c +#define SQ_V_CMP_NEQ_F32 0x4d +#define SQ_V_CMP_NLT_F32 0x4e +#define SQ_V_CMP_TRU_F32 0x4f +#define SQ_V_CMPX_F_F32 0x50 +#define SQ_V_CMPX_LT_F32 0x51 +#define SQ_V_CMPX_EQ_F32 0x52 +#define SQ_V_CMPX_LE_F32 0x53 +#define SQ_V_CMPX_GT_F32 0x54 +#define SQ_V_CMPX_LG_F32 0x55 +#define SQ_V_CMPX_GE_F32 0x56 +#define SQ_V_CMPX_O_F32 0x57 +#define SQ_V_CMPX_U_F32 0x58 +#define SQ_V_CMPX_NGE_F32 0x59 +#define SQ_V_CMPX_NLG_F32 0x5a +#define SQ_V_CMPX_NGT_F32 0x5b +#define SQ_V_CMPX_NLE_F32 0x5c +#define SQ_V_CMPX_NEQ_F32 0x5d +#define SQ_V_CMPX_NLT_F32 0x5e +#define SQ_V_CMPX_TRU_F32 0x5f +#define SQ_V_CMP_F_F64 0x60 +#define SQ_V_CMP_LT_F64 0x61 +#define SQ_V_CMP_EQ_F64 0x62 +#define SQ_V_CMP_LE_F64 0x63 +#define SQ_V_CMP_GT_F64 0x64 +#define SQ_V_CMP_LG_F64 0x65 +#define SQ_V_CMP_GE_F64 0x66 +#define SQ_V_CMP_O_F64 0x67 +#define SQ_V_CMP_U_F64 0x68 +#define SQ_V_CMP_NGE_F64 0x69 +#define SQ_V_CMP_NLG_F64 0x6a +#define SQ_V_CMP_NGT_F64 0x6b +#define SQ_V_CMP_NLE_F64 0x6c +#define SQ_V_CMP_NEQ_F64 0x6d +#define SQ_V_CMP_NLT_F64 0x6e +#define SQ_V_CMP_TRU_F64 0x6f +#define SQ_V_CMPX_F_F64 0x70 +#define SQ_V_CMPX_LT_F64 0x71 +#define SQ_V_CMPX_EQ_F64 0x72 +#define SQ_V_CMPX_LE_F64 0x73 +#define SQ_V_CMPX_GT_F64 0x74 +#define SQ_V_CMPX_LG_F64 0x75 +#define SQ_V_CMPX_GE_F64 0x76 +#define SQ_V_CMPX_O_F64 0x77 +#define SQ_V_CMPX_U_F64 0x78 +#define SQ_V_CMPX_NGE_F64 0x79 +#define SQ_V_CMPX_NLG_F64 0x7a +#define SQ_V_CMPX_NGT_F64 0x7b +#define SQ_V_CMPX_NLE_F64 0x7c +#define SQ_V_CMPX_NEQ_F64 0x7d +#define SQ_V_CMPX_NLT_F64 0x7e +#define SQ_V_CMPX_TRU_F64 0x7f +#define SQ_V_CMP_F_I16 0xa0 +#define SQ_V_CMP_LT_I16 0xa1 +#define SQ_V_CMP_EQ_I16 0xa2 +#define SQ_V_CMP_LE_I16 0xa3 +#define SQ_V_CMP_GT_I16 0xa4 +#define SQ_V_CMP_NE_I16 0xa5 +#define SQ_V_CMP_GE_I16 0xa6 +#define SQ_V_CMP_T_I16 0xa7 +#define SQ_V_CMP_F_U16 0xa8 +#define SQ_V_CMP_LT_U16 0xa9 +#define SQ_V_CMP_EQ_U16 0xaa +#define SQ_V_CMP_LE_U16 0xab +#define SQ_V_CMP_GT_U16 0xac +#define SQ_V_CMP_NE_U16 0xad +#define SQ_V_CMP_GE_U16 0xae +#define SQ_V_CMP_T_U16 0xaf +#define SQ_V_CMPX_F_I16 0xb0 +#define SQ_V_CMPX_LT_I16 0xb1 +#define SQ_V_CMPX_EQ_I16 0xb2 +#define SQ_V_CMPX_LE_I16 0xb3 +#define SQ_V_CMPX_GT_I16 0xb4 +#define SQ_V_CMPX_NE_I16 0xb5 +#define SQ_V_CMPX_GE_I16 0xb6 +#define SQ_V_CMPX_T_I16 0xb7 +#define SQ_V_CMPX_F_U16 0xb8 +#define SQ_V_CMPX_LT_U16 0xb9 +#define SQ_V_CMPX_EQ_U16 0xba +#define SQ_V_CMPX_LE_U16 0xbb +#define SQ_V_CMPX_GT_U16 0xbc +#define SQ_V_CMPX_NE_U16 0xbd +#define SQ_V_CMPX_GE_U16 0xbe +#define SQ_V_CMPX_T_U16 0xbf +#define SQ_V_CMP_F_I32 0xc0 +#define SQ_V_CMP_LT_I32 0xc1 +#define SQ_V_CMP_EQ_I32 0xc2 +#define SQ_V_CMP_LE_I32 0xc3 +#define SQ_V_CMP_GT_I32 0xc4 +#define SQ_V_CMP_NE_I32 0xc5 +#define SQ_V_CMP_GE_I32 0xc6 +#define SQ_V_CMP_T_I32 0xc7 +#define SQ_V_CMP_F_U32 0xc8 +#define SQ_V_CMP_LT_U32 0xc9 +#define SQ_V_CMP_EQ_U32 0xca +#define SQ_V_CMP_LE_U32 0xcb +#define SQ_V_CMP_GT_U32 0xcc +#define SQ_V_CMP_NE_U32 0xcd +#define SQ_V_CMP_GE_U32 0xce +#define SQ_V_CMP_T_U32 0xcf +#define SQ_V_CMPX_F_I32 0xd0 +#define SQ_V_CMPX_LT_I32 0xd1 +#define SQ_V_CMPX_EQ_I32 0xd2 +#define SQ_V_CMPX_LE_I32 0xd3 +#define SQ_V_CMPX_GT_I32 0xd4 +#define SQ_V_CMPX_NE_I32 0xd5 +#define SQ_V_CMPX_GE_I32 0xd6 +#define SQ_V_CMPX_T_I32 0xd7 +#define SQ_V_CMPX_F_U32 0xd8 +#define SQ_V_CMPX_LT_U32 0xd9 +#define SQ_V_CMPX_EQ_U32 0xda +#define SQ_V_CMPX_LE_U32 0xdb +#define SQ_V_CMPX_GT_U32 0xdc +#define SQ_V_CMPX_NE_U32 0xdd +#define SQ_V_CMPX_GE_U32 0xde +#define SQ_V_CMPX_T_U32 0xdf +#define SQ_V_CMP_F_I64 0xe0 +#define SQ_V_CMP_LT_I64 0xe1 +#define SQ_V_CMP_EQ_I64 0xe2 +#define SQ_V_CMP_LE_I64 0xe3 +#define SQ_V_CMP_GT_I64 0xe4 +#define SQ_V_CMP_NE_I64 0xe5 +#define SQ_V_CMP_GE_I64 0xe6 +#define SQ_V_CMP_T_I64 0xe7 +#define SQ_V_CMP_F_U64 0xe8 +#define SQ_V_CMP_LT_U64 0xe9 +#define SQ_V_CMP_EQ_U64 0xea +#define SQ_V_CMP_LE_U64 0xeb +#define SQ_V_CMP_GT_U64 0xec +#define SQ_V_CMP_NE_U64 0xed +#define SQ_V_CMP_GE_U64 0xee +#define SQ_V_CMP_T_U64 0xef +#define SQ_V_CMPX_F_I64 0xf0 +#define SQ_V_CMPX_LT_I64 0xf1 +#define SQ_V_CMPX_EQ_I64 0xf2 +#define SQ_V_CMPX_LE_I64 0xf3 +#define SQ_V_CMPX_GT_I64 0xf4 +#define SQ_V_CMPX_NE_I64 0xf5 +#define SQ_V_CMPX_GE_I64 0xf6 +#define SQ_V_CMPX_T_I64 0xf7 +#define SQ_V_CMPX_F_U64 0xf8 +#define SQ_V_CMPX_LT_U64 0xf9 +#define SQ_V_CMPX_EQ_U64 0xfa +#define SQ_V_CMPX_LE_U64 0xfb +#define SQ_V_CMPX_GT_U64 0xfc +#define SQ_V_CMPX_NE_U64 0xfd +#define SQ_V_CMPX_GE_U64 0xfe +#define SQ_V_CMPX_T_U64 0xff +#define SQ_L1 0x1 +#define SQ_L2 0x2 +#define SQ_L3 0x3 +#define SQ_L4 0x4 +#define SQ_L5 0x5 +#define SQ_L6 0x6 +#define SQ_L7 0x7 +#define SQ_L8 0x8 +#define SQ_L9 0x9 +#define SQ_L10 0xa +#define SQ_L11 0xb +#define SQ_L12 0xc +#define SQ_L13 0xd +#define SQ_L14 0xe +#define SQ_L15 0xf +#define SQ_SGPR0 0x0 +#define SQ_SDWA_UNUSED_PAD 0x0 +#define SQ_SDWA_UNUSED_SEXT 0x1 +#define SQ_SDWA_UNUSED_PRESERVE 0x2 +#define SQ_F 0x0 +#define SQ_LT 0x1 +#define SQ_EQ 0x2 +#define SQ_LE 0x3 +#define SQ_GT 0x4 +#define SQ_NE 0x5 +#define SQ_GE 0x6 +#define SQ_T 0x7 +#define SQ_SRC_64_INT 0xc0 +#define SQ_SRC_M_1_INT 0xc1 +#define SQ_SRC_M_2_INT 0xc2 +#define SQ_SRC_M_3_INT 0xc3 +#define SQ_SRC_M_4_INT 0xc4 +#define SQ_SRC_M_5_INT 0xc5 +#define SQ_SRC_M_6_INT 0xc6 +#define SQ_SRC_M_7_INT 0xc7 +#define SQ_SRC_M_8_INT 0xc8 +#define SQ_SRC_M_9_INT 0xc9 +#define SQ_SRC_M_10_INT 0xca +#define SQ_SRC_M_11_INT 0xcb +#define SQ_SRC_M_12_INT 0xcc +#define SQ_SRC_M_13_INT 0xcd +#define SQ_SRC_M_14_INT 0xce +#define SQ_SRC_M_15_INT 0xcf +#define SQ_SRC_M_16_INT 0xd0 +#define SQ_SRC_0_5 0xf0 +#define SQ_SRC_M_0_5 0xf1 +#define SQ_SRC_1 0xf2 +#define SQ_SRC_M_1 0xf3 +#define SQ_SRC_2 0xf4 +#define SQ_SRC_M_2 0xf5 +#define SQ_SRC_4 0xf6 +#define SQ_SRC_M_4 0xf7 +#define SQ_SRC_INV_2PI 0xf8 +#define SQ_SRC_0 0x80 +#define SQ_SRC_1_INT 0x81 +#define SQ_SRC_2_INT 0x82 +#define SQ_SRC_3_INT 0x83 +#define SQ_SRC_4_INT 0x84 +#define SQ_SRC_5_INT 0x85 +#define SQ_SRC_6_INT 0x86 +#define SQ_SRC_7_INT 0x87 +#define SQ_SRC_8_INT 0x88 +#define SQ_SRC_9_INT 0x89 +#define SQ_SRC_10_INT 0x8a +#define SQ_SRC_11_INT 0x8b +#define SQ_SRC_12_INT 0x8c +#define SQ_SRC_13_INT 0x8d +#define SQ_SRC_14_INT 0x8e +#define SQ_SRC_15_INT 0x8f +#define SQ_SRC_16_INT 0x90 +#define SQ_SRC_17_INT 0x91 +#define SQ_SRC_18_INT 0x92 +#define SQ_SRC_19_INT 0x93 +#define SQ_SRC_20_INT 0x94 +#define SQ_SRC_21_INT 0x95 +#define SQ_SRC_22_INT 0x96 +#define SQ_SRC_23_INT 0x97 +#define SQ_SRC_24_INT 0x98 +#define SQ_SRC_25_INT 0x99 +#define SQ_SRC_26_INT 0x9a +#define SQ_SRC_27_INT 0x9b +#define SQ_SRC_28_INT 0x9c +#define SQ_SRC_29_INT 0x9d +#define SQ_SRC_30_INT 0x9e +#define SQ_SRC_31_INT 0x9f +#define SQ_SRC_32_INT 0xa0 +#define SQ_SRC_33_INT 0xa1 +#define SQ_SRC_34_INT 0xa2 +#define SQ_SRC_35_INT 0xa3 +#define SQ_SRC_36_INT 0xa4 +#define SQ_SRC_37_INT 0xa5 +#define SQ_SRC_38_INT 0xa6 +#define SQ_SRC_39_INT 0xa7 +#define SQ_SRC_40_INT 0xa8 +#define SQ_SRC_41_INT 0xa9 +#define SQ_SRC_42_INT 0xaa +#define SQ_SRC_43_INT 0xab +#define SQ_SRC_44_INT 0xac +#define SQ_SRC_45_INT 0xad +#define SQ_SRC_46_INT 0xae +#define SQ_SRC_47_INT 0xaf +#define SQ_SRC_48_INT 0xb0 +#define SQ_SRC_49_INT 0xb1 +#define SQ_SRC_50_INT 0xb2 +#define SQ_SRC_51_INT 0xb3 +#define SQ_SRC_52_INT 0xb4 +#define SQ_SRC_53_INT 0xb5 +#define SQ_SRC_54_INT 0xb6 +#define SQ_SRC_55_INT 0xb7 +#define SQ_SRC_56_INT 0xb8 +#define SQ_SRC_57_INT 0xb9 +#define SQ_SRC_58_INT 0xba +#define SQ_SRC_59_INT 0xbb +#define SQ_SRC_60_INT 0xbc +#define SQ_SRC_61_INT 0xbd +#define SQ_SRC_62_INT 0xbe +#define SQ_SRC_63_INT 0xbf +#define SQ_DS_ADD_U32 0x0 +#define SQ_DS_SUB_U32 0x1 +#define SQ_DS_RSUB_U32 0x2 +#define SQ_DS_INC_U32 0x3 +#define SQ_DS_DEC_U32 0x4 +#define SQ_DS_MIN_I32 0x5 +#define SQ_DS_MAX_I32 0x6 +#define SQ_DS_MIN_U32 0x7 +#define SQ_DS_MAX_U32 0x8 +#define SQ_DS_AND_B32 0x9 +#define SQ_DS_OR_B32 0xa +#define SQ_DS_XOR_B32 0xb +#define SQ_DS_MSKOR_B32 0xc +#define SQ_DS_WRITE_B32 0xd +#define SQ_DS_WRITE2_B32 0xe +#define SQ_DS_WRITE2ST64_B32 0xf +#define SQ_DS_CMPST_B32 0x10 +#define SQ_DS_CMPST_F32 0x11 +#define SQ_DS_MIN_F32 0x12 +#define SQ_DS_MAX_F32 0x13 +#define SQ_DS_NOP 0x14 +#define SQ_DS_ADD_F32 0x15 +#define SQ_DS_WRITE_B8 0x1e +#define SQ_DS_WRITE_B16 0x1f +#define SQ_DS_ADD_RTN_U32 0x20 +#define SQ_DS_SUB_RTN_U32 0x21 +#define SQ_DS_RSUB_RTN_U32 0x22 +#define SQ_DS_INC_RTN_U32 0x23 +#define SQ_DS_DEC_RTN_U32 0x24 +#define SQ_DS_MIN_RTN_I32 0x25 +#define SQ_DS_MAX_RTN_I32 0x26 +#define SQ_DS_MIN_RTN_U32 0x27 +#define SQ_DS_MAX_RTN_U32 0x28 +#define SQ_DS_AND_RTN_B32 0x29 +#define SQ_DS_OR_RTN_B32 0x2a +#define SQ_DS_XOR_RTN_B32 0x2b +#define SQ_DS_MSKOR_RTN_B32 0x2c +#define SQ_DS_WRXCHG_RTN_B32 0x2d +#define SQ_DS_WRXCHG2_RTN_B32 0x2e +#define SQ_DS_WRXCHG2ST64_RTN_B32 0x2f +#define SQ_DS_CMPST_RTN_B32 0x30 +#define SQ_DS_CMPST_RTN_F32 0x31 +#define SQ_DS_MIN_RTN_F32 0x32 +#define SQ_DS_MAX_RTN_F32 0x33 +#define SQ_DS_WRAP_RTN_B32 0x34 +#define SQ_DS_ADD_RTN_F32 0x35 +#define SQ_DS_READ_B32 0x36 +#define SQ_DS_READ2_B32 0x37 +#define SQ_DS_READ2ST64_B32 0x38 +#define SQ_DS_READ_I8 0x39 +#define SQ_DS_READ_U8 0x3a +#define SQ_DS_READ_I16 0x3b +#define SQ_DS_READ_U16 0x3c +#define SQ_DS_SWIZZLE_B32 0x3d +#define SQ_DS_PERMUTE_B32 0x3e +#define SQ_DS_BPERMUTE_B32 0x3f +#define SQ_DS_ADD_U64 0x40 +#define SQ_DS_SUB_U64 0x41 +#define SQ_DS_RSUB_U64 0x42 +#define SQ_DS_INC_U64 0x43 +#define SQ_DS_DEC_U64 0x44 +#define SQ_DS_MIN_I64 0x45 +#define SQ_DS_MAX_I64 0x46 +#define SQ_DS_MIN_U64 0x47 +#define SQ_DS_MAX_U64 0x48 +#define SQ_DS_AND_B64 0x49 +#define SQ_DS_OR_B64 0x4a +#define SQ_DS_XOR_B64 0x4b +#define SQ_DS_MSKOR_B64 0x4c +#define SQ_DS_WRITE_B64 0x4d +#define SQ_DS_WRITE2_B64 0x4e +#define SQ_DS_WRITE2ST64_B64 0x4f +#define SQ_DS_CMPST_B64 0x50 +#define SQ_DS_CMPST_F64 0x51 +#define SQ_DS_MIN_F64 0x52 +#define SQ_DS_MAX_F64 0x53 +#define SQ_DS_ADD_RTN_U64 0x60 +#define SQ_DS_SUB_RTN_U64 0x61 +#define SQ_DS_RSUB_RTN_U64 0x62 +#define SQ_DS_INC_RTN_U64 0x63 +#define SQ_DS_DEC_RTN_U64 0x64 +#define SQ_DS_MIN_RTN_I64 0x65 +#define SQ_DS_MAX_RTN_I64 0x66 +#define SQ_DS_MIN_RTN_U64 0x67 +#define SQ_DS_MAX_RTN_U64 0x68 +#define SQ_DS_AND_RTN_B64 0x69 +#define SQ_DS_OR_RTN_B64 0x6a +#define SQ_DS_XOR_RTN_B64 0x6b +#define SQ_DS_MSKOR_RTN_B64 0x6c +#define SQ_DS_WRXCHG_RTN_B64 0x6d +#define SQ_DS_WRXCHG2_RTN_B64 0x6e +#define SQ_DS_WRXCHG2ST64_RTN_B64 0x6f +#define SQ_DS_CMPST_RTN_B64 0x70 +#define SQ_DS_CMPST_RTN_F64 0x71 +#define SQ_DS_MIN_RTN_F64 0x72 +#define SQ_DS_MAX_RTN_F64 0x73 +#define SQ_DS_READ_B64 0x76 +#define SQ_DS_READ2_B64 0x77 +#define SQ_DS_READ2ST64_B64 0x78 +#define SQ_DS_CONDXCHG32_RTN_B64 0x7e +#define SQ_DS_ADD_SRC2_U32 0x80 +#define SQ_DS_SUB_SRC2_U32 0x81 +#define SQ_DS_RSUB_SRC2_U32 0x82 +#define SQ_DS_INC_SRC2_U32 0x83 +#define SQ_DS_DEC_SRC2_U32 0x84 +#define SQ_DS_MIN_SRC2_I32 0x85 +#define SQ_DS_MAX_SRC2_I32 0x86 +#define SQ_DS_MIN_SRC2_U32 0x87 +#define SQ_DS_MAX_SRC2_U32 0x88 +#define SQ_DS_AND_SRC2_B32 0x89 +#define SQ_DS_OR_SRC2_B32 0x8a +#define SQ_DS_XOR_SRC2_B32 0x8b +#define SQ_DS_WRITE_SRC2_B32 0x8d +#define SQ_DS_MIN_SRC2_F32 0x92 +#define SQ_DS_MAX_SRC2_F32 0x93 +#define SQ_DS_ADD_SRC2_F32 0x95 +#define SQ_DS_GWS_SEMA_RELEASE_ALL 0x98 +#define SQ_DS_GWS_INIT 0x99 +#define SQ_DS_GWS_SEMA_V 0x9a +#define SQ_DS_GWS_SEMA_BR 0x9b +#define SQ_DS_GWS_SEMA_P 0x9c +#define SQ_DS_GWS_BARRIER 0x9d +#define SQ_DS_CONSUME 0xbd +#define SQ_DS_APPEND 0xbe +#define SQ_DS_ORDERED_COUNT 0xbf +#define SQ_DS_ADD_SRC2_U64 0xc0 +#define SQ_DS_SUB_SRC2_U64 0xc1 +#define SQ_DS_RSUB_SRC2_U64 0xc2 +#define SQ_DS_INC_SRC2_U64 0xc3 +#define SQ_DS_DEC_SRC2_U64 0xc4 +#define SQ_DS_MIN_SRC2_I64 0xc5 +#define SQ_DS_MAX_SRC2_I64 0xc6 +#define SQ_DS_MIN_SRC2_U64 0xc7 +#define SQ_DS_MAX_SRC2_U64 0xc8 +#define SQ_DS_AND_SRC2_B64 0xc9 +#define SQ_DS_OR_SRC2_B64 0xca +#define SQ_DS_XOR_SRC2_B64 0xcb +#define SQ_DS_WRITE_SRC2_B64 0xcd +#define SQ_DS_MIN_SRC2_F64 0xd2 +#define SQ_DS_MAX_SRC2_F64 0xd3 +#define SQ_DS_WRITE_B96 0xde +#define SQ_DS_WRITE_B128 0xdf +#define SQ_DS_CONDXCHG32_RTN_B128 0xfd +#define SQ_DS_READ_B96 0xfe +#define SQ_DS_READ_B128 0xff +#define SQ_BUFFER_LOAD_FORMAT_X 0x0 +#define SQ_BUFFER_LOAD_FORMAT_XY 0x1 +#define SQ_BUFFER_LOAD_FORMAT_XYZ 0x2 +#define SQ_BUFFER_LOAD_FORMAT_XYZW 0x3 +#define SQ_BUFFER_STORE_FORMAT_X 0x4 +#define SQ_BUFFER_STORE_FORMAT_XY 0x5 +#define SQ_BUFFER_STORE_FORMAT_XYZ 0x6 +#define SQ_BUFFER_STORE_FORMAT_XYZW 0x7 +#define SQ_BUFFER_LOAD_FORMAT_D16_X 0x8 +#define SQ_BUFFER_LOAD_FORMAT_D16_XY 0x9 +#define SQ_BUFFER_LOAD_FORMAT_D16_XYZ 0xa +#define SQ_BUFFER_LOAD_FORMAT_D16_XYZW 0xb +#define SQ_BUFFER_STORE_FORMAT_D16_X 0xc +#define SQ_BUFFER_STORE_FORMAT_D16_XY 0xd +#define SQ_BUFFER_STORE_FORMAT_D16_XYZ 0xe +#define SQ_BUFFER_STORE_FORMAT_D16_XYZW 0xf +#define SQ_BUFFER_LOAD_UBYTE 0x10 +#define SQ_BUFFER_LOAD_SBYTE 0x11 +#define SQ_BUFFER_LOAD_USHORT 0x12 +#define SQ_BUFFER_LOAD_SSHORT 0x13 +#define SQ_BUFFER_LOAD_DWORD 0x14 +#define SQ_BUFFER_LOAD_DWORDX2 0x15 +#define SQ_BUFFER_LOAD_DWORDX3 0x16 +#define SQ_BUFFER_LOAD_DWORDX4 0x17 +#define SQ_BUFFER_STORE_BYTE 0x18 +#define SQ_BUFFER_STORE_SHORT 0x1a +#define SQ_BUFFER_STORE_DWORD 0x1c +#define SQ_BUFFER_STORE_DWORDX2 0x1d +#define SQ_BUFFER_STORE_DWORDX3 0x1e +#define SQ_BUFFER_STORE_DWORDX4 0x1f +#define SQ_BUFFER_STORE_LDS_DWORD 0x3d +#define SQ_BUFFER_WBINVL1 0x3e +#define SQ_BUFFER_WBINVL1_VOL 0x3f +#define SQ_BUFFER_ATOMIC_SWAP 0x40 +#define SQ_BUFFER_ATOMIC_CMPSWAP 0x41 +#define SQ_BUFFER_ATOMIC_ADD 0x42 +#define SQ_BUFFER_ATOMIC_SUB 0x43 +#define SQ_BUFFER_ATOMIC_SMIN 0x44 +#define SQ_BUFFER_ATOMIC_UMIN 0x45 +#define SQ_BUFFER_ATOMIC_SMAX 0x46 +#define SQ_BUFFER_ATOMIC_UMAX 0x47 +#define SQ_BUFFER_ATOMIC_AND 0x48 +#define SQ_BUFFER_ATOMIC_OR 0x49 +#define SQ_BUFFER_ATOMIC_XOR 0x4a +#define SQ_BUFFER_ATOMIC_INC 0x4b +#define SQ_BUFFER_ATOMIC_DEC 0x4c +#define SQ_BUFFER_ATOMIC_SWAP_X2 0x60 +#define SQ_BUFFER_ATOMIC_CMPSWAP_X2 0x61 +#define SQ_BUFFER_ATOMIC_ADD_X2 0x62 +#define SQ_BUFFER_ATOMIC_SUB_X2 0x63 +#define SQ_BUFFER_ATOMIC_SMIN_X2 0x64 +#define SQ_BUFFER_ATOMIC_UMIN_X2 0x65 +#define SQ_BUFFER_ATOMIC_SMAX_X2 0x66 +#define SQ_BUFFER_ATOMIC_UMAX_X2 0x67 +#define SQ_BUFFER_ATOMIC_AND_X2 0x68 +#define SQ_BUFFER_ATOMIC_OR_X2 0x69 +#define SQ_BUFFER_ATOMIC_XOR_X2 0x6a +#define SQ_BUFFER_ATOMIC_INC_X2 0x6b +#define SQ_BUFFER_ATOMIC_DEC_X2 0x6c +#define SQ_EXEC_LO 0x7e +#define SQ_EXEC_HI 0x7f +#define SQ_SRC_SCC 0xfd +#define SQ_OMOD_OFF 0x0 +#define SQ_OMOD_M2 0x1 +#define SQ_OMOD_M4 0x2 +#define SQ_OMOD_D2 0x3 +#define SQ_DPP_QUAD_PERM 0x0 +#define SQ_DPP_ROW_SL1 0x101 +#define SQ_DPP_ROW_SL2 0x102 +#define SQ_DPP_ROW_SL3 0x103 +#define SQ_DPP_ROW_SL4 0x104 +#define SQ_DPP_ROW_SL5 0x105 +#define SQ_DPP_ROW_SL6 0x106 +#define SQ_DPP_ROW_SL7 0x107 +#define SQ_DPP_ROW_SL8 0x108 +#define SQ_DPP_ROW_SL9 0x109 +#define SQ_DPP_ROW_SL10 0x10a +#define SQ_DPP_ROW_SL11 0x10b +#define SQ_DPP_ROW_SL12 0x10c +#define SQ_DPP_ROW_SL13 0x10d +#define SQ_DPP_ROW_SL14 0x10e +#define SQ_DPP_ROW_SL15 0x10f +#define SQ_DPP_ROW_SR1 0x111 +#define SQ_DPP_ROW_SR2 0x112 +#define SQ_DPP_ROW_SR3 0x113 +#define SQ_DPP_ROW_SR4 0x114 +#define SQ_DPP_ROW_SR5 0x115 +#define SQ_DPP_ROW_SR6 0x116 +#define SQ_DPP_ROW_SR7 0x117 +#define SQ_DPP_ROW_SR8 0x118 +#define SQ_DPP_ROW_SR9 0x119 +#define SQ_DPP_ROW_SR10 0x11a +#define SQ_DPP_ROW_SR11 0x11b +#define SQ_DPP_ROW_SR12 0x11c +#define SQ_DPP_ROW_SR13 0x11d +#define SQ_DPP_ROW_SR14 0x11e +#define SQ_DPP_ROW_SR15 0x11f +#define SQ_DPP_ROW_RR1 0x121 +#define SQ_DPP_ROW_RR2 0x122 +#define SQ_DPP_ROW_RR3 0x123 +#define SQ_DPP_ROW_RR4 0x124 +#define SQ_DPP_ROW_RR5 0x125 +#define SQ_DPP_ROW_RR6 0x126 +#define SQ_DPP_ROW_RR7 0x127 +#define SQ_DPP_ROW_RR8 0x128 +#define SQ_DPP_ROW_RR9 0x129 +#define SQ_DPP_ROW_RR10 0x12a +#define SQ_DPP_ROW_RR11 0x12b +#define SQ_DPP_ROW_RR12 0x12c +#define SQ_DPP_ROW_RR13 0x12d +#define SQ_DPP_ROW_RR14 0x12e +#define SQ_DPP_ROW_RR15 0x12f +#define SQ_DPP_WF_SL1 0x130 +#define SQ_DPP_WF_RL1 0x134 +#define SQ_DPP_WF_SR1 0x138 +#define SQ_DPP_WF_RR1 0x13c +#define SQ_DPP_ROW_MIRROR 0x140 +#define SQ_DPP_ROW_HALF_MIRROR 0x141 +#define SQ_DPP_ROW_BCAST15 0x142 +#define SQ_DPP_ROW_BCAST31 0x143 +#define SQ_EXP_GDS0 0x18 +#define SQ_GS_OP_NOP 0x0 +#define SQ_GS_OP_CUT 0x1 +#define SQ_GS_OP_EMIT 0x2 +#define SQ_GS_OP_EMIT_CUT 0x3 +#define SQ_IMAGE_LOAD 0x0 +#define SQ_IMAGE_LOAD_MIP 0x1 +#define SQ_IMAGE_LOAD_PCK 0x2 +#define SQ_IMAGE_LOAD_PCK_SGN 0x3 +#define SQ_IMAGE_LOAD_MIP_PCK 0x4 +#define SQ_IMAGE_LOAD_MIP_PCK_SGN 0x5 +#define SQ_IMAGE_STORE 0x8 +#define SQ_IMAGE_STORE_MIP 0x9 +#define SQ_IMAGE_STORE_PCK 0xa +#define SQ_IMAGE_STORE_MIP_PCK 0xb +#define SQ_IMAGE_GET_RESINFO 0xe +#define SQ_IMAGE_ATOMIC_SWAP 0x10 +#define SQ_IMAGE_ATOMIC_CMPSWAP 0x11 +#define SQ_IMAGE_ATOMIC_ADD 0x12 +#define SQ_IMAGE_ATOMIC_SUB 0x13 +#define SQ_IMAGE_ATOMIC_SMIN 0x14 +#define SQ_IMAGE_ATOMIC_UMIN 0x15 +#define SQ_IMAGE_ATOMIC_SMAX 0x16 +#define SQ_IMAGE_ATOMIC_UMAX 0x17 +#define SQ_IMAGE_ATOMIC_AND 0x18 +#define SQ_IMAGE_ATOMIC_OR 0x19 +#define SQ_IMAGE_ATOMIC_XOR 0x1a +#define SQ_IMAGE_ATOMIC_INC 0x1b +#define SQ_IMAGE_ATOMIC_DEC 0x1c +#define SQ_IMAGE_SAMPLE 0x20 +#define SQ_IMAGE_SAMPLE_CL 0x21 +#define SQ_IMAGE_SAMPLE_D 0x22 +#define SQ_IMAGE_SAMPLE_D_CL 0x23 +#define SQ_IMAGE_SAMPLE_L 0x24 +#define SQ_IMAGE_SAMPLE_B 0x25 +#define SQ_IMAGE_SAMPLE_B_CL 0x26 +#define SQ_IMAGE_SAMPLE_LZ 0x27 +#define SQ_IMAGE_SAMPLE_C 0x28 +#define SQ_IMAGE_SAMPLE_C_CL 0x29 +#define SQ_IMAGE_SAMPLE_C_D 0x2a +#define SQ_IMAGE_SAMPLE_C_D_CL 0x2b +#define SQ_IMAGE_SAMPLE_C_L 0x2c +#define SQ_IMAGE_SAMPLE_C_B 0x2d +#define SQ_IMAGE_SAMPLE_C_B_CL 0x2e +#define SQ_IMAGE_SAMPLE_C_LZ 0x2f +#define SQ_IMAGE_SAMPLE_O 0x30 +#define SQ_IMAGE_SAMPLE_CL_O 0x31 +#define SQ_IMAGE_SAMPLE_D_O 0x32 +#define SQ_IMAGE_SAMPLE_D_CL_O 0x33 +#define SQ_IMAGE_SAMPLE_L_O 0x34 +#define SQ_IMAGE_SAMPLE_B_O 0x35 +#define SQ_IMAGE_SAMPLE_B_CL_O 0x36 +#define SQ_IMAGE_SAMPLE_LZ_O 0x37 +#define SQ_IMAGE_SAMPLE_C_O 0x38 +#define SQ_IMAGE_SAMPLE_C_CL_O 0x39 +#define SQ_IMAGE_SAMPLE_C_D_O 0x3a +#define SQ_IMAGE_SAMPLE_C_D_CL_O 0x3b +#define SQ_IMAGE_SAMPLE_C_L_O 0x3c +#define SQ_IMAGE_SAMPLE_C_B_O 0x3d +#define SQ_IMAGE_SAMPLE_C_B_CL_O 0x3e +#define SQ_IMAGE_SAMPLE_C_LZ_O 0x3f +#define SQ_IMAGE_GATHER4 0x40 +#define SQ_IMAGE_GATHER4_CL 0x41 +#define SQ_IMAGE_GATHER4_L 0x44 +#define SQ_IMAGE_GATHER4_B 0x45 +#define SQ_IMAGE_GATHER4_B_CL 0x46 +#define SQ_IMAGE_GATHER4_LZ 0x47 +#define SQ_IMAGE_GATHER4_C 0x48 +#define SQ_IMAGE_GATHER4_C_CL 0x49 +#define SQ_IMAGE_GATHER4_C_L 0x4c +#define SQ_IMAGE_GATHER4_C_B 0x4d +#define SQ_IMAGE_GATHER4_C_B_CL 0x4e +#define SQ_IMAGE_GATHER4_C_LZ 0x4f +#define SQ_IMAGE_GATHER4_O 0x50 +#define SQ_IMAGE_GATHER4_CL_O 0x51 +#define SQ_IMAGE_GATHER4_L_O 0x54 +#define SQ_IMAGE_GATHER4_B_O 0x55 +#define SQ_IMAGE_GATHER4_B_CL_O 0x56 +#define SQ_IMAGE_GATHER4_LZ_O 0x57 +#define SQ_IMAGE_GATHER4_C_O 0x58 +#define SQ_IMAGE_GATHER4_C_CL_O 0x59 +#define SQ_IMAGE_GATHER4_C_L_O 0x5c +#define SQ_IMAGE_GATHER4_C_B_O 0x5d +#define SQ_IMAGE_GATHER4_C_B_CL_O 0x5e +#define SQ_IMAGE_GATHER4_C_LZ_O 0x5f +#define SQ_IMAGE_GET_LOD 0x60 +#define SQ_IMAGE_SAMPLE_CD 0x68 +#define SQ_IMAGE_SAMPLE_CD_CL 0x69 +#define SQ_IMAGE_SAMPLE_C_CD 0x6a +#define SQ_IMAGE_SAMPLE_C_CD_CL 0x6b +#define SQ_IMAGE_SAMPLE_CD_O 0x6c +#define SQ_IMAGE_SAMPLE_CD_CL_O 0x6d +#define SQ_IMAGE_SAMPLE_C_CD_O 0x6e +#define SQ_IMAGE_SAMPLE_C_CD_CL_O 0x6f +#define SQ_IMAGE_RSRC256 0x7e +#define SQ_IMAGE_SAMPLER 0x7f +#define SQ_SRC_VCCZ 0xfb +#define SQ_SRC_VGPR0 0x100 +#define SQ_SDWA_BYTE_0 0x0 +#define SQ_SDWA_BYTE_1 0x1 +#define SQ_SDWA_BYTE_2 0x2 +#define SQ_SDWA_BYTE_3 0x3 +#define SQ_SDWA_WORD_0 0x4 +#define SQ_SDWA_WORD_1 0x5 +#define SQ_SDWA_DWORD 0x6 +#define SQ_XNACK_MASK_LO 0x68 +#define SQ_XNACK_MASK_HI 0x69 +#define SQ_TBUFFER_LOAD_FORMAT_X 0x0 +#define SQ_TBUFFER_LOAD_FORMAT_XY 0x1 +#define SQ_TBUFFER_LOAD_FORMAT_XYZ 0x2 +#define SQ_TBUFFER_LOAD_FORMAT_XYZW 0x3 +#define SQ_TBUFFER_STORE_FORMAT_X 0x4 +#define SQ_TBUFFER_STORE_FORMAT_XY 0x5 +#define SQ_TBUFFER_STORE_FORMAT_XYZ 0x6 +#define SQ_TBUFFER_STORE_FORMAT_XYZW 0x7 +#define SQ_TBUFFER_LOAD_FORMAT_D16_X 0x8 +#define SQ_TBUFFER_LOAD_FORMAT_D16_XY 0x9 +#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZ 0xa +#define SQ_TBUFFER_LOAD_FORMAT_D16_XYZW 0xb +#define SQ_TBUFFER_STORE_FORMAT_D16_X 0xc +#define SQ_TBUFFER_STORE_FORMAT_D16_XY 0xd +#define SQ_TBUFFER_STORE_FORMAT_D16_XYZ 0xe +#define SQ_TBUFFER_STORE_FORMAT_D16_XYZW 0xf +#define SQ_CHAN_X 0x0 +#define SQ_CHAN_Y 0x1 +#define SQ_CHAN_Z 0x2 +#define SQ_CHAN_W 0x3 +#define SQ_V_NOP 0x0 +#define SQ_V_MOV_B32 0x1 +#define SQ_V_READFIRSTLANE_B32 0x2 +#define SQ_V_CVT_I32_F64 0x3 +#define SQ_V_CVT_F64_I32 0x4 +#define SQ_V_CVT_F32_I32 0x5 +#define SQ_V_CVT_F32_U32 0x6 +#define SQ_V_CVT_U32_F32 0x7 +#define SQ_V_CVT_I32_F32 0x8 +#define SQ_V_MOV_FED_B32 0x9 +#define SQ_V_CVT_F16_F32 0xa +#define SQ_V_CVT_F32_F16 0xb +#define SQ_V_CVT_RPI_I32_F32 0xc +#define SQ_V_CVT_FLR_I32_F32 0xd +#define SQ_V_CVT_OFF_F32_I4 0xe +#define SQ_V_CVT_F32_F64 0xf +#define SQ_V_CVT_F64_F32 0x10 +#define SQ_V_CVT_F32_UBYTE0 0x11 +#define SQ_V_CVT_F32_UBYTE1 0x12 +#define SQ_V_CVT_F32_UBYTE2 0x13 +#define SQ_V_CVT_F32_UBYTE3 0x14 +#define SQ_V_CVT_U32_F64 0x15 +#define SQ_V_CVT_F64_U32 0x16 +#define SQ_V_TRUNC_F64 0x17 +#define SQ_V_CEIL_F64 0x18 +#define SQ_V_RNDNE_F64 0x19 +#define SQ_V_FLOOR_F64 0x1a +#define SQ_V_FRACT_F32 0x1b +#define SQ_V_TRUNC_F32 0x1c +#define SQ_V_CEIL_F32 0x1d +#define SQ_V_RNDNE_F32 0x1e +#define SQ_V_FLOOR_F32 0x1f +#define SQ_V_EXP_F32 0x20 +#define SQ_V_LOG_F32 0x21 +#define SQ_V_RCP_F32 0x22 +#define SQ_V_RCP_IFLAG_F32 0x23 +#define SQ_V_RSQ_F32 0x24 +#define SQ_V_RCP_F64 0x25 +#define SQ_V_RSQ_F64 0x26 +#define SQ_V_SQRT_F32 0x27 +#define SQ_V_SQRT_F64 0x28 +#define SQ_V_SIN_F32 0x29 +#define SQ_V_COS_F32 0x2a +#define SQ_V_NOT_B32 0x2b +#define SQ_V_BFREV_B32 0x2c +#define SQ_V_FFBH_U32 0x2d +#define SQ_V_FFBL_B32 0x2e +#define SQ_V_FFBH_I32 0x2f +#define SQ_V_FREXP_EXP_I32_F64 0x30 +#define SQ_V_FREXP_MANT_F64 0x31 +#define SQ_V_FRACT_F64 0x32 +#define SQ_V_FREXP_EXP_I32_F32 0x33 +#define SQ_V_FREXP_MANT_F32 0x34 +#define SQ_V_CLREXCP 0x35 +#define SQ_V_MOVRELD_B32 0x36 +#define SQ_V_MOVRELS_B32 0x37 +#define SQ_V_MOVRELSD_B32 0x38 +#define SQ_V_CVT_F16_U16 0x39 +#define SQ_V_CVT_F16_I16 0x3a +#define SQ_V_CVT_U16_F16 0x3b +#define SQ_V_CVT_I16_F16 0x3c +#define SQ_V_RCP_F16 0x3d +#define SQ_V_SQRT_F16 0x3e +#define SQ_V_RSQ_F16 0x3f +#define SQ_V_LOG_F16 0x40 +#define SQ_V_EXP_F16 0x41 +#define SQ_V_FREXP_MANT_F16 0x42 +#define SQ_V_FREXP_EXP_I16_F16 0x43 +#define SQ_V_FLOOR_F16 0x44 +#define SQ_V_CEIL_F16 0x45 +#define SQ_V_TRUNC_F16 0x46 +#define SQ_V_RNDNE_F16 0x47 +#define SQ_V_FRACT_F16 0x48 +#define SQ_V_SIN_F16 0x49 +#define SQ_V_COS_F16 0x4a +#define SQ_V_EXP_LEGACY_F32 0x4b +#define SQ_V_LOG_LEGACY_F32 0x4c +#define SQ_V_CVT_NORM_I16_F16 0x4d +#define SQ_V_CVT_NORM_U16_F16 0x4e +#define SQ_SRC_SDWA 0xf9 +#define SQ_V_OPC_OFFSET 0x0 +#define SQ_V_OP2_OFFSET 0x100 +#define SQ_V_OP1_OFFSET 0x140 +#define SQ_V_INTRP_OFFSET 0x270 +#define SQ_V_INTERP_P1_F32 0x0 +#define SQ_V_INTERP_P2_F32 0x1 +#define SQ_V_INTERP_MOV_F32 0x2 +#define SQ_S_NOP 0x0 +#define SQ_S_ENDPGM 0x1 +#define SQ_S_BRANCH 0x2 +#define SQ_S_WAKEUP 0x3 +#define SQ_S_CBRANCH_SCC0 0x4 +#define SQ_S_CBRANCH_SCC1 0x5 +#define SQ_S_CBRANCH_VCCZ 0x6 +#define SQ_S_CBRANCH_VCCNZ 0x7 +#define SQ_S_CBRANCH_EXECZ 0x8 +#define SQ_S_CBRANCH_EXECNZ 0x9 +#define SQ_S_BARRIER 0xa +#define SQ_S_SETKILL 0xb +#define SQ_S_WAITCNT 0xc +#define SQ_S_SETHALT 0xd +#define SQ_S_SLEEP 0xe +#define SQ_S_SETPRIO 0xf +#define SQ_S_SENDMSG 0x10 +#define SQ_S_SENDMSGHALT 0x11 +#define SQ_S_TRAP 0x12 +#define SQ_S_ICACHE_INV 0x13 +#define SQ_S_INCPERFLEVEL 0x14 +#define SQ_S_DECPERFLEVEL 0x15 +#define SQ_S_TTRACEDATA 0x16 +#define SQ_S_CBRANCH_CDBGSYS 0x17 +#define SQ_S_CBRANCH_CDBGUSER 0x18 +#define SQ_S_CBRANCH_CDBGSYS_OR_USER 0x19 +#define SQ_S_CBRANCH_CDBGSYS_AND_USER 0x1a +#define SQ_S_ENDPGM_SAVED 0x1b +#define SQ_S_SET_GPR_IDX_OFF 0x1c +#define SQ_S_SET_GPR_IDX_MODE 0x1d +#define SQ_SRC_DPP 0xfa +#define SQ_SRC_LITERAL 0xff +#define SQ_VCC_LO 0x6a +#define SQ_VCC_HI 0x6b +#define SQ_PARAM_P10 0x0 +#define SQ_PARAM_P20 0x1 +#define SQ_PARAM_P0 0x2 +#define SQ_SRC_LDS_DIRECT 0xfe +#define SQ_V_CNDMASK_B32 0x0 +#define SQ_V_ADD_F32 0x1 +#define SQ_V_SUB_F32 0x2 +#define SQ_V_SUBREV_F32 0x3 +#define SQ_V_MUL_LEGACY_F32 0x4 +#define SQ_V_MUL_F32 0x5 +#define SQ_V_MUL_I32_I24 0x6 +#define SQ_V_MUL_HI_I32_I24 0x7 +#define SQ_V_MUL_U32_U24 0x8 +#define SQ_V_MUL_HI_U32_U24 0x9 +#define SQ_V_MIN_F32 0xa +#define SQ_V_MAX_F32 0xb +#define SQ_V_MIN_I32 0xc +#define SQ_V_MAX_I32 0xd +#define SQ_V_MIN_U32 0xe +#define SQ_V_MAX_U32 0xf +#define SQ_V_LSHRREV_B32 0x10 +#define SQ_V_ASHRREV_I32 0x11 +#define SQ_V_LSHLREV_B32 0x12 +#define SQ_V_AND_B32 0x13 +#define SQ_V_OR_B32 0x14 +#define SQ_V_XOR_B32 0x15 +#define SQ_V_MAC_F32 0x16 +#define SQ_V_MADMK_F32 0x17 +#define SQ_V_MADAK_F32 0x18 +#define SQ_V_ADD_U32 0x19 +#define SQ_V_SUB_U32 0x1a +#define SQ_V_SUBREV_U32 0x1b +#define SQ_V_ADDC_U32 0x1c +#define SQ_V_SUBB_U32 0x1d +#define SQ_V_SUBBREV_U32 0x1e +#define SQ_V_ADD_F16 0x1f +#define SQ_V_SUB_F16 0x20 +#define SQ_V_SUBREV_F16 0x21 +#define SQ_V_MUL_F16 0x22 +#define SQ_V_MAC_F16 0x23 +#define SQ_V_MADMK_F16 0x24 +#define SQ_V_MADAK_F16 0x25 +#define SQ_V_ADD_U16 0x26 +#define SQ_V_SUB_U16 0x27 +#define SQ_V_SUBREV_U16 0x28 +#define SQ_V_MUL_LO_U16 0x29 +#define SQ_V_LSHLREV_B16 0x2a +#define SQ_V_LSHRREV_B16 0x2b +#define SQ_V_ASHRREV_I16 0x2c +#define SQ_V_MAX_F16 0x2d +#define SQ_V_MIN_F16 0x2e +#define SQ_V_MAX_U16 0x2f +#define SQ_V_MAX_I16 0x30 +#define SQ_V_MIN_U16 0x31 +#define SQ_V_MIN_I16 0x32 +#define SQ_V_LDEXP_F16 0x33 +#define SQ_FLAT_LOAD_UBYTE 0x10 +#define SQ_FLAT_LOAD_SBYTE 0x11 +#define SQ_FLAT_LOAD_USHORT 0x12 +#define SQ_FLAT_LOAD_SSHORT 0x13 +#define SQ_FLAT_LOAD_DWORD 0x14 +#define SQ_FLAT_LOAD_DWORDX2 0x15 +#define SQ_FLAT_LOAD_DWORDX3 0x16 +#define SQ_FLAT_LOAD_DWORDX4 0x17 +#define SQ_FLAT_STORE_BYTE 0x18 +#define SQ_FLAT_STORE_SHORT 0x1a +#define SQ_FLAT_STORE_DWORD 0x1c +#define SQ_FLAT_STORE_DWORDX2 0x1d +#define SQ_FLAT_STORE_DWORDX3 0x1e +#define SQ_FLAT_STORE_DWORDX4 0x1f +#define SQ_FLAT_ATOMIC_SWAP 0x40 +#define SQ_FLAT_ATOMIC_CMPSWAP 0x41 +#define SQ_FLAT_ATOMIC_ADD 0x42 +#define SQ_FLAT_ATOMIC_SUB 0x43 +#define SQ_FLAT_ATOMIC_SMIN 0x44 +#define SQ_FLAT_ATOMIC_UMIN 0x45 +#define SQ_FLAT_ATOMIC_SMAX 0x46 +#define SQ_FLAT_ATOMIC_UMAX 0x47 +#define SQ_FLAT_ATOMIC_AND 0x48 +#define SQ_FLAT_ATOMIC_OR 0x49 +#define SQ_FLAT_ATOMIC_XOR 0x4a +#define SQ_FLAT_ATOMIC_INC 0x4b +#define SQ_FLAT_ATOMIC_DEC 0x4c +#define SQ_FLAT_ATOMIC_SWAP_X2 0x60 +#define SQ_FLAT_ATOMIC_CMPSWAP_X2 0x61 +#define SQ_FLAT_ATOMIC_ADD_X2 0x62 +#define SQ_FLAT_ATOMIC_SUB_X2 0x63 +#define SQ_FLAT_ATOMIC_SMIN_X2 0x64 +#define SQ_FLAT_ATOMIC_UMIN_X2 0x65 +#define SQ_FLAT_ATOMIC_SMAX_X2 0x66 +#define SQ_FLAT_ATOMIC_UMAX_X2 0x67 +#define SQ_FLAT_ATOMIC_AND_X2 0x68 +#define SQ_FLAT_ATOMIC_OR_X2 0x69 +#define SQ_FLAT_ATOMIC_XOR_X2 0x6a +#define SQ_FLAT_ATOMIC_INC_X2 0x6b +#define SQ_FLAT_ATOMIC_DEC_X2 0x6c +#define SQ_S_CMP_EQ_I32 0x0 +#define SQ_S_CMP_LG_I32 0x1 +#define SQ_S_CMP_GT_I32 0x2 +#define SQ_S_CMP_GE_I32 0x3 +#define SQ_S_CMP_LT_I32 0x4 +#define SQ_S_CMP_LE_I32 0x5 +#define SQ_S_CMP_EQ_U32 0x6 +#define SQ_S_CMP_LG_U32 0x7 +#define SQ_S_CMP_GT_U32 0x8 +#define SQ_S_CMP_GE_U32 0x9 +#define SQ_S_CMP_LT_U32 0xa +#define SQ_S_CMP_LE_U32 0xb +#define SQ_S_BITCMP0_B32 0xc +#define SQ_S_BITCMP1_B32 0xd +#define SQ_S_BITCMP0_B64 0xe +#define SQ_S_BITCMP1_B64 0xf +#define SQ_S_SETVSKIP 0x10 +#define SQ_S_SET_GPR_IDX_ON 0x11 +#define SQ_S_CMP_EQ_U64 0x12 +#define SQ_S_CMP_LG_U64 0x13 +#define SQ_M0 0x7c +#define SQ_V_MAD_LEGACY_F32 0x1c0 +#define SQ_V_MAD_F32 0x1c1 +#define SQ_V_MAD_I32_I24 0x1c2 +#define SQ_V_MAD_U32_U24 0x1c3 +#define SQ_V_CUBEID_F32 0x1c4 +#define SQ_V_CUBESC_F32 0x1c5 +#define SQ_V_CUBETC_F32 0x1c6 +#define SQ_V_CUBEMA_F32 0x1c7 +#define SQ_V_BFE_U32 0x1c8 +#define SQ_V_BFE_I32 0x1c9 +#define SQ_V_BFI_B32 0x1ca +#define SQ_V_FMA_F32 0x1cb +#define SQ_V_FMA_F64 0x1cc +#define SQ_V_LERP_U8 0x1cd +#define SQ_V_ALIGNBIT_B32 0x1ce +#define SQ_V_ALIGNBYTE_B32 0x1cf +#define SQ_V_MIN3_F32 0x1d0 +#define SQ_V_MIN3_I32 0x1d1 +#define SQ_V_MIN3_U32 0x1d2 +#define SQ_V_MAX3_F32 0x1d3 +#define SQ_V_MAX3_I32 0x1d4 +#define SQ_V_MAX3_U32 0x1d5 +#define SQ_V_MED3_F32 0x1d6 +#define SQ_V_MED3_I32 0x1d7 +#define SQ_V_MED3_U32 0x1d8 +#define SQ_V_SAD_U8 0x1d9 +#define SQ_V_SAD_HI_U8 0x1da +#define SQ_V_SAD_U16 0x1db +#define SQ_V_SAD_U32 0x1dc +#define SQ_V_CVT_PK_U8_F32 0x1dd +#define SQ_V_DIV_FIXUP_F32 0x1de +#define SQ_V_DIV_FIXUP_F64 0x1df +#define SQ_V_DIV_SCALE_F32 0x1e0 +#define SQ_V_DIV_SCALE_F64 0x1e1 +#define SQ_V_DIV_FMAS_F32 0x1e2 +#define SQ_V_DIV_FMAS_F64 0x1e3 +#define SQ_V_MSAD_U8 0x1e4 +#define SQ_V_QSAD_PK_U16_U8 0x1e5 +#define SQ_V_MQSAD_PK_U16_U8 0x1e6 +#define SQ_V_MQSAD_U32_U8 0x1e7 +#define SQ_V_MAD_U64_U32 0x1e8 +#define SQ_V_MAD_I64_I32 0x1e9 +#define SQ_V_MAD_F16 0x1ea +#define SQ_V_MAD_U16 0x1eb +#define SQ_V_MAD_I16 0x1ec +#define SQ_V_PERM_B32 0x1ed +#define SQ_V_FMA_F16 0x1ee +#define SQ_V_DIV_FIXUP_F16 0x1ef +#define SQ_V_CVT_PKACCUM_U8_F32 0x1f0 +#define SQ_V_INTERP_P1LL_F16 0x274 +#define SQ_V_INTERP_P1LV_F16 0x275 +#define SQ_V_INTERP_P2_F16 0x276 +#define SQ_V_ADD_F64 0x280 +#define SQ_V_MUL_F64 0x281 +#define SQ_V_MIN_F64 0x282 +#define SQ_V_MAX_F64 0x283 +#define SQ_V_LDEXP_F64 0x284 +#define SQ_V_MUL_LO_U32 0x285 +#define SQ_V_MUL_HI_U32 0x286 +#define SQ_V_MUL_HI_I32 0x287 +#define SQ_V_LDEXP_F32 0x288 +#define SQ_V_READLANE_B32 0x289 +#define SQ_V_WRITELANE_B32 0x28a +#define SQ_V_BCNT_U32_B32 0x28b +#define SQ_V_MBCNT_LO_U32_B32 0x28c +#define SQ_V_MBCNT_HI_U32_B32 0x28d +#define SQ_V_MAC_LEGACY_F32 0x28e +#define SQ_V_LSHLREV_B64 0x28f +#define SQ_V_LSHRREV_B64 0x290 +#define SQ_V_ASHRREV_I64 0x291 +#define SQ_V_TRIG_PREOP_F64 0x292 +#define SQ_V_BFM_B32 0x293 +#define SQ_V_CVT_PKNORM_I16_F32 0x294 +#define SQ_V_CVT_PKNORM_U16_F32 0x295 +#define SQ_V_CVT_PKRTZ_F16_F32 0x296 +#define SQ_V_CVT_PK_U16_U32 0x297 +#define SQ_V_CVT_PK_I16_I32 0x298 +#define SQ_V_CVT_PKNORM_I16_F16 0x299 +#define SQ_V_CVT_PKNORM_U16_F16 0x29a +#define SQ_VCC_ALL 0x0 +#define SQ_SRC_EXECZ 0xfc +#define SQ_FLAT_SCRATCH_LO 0x66 +#define SQ_FLAT_SCRATCH_HI 0x67 +#define SQ_SYSMSG_OP_ECC_ERR_INTERRUPT 0x1 +#define SQ_SYSMSG_OP_REG_RD 0x2 +#define SQ_SYSMSG_OP_HOST_TRAP_ACK 0x3 +#define SQ_SYSMSG_OP_TTRACE_PC 0x4 +#define SQ_HW_REG_MODE 0x1 +#define SQ_HW_REG_STATUS 0x2 +#define SQ_HW_REG_TRAPSTS 0x3 +#define SQ_HW_REG_HW_ID 0x4 +#define SQ_HW_REG_GPR_ALLOC 0x5 +#define SQ_HW_REG_LDS_ALLOC 0x6 +#define SQ_HW_REG_IB_STS 0x7 +#define SQ_HW_REG_PC_LO 0x8 +#define SQ_HW_REG_PC_HI 0x9 +#define SQ_HW_REG_INST_DW0 0xa +#define SQ_HW_REG_INST_DW1 0xb +#define SQ_HW_REG_IB_DBG0 0xc +#define SQ_HW_REG_IB_DBG1 0xd +#define SQ_DPP_BOUND_OFF 0x0 +#define SQ_DPP_BOUND_ZERO 0x1 +#define SQ_R1 0x1 +#define SQ_R2 0x2 +#define SQ_R3 0x3 +#define SQ_R4 0x4 +#define SQ_R5 0x5 +#define SQ_R6 0x6 +#define SQ_R7 0x7 +#define SQ_R8 0x8 +#define SQ_R9 0x9 +#define SQ_R10 0xa +#define SQ_R11 0xb +#define SQ_R12 0xc +#define SQ_R13 0xd +#define SQ_R14 0xe +#define SQ_R15 0xf +#define SQ_S_ADD_U32 0x0 +#define SQ_S_SUB_U32 0x1 +#define SQ_S_ADD_I32 0x2 +#define SQ_S_SUB_I32 0x3 +#define SQ_S_ADDC_U32 0x4 +#define SQ_S_SUBB_U32 0x5 +#define SQ_S_MIN_I32 0x6 +#define SQ_S_MIN_U32 0x7 +#define SQ_S_MAX_I32 0x8 +#define SQ_S_MAX_U32 0x9 +#define SQ_S_CSELECT_B32 0xa +#define SQ_S_CSELECT_B64 0xb +#define SQ_S_AND_B32 0xc +#define SQ_S_AND_B64 0xd +#define SQ_S_OR_B32 0xe +#define SQ_S_OR_B64 0xf +#define SQ_S_XOR_B32 0x10 +#define SQ_S_XOR_B64 0x11 +#define SQ_S_ANDN2_B32 0x12 +#define SQ_S_ANDN2_B64 0x13 +#define SQ_S_ORN2_B32 0x14 +#define SQ_S_ORN2_B64 0x15 +#define SQ_S_NAND_B32 0x16 +#define SQ_S_NAND_B64 0x17 +#define SQ_S_NOR_B32 0x18 +#define SQ_S_NOR_B64 0x19 +#define SQ_S_XNOR_B32 0x1a +#define SQ_S_XNOR_B64 0x1b +#define SQ_S_LSHL_B32 0x1c +#define SQ_S_LSHL_B64 0x1d +#define SQ_S_LSHR_B32 0x1e +#define SQ_S_LSHR_B64 0x1f +#define SQ_S_ASHR_I32 0x20 +#define SQ_S_ASHR_I64 0x21 +#define SQ_S_BFM_B32 0x22 +#define SQ_S_BFM_B64 0x23 +#define SQ_S_MUL_I32 0x24 +#define SQ_S_BFE_U32 0x25 +#define SQ_S_BFE_I32 0x26 +#define SQ_S_BFE_U64 0x27 +#define SQ_S_BFE_I64 0x28 +#define SQ_S_CBRANCH_G_FORK 0x29 +#define SQ_S_ABSDIFF_I32 0x2a +#define SQ_S_RFE_RESTORE_B64 0x2b +#define SQ_MSG_INTERRUPT 0x1 +#define SQ_MSG_GS 0x2 +#define SQ_MSG_GS_DONE 0x3 +#define SQ_MSG_SAVEWAVE 0x4 +#define SQ_MSG_SYSMSG 0xf +typedef enum SX_BLEND_OPT { + BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x0, + BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x1, + BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x2, + BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x3, + BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x4, + BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x5, + BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x6, + BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x7, +} SX_BLEND_OPT; +typedef enum SX_OPT_COMB_FCN { + OPT_COMB_NONE = 0x0, + OPT_COMB_ADD = 0x1, + OPT_COMB_SUBTRACT = 0x2, + OPT_COMB_MIN = 0x3, + OPT_COMB_MAX = 0x4, + OPT_COMB_REVSUBTRACT = 0x5, + OPT_COMB_BLEND_DISABLED = 0x6, + OPT_COMB_SAFE_ADD = 0x7, +} SX_OPT_COMB_FCN; +typedef enum SX_DOWNCONVERT_FORMAT { + SX_RT_EXPORT_NO_CONVERSION = 0x0, + SX_RT_EXPORT_32_R = 0x1, + SX_RT_EXPORT_32_A = 0x2, + SX_RT_EXPORT_10_11_11 = 0x3, + SX_RT_EXPORT_2_10_10_10 = 0x4, + SX_RT_EXPORT_8_8_8_8 = 0x5, + SX_RT_EXPORT_5_6_5 = 0x6, + SX_RT_EXPORT_1_5_5_5 = 0x7, + SX_RT_EXPORT_4_4_4_4 = 0x8, + SX_RT_EXPORT_16_16_GR = 0x9, + SX_RT_EXPORT_16_16_AR = 0xa, +} SX_DOWNCONVERT_FORMAT; +typedef enum TEX_BORDER_COLOR_TYPE { + TEX_BorderColor_TransparentBlack = 0x0, + TEX_BorderColor_OpaqueBlack = 0x1, + TEX_BorderColor_OpaqueWhite = 0x2, + TEX_BorderColor_Register = 0x3, +} TEX_BORDER_COLOR_TYPE; +typedef enum TEX_CHROMA_KEY { + TEX_ChromaKey_Disabled = 0x0, + TEX_ChromaKey_Kill = 0x1, + TEX_ChromaKey_Blend = 0x2, + TEX_ChromaKey_RESERVED_3 = 0x3, +} TEX_CHROMA_KEY; +typedef enum TEX_CLAMP { + TEX_Clamp_Repeat = 0x0, + TEX_Clamp_Mirror = 0x1, + TEX_Clamp_ClampToLast = 0x2, + TEX_Clamp_MirrorOnceToLast = 0x3, + TEX_Clamp_ClampHalfToBorder = 0x4, + TEX_Clamp_MirrorOnceHalfToBorder = 0x5, + TEX_Clamp_ClampToBorder = 0x6, + TEX_Clamp_MirrorOnceToBorder = 0x7, +} TEX_CLAMP; +typedef enum TEX_COORD_TYPE { + TEX_CoordType_Unnormalized = 0x0, + TEX_CoordType_Normalized = 0x1, +} TEX_COORD_TYPE; +typedef enum TEX_DEPTH_COMPARE_FUNCTION { + TEX_DepthCompareFunction_Never = 0x0, + TEX_DepthCompareFunction_Less = 0x1, + TEX_DepthCompareFunction_Equal = 0x2, + TEX_DepthCompareFunction_LessEqual = 0x3, + TEX_DepthCompareFunction_Greater = 0x4, + TEX_DepthCompareFunction_NotEqual = 0x5, + TEX_DepthCompareFunction_GreaterEqual = 0x6, + TEX_DepthCompareFunction_Always = 0x7, +} TEX_DEPTH_COMPARE_FUNCTION; +typedef enum TEX_DIM { + TEX_Dim_1D = 0x0, + TEX_Dim_2D = 0x1, + TEX_Dim_3D = 0x2, + TEX_Dim_CubeMap = 0x3, + TEX_Dim_1DArray = 0x4, + TEX_Dim_2DArray = 0x5, + TEX_Dim_2D_MSAA = 0x6, + TEX_Dim_2DArray_MSAA = 0x7, +} TEX_DIM; +typedef enum TEX_FORMAT_COMP { + TEX_FormatComp_Unsigned = 0x0, + TEX_FormatComp_Signed = 0x1, + TEX_FormatComp_UnsignedBiased = 0x2, + TEX_FormatComp_RESERVED_3 = 0x3, +} TEX_FORMAT_COMP; +typedef enum TEX_MAX_ANISO_RATIO { + TEX_MaxAnisoRatio_1to1 = 0x0, + TEX_MaxAnisoRatio_2to1 = 0x1, + TEX_MaxAnisoRatio_4to1 = 0x2, + TEX_MaxAnisoRatio_8to1 = 0x3, + TEX_MaxAnisoRatio_16to1 = 0x4, + TEX_MaxAnisoRatio_RESERVED_5 = 0x5, + TEX_MaxAnisoRatio_RESERVED_6 = 0x6, + TEX_MaxAnisoRatio_RESERVED_7 = 0x7, +} TEX_MAX_ANISO_RATIO; +typedef enum TEX_MIP_FILTER { + TEX_MipFilter_None = 0x0, + TEX_MipFilter_Point = 0x1, + TEX_MipFilter_Linear = 0x2, + TEX_MipFilter_Point_Aniso_Adj = 0x3, +} TEX_MIP_FILTER; +typedef enum TEX_REQUEST_SIZE { + TEX_RequestSize_32B = 0x0, + TEX_RequestSize_64B = 0x1, + TEX_RequestSize_128B = 0x2, + TEX_RequestSize_2X64B = 0x3, +} TEX_REQUEST_SIZE; +typedef enum TEX_SAMPLER_TYPE { + TEX_SamplerType_Invalid = 0x0, + TEX_SamplerType_Valid = 0x1, +} TEX_SAMPLER_TYPE; +typedef enum TEX_XY_FILTER { + TEX_XYFilter_Point = 0x0, + TEX_XYFilter_Linear = 0x1, + TEX_XYFilter_AnisoPoint = 0x2, + TEX_XYFilter_AnisoLinear = 0x3, +} TEX_XY_FILTER; +typedef enum TEX_Z_FILTER { + TEX_ZFilter_None = 0x0, + TEX_ZFilter_Point = 0x1, + TEX_ZFilter_Linear = 0x2, + TEX_ZFilter_RESERVED_3 = 0x3, +} TEX_Z_FILTER; +typedef enum VTX_CLAMP { + VTX_Clamp_ClampToZero = 0x0, + VTX_Clamp_ClampToNAN = 0x1, +} VTX_CLAMP; +typedef enum VTX_FETCH_TYPE { + VTX_FetchType_VertexData = 0x0, + VTX_FetchType_InstanceData = 0x1, + VTX_FetchType_NoIndexOffset = 0x2, + VTX_FetchType_RESERVED_3 = 0x3, +} VTX_FETCH_TYPE; +typedef enum VTX_FORMAT_COMP_ALL { + VTX_FormatCompAll_Unsigned = 0x0, + VTX_FormatCompAll_Signed = 0x1, +} VTX_FORMAT_COMP_ALL; +typedef enum VTX_MEM_REQUEST_SIZE { + VTX_MemRequestSize_32B = 0x0, + VTX_MemRequestSize_64B = 0x1, +} VTX_MEM_REQUEST_SIZE; +typedef enum TVX_DATA_FORMAT { + TVX_FMT_INVALID = 0x0, + TVX_FMT_8 = 0x1, + TVX_FMT_4_4 = 0x2, + TVX_FMT_3_3_2 = 0x3, + TVX_FMT_RESERVED_4 = 0x4, + TVX_FMT_16 = 0x5, + TVX_FMT_16_FLOAT = 0x6, + TVX_FMT_8_8 = 0x7, + TVX_FMT_5_6_5 = 0x8, + TVX_FMT_6_5_5 = 0x9, + TVX_FMT_1_5_5_5 = 0xa, + TVX_FMT_4_4_4_4 = 0xb, + TVX_FMT_5_5_5_1 = 0xc, + TVX_FMT_32 = 0xd, + TVX_FMT_32_FLOAT = 0xe, + TVX_FMT_16_16 = 0xf, + TVX_FMT_16_16_FLOAT = 0x10, + TVX_FMT_8_24 = 0x11, + TVX_FMT_8_24_FLOAT = 0x12, + TVX_FMT_24_8 = 0x13, + TVX_FMT_24_8_FLOAT = 0x14, + TVX_FMT_10_11_11 = 0x15, + TVX_FMT_10_11_11_FLOAT = 0x16, + TVX_FMT_11_11_10 = 0x17, + TVX_FMT_11_11_10_FLOAT = 0x18, + TVX_FMT_2_10_10_10 = 0x19, + TVX_FMT_8_8_8_8 = 0x1a, + TVX_FMT_10_10_10_2 = 0x1b, + TVX_FMT_X24_8_32_FLOAT = 0x1c, + TVX_FMT_32_32 = 0x1d, + TVX_FMT_32_32_FLOAT = 0x1e, + TVX_FMT_16_16_16_16 = 0x1f, + TVX_FMT_16_16_16_16_FLOAT = 0x20, + TVX_FMT_RESERVED_33 = 0x21, + TVX_FMT_32_32_32_32 = 0x22, + TVX_FMT_32_32_32_32_FLOAT = 0x23, + TVX_FMT_RESERVED_36 = 0x24, + TVX_FMT_1 = 0x25, + TVX_FMT_1_REVERSED = 0x26, + TVX_FMT_GB_GR = 0x27, + TVX_FMT_BG_RG = 0x28, + TVX_FMT_32_AS_8 = 0x29, + TVX_FMT_32_AS_8_8 = 0x2a, + TVX_FMT_5_9_9_9_SHAREDEXP = 0x2b, + TVX_FMT_8_8_8 = 0x2c, + TVX_FMT_16_16_16 = 0x2d, + TVX_FMT_16_16_16_FLOAT = 0x2e, + TVX_FMT_32_32_32 = 0x2f, + TVX_FMT_32_32_32_FLOAT = 0x30, + TVX_FMT_BC1 = 0x31, + TVX_FMT_BC2 = 0x32, + TVX_FMT_BC3 = 0x33, + TVX_FMT_BC4 = 0x34, + TVX_FMT_BC5 = 0x35, + TVX_FMT_APC0 = 0x36, + TVX_FMT_APC1 = 0x37, + TVX_FMT_APC2 = 0x38, + TVX_FMT_APC3 = 0x39, + TVX_FMT_APC4 = 0x3a, + TVX_FMT_APC5 = 0x3b, + TVX_FMT_APC6 = 0x3c, + TVX_FMT_APC7 = 0x3d, + TVX_FMT_CTX1 = 0x3e, + TVX_FMT_RESERVED_63 = 0x3f, +} TVX_DATA_FORMAT; +typedef enum TVX_DST_SEL { + TVX_DstSel_X = 0x0, + TVX_DstSel_Y = 0x1, + TVX_DstSel_Z = 0x2, + TVX_DstSel_W = 0x3, + TVX_DstSel_0f = 0x4, + TVX_DstSel_1f = 0x5, + TVX_DstSel_RESERVED_6 = 0x6, + TVX_DstSel_Mask = 0x7, +} TVX_DST_SEL; +typedef enum TVX_ENDIAN_SWAP { + TVX_EndianSwap_None = 0x0, + TVX_EndianSwap_8in16 = 0x1, + TVX_EndianSwap_8in32 = 0x2, + TVX_EndianSwap_8in64 = 0x3, +} TVX_ENDIAN_SWAP; +typedef enum TVX_INST { + TVX_Inst_NormalVertexFetch = 0x0, + TVX_Inst_SemanticVertexFetch = 0x1, + TVX_Inst_RESERVED_2 = 0x2, + TVX_Inst_LD = 0x3, + TVX_Inst_GetTextureResInfo = 0x4, + TVX_Inst_GetNumberOfSamples = 0x5, + TVX_Inst_GetLOD = 0x6, + TVX_Inst_GetGradientsH = 0x7, + TVX_Inst_GetGradientsV = 0x8, + TVX_Inst_SetTextureOffsets = 0x9, + TVX_Inst_KeepGradients = 0xa, + TVX_Inst_SetGradientsH = 0xb, + TVX_Inst_SetGradientsV = 0xc, + TVX_Inst_Pass = 0xd, + TVX_Inst_GetBufferResInfo = 0xe, + TVX_Inst_RESERVED_15 = 0xf, + TVX_Inst_Sample = 0x10, + TVX_Inst_Sample_L = 0x11, + TVX_Inst_Sample_LB = 0x12, + TVX_Inst_Sample_LZ = 0x13, + TVX_Inst_Sample_G = 0x14, + TVX_Inst_Gather4 = 0x15, + TVX_Inst_Sample_G_LB = 0x16, + TVX_Inst_Gather4_O = 0x17, + TVX_Inst_Sample_C = 0x18, + TVX_Inst_Sample_C_L = 0x19, + TVX_Inst_Sample_C_LB = 0x1a, + TVX_Inst_Sample_C_LZ = 0x1b, + TVX_Inst_Sample_C_G = 0x1c, + TVX_Inst_Gather4_C = 0x1d, + TVX_Inst_Sample_C_G_LB = 0x1e, + TVX_Inst_Gather4_C_O = 0x1f, +} TVX_INST; +typedef enum TVX_NUM_FORMAT_ALL { + TVX_NumFormatAll_Norm = 0x0, + TVX_NumFormatAll_Int = 0x1, + TVX_NumFormatAll_Scaled = 0x2, + TVX_NumFormatAll_RESERVED_3 = 0x3, +} TVX_NUM_FORMAT_ALL; +typedef enum TVX_SRC_SEL { + TVX_SrcSel_X = 0x0, + TVX_SrcSel_Y = 0x1, + TVX_SrcSel_Z = 0x2, + TVX_SrcSel_W = 0x3, + TVX_SrcSel_0f = 0x4, + TVX_SrcSel_1f = 0x5, +} TVX_SRC_SEL; +typedef enum TVX_SRF_MODE_ALL { + TVX_SRFModeAll_ZCMO = 0x0, + TVX_SRFModeAll_NZ = 0x1, +} TVX_SRF_MODE_ALL; +typedef enum TVX_TYPE { + TVX_Type_InvalidTextureResource = 0x0, + TVX_Type_InvalidVertexBuffer = 0x1, + TVX_Type_ValidTextureResource = 0x2, + TVX_Type_ValidVertexBuffer = 0x3, +} TVX_TYPE; +typedef enum TC_OP_MASKS { + TC_OP_MASK_FLUSH_DENROM = 0x8, + TC_OP_MASK_64 = 0x20, + TC_OP_MASK_NO_RTN = 0x40, +} TC_OP_MASKS; +typedef enum TC_OP { + TC_OP_READ = 0x0, + TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x1, + TC_OP_ATOMIC_FMIN_RTN_32 = 0x2, + TC_OP_ATOMIC_FMAX_RTN_32 = 0x3, + TC_OP_RESERVED_FOP_RTN_32_0 = 0x4, + TC_OP_RESERVED_FOP_RTN_32_1 = 0x5, + TC_OP_RESERVED_FOP_RTN_32_2 = 0x6, + TC_OP_ATOMIC_SWAP_RTN_32 = 0x7, + TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x8, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x9, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0xa, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0xb, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_0 = 0xc, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0xd, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0xe, + TC_OP_ATOMIC_ADD_RTN_32 = 0xf, + TC_OP_ATOMIC_SUB_RTN_32 = 0x10, + TC_OP_ATOMIC_SMIN_RTN_32 = 0x11, + TC_OP_ATOMIC_UMIN_RTN_32 = 0x12, + TC_OP_ATOMIC_SMAX_RTN_32 = 0x13, + TC_OP_ATOMIC_UMAX_RTN_32 = 0x14, + TC_OP_ATOMIC_AND_RTN_32 = 0x15, + TC_OP_ATOMIC_OR_RTN_32 = 0x16, + TC_OP_ATOMIC_XOR_RTN_32 = 0x17, + TC_OP_ATOMIC_INC_RTN_32 = 0x18, + TC_OP_ATOMIC_DEC_RTN_32 = 0x19, + TC_OP_WBINVL1_VOL = 0x1a, + TC_OP_WBINVL1_SD = 0x1b, + TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x1c, + TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x1d, + TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x1e, + TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x1f, + TC_OP_WRITE = 0x20, + TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x21, + TC_OP_ATOMIC_FMIN_RTN_64 = 0x22, + TC_OP_ATOMIC_FMAX_RTN_64 = 0x23, + TC_OP_RESERVED_FOP_RTN_64_0 = 0x24, + TC_OP_RESERVED_FOP_RTN_64_1 = 0x25, + TC_OP_RESERVED_FOP_RTN_64_2 = 0x26, + TC_OP_ATOMIC_SWAP_RTN_64 = 0x27, + TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x28, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x29, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x2a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x2b, + TC_OP_WBINVL2_SD = 0x2c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x2d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x2e, + TC_OP_ATOMIC_ADD_RTN_64 = 0x2f, + TC_OP_ATOMIC_SUB_RTN_64 = 0x30, + TC_OP_ATOMIC_SMIN_RTN_64 = 0x31, + TC_OP_ATOMIC_UMIN_RTN_64 = 0x32, + TC_OP_ATOMIC_SMAX_RTN_64 = 0x33, + TC_OP_ATOMIC_UMAX_RTN_64 = 0x34, + TC_OP_ATOMIC_AND_RTN_64 = 0x35, + TC_OP_ATOMIC_OR_RTN_64 = 0x36, + TC_OP_ATOMIC_XOR_RTN_64 = 0x37, + TC_OP_ATOMIC_INC_RTN_64 = 0x38, + TC_OP_ATOMIC_DEC_RTN_64 = 0x39, + TC_OP_WBL2_NC = 0x3a, + TC_OP_RESERVED_NON_FLOAT_RTN_64_0 = 0x3b, + TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x3c, + TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x3d, + TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x3e, + TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x3f, + TC_OP_WBINVL1 = 0x40, + TC_OP_ATOMIC_FCMPSWAP_32 = 0x41, + TC_OP_ATOMIC_FMIN_32 = 0x42, + TC_OP_ATOMIC_FMAX_32 = 0x43, + TC_OP_RESERVED_FOP_32_0 = 0x44, + TC_OP_RESERVED_FOP_32_1 = 0x45, + TC_OP_RESERVED_FOP_32_2 = 0x46, + TC_OP_ATOMIC_SWAP_32 = 0x47, + TC_OP_ATOMIC_CMPSWAP_32 = 0x48, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x49, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x4a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x4b, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_0 = 0x4c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x4d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x4e, + TC_OP_ATOMIC_ADD_32 = 0x4f, + TC_OP_ATOMIC_SUB_32 = 0x50, + TC_OP_ATOMIC_SMIN_32 = 0x51, + TC_OP_ATOMIC_UMIN_32 = 0x52, + TC_OP_ATOMIC_SMAX_32 = 0x53, + TC_OP_ATOMIC_UMAX_32 = 0x54, + TC_OP_ATOMIC_AND_32 = 0x55, + TC_OP_ATOMIC_OR_32 = 0x56, + TC_OP_ATOMIC_XOR_32 = 0x57, + TC_OP_ATOMIC_INC_32 = 0x58, + TC_OP_ATOMIC_DEC_32 = 0x59, + TC_OP_INVL2_NC = 0x5a, + TC_OP_RESERVED_NON_FLOAT_32_0 = 0x5b, + TC_OP_RESERVED_NON_FLOAT_32_1 = 0x5c, + TC_OP_RESERVED_NON_FLOAT_32_2 = 0x5d, + TC_OP_RESERVED_NON_FLOAT_32_3 = 0x5e, + TC_OP_RESERVED_NON_FLOAT_32_4 = 0x5f, + TC_OP_WBINVL2 = 0x60, + TC_OP_ATOMIC_FCMPSWAP_64 = 0x61, + TC_OP_ATOMIC_FMIN_64 = 0x62, + TC_OP_ATOMIC_FMAX_64 = 0x63, + TC_OP_RESERVED_FOP_64_0 = 0x64, + TC_OP_RESERVED_FOP_64_1 = 0x65, + TC_OP_RESERVED_FOP_64_2 = 0x66, + TC_OP_ATOMIC_SWAP_64 = 0x67, + TC_OP_ATOMIC_CMPSWAP_64 = 0x68, + TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x69, + TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x6a, + TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x6b, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x6c, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x6d, + TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x6e, + TC_OP_ATOMIC_ADD_64 = 0x6f, + TC_OP_ATOMIC_SUB_64 = 0x70, + TC_OP_ATOMIC_SMIN_64 = 0x71, + TC_OP_ATOMIC_UMIN_64 = 0x72, + TC_OP_ATOMIC_SMAX_64 = 0x73, + TC_OP_ATOMIC_UMAX_64 = 0x74, + TC_OP_ATOMIC_AND_64 = 0x75, + TC_OP_ATOMIC_OR_64 = 0x76, + TC_OP_ATOMIC_XOR_64 = 0x77, + TC_OP_ATOMIC_INC_64 = 0x78, + TC_OP_ATOMIC_DEC_64 = 0x79, + TC_OP_WBINVL2_NC = 0x7a, + TC_OP_RESERVED_NON_FLOAT_64_0 = 0x7b, + TC_OP_RESERVED_NON_FLOAT_64_1 = 0x7c, + TC_OP_RESERVED_NON_FLOAT_64_2 = 0x7d, + TC_OP_RESERVED_NON_FLOAT_64_3 = 0x7e, + TC_OP_RESERVED_NON_FLOAT_64_4 = 0x7f, +} TC_OP; +typedef enum TC_CHUB_REQ_CREDITS_ENUM { + TC_CHUB_REQ_CREDITS = 0x10, +} TC_CHUB_REQ_CREDITS_ENUM; +typedef enum CHUB_TC_RET_CREDITS_ENUM { + CHUB_TC_RET_CREDITS = 0x20, +} CHUB_TC_RET_CREDITS_ENUM; +typedef enum TC_NACKS { + TC_NACK_NO_FAULT = 0x0, + TC_NACK_PAGE_FAULT = 0x1, + TC_NACK_PROTECTION_FAULT = 0x2, + TC_NACK_DATA_ERROR = 0x3, +} TC_NACKS; +typedef enum TCC_PERF_SEL { + TCC_PERF_SEL_NONE = 0x0, + TCC_PERF_SEL_CYCLE = 0x1, + TCC_PERF_SEL_BUSY = 0x2, + TCC_PERF_SEL_REQ = 0x3, + TCC_PERF_SEL_STREAMING_REQ = 0x4, + TCC_PERF_SEL_EXE_REQ = 0x5, + TCC_PERF_SEL_COMPRESSED_REQ = 0x6, + TCC_PERF_SEL_COMPRESSED_0_REQ = 0x7, + TCC_PERF_SEL_METADATA_REQ = 0x8, + TCC_PERF_SEL_NC_VIRTUAL_REQ = 0x9, + TCC_PERF_SEL_NC_PHYSICAL_REQ = 0xa, + TCC_PERF_SEL_UC_VIRTUAL_REQ = 0xb, + TCC_PERF_SEL_UC_PHYSICAL_REQ = 0xc, + TCC_PERF_SEL_CC_PHYSICAL_REQ = 0xd, + TCC_PERF_SEL_PROBE = 0xe, + TCC_PERF_SEL_READ = 0xf, + TCC_PERF_SEL_WRITE = 0x10, + TCC_PERF_SEL_ATOMIC = 0x11, + TCC_PERF_SEL_HIT = 0x12, + TCC_PERF_SEL_MISS = 0x13, + TCC_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x14, + TCC_PERF_SEL_FULLY_WRITTEN_HIT = 0x15, + TCC_PERF_SEL_WRITEBACK = 0x16, + TCC_PERF_SEL_LATENCY_FIFO_FULL = 0x17, + TCC_PERF_SEL_SRC_FIFO_FULL = 0x18, + TCC_PERF_SEL_HOLE_FIFO_FULL = 0x19, + TCC_PERF_SEL_MC_WRREQ = 0x1a, + TCC_PERF_SEL_MC_WRREQ_UNCACHED = 0x1b, + TCC_PERF_SEL_MC_WRREQ_STALL = 0x1c, + TCC_PERF_SEL_MC_WRREQ_CREDIT_STALL = 0x1d, + TCC_PERF_SEL_MC_WRREQ_MC_HALT_STALL = 0x1e, + TCC_PERF_SEL_TOO_MANY_MC_WRREQS_STALL = 0x1f, + TCC_PERF_SEL_MC_WRREQ_LEVEL = 0x20, + TCC_PERF_SEL_MC_ATOMIC = 0x21, + TCC_PERF_SEL_MC_ATOMIC_LEVEL = 0x22, + TCC_PERF_SEL_MC_RDREQ = 0x23, + TCC_PERF_SEL_MC_RDREQ_UNCACHED = 0x24, + TCC_PERF_SEL_MC_RDREQ_MDC = 0x25, + TCC_PERF_SEL_MC_RDREQ_COMPRESSED = 0x26, + TCC_PERF_SEL_MC_RDREQ_CREDIT_STALL = 0x27, + TCC_PERF_SEL_MC_RDREQ_MC_HALT_STALL = 0x28, + TCC_PERF_SEL_MC_RDREQ_LEVEL = 0x29, + TCC_PERF_SEL_TAG_STALL = 0x2a, + TCC_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x2b, + TCC_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x2c, + TCC_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL= 0x2d, + TCC_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL= 0x2e, + TCC_PERF_SEL_TAG_PROBE_STALL = 0x2f, + TCC_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x30, + TCC_PERF_SEL_READ_RETURN_TIMEOUT = 0x31, + TCC_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x32, + TCC_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x33, + TCC_PERF_SEL_BUBBLE = 0x34, + TCC_PERF_SEL_RETURN_ACK = 0x35, + TCC_PERF_SEL_RETURN_DATA = 0x36, + TCC_PERF_SEL_RETURN_HOLE = 0x37, + TCC_PERF_SEL_RETURN_ACK_HOLE = 0x38, + TCC_PERF_SEL_IB_REQ = 0x39, + TCC_PERF_SEL_IB_STALL = 0x3a, + TCC_PERF_SEL_IB_TAG_STALL = 0x3b, + TCC_PERF_SEL_IB_MDC_STALL = 0x3c, + TCC_PERF_SEL_TCA_LEVEL = 0x3d, + TCC_PERF_SEL_HOLE_LEVEL = 0x3e, + TCC_PERF_SEL_MC_RDRET_NACK = 0x3f, + TCC_PERF_SEL_MC_WRRET_NACK = 0x40, + TCC_PERF_SEL_NORMAL_WRITEBACK = 0x41, + TCC_PERF_SEL_TC_OP_WBL2_NC_WRITEBACK = 0x42, + TCC_PERF_SEL_TC_OP_WBINVL2_WRITEBACK = 0x43, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_WRITEBACK = 0x44, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_WRITEBACK = 0x45, + TCC_PERF_SEL_ALL_TC_OP_WB_WRITEBACK = 0x46, + TCC_PERF_SEL_NORMAL_EVICT = 0x47, + TCC_PERF_SEL_TC_OP_WBL2_NC_EVICT = 0x48, + TCC_PERF_SEL_TC_OP_INVL2_NC_EVICT = 0x49, + TCC_PERF_SEL_TC_OP_WBINVL2_EVICT = 0x4a, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_EVICT = 0x4b, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_EVICT = 0x4c, + TCC_PERF_SEL_ALL_TC_OP_INV_EVICT = 0x4d, + TCC_PERF_SEL_PROBE_EVICT = 0x4e, + TCC_PERF_SEL_TC_OP_WBL2_NC_CYCLE = 0x4f, + TCC_PERF_SEL_TC_OP_INVL2_NC_CYCLE = 0x50, + TCC_PERF_SEL_TC_OP_WBINVL2_CYCLE = 0x51, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_CYCLE = 0x52, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_CYCLE = 0x53, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_CYCLE = 0x54, + TCC_PERF_SEL_TC_OP_WBL2_NC_START = 0x55, + TCC_PERF_SEL_TC_OP_INVL2_NC_START = 0x56, + TCC_PERF_SEL_TC_OP_WBINVL2_START = 0x57, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_START = 0x58, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_START = 0x59, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x5a, + TCC_PERF_SEL_TC_OP_WBL2_NC_FINISH = 0x5b, + TCC_PERF_SEL_TC_OP_INVL2_NC_FINISH = 0x5c, + TCC_PERF_SEL_TC_OP_WBINVL2_FINISH = 0x5d, + TCC_PERF_SEL_TC_OP_WBINVL2_NC_FINISH = 0x5e, + TCC_PERF_SEL_TC_OP_WBINVL2_SD_FINISH = 0x5f, + TCC_PERF_SEL_ALL_TC_OP_WB_OR_INV_FINISH = 0x60, + TCC_PERF_SEL_MDC_REQ = 0x61, + TCC_PERF_SEL_MDC_LEVEL = 0x62, + TCC_PERF_SEL_MDC_TAG_HIT = 0x63, + TCC_PERF_SEL_MDC_SECTOR_HIT = 0x64, + TCC_PERF_SEL_MDC_SECTOR_MISS = 0x65, + TCC_PERF_SEL_MDC_TAG_STALL = 0x66, + TCC_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL= 0x67, + TCC_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL= 0x68, + TCC_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL= 0x69, + TCC_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x6a, + TCC_PERF_SEL_PROBE_FILTER_DISABLED = 0x6b, + TCC_PERF_SEL_CLIENT0_REQ = 0x80, + TCC_PERF_SEL_CLIENT1_REQ = 0x81, + TCC_PERF_SEL_CLIENT2_REQ = 0x82, + TCC_PERF_SEL_CLIENT3_REQ = 0x83, + TCC_PERF_SEL_CLIENT4_REQ = 0x84, + TCC_PERF_SEL_CLIENT5_REQ = 0x85, + TCC_PERF_SEL_CLIENT6_REQ = 0x86, + TCC_PERF_SEL_CLIENT7_REQ = 0x87, + TCC_PERF_SEL_CLIENT8_REQ = 0x88, + TCC_PERF_SEL_CLIENT9_REQ = 0x89, + TCC_PERF_SEL_CLIENT10_REQ = 0x8a, + TCC_PERF_SEL_CLIENT11_REQ = 0x8b, + TCC_PERF_SEL_CLIENT12_REQ = 0x8c, + TCC_PERF_SEL_CLIENT13_REQ = 0x8d, + TCC_PERF_SEL_CLIENT14_REQ = 0x8e, + TCC_PERF_SEL_CLIENT15_REQ = 0x8f, + TCC_PERF_SEL_CLIENT16_REQ = 0x90, + TCC_PERF_SEL_CLIENT17_REQ = 0x91, + TCC_PERF_SEL_CLIENT18_REQ = 0x92, + TCC_PERF_SEL_CLIENT19_REQ = 0x93, + TCC_PERF_SEL_CLIENT20_REQ = 0x94, + TCC_PERF_SEL_CLIENT21_REQ = 0x95, + TCC_PERF_SEL_CLIENT22_REQ = 0x96, + TCC_PERF_SEL_CLIENT23_REQ = 0x97, + TCC_PERF_SEL_CLIENT24_REQ = 0x98, + TCC_PERF_SEL_CLIENT25_REQ = 0x99, + TCC_PERF_SEL_CLIENT26_REQ = 0x9a, + TCC_PERF_SEL_CLIENT27_REQ = 0x9b, + TCC_PERF_SEL_CLIENT28_REQ = 0x9c, + TCC_PERF_SEL_CLIENT29_REQ = 0x9d, + TCC_PERF_SEL_CLIENT30_REQ = 0x9e, + TCC_PERF_SEL_CLIENT31_REQ = 0x9f, + TCC_PERF_SEL_CLIENT32_REQ = 0xa0, + TCC_PERF_SEL_CLIENT33_REQ = 0xa1, + TCC_PERF_SEL_CLIENT34_REQ = 0xa2, + TCC_PERF_SEL_CLIENT35_REQ = 0xa3, + TCC_PERF_SEL_CLIENT36_REQ = 0xa4, + TCC_PERF_SEL_CLIENT37_REQ = 0xa5, + TCC_PERF_SEL_CLIENT38_REQ = 0xa6, + TCC_PERF_SEL_CLIENT39_REQ = 0xa7, + TCC_PERF_SEL_CLIENT40_REQ = 0xa8, + TCC_PERF_SEL_CLIENT41_REQ = 0xa9, + TCC_PERF_SEL_CLIENT42_REQ = 0xaa, + TCC_PERF_SEL_CLIENT43_REQ = 0xab, + TCC_PERF_SEL_CLIENT44_REQ = 0xac, + TCC_PERF_SEL_CLIENT45_REQ = 0xad, + TCC_PERF_SEL_CLIENT46_REQ = 0xae, + TCC_PERF_SEL_CLIENT47_REQ = 0xaf, + TCC_PERF_SEL_CLIENT48_REQ = 0xb0, + TCC_PERF_SEL_CLIENT49_REQ = 0xb1, + TCC_PERF_SEL_CLIENT50_REQ = 0xb2, + TCC_PERF_SEL_CLIENT51_REQ = 0xb3, + TCC_PERF_SEL_CLIENT52_REQ = 0xb4, + TCC_PERF_SEL_CLIENT53_REQ = 0xb5, + TCC_PERF_SEL_CLIENT54_REQ = 0xb6, + TCC_PERF_SEL_CLIENT55_REQ = 0xb7, + TCC_PERF_SEL_CLIENT56_REQ = 0xb8, + TCC_PERF_SEL_CLIENT57_REQ = 0xb9, + TCC_PERF_SEL_CLIENT58_REQ = 0xba, + TCC_PERF_SEL_CLIENT59_REQ = 0xbb, + TCC_PERF_SEL_CLIENT60_REQ = 0xbc, + TCC_PERF_SEL_CLIENT61_REQ = 0xbd, + TCC_PERF_SEL_CLIENT62_REQ = 0xbe, + TCC_PERF_SEL_CLIENT63_REQ = 0xbf, + TCC_PERF_SEL_CLIENT64_REQ = 0xc0, + TCC_PERF_SEL_CLIENT65_REQ = 0xc1, + TCC_PERF_SEL_CLIENT66_REQ = 0xc2, + TCC_PERF_SEL_CLIENT67_REQ = 0xc3, + TCC_PERF_SEL_CLIENT68_REQ = 0xc4, + TCC_PERF_SEL_CLIENT69_REQ = 0xc5, + TCC_PERF_SEL_CLIENT70_REQ = 0xc6, + TCC_PERF_SEL_CLIENT71_REQ = 0xc7, + TCC_PERF_SEL_CLIENT72_REQ = 0xc8, + TCC_PERF_SEL_CLIENT73_REQ = 0xc9, + TCC_PERF_SEL_CLIENT74_REQ = 0xca, + TCC_PERF_SEL_CLIENT75_REQ = 0xcb, + TCC_PERF_SEL_CLIENT76_REQ = 0xcc, + TCC_PERF_SEL_CLIENT77_REQ = 0xcd, + TCC_PERF_SEL_CLIENT78_REQ = 0xce, + TCC_PERF_SEL_CLIENT79_REQ = 0xcf, + TCC_PERF_SEL_CLIENT80_REQ = 0xd0, + TCC_PERF_SEL_CLIENT81_REQ = 0xd1, + TCC_PERF_SEL_CLIENT82_REQ = 0xd2, + TCC_PERF_SEL_CLIENT83_REQ = 0xd3, + TCC_PERF_SEL_CLIENT84_REQ = 0xd4, + TCC_PERF_SEL_CLIENT85_REQ = 0xd5, + TCC_PERF_SEL_CLIENT86_REQ = 0xd6, + TCC_PERF_SEL_CLIENT87_REQ = 0xd7, + TCC_PERF_SEL_CLIENT88_REQ = 0xd8, + TCC_PERF_SEL_CLIENT89_REQ = 0xd9, + TCC_PERF_SEL_CLIENT90_REQ = 0xda, + TCC_PERF_SEL_CLIENT91_REQ = 0xdb, + TCC_PERF_SEL_CLIENT92_REQ = 0xdc, + TCC_PERF_SEL_CLIENT93_REQ = 0xdd, + TCC_PERF_SEL_CLIENT94_REQ = 0xde, + TCC_PERF_SEL_CLIENT95_REQ = 0xdf, + TCC_PERF_SEL_CLIENT96_REQ = 0xe0, + TCC_PERF_SEL_CLIENT97_REQ = 0xe1, + TCC_PERF_SEL_CLIENT98_REQ = 0xe2, + TCC_PERF_SEL_CLIENT99_REQ = 0xe3, + TCC_PERF_SEL_CLIENT100_REQ = 0xe4, + TCC_PERF_SEL_CLIENT101_REQ = 0xe5, + TCC_PERF_SEL_CLIENT102_REQ = 0xe6, + TCC_PERF_SEL_CLIENT103_REQ = 0xe7, + TCC_PERF_SEL_CLIENT104_REQ = 0xe8, + TCC_PERF_SEL_CLIENT105_REQ = 0xe9, + TCC_PERF_SEL_CLIENT106_REQ = 0xea, + TCC_PERF_SEL_CLIENT107_REQ = 0xeb, + TCC_PERF_SEL_CLIENT108_REQ = 0xec, + TCC_PERF_SEL_CLIENT109_REQ = 0xed, + TCC_PERF_SEL_CLIENT110_REQ = 0xee, + TCC_PERF_SEL_CLIENT111_REQ = 0xef, + TCC_PERF_SEL_CLIENT112_REQ = 0xf0, + TCC_PERF_SEL_CLIENT113_REQ = 0xf1, + TCC_PERF_SEL_CLIENT114_REQ = 0xf2, + TCC_PERF_SEL_CLIENT115_REQ = 0xf3, + TCC_PERF_SEL_CLIENT116_REQ = 0xf4, + TCC_PERF_SEL_CLIENT117_REQ = 0xf5, + TCC_PERF_SEL_CLIENT118_REQ = 0xf6, + TCC_PERF_SEL_CLIENT119_REQ = 0xf7, + TCC_PERF_SEL_CLIENT120_REQ = 0xf8, + TCC_PERF_SEL_CLIENT121_REQ = 0xf9, + TCC_PERF_SEL_CLIENT122_REQ = 0xfa, + TCC_PERF_SEL_CLIENT123_REQ = 0xfb, + TCC_PERF_SEL_CLIENT124_REQ = 0xfc, + TCC_PERF_SEL_CLIENT125_REQ = 0xfd, + TCC_PERF_SEL_CLIENT126_REQ = 0xfe, + TCC_PERF_SEL_CLIENT127_REQ = 0xff, +} TCC_PERF_SEL; +typedef enum TCA_PERF_SEL { + TCA_PERF_SEL_NONE = 0x0, + TCA_PERF_SEL_CYCLE = 0x1, + TCA_PERF_SEL_BUSY = 0x2, + TCA_PERF_SEL_FORCED_HOLE_TCC0 = 0x3, + TCA_PERF_SEL_FORCED_HOLE_TCC1 = 0x4, + TCA_PERF_SEL_FORCED_HOLE_TCC2 = 0x5, + TCA_PERF_SEL_FORCED_HOLE_TCC3 = 0x6, + TCA_PERF_SEL_FORCED_HOLE_TCC4 = 0x7, + TCA_PERF_SEL_FORCED_HOLE_TCC5 = 0x8, + TCA_PERF_SEL_FORCED_HOLE_TCC6 = 0x9, + TCA_PERF_SEL_FORCED_HOLE_TCC7 = 0xa, + TCA_PERF_SEL_REQ_TCC0 = 0xb, + TCA_PERF_SEL_REQ_TCC1 = 0xc, + TCA_PERF_SEL_REQ_TCC2 = 0xd, + TCA_PERF_SEL_REQ_TCC3 = 0xe, + TCA_PERF_SEL_REQ_TCC4 = 0xf, + TCA_PERF_SEL_REQ_TCC5 = 0x10, + TCA_PERF_SEL_REQ_TCC6 = 0x11, + TCA_PERF_SEL_REQ_TCC7 = 0x12, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC0 = 0x13, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC1 = 0x14, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC2 = 0x15, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC3 = 0x16, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC4 = 0x17, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC5 = 0x18, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC6 = 0x19, + TCA_PERF_SEL_CROSSBAR_DOUBLE_ARB_TCC7 = 0x1a, + TCA_PERF_SEL_CROSSBAR_STALL_TCC0 = 0x1b, + TCA_PERF_SEL_CROSSBAR_STALL_TCC1 = 0x1c, + TCA_PERF_SEL_CROSSBAR_STALL_TCC2 = 0x1d, + TCA_PERF_SEL_CROSSBAR_STALL_TCC3 = 0x1e, + TCA_PERF_SEL_CROSSBAR_STALL_TCC4 = 0x1f, + TCA_PERF_SEL_CROSSBAR_STALL_TCC5 = 0x20, + TCA_PERF_SEL_CROSSBAR_STALL_TCC6 = 0x21, + TCA_PERF_SEL_CROSSBAR_STALL_TCC7 = 0x22, +} TCA_PERF_SEL; +typedef enum TA_TC_ADDR_MODES { + TA_TC_ADDR_MODE_DEFAULT = 0x0, + TA_TC_ADDR_MODE_COMP0 = 0x1, + TA_TC_ADDR_MODE_COMP1 = 0x2, + TA_TC_ADDR_MODE_COMP2 = 0x3, + TA_TC_ADDR_MODE_COMP3 = 0x4, + TA_TC_ADDR_MODE_UNALIGNED = 0x5, + TA_TC_ADDR_MODE_BORDER_COLOR = 0x6, +} TA_TC_ADDR_MODES; +typedef enum TA_PERFCOUNT_SEL { + TA_PERF_SEL_NULL = 0x0, + TA_PERF_SEL_sh_fifo_busy = 0x1, + TA_PERF_SEL_sh_fifo_cmd_busy = 0x2, + TA_PERF_SEL_sh_fifo_addr_busy = 0x3, + TA_PERF_SEL_sh_fifo_data_busy = 0x4, + TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x5, + TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x6, + TA_PERF_SEL_gradient_busy = 0x7, + TA_PERF_SEL_gradient_fifo_busy = 0x8, + TA_PERF_SEL_lod_busy = 0x9, + TA_PERF_SEL_lod_fifo_busy = 0xa, + TA_PERF_SEL_addresser_busy = 0xb, + TA_PERF_SEL_addresser_fifo_busy = 0xc, + TA_PERF_SEL_aligner_busy = 0xd, + TA_PERF_SEL_write_path_busy = 0xe, + TA_PERF_SEL_ta_busy = 0xf, + TA_PERF_SEL_sq_ta_cmd_cycles = 0x10, + TA_PERF_SEL_sp_ta_addr_cycles = 0x11, + TA_PERF_SEL_sp_ta_data_cycles = 0x12, + TA_PERF_SEL_ta_fa_data_state_cycles = 0x13, + TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x14, + TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x15, + TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles= 0x16, + TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles= 0x17, + TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles= 0x18, + TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles= 0x19, + TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles= 0x1a, + TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles= 0x1b, + TA_PERF_SEL_RESERVED_28 = 0x1c, + TA_PERF_SEL_RESERVED_29 = 0x1d, + TA_PERF_SEL_sh_fifo_addr_cycles = 0x1e, + TA_PERF_SEL_sh_fifo_data_cycles = 0x1f, + TA_PERF_SEL_total_wavefronts = 0x20, + TA_PERF_SEL_gradient_cycles = 0x21, + TA_PERF_SEL_walker_cycles = 0x22, + TA_PERF_SEL_aligner_cycles = 0x23, + TA_PERF_SEL_image_wavefronts = 0x24, + TA_PERF_SEL_image_read_wavefronts = 0x25, + TA_PERF_SEL_image_write_wavefronts = 0x26, + TA_PERF_SEL_image_atomic_wavefronts = 0x27, + TA_PERF_SEL_image_total_cycles = 0x28, + TA_PERF_SEL_RESERVED_41 = 0x29, + TA_PERF_SEL_RESERVED_42 = 0x2a, + TA_PERF_SEL_RESERVED_43 = 0x2b, + TA_PERF_SEL_buffer_wavefronts = 0x2c, + TA_PERF_SEL_buffer_read_wavefronts = 0x2d, + TA_PERF_SEL_buffer_write_wavefronts = 0x2e, + TA_PERF_SEL_buffer_atomic_wavefronts = 0x2f, + TA_PERF_SEL_buffer_coalescable_wavefronts = 0x30, + TA_PERF_SEL_buffer_total_cycles = 0x31, + TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles= 0x32, + TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles= 0x33, + TA_PERF_SEL_buffer_coalesced_read_cycles = 0x34, + TA_PERF_SEL_buffer_coalesced_write_cycles = 0x35, + TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x36, + TA_PERF_SEL_addr_stalled_by_td_cycles = 0x37, + TA_PERF_SEL_data_stalled_by_tc_cycles = 0x38, + TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles= 0x39, + TA_PERF_SEL_addresser_stalled_cycles = 0x3a, + TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles= 0x3b, + TA_PERF_SEL_aniso_stalled_cycles = 0x3c, + TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x3d, + TA_PERF_SEL_deriv_stalled_cycles = 0x3e, + TA_PERF_SEL_aniso_gt1_cycle_quads = 0x3f, + TA_PERF_SEL_color_1_cycle_pixels = 0x40, + TA_PERF_SEL_color_2_cycle_pixels = 0x41, + TA_PERF_SEL_color_3_cycle_pixels = 0x42, + TA_PERF_SEL_color_4_cycle_pixels = 0x43, + TA_PERF_SEL_mip_1_cycle_pixels = 0x44, + TA_PERF_SEL_mip_2_cycle_pixels = 0x45, + TA_PERF_SEL_vol_1_cycle_pixels = 0x46, + TA_PERF_SEL_vol_2_cycle_pixels = 0x47, + TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x48, + TA_PERF_SEL_mipmap_lod_0_samples = 0x49, + TA_PERF_SEL_mipmap_lod_1_samples = 0x4a, + TA_PERF_SEL_mipmap_lod_2_samples = 0x4b, + TA_PERF_SEL_mipmap_lod_3_samples = 0x4c, + TA_PERF_SEL_mipmap_lod_4_samples = 0x4d, + TA_PERF_SEL_mipmap_lod_5_samples = 0x4e, + TA_PERF_SEL_mipmap_lod_6_samples = 0x4f, + TA_PERF_SEL_mipmap_lod_7_samples = 0x50, + TA_PERF_SEL_mipmap_lod_8_samples = 0x51, + TA_PERF_SEL_mipmap_lod_9_samples = 0x52, + TA_PERF_SEL_mipmap_lod_10_samples = 0x53, + TA_PERF_SEL_mipmap_lod_11_samples = 0x54, + TA_PERF_SEL_mipmap_lod_12_samples = 0x55, + TA_PERF_SEL_mipmap_lod_13_samples = 0x56, + TA_PERF_SEL_mipmap_lod_14_samples = 0x57, + TA_PERF_SEL_mipmap_invalid_samples = 0x58, + TA_PERF_SEL_aniso_1_cycle_quads = 0x59, + TA_PERF_SEL_aniso_2_cycle_quads = 0x5a, + TA_PERF_SEL_aniso_4_cycle_quads = 0x5b, + TA_PERF_SEL_aniso_6_cycle_quads = 0x5c, + TA_PERF_SEL_aniso_8_cycle_quads = 0x5d, + TA_PERF_SEL_aniso_10_cycle_quads = 0x5e, + TA_PERF_SEL_aniso_12_cycle_quads = 0x5f, + TA_PERF_SEL_aniso_14_cycle_quads = 0x60, + TA_PERF_SEL_aniso_16_cycle_quads = 0x61, + TA_PERF_SEL_write_path_input_cycles = 0x62, + TA_PERF_SEL_write_path_output_cycles = 0x63, + TA_PERF_SEL_flat_wavefronts = 0x64, + TA_PERF_SEL_flat_read_wavefronts = 0x65, + TA_PERF_SEL_flat_write_wavefronts = 0x66, + TA_PERF_SEL_flat_atomic_wavefronts = 0x67, + TA_PERF_SEL_flat_coalesceable_wavefronts = 0x68, + TA_PERF_SEL_reg_sclk_vld = 0x69, + TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6a, + TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x6b, + TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x6c, + TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x6d, + TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x6e, + TA_PERF_SEL_xnack_on_phase0 = 0x6f, + TA_PERF_SEL_xnack_on_phase1 = 0x70, + TA_PERF_SEL_xnack_on_phase2 = 0x71, + TA_PERF_SEL_xnack_on_phase3 = 0x72, + TA_PERF_SEL_first_xnack_on_phase0 = 0x73, + TA_PERF_SEL_first_xnack_on_phase1 = 0x74, + TA_PERF_SEL_first_xnack_on_phase2 = 0x75, + TA_PERF_SEL_first_xnack_on_phase3 = 0x76, +} TA_PERFCOUNT_SEL; +typedef enum TD_PERFCOUNT_SEL { + TD_PERF_SEL_none = 0x0, + TD_PERF_SEL_td_busy = 0x1, + TD_PERF_SEL_input_busy = 0x2, + TD_PERF_SEL_output_busy = 0x3, + TD_PERF_SEL_lerp_busy = 0x4, + TD_PERF_SEL_reg_sclk_vld = 0x5, + TD_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x6, + TD_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x7, + TD_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x8, + TD_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x9, + TD_PERF_SEL_tc_td_fifo_full = 0xa, + TD_PERF_SEL_constant_state_full = 0xb, + TD_PERF_SEL_sample_state_full = 0xc, + TD_PERF_SEL_output_fifo_full = 0xd, + TD_PERF_SEL_RESERVED_14 = 0xe, + TD_PERF_SEL_tc_stall = 0xf, + TD_PERF_SEL_pc_stall = 0x10, + TD_PERF_SEL_gds_stall = 0x11, + TD_PERF_SEL_RESERVED_18 = 0x12, + TD_PERF_SEL_RESERVED_19 = 0x13, + TD_PERF_SEL_gather4_wavefront = 0x14, + TD_PERF_SEL_sample_c_wavefront = 0x15, + TD_PERF_SEL_load_wavefront = 0x16, + TD_PERF_SEL_atomic_wavefront = 0x17, + TD_PERF_SEL_store_wavefront = 0x18, + TD_PERF_SEL_ldfptr_wavefront = 0x19, + TD_PERF_SEL_RESERVED_26 = 0x1a, + TD_PERF_SEL_RESERVED_27 = 0x1b, + TD_PERF_SEL_d16_en_wavefront = 0x1c, + TD_PERF_SEL_bicubic_filter_wavefront = 0x1d, + TD_PERF_SEL_bypass_filter_wavefront = 0x1e, + TD_PERF_SEL_min_max_filter_wavefront = 0x1f, + TD_PERF_SEL_coalescable_wavefront = 0x20, + TD_PERF_SEL_coalesced_phase = 0x21, + TD_PERF_SEL_four_phase_wavefront = 0x22, + TD_PERF_SEL_eight_phase_wavefront = 0x23, + TD_PERF_SEL_sixteen_phase_wavefront = 0x24, + TD_PERF_SEL_four_phase_forward_wavefront = 0x25, + TD_PERF_SEL_write_ack_wavefront = 0x26, + TD_PERF_SEL_RESERVED_39 = 0x27, + TD_PERF_SEL_user_defined_border = 0x28, + TD_PERF_SEL_white_border = 0x29, + TD_PERF_SEL_opaque_black_border = 0x2a, + TD_PERF_SEL_RESERVED_43 = 0x2b, + TD_PERF_SEL_RESERVED_44 = 0x2c, + TD_PERF_SEL_nack = 0x2d, + TD_PERF_SEL_td_sp_traffic = 0x2e, + TD_PERF_SEL_consume_gds_traffic = 0x2f, + TD_PERF_SEL_addresscmd_poison = 0x30, + TD_PERF_SEL_data_poison = 0x31, + TD_PERF_SEL_start_cycle_0 = 0x32, + TD_PERF_SEL_start_cycle_1 = 0x33, + TD_PERF_SEL_start_cycle_2 = 0x34, + TD_PERF_SEL_start_cycle_3 = 0x35, + TD_PERF_SEL_null_cycle_output = 0x36, + TD_PERF_SEL_d16_data_packed = 0x37, +} TD_PERFCOUNT_SEL; +typedef enum TCP_PERFCOUNT_SELECT { + TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x0, + TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x1, + TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x2, + TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x3, + TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x4, + TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x5, + TCP_PERF_SEL_LOD_STALL_CYCLES = 0x6, + TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x7, + TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x8, + TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x9, + TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0xa, + TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0xb, + TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0xc, + TCP_PERF_SEL_TCR_RDRET_STALL = 0xd, + TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0xe, + TCP_PERF_SEL_HOLE_READ_STALL = 0xf, + TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x10, + TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x11, + TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x12, + TCP_PERF_SEL_TCP_LATENCY = 0x13, + TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x14, + TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x15, + TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x16, + TCP_PERF_SEL_TCC_READ_REQ = 0x17, + TCP_PERF_SEL_TCC_WRITE_REQ = 0x18, + TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x19, + TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x1a, + TCP_PERF_SEL_TOTAL_LOCAL_READ = 0x1b, + TCP_PERF_SEL_TOTAL_GLOBAL_READ = 0x1c, + TCP_PERF_SEL_TOTAL_LOCAL_WRITE = 0x1d, + TCP_PERF_SEL_TOTAL_GLOBAL_WRITE = 0x1e, + TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x1f, + TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x20, + TCP_PERF_SEL_TOTAL_WBINVL1 = 0x21, + TCP_PERF_SEL_IMG_READ_FMT_1 = 0x22, + TCP_PERF_SEL_IMG_READ_FMT_8 = 0x23, + TCP_PERF_SEL_IMG_READ_FMT_16 = 0x24, + TCP_PERF_SEL_IMG_READ_FMT_32 = 0x25, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_8 = 0x26, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_16 = 0x27, + TCP_PERF_SEL_IMG_READ_FMT_32_AS_128 = 0x28, + TCP_PERF_SEL_IMG_READ_FMT_64_2_CYCLE = 0x29, + TCP_PERF_SEL_IMG_READ_FMT_64_1_CYCLE = 0x2a, + TCP_PERF_SEL_IMG_READ_FMT_96 = 0x2b, + TCP_PERF_SEL_IMG_READ_FMT_128_4_CYCLE = 0x2c, + TCP_PERF_SEL_IMG_READ_FMT_128_1_CYCLE = 0x2d, + TCP_PERF_SEL_IMG_READ_FMT_BC1 = 0x2e, + TCP_PERF_SEL_IMG_READ_FMT_BC2 = 0x2f, + TCP_PERF_SEL_IMG_READ_FMT_BC3 = 0x30, + TCP_PERF_SEL_IMG_READ_FMT_BC4 = 0x31, + TCP_PERF_SEL_IMG_READ_FMT_BC5 = 0x32, + TCP_PERF_SEL_IMG_READ_FMT_BC6 = 0x33, + TCP_PERF_SEL_IMG_READ_FMT_BC7 = 0x34, + TCP_PERF_SEL_IMG_READ_FMT_I8 = 0x35, + TCP_PERF_SEL_IMG_READ_FMT_I16 = 0x36, + TCP_PERF_SEL_IMG_READ_FMT_I32 = 0x37, + TCP_PERF_SEL_IMG_READ_FMT_I32_AS_8 = 0x38, + TCP_PERF_SEL_IMG_READ_FMT_I32_AS_16 = 0x39, + TCP_PERF_SEL_IMG_READ_FMT_D8 = 0x3a, + TCP_PERF_SEL_IMG_READ_FMT_D16 = 0x3b, + TCP_PERF_SEL_IMG_READ_FMT_D32 = 0x3c, + TCP_PERF_SEL_IMG_WRITE_FMT_8 = 0x3d, + TCP_PERF_SEL_IMG_WRITE_FMT_16 = 0x3e, + TCP_PERF_SEL_IMG_WRITE_FMT_32 = 0x3f, + TCP_PERF_SEL_IMG_WRITE_FMT_64 = 0x40, + TCP_PERF_SEL_IMG_WRITE_FMT_128 = 0x41, + TCP_PERF_SEL_IMG_WRITE_FMT_D8 = 0x42, + TCP_PERF_SEL_IMG_WRITE_FMT_D16 = 0x43, + TCP_PERF_SEL_IMG_WRITE_FMT_D32 = 0x44, + TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_32 = 0x45, + TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_32 = 0x46, + TCP_PERF_SEL_IMG_ATOMIC_WITH_RET_FMT_64 = 0x47, + TCP_PERF_SEL_IMG_ATOMIC_WITHOUT_RET_FMT_64 = 0x48, + TCP_PERF_SEL_BUF_READ_FMT_8 = 0x49, + TCP_PERF_SEL_BUF_READ_FMT_16 = 0x4a, + TCP_PERF_SEL_BUF_READ_FMT_32 = 0x4b, + TCP_PERF_SEL_BUF_WRITE_FMT_8 = 0x4c, + TCP_PERF_SEL_BUF_WRITE_FMT_16 = 0x4d, + TCP_PERF_SEL_BUF_WRITE_FMT_32 = 0x4e, + TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_32 = 0x4f, + TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_32 = 0x50, + TCP_PERF_SEL_BUF_ATOMIC_WITH_RET_FMT_64 = 0x51, + TCP_PERF_SEL_BUF_ATOMIC_WITHOUT_RET_FMT_64 = 0x52, + TCP_PERF_SEL_ARR_LINEAR_GENERAL = 0x53, + TCP_PERF_SEL_ARR_LINEAR_ALIGNED = 0x54, + TCP_PERF_SEL_ARR_1D_THIN1 = 0x55, + TCP_PERF_SEL_ARR_1D_THICK = 0x56, + TCP_PERF_SEL_ARR_2D_THIN1 = 0x57, + TCP_PERF_SEL_ARR_2D_THICK = 0x58, + TCP_PERF_SEL_ARR_2D_XTHICK = 0x59, + TCP_PERF_SEL_ARR_3D_THIN1 = 0x5a, + TCP_PERF_SEL_ARR_3D_THICK = 0x5b, + TCP_PERF_SEL_ARR_3D_XTHICK = 0x5c, + TCP_PERF_SEL_DIM_1D = 0x5d, + TCP_PERF_SEL_DIM_2D = 0x5e, + TCP_PERF_SEL_DIM_3D = 0x5f, + TCP_PERF_SEL_DIM_1D_ARRAY = 0x60, + TCP_PERF_SEL_DIM_2D_ARRAY = 0x61, + TCP_PERF_SEL_DIM_2D_MSAA = 0x62, + TCP_PERF_SEL_DIM_2D_ARRAY_MSAA = 0x63, + TCP_PERF_SEL_DIM_CUBE_ARRAY = 0x64, + TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x65, + TCP_PERF_SEL_TA_TCP_STATE_READ = 0x66, + TCP_PERF_SEL_TAGRAM0_REQ = 0x67, + TCP_PERF_SEL_TAGRAM1_REQ = 0x68, + TCP_PERF_SEL_TAGRAM2_REQ = 0x69, + TCP_PERF_SEL_TAGRAM3_REQ = 0x6a, + TCP_PERF_SEL_GATE_EN1 = 0x6b, + TCP_PERF_SEL_GATE_EN2 = 0x6c, + TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x6d, + TCP_PERF_SEL_TCC_REQ = 0x6e, + TCP_PERF_SEL_TCC_NON_READ_REQ = 0x6f, + TCP_PERF_SEL_TCC_BYPASS_READ_REQ = 0x70, + TCP_PERF_SEL_TCC_MISS_EVICT_READ_REQ = 0x71, + TCP_PERF_SEL_TCC_VOLATILE_READ_REQ = 0x72, + TCP_PERF_SEL_TCC_VOLATILE_BYPASS_READ_REQ = 0x73, + TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_READ_REQ = 0x74, + TCP_PERF_SEL_TCC_BYPASS_WRITE_REQ = 0x75, + TCP_PERF_SEL_TCC_MISS_EVICT_WRITE_REQ = 0x76, + TCP_PERF_SEL_TCC_VOLATILE_BYPASS_WRITE_REQ = 0x77, + TCP_PERF_SEL_TCC_VOLATILE_WRITE_REQ = 0x78, + TCP_PERF_SEL_TCC_VOLATILE_MISS_EVICT_WRITE_REQ = 0x79, + TCP_PERF_SEL_TCC_BYPASS_ATOMIC_REQ = 0x7a, + TCP_PERF_SEL_TCC_ATOMIC_REQ = 0x7b, + TCP_PERF_SEL_TCC_VOLATILE_ATOMIC_REQ = 0x7c, + TCP_PERF_SEL_TCC_DATA_BUS_BUSY = 0x7d, + TCP_PERF_SEL_TOTAL_ACCESSES = 0x7e, + TCP_PERF_SEL_TOTAL_READ = 0x7f, + TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x80, + TCP_PERF_SEL_TOTAL_HIT_EVICT_READ = 0x81, + TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x82, + TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x83, + TCP_PERF_SEL_TOTAL_NON_READ = 0x84, + TCP_PERF_SEL_TOTAL_WRITE = 0x85, + TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x86, + TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x87, + TCP_PERF_SEL_TOTAL_WBINVL1_VOL = 0x88, + TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x89, + TCP_PERF_SEL_DISPLAY_MICROTILING = 0x8a, + TCP_PERF_SEL_THIN_MICROTILING = 0x8b, + TCP_PERF_SEL_DEPTH_MICROTILING = 0x8c, + TCP_PERF_SEL_ARR_PRT_THIN1 = 0x8d, + TCP_PERF_SEL_ARR_PRT_2D_THIN1 = 0x8e, + TCP_PERF_SEL_ARR_PRT_3D_THIN1 = 0x8f, + TCP_PERF_SEL_ARR_PRT_THICK = 0x90, + TCP_PERF_SEL_ARR_PRT_2D_THICK = 0x91, + TCP_PERF_SEL_ARR_PRT_3D_THICK = 0x92, + TCP_PERF_SEL_CP_TCP_INVALIDATE_VOL = 0x93, + TCP_PERF_SEL_SQ_TCP_INVALIDATE_VOL = 0x94, + TCP_PERF_SEL_UNALIGNED = 0x95, + TCP_PERF_SEL_ROTATED_MICROTILING = 0x96, + TCP_PERF_SEL_THICK_MICROTILING = 0x97, + TCP_PERF_SEL_ATC = 0x98, + TCP_PERF_SEL_POWER_STALL = 0x99, + TCP_PERF_SEL_RESERVED_154 = 0x9a, + TCP_PERF_SEL_TCC_LRU_REQ = 0x9b, + TCP_PERF_SEL_TCC_STREAM_REQ = 0x9c, + TCP_PERF_SEL_TCC_NC_READ_REQ = 0x9d, + TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x9e, + TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x9f, + TCP_PERF_SEL_TCC_UC_READ_REQ = 0xa0, + TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0xa1, + TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0xa2, + TCP_PERF_SEL_TCC_CC_READ_REQ = 0xa3, + TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0xa4, + TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0xa5, + TCP_PERF_SEL_TCC_DCC_REQ = 0xa6, + TCP_PERF_SEL_TCC_PHYSICAL_REQ = 0xa7, + TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0xa8, + TCP_PERF_SEL_VOLATILE = 0xa9, + TCP_PERF_SEL_TC_TA_XNACK_STALL = 0xaa, + TCP_PERF_SEL_ATCL1_SERIALIZATION_STALL = 0xab, + TCP_PERF_SEL_SHOOTDOWN = 0xac, + TCP_PERF_SEL_GATCL1_TRANSLATION_MISS = 0xad, + TCP_PERF_SEL_GATCL1_PERMISSION_MISS = 0xae, + TCP_PERF_SEL_GATCL1_REQUEST = 0xaf, + TCP_PERF_SEL_GATCL1_STALL_INFLIGHT_MAX = 0xb0, + TCP_PERF_SEL_GATCL1_STALL_LRU_INFLIGHT = 0xb1, + TCP_PERF_SEL_GATCL1_LFIFO_FULL = 0xb2, + TCP_PERF_SEL_GATCL1_STALL_LFIFO_NOT_RES = 0xb3, + TCP_PERF_SEL_GATCL1_STALL_ATCL2_REQ_OUT_OF_CREDITS= 0xb4, + TCP_PERF_SEL_GATCL1_ATCL2_INFLIGHT = 0xb5, + TCP_PERF_SEL_GATCL1_STALL_MISSFIFO_FULL = 0xb6, + TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGB = 0xb7, + TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA = 0xb8, + TCP_PERF_SEL_IMG_READ_FMT_ETC2_RGBA1 = 0xb9, + TCP_PERF_SEL_IMG_READ_FMT_ETC2_R = 0xba, + TCP_PERF_SEL_IMG_READ_FMT_ETC2_RG = 0xbb, + TCP_PERF_SEL_IMG_READ_FMT_8_AS_32 = 0xbc, + TCP_PERF_SEL_IMG_READ_FMT_8_AS_64 = 0xbd, + TCP_PERF_SEL_IMG_READ_FMT_16_AS_64 = 0xbe, + TCP_PERF_SEL_IMG_READ_FMT_16_AS_128 = 0xbf, + TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_32 = 0xc0, + TCP_PERF_SEL_IMG_WRITE_FMT_8_AS_64 = 0xc1, + TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_64 = 0xc2, + TCP_PERF_SEL_IMG_WRITE_FMT_16_AS_128 = 0xc3, +} TCP_PERFCOUNT_SELECT; +typedef enum TCP_CACHE_POLICIES { + TCP_CACHE_POLICY_MISS_LRU = 0x0, + TCP_CACHE_POLICY_MISS_EVICT = 0x1, + TCP_CACHE_POLICY_HIT_LRU = 0x2, + TCP_CACHE_POLICY_HIT_EVICT = 0x3, +} TCP_CACHE_POLICIES; +typedef enum TCP_CACHE_STORE_POLICIES { + TCP_CACHE_STORE_POLICY_WT_LRU = 0x0, + TCP_CACHE_STORE_POLICY_WT_EVICT = 0x1, +} TCP_CACHE_STORE_POLICIES; +typedef enum TCP_WATCH_MODES { + TCP_WATCH_MODE_READ = 0x0, + TCP_WATCH_MODE_NONREAD = 0x1, + TCP_WATCH_MODE_ATOMIC = 0x2, + TCP_WATCH_MODE_ALL = 0x3, +} TCP_WATCH_MODES; +typedef enum TCP_DSM_DATA_SEL { + TCP_DSM_DISABLE = 0x0, + TCP_DSM_SEL0 = 0x1, + TCP_DSM_SEL1 = 0x2, + TCP_DSM_SEL_BOTH = 0x3, +} TCP_DSM_DATA_SEL; +typedef enum TCP_DSM_SINGLE_WRITE { + TCP_DSM_SINGLE_WRITE_EN = 0x1, +} TCP_DSM_SINGLE_WRITE; +typedef enum VGT_OUT_PRIM_TYPE { + VGT_OUT_POINT = 0x0, + VGT_OUT_LINE = 0x1, + VGT_OUT_TRI = 0x2, + VGT_OUT_RECT_V0 = 0x3, + VGT_OUT_RECT_V1 = 0x4, + VGT_OUT_RECT_V2 = 0x5, + VGT_OUT_RECT_V3 = 0x6, + VGT_OUT_RESERVED = 0x7, + VGT_TE_QUAD = 0x8, + VGT_TE_PRIM_INDEX_LINE = 0x9, + VGT_TE_PRIM_INDEX_TRI = 0xa, + VGT_TE_PRIM_INDEX_QUAD = 0xb, + VGT_OUT_LINE_ADJ = 0xc, + VGT_OUT_TRI_ADJ = 0xd, + VGT_OUT_PATCH = 0xe, +} VGT_OUT_PRIM_TYPE; +typedef enum VGT_DI_PRIM_TYPE { + DI_PT_NONE = 0x0, + DI_PT_POINTLIST = 0x1, + DI_PT_LINELIST = 0x2, + DI_PT_LINESTRIP = 0x3, + DI_PT_TRILIST = 0x4, + DI_PT_TRIFAN = 0x5, + DI_PT_TRISTRIP = 0x6, + DI_PT_UNUSED_0 = 0x7, + DI_PT_UNUSED_1 = 0x8, + DI_PT_PATCH = 0x9, + DI_PT_LINELIST_ADJ = 0xa, + DI_PT_LINESTRIP_ADJ = 0xb, + DI_PT_TRILIST_ADJ = 0xc, + DI_PT_TRISTRIP_ADJ = 0xd, + DI_PT_UNUSED_3 = 0xe, + DI_PT_UNUSED_4 = 0xf, + DI_PT_TRI_WITH_WFLAGS = 0x10, + DI_PT_RECTLIST = 0x11, + DI_PT_LINELOOP = 0x12, + DI_PT_QUADLIST = 0x13, + DI_PT_QUADSTRIP = 0x14, + DI_PT_POLYGON = 0x15, + DI_PT_2D_COPY_RECT_LIST_V0 = 0x16, + DI_PT_2D_COPY_RECT_LIST_V1 = 0x17, + DI_PT_2D_COPY_RECT_LIST_V2 = 0x18, + DI_PT_2D_COPY_RECT_LIST_V3 = 0x19, + DI_PT_2D_FILL_RECT_LIST = 0x1a, + DI_PT_2D_LINE_STRIP = 0x1b, + DI_PT_2D_TRI_STRIP = 0x1c, +} VGT_DI_PRIM_TYPE; +typedef enum VGT_DI_SOURCE_SELECT { + DI_SRC_SEL_DMA = 0x0, + DI_SRC_SEL_IMMEDIATE = 0x1, + DI_SRC_SEL_AUTO_INDEX = 0x2, + DI_SRC_SEL_RESERVED = 0x3, +} VGT_DI_SOURCE_SELECT; +typedef enum VGT_DI_MAJOR_MODE_SELECT { + DI_MAJOR_MODE_0 = 0x0, + DI_MAJOR_MODE_1 = 0x1, +} VGT_DI_MAJOR_MODE_SELECT; +typedef enum VGT_DI_INDEX_SIZE { + DI_INDEX_SIZE_16_BIT = 0x0, + DI_INDEX_SIZE_32_BIT = 0x1, + DI_INDEX_SIZE_8_BIT = 0x2, +} VGT_DI_INDEX_SIZE; +typedef enum VGT_EVENT_TYPE { + Reserved_0x00 = 0x0, + SAMPLE_STREAMOUTSTATS1 = 0x1, + SAMPLE_STREAMOUTSTATS2 = 0x2, + SAMPLE_STREAMOUTSTATS3 = 0x3, + CACHE_FLUSH_TS = 0x4, + CONTEXT_DONE = 0x5, + CACHE_FLUSH = 0x6, + CS_PARTIAL_FLUSH = 0x7, + VGT_STREAMOUT_SYNC = 0x8, + Reserved_0x09 = 0x9, + VGT_STREAMOUT_RESET = 0xa, + END_OF_PIPE_INCR_DE = 0xb, + END_OF_PIPE_IB_END = 0xc, + RST_PIX_CNT = 0xd, + Reserved_0x0E = 0xe, + VS_PARTIAL_FLUSH = 0xf, + PS_PARTIAL_FLUSH = 0x10, + FLUSH_HS_OUTPUT = 0x11, + FLUSH_LS_OUTPUT = 0x12, + Reserved_0x13 = 0x13, + CACHE_FLUSH_AND_INV_TS_EVENT = 0x14, + ZPASS_DONE = 0x15, + CACHE_FLUSH_AND_INV_EVENT = 0x16, + PERFCOUNTER_START = 0x17, + PERFCOUNTER_STOP = 0x18, + PIPELINESTAT_START = 0x19, + PIPELINESTAT_STOP = 0x1a, + PERFCOUNTER_SAMPLE = 0x1b, + FLUSH_ES_OUTPUT = 0x1c, + FLUSH_GS_OUTPUT = 0x1d, + SAMPLE_PIPELINESTAT = 0x1e, + SO_VGTSTREAMOUT_FLUSH = 0x1f, + SAMPLE_STREAMOUTSTATS = 0x20, + RESET_VTX_CNT = 0x21, + BLOCK_CONTEXT_DONE = 0x22, + CS_CONTEXT_DONE = 0x23, + VGT_FLUSH = 0x24, + TGID_ROLLOVER = 0x25, + SQ_NON_EVENT = 0x26, + SC_SEND_DB_VPZ = 0x27, + BOTTOM_OF_PIPE_TS = 0x28, + FLUSH_SX_TS = 0x29, + DB_CACHE_FLUSH_AND_INV = 0x2a, + FLUSH_AND_INV_DB_DATA_TS = 0x2b, + FLUSH_AND_INV_DB_META = 0x2c, + FLUSH_AND_INV_CB_DATA_TS = 0x2d, + FLUSH_AND_INV_CB_META = 0x2e, + CS_DONE = 0x2f, + PS_DONE = 0x30, + FLUSH_AND_INV_CB_PIXEL_DATA = 0x31, + SX_CB_RAT_ACK_REQUEST = 0x32, + THREAD_TRACE_START = 0x33, + THREAD_TRACE_STOP = 0x34, + THREAD_TRACE_MARKER = 0x35, + THREAD_TRACE_FLUSH = 0x36, + THREAD_TRACE_FINISH = 0x37, + PIXEL_PIPE_STAT_CONTROL = 0x38, + PIXEL_PIPE_STAT_DUMP = 0x39, + PIXEL_PIPE_STAT_RESET = 0x3a, + CONTEXT_SUSPEND = 0x3b, + OFFCHIP_HS_DEALLOC = 0x3c, +} VGT_EVENT_TYPE; +typedef enum VGT_DMA_SWAP_MODE { + VGT_DMA_SWAP_NONE = 0x0, + VGT_DMA_SWAP_16_BIT = 0x1, + VGT_DMA_SWAP_32_BIT = 0x2, + VGT_DMA_SWAP_WORD = 0x3, +} VGT_DMA_SWAP_MODE; +typedef enum VGT_INDEX_TYPE_MODE { + VGT_INDEX_16 = 0x0, + VGT_INDEX_32 = 0x1, + VGT_INDEX_8 = 0x2, +} VGT_INDEX_TYPE_MODE; +typedef enum VGT_DMA_BUF_TYPE { + VGT_DMA_BUF_MEM = 0x0, + VGT_DMA_BUF_RING = 0x1, + VGT_DMA_BUF_SETUP = 0x2, + VGT_DMA_PTR_UPDATE = 0x3, +} VGT_DMA_BUF_TYPE; +typedef enum VGT_OUTPATH_SELECT { + VGT_OUTPATH_VTX_REUSE = 0x0, + VGT_OUTPATH_TESS_EN = 0x1, + VGT_OUTPATH_PASSTHRU = 0x2, + VGT_OUTPATH_GS_BLOCK = 0x3, + VGT_OUTPATH_HS_BLOCK = 0x4, +} VGT_OUTPATH_SELECT; +typedef enum VGT_GRP_PRIM_TYPE { + VGT_GRP_3D_POINT = 0x0, + VGT_GRP_3D_LINE = 0x1, + VGT_GRP_3D_TRI = 0x2, + VGT_GRP_3D_RECT = 0x3, + VGT_GRP_3D_QUAD = 0x4, + VGT_GRP_2D_COPY_RECT_V0 = 0x5, + VGT_GRP_2D_COPY_RECT_V1 = 0x6, + VGT_GRP_2D_COPY_RECT_V2 = 0x7, + VGT_GRP_2D_COPY_RECT_V3 = 0x8, + VGT_GRP_2D_FILL_RECT = 0x9, + VGT_GRP_2D_LINE = 0xa, + VGT_GRP_2D_TRI = 0xb, + VGT_GRP_PRIM_INDEX_LINE = 0xc, + VGT_GRP_PRIM_INDEX_TRI = 0xd, + VGT_GRP_PRIM_INDEX_QUAD = 0xe, + VGT_GRP_3D_LINE_ADJ = 0xf, + VGT_GRP_3D_TRI_ADJ = 0x10, + VGT_GRP_3D_PATCH = 0x11, +} VGT_GRP_PRIM_TYPE; +typedef enum VGT_GRP_PRIM_ORDER { + VGT_GRP_LIST = 0x0, + VGT_GRP_STRIP = 0x1, + VGT_GRP_FAN = 0x2, + VGT_GRP_LOOP = 0x3, + VGT_GRP_POLYGON = 0x4, +} VGT_GRP_PRIM_ORDER; +typedef enum VGT_GROUP_CONV_SEL { + VGT_GRP_INDEX_16 = 0x0, + VGT_GRP_INDEX_32 = 0x1, + VGT_GRP_UINT_16 = 0x2, + VGT_GRP_UINT_32 = 0x3, + VGT_GRP_SINT_16 = 0x4, + VGT_GRP_SINT_32 = 0x5, + VGT_GRP_FLOAT_32 = 0x6, + VGT_GRP_AUTO_PRIM = 0x7, + VGT_GRP_FIX_1_23_TO_FLOAT = 0x8, +} VGT_GROUP_CONV_SEL; +typedef enum VGT_GS_MODE_TYPE { + GS_OFF = 0x0, + GS_SCENARIO_A = 0x1, + GS_SCENARIO_B = 0x2, + GS_SCENARIO_G = 0x3, + GS_SCENARIO_C = 0x4, + SPRITE_EN = 0x5, +} VGT_GS_MODE_TYPE; +typedef enum VGT_GS_CUT_MODE { + GS_CUT_1024 = 0x0, + GS_CUT_512 = 0x1, + GS_CUT_256 = 0x2, + GS_CUT_128 = 0x3, +} VGT_GS_CUT_MODE; +typedef enum VGT_GS_OUTPRIM_TYPE { + POINTLIST = 0x0, + LINESTRIP = 0x1, + TRISTRIP = 0x2, +} VGT_GS_OUTPRIM_TYPE; +typedef enum VGT_CACHE_INVALID_MODE { + VC_ONLY = 0x0, + TC_ONLY = 0x1, + VC_AND_TC = 0x2, +} VGT_CACHE_INVALID_MODE; +typedef enum VGT_TESS_TYPE { + TESS_ISOLINE = 0x0, + TESS_TRIANGLE = 0x1, + TESS_QUAD = 0x2, +} VGT_TESS_TYPE; +typedef enum VGT_TESS_PARTITION { + PART_INTEGER = 0x0, + PART_POW2 = 0x1, + PART_FRAC_ODD = 0x2, + PART_FRAC_EVEN = 0x3, +} VGT_TESS_PARTITION; +typedef enum VGT_TESS_TOPOLOGY { + OUTPUT_POINT = 0x0, + OUTPUT_LINE = 0x1, + OUTPUT_TRIANGLE_CW = 0x2, + OUTPUT_TRIANGLE_CCW = 0x3, +} VGT_TESS_TOPOLOGY; +typedef enum VGT_RDREQ_POLICY { + VGT_POLICY_LRU = 0x0, + VGT_POLICY_STREAM = 0x1, +} VGT_RDREQ_POLICY; +typedef enum VGT_DIST_MODE { + NO_DIST = 0x0, + PATCHES = 0x1, + DONUTS = 0x2, +} VGT_DIST_MODE; +typedef enum VGT_STAGES_LS_EN { + LS_STAGE_OFF = 0x0, + LS_STAGE_ON = 0x1, + CS_STAGE_ON = 0x2, + RESERVED_LS = 0x3, +} VGT_STAGES_LS_EN; +typedef enum VGT_STAGES_HS_EN { + HS_STAGE_OFF = 0x0, + HS_STAGE_ON = 0x1, +} VGT_STAGES_HS_EN; +typedef enum VGT_STAGES_ES_EN { + ES_STAGE_OFF = 0x0, + ES_STAGE_DS = 0x1, + ES_STAGE_REAL = 0x2, + RESERVED_ES = 0x3, +} VGT_STAGES_ES_EN; +typedef enum VGT_STAGES_GS_EN { + GS_STAGE_OFF = 0x0, + GS_STAGE_ON = 0x1, +} VGT_STAGES_GS_EN; +typedef enum VGT_STAGES_VS_EN { + VS_STAGE_REAL = 0x0, + VS_STAGE_DS = 0x1, + VS_STAGE_COPY_SHADER = 0x2, + RESERVED_VS = 0x3, +} VGT_STAGES_VS_EN; +typedef enum VGT_PERFCOUNT_SELECT { + vgt_perf_VGT_SPI_ESTHREAD_EVENT_WINDOW_ACTIVE = 0x0, + vgt_perf_VGT_SPI_ESVERT_VALID = 0x1, + vgt_perf_VGT_SPI_ESVERT_EOV = 0x2, + vgt_perf_VGT_SPI_ESVERT_STALLED = 0x3, + vgt_perf_VGT_SPI_ESVERT_STARVED_BUSY = 0x4, + vgt_perf_VGT_SPI_ESVERT_STARVED_IDLE = 0x5, + vgt_perf_VGT_SPI_ESVERT_STATIC = 0x6, + vgt_perf_VGT_SPI_ESTHREAD_IS_EVENT = 0x7, + vgt_perf_VGT_SPI_ESTHREAD_SEND = 0x8, + vgt_perf_VGT_SPI_GSPRIM_VALID = 0x9, + vgt_perf_VGT_SPI_GSPRIM_EOV = 0xa, + vgt_perf_VGT_SPI_GSPRIM_CONT = 0xb, + vgt_perf_VGT_SPI_GSPRIM_STALLED = 0xc, + vgt_perf_VGT_SPI_GSPRIM_STARVED_BUSY = 0xd, + vgt_perf_VGT_SPI_GSPRIM_STARVED_IDLE = 0xe, + vgt_perf_VGT_SPI_GSPRIM_STATIC = 0xf, + vgt_perf_VGT_SPI_GSTHREAD_EVENT_WINDOW_ACTIVE = 0x10, + vgt_perf_VGT_SPI_GSTHREAD_IS_EVENT = 0x11, + vgt_perf_VGT_SPI_GSTHREAD_SEND = 0x12, + vgt_perf_VGT_SPI_VSTHREAD_EVENT_WINDOW_ACTIVE = 0x13, + vgt_perf_VGT_SPI_VSVERT_SEND = 0x14, + vgt_perf_VGT_SPI_VSVERT_EOV = 0x15, + vgt_perf_VGT_SPI_VSVERT_STALLED = 0x16, + vgt_perf_VGT_SPI_VSVERT_STARVED_BUSY = 0x17, + vgt_perf_VGT_SPI_VSVERT_STARVED_IDLE = 0x18, + vgt_perf_VGT_SPI_VSVERT_STATIC = 0x19, + vgt_perf_VGT_SPI_VSTHREAD_IS_EVENT = 0x1a, + vgt_perf_VGT_SPI_VSTHREAD_SEND = 0x1b, + vgt_perf_VGT_PA_EVENT_WINDOW_ACTIVE = 0x1c, + vgt_perf_VGT_PA_CLIPV_SEND = 0x1d, + vgt_perf_VGT_PA_CLIPV_FIRSTVERT = 0x1e, + vgt_perf_VGT_PA_CLIPV_STALLED = 0x1f, + vgt_perf_VGT_PA_CLIPV_STARVED_BUSY = 0x20, + vgt_perf_VGT_PA_CLIPV_STARVED_IDLE = 0x21, + vgt_perf_VGT_PA_CLIPV_STATIC = 0x22, + vgt_perf_VGT_PA_CLIPP_SEND = 0x23, + vgt_perf_VGT_PA_CLIPP_EOP = 0x24, + vgt_perf_VGT_PA_CLIPP_IS_EVENT = 0x25, + vgt_perf_VGT_PA_CLIPP_NULL_PRIM = 0x26, + vgt_perf_VGT_PA_CLIPP_NEW_VTX_VECT = 0x27, + vgt_perf_VGT_PA_CLIPP_STALLED = 0x28, + vgt_perf_VGT_PA_CLIPP_STARVED_BUSY = 0x29, + vgt_perf_VGT_PA_CLIPP_STARVED_IDLE = 0x2a, + vgt_perf_VGT_PA_CLIPP_STATIC = 0x2b, + vgt_perf_VGT_PA_CLIPS_SEND = 0x2c, + vgt_perf_VGT_PA_CLIPS_STALLED = 0x2d, + vgt_perf_VGT_PA_CLIPS_STARVED_BUSY = 0x2e, + vgt_perf_VGT_PA_CLIPS_STARVED_IDLE = 0x2f, + vgt_perf_VGT_PA_CLIPS_STATIC = 0x30, + vgt_perf_vsvert_ds_send = 0x31, + vgt_perf_vsvert_api_send = 0x32, + vgt_perf_hs_tif_stall = 0x33, + vgt_perf_hs_input_stall = 0x34, + vgt_perf_hs_interface_stall = 0x35, + vgt_perf_hs_tfm_stall = 0x36, + vgt_perf_te11_starved = 0x37, + vgt_perf_gs_event_stall = 0x38, + vgt_perf_vgt_pa_clipp_send_not_event = 0x39, + vgt_perf_vgt_pa_clipp_valid_prim = 0x3a, + vgt_perf_reused_es_indices = 0x3b, + vgt_perf_vs_cache_hits = 0x3c, + vgt_perf_gs_cache_hits = 0x3d, + vgt_perf_ds_cache_hits = 0x3e, + vgt_perf_total_cache_hits = 0x3f, + vgt_perf_vgt_busy = 0x40, + vgt_perf_vgt_gs_busy = 0x41, + vgt_perf_esvert_stalled_es_tbl = 0x42, + vgt_perf_esvert_stalled_gs_tbl = 0x43, + vgt_perf_esvert_stalled_gs_event = 0x44, + vgt_perf_esvert_stalled_gsprim = 0x45, + vgt_perf_gsprim_stalled_es_tbl = 0x46, + vgt_perf_gsprim_stalled_gs_tbl = 0x47, + vgt_perf_gsprim_stalled_gs_event = 0x48, + vgt_perf_gsprim_stalled_esvert = 0x49, + vgt_perf_esthread_stalled_es_rb_full = 0x4a, + vgt_perf_esthread_stalled_spi_bp = 0x4b, + vgt_perf_counters_avail_stalled = 0x4c, + vgt_perf_gs_rb_space_avail_stalled = 0x4d, + vgt_perf_gs_issue_rtr_stalled = 0x4e, + vgt_perf_gsthread_stalled = 0x4f, + vgt_perf_strmout_stalled = 0x50, + vgt_perf_wait_for_es_done_stalled = 0x51, + vgt_perf_cm_stalled_by_gog = 0x52, + vgt_perf_cm_reading_stalled = 0x53, + vgt_perf_cm_stalled_by_gsfetch_done = 0x54, + vgt_perf_gog_vs_tbl_stalled = 0x55, + vgt_perf_gog_out_indx_stalled = 0x56, + vgt_perf_gog_out_prim_stalled = 0x57, + vgt_perf_waveid_stalled = 0x58, + vgt_perf_gog_busy = 0x59, + vgt_perf_reused_vs_indices = 0x5a, + vgt_perf_sclk_reg_vld_event = 0x5b, + vgt_perf_vs_conflicting_indices = 0x5c, + vgt_perf_sclk_core_vld_event = 0x5d, + vgt_perf_hswave_stalled = 0x5e, + vgt_perf_sclk_gs_vld_event = 0x5f, + vgt_perf_VGT_SPI_LSVERT_VALID = 0x60, + vgt_perf_VGT_SPI_LSVERT_EOV = 0x61, + vgt_perf_VGT_SPI_LSVERT_STALLED = 0x62, + vgt_perf_VGT_SPI_LSVERT_STARVED_BUSY = 0x63, + vgt_perf_VGT_SPI_LSVERT_STARVED_IDLE = 0x64, + vgt_perf_VGT_SPI_LSVERT_STATIC = 0x65, + vgt_perf_VGT_SPI_LSWAVE_EVENT_WINDOW_ACTIVE = 0x66, + vgt_perf_VGT_SPI_LSWAVE_IS_EVENT = 0x67, + vgt_perf_VGT_SPI_LSWAVE_SEND = 0x68, + vgt_perf_VGT_SPI_HSVERT_VALID = 0x69, + vgt_perf_VGT_SPI_HSVERT_EOV = 0x6a, + vgt_perf_VGT_SPI_HSVERT_STALLED = 0x6b, + vgt_perf_VGT_SPI_HSVERT_STARVED_BUSY = 0x6c, + vgt_perf_VGT_SPI_HSVERT_STARVED_IDLE = 0x6d, + vgt_perf_VGT_SPI_HSVERT_STATIC = 0x6e, + vgt_perf_VGT_SPI_HSWAVE_EVENT_WINDOW_ACTIVE = 0x6f, + vgt_perf_VGT_SPI_HSWAVE_IS_EVENT = 0x70, + vgt_perf_VGT_SPI_HSWAVE_SEND = 0x71, + vgt_perf_ds_prims = 0x72, + vgt_perf_ls_thread_groups = 0x73, + vgt_perf_hs_thread_groups = 0x74, + vgt_perf_es_thread_groups = 0x75, + vgt_perf_vs_thread_groups = 0x76, + vgt_perf_ls_done_latency = 0x77, + vgt_perf_hs_done_latency = 0x78, + vgt_perf_es_done_latency = 0x79, + vgt_perf_gs_done_latency = 0x7a, + vgt_perf_vgt_hs_busy = 0x7b, + vgt_perf_vgt_te11_busy = 0x7c, + vgt_perf_ls_flush = 0x7d, + vgt_perf_hs_flush = 0x7e, + vgt_perf_es_flush = 0x7f, + vgt_perf_vgt_pa_clipp_eopg = 0x80, + vgt_perf_ls_done = 0x81, + vgt_perf_hs_done = 0x82, + vgt_perf_es_done = 0x83, + vgt_perf_gs_done = 0x84, + vgt_perf_vsfetch_done = 0x85, + vgt_perf_gs_done_received = 0x86, + vgt_perf_es_ring_high_water_mark = 0x87, + vgt_perf_gs_ring_high_water_mark = 0x88, + vgt_perf_vs_table_high_water_mark = 0x89, + vgt_perf_hs_tgs_active_high_water_mark = 0x8a, + vgt_perf_pa_clipp_dealloc = 0x8b, + vgt_perf_cut_mem_flush_stalled = 0x8c, + vgt_perf_vsvert_work_received = 0x8d, + vgt_perf_vgt_pa_clipp_starved_after_work = 0x8e, + vgt_perf_te11_con_starved_after_work = 0x8f, + vgt_perf_hs_waiting_on_ls_done_stall = 0x90, + vgt_spi_vsvert_valid = 0x91, +} VGT_PERFCOUNT_SELECT; +typedef enum IA_PERFCOUNT_SELECT { + ia_perf_GRP_INPUT_EVENT_WINDOW_ACTIVE = 0x0, + ia_perf_dma_data_fifo_full = 0x1, + ia_perf_RESERVED1 = 0x2, + ia_perf_RESERVED2 = 0x3, + ia_perf_RESERVED3 = 0x4, + ia_perf_RESERVED4 = 0x5, + ia_perf_RESERVED5 = 0x6, + ia_perf_MC_LAT_BIN_0 = 0x7, + ia_perf_MC_LAT_BIN_1 = 0x8, + ia_perf_MC_LAT_BIN_2 = 0x9, + ia_perf_MC_LAT_BIN_3 = 0xa, + ia_perf_MC_LAT_BIN_4 = 0xb, + ia_perf_MC_LAT_BIN_5 = 0xc, + ia_perf_MC_LAT_BIN_6 = 0xd, + ia_perf_MC_LAT_BIN_7 = 0xe, + ia_perf_ia_busy = 0xf, + ia_perf_ia_sclk_reg_vld_event = 0x10, + ia_perf_RESERVED6 = 0x11, + ia_perf_ia_sclk_core_vld_event = 0x12, + ia_perf_RESERVED7 = 0x13, + ia_perf_ia_dma_return = 0x14, + ia_perf_ia_stalled = 0x15, + ia_perf_shift_starved_pipe0_event = 0x16, + ia_perf_shift_starved_pipe1_event = 0x17, +} IA_PERFCOUNT_SELECT; +typedef enum WD_PERFCOUNT_SELECT { + wd_perf_RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 0x0, + wd_perf_RBIU_DR_FIFO_STARVED = 0x1, + wd_perf_RBIU_DR_FIFO_STALLED = 0x2, + wd_perf_RBIU_DI_FIFO_STARVED = 0x3, + wd_perf_RBIU_DI_FIFO_STALLED = 0x4, + wd_perf_wd_busy = 0x5, + wd_perf_wd_sclk_reg_vld_event = 0x6, + wd_perf_wd_sclk_input_vld_event = 0x7, + wd_perf_wd_sclk_core_vld_event = 0x8, + wd_perf_wd_stalled = 0x9, + wd_perf_inside_tf_bin_0 = 0xa, + wd_perf_inside_tf_bin_1 = 0xb, + wd_perf_inside_tf_bin_2 = 0xc, + wd_perf_inside_tf_bin_3 = 0xd, + wd_perf_inside_tf_bin_4 = 0xe, + wd_perf_inside_tf_bin_5 = 0xf, + wd_perf_inside_tf_bin_6 = 0x10, + wd_perf_inside_tf_bin_7 = 0x11, + wd_perf_inside_tf_bin_8 = 0x12, + wd_perf_tfreq_lat_bin_0 = 0x13, + wd_perf_tfreq_lat_bin_1 = 0x14, + wd_perf_tfreq_lat_bin_2 = 0x15, + wd_perf_tfreq_lat_bin_3 = 0x16, + wd_perf_tfreq_lat_bin_4 = 0x17, + wd_perf_tfreq_lat_bin_5 = 0x18, + wd_perf_tfreq_lat_bin_6 = 0x19, + wd_perf_tfreq_lat_bin_7 = 0x1a, + wd_starved_on_hs_done = 0x1b, + wd_perf_se0_hs_done_latency = 0x1c, + wd_perf_se1_hs_done_latency = 0x1d, + wd_perf_se2_hs_done_latency = 0x1e, + wd_perf_se3_hs_done_latency = 0x1f, + wd_perf_hs_done_se0 = 0x20, + wd_perf_hs_done_se1 = 0x21, + wd_perf_hs_done_se2 = 0x22, + wd_perf_hs_done_se3 = 0x23, + wd_perf_null_patches = 0x24, +} WD_PERFCOUNT_SELECT; +typedef enum WD_IA_DRAW_TYPE { + WD_IA_DRAW_TYPE_DI_MM0 = 0x0, + WD_IA_DRAW_TYPE_DI_MM1 = 0x1, + WD_IA_DRAW_TYPE_EVENT_INIT = 0x2, + WD_IA_DRAW_TYPE_EVENT_ADDR = 0x3, + WD_IA_DRAW_TYPE_MIN_INDX = 0x4, + WD_IA_DRAW_TYPE_MAX_INDX = 0x5, + WD_IA_DRAW_TYPE_INDX_OFF = 0x6, + WD_IA_DRAW_TYPE_IMM_DATA = 0x7, +} WD_IA_DRAW_TYPE; +typedef enum WD_IA_DRAW_SOURCE { + WD_IA_DRAW_SOURCE_DMA = 0x0, + WD_IA_DRAW_SOURCE_IMMD = 0x1, + WD_IA_DRAW_SOURCE_AUTO = 0x2, + WD_IA_DRAW_SOURCE_OPAQ = 0x3, +} WD_IA_DRAW_SOURCE; +#define GSTHREADID_SIZE 0x2 +typedef enum DebugBlockId { + DBG_BLOCK_ID_RESERVED = 0x0, + DBG_BLOCK_ID_DBG = 0x1, + DBG_BLOCK_ID_VMC = 0x2, + DBG_BLOCK_ID_PDMA = 0x3, + DBG_BLOCK_ID_CG = 0x4, + DBG_BLOCK_ID_SRBM = 0x5, + DBG_BLOCK_ID_GRBM = 0x6, + DBG_BLOCK_ID_RLC = 0x7, + DBG_BLOCK_ID_CSC = 0x8, + DBG_BLOCK_ID_SEM = 0x9, + DBG_BLOCK_ID_IH = 0xa, + DBG_BLOCK_ID_SC = 0xb, + DBG_BLOCK_ID_SQ = 0xc, + DBG_BLOCK_ID_UVDU = 0xd, + DBG_BLOCK_ID_SQA = 0xe, + DBG_BLOCK_ID_SDMA0 = 0xf, + DBG_BLOCK_ID_SDMA1 = 0x10, + DBG_BLOCK_ID_SPIM = 0x11, + DBG_BLOCK_ID_GDS = 0x12, + DBG_BLOCK_ID_VC0 = 0x13, + DBG_BLOCK_ID_VC1 = 0x14, + DBG_BLOCK_ID_PA0 = 0x15, + DBG_BLOCK_ID_PA1 = 0x16, + DBG_BLOCK_ID_CP0 = 0x17, + DBG_BLOCK_ID_CP1 = 0x18, + DBG_BLOCK_ID_CP2 = 0x19, + DBG_BLOCK_ID_XBR = 0x1a, + DBG_BLOCK_ID_UVDM = 0x1b, + DBG_BLOCK_ID_VGT0 = 0x1c, + DBG_BLOCK_ID_VGT1 = 0x1d, + DBG_BLOCK_ID_IA = 0x1e, + DBG_BLOCK_ID_SXM0 = 0x1f, + DBG_BLOCK_ID_SXM1 = 0x20, + DBG_BLOCK_ID_SCT0 = 0x21, + DBG_BLOCK_ID_SCT1 = 0x22, + DBG_BLOCK_ID_SPM0 = 0x23, + DBG_BLOCK_ID_SPM1 = 0x24, + DBG_BLOCK_ID_UNUSED0 = 0x25, + DBG_BLOCK_ID_UNUSED1 = 0x26, + DBG_BLOCK_ID_TCAA = 0x27, + DBG_BLOCK_ID_TCAB = 0x28, + DBG_BLOCK_ID_TCCA = 0x29, + DBG_BLOCK_ID_TCCB = 0x2a, + DBG_BLOCK_ID_MCC0 = 0x2b, + DBG_BLOCK_ID_MCC1 = 0x2c, + DBG_BLOCK_ID_MCC2 = 0x2d, + DBG_BLOCK_ID_MCC3 = 0x2e, + DBG_BLOCK_ID_SXS0 = 0x2f, + DBG_BLOCK_ID_SXS1 = 0x30, + DBG_BLOCK_ID_SXS2 = 0x31, + DBG_BLOCK_ID_SXS3 = 0x32, + DBG_BLOCK_ID_SXS4 = 0x33, + DBG_BLOCK_ID_SXS5 = 0x34, + DBG_BLOCK_ID_SXS6 = 0x35, + DBG_BLOCK_ID_SXS7 = 0x36, + DBG_BLOCK_ID_SXS8 = 0x37, + DBG_BLOCK_ID_SXS9 = 0x38, + DBG_BLOCK_ID_BCI0 = 0x39, + DBG_BLOCK_ID_BCI1 = 0x3a, + DBG_BLOCK_ID_BCI2 = 0x3b, + DBG_BLOCK_ID_BCI3 = 0x3c, + DBG_BLOCK_ID_MCB = 0x3d, + DBG_BLOCK_ID_UNUSED6 = 0x3e, + DBG_BLOCK_ID_SQA00 = 0x3f, + DBG_BLOCK_ID_SQA01 = 0x40, + DBG_BLOCK_ID_SQA02 = 0x41, + DBG_BLOCK_ID_SQA10 = 0x42, + DBG_BLOCK_ID_SQA11 = 0x43, + DBG_BLOCK_ID_SQA12 = 0x44, + DBG_BLOCK_ID_UNUSED7 = 0x45, + DBG_BLOCK_ID_UNUSED8 = 0x46, + DBG_BLOCK_ID_SQB00 = 0x47, + DBG_BLOCK_ID_SQB01 = 0x48, + DBG_BLOCK_ID_SQB10 = 0x49, + DBG_BLOCK_ID_SQB11 = 0x4a, + DBG_BLOCK_ID_SQ00 = 0x4b, + DBG_BLOCK_ID_SQ01 = 0x4c, + DBG_BLOCK_ID_SQ10 = 0x4d, + DBG_BLOCK_ID_SQ11 = 0x4e, + DBG_BLOCK_ID_CB00 = 0x4f, + DBG_BLOCK_ID_CB01 = 0x50, + DBG_BLOCK_ID_CB02 = 0x51, + DBG_BLOCK_ID_CB03 = 0x52, + DBG_BLOCK_ID_CB04 = 0x53, + DBG_BLOCK_ID_UNUSED9 = 0x54, + DBG_BLOCK_ID_UNUSED10 = 0x55, + DBG_BLOCK_ID_UNUSED11 = 0x56, + DBG_BLOCK_ID_CB10 = 0x57, + DBG_BLOCK_ID_CB11 = 0x58, + DBG_BLOCK_ID_CB12 = 0x59, + DBG_BLOCK_ID_CB13 = 0x5a, + DBG_BLOCK_ID_CB14 = 0x5b, + DBG_BLOCK_ID_UNUSED12 = 0x5c, + DBG_BLOCK_ID_UNUSED13 = 0x5d, + DBG_BLOCK_ID_UNUSED14 = 0x5e, + DBG_BLOCK_ID_TCP0 = 0x5f, + DBG_BLOCK_ID_TCP1 = 0x60, + DBG_BLOCK_ID_TCP2 = 0x61, + DBG_BLOCK_ID_TCP3 = 0x62, + DBG_BLOCK_ID_TCP4 = 0x63, + DBG_BLOCK_ID_TCP5 = 0x64, + DBG_BLOCK_ID_TCP6 = 0x65, + DBG_BLOCK_ID_TCP7 = 0x66, + DBG_BLOCK_ID_TCP8 = 0x67, + DBG_BLOCK_ID_TCP9 = 0x68, + DBG_BLOCK_ID_TCP10 = 0x69, + DBG_BLOCK_ID_TCP11 = 0x6a, + DBG_BLOCK_ID_TCP12 = 0x6b, + DBG_BLOCK_ID_TCP13 = 0x6c, + DBG_BLOCK_ID_TCP14 = 0x6d, + DBG_BLOCK_ID_TCP15 = 0x6e, + DBG_BLOCK_ID_TCP16 = 0x6f, + DBG_BLOCK_ID_TCP17 = 0x70, + DBG_BLOCK_ID_TCP18 = 0x71, + DBG_BLOCK_ID_TCP19 = 0x72, + DBG_BLOCK_ID_TCP20 = 0x73, + DBG_BLOCK_ID_TCP21 = 0x74, + DBG_BLOCK_ID_TCP22 = 0x75, + DBG_BLOCK_ID_TCP23 = 0x76, + DBG_BLOCK_ID_TCP_RESERVED0 = 0x77, + DBG_BLOCK_ID_TCP_RESERVED1 = 0x78, + DBG_BLOCK_ID_TCP_RESERVED2 = 0x79, + DBG_BLOCK_ID_TCP_RESERVED3 = 0x7a, + DBG_BLOCK_ID_TCP_RESERVED4 = 0x7b, + DBG_BLOCK_ID_TCP_RESERVED5 = 0x7c, + DBG_BLOCK_ID_TCP_RESERVED6 = 0x7d, + DBG_BLOCK_ID_TCP_RESERVED7 = 0x7e, + DBG_BLOCK_ID_DB00 = 0x7f, + DBG_BLOCK_ID_DB01 = 0x80, + DBG_BLOCK_ID_DB02 = 0x81, + DBG_BLOCK_ID_DB03 = 0x82, + DBG_BLOCK_ID_DB04 = 0x83, + DBG_BLOCK_ID_UNUSED15 = 0x84, + DBG_BLOCK_ID_UNUSED16 = 0x85, + DBG_BLOCK_ID_UNUSED17 = 0x86, + DBG_BLOCK_ID_DB10 = 0x87, + DBG_BLOCK_ID_DB11 = 0x88, + DBG_BLOCK_ID_DB12 = 0x89, + DBG_BLOCK_ID_DB13 = 0x8a, + DBG_BLOCK_ID_DB14 = 0x8b, + DBG_BLOCK_ID_UNUSED18 = 0x8c, + DBG_BLOCK_ID_UNUSED19 = 0x8d, + DBG_BLOCK_ID_UNUSED20 = 0x8e, + DBG_BLOCK_ID_TCC0 = 0x8f, + DBG_BLOCK_ID_TCC1 = 0x90, + DBG_BLOCK_ID_TCC2 = 0x91, + DBG_BLOCK_ID_TCC3 = 0x92, + DBG_BLOCK_ID_TCC4 = 0x93, + DBG_BLOCK_ID_TCC5 = 0x94, + DBG_BLOCK_ID_TCC6 = 0x95, + DBG_BLOCK_ID_TCC7 = 0x96, + DBG_BLOCK_ID_SPS00 = 0x97, + DBG_BLOCK_ID_SPS01 = 0x98, + DBG_BLOCK_ID_SPS02 = 0x99, + DBG_BLOCK_ID_SPS10 = 0x9a, + DBG_BLOCK_ID_SPS11 = 0x9b, + DBG_BLOCK_ID_SPS12 = 0x9c, + DBG_BLOCK_ID_UNUSED21 = 0x9d, + DBG_BLOCK_ID_UNUSED22 = 0x9e, + DBG_BLOCK_ID_TA00 = 0x9f, + DBG_BLOCK_ID_TA01 = 0xa0, + DBG_BLOCK_ID_TA02 = 0xa1, + DBG_BLOCK_ID_TA03 = 0xa2, + DBG_BLOCK_ID_TA04 = 0xa3, + DBG_BLOCK_ID_TA05 = 0xa4, + DBG_BLOCK_ID_TA06 = 0xa5, + DBG_BLOCK_ID_TA07 = 0xa6, + DBG_BLOCK_ID_TA08 = 0xa7, + DBG_BLOCK_ID_TA09 = 0xa8, + DBG_BLOCK_ID_TA0A = 0xa9, + DBG_BLOCK_ID_TA0B = 0xaa, + DBG_BLOCK_ID_UNUSED23 = 0xab, + DBG_BLOCK_ID_UNUSED24 = 0xac, + DBG_BLOCK_ID_UNUSED25 = 0xad, + DBG_BLOCK_ID_UNUSED26 = 0xae, + DBG_BLOCK_ID_TA10 = 0xaf, + DBG_BLOCK_ID_TA11 = 0xb0, + DBG_BLOCK_ID_TA12 = 0xb1, + DBG_BLOCK_ID_TA13 = 0xb2, + DBG_BLOCK_ID_TA14 = 0xb3, + DBG_BLOCK_ID_TA15 = 0xb4, + DBG_BLOCK_ID_TA16 = 0xb5, + DBG_BLOCK_ID_TA17 = 0xb6, + DBG_BLOCK_ID_TA18 = 0xb7, + DBG_BLOCK_ID_TA19 = 0xb8, + DBG_BLOCK_ID_TA1A = 0xb9, + DBG_BLOCK_ID_TA1B = 0xba, + DBG_BLOCK_ID_UNUSED27 = 0xbb, + DBG_BLOCK_ID_UNUSED28 = 0xbc, + DBG_BLOCK_ID_UNUSED29 = 0xbd, + DBG_BLOCK_ID_UNUSED30 = 0xbe, + DBG_BLOCK_ID_TD00 = 0xbf, + DBG_BLOCK_ID_TD01 = 0xc0, + DBG_BLOCK_ID_TD02 = 0xc1, + DBG_BLOCK_ID_TD03 = 0xc2, + DBG_BLOCK_ID_TD04 = 0xc3, + DBG_BLOCK_ID_TD05 = 0xc4, + DBG_BLOCK_ID_TD06 = 0xc5, + DBG_BLOCK_ID_TD07 = 0xc6, + DBG_BLOCK_ID_TD08 = 0xc7, + DBG_BLOCK_ID_TD09 = 0xc8, + DBG_BLOCK_ID_TD0A = 0xc9, + DBG_BLOCK_ID_TD0B = 0xca, + DBG_BLOCK_ID_UNUSED31 = 0xcb, + DBG_BLOCK_ID_UNUSED32 = 0xcc, + DBG_BLOCK_ID_UNUSED33 = 0xcd, + DBG_BLOCK_ID_UNUSED34 = 0xce, + DBG_BLOCK_ID_TD10 = 0xcf, + DBG_BLOCK_ID_TD11 = 0xd0, + DBG_BLOCK_ID_TD12 = 0xd1, + DBG_BLOCK_ID_TD13 = 0xd2, + DBG_BLOCK_ID_TD14 = 0xd3, + DBG_BLOCK_ID_TD15 = 0xd4, + DBG_BLOCK_ID_TD16 = 0xd5, + DBG_BLOCK_ID_TD17 = 0xd6, + DBG_BLOCK_ID_TD18 = 0xd7, + DBG_BLOCK_ID_TD19 = 0xd8, + DBG_BLOCK_ID_TD1A = 0xd9, + DBG_BLOCK_ID_TD1B = 0xda, + DBG_BLOCK_ID_UNUSED35 = 0xdb, + DBG_BLOCK_ID_UNUSED36 = 0xdc, + DBG_BLOCK_ID_UNUSED37 = 0xdd, + DBG_BLOCK_ID_UNUSED38 = 0xde, + DBG_BLOCK_ID_LDS00 = 0xdf, + DBG_BLOCK_ID_LDS01 = 0xe0, + DBG_BLOCK_ID_LDS02 = 0xe1, + DBG_BLOCK_ID_LDS03 = 0xe2, + DBG_BLOCK_ID_LDS04 = 0xe3, + DBG_BLOCK_ID_LDS05 = 0xe4, + DBG_BLOCK_ID_LDS06 = 0xe5, + DBG_BLOCK_ID_LDS07 = 0xe6, + DBG_BLOCK_ID_LDS08 = 0xe7, + DBG_BLOCK_ID_LDS09 = 0xe8, + DBG_BLOCK_ID_LDS0A = 0xe9, + DBG_BLOCK_ID_LDS0B = 0xea, + DBG_BLOCK_ID_UNUSED39 = 0xeb, + DBG_BLOCK_ID_UNUSED40 = 0xec, + DBG_BLOCK_ID_UNUSED41 = 0xed, + DBG_BLOCK_ID_UNUSED42 = 0xee, + DBG_BLOCK_ID_LDS10 = 0xef, + DBG_BLOCK_ID_LDS11 = 0xf0, + DBG_BLOCK_ID_LDS12 = 0xf1, + DBG_BLOCK_ID_LDS13 = 0xf2, + DBG_BLOCK_ID_LDS14 = 0xf3, + DBG_BLOCK_ID_LDS15 = 0xf4, + DBG_BLOCK_ID_LDS16 = 0xf5, + DBG_BLOCK_ID_LDS17 = 0xf6, + DBG_BLOCK_ID_LDS18 = 0xf7, + DBG_BLOCK_ID_LDS19 = 0xf8, + DBG_BLOCK_ID_LDS1A = 0xf9, + DBG_BLOCK_ID_LDS1B = 0xfa, + DBG_BLOCK_ID_UNUSED43 = 0xfb, + DBG_BLOCK_ID_UNUSED44 = 0xfc, + DBG_BLOCK_ID_UNUSED45 = 0xfd, + DBG_BLOCK_ID_UNUSED46 = 0xfe, +} DebugBlockId; +typedef enum DebugBlockId_BY2 { + DBG_BLOCK_ID_RESERVED_BY2 = 0x0, + DBG_BLOCK_ID_VMC_BY2 = 0x1, + DBG_BLOCK_ID_UNUSED0_BY2 = 0x2, + DBG_BLOCK_ID_GRBM_BY2 = 0x3, + DBG_BLOCK_ID_CSC_BY2 = 0x4, + DBG_BLOCK_ID_IH_BY2 = 0x5, + DBG_BLOCK_ID_SQ_BY2 = 0x6, + DBG_BLOCK_ID_UVD_BY2 = 0x7, + DBG_BLOCK_ID_SDMA0_BY2 = 0x8, + DBG_BLOCK_ID_SPIM_BY2 = 0x9, + DBG_BLOCK_ID_VC0_BY2 = 0xa, + DBG_BLOCK_ID_PA_BY2 = 0xb, + DBG_BLOCK_ID_CP0_BY2 = 0xc, + DBG_BLOCK_ID_CP2_BY2 = 0xd, + DBG_BLOCK_ID_PC0_BY2 = 0xe, + DBG_BLOCK_ID_BCI0_BY2 = 0xf, + DBG_BLOCK_ID_SXM0_BY2 = 0x10, + DBG_BLOCK_ID_SCT0_BY2 = 0x11, + DBG_BLOCK_ID_SPM0_BY2 = 0x12, + DBG_BLOCK_ID_BCI2_BY2 = 0x13, + DBG_BLOCK_ID_TCA_BY2 = 0x14, + DBG_BLOCK_ID_TCCA_BY2 = 0x15, + DBG_BLOCK_ID_MCC_BY2 = 0x16, + DBG_BLOCK_ID_MCC2_BY2 = 0x17, + DBG_BLOCK_ID_MCD_BY2 = 0x18, + DBG_BLOCK_ID_MCD2_BY2 = 0x19, + DBG_BLOCK_ID_MCD4_BY2 = 0x1a, + DBG_BLOCK_ID_MCB_BY2 = 0x1b, + DBG_BLOCK_ID_SQA_BY2 = 0x1c, + DBG_BLOCK_ID_SQA02_BY2 = 0x1d, + DBG_BLOCK_ID_SQA11_BY2 = 0x1e, + DBG_BLOCK_ID_UNUSED8_BY2 = 0x1f, + DBG_BLOCK_ID_SQB_BY2 = 0x20, + DBG_BLOCK_ID_SQB10_BY2 = 0x21, + DBG_BLOCK_ID_UNUSED10_BY2 = 0x22, + DBG_BLOCK_ID_UNUSED12_BY2 = 0x23, + DBG_BLOCK_ID_CB_BY2 = 0x24, + DBG_BLOCK_ID_CB02_BY2 = 0x25, + DBG_BLOCK_ID_CB10_BY2 = 0x26, + DBG_BLOCK_ID_CB12_BY2 = 0x27, + DBG_BLOCK_ID_SXS_BY2 = 0x28, + DBG_BLOCK_ID_SXS2_BY2 = 0x29, + DBG_BLOCK_ID_SXS4_BY2 = 0x2a, + DBG_BLOCK_ID_SXS6_BY2 = 0x2b, + DBG_BLOCK_ID_DB_BY2 = 0x2c, + DBG_BLOCK_ID_DB02_BY2 = 0x2d, + DBG_BLOCK_ID_DB10_BY2 = 0x2e, + DBG_BLOCK_ID_DB12_BY2 = 0x2f, + DBG_BLOCK_ID_TCP_BY2 = 0x30, + DBG_BLOCK_ID_TCP2_BY2 = 0x31, + DBG_BLOCK_ID_TCP4_BY2 = 0x32, + DBG_BLOCK_ID_TCP6_BY2 = 0x33, + DBG_BLOCK_ID_TCP8_BY2 = 0x34, + DBG_BLOCK_ID_TCP10_BY2 = 0x35, + DBG_BLOCK_ID_TCP12_BY2 = 0x36, + DBG_BLOCK_ID_TCP14_BY2 = 0x37, + DBG_BLOCK_ID_TCP16_BY2 = 0x38, + DBG_BLOCK_ID_TCP18_BY2 = 0x39, + DBG_BLOCK_ID_TCP20_BY2 = 0x3a, + DBG_BLOCK_ID_TCP22_BY2 = 0x3b, + DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c, + DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d, + DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e, + DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f, + DBG_BLOCK_ID_TCC_BY2 = 0x40, + DBG_BLOCK_ID_TCC2_BY2 = 0x41, + DBG_BLOCK_ID_TCC4_BY2 = 0x42, + DBG_BLOCK_ID_TCC6_BY2 = 0x43, + DBG_BLOCK_ID_SPS_BY2 = 0x44, + DBG_BLOCK_ID_SPS02_BY2 = 0x45, + DBG_BLOCK_ID_SPS11_BY2 = 0x46, + DBG_BLOCK_ID_UNUSED14_BY2 = 0x47, + DBG_BLOCK_ID_TA_BY2 = 0x48, + DBG_BLOCK_ID_TA02_BY2 = 0x49, + DBG_BLOCK_ID_TA04_BY2 = 0x4a, + DBG_BLOCK_ID_TA06_BY2 = 0x4b, + DBG_BLOCK_ID_TA08_BY2 = 0x4c, + DBG_BLOCK_ID_TA0A_BY2 = 0x4d, + DBG_BLOCK_ID_UNUSED20_BY2 = 0x4e, + DBG_BLOCK_ID_UNUSED22_BY2 = 0x4f, + DBG_BLOCK_ID_TA10_BY2 = 0x50, + DBG_BLOCK_ID_TA12_BY2 = 0x51, + DBG_BLOCK_ID_TA14_BY2 = 0x52, + DBG_BLOCK_ID_TA16_BY2 = 0x53, + DBG_BLOCK_ID_TA18_BY2 = 0x54, + DBG_BLOCK_ID_TA1A_BY2 = 0x55, + DBG_BLOCK_ID_UNUSED24_BY2 = 0x56, + DBG_BLOCK_ID_UNUSED26_BY2 = 0x57, + DBG_BLOCK_ID_TD_BY2 = 0x58, + DBG_BLOCK_ID_TD02_BY2 = 0x59, + DBG_BLOCK_ID_TD04_BY2 = 0x5a, + DBG_BLOCK_ID_TD06_BY2 = 0x5b, + DBG_BLOCK_ID_TD08_BY2 = 0x5c, + DBG_BLOCK_ID_TD0A_BY2 = 0x5d, + DBG_BLOCK_ID_UNUSED28_BY2 = 0x5e, + DBG_BLOCK_ID_UNUSED30_BY2 = 0x5f, + DBG_BLOCK_ID_TD10_BY2 = 0x60, + DBG_BLOCK_ID_TD12_BY2 = 0x61, + DBG_BLOCK_ID_TD14_BY2 = 0x62, + DBG_BLOCK_ID_TD16_BY2 = 0x63, + DBG_BLOCK_ID_TD18_BY2 = 0x64, + DBG_BLOCK_ID_TD1A_BY2 = 0x65, + DBG_BLOCK_ID_UNUSED32_BY2 = 0x66, + DBG_BLOCK_ID_UNUSED34_BY2 = 0x67, + DBG_BLOCK_ID_LDS_BY2 = 0x68, + DBG_BLOCK_ID_LDS02_BY2 = 0x69, + DBG_BLOCK_ID_LDS04_BY2 = 0x6a, + DBG_BLOCK_ID_LDS06_BY2 = 0x6b, + DBG_BLOCK_ID_LDS08_BY2 = 0x6c, + DBG_BLOCK_ID_LDS0A_BY2 = 0x6d, + DBG_BLOCK_ID_UNUSED36_BY2 = 0x6e, + DBG_BLOCK_ID_UNUSED38_BY2 = 0x6f, + DBG_BLOCK_ID_LDS10_BY2 = 0x70, + DBG_BLOCK_ID_LDS12_BY2 = 0x71, + DBG_BLOCK_ID_LDS14_BY2 = 0x72, + DBG_BLOCK_ID_LDS16_BY2 = 0x73, + DBG_BLOCK_ID_LDS18_BY2 = 0x74, + DBG_BLOCK_ID_LDS1A_BY2 = 0x75, + DBG_BLOCK_ID_UNUSED40_BY2 = 0x76, + DBG_BLOCK_ID_UNUSED42_BY2 = 0x77, +} DebugBlockId_BY2; +typedef enum DebugBlockId_BY4 { + DBG_BLOCK_ID_RESERVED_BY4 = 0x0, + DBG_BLOCK_ID_UNUSED0_BY4 = 0x1, + DBG_BLOCK_ID_CSC_BY4 = 0x2, + DBG_BLOCK_ID_SQ_BY4 = 0x3, + DBG_BLOCK_ID_SDMA0_BY4 = 0x4, + DBG_BLOCK_ID_VC0_BY4 = 0x5, + DBG_BLOCK_ID_CP0_BY4 = 0x6, + DBG_BLOCK_ID_UNUSED1_BY4 = 0x7, + DBG_BLOCK_ID_SXM0_BY4 = 0x8, + DBG_BLOCK_ID_SPM0_BY4 = 0x9, + DBG_BLOCK_ID_TCAA_BY4 = 0xa, + DBG_BLOCK_ID_MCC_BY4 = 0xb, + DBG_BLOCK_ID_MCD_BY4 = 0xc, + DBG_BLOCK_ID_MCD4_BY4 = 0xd, + DBG_BLOCK_ID_SQA_BY4 = 0xe, + DBG_BLOCK_ID_SQA11_BY4 = 0xf, + DBG_BLOCK_ID_SQB_BY4 = 0x10, + DBG_BLOCK_ID_UNUSED10_BY4 = 0x11, + DBG_BLOCK_ID_CB_BY4 = 0x12, + DBG_BLOCK_ID_CB10_BY4 = 0x13, + DBG_BLOCK_ID_SXS_BY4 = 0x14, + DBG_BLOCK_ID_SXS4_BY4 = 0x15, + DBG_BLOCK_ID_DB_BY4 = 0x16, + DBG_BLOCK_ID_DB10_BY4 = 0x17, + DBG_BLOCK_ID_TCP_BY4 = 0x18, + DBG_BLOCK_ID_TCP4_BY4 = 0x19, + DBG_BLOCK_ID_TCP8_BY4 = 0x1a, + DBG_BLOCK_ID_TCP12_BY4 = 0x1b, + DBG_BLOCK_ID_TCP16_BY4 = 0x1c, + DBG_BLOCK_ID_TCP20_BY4 = 0x1d, + DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e, + DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f, + DBG_BLOCK_ID_TCC_BY4 = 0x20, + DBG_BLOCK_ID_TCC4_BY4 = 0x21, + DBG_BLOCK_ID_SPS_BY4 = 0x22, + DBG_BLOCK_ID_SPS11_BY4 = 0x23, + DBG_BLOCK_ID_TA_BY4 = 0x24, + DBG_BLOCK_ID_TA04_BY4 = 0x25, + DBG_BLOCK_ID_TA08_BY4 = 0x26, + DBG_BLOCK_ID_UNUSED20_BY4 = 0x27, + DBG_BLOCK_ID_TA10_BY4 = 0x28, + DBG_BLOCK_ID_TA14_BY4 = 0x29, + DBG_BLOCK_ID_TA18_BY4 = 0x2a, + DBG_BLOCK_ID_UNUSED24_BY4 = 0x2b, + DBG_BLOCK_ID_TD_BY4 = 0x2c, + DBG_BLOCK_ID_TD04_BY4 = 0x2d, + DBG_BLOCK_ID_TD08_BY4 = 0x2e, + DBG_BLOCK_ID_UNUSED28_BY4 = 0x2f, + DBG_BLOCK_ID_TD10_BY4 = 0x30, + DBG_BLOCK_ID_TD14_BY4 = 0x31, + DBG_BLOCK_ID_TD18_BY4 = 0x32, + DBG_BLOCK_ID_UNUSED32_BY4 = 0x33, + DBG_BLOCK_ID_LDS_BY4 = 0x34, + DBG_BLOCK_ID_LDS04_BY4 = 0x35, + DBG_BLOCK_ID_LDS08_BY4 = 0x36, + DBG_BLOCK_ID_UNUSED36_BY4 = 0x37, + DBG_BLOCK_ID_LDS10_BY4 = 0x38, + DBG_BLOCK_ID_LDS14_BY4 = 0x39, + DBG_BLOCK_ID_LDS18_BY4 = 0x3a, + DBG_BLOCK_ID_UNUSED40_BY4 = 0x3b, +} DebugBlockId_BY4; +typedef enum DebugBlockId_BY8 { + DBG_BLOCK_ID_RESERVED_BY8 = 0x0, + DBG_BLOCK_ID_CSC_BY8 = 0x1, + DBG_BLOCK_ID_SDMA0_BY8 = 0x2, + DBG_BLOCK_ID_CP0_BY8 = 0x3, + DBG_BLOCK_ID_SXM0_BY8 = 0x4, + DBG_BLOCK_ID_TCA_BY8 = 0x5, + DBG_BLOCK_ID_MCD_BY8 = 0x6, + DBG_BLOCK_ID_SQA_BY8 = 0x7, + DBG_BLOCK_ID_SQB_BY8 = 0x8, + DBG_BLOCK_ID_CB_BY8 = 0x9, + DBG_BLOCK_ID_SXS_BY8 = 0xa, + DBG_BLOCK_ID_DB_BY8 = 0xb, + DBG_BLOCK_ID_TCP_BY8 = 0xc, + DBG_BLOCK_ID_TCP8_BY8 = 0xd, + DBG_BLOCK_ID_TCP16_BY8 = 0xe, + DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf, + DBG_BLOCK_ID_TCC_BY8 = 0x10, + DBG_BLOCK_ID_SPS_BY8 = 0x11, + DBG_BLOCK_ID_TA_BY8 = 0x12, + DBG_BLOCK_ID_TA08_BY8 = 0x13, + DBG_BLOCK_ID_TA10_BY8 = 0x14, + DBG_BLOCK_ID_TA18_BY8 = 0x15, + DBG_BLOCK_ID_TD_BY8 = 0x16, + DBG_BLOCK_ID_TD08_BY8 = 0x17, + DBG_BLOCK_ID_TD10_BY8 = 0x18, + DBG_BLOCK_ID_TD18_BY8 = 0x19, + DBG_BLOCK_ID_LDS_BY8 = 0x1a, + DBG_BLOCK_ID_LDS08_BY8 = 0x1b, + DBG_BLOCK_ID_LDS10_BY8 = 0x1c, + DBG_BLOCK_ID_LDS18_BY8 = 0x1d, +} DebugBlockId_BY8; +typedef enum DebugBlockId_BY16 { + DBG_BLOCK_ID_RESERVED_BY16 = 0x0, + DBG_BLOCK_ID_SDMA0_BY16 = 0x1, + DBG_BLOCK_ID_SXM_BY16 = 0x2, + DBG_BLOCK_ID_MCD_BY16 = 0x3, + DBG_BLOCK_ID_SQB_BY16 = 0x4, + DBG_BLOCK_ID_SXS_BY16 = 0x5, + DBG_BLOCK_ID_TCP_BY16 = 0x6, + DBG_BLOCK_ID_TCP16_BY16 = 0x7, + DBG_BLOCK_ID_TCC_BY16 = 0x8, + DBG_BLOCK_ID_TA_BY16 = 0x9, + DBG_BLOCK_ID_TA10_BY16 = 0xa, + DBG_BLOCK_ID_TD_BY16 = 0xb, + DBG_BLOCK_ID_TD10_BY16 = 0xc, + DBG_BLOCK_ID_LDS_BY16 = 0xd, + DBG_BLOCK_ID_LDS10_BY16 = 0xe, +} DebugBlockId_BY16; +typedef enum SurfaceEndian { + ENDIAN_NONE = 0x0, + ENDIAN_8IN16 = 0x1, + ENDIAN_8IN32 = 0x2, + ENDIAN_8IN64 = 0x3, +} SurfaceEndian; +typedef enum ArrayMode { + ARRAY_LINEAR_GENERAL = 0x0, + ARRAY_LINEAR_ALIGNED = 0x1, + ARRAY_1D_TILED_THIN1 = 0x2, + ARRAY_1D_TILED_THICK = 0x3, + ARRAY_2D_TILED_THIN1 = 0x4, + ARRAY_PRT_TILED_THIN1 = 0x5, + ARRAY_PRT_2D_TILED_THIN1 = 0x6, + ARRAY_2D_TILED_THICK = 0x7, + ARRAY_2D_TILED_XTHICK = 0x8, + ARRAY_PRT_TILED_THICK = 0x9, + ARRAY_PRT_2D_TILED_THICK = 0xa, + ARRAY_PRT_3D_TILED_THIN1 = 0xb, + ARRAY_3D_TILED_THIN1 = 0xc, + ARRAY_3D_TILED_THICK = 0xd, + ARRAY_3D_TILED_XTHICK = 0xe, + ARRAY_PRT_3D_TILED_THICK = 0xf, +} ArrayMode; +typedef enum PipeTiling { + CONFIG_1_PIPE = 0x0, + CONFIG_2_PIPE = 0x1, + CONFIG_4_PIPE = 0x2, + CONFIG_8_PIPE = 0x3, +} PipeTiling; +typedef enum BankTiling { + CONFIG_4_BANK = 0x0, + CONFIG_8_BANK = 0x1, +} BankTiling; +typedef enum GroupInterleave { + CONFIG_256B_GROUP = 0x0, + CONFIG_512B_GROUP = 0x1, +} GroupInterleave; +typedef enum RowTiling { + CONFIG_1KB_ROW = 0x0, + CONFIG_2KB_ROW = 0x1, + CONFIG_4KB_ROW = 0x2, + CONFIG_8KB_ROW = 0x3, + CONFIG_1KB_ROW_OPT = 0x4, + CONFIG_2KB_ROW_OPT = 0x5, + CONFIG_4KB_ROW_OPT = 0x6, + CONFIG_8KB_ROW_OPT = 0x7, +} RowTiling; +typedef enum BankSwapBytes { + CONFIG_128B_SWAPS = 0x0, + CONFIG_256B_SWAPS = 0x1, + CONFIG_512B_SWAPS = 0x2, + CONFIG_1KB_SWAPS = 0x3, +} BankSwapBytes; +typedef enum SampleSplitBytes { + CONFIG_1KB_SPLIT = 0x0, + CONFIG_2KB_SPLIT = 0x1, + CONFIG_4KB_SPLIT = 0x2, + CONFIG_8KB_SPLIT = 0x3, +} SampleSplitBytes; +typedef enum NumPipes { + ADDR_CONFIG_1_PIPE = 0x0, + ADDR_CONFIG_2_PIPE = 0x1, + ADDR_CONFIG_4_PIPE = 0x2, + ADDR_CONFIG_8_PIPE = 0x3, +} NumPipes; +typedef enum PipeInterleaveSize { + ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0, + ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1, +} PipeInterleaveSize; +typedef enum BankInterleaveSize { + ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0, + ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1, + ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2, + ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3, +} BankInterleaveSize; +typedef enum NumShaderEngines { + ADDR_CONFIG_1_SHADER_ENGINE = 0x0, + ADDR_CONFIG_2_SHADER_ENGINE = 0x1, +} NumShaderEngines; +typedef enum ShaderEngineTileSize { + ADDR_CONFIG_SE_TILE_16 = 0x0, + ADDR_CONFIG_SE_TILE_32 = 0x1, +} ShaderEngineTileSize; +typedef enum NumGPUs { + ADDR_CONFIG_1_GPU = 0x0, + ADDR_CONFIG_2_GPU = 0x1, + ADDR_CONFIG_4_GPU = 0x2, +} NumGPUs; +typedef enum MultiGPUTileSize { + ADDR_CONFIG_GPU_TILE_16 = 0x0, + ADDR_CONFIG_GPU_TILE_32 = 0x1, + ADDR_CONFIG_GPU_TILE_64 = 0x2, + ADDR_CONFIG_GPU_TILE_128 = 0x3, +} MultiGPUTileSize; +typedef enum RowSize { + ADDR_CONFIG_1KB_ROW = 0x0, + ADDR_CONFIG_2KB_ROW = 0x1, + ADDR_CONFIG_4KB_ROW = 0x2, +} RowSize; +typedef enum NumLowerPipes { + ADDR_CONFIG_1_LOWER_PIPES = 0x0, + ADDR_CONFIG_2_LOWER_PIPES = 0x1, +} NumLowerPipes; +typedef enum ColorTransform { + DCC_CT_AUTO = 0x0, + DCC_CT_NONE = 0x1, + ABGR_TO_A_BG_G_RB = 0x2, + BGRA_TO_BG_G_RB_A = 0x3, +} ColorTransform; +typedef enum CompareRef { + REF_NEVER = 0x0, + REF_LESS = 0x1, + REF_EQUAL = 0x2, + REF_LEQUAL = 0x3, + REF_GREATER = 0x4, + REF_NOTEQUAL = 0x5, + REF_GEQUAL = 0x6, + REF_ALWAYS = 0x7, +} CompareRef; +typedef enum ReadSize { + READ_256_BITS = 0x0, + READ_512_BITS = 0x1, +} ReadSize; +typedef enum DepthFormat { + DEPTH_INVALID = 0x0, + DEPTH_16 = 0x1, + DEPTH_X8_24 = 0x2, + DEPTH_8_24 = 0x3, + DEPTH_X8_24_FLOAT = 0x4, + DEPTH_8_24_FLOAT = 0x5, + DEPTH_32_FLOAT = 0x6, + DEPTH_X24_8_32_FLOAT = 0x7, +} DepthFormat; +typedef enum ZFormat { + Z_INVALID = 0x0, + Z_16 = 0x1, + Z_24 = 0x2, + Z_32_FLOAT = 0x3, +} ZFormat; +typedef enum StencilFormat { + STENCIL_INVALID = 0x0, + STENCIL_8 = 0x1, +} StencilFormat; +typedef enum CmaskMode { + CMASK_CLEAR_NONE = 0x0, + CMASK_CLEAR_ONE = 0x1, + CMASK_CLEAR_ALL = 0x2, + CMASK_ANY_EXPANDED = 0x3, + CMASK_ALPHA0_FRAG1 = 0x4, + CMASK_ALPHA0_FRAG2 = 0x5, + CMASK_ALPHA0_FRAG4 = 0x6, + CMASK_ALPHA0_FRAGS = 0x7, + CMASK_ALPHA1_FRAG1 = 0x8, + CMASK_ALPHA1_FRAG2 = 0x9, + CMASK_ALPHA1_FRAG4 = 0xa, + CMASK_ALPHA1_FRAGS = 0xb, + CMASK_ALPHAX_FRAG1 = 0xc, + CMASK_ALPHAX_FRAG2 = 0xd, + CMASK_ALPHAX_FRAG4 = 0xe, + CMASK_ALPHAX_FRAGS = 0xf, +} CmaskMode; +typedef enum QuadExportFormat { + EXPORT_UNUSED = 0x0, + EXPORT_32_R = 0x1, + EXPORT_32_GR = 0x2, + EXPORT_32_AR = 0x3, + EXPORT_FP16_ABGR = 0x4, + EXPORT_UNSIGNED16_ABGR = 0x5, + EXPORT_SIGNED16_ABGR = 0x6, + EXPORT_32_ABGR = 0x7, + EXPORT_32BPP_8PIX = 0x8, + EXPORT_16_16_UNSIGNED_8PIX = 0x9, + EXPORT_16_16_SIGNED_8PIX = 0xa, + EXPORT_16_16_FLOAT_8PIX = 0xb, +} QuadExportFormat; +typedef enum QuadExportFormatOld { + EXPORT_4P_32BPC_ABGR = 0x0, + EXPORT_4P_16BPC_ABGR = 0x1, + EXPORT_4P_32BPC_GR = 0x2, + EXPORT_4P_32BPC_AR = 0x3, + EXPORT_2P_32BPC_ABGR = 0x4, + EXPORT_8P_32BPC_R = 0x5, +} QuadExportFormatOld; +typedef enum ColorFormat { + COLOR_INVALID = 0x0, + COLOR_8 = 0x1, + COLOR_16 = 0x2, + COLOR_8_8 = 0x3, + COLOR_32 = 0x4, + COLOR_16_16 = 0x5, + COLOR_10_11_11 = 0x6, + COLOR_11_11_10 = 0x7, + COLOR_10_10_10_2 = 0x8, + COLOR_2_10_10_10 = 0x9, + COLOR_8_8_8_8 = 0xa, + COLOR_32_32 = 0xb, + COLOR_16_16_16_16 = 0xc, + COLOR_RESERVED_13 = 0xd, + COLOR_32_32_32_32 = 0xe, + COLOR_RESERVED_15 = 0xf, + COLOR_5_6_5 = 0x10, + COLOR_1_5_5_5 = 0x11, + COLOR_5_5_5_1 = 0x12, + COLOR_4_4_4_4 = 0x13, + COLOR_8_24 = 0x14, + COLOR_24_8 = 0x15, + COLOR_X24_8_32_FLOAT = 0x16, + COLOR_RESERVED_23 = 0x17, + COLOR_RESERVED_24 = 0x18, + COLOR_RESERVED_25 = 0x19, + COLOR_RESERVED_26 = 0x1a, + COLOR_RESERVED_27 = 0x1b, + COLOR_RESERVED_28 = 0x1c, + COLOR_RESERVED_29 = 0x1d, + COLOR_RESERVED_30 = 0x1e, +} ColorFormat; +typedef enum SurfaceFormat { + FMT_INVALID = 0x0, + FMT_8 = 0x1, + FMT_16 = 0x2, + FMT_8_8 = 0x3, + FMT_32 = 0x4, + FMT_16_16 = 0x5, + FMT_10_11_11 = 0x6, + FMT_11_11_10 = 0x7, + FMT_10_10_10_2 = 0x8, + FMT_2_10_10_10 = 0x9, + FMT_8_8_8_8 = 0xa, + FMT_32_32 = 0xb, + FMT_16_16_16_16 = 0xc, + FMT_32_32_32 = 0xd, + FMT_32_32_32_32 = 0xe, + FMT_RESERVED_4 = 0xf, + FMT_5_6_5 = 0x10, + FMT_1_5_5_5 = 0x11, + FMT_5_5_5_1 = 0x12, + FMT_4_4_4_4 = 0x13, + FMT_8_24 = 0x14, + FMT_24_8 = 0x15, + FMT_X24_8_32_FLOAT = 0x16, + FMT_RESERVED_33 = 0x17, + FMT_11_11_10_FLOAT = 0x18, + FMT_16_FLOAT = 0x19, + FMT_32_FLOAT = 0x1a, + FMT_16_16_FLOAT = 0x1b, + FMT_8_24_FLOAT = 0x1c, + FMT_24_8_FLOAT = 0x1d, + FMT_32_32_FLOAT = 0x1e, + FMT_10_11_11_FLOAT = 0x1f, + FMT_16_16_16_16_FLOAT = 0x20, + FMT_3_3_2 = 0x21, + FMT_6_5_5 = 0x22, + FMT_32_32_32_32_FLOAT = 0x23, + FMT_RESERVED_36 = 0x24, + FMT_1 = 0x25, + FMT_1_REVERSED = 0x26, + FMT_GB_GR = 0x27, + FMT_BG_RG = 0x28, + FMT_32_AS_8 = 0x29, + FMT_32_AS_8_8 = 0x2a, + FMT_5_9_9_9_SHAREDEXP = 0x2b, + FMT_8_8_8 = 0x2c, + FMT_16_16_16 = 0x2d, + FMT_16_16_16_FLOAT = 0x2e, + FMT_4_4 = 0x2f, + FMT_32_32_32_FLOAT = 0x30, + FMT_BC1 = 0x31, + FMT_BC2 = 0x32, + FMT_BC3 = 0x33, + FMT_BC4 = 0x34, + FMT_BC5 = 0x35, + FMT_BC6 = 0x36, + FMT_BC7 = 0x37, + FMT_32_AS_32_32_32_32 = 0x38, + FMT_APC3 = 0x39, + FMT_APC4 = 0x3a, + FMT_APC5 = 0x3b, + FMT_APC6 = 0x3c, + FMT_APC7 = 0x3d, + FMT_CTX1 = 0x3e, + FMT_RESERVED_63 = 0x3f, +} SurfaceFormat; +typedef enum BUF_DATA_FORMAT { + BUF_DATA_FORMAT_INVALID = 0x0, + BUF_DATA_FORMAT_8 = 0x1, + BUF_DATA_FORMAT_16 = 0x2, + BUF_DATA_FORMAT_8_8 = 0x3, + BUF_DATA_FORMAT_32 = 0x4, + BUF_DATA_FORMAT_16_16 = 0x5, + BUF_DATA_FORMAT_10_11_11 = 0x6, + BUF_DATA_FORMAT_11_11_10 = 0x7, + BUF_DATA_FORMAT_10_10_10_2 = 0x8, + BUF_DATA_FORMAT_2_10_10_10 = 0x9, + BUF_DATA_FORMAT_8_8_8_8 = 0xa, + BUF_DATA_FORMAT_32_32 = 0xb, + BUF_DATA_FORMAT_16_16_16_16 = 0xc, + BUF_DATA_FORMAT_32_32_32 = 0xd, + BUF_DATA_FORMAT_32_32_32_32 = 0xe, + BUF_DATA_FORMAT_RESERVED_15 = 0xf, +} BUF_DATA_FORMAT; +typedef enum IMG_DATA_FORMAT { + IMG_DATA_FORMAT_INVALID = 0x0, + IMG_DATA_FORMAT_8 = 0x1, + IMG_DATA_FORMAT_16 = 0x2, + IMG_DATA_FORMAT_8_8 = 0x3, + IMG_DATA_FORMAT_32 = 0x4, + IMG_DATA_FORMAT_16_16 = 0x5, + IMG_DATA_FORMAT_10_11_11 = 0x6, + IMG_DATA_FORMAT_11_11_10 = 0x7, + IMG_DATA_FORMAT_10_10_10_2 = 0x8, + IMG_DATA_FORMAT_2_10_10_10 = 0x9, + IMG_DATA_FORMAT_8_8_8_8 = 0xa, + IMG_DATA_FORMAT_32_32 = 0xb, + IMG_DATA_FORMAT_16_16_16_16 = 0xc, + IMG_DATA_FORMAT_32_32_32 = 0xd, + IMG_DATA_FORMAT_32_32_32_32 = 0xe, + IMG_DATA_FORMAT_16_AS_32_32 = 0xf, + IMG_DATA_FORMAT_5_6_5 = 0x10, + IMG_DATA_FORMAT_1_5_5_5 = 0x11, + IMG_DATA_FORMAT_5_5_5_1 = 0x12, + IMG_DATA_FORMAT_4_4_4_4 = 0x13, + IMG_DATA_FORMAT_8_24 = 0x14, + IMG_DATA_FORMAT_24_8 = 0x15, + IMG_DATA_FORMAT_X24_8_32 = 0x16, + IMG_DATA_FORMAT_8_AS_8_8_8_8 = 0x17, + IMG_DATA_FORMAT_ETC2_RGB = 0x18, + IMG_DATA_FORMAT_ETC2_RGBA = 0x19, + IMG_DATA_FORMAT_ETC2_R = 0x1a, + IMG_DATA_FORMAT_ETC2_RG = 0x1b, + IMG_DATA_FORMAT_ETC2_RGBA1 = 0x1c, + IMG_DATA_FORMAT_RESERVED_29 = 0x1d, + IMG_DATA_FORMAT_RESERVED_30 = 0x1e, + IMG_DATA_FORMAT_RESERVED_31 = 0x1f, + IMG_DATA_FORMAT_GB_GR = 0x20, + IMG_DATA_FORMAT_BG_RG = 0x21, + IMG_DATA_FORMAT_5_9_9_9 = 0x22, + IMG_DATA_FORMAT_BC1 = 0x23, + IMG_DATA_FORMAT_BC2 = 0x24, + IMG_DATA_FORMAT_BC3 = 0x25, + IMG_DATA_FORMAT_BC4 = 0x26, + IMG_DATA_FORMAT_BC5 = 0x27, + IMG_DATA_FORMAT_BC6 = 0x28, + IMG_DATA_FORMAT_BC7 = 0x29, + IMG_DATA_FORMAT_16_AS_16_16_16_16 = 0x2a, + IMG_DATA_FORMAT_16_AS_32_32_32_32 = 0x2b, + IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c, + IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d, + IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e, + IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f, + IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30, + IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31, + IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32, + IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33, + IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34, + IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35, + IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36, + IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37, + IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38, + IMG_DATA_FORMAT_4_4 = 0x39, + IMG_DATA_FORMAT_6_5_5 = 0x3a, + IMG_DATA_FORMAT_1 = 0x3b, + IMG_DATA_FORMAT_1_REVERSED = 0x3c, + IMG_DATA_FORMAT_8_AS_32 = 0x3d, + IMG_DATA_FORMAT_8_AS_32_32 = 0x3e, + IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f, +} IMG_DATA_FORMAT; +typedef enum BUF_NUM_FORMAT { + BUF_NUM_FORMAT_UNORM = 0x0, + BUF_NUM_FORMAT_SNORM = 0x1, + BUF_NUM_FORMAT_USCALED = 0x2, + BUF_NUM_FORMAT_SSCALED = 0x3, + BUF_NUM_FORMAT_UINT = 0x4, + BUF_NUM_FORMAT_SINT = 0x5, + BUF_NUM_FORMAT_RESERVED_6 = 0x6, + BUF_NUM_FORMAT_FLOAT = 0x7, +} BUF_NUM_FORMAT; +typedef enum IMG_NUM_FORMAT { + IMG_NUM_FORMAT_UNORM = 0x0, + IMG_NUM_FORMAT_SNORM = 0x1, + IMG_NUM_FORMAT_USCALED = 0x2, + IMG_NUM_FORMAT_SSCALED = 0x3, + IMG_NUM_FORMAT_UINT = 0x4, + IMG_NUM_FORMAT_SINT = 0x5, + IMG_NUM_FORMAT_RESERVED_6 = 0x6, + IMG_NUM_FORMAT_FLOAT = 0x7, + IMG_NUM_FORMAT_RESERVED_8 = 0x8, + IMG_NUM_FORMAT_SRGB = 0x9, + IMG_NUM_FORMAT_RESERVED_10 = 0xa, + IMG_NUM_FORMAT_RESERVED_11 = 0xb, + IMG_NUM_FORMAT_RESERVED_12 = 0xc, + IMG_NUM_FORMAT_RESERVED_13 = 0xd, + IMG_NUM_FORMAT_RESERVED_14 = 0xe, + IMG_NUM_FORMAT_RESERVED_15 = 0xf, +} IMG_NUM_FORMAT; +typedef enum TileType { + ARRAY_COLOR_TILE = 0x0, + ARRAY_DEPTH_TILE = 0x1, +} TileType; +typedef enum NonDispTilingOrder { + ADDR_SURF_MICRO_TILING_DISPLAY = 0x0, + ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, +} NonDispTilingOrder; +typedef enum MicroTileMode { + ADDR_SURF_DISPLAY_MICRO_TILING = 0x0, + ADDR_SURF_THIN_MICRO_TILING = 0x1, + ADDR_SURF_DEPTH_MICRO_TILING = 0x2, + ADDR_SURF_ROTATED_MICRO_TILING = 0x3, + ADDR_SURF_THICK_MICRO_TILING = 0x4, +} MicroTileMode; +typedef enum TileSplit { + ADDR_SURF_TILE_SPLIT_64B = 0x0, + ADDR_SURF_TILE_SPLIT_128B = 0x1, + ADDR_SURF_TILE_SPLIT_256B = 0x2, + ADDR_SURF_TILE_SPLIT_512B = 0x3, + ADDR_SURF_TILE_SPLIT_1KB = 0x4, + ADDR_SURF_TILE_SPLIT_2KB = 0x5, + ADDR_SURF_TILE_SPLIT_4KB = 0x6, +} TileSplit; +typedef enum SampleSplit { + ADDR_SURF_SAMPLE_SPLIT_1 = 0x0, + ADDR_SURF_SAMPLE_SPLIT_2 = 0x1, + ADDR_SURF_SAMPLE_SPLIT_4 = 0x2, + ADDR_SURF_SAMPLE_SPLIT_8 = 0x3, +} SampleSplit; +typedef enum PipeConfig { + ADDR_SURF_P2 = 0x0, + ADDR_SURF_P2_RESERVED0 = 0x1, + ADDR_SURF_P2_RESERVED1 = 0x2, + ADDR_SURF_P2_RESERVED2 = 0x3, + ADDR_SURF_P4_8x16 = 0x4, + ADDR_SURF_P4_16x16 = 0x5, + ADDR_SURF_P4_16x32 = 0x6, + ADDR_SURF_P4_32x32 = 0x7, + ADDR_SURF_P8_16x16_8x16 = 0x8, + ADDR_SURF_P8_16x32_8x16 = 0x9, + ADDR_SURF_P8_32x32_8x16 = 0xa, + ADDR_SURF_P8_16x32_16x16 = 0xb, + ADDR_SURF_P8_32x32_16x16 = 0xc, + ADDR_SURF_P8_32x32_16x32 = 0xd, + ADDR_SURF_P8_32x64_32x32 = 0xe, + ADDR_SURF_P8_RESERVED0 = 0xf, + ADDR_SURF_P16_32x32_8x16 = 0x10, + ADDR_SURF_P16_32x32_16x16 = 0x11, +} PipeConfig; +typedef enum NumBanks { + ADDR_SURF_2_BANK = 0x0, + ADDR_SURF_4_BANK = 0x1, + ADDR_SURF_8_BANK = 0x2, + ADDR_SURF_16_BANK = 0x3, +} NumBanks; +typedef enum BankWidth { + ADDR_SURF_BANK_WIDTH_1 = 0x0, + ADDR_SURF_BANK_WIDTH_2 = 0x1, + ADDR_SURF_BANK_WIDTH_4 = 0x2, + ADDR_SURF_BANK_WIDTH_8 = 0x3, +} BankWidth; +typedef enum BankHeight { + ADDR_SURF_BANK_HEIGHT_1 = 0x0, + ADDR_SURF_BANK_HEIGHT_2 = 0x1, + ADDR_SURF_BANK_HEIGHT_4 = 0x2, + ADDR_SURF_BANK_HEIGHT_8 = 0x3, +} BankHeight; +typedef enum BankWidthHeight { + ADDR_SURF_BANK_WH_1 = 0x0, + ADDR_SURF_BANK_WH_2 = 0x1, + ADDR_SURF_BANK_WH_4 = 0x2, + ADDR_SURF_BANK_WH_8 = 0x3, +} BankWidthHeight; +typedef enum MacroTileAspect { + ADDR_SURF_MACRO_ASPECT_1 = 0x0, + ADDR_SURF_MACRO_ASPECT_2 = 0x1, + ADDR_SURF_MACRO_ASPECT_4 = 0x2, + ADDR_SURF_MACRO_ASPECT_8 = 0x3, +} MacroTileAspect; +typedef enum GATCL1RequestType { + GATCL1_TYPE_NORMAL = 0x0, + GATCL1_TYPE_SHOOTDOWN = 0x1, + GATCL1_TYPE_BYPASS = 0x2, +} GATCL1RequestType; +typedef enum TCC_CACHE_POLICIES { + TCC_CACHE_POLICY_LRU = 0x0, + TCC_CACHE_POLICY_STREAM = 0x1, +} TCC_CACHE_POLICIES; +typedef enum MTYPE { + MTYPE_NC_NV = 0x0, + MTYPE_NC = 0x1, + MTYPE_CC = 0x2, + MTYPE_UC = 0x3, +} MTYPE; +typedef enum PERFMON_COUNTER_MODE { + PERFMON_COUNTER_MODE_ACCUM = 0x0, + PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1, + PERFMON_COUNTER_MODE_MAX = 0x2, + PERFMON_COUNTER_MODE_DIRTY = 0x3, + PERFMON_COUNTER_MODE_SAMPLE = 0x4, + PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5, + PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6, + PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7, + PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8, + PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9, + PERFMON_COUNTER_MODE_RESERVED = 0xf, +} PERFMON_COUNTER_MODE; +typedef enum PERFMON_SPM_MODE { + PERFMON_SPM_MODE_OFF = 0x0, + PERFMON_SPM_MODE_16BIT_CLAMP = 0x1, + PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2, + PERFMON_SPM_MODE_32BIT_CLAMP = 0x3, + PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4, + PERFMON_SPM_MODE_RESERVED_5 = 0x5, + PERFMON_SPM_MODE_RESERVED_6 = 0x6, + PERFMON_SPM_MODE_RESERVED_7 = 0x7, + PERFMON_SPM_MODE_TEST_MODE_0 = 0x8, + PERFMON_SPM_MODE_TEST_MODE_1 = 0x9, + PERFMON_SPM_MODE_TEST_MODE_2 = 0xa, +} PERFMON_SPM_MODE; +typedef enum SurfaceTiling { + ARRAY_LINEAR = 0x0, + ARRAY_TILED = 0x1, +} SurfaceTiling; +typedef enum SurfaceArray { + ARRAY_1D = 0x0, + ARRAY_2D = 0x1, + ARRAY_3D = 0x2, + ARRAY_3D_SLICE = 0x3, +} SurfaceArray; +typedef enum ColorArray { + ARRAY_2D_ALT_COLOR = 0x0, + ARRAY_2D_COLOR = 0x1, + ARRAY_3D_SLICE_COLOR = 0x3, +} ColorArray; +typedef enum DepthArray { + ARRAY_2D_ALT_DEPTH = 0x0, + ARRAY_2D_DEPTH = 0x1, +} DepthArray; +typedef enum ENUM_NUM_SIMD_PER_CU { + NUM_SIMD_PER_CU = 0x4, +} ENUM_NUM_SIMD_PER_CU; +typedef enum MEM_PWR_FORCE_CTRL { + NO_FORCE_REQUEST = 0x0, + FORCE_LIGHT_SLEEP_REQUEST = 0x1, + FORCE_DEEP_SLEEP_REQUEST = 0x2, + FORCE_SHUT_DOWN_REQUEST = 0x3, +} MEM_PWR_FORCE_CTRL; +typedef enum MEM_PWR_FORCE_CTRL2 { + NO_FORCE_REQ = 0x0, + FORCE_LIGHT_SLEEP_REQ = 0x1, +} MEM_PWR_FORCE_CTRL2; +typedef enum MEM_PWR_DIS_CTRL { + ENABLE_MEM_PWR_CTRL = 0x0, + DISABLE_MEM_PWR_CTRL = 0x1, +} MEM_PWR_DIS_CTRL; +typedef enum MEM_PWR_SEL_CTRL { + DYNAMIC_SHUT_DOWN_ENABLE = 0x0, + DYNAMIC_DEEP_SLEEP_ENABLE = 0x1, + DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2, +} MEM_PWR_SEL_CTRL; +typedef enum MEM_PWR_SEL_CTRL2 { + DYNAMIC_DEEP_SLEEP_EN = 0x0, + DYNAMIC_LIGHT_SLEEP_EN = 0x1, +} MEM_PWR_SEL_CTRL2; + +#endif /* GFX_8_1_ENUM_H */ diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h new file mode 100644 index 000000000000..397705a6b3a2 --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h @@ -0,0 +1,21368 @@ +/* + * GFX_8_1 Register documentation + * + * Copyright (C) 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN + * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef GFX_8_1_SH_MASK_H +#define GFX_8_1_SH_MASK_H + +#define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff +#define CB_BLEND_RED__BLEND_RED__SHIFT 0x0 +#define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff +#define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0 +#define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff +#define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0 +#define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff +#define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE_MASK 0x2 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_MRT_SHARING_DISABLE__SHIFT 0x1 +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK_MASK 0x7c +#define CB_DCC_CONTROL__OVERWRITE_COMBINER_WATERMARK__SHIFT 0x2 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD_MASK 0x1 +#define CB_COLOR_CONTROL__DISABLE_DUAL_QUAD__SHIFT 0x0 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8 +#define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3 +#define CB_COLOR_CONTROL__MODE_MASK 0x70 +#define CB_COLOR_CONTROL__MODE__SHIFT 0x4 +#define CB_COLOR_CONTROL__ROP3_MASK 0xff0000 +#define CB_COLOR_CONTROL__ROP3__SHIFT 0x10 +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND0_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND0_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND0_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND0_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND0_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND0_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND0_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND1_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND1_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND1_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND1_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND1_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND1_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND1_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND1_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND1_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND1_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND1_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND2_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND2_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND2_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND2_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND2_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND2_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND2_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND2_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND2_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND2_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND2_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND3_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND3_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND3_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND3_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND3_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND3_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND3_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND3_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND3_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND3_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND3_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND4_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND4_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND4_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND4_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND4_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND4_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND4_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND4_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND4_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND4_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND4_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND5_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND5_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND5_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND5_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND5_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND5_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND5_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND5_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND5_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND5_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND5_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND6_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND6_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND6_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND6_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND6_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND6_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND6_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND6_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND6_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND6_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND6_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND_MASK 0x1f +#define CB_BLEND7_CONTROL__COLOR_SRCBLEND__SHIFT 0x0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN_MASK 0xe0 +#define CB_BLEND7_CONTROL__COLOR_COMB_FCN__SHIFT 0x5 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND_MASK 0x1f00 +#define CB_BLEND7_CONTROL__COLOR_DESTBLEND__SHIFT 0x8 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND_MASK 0x1f0000 +#define CB_BLEND7_CONTROL__ALPHA_SRCBLEND__SHIFT 0x10 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN_MASK 0xe00000 +#define CB_BLEND7_CONTROL__ALPHA_COMB_FCN__SHIFT 0x15 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000 +#define CB_BLEND7_CONTROL__ALPHA_DESTBLEND__SHIFT 0x18 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND_MASK 0x20000000 +#define CB_BLEND7_CONTROL__SEPARATE_ALPHA_BLEND__SHIFT 0x1d +#define CB_BLEND7_CONTROL__ENABLE_MASK 0x40000000 +#define CB_BLEND7_CONTROL__ENABLE__SHIFT 0x1e +#define CB_BLEND7_CONTROL__DISABLE_ROP3_MASK 0x80000000 +#define CB_BLEND7_CONTROL__DISABLE_ROP3__SHIFT 0x1f +#define CB_COLOR0_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR0_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR0_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR1_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR1_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR1_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR2_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR2_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR2_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR3_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR3_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR3_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR4_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR4_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR4_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR5_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR5_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR5_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR6_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR6_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR6_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR7_PITCH__TILE_MAX_MASK 0x7ff +#define CB_COLOR7_PITCH__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX_MASK 0x7ff00000 +#define CB_COLOR7_PITCH__FMASK_TILE_MAX__SHIFT 0x14 +#define CB_COLOR0_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR0_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR1_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR2_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR3_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR4_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR5_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR6_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR7_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR0_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR0_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR0_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR1_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR1_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR1_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR1_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR2_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR2_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR2_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR2_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR3_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR3_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR3_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR3_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR4_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR4_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR4_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR4_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR5_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR5_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR5_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR5_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR6_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR6_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR6_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR6_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR7_VIEW__SLICE_START_MASK 0x7ff +#define CB_COLOR7_VIEW__SLICE_START__SHIFT 0x0 +#define CB_COLOR7_VIEW__SLICE_MAX_MASK 0xffe000 +#define CB_COLOR7_VIEW__SLICE_MAX__SHIFT 0xd +#define CB_COLOR0_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR0_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR0_INFO__FORMAT_MASK 0x7c +#define CB_COLOR0_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR0_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR0_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR0_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR0_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR0_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR0_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR0_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR0_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR0_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR0_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR0_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR0_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR0_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR0_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR0_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR0_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR0_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR0_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR0_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR0_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR0_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR0_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR0_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR0_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR0_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR0_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR1_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR1_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR1_INFO__FORMAT_MASK 0x7c +#define CB_COLOR1_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR1_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR1_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR1_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR1_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR1_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR1_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR1_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR1_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR1_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR1_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR1_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR1_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR1_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR1_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR1_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR1_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR1_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR1_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR1_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR1_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR1_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR1_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR1_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR1_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR1_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR1_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR2_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR2_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR2_INFO__FORMAT_MASK 0x7c +#define CB_COLOR2_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR2_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR2_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR2_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR2_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR2_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR2_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR2_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR2_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR2_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR2_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR2_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR2_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR2_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR2_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR2_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR2_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR2_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR2_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR2_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR2_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR2_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR2_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR2_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR2_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR2_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR2_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR3_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR3_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR3_INFO__FORMAT_MASK 0x7c +#define CB_COLOR3_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR3_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR3_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR3_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR3_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR3_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR3_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR3_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR3_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR3_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR3_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR3_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR3_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR3_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR3_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR3_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR3_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR3_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR3_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR3_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR3_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR3_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR3_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR3_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR3_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR3_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR3_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR4_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR4_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR4_INFO__FORMAT_MASK 0x7c +#define CB_COLOR4_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR4_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR4_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR4_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR4_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR4_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR4_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR4_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR4_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR4_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR4_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR4_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR4_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR4_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR4_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR4_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR4_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR4_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR4_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR4_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR4_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR4_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR4_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR4_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR4_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR4_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR4_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR5_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR5_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR5_INFO__FORMAT_MASK 0x7c +#define CB_COLOR5_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR5_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR5_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR5_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR5_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR5_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR5_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR5_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR5_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR5_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR5_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR5_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR5_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR5_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR5_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR5_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR5_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR5_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR5_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR5_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR5_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR5_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR5_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR5_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR5_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR5_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR5_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR6_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR6_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR6_INFO__FORMAT_MASK 0x7c +#define CB_COLOR6_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR6_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR6_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR6_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR6_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR6_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR6_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR6_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR6_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR6_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR6_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR6_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR6_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR6_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR6_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR6_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR6_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR6_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR6_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR6_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR6_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR6_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR6_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR6_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR6_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR6_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR6_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR7_INFO__ENDIAN_MASK 0x3 +#define CB_COLOR7_INFO__ENDIAN__SHIFT 0x0 +#define CB_COLOR7_INFO__FORMAT_MASK 0x7c +#define CB_COLOR7_INFO__FORMAT__SHIFT 0x2 +#define CB_COLOR7_INFO__LINEAR_GENERAL_MASK 0x80 +#define CB_COLOR7_INFO__LINEAR_GENERAL__SHIFT 0x7 +#define CB_COLOR7_INFO__NUMBER_TYPE_MASK 0x700 +#define CB_COLOR7_INFO__NUMBER_TYPE__SHIFT 0x8 +#define CB_COLOR7_INFO__COMP_SWAP_MASK 0x1800 +#define CB_COLOR7_INFO__COMP_SWAP__SHIFT 0xb +#define CB_COLOR7_INFO__FAST_CLEAR_MASK 0x2000 +#define CB_COLOR7_INFO__FAST_CLEAR__SHIFT 0xd +#define CB_COLOR7_INFO__COMPRESSION_MASK 0x4000 +#define CB_COLOR7_INFO__COMPRESSION__SHIFT 0xe +#define CB_COLOR7_INFO__BLEND_CLAMP_MASK 0x8000 +#define CB_COLOR7_INFO__BLEND_CLAMP__SHIFT 0xf +#define CB_COLOR7_INFO__BLEND_BYPASS_MASK 0x10000 +#define CB_COLOR7_INFO__BLEND_BYPASS__SHIFT 0x10 +#define CB_COLOR7_INFO__SIMPLE_FLOAT_MASK 0x20000 +#define CB_COLOR7_INFO__SIMPLE_FLOAT__SHIFT 0x11 +#define CB_COLOR7_INFO__ROUND_MODE_MASK 0x40000 +#define CB_COLOR7_INFO__ROUND_MODE__SHIFT 0x12 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR_MASK 0x80000 +#define CB_COLOR7_INFO__CMASK_IS_LINEAR__SHIFT 0x13 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST_MASK 0x700000 +#define CB_COLOR7_INFO__BLEND_OPT_DONT_RD_DST__SHIFT 0x14 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL_MASK 0x3800000 +#define CB_COLOR7_INFO__BLEND_OPT_DISCARD_PIXEL__SHIFT 0x17 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE_MASK 0x4000000 +#define CB_COLOR7_INFO__FMASK_COMPRESSION_DISABLE__SHIFT 0x1a +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY_MASK 0x8000000 +#define CB_COLOR7_INFO__FMASK_COMPRESS_1FRAG_ONLY__SHIFT 0x1b +#define CB_COLOR7_INFO__DCC_ENABLE_MASK 0x10000000 +#define CB_COLOR7_INFO__DCC_ENABLE__SHIFT 0x1c +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE_MASK 0x60000000 +#define CB_COLOR7_INFO__CMASK_ADDR_TYPE__SHIFT 0x1d +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR0_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR0_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR0_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR0_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR0_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR0_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR0_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR1_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR1_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR1_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR1_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR1_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR1_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR1_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR2_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR2_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR2_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR2_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR2_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR2_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR2_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR3_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR3_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR3_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR3_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR3_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR3_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR3_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR4_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR4_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR4_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR4_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR4_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR4_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR4_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR5_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR5_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR5_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR5_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR5_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR5_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR5_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR6_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR6_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR6_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR6_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR6_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR6_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR6_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX_MASK 0x1f +#define CB_COLOR7_ATTRIB__TILE_MODE_INDEX__SHIFT 0x0 +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX_MASK 0x3e0 +#define CB_COLOR7_ATTRIB__FMASK_TILE_MODE_INDEX__SHIFT 0x5 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT_MASK 0xc00 +#define CB_COLOR7_ATTRIB__FMASK_BANK_HEIGHT__SHIFT 0xa +#define CB_COLOR7_ATTRIB__NUM_SAMPLES_MASK 0x7000 +#define CB_COLOR7_ATTRIB__NUM_SAMPLES__SHIFT 0xc +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS_MASK 0x18000 +#define CB_COLOR7_ATTRIB__NUM_FRAGMENTS__SHIFT 0xf +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1_MASK 0x20000 +#define CB_COLOR7_ATTRIB__FORCE_DST_ALPHA_1__SHIFT 0x11 +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR0_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR0_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR0_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR0_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR0_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR0_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR0_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR0_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR0_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR1_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR1_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR1_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR1_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR1_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR1_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR1_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR1_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR1_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR2_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR2_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR2_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR2_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR2_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR2_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR2_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR2_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR2_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR3_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR3_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR3_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR3_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR3_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR3_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR3_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR3_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR3_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR4_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR4_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR4_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR4_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR4_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR4_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR4_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR4_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR4_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR5_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR5_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR5_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR5_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR5_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR5_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR5_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR5_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR5_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR6_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR6_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR6_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR6_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR6_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR6_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR6_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR6_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR6_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1 +#define CB_COLOR7_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0 +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE_MASK 0x2 +#define CB_COLOR7_DCC_CONTROL__KEY_CLEAR_ENABLE__SHIFT 0x1 +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE_MASK 0xc +#define CB_COLOR7_DCC_CONTROL__MAX_UNCOMPRESSED_BLOCK_SIZE__SHIFT 0x2 +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE_MASK 0x10 +#define CB_COLOR7_DCC_CONTROL__MIN_COMPRESSED_BLOCK_SIZE__SHIFT 0x4 +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE_MASK 0x60 +#define CB_COLOR7_DCC_CONTROL__MAX_COMPRESSED_BLOCK_SIZE__SHIFT 0x5 +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM_MASK 0x180 +#define CB_COLOR7_DCC_CONTROL__COLOR_TRANSFORM__SHIFT 0x7 +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS_MASK 0x200 +#define CB_COLOR7_DCC_CONTROL__INDEPENDENT_64B_BLOCKS__SHIFT 0x9 +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION_MASK 0x3c00 +#define CB_COLOR7_DCC_CONTROL__LOSSY_RGB_PRECISION__SHIFT 0xa +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION_MASK 0x3c000 +#define CB_COLOR7_DCC_CONTROL__LOSSY_ALPHA_PRECISION__SHIFT 0xe +#define CB_COLOR0_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_CMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_CMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR0_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR1_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR2_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR3_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR4_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR5_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR6_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_CMASK_SLICE__TILE_MAX_MASK 0x3fff +#define CB_COLOR7_CMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_FMASK__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_FMASK__BASE_256B__SHIFT 0x0 +#define CB_COLOR0_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR0_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR1_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR1_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR2_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR2_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR3_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR3_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR4_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR4_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR5_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR5_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR6_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR6_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR7_FMASK_SLICE__TILE_MAX_MASK 0x3fffff +#define CB_COLOR7_FMASK_SLICE__TILE_MAX__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR0_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR1_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR2_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR3_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR4_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR5_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR6_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0_MASK 0xffffffff +#define CB_COLOR7_CLEAR_WORD0__CLEAR_WORD0__SHIFT 0x0 +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR0_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR1_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR2_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR3_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR4_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR5_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR6_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1_MASK 0xffffffff +#define CB_COLOR7_CLEAR_WORD1__CLEAR_WORD1__SHIFT 0x0 +#define CB_COLOR0_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR0_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR1_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR1_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR2_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR2_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR3_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR3_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR4_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR4_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR5_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR5_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR6_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR6_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_COLOR7_DCC_BASE__BASE_256B_MASK 0xffffffff +#define CB_COLOR7_DCC_BASE__BASE_256B__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET0_ENABLE_MASK 0xf +#define CB_TARGET_MASK__TARGET0_ENABLE__SHIFT 0x0 +#define CB_TARGET_MASK__TARGET1_ENABLE_MASK 0xf0 +#define CB_TARGET_MASK__TARGET1_ENABLE__SHIFT 0x4 +#define CB_TARGET_MASK__TARGET2_ENABLE_MASK 0xf00 +#define CB_TARGET_MASK__TARGET2_ENABLE__SHIFT 0x8 +#define CB_TARGET_MASK__TARGET3_ENABLE_MASK 0xf000 +#define CB_TARGET_MASK__TARGET3_ENABLE__SHIFT 0xc +#define CB_TARGET_MASK__TARGET4_ENABLE_MASK 0xf0000 +#define CB_TARGET_MASK__TARGET4_ENABLE__SHIFT 0x10 +#define CB_TARGET_MASK__TARGET5_ENABLE_MASK 0xf00000 +#define CB_TARGET_MASK__TARGET5_ENABLE__SHIFT 0x14 +#define CB_TARGET_MASK__TARGET6_ENABLE_MASK 0xf000000 +#define CB_TARGET_MASK__TARGET6_ENABLE__SHIFT 0x18 +#define CB_TARGET_MASK__TARGET7_ENABLE_MASK 0xf0000000 +#define CB_TARGET_MASK__TARGET7_ENABLE__SHIFT 0x1c +#define CB_SHADER_MASK__OUTPUT0_ENABLE_MASK 0xf +#define CB_SHADER_MASK__OUTPUT0_ENABLE__SHIFT 0x0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE_MASK 0xf0 +#define CB_SHADER_MASK__OUTPUT1_ENABLE__SHIFT 0x4 +#define CB_SHADER_MASK__OUTPUT2_ENABLE_MASK 0xf00 +#define CB_SHADER_MASK__OUTPUT2_ENABLE__SHIFT 0x8 +#define CB_SHADER_MASK__OUTPUT3_ENABLE_MASK 0xf000 +#define CB_SHADER_MASK__OUTPUT3_ENABLE__SHIFT 0xc +#define CB_SHADER_MASK__OUTPUT4_ENABLE_MASK 0xf0000 +#define CB_SHADER_MASK__OUTPUT4_ENABLE__SHIFT 0x10 +#define CB_SHADER_MASK__OUTPUT5_ENABLE_MASK 0xf00000 +#define CB_SHADER_MASK__OUTPUT5_ENABLE__SHIFT 0x14 +#define CB_SHADER_MASK__OUTPUT6_ENABLE_MASK 0xf000000 +#define CB_SHADER_MASK__OUTPUT6_ENABLE__SHIFT 0x18 +#define CB_SHADER_MASK__OUTPUT7_ENABLE_MASK 0xf0000000 +#define CB_SHADER_MASK__OUTPUT7_ENABLE__SHIFT 0x1c +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT_MASK 0xf +#define CB_HW_CONTROL__CM_CACHE_EVICT_POINT__SHIFT 0x0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT_MASK 0x3c0 +#define CB_HW_CONTROL__FC_CACHE_EVICT_POINT__SHIFT 0x6 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT_MASK 0xf000 +#define CB_HW_CONTROL__CC_CACHE_EVICT_POINT__SHIFT 0xc +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE_MASK 0x10000 +#define CB_HW_CONTROL__ALLOW_MRT_WITH_DUAL_SOURCE__SHIFT 0x10 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING_MASK 0x40000 +#define CB_HW_CONTROL__DISABLE_INTNORM_LE11BPC_CLAMPING__SHIFT 0x12 +#define CB_HW_CONTROL__FORCE_NEEDS_DST_MASK 0x80000 +#define CB_HW_CONTROL__FORCE_NEEDS_DST__SHIFT 0x13 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE_MASK 0x100000 +#define CB_HW_CONTROL__FORCE_ALWAYS_TOGGLE__SHIFT 0x14 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST_MASK 0x200000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_RESULT_EQ_DEST__SHIFT 0x15 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK_MASK 0x400000 +#define CB_HW_CONTROL__DISABLE_FULL_WRITE_MASK__SHIFT 0x16 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG_MASK 0x800000 +#define CB_HW_CONTROL__DISABLE_RESOLVE_OPT_FOR_SINGLE_FRAG__SHIFT 0x17 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x1000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x18 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS_MASK 0x2000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x19 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x4000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0x1a +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED_MASK 0x8000000 +#define CB_HW_CONTROL__DISABLE_BLEND_OPT_WHEN_DISABLED_SRCALPHA_IS_USED__SHIFT 0x1b +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT_MASK 0x10000000 +#define CB_HW_CONTROL__PRIORITIZE_FC_WR_OVER_FC_RD_ON_CMASK_CONFLICT__SHIFT 0x1c +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT_MASK 0x20000000 +#define CB_HW_CONTROL__PRIORITIZE_FC_EVICT_OVER_FOP_RD_ON_BANK_CONFLICT__SHIFT 0x1d +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT_MASK 0x40000000 +#define CB_HW_CONTROL__DISABLE_CC_IB_SERIALIZER_STATE_OPT__SHIFT 0x1e +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE_MASK 0x80000000 +#define CB_HW_CONTROL__DISABLE_PIXEL_IN_QUAD_FIX_FOR_LINEAR_SURFACE__SHIFT 0x1f +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS_MASK 0x1f +#define CB_HW_CONTROL_1__CM_CACHE_NUM_TAGS__SHIFT 0x0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS_MASK 0x7e0 +#define CB_HW_CONTROL_1__FC_CACHE_NUM_TAGS__SHIFT 0x5 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS_MASK 0x1f800 +#define CB_HW_CONTROL_1__CC_CACHE_NUM_TAGS__SHIFT 0xb +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH_MASK 0x3fe0000 +#define CB_HW_CONTROL_1__CM_TILE_FIFO_DEPTH__SHIFT 0x11 +#define CB_HW_CONTROL_1__CHICKEN_BITS_MASK 0xfc000000 +#define CB_HW_CONTROL_1__CHICKEN_BITS__SHIFT 0x1a +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH_MASK 0xff +#define CB_HW_CONTROL_2__CC_EVEN_ODD_FIFO_DEPTH__SHIFT 0x0 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH_MASK 0x7f00 +#define CB_HW_CONTROL_2__FC_RDLAT_TILE_FIFO_DEPTH__SHIFT 0x8 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH_MASK 0x7f8000 +#define CB_HW_CONTROL_2__FC_RDLAT_QUAD_FIFO_DEPTH__SHIFT 0xf +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8_MASK 0xf000000 +#define CB_HW_CONTROL_2__DRR_ASSUMED_FIFO_DEPTH_DIV8__SHIFT 0x18 +#define CB_HW_CONTROL_2__CHICKEN_BITS_MASK 0xf0000000 +#define CB_HW_CONTROL_2__CHICKEN_BITS__SHIFT 0x1c +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL_MASK 0x1 +#define CB_HW_CONTROL_3__DISABLE_SLOW_MODE_EMPTY_HALF_QUAD_KILL__SHIFT 0x0 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED_MASK 0x2 +#define CB_HW_CONTROL_3__RAM_ADDRESS_CONFLICTS_DISALLOWED__SHIFT 0x1 +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT_MASK 0x4 +#define CB_HW_CONTROL_3__DISABLE_FAST_CLEAR_FETCH_OPT__SHIFT 0x2 +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP_MASK 0x8 +#define CB_HW_CONTROL_3__DISABLE_QUAD_MARKER_DROP_STOP__SHIFT 0x3 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR_MASK 0x10 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_CAM_CLR__SHIFT 0x4 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM_MASK 0x20 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_OVWR_STATUS_ACCUM__SHIFT 0x5 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING_MASK 0x80 +#define CB_HW_CONTROL_3__DISABLE_CC_CACHE_PANIC_GATING__SHIFT 0x7 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION_MASK 0x100 +#define CB_HW_CONTROL_3__DISABLE_OVERWRITE_COMBINER_TARGET_MASK_VALIDATION__SHIFT 0x8 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS_MASK 0x200 +#define CB_HW_CONTROL_3__SPLIT_ALL_FAST_MODE_TRANSFERS__SHIFT 0x9 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS_MASK 0x400 +#define CB_HW_CONTROL_3__DISABLE_SHADER_BLEND_OPTS__SHIFT 0xa +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION_MASK 0x800 +#define CB_HW_CONTROL_3__DISABLE_CMASK_LAST_QUAD_INSERTION__SHIFT 0xb +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967_MASK 0x1000 +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_511967__SHIFT 0xc +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657_MASK 0x2000 +#define CB_HW_CONTROL_3__DISABLE_ROP3_FIXES_OF_BUG_520657__SHIFT 0xd +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH_MASK 0x1f +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DEPTH__SHIFT 0x0 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE_MASK 0x20 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_DISABLE__SHIFT 0x5 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE_MASK 0x40 +#define CB_DCC_CONFIG__OVERWRITE_COMBINER_CC_POP_DISABLE__SHIFT 0x6 +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH_MASK 0xff00 +#define CB_DCC_CONFIG__FC_RDLAT_KEYID_FIFO_DEPTH__SHIFT 0x8 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH_MASK 0x7f0000 +#define CB_DCC_CONFIG__READ_RETURN_SKID_FIFO_DEPTH__SHIFT 0x10 +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT_MASK 0xf000000 +#define CB_DCC_CONFIG__DCC_CACHE_EVICT_POINT__SHIFT 0x18 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS_MASK 0xf0000000 +#define CB_DCC_CONFIG__DCC_CACHE_NUM_TAGS__SHIFT 0x1c +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE_MASK 0x1 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_ENABLE__SHIFT 0x0 +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL_MASK 0xe +#define CB_PERFCOUNTER_FILTER__OP_FILTER_SEL__SHIFT 0x1 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE_MASK 0x10 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_ENABLE__SHIFT 0x4 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL_MASK 0x3e0 +#define CB_PERFCOUNTER_FILTER__FORMAT_FILTER_SEL__SHIFT 0x5 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE_MASK 0x400 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_ENABLE__SHIFT 0xa +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL_MASK 0x800 +#define CB_PERFCOUNTER_FILTER__CLEAR_FILTER_SEL__SHIFT 0xb +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE_MASK 0x1000 +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_ENABLE__SHIFT 0xc +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL_MASK 0xe000 +#define CB_PERFCOUNTER_FILTER__MRT_FILTER_SEL__SHIFT 0xd +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE_MASK 0x20000 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_ENABLE__SHIFT 0x11 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL_MASK 0x1c0000 +#define CB_PERFCOUNTER_FILTER__NUM_SAMPLES_FILTER_SEL__SHIFT 0x12 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE_MASK 0x200000 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_ENABLE__SHIFT 0x15 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL_MASK 0xc00000 +#define CB_PERFCOUNTER_FILTER__NUM_FRAGMENTS_FILTER_SEL__SHIFT 0x16 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x7fc00 +#define CB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x1ff +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x7fc00 +#define CB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define CB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define CB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff +#define CB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define CB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define CB_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CB_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CB_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CB_DEBUG_BUS_1__CB_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_1__CB_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY_MASK 0x2 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READY__SHIFT 0x1 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB_MASK 0x4 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALID_READYB__SHIFT 0x2 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY_MASK 0x8 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READY__SHIFT 0x3 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB_MASK 0x10 +#define CB_DEBUG_BUS_1__DB_CB_TILE_VALIDB_READYB__SHIFT 0x4 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY_MASK 0x20 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READY__SHIFT 0x5 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB_MASK 0x40 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALID_READYB__SHIFT 0x6 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY_MASK 0x80 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READY__SHIFT 0x7 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB_MASK 0x100 +#define CB_DEBUG_BUS_1__DB_CB_LQUAD_VALIDB_READYB__SHIFT 0x8 +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY_MASK 0x200 +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READY__SHIFT 0x9 +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB_MASK 0x400 +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALID_READYB__SHIFT 0xa +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY_MASK 0x800 +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READY__SHIFT 0xb +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB_MASK 0x1000 +#define CB_DEBUG_BUS_1__CB_TAP_WRREQ_VALIDB_READYB__SHIFT 0xc +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY_MASK 0x2000 +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READY__SHIFT 0xd +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB_MASK 0x4000 +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALID_READYB__SHIFT 0xe +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY_MASK 0x8000 +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READY__SHIFT 0xf +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB_MASK 0x10000 +#define CB_DEBUG_BUS_1__CB_TAP_RDREQ_VALIDB_READYB__SHIFT 0x10 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY_MASK 0x20000 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READY__SHIFT 0x11 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB_MASK 0x40000 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALID_READYB__SHIFT 0x12 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY_MASK 0x80000 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READY__SHIFT 0x13 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB_MASK 0x100000 +#define CB_DEBUG_BUS_1__CM_FC_TILE_VALIDB_READYB__SHIFT 0x14 +#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY_MASK 0x200000 +#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READY__SHIFT 0x15 +#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB_MASK 0x400000 +#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALID_READYB__SHIFT 0x16 +#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY_MASK 0x800000 +#define CB_DEBUG_BUS_1__FC_CLEAR_QUAD_VALIDB_READY__SHIFT 0x17 +#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB_MASK 0x1 +#define CB_DEBUG_BUS_2__FC_CLEAR_QUAD_VALIDB_READYB__SHIFT 0x0 +#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL_MASK 0x2 +#define CB_DEBUG_BUS_2__FC_QUAD_RESIDENCY_STALL__SHIFT 0x1 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY_MASK 0x4 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READY__SHIFT 0x2 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB_MASK 0x8 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALID_READYB__SHIFT 0x3 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY_MASK 0x10 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READY__SHIFT 0x4 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB_MASK 0x20 +#define CB_DEBUG_BUS_2__FC_CC_QUADFRAG_VALIDB_READYB__SHIFT 0x5 +#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY_MASK 0x40 +#define CB_DEBUG_BUS_2__FOP_IN_VALID_READY__SHIFT 0x6 +#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB_MASK 0x80 +#define CB_DEBUG_BUS_2__FOP_IN_VALID_READYB__SHIFT 0x7 +#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY_MASK 0x100 +#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READY__SHIFT 0x8 +#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB_MASK 0x200 +#define CB_DEBUG_BUS_2__FOP_IN_VALIDB_READYB__SHIFT 0x9 +#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL_MASK 0x400 +#define CB_DEBUG_BUS_2__FOP_FMASK_RAW_STALL__SHIFT 0xa +#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL_MASK 0x800 +#define CB_DEBUG_BUS_2__FOP_FMASK_BYPASS_STALL__SHIFT 0xb +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY_MASK 0x1000 +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READY__SHIFT 0xc +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB_MASK 0x2000 +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALID_READYB__SHIFT 0xd +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY_MASK 0x4000 +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READY__SHIFT 0xe +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB_MASK 0x8000 +#define CB_DEBUG_BUS_2__CC_IB_TB_FRAG_VALIDB_READYB__SHIFT 0xf +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY_MASK 0x10000 +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READY__SHIFT 0x10 +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB_MASK 0x20000 +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALID_READYB__SHIFT 0x11 +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY_MASK 0x40000 +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READY__SHIFT 0x12 +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB_MASK 0x80000 +#define CB_DEBUG_BUS_2__CC_IB_SR_FRAG_VALIDB_READYB__SHIFT 0x13 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY_MASK 0x100000 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READY__SHIFT 0x14 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB_MASK 0x200000 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALID_READYB__SHIFT 0x15 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY_MASK 0x400000 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READY__SHIFT 0x16 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB_MASK 0x800000 +#define CB_DEBUG_BUS_2__CC_RB_BC_EVENFRAG_VALIDB_READYB__SHIFT 0x17 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY_MASK 0x1 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READY__SHIFT 0x0 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB_MASK 0x2 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALID_READYB__SHIFT 0x1 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY_MASK 0x4 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READY__SHIFT 0x2 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB_MASK 0x8 +#define CB_DEBUG_BUS_3__CC_RB_BC_ODDFRAG_VALIDB_READYB__SHIFT 0x3 +#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID_MASK 0x10 +#define CB_DEBUG_BUS_3__CC_BC_CS_FRAG_VALID__SHIFT 0x4 +#define CB_DEBUG_BUS_3__CC_SF_FULL_MASK 0x20 +#define CB_DEBUG_BUS_3__CC_SF_FULL__SHIFT 0x5 +#define CB_DEBUG_BUS_3__CC_RB_FULL_MASK 0x40 +#define CB_DEBUG_BUS_3__CC_RB_FULL__SHIFT 0x6 +#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL_MASK 0x80 +#define CB_DEBUG_BUS_3__CC_EVENFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x7 +#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL_MASK 0x100 +#define CB_DEBUG_BUS_3__CC_ODDFIFO_QUAD_RESIDENCY_STALL__SHIFT 0x8 +#define CB_DEBUG_BUS_3__CM_TQ_FULL_MASK 0x200 +#define CB_DEBUG_BUS_3__CM_TQ_FULL__SHIFT 0x9 +#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL_MASK 0x400 +#define CB_DEBUG_BUS_3__CM_TILE_RESIDENCY_STALL__SHIFT 0xa +#define CB_DEBUG_BUS_3__LQUAD_NO_TILE_MASK 0x800 +#define CB_DEBUG_BUS_3__LQUAD_NO_TILE__SHIFT 0xb +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R_MASK 0x1000 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_R__SHIFT 0xc +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR_MASK 0x2000 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_AR__SHIFT 0xd +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR_MASK 0x4000 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_GR__SHIFT 0xe +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR_MASK 0x8000 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_32_ABGR__SHIFT 0xf +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR_MASK 0x10000 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_FP16_ABGR__SHIFT 0x10 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR_MASK 0x20000 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR__SHIFT 0x11 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR_MASK 0x40000 +#define CB_DEBUG_BUS_3__LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR__SHIFT 0x12 +#define CB_DEBUG_BUS_3__CM_CACHE_HIT_MASK 0x80000 +#define CB_DEBUG_BUS_3__CM_CACHE_HIT__SHIFT 0x13 +#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS_MASK 0x100000 +#define CB_DEBUG_BUS_3__CM_CACHE_TAG_MISS__SHIFT 0x14 +#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS_MASK 0x200000 +#define CB_DEBUG_BUS_3__CM_CACHE_SECTOR_MISS__SHIFT 0x15 +#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL_MASK 0x400000 +#define CB_DEBUG_BUS_3__CM_CACHE_REEVICTION_STALL__SHIFT 0x16 +#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x800000 +#define CB_DEBUG_BUS_3__CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x17 +#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x1 +#define CB_DEBUG_BUS_4__CM_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x0 +#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x2 +#define CB_DEBUG_BUS_4__CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x1 +#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL_MASK 0x4 +#define CB_DEBUG_BUS_4__CM_CACHE_READ_OUTPUT_STALL__SHIFT 0x2 +#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL_MASK 0x8 +#define CB_DEBUG_BUS_4__CM_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x3 +#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL_MASK 0x10 +#define CB_DEBUG_BUS_4__CM_CACHE_ACK_OUTPUT_STALL__SHIFT 0x4 +#define CB_DEBUG_BUS_4__CM_CACHE_STALL_MASK 0x20 +#define CB_DEBUG_BUS_4__CM_CACHE_STALL__SHIFT 0x5 +#define CB_DEBUG_BUS_4__FC_CACHE_HIT_MASK 0x40 +#define CB_DEBUG_BUS_4__FC_CACHE_HIT__SHIFT 0x6 +#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS_MASK 0x80 +#define CB_DEBUG_BUS_4__FC_CACHE_TAG_MISS__SHIFT 0x7 +#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS_MASK 0x100 +#define CB_DEBUG_BUS_4__FC_CACHE_SECTOR_MISS__SHIFT 0x8 +#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL_MASK 0x200 +#define CB_DEBUG_BUS_4__FC_CACHE_REEVICTION_STALL__SHIFT 0x9 +#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x400 +#define CB_DEBUG_BUS_4__FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xa +#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x800 +#define CB_DEBUG_BUS_4__FC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xb +#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x1000 +#define CB_DEBUG_BUS_4__FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xc +#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL_MASK 0x2000 +#define CB_DEBUG_BUS_4__FC_CACHE_READ_OUTPUT_STALL__SHIFT 0xd +#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL_MASK 0x4000 +#define CB_DEBUG_BUS_4__FC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0xe +#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL_MASK 0x8000 +#define CB_DEBUG_BUS_4__FC_CACHE_ACK_OUTPUT_STALL__SHIFT 0xf +#define CB_DEBUG_BUS_4__FC_CACHE_STALL_MASK 0x10000 +#define CB_DEBUG_BUS_4__FC_CACHE_STALL__SHIFT 0x10 +#define CB_DEBUG_BUS_4__CC_CACHE_HIT_MASK 0x20000 +#define CB_DEBUG_BUS_4__CC_CACHE_HIT__SHIFT 0x11 +#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS_MASK 0x40000 +#define CB_DEBUG_BUS_4__CC_CACHE_TAG_MISS__SHIFT 0x12 +#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS_MASK 0x80000 +#define CB_DEBUG_BUS_4__CC_CACHE_SECTOR_MISS__SHIFT 0x13 +#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL_MASK 0x100000 +#define CB_DEBUG_BUS_4__CC_CACHE_REEVICTION_STALL__SHIFT 0x14 +#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x200000 +#define CB_DEBUG_BUS_4__CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0x15 +#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x400000 +#define CB_DEBUG_BUS_4__CC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0x16 +#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x800000 +#define CB_DEBUG_BUS_4__CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0x17 +#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL_MASK 0x1 +#define CB_DEBUG_BUS_5__CC_CACHE_READ_OUTPUT_STALL__SHIFT 0x0 +#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL_MASK 0x2 +#define CB_DEBUG_BUS_5__CC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x1 +#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL_MASK 0x4 +#define CB_DEBUG_BUS_5__CC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x2 +#define CB_DEBUG_BUS_5__CC_CACHE_STALL_MASK 0x8 +#define CB_DEBUG_BUS_5__CC_CACHE_STALL__SHIFT 0x3 +#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION_MASK 0x10 +#define CB_DEBUG_BUS_5__CC_CACHE_WA_TO_RMW_CONVERSION__SHIFT 0x4 +#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH_MASK 0x20 +#define CB_DEBUG_BUS_5__CM_CACHE_FLUSH__SHIFT 0x5 +#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED_MASK 0x40 +#define CB_DEBUG_BUS_5__CM_CACHE_TAGS_FLUSHED__SHIFT 0x6 +#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED_MASK 0x80 +#define CB_DEBUG_BUS_5__CM_CACHE_SECTORS_FLUSHED__SHIFT 0x7 +#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x100 +#define CB_DEBUG_BUS_5__CM_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x8 +#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH_MASK 0x200 +#define CB_DEBUG_BUS_5__FC_CACHE_FLUSH__SHIFT 0x9 +#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED_MASK 0x400 +#define CB_DEBUG_BUS_5__FC_CACHE_TAGS_FLUSHED__SHIFT 0xa +#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED_MASK 0x3800 +#define CB_DEBUG_BUS_5__FC_CACHE_SECTORS_FLUSHED__SHIFT 0xb +#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x1c000 +#define CB_DEBUG_BUS_5__FC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0xe +#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH_MASK 0x20000 +#define CB_DEBUG_BUS_5__CC_CACHE_FLUSH__SHIFT 0x11 +#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED_MASK 0x40000 +#define CB_DEBUG_BUS_5__CC_CACHE_TAGS_FLUSHED__SHIFT 0x12 +#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED_MASK 0x380000 +#define CB_DEBUG_BUS_5__CC_CACHE_SECTORS_FLUSHED__SHIFT 0x13 +#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x7 +#define CB_DEBUG_BUS_6__CC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x0 +#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST_MASK 0x8 +#define CB_DEBUG_BUS_6__CM_MC_READ_REQUEST__SHIFT 0x3 +#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST_MASK 0x10 +#define CB_DEBUG_BUS_6__FC_MC_READ_REQUEST__SHIFT 0x4 +#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST_MASK 0x20 +#define CB_DEBUG_BUS_6__CC_MC_READ_REQUEST__SHIFT 0x5 +#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST_MASK 0x40 +#define CB_DEBUG_BUS_6__CM_MC_WRITE_REQUEST__SHIFT 0x6 +#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST_MASK 0x80 +#define CB_DEBUG_BUS_6__FC_MC_WRITE_REQUEST__SHIFT 0x7 +#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST_MASK 0x100 +#define CB_DEBUG_BUS_6__CC_MC_WRITE_REQUEST__SHIFT 0x8 +#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1fe00 +#define CB_DEBUG_BUS_6__CM_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x9 +#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x7ff +#define CB_DEBUG_BUS_7__FC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0x0 +#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT_MASK 0x1ff800 +#define CB_DEBUG_BUS_7__CC_MC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb +#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0xff +#define CB_DEBUG_BUS_8__CM_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0 +#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff00 +#define CB_DEBUG_BUS_8__FC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x8 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE_MASK 0x80000 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_COMPRESSION_DISABLE__SHIFT 0x13 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS_MASK 0x100000 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_FMASK_DECOMPRESS__SHIFT 0x14 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR_MASK 0x200000 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_ELIMINATE_FAST_CLEAR__SHIFT 0x15 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR_MASK 0x400000 +#define CB_DEBUG_BUS_8__FC_SEQUENCER_CLEAR__SHIFT 0x16 +#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x3ff +#define CB_DEBUG_BUS_9__CC_MC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0 +#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC_MASK 0x400 +#define CB_DEBUG_BUS_9__CC_SURFACE_SYNC__SHIFT 0xa +#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT_MASK 0x800 +#define CB_DEBUG_BUS_9__TWO_PROBE_QUAD_FRAGMENT__SHIFT 0xb +#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT_MASK 0x1000 +#define CB_DEBUG_BUS_9__EXPORT_32_ABGR_QUAD_FRAGMENT__SHIFT 0xc +#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT_MASK 0x2000 +#define CB_DEBUG_BUS_9__DUAL_SOURCE_COLOR_QUAD_FRAGMENT__SHIFT 0xd +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_MASK 0x4000 +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD__SHIFT 0xe +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL_MASK 0x78000 +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_PIXEL__SHIFT 0xf +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT_MASK 0x80000 +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_QUAD_FRAGMENT__SHIFT 0x13 +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE_MASK 0x100000 +#define CB_DEBUG_BUS_9__DEBUG_BUS_DRAWN_TILE__SHIFT 0x14 +#define CB_DEBUG_BUS_9__EVENT_ALL_MASK 0x200000 +#define CB_DEBUG_BUS_9__EVENT_ALL__SHIFT 0x15 +#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS_MASK 0x400000 +#define CB_DEBUG_BUS_9__EVENT_CACHE_FLUSH_TS__SHIFT 0x16 +#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE_MASK 0x800000 +#define CB_DEBUG_BUS_9__EVENT_CONTEXT_DONE__SHIFT 0x17 +#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_MASK 0x1 +#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH__SHIFT 0x0 +#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT_MASK 0x2 +#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_TS_EVENT__SHIFT 0x1 +#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT_MASK 0x4 +#define CB_DEBUG_BUS_10__EVENT_CACHE_FLUSH_AND_INV_EVENT__SHIFT 0x2 +#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS_MASK 0x8 +#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_DATA_TS__SHIFT 0x3 +#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META_MASK 0x10 +#define CB_DEBUG_BUS_10__EVENT_FLUSH_AND_INV_CB_META__SHIFT 0x4 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC_MASK 0x20 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XC__SHIFT 0x5 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD_MASK 0x40 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XD__SHIFT 0x6 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE_MASK 0x80 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XE__SHIFT 0x7 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF_MASK 0x100 +#define CB_DEBUG_BUS_10__CMASK_READ_DATA_0XF__SHIFT 0x8 +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC_MASK 0x200 +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XC__SHIFT 0x9 +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD_MASK 0x400 +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XD__SHIFT 0xa +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE_MASK 0x800 +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XE__SHIFT 0xb +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF_MASK 0x1000 +#define CB_DEBUG_BUS_10__CMASK_WRITE_DATA_0XF__SHIFT 0xc +#define CB_DEBUG_BUS_10__CORE_SCLK_VLD_MASK 0x2000 +#define CB_DEBUG_BUS_10__CORE_SCLK_VLD__SHIFT 0xd +#define CB_DEBUG_BUS_10__REG_SCLK0_VLD_MASK 0x4000 +#define CB_DEBUG_BUS_10__REG_SCLK0_VLD__SHIFT 0xe +#define CB_DEBUG_BUS_10__REG_SCLK1_VLD_MASK 0x8000 +#define CB_DEBUG_BUS_10__REG_SCLK1_VLD__SHIFT 0xf +#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY_MASK 0x10000 +#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READY__SHIFT 0x10 +#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB_MASK 0x20000 +#define CB_DEBUG_BUS_10__MERGE_TILE_ONLY_VALID_READYB__SHIFT 0x11 +#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL_MASK 0x40000 +#define CB_DEBUG_BUS_10__FC_QUAD_RDLAT_FIFO_FULL__SHIFT 0x12 +#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL_MASK 0x80000 +#define CB_DEBUG_BUS_10__FC_TILE_RDLAT_FIFO_FULL__SHIFT 0x13 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE_MASK 0x100000 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE__SHIFT 0x14 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE_MASK 0x200000 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x15 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE_MASK 0x400000 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x16 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE_MASK 0x800000 +#define CB_DEBUG_BUS_10__FOP_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x17 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE_MASK 0x1 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x0 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE_MASK 0x2 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x1 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE_MASK 0x4 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x2 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE_MASK 0x8 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE__SHIFT 0x3 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE_MASK 0x10 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE__SHIFT 0x4 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE_MASK 0x20 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE__SHIFT 0x5 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE_MASK 0x40 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE__SHIFT 0x6 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE_MASK 0x80 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE__SHIFT 0x7 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE_MASK 0x100 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE__SHIFT 0x8 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE_MASK 0x200 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE__SHIFT 0x9 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE_MASK 0x400 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE__SHIFT 0xa +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE_MASK 0x800 +#define CB_DEBUG_BUS_11__FOP_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE__SHIFT 0xb +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT_MASK 0x1000 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_1_FRAGMENT__SHIFT 0xc +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS_MASK 0x2000 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_2_FRAGMENTS__SHIFT 0xd +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS_MASK 0x4000 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_3_FRAGMENTS__SHIFT 0xe +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS_MASK 0x8000 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_4_FRAGMENTS__SHIFT 0xf +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS_MASK 0x10000 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_5_FRAGMENTS__SHIFT 0x10 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS_MASK 0x20000 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_6_FRAGMENTS__SHIFT 0x11 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS_MASK 0x40000 +#define CB_DEBUG_BUS_11__FOP_QUAD_ADDED_7_FRAGMENTS__SHIFT 0x12 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT_MASK 0x80000 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_1_FRAGMENT__SHIFT 0x13 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS_MASK 0x100000 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_2_FRAGMENTS__SHIFT 0x14 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS_MASK 0x200000 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_3_FRAGMENTS__SHIFT 0x15 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS_MASK 0x400000 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_4_FRAGMENTS__SHIFT 0x16 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS_MASK 0x800000 +#define CB_DEBUG_BUS_11__FOP_QUAD_REMOVED_5_FRAGMENTS__SHIFT 0x17 +#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS_MASK 0x1 +#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_6_FRAGMENTS__SHIFT 0x0 +#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS_MASK 0x2 +#define CB_DEBUG_BUS_12__FOP_QUAD_REMOVED_7_FRAGMENTS__SHIFT 0x1 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0_MASK 0x4 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_0__SHIFT 0x2 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1_MASK 0x8 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_1__SHIFT 0x3 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2_MASK 0x10 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_2__SHIFT 0x4 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3_MASK 0x20 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_3__SHIFT 0x5 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4_MASK 0x40 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_4__SHIFT 0x6 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5_MASK 0x80 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_5__SHIFT 0x7 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6_MASK 0x100 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_6__SHIFT 0x8 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7_MASK 0x200 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_READS_FRAGMENT_7__SHIFT 0x9 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0_MASK 0x400 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_0__SHIFT 0xa +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1_MASK 0x800 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_1__SHIFT 0xb +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2_MASK 0x1000 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_2__SHIFT 0xc +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3_MASK 0x2000 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_3__SHIFT 0xd +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4_MASK 0x4000 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_4__SHIFT 0xe +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5_MASK 0x8000 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_5__SHIFT 0xf +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6_MASK 0x10000 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_6__SHIFT 0x10 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7_MASK 0x20000 +#define CB_DEBUG_BUS_12__FC_CC_QUADFRAG_WRITES_FRAGMENT_7__SHIFT 0x11 +#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST_MASK 0x40000 +#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DONT_READ_DST__SHIFT 0x12 +#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS_MASK 0x80000 +#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_BLEND_BYPASS__SHIFT 0x13 +#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS_MASK 0x100000 +#define CB_DEBUG_BUS_12__FC_QUAD_BLEND_OPT_DISCARD_PIXELS__SHIFT 0x14 +#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT_MASK 0x200000 +#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT__SHIFT 0x15 +#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID_MASK 0x400000 +#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_COLOR_INVALID__SHIFT 0x16 +#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK_MASK 0x800000 +#define CB_DEBUG_BUS_12__FC_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK__SHIFT 0x17 +#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL_MASK 0x1 +#define CB_DEBUG_BUS_13__FC_PF_FC_KEYID_RDLAT_FIFO_FULL__SHIFT 0x0 +#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS_MASK 0x2 +#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_MISS__SHIFT 0x1 +#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT_MASK 0x4 +#define CB_DEBUG_BUS_13__FC_DOC_QTILE_CAM_HIT__SHIFT 0x2 +#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS_MASK 0x8 +#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_MISS__SHIFT 0x3 +#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT_MASK 0x10 +#define CB_DEBUG_BUS_13__FC_DOC_CLINE_CAM_HIT__SHIFT 0x4 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR_MASK 0x20 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_1_SECTOR__SHIFT 0x5 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS_MASK 0x40 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_2_SECTORS__SHIFT 0x6 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS_MASK 0x80 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_3_SECTORS__SHIFT 0x7 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS_MASK 0x100 +#define CB_DEBUG_BUS_13__FC_DOC_OVERWROTE_4_SECTORS__SHIFT 0x8 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT_MASK 0x200 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_HIT__SHIFT 0x9 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS_MASK 0x400 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAG_MISS__SHIFT 0xa +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS_MASK 0x800 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTOR_MISS__SHIFT 0xb +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL_MASK 0x1000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REEVICTION_STALL__SHIFT 0xc +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL_MASK 0x2000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL__SHIFT 0xd +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL_MASK 0x4000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_REPLACE_PENDING_EVICT_STALL__SHIFT 0xe +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL_MASK 0x8000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL__SHIFT 0xf +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL_MASK 0x10000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_READ_OUTPUT_STALL__SHIFT 0x10 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL_MASK 0x20000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_WRITE_OUTPUT_STALL__SHIFT 0x11 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL_MASK 0x40000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_ACK_OUTPUT_STALL__SHIFT 0x12 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL_MASK 0x80000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_STALL__SHIFT 0x13 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH_MASK 0x100000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_FLUSH__SHIFT 0x14 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED_MASK 0x200000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_SECTORS_FLUSHED__SHIFT 0x15 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED_MASK 0x400000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_DIRTY_SECTORS_FLUSHED__SHIFT 0x16 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED_MASK 0x800000 +#define CB_DEBUG_BUS_13__FC_PF_DCC_CACHE_TAGS_FLUSHED__SHIFT 0x17 +#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT_MASK 0x7ff +#define CB_DEBUG_BUS_14__FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT__SHIFT 0x0 +#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT_MASK 0x3ff800 +#define CB_DEBUG_BUS_14__FC_MC_DCC_READ_REQUESTS_IN_FLIGHT__SHIFT 0xb +#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT_MASK 0x400000 +#define CB_DEBUG_BUS_14__CC_PF_DCC_BEYOND_TILE_SPLIT__SHIFT 0x16 +#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL_MASK 0x800000 +#define CB_DEBUG_BUS_14__CC_PF_DCC_RDREQ_STALL__SHIFT 0x17 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1_MASK 0x7 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_2TO1__SHIFT 0x0 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1_MASK 0x18 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO1__SHIFT 0x3 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2_MASK 0x60 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO2__SHIFT 0x5 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3_MASK 0x180 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_4TO3__SHIFT 0x7 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1_MASK 0x600 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO1__SHIFT 0x9 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2_MASK 0x1800 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO2__SHIFT 0xb +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3_MASK 0x6000 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO3__SHIFT 0xd +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4_MASK 0x18000 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO4__SHIFT 0xf +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5_MASK 0x60000 +#define CB_DEBUG_BUS_15__CC_PF_DCC_COMPRESS_RATIO_6TO5__SHIFT 0x11 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1_MASK 0x1 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO1__SHIFT 0x0 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2_MASK 0x2 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO2__SHIFT 0x1 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3_MASK 0x4 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO3__SHIFT 0x2 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4_MASK 0x8 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO4__SHIFT 0x3 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5_MASK 0x10 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO5__SHIFT 0x4 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6_MASK 0x20 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO6__SHIFT 0x5 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7_MASK 0x40 +#define CB_DEBUG_BUS_16__CC_PF_DCC_COMPRESS_RATIO_8TO7__SHIFT 0x6 +#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_17__TILE_INTFC_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_17__MU_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_17__MU_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_17__TQ_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_17__TQ_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_17__AC_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_17__AC_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_17__CRW_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_17__CRW_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_17__CACHE_CTRL_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_17__MC_WR_PENDING_MASK 0x40 +#define CB_DEBUG_BUS_17__MC_WR_PENDING__SHIFT 0x6 +#define CB_DEBUG_BUS_17__FC_WR_PENDING_MASK 0x80 +#define CB_DEBUG_BUS_17__FC_WR_PENDING__SHIFT 0x7 +#define CB_DEBUG_BUS_17__FC_RD_PENDING_MASK 0x100 +#define CB_DEBUG_BUS_17__FC_RD_PENDING__SHIFT 0x8 +#define CB_DEBUG_BUS_17__EVICT_PENDING_MASK 0x200 +#define CB_DEBUG_BUS_17__EVICT_PENDING__SHIFT 0x9 +#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER_MASK 0x400 +#define CB_DEBUG_BUS_17__LAST_RD_ARB_WINNER__SHIFT 0xa +#define CB_DEBUG_BUS_17__MU_STATE_MASK 0x7f800 +#define CB_DEBUG_BUS_17__MU_STATE__SHIFT 0xb +#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_18__TILE_RETIREMENT_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_18__FOP_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_18__FOP_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_18__CLEAR_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_18__CLEAR_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_18__LAT_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_18__LAT_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_18__CACHE_CTL_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_18__ADDR_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_18__ADDR_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_18__MERGE_BUSY_MASK 0x40 +#define CB_DEBUG_BUS_18__MERGE_BUSY__SHIFT 0x6 +#define CB_DEBUG_BUS_18__QUAD_BUSY_MASK 0x80 +#define CB_DEBUG_BUS_18__QUAD_BUSY__SHIFT 0x7 +#define CB_DEBUG_BUS_18__TILE_BUSY_MASK 0x100 +#define CB_DEBUG_BUS_18__TILE_BUSY__SHIFT 0x8 +#define CB_DEBUG_BUS_18__DCC_BUSY_MASK 0x200 +#define CB_DEBUG_BUS_18__DCC_BUSY__SHIFT 0x9 +#define CB_DEBUG_BUS_18__DOC_BUSY_MASK 0x400 +#define CB_DEBUG_BUS_18__DOC_BUSY__SHIFT 0xa +#define CB_DEBUG_BUS_18__DAG_BUSY_MASK 0x800 +#define CB_DEBUG_BUS_18__DAG_BUSY__SHIFT 0xb +#define CB_DEBUG_BUS_18__DOC_STALL_MASK 0x1000 +#define CB_DEBUG_BUS_18__DOC_STALL__SHIFT 0xc +#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL_MASK 0x2000 +#define CB_DEBUG_BUS_18__DOC_QT_CAM_FULL__SHIFT 0xd +#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL_MASK 0x4000 +#define CB_DEBUG_BUS_18__DOC_CL_CAM_FULL__SHIFT 0xe +#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL_MASK 0x8000 +#define CB_DEBUG_BUS_18__DOC_QUAD_PTR_FIFO_FULL__SHIFT 0xf +#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL_MASK 0x10000 +#define CB_DEBUG_BUS_18__DOC_SECTOR_MASK_FIFO_FULL__SHIFT 0x10 +#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST_MASK 0x20000 +#define CB_DEBUG_BUS_18__DCS_READ_WINNER_LAST__SHIFT 0x11 +#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING_MASK 0x40000 +#define CB_DEBUG_BUS_18__DCS_READ_EV_PENDING__SHIFT 0x12 +#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING_MASK 0x80000 +#define CB_DEBUG_BUS_18__DCS_WRITE_CC_PENDING__SHIFT 0x13 +#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING_MASK 0x100000 +#define CB_DEBUG_BUS_18__DCS_READ_CC_PENDING__SHIFT 0x14 +#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING_MASK 0x200000 +#define CB_DEBUG_BUS_18__DCS_WRITE_MC_PENDING__SHIFT 0x15 +#define CB_DEBUG_BUS_19__SURF_SYNC_STATE_MASK 0x3 +#define CB_DEBUG_BUS_19__SURF_SYNC_STATE__SHIFT 0x0 +#define CB_DEBUG_BUS_19__SURF_SYNC_START_MASK 0x4 +#define CB_DEBUG_BUS_19__SURF_SYNC_START__SHIFT 0x2 +#define CB_DEBUG_BUS_19__SF_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_19__SF_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_19__CS_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_19__CS_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_19__RB_BUSY_MASK 0x20 +#define CB_DEBUG_BUS_19__RB_BUSY__SHIFT 0x5 +#define CB_DEBUG_BUS_19__DS_BUSY_MASK 0x40 +#define CB_DEBUG_BUS_19__DS_BUSY__SHIFT 0x6 +#define CB_DEBUG_BUS_19__TB_BUSY_MASK 0x80 +#define CB_DEBUG_BUS_19__TB_BUSY__SHIFT 0x7 +#define CB_DEBUG_BUS_19__IB_BUSY_MASK 0x100 +#define CB_DEBUG_BUS_19__IB_BUSY__SHIFT 0x8 +#define CB_DEBUG_BUS_19__DRR_BUSY_MASK 0x200 +#define CB_DEBUG_BUS_19__DRR_BUSY__SHIFT 0x9 +#define CB_DEBUG_BUS_19__DF_BUSY_MASK 0x400 +#define CB_DEBUG_BUS_19__DF_BUSY__SHIFT 0xa +#define CB_DEBUG_BUS_19__DD_BUSY_MASK 0x800 +#define CB_DEBUG_BUS_19__DD_BUSY__SHIFT 0xb +#define CB_DEBUG_BUS_19__DC_BUSY_MASK 0x1000 +#define CB_DEBUG_BUS_19__DC_BUSY__SHIFT 0xc +#define CB_DEBUG_BUS_19__DK_BUSY_MASK 0x2000 +#define CB_DEBUG_BUS_19__DK_BUSY__SHIFT 0xd +#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY_MASK 0x4000 +#define CB_DEBUG_BUS_19__DF_SKID_FIFO_EMPTY__SHIFT 0xe +#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY_MASK 0x8000 +#define CB_DEBUG_BUS_19__DF_CLEAR_FIFO_EMPTY__SHIFT 0xf +#define CB_DEBUG_BUS_19__DD_READY_MASK 0x10000 +#define CB_DEBUG_BUS_19__DD_READY__SHIFT 0x10 +#define CB_DEBUG_BUS_19__DC_FIFO_FULL_MASK 0x20000 +#define CB_DEBUG_BUS_19__DC_FIFO_FULL__SHIFT 0x11 +#define CB_DEBUG_BUS_19__DC_READY_MASK 0x40000 +#define CB_DEBUG_BUS_19__DC_READY__SHIFT 0x12 +#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS_MASK 0x3f +#define CB_DEBUG_BUS_20__MC_RDREQ_CREDITS__SHIFT 0x0 +#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS_MASK 0xfc0 +#define CB_DEBUG_BUS_20__MC_WRREQ_CREDITS__SHIFT 0x6 +#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN_MASK 0x1000 +#define CB_DEBUG_BUS_20__CC_RDREQ_HAD_ITS_TURN__SHIFT 0xc +#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN_MASK 0x2000 +#define CB_DEBUG_BUS_20__FC_RDREQ_HAD_ITS_TURN__SHIFT 0xd +#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN_MASK 0x4000 +#define CB_DEBUG_BUS_20__CM_RDREQ_HAD_ITS_TURN__SHIFT 0xe +#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN_MASK 0x10000 +#define CB_DEBUG_BUS_20__CC_WRREQ_HAD_ITS_TURN__SHIFT 0x10 +#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN_MASK 0x20000 +#define CB_DEBUG_BUS_20__FC_WRREQ_HAD_ITS_TURN__SHIFT 0x11 +#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN_MASK 0x40000 +#define CB_DEBUG_BUS_20__CM_WRREQ_HAD_ITS_TURN__SHIFT 0x12 +#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY_MASK 0x100000 +#define CB_DEBUG_BUS_20__CC_WRREQ_FIFO_EMPTY__SHIFT 0x14 +#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY_MASK 0x200000 +#define CB_DEBUG_BUS_20__FC_WRREQ_FIFO_EMPTY__SHIFT 0x15 +#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY_MASK 0x400000 +#define CB_DEBUG_BUS_20__CM_WRREQ_FIFO_EMPTY__SHIFT 0x16 +#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY_MASK 0x800000 +#define CB_DEBUG_BUS_20__DCC_WRREQ_FIFO_EMPTY__SHIFT 0x17 +#define CB_DEBUG_BUS_21__CM_BUSY_MASK 0x1 +#define CB_DEBUG_BUS_21__CM_BUSY__SHIFT 0x0 +#define CB_DEBUG_BUS_21__FC_BUSY_MASK 0x2 +#define CB_DEBUG_BUS_21__FC_BUSY__SHIFT 0x1 +#define CB_DEBUG_BUS_21__CC_BUSY_MASK 0x4 +#define CB_DEBUG_BUS_21__CC_BUSY__SHIFT 0x2 +#define CB_DEBUG_BUS_21__BB_BUSY_MASK 0x8 +#define CB_DEBUG_BUS_21__BB_BUSY__SHIFT 0x3 +#define CB_DEBUG_BUS_21__MA_BUSY_MASK 0x10 +#define CB_DEBUG_BUS_21__MA_BUSY__SHIFT 0x4 +#define CB_DEBUG_BUS_21__CORE_SCLK_VLD_MASK 0x20 +#define CB_DEBUG_BUS_21__CORE_SCLK_VLD__SHIFT 0x5 +#define CB_DEBUG_BUS_21__REG_SCLK1_VLD_MASK 0x40 +#define CB_DEBUG_BUS_21__REG_SCLK1_VLD__SHIFT 0x6 +#define CB_DEBUG_BUS_21__REG_SCLK0_VLD_MASK 0x80 +#define CB_DEBUG_BUS_21__REG_SCLK0_VLD__SHIFT 0x7 +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS_MASK 0xfff +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_READS__SHIFT 0x0 +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES_MASK 0xfff000 +#define CB_DEBUG_BUS_22__OUTSTANDING_MC_WRITES__SHIFT 0xc +#define CP_DFY_CNTL__POLICY_MASK 0x1 +#define CP_DFY_CNTL__POLICY__SHIFT 0x0 +#define CP_DFY_CNTL__MTYPE_MASK 0xc +#define CP_DFY_CNTL__MTYPE__SHIFT 0x2 +#define CP_DFY_CNTL__LFSR_RESET_MASK 0x10000000 +#define CP_DFY_CNTL__LFSR_RESET__SHIFT 0x1c +#define CP_DFY_CNTL__MODE_MASK 0x60000000 +#define CP_DFY_CNTL__MODE__SHIFT 0x1d +#define CP_DFY_CNTL__ENABLE_MASK 0x80000000 +#define CP_DFY_CNTL__ENABLE__SHIFT 0x1f +#define CP_DFY_STAT__BURST_COUNT_MASK 0xffff +#define CP_DFY_STAT__BURST_COUNT__SHIFT 0x0 +#define CP_DFY_STAT__TAGS_PENDING_MASK 0x1ff0000 +#define CP_DFY_STAT__TAGS_PENDING__SHIFT 0x10 +#define CP_DFY_STAT__BUSY_MASK 0x80000000 +#define CP_DFY_STAT__BUSY__SHIFT 0x1f +#define CP_DFY_ADDR_HI__ADDR_HI_MASK 0xffffffff +#define CP_DFY_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DFY_ADDR_LO__ADDR_LO_MASK 0xffffffe0 +#define CP_DFY_ADDR_LO__ADDR_LO__SHIFT 0x5 +#define CP_DFY_DATA_0__DATA_MASK 0xffffffff +#define CP_DFY_DATA_0__DATA__SHIFT 0x0 +#define CP_DFY_DATA_1__DATA_MASK 0xffffffff +#define CP_DFY_DATA_1__DATA__SHIFT 0x0 +#define CP_DFY_DATA_2__DATA_MASK 0xffffffff +#define CP_DFY_DATA_2__DATA__SHIFT 0x0 +#define CP_DFY_DATA_3__DATA_MASK 0xffffffff +#define CP_DFY_DATA_3__DATA__SHIFT 0x0 +#define CP_DFY_DATA_4__DATA_MASK 0xffffffff +#define CP_DFY_DATA_4__DATA__SHIFT 0x0 +#define CP_DFY_DATA_5__DATA_MASK 0xffffffff +#define CP_DFY_DATA_5__DATA__SHIFT 0x0 +#define CP_DFY_DATA_6__DATA_MASK 0xffffffff +#define CP_DFY_DATA_6__DATA__SHIFT 0x0 +#define CP_DFY_DATA_7__DATA_MASK 0xffffffff +#define CP_DFY_DATA_7__DATA__SHIFT 0x0 +#define CP_DFY_DATA_8__DATA_MASK 0xffffffff +#define CP_DFY_DATA_8__DATA__SHIFT 0x0 +#define CP_DFY_DATA_9__DATA_MASK 0xffffffff +#define CP_DFY_DATA_9__DATA__SHIFT 0x0 +#define CP_DFY_DATA_10__DATA_MASK 0xffffffff +#define CP_DFY_DATA_10__DATA__SHIFT 0x0 +#define CP_DFY_DATA_11__DATA_MASK 0xffffffff +#define CP_DFY_DATA_11__DATA__SHIFT 0x0 +#define CP_DFY_DATA_12__DATA_MASK 0xffffffff +#define CP_DFY_DATA_12__DATA__SHIFT 0x0 +#define CP_DFY_DATA_13__DATA_MASK 0xffffffff +#define CP_DFY_DATA_13__DATA__SHIFT 0x0 +#define CP_DFY_DATA_14__DATA_MASK 0xffffffff +#define CP_DFY_DATA_14__DATA__SHIFT 0x0 +#define CP_DFY_DATA_15__DATA_MASK 0xffffffff +#define CP_DFY_DATA_15__DATA__SHIFT 0x0 +#define CP_DFY_CMD__OFFSET_MASK 0x1ff +#define CP_DFY_CMD__OFFSET__SHIFT 0x0 +#define CP_DFY_CMD__SIZE_MASK 0xffff0000 +#define CP_DFY_CMD__SIZE__SHIFT 0x10 +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD_MASK 0xff +#define CP_CPC_MGCG_SYNC_CNTL__COOLDOWN_PERIOD__SHIFT 0x0 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD_MASK 0xff00 +#define CP_CPC_MGCG_SYNC_CNTL__WARMUP_PERIOD__SHIFT 0x8 +#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT_MASK 0x3ff +#define CP_ATCL1_CNTL__XNACK_REDO_TIMER_CNT__SHIFT 0x0 +#define CP_RB0_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB0_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_BASE_HI__RB_BASE_HI_MASK 0xff +#define CP_RB0_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB1_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB1_BASE_HI__RB_BASE_HI_MASK 0xff +#define CP_RB1_BASE_HI__RB_BASE_HI__SHIFT 0x0 +#define CP_RB2_BASE__RB_BASE_MASK 0xffffffff +#define CP_RB2_BASE__RB_BASE__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB0_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB0_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB0_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB0_CNTL__MTYPE_MASK 0x18000 +#define CP_RB0_CNTL__MTYPE__SHIFT 0xf +#define CP_RB0_CNTL__BUF_SWAP_MASK 0x60000 +#define CP_RB0_CNTL__BUF_SWAP__SHIFT 0x11 +#define CP_RB0_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB0_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB0_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB0_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB0_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB0_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB0_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB0_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB_CNTL__MTYPE_MASK 0x18000 +#define CP_RB_CNTL__MTYPE__SHIFT 0xf +#define CP_RB_CNTL__BUF_SWAP_MASK 0x60000 +#define CP_RB_CNTL__BUF_SWAP__SHIFT 0x11 +#define CP_RB_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB1_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB1_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB1_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB1_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB1_CNTL__MTYPE_MASK 0x18000 +#define CP_RB1_CNTL__MTYPE__SHIFT 0xf +#define CP_RB1_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB1_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB1_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB1_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB1_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB1_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB1_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB1_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB2_CNTL__RB_BUFSZ_MASK 0x3f +#define CP_RB2_CNTL__RB_BUFSZ__SHIFT 0x0 +#define CP_RB2_CNTL__RB_BLKSZ_MASK 0x3f00 +#define CP_RB2_CNTL__RB_BLKSZ__SHIFT 0x8 +#define CP_RB2_CNTL__MTYPE_MASK 0x18000 +#define CP_RB2_CNTL__MTYPE__SHIFT 0xf +#define CP_RB2_CNTL__MIN_AVAILSZ_MASK 0x300000 +#define CP_RB2_CNTL__MIN_AVAILSZ__SHIFT 0x14 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ_MASK 0xc00000 +#define CP_RB2_CNTL__MIN_IB_AVAILSZ__SHIFT 0x16 +#define CP_RB2_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_RB2_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_RB2_CNTL__RB_NO_UPDATE_MASK 0x8000000 +#define CP_RB2_CNTL__RB_NO_UPDATE__SHIFT 0x1b +#define CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK 0x80000000 +#define CP_RB2_CNTL__RB_RPTR_WR_ENA__SHIFT 0x1f +#define CP_RB_RPTR_WR__RB_RPTR_WR_MASK 0xfffff +#define CP_RB_RPTR_WR__RB_RPTR_WR__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB0_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB0_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB1_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB1_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP_MASK 0x3 +#define CP_RB2_RPTR_ADDR__RB_RPTR_SWAP__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xfffffffc +#define CP_RB2_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x2 +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB0_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK 0xffff +#define CP_RB2_RPTR_ADDR_HI__RB_RPTR_ADDR_HI__SHIFT 0x0 +#define CP_RB0_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB0_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB1_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB1_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB2_WPTR__RB_WPTR_MASK 0xfffff +#define CP_RB2_WPTR__RB_WPTR__SHIFT 0x0 +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO_MASK 0xfffffffc +#define CP_RB_WPTR_POLL_ADDR_LO__RB_WPTR_POLL_ADDR_LO__SHIFT 0x2 +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI_MASK 0xff +#define CP_RB_WPTR_POLL_ADDR_HI__RB_WPTR_POLL_ADDR_HI__SHIFT 0x0 +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL_RING0__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING0__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING0__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL_RING0__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING0__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING0__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL_RING0__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING0__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING0__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING0__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING0__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL_RING1__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING1__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING1__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL_RING1__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING1__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING1__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL_RING1__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING1__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING1__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING1__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING1__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING1__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING1__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING1__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE_MASK 0x800 +#define CP_INT_CNTL_RING2__CP_VM_DOORBELL_WR_INT_ENABLE__SHIFT 0xb +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_INT_CNTL_RING2__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_INT_CNTL_RING2__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE_MASK 0x40000 +#define CP_INT_CNTL_RING2__CMP_BUSY_INT_ENABLE__SHIFT 0x12 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE_MASK 0x80000 +#define CP_INT_CNTL_RING2__CNTX_BUSY_INT_ENABLE__SHIFT 0x13 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE_MASK 0x100000 +#define CP_INT_CNTL_RING2__CNTX_EMPTY_INT_ENABLE__SHIFT 0x14 +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE_MASK 0x200000 +#define CP_INT_CNTL_RING2__GFX_IDLE_INT_ENABLE__SHIFT 0x15 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE_MASK 0x400000 +#define CP_INT_CNTL_RING2__PRIV_INSTR_INT_ENABLE__SHIFT 0x16 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_INT_CNTL_RING2__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_INT_CNTL_RING2__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_INT_CNTL_RING2__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_INT_CNTL_RING2__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_INT_CNTL_RING2__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_INT_CNTL_RING2__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS_RING0__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING0__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING0__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS_RING0__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING0__GCNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING0__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS_RING0__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING0__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING0__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING0__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING0__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING0__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING0__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING0__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING0__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS_RING1__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING1__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING1__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS_RING1__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING1__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING1__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS_RING1__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING1__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING1__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING1__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING1__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING1__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING1__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING1__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING1__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT_MASK 0x800 +#define CP_INT_STATUS_RING2__CP_VM_DOORBELL_WR_INT_STAT__SHIFT 0xb +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT_MASK 0x4000 +#define CP_INT_STATUS_RING2__CP_ECC_ERROR_INT_STAT__SHIFT 0xe +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT_MASK 0x20000 +#define CP_INT_STATUS_RING2__WRM_POLL_TIMEOUT_INT_STAT__SHIFT 0x11 +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT_MASK 0x40000 +#define CP_INT_STATUS_RING2__CMP_BUSY_INT_STAT__SHIFT 0x12 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT_MASK 0x80000 +#define CP_INT_STATUS_RING2__CNTX_BUSY_INT_STAT__SHIFT 0x13 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT_MASK 0x100000 +#define CP_INT_STATUS_RING2__CNTX_EMPTY_INT_STAT__SHIFT 0x14 +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT_MASK 0x200000 +#define CP_INT_STATUS_RING2__GFX_IDLE_INT_STAT__SHIFT 0x15 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT_MASK 0x400000 +#define CP_INT_STATUS_RING2__PRIV_INSTR_INT_STAT__SHIFT 0x16 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT_MASK 0x800000 +#define CP_INT_STATUS_RING2__PRIV_REG_INT_STAT__SHIFT 0x17 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT_MASK 0x1000000 +#define CP_INT_STATUS_RING2__OPCODE_ERROR_INT_STAT__SHIFT 0x18 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT_MASK 0x4000000 +#define CP_INT_STATUS_RING2__TIME_STAMP_INT_STAT__SHIFT 0x1a +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT_MASK 0x8000000 +#define CP_INT_STATUS_RING2__RESERVED_BIT_ERROR_INT_STAT__SHIFT 0x1b +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT_MASK 0x20000000 +#define CP_INT_STATUS_RING2__GENERIC2_INT_STAT__SHIFT 0x1d +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT_MASK 0x40000000 +#define CP_INT_STATUS_RING2__GENERIC1_INT_STAT__SHIFT 0x1e +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT_MASK 0x80000000 +#define CP_INT_STATUS_RING2__GENERIC0_INT_STAT__SHIFT 0x1f +#define CP_DEVICE_ID__DEVICE_ID_MASK 0xff +#define CP_DEVICE_ID__DEVICE_ID__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_RING_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_RING_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_RING_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_RING_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME0_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_RING0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_RING2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_RING2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME0_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ENDIAN_SWAP__ENDIAN_SWAP_MASK 0x3 +#define CP_ENDIAN_SWAP__ENDIAN_SWAP__SHIFT 0x0 +#define CP_RB_VMID__RB0_VMID_MASK 0xf +#define CP_RB_VMID__RB0_VMID__SHIFT 0x0 +#define CP_RB_VMID__RB1_VMID_MASK 0xf00 +#define CP_RB_VMID__RB1_VMID__SHIFT 0x8 +#define CP_RB_VMID__RB2_VMID_MASK 0xf0000 +#define CP_RB_VMID__RB2_VMID__SHIFT 0x10 +#define CP_ME0_PIPE0_VMID__VMID_MASK 0xf +#define CP_ME0_PIPE0_VMID__VMID__SHIFT 0x0 +#define CP_ME0_PIPE1_VMID__VMID_MASK 0xf +#define CP_ME0_PIPE1_VMID__VMID__SHIFT 0x0 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc +#define CP_RB_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 +#define CP_RB_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc +#define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc +#define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_MASK 0x7ffffc +#define CP_MEC_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER__SHIFT 0x2 +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK 0x7ffffc +#define CP_MEC_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER__SHIFT 0x2 +#define CP_PFP_UCODE_ADDR__UCODE_ADDR_MASK 0x1fff +#define CP_PFP_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_PFP_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_PFP_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_ME_RAM_RADDR__ME_RAM_RADDR_MASK 0x1fff +#define CP_ME_RAM_RADDR__ME_RAM_RADDR__SHIFT 0x0 +#define CP_ME_RAM_WADDR__ME_RAM_WADDR_MASK 0x1fff +#define CP_ME_RAM_WADDR__ME_RAM_WADDR__SHIFT 0x0 +#define CP_ME_RAM_DATA__ME_RAM_DATA_MASK 0xffffffff +#define CP_ME_RAM_DATA__ME_RAM_DATA__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CPC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CPC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CPC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CPF_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CPF_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CPF_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CPF_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CGTT_CP_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_CP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_CP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON_MASK 0x20000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_PERFMON__SHIFT 0x1d +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_CP_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define CP_CE_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define CP_CE_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_CE_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_CE_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff +#define CP_MEC_ME1_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_MEC_ME1_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR_MASK 0x1ffff +#define CP_MEC_ME2_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define CP_MEC_ME2_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_PFP_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_MEC1_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT_MASK 0x2 +#define CP_MEC2_F32_INTERRUPT__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 +#define CP_MEC1_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 +#define CP_MEC1_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 +#define CP_MEC1_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 +#define CP_MEC1_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 +#define CP_MEC1_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 +#define CP_MEC1_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 +#define CP_MEC1_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 +#define CP_MEC1_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 +#define CP_MEC1_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 +#define CP_MEC1_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT_MASK 0x1 +#define CP_MEC2_F32_INT_DIS__EDC_ROQ_FED_INT__SHIFT 0x0 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT_MASK 0x2 +#define CP_MEC2_F32_INT_DIS__PRIV_REG_INT__SHIFT 0x1 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT_MASK 0x4 +#define CP_MEC2_F32_INT_DIS__RESERVED_BIT_ERR_INT__SHIFT 0x2 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT_MASK 0x8 +#define CP_MEC2_F32_INT_DIS__EDC_TC_FED_INT__SHIFT 0x3 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT_MASK 0x10 +#define CP_MEC2_F32_INT_DIS__EDC_GDS_FED_INT__SHIFT 0x4 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT_MASK 0x20 +#define CP_MEC2_F32_INT_DIS__EDC_SCRATCH_FED_INT__SHIFT 0x5 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT_MASK 0x40 +#define CP_MEC2_F32_INT_DIS__WAVE_RESTORE_INT__SHIFT 0x6 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT_MASK 0x80 +#define CP_MEC2_F32_INT_DIS__SUA_VIOLATION_INT__SHIFT 0x7 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT_MASK 0x100 +#define CP_MEC2_F32_INT_DIS__EDC_DMA_FED_INT__SHIFT 0x8 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT_MASK 0x200 +#define CP_MEC2_F32_INT_DIS__IQ_TIMER_INT__SHIFT 0x9 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0_MASK 0x1 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE0__SHIFT 0x0 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1_MASK 0x2 +#define CP_PWR_CNTL__GFX_CLK_HALT_ME0_PIPE1__SHIFT 0x1 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0_MASK 0x100 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE0__SHIFT 0x8 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1_MASK 0x200 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE1__SHIFT 0x9 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2_MASK 0x400 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE2__SHIFT 0xa +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3_MASK 0x800 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME1_PIPE3__SHIFT 0xb +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0_MASK 0x10000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE0__SHIFT 0x10 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1_MASK 0x20000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE1__SHIFT 0x11 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2_MASK 0x40000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE2__SHIFT 0x12 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3_MASK 0x80000 +#define CP_PWR_CNTL__CMP_CLK_HALT_ME2_PIPE3__SHIFT 0x13 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK 0x1 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_EN__SHIFT 0x0 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN_MASK 0x2 +#define CP_MEM_SLP_CNTL__CP_MEM_DS_EN__SHIFT 0x1 +#define CP_MEM_SLP_CNTL__RESERVED_MASK 0x7c +#define CP_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE_MASK 0x80 +#define CP_MEM_SLP_CNTL__CP_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY_MASK 0xff00 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_ON_DELAY__SHIFT 0x8 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY_MASK 0xff0000 +#define CP_MEM_SLP_CNTL__CP_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define CP_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 +#define CP_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE_MASK 0x3 +#define CP_ECC_FIRSTOCCURRENCE__INTERFACE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT_MASK 0xf0 +#define CP_ECC_FIRSTOCCURRENCE__CLIENT__SHIFT 0x4 +#define CP_ECC_FIRSTOCCURRENCE__ME_MASK 0x300 +#define CP_ECC_FIRSTOCCURRENCE__ME__SHIFT 0x8 +#define CP_ECC_FIRSTOCCURRENCE__PIPE_MASK 0xc00 +#define CP_ECC_FIRSTOCCURRENCE__PIPE__SHIFT 0xa +#define CP_ECC_FIRSTOCCURRENCE__QUEUE_MASK 0x7000 +#define CP_ECC_FIRSTOCCURRENCE__QUEUE__SHIFT 0xc +#define CP_ECC_FIRSTOCCURRENCE__VMID_MASK 0xf0000 +#define CP_ECC_FIRSTOCCURRENCE__VMID__SHIFT 0x10 +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE_MASK 0xffffffff +#define CP_ECC_FIRSTOCCURRENCE_RING0__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE_MASK 0xffffffff +#define CP_ECC_FIRSTOCCURRENCE_RING1__OBSOLETE__SHIFT 0x0 +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE_MASK 0xffffffff +#define CP_ECC_FIRSTOCCURRENCE_RING2__OBSOLETE__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__PERIOD_MASK 0xff +#define CP_PQ_WPTR_POLL_CNTL__PERIOD__SHIFT 0x0 +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE_MASK 0x40000000 +#define CP_PQ_WPTR_POLL_CNTL__POLL_ACTIVE__SHIFT 0x1e +#define CP_PQ_WPTR_POLL_CNTL__EN_MASK 0x80000000 +#define CP_PQ_WPTR_POLL_CNTL__EN__SHIFT 0x1f +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK_MASK 0xffffffff +#define CP_PQ_WPTR_POLL_CNTL1__QUEUE_MASK__SHIFT 0x0 +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CPC_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CPC_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CPC_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CPC_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CPC_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CPC_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CPC_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CPC_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CPC_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CPC_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CPC_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CPC_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME1_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME1_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME1_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME1_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME1_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME1_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME1_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME1_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME1_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME1_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE0_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE0_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE0_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE0_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE0_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE0_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE0_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE0_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE0_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE0_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE1_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE1_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE1_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE1_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE1_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE1_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE1_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE1_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE1_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE1_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE2_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE2_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE2_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE2_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE2_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE2_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE2_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE2_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE2_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE2_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE_MASK 0x1000 +#define CP_ME2_PIPE3_INT_CNTL__CMP_QUERY_STATUS_INT_ENABLE__SHIFT 0xc +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE_MASK 0x2000 +#define CP_ME2_PIPE3_INT_CNTL__DEQUEUE_REQUEST_INT_ENABLE__SHIFT 0xd +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE_MASK 0x4000 +#define CP_ME2_PIPE3_INT_CNTL__CP_ECC_ERROR_INT_ENABLE__SHIFT 0xe +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE_MASK 0x8000 +#define CP_ME2_PIPE3_INT_CNTL__SUA_VIOLATION_INT_ENABLE__SHIFT 0xf +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE_MASK 0x20000 +#define CP_ME2_PIPE3_INT_CNTL__WRM_POLL_TIMEOUT_INT_ENABLE__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE_MASK 0x800000 +#define CP_ME2_PIPE3_INT_CNTL__PRIV_REG_INT_ENABLE__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE_MASK 0x1000000 +#define CP_ME2_PIPE3_INT_CNTL__OPCODE_ERROR_INT_ENABLE__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE_MASK 0x4000000 +#define CP_ME2_PIPE3_INT_CNTL__TIME_STAMP_INT_ENABLE__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE_MASK 0x8000000 +#define CP_ME2_PIPE3_INT_CNTL__RESERVED_BIT_ERROR_INT_ENABLE__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE_MASK 0x20000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC2_INT_ENABLE__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE_MASK 0x40000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC1_INT_ENABLE__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE_MASK 0x80000000 +#define CP_ME2_PIPE3_INT_CNTL__GENERIC0_INT_ENABLE__SHIFT 0x1f +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CPC_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CPC_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CPC_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CPC_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CPC_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CPC_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CPC_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CPC_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CPC_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CPC_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CPC_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CPC_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CPC_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CPC_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CPC_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME1_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME1_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME1_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME1_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME1_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME1_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME1_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME1_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME1_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE0_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE0_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE0_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE0_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE0_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE0_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE0_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE0_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE0_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE0_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE1_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE1_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE1_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE1_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE1_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE1_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE1_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE1_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE1_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE1_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE2_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE2_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE2_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE2_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE2_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE2_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE2_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE2_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE2_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE2_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS_MASK 0x1000 +#define CP_ME2_PIPE3_INT_STATUS__CMP_QUERY_STATUS_INT_STATUS__SHIFT 0xc +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS_MASK 0x2000 +#define CP_ME2_PIPE3_INT_STATUS__DEQUEUE_REQUEST_INT_STATUS__SHIFT 0xd +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS_MASK 0x4000 +#define CP_ME2_PIPE3_INT_STATUS__CP_ECC_ERROR_INT_STATUS__SHIFT 0xe +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_PIPE3_INT_STATUS__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS_MASK 0x20000 +#define CP_ME2_PIPE3_INT_STATUS__WRM_POLL_TIMEOUT_INT_STATUS__SHIFT 0x11 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS_MASK 0x800000 +#define CP_ME2_PIPE3_INT_STATUS__PRIV_REG_INT_STATUS__SHIFT 0x17 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS_MASK 0x1000000 +#define CP_ME2_PIPE3_INT_STATUS__OPCODE_ERROR_INT_STATUS__SHIFT 0x18 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS_MASK 0x4000000 +#define CP_ME2_PIPE3_INT_STATUS__TIME_STAMP_INT_STATUS__SHIFT 0x1a +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS_MASK 0x8000000 +#define CP_ME2_PIPE3_INT_STATUS__RESERVED_BIT_ERROR_INT_STATUS__SHIFT 0x1b +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS_MASK 0x20000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC2_INT_STATUS__SHIFT 0x1d +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS_MASK 0x40000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC1_INT_STATUS__SHIFT 0x1e +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS_MASK 0x80000000 +#define CP_ME2_PIPE3_INT_STATUS__GENERIC0_INT_STATUS__SHIFT 0x1f +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 +#define CP_ME1_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 +#define CP_ME1_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_ME1_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME1_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_ME1_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_ME1_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_ME1_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_ME1_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_ME1_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_ME1_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED_MASK 0x1000 +#define CP_ME2_INT_STAT_DEBUG__CMP_QUERY_STATUS_INT_ASSERTED__SHIFT 0xc +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED_MASK 0x2000 +#define CP_ME2_INT_STAT_DEBUG__DEQUEUE_REQUEST_INT_ASSERTED__SHIFT 0xd +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_ME2_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS_MASK 0x8000 +#define CP_ME2_INT_STAT_DEBUG__SUA_VIOLATION_INT_STATUS__SHIFT 0xf +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_ME2_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_ME2_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_ME2_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_ME2_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_ME2_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_ME2_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME1_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME1_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT_MASK 0xff +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY1_CNT__SHIFT 0x0 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT_MASK 0xff00 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2A_CNT__SHIFT 0x8 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT_MASK 0xff0000 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY2B_CNT__SHIFT 0x10 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT_MASK 0xff000000 +#define CP_ME2_PIPE_PRIORITY_CNTS__PRIORITY3_CNT__SHIFT 0x18 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE0_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE1_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE2_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY_MASK 0x3 +#define CP_ME2_PIPE3_PRIORITY__PRIORITY__SHIFT 0x0 +#define CP_CE_PRGRM_CNTR_START__IP_START_MASK 0x7ff +#define CP_CE_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_PFP_PRGRM_CNTR_START__IP_START_MASK 0xfff +#define CP_PFP_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_ME_PRGRM_CNTR_START__IP_START_MASK 0xfff +#define CP_ME_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC1_PRGRM_CNTR_START__IP_START_MASK 0xffff +#define CP_MEC1_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_MEC2_PRGRM_CNTR_START__IP_START_MASK 0xffff +#define CP_MEC2_PRGRM_CNTR_START__IP_START__SHIFT 0x0 +#define CP_CE_INTR_ROUTINE_START__IR_START_MASK 0x7ff +#define CP_CE_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_PFP_INTR_ROUTINE_START__IR_START_MASK 0xfff +#define CP_PFP_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_ME_INTR_ROUTINE_START__IR_START_MASK 0xfff +#define CP_ME_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC1_INTR_ROUTINE_START__IR_START_MASK 0xffff +#define CP_MEC1_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_MEC2_INTR_ROUTINE_START__IR_START_MASK 0xffff +#define CP_MEC2_INTR_ROUTINE_START__IR_START__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX_MASK 0x7 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_WD_CNTX__SHIFT 0x0 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX_MASK 0x70 +#define CP_CONTEXT_CNTL__ME0PIPE0_MAX_PIPE_CNTX__SHIFT 0x4 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX_MASK 0x70000 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_WD_CNTX__SHIFT 0x10 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX_MASK 0x700000 +#define CP_CONTEXT_CNTL__ME0PIPE1_MAX_PIPE_CNTX__SHIFT 0x14 +#define CP_MAX_CONTEXT__MAX_CONTEXT_MASK 0x7 +#define CP_MAX_CONTEXT__MAX_CONTEXT__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD_MASK 0xff +#define CP_IQ_WAIT_TIME1__IB_OFFLOAD__SHIFT 0x0 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD_MASK 0xff00 +#define CP_IQ_WAIT_TIME1__ATOMIC_OFFLOAD__SHIFT 0x8 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD_MASK 0xff0000 +#define CP_IQ_WAIT_TIME1__WRM_OFFLOAD__SHIFT 0x10 +#define CP_IQ_WAIT_TIME1__GWS_MASK 0xff000000 +#define CP_IQ_WAIT_TIME1__GWS__SHIFT 0x18 +#define CP_IQ_WAIT_TIME2__QUE_SLEEP_MASK 0xff +#define CP_IQ_WAIT_TIME2__QUE_SLEEP__SHIFT 0x0 +#define CP_IQ_WAIT_TIME2__SCH_WAVE_MASK 0xff00 +#define CP_IQ_WAIT_TIME2__SCH_WAVE__SHIFT 0x8 +#define CP_IQ_WAIT_TIME2__SEM_REARM_MASK 0xff0000 +#define CP_IQ_WAIT_TIME2__SEM_REARM__SHIFT 0x10 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY_MASK 0xff000000 +#define CP_IQ_WAIT_TIME2__DEQ_RETRY__SHIFT 0x18 +#define CP_VMID_RESET__RESET_REQUEST_MASK 0xffff +#define CP_VMID_RESET__RESET_REQUEST__SHIFT 0x0 +#define CP_VMID_RESET__RESET_STATUS_MASK 0xffff0000 +#define CP_VMID_RESET__RESET_STATUS__SHIFT 0x10 +#define CP_VMID_PREEMPT__PREEMPT_REQUEST_MASK 0xffff +#define CP_VMID_PREEMPT__PREEMPT_REQUEST__SHIFT 0x0 +#define CP_VMID_PREEMPT__VIRT_COMMAND_MASK 0xf0000 +#define CP_VMID_PREEMPT__VIRT_COMMAND__SHIFT 0x10 +#define CP_VMID_STATUS__PREEMPT_DE_STATUS_MASK 0xffff +#define CP_VMID_STATUS__PREEMPT_DE_STATUS__SHIFT 0x0 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS_MASK 0xffff0000 +#define CP_VMID_STATUS__PREEMPT_CE_STATUS__SHIFT 0x10 +#define CPC_INT_CNTX_ID__CNTX_ID_MASK 0xfffffff +#define CPC_INT_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CPC_INT_CNTX_ID__QUEUE_ID_MASK 0x70000000 +#define CPC_INT_CNTX_ID__QUEUE_ID__SHIFT 0x1c +#define CP_PQ_STATUS__DOORBELL_UPDATED_MASK 0x1 +#define CP_PQ_STATUS__DOORBELL_UPDATED__SHIFT 0x0 +#define CP_PQ_STATUS__DOORBELL_ENABLE_MASK 0x2 +#define CP_PQ_STATUS__DOORBELL_ENABLE__SHIFT 0x1 +#define CP_CPC_IC_BASE_LO__IC_BASE_LO_MASK 0xfffff000 +#define CP_CPC_IC_BASE_LO__IC_BASE_LO__SHIFT 0xc +#define CP_CPC_IC_BASE_HI__IC_BASE_HI_MASK 0xffff +#define CP_CPC_IC_BASE_HI__IC_BASE_HI__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__VMID_MASK 0xf +#define CP_CPC_IC_BASE_CNTL__VMID__SHIFT 0x0 +#define CP_CPC_IC_BASE_CNTL__ATC_MASK 0x800000 +#define CP_CPC_IC_BASE_CNTL__ATC__SHIFT 0x17 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY_MASK 0x1000000 +#define CP_CPC_IC_BASE_CNTL__CACHE_POLICY__SHIFT 0x18 +#define CP_CPC_IC_BASE_CNTL__MTYPE_MASK 0x18000000 +#define CP_CPC_IC_BASE_CNTL__MTYPE__SHIFT 0x1b +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE_MASK 0x1 +#define CP_CPC_IC_OP_CNTL__INVALIDATE_CACHE__SHIFT 0x0 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE_MASK 0x10 +#define CP_CPC_IC_OP_CNTL__PRIME_ICACHE__SHIFT 0x4 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED_MASK 0x20 +#define CP_CPC_IC_OP_CNTL__ICACHE_PRIMED__SHIFT 0x5 +#define CP_CPC_STATUS__MEC1_BUSY_MASK 0x1 +#define CP_CPC_STATUS__MEC1_BUSY__SHIFT 0x0 +#define CP_CPC_STATUS__MEC2_BUSY_MASK 0x2 +#define CP_CPC_STATUS__MEC2_BUSY__SHIFT 0x1 +#define CP_CPC_STATUS__DC0_BUSY_MASK 0x4 +#define CP_CPC_STATUS__DC0_BUSY__SHIFT 0x2 +#define CP_CPC_STATUS__DC1_BUSY_MASK 0x8 +#define CP_CPC_STATUS__DC1_BUSY__SHIFT 0x3 +#define CP_CPC_STATUS__RCIU1_BUSY_MASK 0x10 +#define CP_CPC_STATUS__RCIU1_BUSY__SHIFT 0x4 +#define CP_CPC_STATUS__RCIU2_BUSY_MASK 0x20 +#define CP_CPC_STATUS__RCIU2_BUSY__SHIFT 0x5 +#define CP_CPC_STATUS__ROQ1_BUSY_MASK 0x40 +#define CP_CPC_STATUS__ROQ1_BUSY__SHIFT 0x6 +#define CP_CPC_STATUS__ROQ2_BUSY_MASK 0x80 +#define CP_CPC_STATUS__ROQ2_BUSY__SHIFT 0x7 +#define CP_CPC_STATUS__TCIU_BUSY_MASK 0x400 +#define CP_CPC_STATUS__TCIU_BUSY__SHIFT 0xa +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY_MASK 0x800 +#define CP_CPC_STATUS__SCRATCH_RAM_BUSY__SHIFT 0xb +#define CP_CPC_STATUS__QU_BUSY_MASK 0x1000 +#define CP_CPC_STATUS__QU_BUSY__SHIFT 0xc +#define CP_CPC_STATUS__ATCL2IU_BUSY_MASK 0x2000 +#define CP_CPC_STATUS__ATCL2IU_BUSY__SHIFT 0xd +#define CP_CPC_STATUS__CPG_CPC_BUSY_MASK 0x20000000 +#define CP_CPC_STATUS__CPG_CPC_BUSY__SHIFT 0x1d +#define CP_CPC_STATUS__CPF_CPC_BUSY_MASK 0x40000000 +#define CP_CPC_STATUS__CPF_CPC_BUSY__SHIFT 0x1e +#define CP_CPC_STATUS__CPC_BUSY_MASK 0x80000000 +#define CP_CPC_STATUS__CPC_BUSY__SHIFT 0x1f +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY_MASK 0x1 +#define CP_CPC_BUSY_STAT__MEC1_LOAD_BUSY__SHIFT 0x0 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY_MASK 0x2 +#define CP_CPC_BUSY_STAT__MEC1_SEMAPOHRE_BUSY__SHIFT 0x1 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY_MASK 0x4 +#define CP_CPC_BUSY_STAT__MEC1_MUTEX_BUSY__SHIFT 0x2 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY_MASK 0x8 +#define CP_CPC_BUSY_STAT__MEC1_MESSAGE_BUSY__SHIFT 0x3 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY_MASK 0x10 +#define CP_CPC_BUSY_STAT__MEC1_EOP_QUEUE_BUSY__SHIFT 0x4 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY_MASK 0x20 +#define CP_CPC_BUSY_STAT__MEC1_IQ_QUEUE_BUSY__SHIFT 0x5 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY_MASK 0x40 +#define CP_CPC_BUSY_STAT__MEC1_IB_QUEUE_BUSY__SHIFT 0x6 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY_MASK 0x80 +#define CP_CPC_BUSY_STAT__MEC1_TC_BUSY__SHIFT 0x7 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY_MASK 0x100 +#define CP_CPC_BUSY_STAT__MEC1_DMA_BUSY__SHIFT 0x8 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY_MASK 0x200 +#define CP_CPC_BUSY_STAT__MEC1_PARTIAL_FLUSH_BUSY__SHIFT 0x9 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY_MASK 0x400 +#define CP_CPC_BUSY_STAT__MEC1_PIPE0_BUSY__SHIFT 0xa +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY_MASK 0x800 +#define CP_CPC_BUSY_STAT__MEC1_PIPE1_BUSY__SHIFT 0xb +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY_MASK 0x1000 +#define CP_CPC_BUSY_STAT__MEC1_PIPE2_BUSY__SHIFT 0xc +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY_MASK 0x2000 +#define CP_CPC_BUSY_STAT__MEC1_PIPE3_BUSY__SHIFT 0xd +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY_MASK 0x10000 +#define CP_CPC_BUSY_STAT__MEC2_LOAD_BUSY__SHIFT 0x10 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY_MASK 0x20000 +#define CP_CPC_BUSY_STAT__MEC2_SEMAPOHRE_BUSY__SHIFT 0x11 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY_MASK 0x40000 +#define CP_CPC_BUSY_STAT__MEC2_MUTEX_BUSY__SHIFT 0x12 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY_MASK 0x80000 +#define CP_CPC_BUSY_STAT__MEC2_MESSAGE_BUSY__SHIFT 0x13 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY_MASK 0x100000 +#define CP_CPC_BUSY_STAT__MEC2_EOP_QUEUE_BUSY__SHIFT 0x14 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY_MASK 0x200000 +#define CP_CPC_BUSY_STAT__MEC2_IQ_QUEUE_BUSY__SHIFT 0x15 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY_MASK 0x400000 +#define CP_CPC_BUSY_STAT__MEC2_IB_QUEUE_BUSY__SHIFT 0x16 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY_MASK 0x800000 +#define CP_CPC_BUSY_STAT__MEC2_TC_BUSY__SHIFT 0x17 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY_MASK 0x1000000 +#define CP_CPC_BUSY_STAT__MEC2_DMA_BUSY__SHIFT 0x18 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY_MASK 0x2000000 +#define CP_CPC_BUSY_STAT__MEC2_PARTIAL_FLUSH_BUSY__SHIFT 0x19 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY_MASK 0x4000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE0_BUSY__SHIFT 0x1a +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY_MASK 0x8000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE1_BUSY__SHIFT 0x1b +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY_MASK 0x10000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE2_BUSY__SHIFT 0x1c +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY_MASK 0x20000000 +#define CP_CPC_BUSY_STAT__MEC2_PIPE3_BUSY__SHIFT 0x1d +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL_MASK 0x8 +#define CP_CPC_STALLED_STAT1__RCIU_TX_FREE_STALL__SHIFT 0x3 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION_MASK 0x10 +#define CP_CPC_STALLED_STAT1__RCIU_PRIV_VIOLATION__SHIFT 0x4 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL_MASK 0x40 +#define CP_CPC_STALLED_STAT1__TCIU_TX_FREE_STALL__SHIFT 0x6 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET_MASK 0x100 +#define CP_CPC_STALLED_STAT1__MEC1_DECODING_PACKET__SHIFT 0x8 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_MASK 0x200 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU__SHIFT 0x9 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ_MASK 0x400 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_RCIU_READ__SHIFT 0xa +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA_MASK 0x2000 +#define CP_CPC_STALLED_STAT1__MEC1_WAIT_ON_ROQ_DATA__SHIFT 0xd +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET_MASK 0x10000 +#define CP_CPC_STALLED_STAT1__MEC2_DECODING_PACKET__SHIFT 0x10 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_MASK 0x20000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU__SHIFT 0x11 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ_MASK 0x40000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_RCIU_READ__SHIFT 0x12 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA_MASK 0x200000 +#define CP_CPC_STALLED_STAT1__MEC2_WAIT_ON_ROQ_DATA__SHIFT 0x15 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x400000 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x16 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x800000 +#define CP_CPC_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x17 +#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x1000000 +#define CP_CPC_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x18 +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY_MASK 0x1 +#define CP_CPF_STATUS__POST_WPTR_GFX_BUSY__SHIFT 0x0 +#define CP_CPF_STATUS__CSF_BUSY_MASK 0x2 +#define CP_CPF_STATUS__CSF_BUSY__SHIFT 0x1 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY_MASK 0x10 +#define CP_CPF_STATUS__ROQ_ALIGN_BUSY__SHIFT 0x4 +#define CP_CPF_STATUS__ROQ_RING_BUSY_MASK 0x20 +#define CP_CPF_STATUS__ROQ_RING_BUSY__SHIFT 0x5 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY_MASK 0x40 +#define CP_CPF_STATUS__ROQ_INDIRECT1_BUSY__SHIFT 0x6 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY_MASK 0x80 +#define CP_CPF_STATUS__ROQ_INDIRECT2_BUSY__SHIFT 0x7 +#define CP_CPF_STATUS__ROQ_STATE_BUSY_MASK 0x100 +#define CP_CPF_STATUS__ROQ_STATE_BUSY__SHIFT 0x8 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY_MASK 0x200 +#define CP_CPF_STATUS__ROQ_CE_RING_BUSY__SHIFT 0x9 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY_MASK 0x400 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT1_BUSY__SHIFT 0xa +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY_MASK 0x800 +#define CP_CPF_STATUS__ROQ_CE_INDIRECT2_BUSY__SHIFT 0xb +#define CP_CPF_STATUS__SEMAPHORE_BUSY_MASK 0x1000 +#define CP_CPF_STATUS__SEMAPHORE_BUSY__SHIFT 0xc +#define CP_CPF_STATUS__INTERRUPT_BUSY_MASK 0x2000 +#define CP_CPF_STATUS__INTERRUPT_BUSY__SHIFT 0xd +#define CP_CPF_STATUS__TCIU_BUSY_MASK 0x4000 +#define CP_CPF_STATUS__TCIU_BUSY__SHIFT 0xe +#define CP_CPF_STATUS__HQD_BUSY_MASK 0x8000 +#define CP_CPF_STATUS__HQD_BUSY__SHIFT 0xf +#define CP_CPF_STATUS__PRT_BUSY_MASK 0x10000 +#define CP_CPF_STATUS__PRT_BUSY__SHIFT 0x10 +#define CP_CPF_STATUS__ATCL2IU_BUSY_MASK 0x20000 +#define CP_CPF_STATUS__ATCL2IU_BUSY__SHIFT 0x11 +#define CP_CPF_STATUS__CPF_GFX_BUSY_MASK 0x4000000 +#define CP_CPF_STATUS__CPF_GFX_BUSY__SHIFT 0x1a +#define CP_CPF_STATUS__CPF_CMP_BUSY_MASK 0x8000000 +#define CP_CPF_STATUS__CPF_CMP_BUSY__SHIFT 0x1b +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY_MASK 0x30000000 +#define CP_CPF_STATUS__GRBM_CPF_STAT_BUSY__SHIFT 0x1c +#define CP_CPF_STATUS__CPC_CPF_BUSY_MASK 0x40000000 +#define CP_CPF_STATUS__CPC_CPF_BUSY__SHIFT 0x1e +#define CP_CPF_STATUS__CPF_BUSY_MASK 0x80000000 +#define CP_CPF_STATUS__CPF_BUSY__SHIFT 0x1f +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 +#define CP_CPF_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY_MASK 0x2 +#define CP_CPF_BUSY_STAT__CSF_RING_BUSY__SHIFT 0x1 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY_MASK 0x4 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT1_BUSY__SHIFT 0x2 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY_MASK 0x8 +#define CP_CPF_BUSY_STAT__CSF_INDIRECT2_BUSY__SHIFT 0x3 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY_MASK 0x10 +#define CP_CPF_BUSY_STAT__CSF_STATE_BUSY__SHIFT 0x4 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY_MASK 0x20 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR1_BUSY__SHIFT 0x5 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY_MASK 0x40 +#define CP_CPF_BUSY_STAT__CSF_CE_INDR2_BUSY__SHIFT 0x6 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY_MASK 0x80 +#define CP_CPF_BUSY_STAT__CSF_ARBITER_BUSY__SHIFT 0x7 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY_MASK 0x100 +#define CP_CPF_BUSY_STAT__CSF_INPUT_BUSY__SHIFT 0x8 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS_MASK 0x200 +#define CP_CPF_BUSY_STAT__OUTSTANDING_READ_TAGS__SHIFT 0x9 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY_MASK 0x800 +#define CP_CPF_BUSY_STAT__HPD_PROCESSING_EOP_BUSY__SHIFT 0xb +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY_MASK 0x1000 +#define CP_CPF_BUSY_STAT__HQD_DISPATCH_BUSY__SHIFT 0xc +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY_MASK 0x2000 +#define CP_CPF_BUSY_STAT__HQD_IQ_TIMER_BUSY__SHIFT 0xd +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY_MASK 0x4000 +#define CP_CPF_BUSY_STAT__HQD_DMA_OFFLOAD_BUSY__SHIFT 0xe +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY_MASK 0x8000 +#define CP_CPF_BUSY_STAT__HQD_WAIT_SEMAPHORE_BUSY__SHIFT 0xf +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY_MASK 0x10000 +#define CP_CPF_BUSY_STAT__HQD_SIGNAL_SEMAPHORE_BUSY__SHIFT 0x10 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY_MASK 0x20000 +#define CP_CPF_BUSY_STAT__HQD_MESSAGE_BUSY__SHIFT 0x11 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY_MASK 0x40000 +#define CP_CPF_BUSY_STAT__HQD_PQ_FETCHER_BUSY__SHIFT 0x12 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY_MASK 0x80000 +#define CP_CPF_BUSY_STAT__HQD_IB_FETCHER_BUSY__SHIFT 0x13 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY_MASK 0x100000 +#define CP_CPF_BUSY_STAT__HQD_IQ_FETCHER_BUSY__SHIFT 0x14 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY_MASK 0x200000 +#define CP_CPF_BUSY_STAT__HQD_EOP_FETCHER_BUSY__SHIFT 0x15 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY_MASK 0x400000 +#define CP_CPF_BUSY_STAT__HQD_CONSUMED_RPTR_BUSY__SHIFT 0x16 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY_MASK 0x800000 +#define CP_CPF_BUSY_STAT__HQD_FETCHER_ARB_BUSY__SHIFT 0x17 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY_MASK 0x1000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_ALIGN_BUSY__SHIFT 0x18 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY_MASK 0x2000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_EOP_BUSY__SHIFT 0x19 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY_MASK 0x4000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IQ_BUSY__SHIFT 0x1a +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY_MASK 0x8000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_PQ_BUSY__SHIFT 0x1b +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY_MASK 0x10000000 +#define CP_CPF_BUSY_STAT__HQD_ROQ_IB_BUSY__SHIFT 0x1c +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY_MASK 0x20000000 +#define CP_CPF_BUSY_STAT__HQD_WPTR_POLL_BUSY__SHIFT 0x1d +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY_MASK 0x40000000 +#define CP_CPF_BUSY_STAT__HQD_PQ_BUSY__SHIFT 0x1e +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY_MASK 0x80000000 +#define CP_CPF_BUSY_STAT__HQD_IB_BUSY__SHIFT 0x1f +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA_MASK 0x1 +#define CP_CPF_STALLED_STAT1__RING_FETCHING_DATA__SHIFT 0x0 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA_MASK 0x2 +#define CP_CPF_STALLED_STAT1__INDR1_FETCHING_DATA__SHIFT 0x1 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA_MASK 0x4 +#define CP_CPF_STALLED_STAT1__INDR2_FETCHING_DATA__SHIFT 0x2 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA_MASK 0x8 +#define CP_CPF_STALLED_STAT1__STATE_FETCHING_DATA__SHIFT 0x3 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE_MASK 0x20 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_FREE__SHIFT 0x5 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS_MASK 0x40 +#define CP_CPF_STALLED_STAT1__TCIU_WAITING_ON_TAGS__SHIFT 0x6 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE_MASK 0x80 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_FREE__SHIFT 0x7 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS_MASK 0x100 +#define CP_CPF_STALLED_STAT1__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x8 +#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS_MASK 0x200 +#define CP_CPF_STALLED_STAT1__ATCL1_WAITING_ON_TRANS__SHIFT 0x9 +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f +#define CP_CPC_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK 0x10 +#define CP_MEC_CNTL__MEC_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK 0x10000 +#define CP_MEC_CNTL__MEC_ME1_PIPE0_RESET__SHIFT 0x10 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK 0x20000 +#define CP_MEC_CNTL__MEC_ME1_PIPE1_RESET__SHIFT 0x11 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK 0x40000 +#define CP_MEC_CNTL__MEC_ME1_PIPE2_RESET__SHIFT 0x12 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK 0x80000 +#define CP_MEC_CNTL__MEC_ME1_PIPE3_RESET__SHIFT 0x13 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK 0x100000 +#define CP_MEC_CNTL__MEC_ME2_PIPE0_RESET__SHIFT 0x14 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK 0x200000 +#define CP_MEC_CNTL__MEC_ME2_PIPE1_RESET__SHIFT 0x15 +#define CP_MEC_CNTL__MEC_ME2_HALT_MASK 0x10000000 +#define CP_MEC_CNTL__MEC_ME2_HALT__SHIFT 0x1c +#define CP_MEC_CNTL__MEC_ME2_STEP_MASK 0x20000000 +#define CP_MEC_CNTL__MEC_ME2_STEP__SHIFT 0x1d +#define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 +#define CP_MEC_CNTL__MEC_ME1_HALT__SHIFT 0x1e +#define CP_MEC_CNTL__MEC_ME1_STEP_MASK 0x80000000 +#define CP_MEC_CNTL__MEC_ME1_STEP__SHIFT 0x1f +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff +#define CP_MEC_ME1_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP_MASK 0xffffffff +#define CP_MEC_ME2_HEADER_DUMP__HEADER_DUMP__SHIFT 0x0 +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0x1ff +#define CP_CPC_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff +#define CP_CPC_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPG_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPG_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPG_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPG_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPG_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPG_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPG_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define CPF_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPF_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPF_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3f +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xfc00 +#define CPF_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xfc00 +#define CPF_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define CPF_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define CPF_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define CPF_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CP_CPC_HALT_HYST_COUNT__COUNT_MASK 0xf +#define CP_CPC_HALT_HYST_COUNT__COUNT__SHIFT 0x0 +#define CP_DRAW_OBJECT__OBJECT_MASK 0xffffffff +#define CP_DRAW_OBJECT__OBJECT__SHIFT 0x0 +#define CP_DRAW_OBJECT_COUNTER__COUNT_MASK 0xffff +#define CP_DRAW_OBJECT_COUNTER__COUNT__SHIFT 0x0 +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI_MASK 0xffffffff +#define CP_DRAW_WINDOW_MASK_HI__WINDOW_MASK_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_HI__WINDOW_HI_MASK 0xffffffff +#define CP_DRAW_WINDOW_HI__WINDOW_HI__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MIN_MASK 0xffff +#define CP_DRAW_WINDOW_LO__MIN__SHIFT 0x0 +#define CP_DRAW_WINDOW_LO__MAX_MASK 0xffff0000 +#define CP_DRAW_WINDOW_LO__MAX__SHIFT 0x10 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX_MASK 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MAX__SHIFT 0x0 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN_MASK 0x2 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_LO_MIN__SHIFT 0x1 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI_MASK 0x4 +#define CP_DRAW_WINDOW_CNTL__DISABLE_DRAW_WINDOW_HI__SHIFT 0x2 +#define CP_DRAW_WINDOW_CNTL__MODE_MASK 0x100 +#define CP_DRAW_WINDOW_CNTL__MODE__SHIFT 0x8 +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE_MASK 0xffffffff +#define CP_PRT_LOD_STATS_CNTL0__BU_SIZE__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO_MASK 0xffffffff +#define CP_PRT_LOD_STATS_CNTL1__BASE_LO__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI_MASK 0x3 +#define CP_PRT_LOD_STATS_CNTL2__BASE_HI__SHIFT 0x0 +#define CP_PRT_LOD_STATS_CNTL2__INTERVAL_MASK 0x3fc +#define CP_PRT_LOD_STATS_CNTL2__INTERVAL__SHIFT 0x2 +#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT_MASK 0x3fc00 +#define CP_PRT_LOD_STATS_CNTL2__RESET_CNT__SHIFT 0xa +#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE_MASK 0x40000 +#define CP_PRT_LOD_STATS_CNTL2__RESET_FORCE__SHIFT 0x12 +#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET_MASK 0x80000 +#define CP_PRT_LOD_STATS_CNTL2__REPORT_AND_RESET__SHIFT 0x13 +#define CP_PRT_LOD_STATS_CNTL2__MC_VMID_MASK 0x7800000 +#define CP_PRT_LOD_STATS_CNTL2__MC_VMID__SHIFT 0x17 +#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY_MASK 0x10000000 +#define CP_PRT_LOD_STATS_CNTL2__CACHE_POLICY__SHIFT 0x1c +#define CP_PRT_LOD_STATS_CNTL2__MTYPE_MASK 0xc0000000 +#define CP_PRT_LOD_STATS_CNTL2__MTYPE__SHIFT 0x1e +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT_MASK 0xffffffff +#define CP_CE_COMPARE_COUNT__COMPARE_COUNT__SHIFT 0x0 +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff +#define CP_CE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT_MASK 0xffffffff +#define CP_DE_CE_COUNT__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT_MASK 0xffffffff +#define CP_DE_LAST_INVAL_COUNT__LAST_INVAL_COUNT__SHIFT 0x0 +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT_MASK 0xffffffff +#define CP_DE_DE_COUNT__DRAW_ENGINE_COUNT__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP_MASK 0x7f +#define CP_EOP_DONE_EVENT_CNTL__WBINV_TC_OP__SHIFT 0x0 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA_MASK 0x3f000 +#define CP_EOP_DONE_EVENT_CNTL__WBINV_ACTION_ENA__SHIFT 0xc +#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL_MASK 0x2000000 +#define CP_EOP_DONE_EVENT_CNTL__CACHE_CONTROL__SHIFT 0x19 +#define CP_EOP_DONE_EVENT_CNTL__MTYPE_MASK 0x18000000 +#define CP_EOP_DONE_EVENT_CNTL__MTYPE__SHIFT 0x1b +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID_MASK 0xffff +#define CP_EOP_DONE_DATA_CNTL__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_DATA_CNTL__DST_SEL_MASK 0x30000 +#define CP_EOP_DONE_DATA_CNTL__DST_SEL__SHIFT 0x10 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL_MASK 0x7000000 +#define CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT 0x18 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL_MASK 0xe0000000 +#define CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT 0x1d +#define CP_EOP_DONE_CNTX_ID__CNTX_ID_MASK 0xfffffff +#define CP_EOP_DONE_CNTX_ID__CNTX_ID__SHIFT 0x0 +#define CP_EOP_DONE_ADDR_LO__ADDR_LO_MASK 0xfffffffc +#define CP_EOP_DONE_ADDR_LO__ADDR_LO__SHIFT 0x2 +#define CP_EOP_DONE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_EOP_DONE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_EOP_DONE_DATA_LO__DATA_LO_MASK 0xffffffff +#define CP_EOP_DONE_DATA_LO__DATA_LO__SHIFT 0x0 +#define CP_EOP_DONE_DATA_HI__DATA_HI_MASK 0xffffffff +#define CP_EOP_DONE_DATA_HI__DATA_HI__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO_MASK 0xffffffff +#define CP_EOP_LAST_FENCE_LO__LAST_FENCE_LO__SHIFT 0x0 +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI_MASK 0xffffffff +#define CP_EOP_LAST_FENCE_HI__LAST_FENCE_HI__SHIFT 0x0 +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO_MASK 0xfffffffc +#define CP_STREAM_OUT_ADDR_LO__STREAM_OUT_ADDR_LO__SHIFT 0x2 +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI_MASK 0xffff +#define CP_STREAM_OUT_ADDR_HI__STREAM_OUT_ADDR_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT0_LO__NUM_PRIM_WRITTEN_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT0_HI__NUM_PRIM_WRITTEN_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT0_LO__NUM_PRIM_NEEDED_CNT0_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT0_HI__NUM_PRIM_NEEDED_CNT0_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT1_LO__NUM_PRIM_WRITTEN_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT1_HI__NUM_PRIM_WRITTEN_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT1_LO__NUM_PRIM_NEEDED_CNT1_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT1_HI__NUM_PRIM_NEEDED_CNT1_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT2_LO__NUM_PRIM_WRITTEN_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT2_HI__NUM_PRIM_WRITTEN_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT2_LO__NUM_PRIM_NEEDED_CNT2_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT2_HI__NUM_PRIM_NEEDED_CNT2_HI__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT3_LO__NUM_PRIM_WRITTEN_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI_MASK 0xffffffff +#define CP_NUM_PRIM_WRITTEN_COUNT3_HI__NUM_PRIM_WRITTEN_CNT3_HI__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT3_LO__NUM_PRIM_NEEDED_CNT3_LO__SHIFT 0x0 +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI_MASK 0xffffffff +#define CP_NUM_PRIM_NEEDED_COUNT3_HI__NUM_PRIM_NEEDED_CNT3_HI__SHIFT 0x0 +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO_MASK 0xfffffffc +#define CP_PIPE_STATS_ADDR_LO__PIPE_STATS_ADDR_LO__SHIFT 0x2 +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI_MASK 0xffff +#define CP_PIPE_STATS_ADDR_HI__PIPE_STATS_ADDR_HI__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO_MASK 0xffffffff +#define CP_VGT_IAVERT_COUNT_LO__IAVERT_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI_MASK 0xffffffff +#define CP_VGT_IAVERT_COUNT_HI__IAVERT_COUNT_HI__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO_MASK 0xffffffff +#define CP_VGT_IAPRIM_COUNT_LO__IAPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI_MASK 0xffffffff +#define CP_VGT_IAPRIM_COUNT_HI__IAPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO_MASK 0xffffffff +#define CP_VGT_GSPRIM_COUNT_LO__GSPRIM_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI_MASK 0xffffffff +#define CP_VGT_GSPRIM_COUNT_HI__GSPRIM_COUNT_HI__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_VSINVOC_COUNT_LO__VSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_VSINVOC_COUNT_HI__VSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_GSINVOC_COUNT_LO__GSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_GSINVOC_COUNT_HI__GSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_HSINVOC_COUNT_LO__HSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_HSINVOC_COUNT_HI__HSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_DSINVOC_COUNT_LO__DSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_DSINVOC_COUNT_HI__DSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO_MASK 0xffffffff +#define CP_PA_CINVOC_COUNT_LO__CINVOC_COUNT_LO__SHIFT 0x0 +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI_MASK 0xffffffff +#define CP_PA_CINVOC_COUNT_HI__CINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO_MASK 0xffffffff +#define CP_PA_CPRIM_COUNT_LO__CPRIM_COUNT_LO__SHIFT 0x0 +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI_MASK 0xffffffff +#define CP_PA_CPRIM_COUNT_HI__CPRIM_COUNT_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT0_LO__PSINVOC_COUNT0_LO__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT0_HI__PSINVOC_COUNT0_HI__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT1_LO__OBSOLETE__SHIFT 0x0 +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE_MASK 0xffffffff +#define CP_SC_PSINVOC_COUNT1_HI__OBSOLETE__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO_MASK 0xffffffff +#define CP_VGT_CSINVOC_COUNT_LO__CSINVOC_COUNT_LO__SHIFT 0x0 +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI_MASK 0xffffffff +#define CP_VGT_CSINVOC_COUNT_HI__CSINVOC_COUNT_HI__SHIFT 0x0 +#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL_MASK 0x2000000 +#define CP_PIPE_STATS_CONTROL__CACHE_CONTROL__SHIFT 0x19 +#define CP_PIPE_STATS_CONTROL__MTYPE_MASK 0x18000000 +#define CP_PIPE_STATS_CONTROL__MTYPE__SHIFT 0x1b +#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL_MASK 0x2000000 +#define CP_STREAM_OUT_CONTROL__CACHE_CONTROL__SHIFT 0x19 +#define CP_STREAM_OUT_CONTROL__MTYPE_MASK 0x18000000 +#define CP_STREAM_OUT_CONTROL__MTYPE__SHIFT 0x1b +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE_MASK 0x1 +#define CP_STRMOUT_CNTL__OFFSET_UPDATE_DONE__SHIFT 0x0 +#define SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff +#define SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff +#define SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff +#define SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff +#define SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff +#define SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff +#define SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff +#define SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff +#define SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_UMSK_MASK 0xff +#define SCRATCH_UMSK__OBSOLETE_UMSK__SHIFT 0x0 +#define SCRATCH_UMSK__OBSOLETE_SWAP_MASK 0x30000 +#define SCRATCH_UMSK__OBSOLETE_SWAP__SHIFT 0x10 +#define SCRATCH_ADDR__OBSOLETE_ADDR_MASK 0xffffffff +#define SCRATCH_ADDR__OBSOLETE_ADDR__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_PFP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_PFP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_PFP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO_MASK 0xfffffffc +#define CP_APPEND_ADDR_LO__MEM_ADDR_LO__SHIFT 0x2 +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI_MASK 0xffff +#define CP_APPEND_ADDR_HI__MEM_ADDR_HI__SHIFT 0x0 +#define CP_APPEND_ADDR_HI__CS_PS_SEL_MASK 0x10000 +#define CP_APPEND_ADDR_HI__CS_PS_SEL__SHIFT 0x10 +#define CP_APPEND_ADDR_HI__CACHE_POLICY_MASK 0x2000000 +#define CP_APPEND_ADDR_HI__CACHE_POLICY__SHIFT 0x19 +#define CP_APPEND_ADDR_HI__MTYPE_MASK 0x18000000 +#define CP_APPEND_ADDR_HI__MTYPE__SHIFT 0x1b +#define CP_APPEND_ADDR_HI__COMMAND_MASK 0xe0000000 +#define CP_APPEND_ADDR_HI__COMMAND__SHIFT 0x1d +#define CP_APPEND_DATA__DATA_MASK 0xffffffff +#define CP_APPEND_DATA__DATA__SHIFT 0x0 +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE_MASK 0xffffffff +#define CP_APPEND_LAST_CS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE_MASK 0xffffffff +#define CP_APPEND_LAST_PS_FENCE__LAST_FENCE__SHIFT 0x0 +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO_MASK 0xffffffff +#define CP_ME_ATOMIC_PREOP_LO__ATOMIC_PREOP_LO__SHIFT 0x0 +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI_MASK 0xffffffff +#define CP_ME_ATOMIC_PREOP_HI__ATOMIC_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC0_PREOP_LO__GDS_ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC0_PREOP_HI__GDS_ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC1_PREOP_LO__GDS_ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_ME_GDS_ATOMIC1_PREOP_HI__GDS_ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP_MASK 0x3 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_SWAP__SHIFT 0x0 +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO_MASK 0xfffffffc +#define CP_ME_MC_WADDR_LO__ME_MC_WADDR_LO__SHIFT 0x2 +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI_MASK 0xffff +#define CP_ME_MC_WADDR_HI__ME_MC_WADDR_HI__SHIFT 0x0 +#define CP_ME_MC_WADDR_HI__MTYPE_MASK 0x300000 +#define CP_ME_MC_WADDR_HI__MTYPE__SHIFT 0x14 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY_MASK 0x400000 +#define CP_ME_MC_WADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO_MASK 0xffffffff +#define CP_ME_MC_WDATA_LO__ME_MC_WDATA_LO__SHIFT 0x0 +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI_MASK 0xffffffff +#define CP_ME_MC_WDATA_HI__ME_MC_WDATA_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP_MASK 0x3 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_SWAP__SHIFT 0x0 +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO_MASK 0xfffffffc +#define CP_ME_MC_RADDR_LO__ME_MC_RADDR_LO__SHIFT 0x2 +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI_MASK 0xffff +#define CP_ME_MC_RADDR_HI__ME_MC_RADDR_HI__SHIFT 0x0 +#define CP_ME_MC_RADDR_HI__MTYPE_MASK 0x300000 +#define CP_ME_MC_RADDR_HI__MTYPE__SHIFT 0x14 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY_MASK 0x400000 +#define CP_ME_MC_RADDR_HI__CACHE_POLICY__SHIFT 0x16 +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER_MASK 0xffffffff +#define CP_SEM_WAIT_TIMER__SEM_WAIT_TIMER__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 +#define CP_SIG_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff +#define CP_SIG_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 +#define CP_SIG_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 +#define CP_SIG_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 +#define CP_SIG_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 +#define CP_SIG_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP_MASK 0x3 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_SWAP__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO_MASK 0xfffffff8 +#define CP_WAIT_SEM_ADDR_LO__SEM_ADDR_LO__SHIFT 0x3 +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI_MASK 0xffff +#define CP_WAIT_SEM_ADDR_HI__SEM_ADDR_HI__SHIFT 0x0 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX_MASK 0x10000 +#define CP_WAIT_SEM_ADDR_HI__SEM_USE_MAILBOX__SHIFT 0x10 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE_MASK 0x100000 +#define CP_WAIT_SEM_ADDR_HI__SEM_SIGNAL_TYPE__SHIFT 0x14 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE_MASK 0x3000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_CLIENT_CODE__SHIFT 0x18 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT_MASK 0xe0000000 +#define CP_WAIT_SEM_ADDR_HI__SEM_SELECT__SHIFT 0x1d +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT_MASK 0xffffffff +#define CP_WAIT_REG_MEM_TIMEOUT__WAIT_REG_MEM_TIMEOUT__SHIFT 0x0 +#define CP_COHER_START_DELAY__START_DELAY_COUNT_MASK 0x3f +#define CP_COHER_START_DELAY__START_DELAY_COUNT__SHIFT 0x0 +#define CP_COHER_CNTL__DEST_BASE_0_ENA_MASK 0x1 +#define CP_COHER_CNTL__DEST_BASE_0_ENA__SHIFT 0x0 +#define CP_COHER_CNTL__DEST_BASE_1_ENA_MASK 0x2 +#define CP_COHER_CNTL__DEST_BASE_1_ENA__SHIFT 0x1 +#define CP_COHER_CNTL__TC_SD_ACTION_ENA_MASK 0x4 +#define CP_COHER_CNTL__TC_SD_ACTION_ENA__SHIFT 0x2 +#define CP_COHER_CNTL__TC_NC_ACTION_ENA_MASK 0x8 +#define CP_COHER_CNTL__TC_NC_ACTION_ENA__SHIFT 0x3 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA_MASK 0x40 +#define CP_COHER_CNTL__CB0_DEST_BASE_ENA__SHIFT 0x6 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA_MASK 0x80 +#define CP_COHER_CNTL__CB1_DEST_BASE_ENA__SHIFT 0x7 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA_MASK 0x100 +#define CP_COHER_CNTL__CB2_DEST_BASE_ENA__SHIFT 0x8 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA_MASK 0x200 +#define CP_COHER_CNTL__CB3_DEST_BASE_ENA__SHIFT 0x9 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA_MASK 0x400 +#define CP_COHER_CNTL__CB4_DEST_BASE_ENA__SHIFT 0xa +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA_MASK 0x800 +#define CP_COHER_CNTL__CB5_DEST_BASE_ENA__SHIFT 0xb +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA_MASK 0x1000 +#define CP_COHER_CNTL__CB6_DEST_BASE_ENA__SHIFT 0xc +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA_MASK 0x2000 +#define CP_COHER_CNTL__CB7_DEST_BASE_ENA__SHIFT 0xd +#define CP_COHER_CNTL__DB_DEST_BASE_ENA_MASK 0x4000 +#define CP_COHER_CNTL__DB_DEST_BASE_ENA__SHIFT 0xe +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA_MASK 0x8000 +#define CP_COHER_CNTL__TCL1_VOL_ACTION_ENA__SHIFT 0xf +#define CP_COHER_CNTL__TC_WB_ACTION_ENA_MASK 0x40000 +#define CP_COHER_CNTL__TC_WB_ACTION_ENA__SHIFT 0x12 +#define CP_COHER_CNTL__DEST_BASE_2_ENA_MASK 0x80000 +#define CP_COHER_CNTL__DEST_BASE_2_ENA__SHIFT 0x13 +#define CP_COHER_CNTL__DEST_BASE_3_ENA_MASK 0x200000 +#define CP_COHER_CNTL__DEST_BASE_3_ENA__SHIFT 0x15 +#define CP_COHER_CNTL__TCL1_ACTION_ENA_MASK 0x400000 +#define CP_COHER_CNTL__TCL1_ACTION_ENA__SHIFT 0x16 +#define CP_COHER_CNTL__TC_ACTION_ENA_MASK 0x800000 +#define CP_COHER_CNTL__TC_ACTION_ENA__SHIFT 0x17 +#define CP_COHER_CNTL__CB_ACTION_ENA_MASK 0x2000000 +#define CP_COHER_CNTL__CB_ACTION_ENA__SHIFT 0x19 +#define CP_COHER_CNTL__DB_ACTION_ENA_MASK 0x4000000 +#define CP_COHER_CNTL__DB_ACTION_ENA__SHIFT 0x1a +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA_MASK 0x8000000 +#define CP_COHER_CNTL__SH_KCACHE_ACTION_ENA__SHIFT 0x1b +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA_MASK 0x10000000 +#define CP_COHER_CNTL__SH_KCACHE_VOL_ACTION_ENA__SHIFT 0x1c +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA_MASK 0x20000000 +#define CP_COHER_CNTL__SH_ICACHE_ACTION_ENA__SHIFT 0x1d +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA_MASK 0x40000000 +#define CP_COHER_CNTL__SH_KCACHE_WB_ACTION_ENA__SHIFT 0x1e +#define CP_COHER_CNTL__SH_SD_ACTION_ENA_MASK 0x80000000 +#define CP_COHER_CNTL__SH_SD_ACTION_ENA__SHIFT 0x1f +#define CP_COHER_SIZE__COHER_SIZE_256B_MASK 0xffffffff +#define CP_COHER_SIZE__COHER_SIZE_256B__SHIFT 0x0 +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B_MASK 0xff +#define CP_COHER_SIZE_HI__COHER_SIZE_HI_256B__SHIFT 0x0 +#define CP_COHER_BASE__COHER_BASE_256B_MASK 0xffffffff +#define CP_COHER_BASE__COHER_BASE_256B__SHIFT 0x0 +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B_MASK 0xff +#define CP_COHER_BASE_HI__COHER_BASE_HI_256B__SHIFT 0x0 +#define CP_COHER_STATUS__MATCHING_GFX_CNTX_MASK 0xff +#define CP_COHER_STATUS__MATCHING_GFX_CNTX__SHIFT 0x0 +#define CP_COHER_STATUS__MEID_MASK 0x3000000 +#define CP_COHER_STATUS__MEID__SHIFT 0x18 +#define CP_COHER_STATUS__PHASE1_STATUS_MASK 0x40000000 +#define CP_COHER_STATUS__PHASE1_STATUS__SHIFT 0x1e +#define CP_COHER_STATUS__STATUS_MASK 0x80000000 +#define CP_COHER_STATUS__STATUS__SHIFT 0x1f +#define COHER_DEST_BASE_0__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_0__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_1__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_1__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_2__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_2__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_3__DEST_BASE_256B_MASK 0xffffffff +#define COHER_DEST_BASE_3__DEST_BASE_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_0__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_1__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_2__DEST_BASE_HI_256B__SHIFT 0x0 +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B_MASK 0xffffffff +#define COHER_DEST_BASE_HI_3__DEST_BASE_HI_256B__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR_MASK 0xffffffff +#define CP_DMA_ME_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff +#define CP_DMA_ME_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR__DST_ADDR_MASK 0xffffffff +#define CP_DMA_ME_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff +#define CP_DMA_ME_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_ME_CONTROL__SRC_MTYPE_MASK 0xc00 +#define CP_DMA_ME_CONTROL__SRC_MTYPE__SHIFT 0xa +#define CP_DMA_ME_CONTROL__SRC_ATC_MASK 0x1000 +#define CP_DMA_ME_CONTROL__SRC_ATC__SHIFT 0xc +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 +#define CP_DMA_ME_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_ME_CONTROL__DST_SELECT_MASK 0x300000 +#define CP_DMA_ME_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_ME_CONTROL__DST_MTYPE_MASK 0xc00000 +#define CP_DMA_ME_CONTROL__DST_MTYPE__SHIFT 0x16 +#define CP_DMA_ME_CONTROL__DST_ATC_MASK 0x1000000 +#define CP_DMA_ME_CONTROL__DST_ATC__SHIFT 0x18 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 +#define CP_DMA_ME_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_ME_CONTROL__SRC_SELECT_MASK 0x60000000 +#define CP_DMA_ME_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__BYTE_COUNT_MASK 0x1fffff +#define CP_DMA_ME_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_ME_COMMAND__DIS_WC_MASK 0x200000 +#define CP_DMA_ME_COMMAND__DIS_WC__SHIFT 0x15 +#define CP_DMA_ME_COMMAND__SRC_SWAP_MASK 0xc00000 +#define CP_DMA_ME_COMMAND__SRC_SWAP__SHIFT 0x16 +#define CP_DMA_ME_COMMAND__DST_SWAP_MASK 0x3000000 +#define CP_DMA_ME_COMMAND__DST_SWAP__SHIFT 0x18 +#define CP_DMA_ME_COMMAND__SAS_MASK 0x4000000 +#define CP_DMA_ME_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_ME_COMMAND__DAS_MASK 0x8000000 +#define CP_DMA_ME_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_ME_COMMAND__SAIC_MASK 0x10000000 +#define CP_DMA_ME_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_ME_COMMAND__DAIC_MASK 0x20000000 +#define CP_DMA_ME_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_ME_COMMAND__RAW_WAIT_MASK 0x40000000 +#define CP_DMA_ME_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR_MASK 0xffffffff +#define CP_DMA_PFP_SRC_ADDR__SRC_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI_MASK 0xffff +#define CP_DMA_PFP_SRC_ADDR_HI__SRC_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR__DST_ADDR_MASK 0xffffffff +#define CP_DMA_PFP_DST_ADDR__DST_ADDR__SHIFT 0x0 +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI_MASK 0xffff +#define CP_DMA_PFP_DST_ADDR_HI__DST_ADDR_HI__SHIFT 0x0 +#define CP_DMA_PFP_CONTROL__SRC_MTYPE_MASK 0xc00 +#define CP_DMA_PFP_CONTROL__SRC_MTYPE__SHIFT 0xa +#define CP_DMA_PFP_CONTROL__SRC_ATC_MASK 0x1000 +#define CP_DMA_PFP_CONTROL__SRC_ATC__SHIFT 0xc +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY_MASK 0x2000 +#define CP_DMA_PFP_CONTROL__SRC_CACHE_POLICY__SHIFT 0xd +#define CP_DMA_PFP_CONTROL__DST_SELECT_MASK 0x300000 +#define CP_DMA_PFP_CONTROL__DST_SELECT__SHIFT 0x14 +#define CP_DMA_PFP_CONTROL__DST_MTYPE_MASK 0xc00000 +#define CP_DMA_PFP_CONTROL__DST_MTYPE__SHIFT 0x16 +#define CP_DMA_PFP_CONTROL__DST_ATC_MASK 0x1000000 +#define CP_DMA_PFP_CONTROL__DST_ATC__SHIFT 0x18 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY_MASK 0x2000000 +#define CP_DMA_PFP_CONTROL__DST_CACHE_POLICY__SHIFT 0x19 +#define CP_DMA_PFP_CONTROL__SRC_SELECT_MASK 0x60000000 +#define CP_DMA_PFP_CONTROL__SRC_SELECT__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__BYTE_COUNT_MASK 0x1fffff +#define CP_DMA_PFP_COMMAND__BYTE_COUNT__SHIFT 0x0 +#define CP_DMA_PFP_COMMAND__DIS_WC_MASK 0x200000 +#define CP_DMA_PFP_COMMAND__DIS_WC__SHIFT 0x15 +#define CP_DMA_PFP_COMMAND__SRC_SWAP_MASK 0xc00000 +#define CP_DMA_PFP_COMMAND__SRC_SWAP__SHIFT 0x16 +#define CP_DMA_PFP_COMMAND__DST_SWAP_MASK 0x3000000 +#define CP_DMA_PFP_COMMAND__DST_SWAP__SHIFT 0x18 +#define CP_DMA_PFP_COMMAND__SAS_MASK 0x4000000 +#define CP_DMA_PFP_COMMAND__SAS__SHIFT 0x1a +#define CP_DMA_PFP_COMMAND__DAS_MASK 0x8000000 +#define CP_DMA_PFP_COMMAND__DAS__SHIFT 0x1b +#define CP_DMA_PFP_COMMAND__SAIC_MASK 0x10000000 +#define CP_DMA_PFP_COMMAND__SAIC__SHIFT 0x1c +#define CP_DMA_PFP_COMMAND__DAIC_MASK 0x20000000 +#define CP_DMA_PFP_COMMAND__DAIC__SHIFT 0x1d +#define CP_DMA_PFP_COMMAND__RAW_WAIT_MASK 0x40000000 +#define CP_DMA_PFP_COMMAND__RAW_WAIT__SHIFT 0x1e +#define CP_DMA_CNTL__MIN_AVAILSZ_MASK 0x30 +#define CP_DMA_CNTL__MIN_AVAILSZ__SHIFT 0x4 +#define CP_DMA_CNTL__BUFFER_DEPTH_MASK 0xf0000 +#define CP_DMA_CNTL__BUFFER_DEPTH__SHIFT 0x10 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY_MASK 0x10000000 +#define CP_DMA_CNTL__PIO_FIFO_EMPTY__SHIFT 0x1c +#define CP_DMA_CNTL__PIO_FIFO_FULL_MASK 0x20000000 +#define CP_DMA_CNTL__PIO_FIFO_FULL__SHIFT 0x1d +#define CP_DMA_CNTL__PIO_COUNT_MASK 0xc0000000 +#define CP_DMA_CNTL__PIO_COUNT__SHIFT 0x1e +#define CP_DMA_READ_TAGS__DMA_READ_TAG_MASK 0x3ffffff +#define CP_DMA_READ_TAGS__DMA_READ_TAG__SHIFT 0x0 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID_MASK 0x10000000 +#define CP_DMA_READ_TAGS__DMA_READ_TAG_VALID__SHIFT 0x1c +#define CP_PFP_IB_CONTROL__IB_EN_MASK 0xff +#define CP_PFP_IB_CONTROL__IB_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN_MASK 0x1 +#define CP_PFP_LOAD_CONTROL__CONFIG_REG_EN__SHIFT 0x0 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN_MASK 0x2 +#define CP_PFP_LOAD_CONTROL__CNTX_REG_EN__SHIFT 0x1 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN_MASK 0x10000 +#define CP_PFP_LOAD_CONTROL__SH_GFX_REG_EN__SHIFT 0x10 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN_MASK 0x1000000 +#define CP_PFP_LOAD_CONTROL__SH_CS_REG_EN__SHIFT 0x18 +#define CP_SCRATCH_INDEX__SCRATCH_INDEX_MASK 0xff +#define CP_SCRATCH_INDEX__SCRATCH_INDEX__SHIFT 0x0 +#define CP_SCRATCH_DATA__SCRATCH_DATA_MASK 0xffffffff +#define CP_SCRATCH_DATA__SCRATCH_DATA__SHIFT 0x0 +#define CP_RB_OFFSET__RB_OFFSET_MASK 0xfffff +#define CP_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff +#define CP_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff +#define CP_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN_MASK 0xfffff +#define CP_IB1_PREAMBLE_BEGIN__IB1_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END_MASK 0xfffff +#define CP_IB1_PREAMBLE_END__IB1_PREAMBLE_END__SHIFT 0x0 +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN_MASK 0xfffff +#define CP_IB2_PREAMBLE_BEGIN__IB2_PREAMBLE_BEGIN__SHIFT 0x0 +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END_MASK 0xfffff +#define CP_IB2_PREAMBLE_END__IB2_PREAMBLE_END__SHIFT 0x0 +#define CP_CE_IB1_OFFSET__IB1_OFFSET_MASK 0xfffff +#define CP_CE_IB1_OFFSET__IB1_OFFSET__SHIFT 0x0 +#define CP_CE_IB2_OFFSET__IB2_OFFSET_MASK 0xfffff +#define CP_CE_IB2_OFFSET__IB2_OFFSET__SHIFT 0x0 +#define CP_CE_COUNTER__CONST_ENGINE_COUNT_MASK 0xffffffff +#define CP_CE_COUNTER__CONST_ENGINE_COUNT__SHIFT 0x0 +#define CP_CE_RB_OFFSET__RB_OFFSET_MASK 0xfffff +#define CP_CE_RB_OFFSET__RB_OFFSET__SHIFT 0x0 +#define CP_PFP_COMPLETION_STATUS__STATUS_MASK 0x3 +#define CP_PFP_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_CE_COMPLETION_STATUS__STATUS_MASK 0x3 +#define CP_CE_COMPLETION_STATUS__STATUS__SHIFT 0x0 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE_MASK 0x1 +#define CP_PRED_NOT_VISIBLE__NOT_VISIBLE__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_PFP_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_PFP_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_CE_METADATA_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_CE_METADATA_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_DRAW_INDX_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_DRAW_INDX_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_DISPATCH_INDR_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_DISPATCH_INDR_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_INDEX_BASE_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_INDEX_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define CP_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR__ADDR_LO_MASK 0xffffffff +#define CP_GDS_BKUP_ADDR__ADDR_LO__SHIFT 0x0 +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_GDS_BKUP_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE_MASK 0x1 +#define CP_SAMPLE_STATUS__Z_PASS_ACITVE__SHIFT 0x0 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE_MASK 0x2 +#define CP_SAMPLE_STATUS__STREAMOUT_ACTIVE__SHIFT 0x1 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE_MASK 0x4 +#define CP_SAMPLE_STATUS__PIPELINE_ACTIVE__SHIFT 0x2 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE_MASK 0x8 +#define CP_SAMPLE_STATUS__STIPPLE_ACTIVE__SHIFT 0x3 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE_MASK 0x10 +#define CP_SAMPLE_STATUS__VGT_BUFFERS_ACTIVE__SHIFT 0x4 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE_MASK 0x20 +#define CP_SAMPLE_STATUS__SCREEN_EXT_ACTIVE__SHIFT 0x5 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE_MASK 0x40 +#define CP_SAMPLE_STATUS__DRAW_INDIRECT_ACTIVE__SHIFT 0x6 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE_MASK 0x80 +#define CP_SAMPLE_STATUS__DISP_INDIRECT_ACTIVE__SHIFT 0x7 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT1__RBIU_TO_DMA_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV_MASK 0x4 +#define CP_STALLED_STAT1__RBIU_TO_SEM_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV_MASK 0x10 +#define CP_STALLED_STAT1__RBIU_TO_MEMWR_NOT_RDY_TO_RCV__SHIFT 0x4 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG_MASK 0x400 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_CE_BUFFER_FLAG__SHIFT 0xa +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG_MASK 0x800 +#define CP_STALLED_STAT1__ME_HAS_ACTIVE_DE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM_MASK 0x1000 +#define CP_STALLED_STAT1__ME_STALLED_ON_TC_WR_CONFIRM__SHIFT 0xc +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x2000 +#define CP_STALLED_STAT1__ME_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0xd +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA_MASK 0x4000 +#define CP_STALLED_STAT1__ME_WAITING_ON_TC_READ_DATA__SHIFT 0xe +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA_MASK 0x8000 +#define CP_STALLED_STAT1__ME_WAITING_ON_REG_READ_DATA__SHIFT 0xf +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE_MASK 0x800000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GDS_FREE__SHIFT 0x17 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE_MASK 0x1000000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_GRBM_FREE__SHIFT 0x18 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE_MASK 0x2000000 +#define CP_STALLED_STAT1__RCIU_WAITING_ON_VGT_FREE__SHIFT 0x19 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ_MASK 0x4000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_ME_READ__SHIFT 0x1a +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ_MASK 0x8000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_DMA_READ__SHIFT 0x1b +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ_MASK 0x10000000 +#define CP_STALLED_STAT1__RCIU_STALLED_ON_APPEND_READ__SHIFT 0x1c +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION_MASK 0x20000000 +#define CP_STALLED_STAT1__RCIU_HALTED_BY_REG_VIOLATION__SHIFT 0x1d +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT2__PFP_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV_MASK 0x2 +#define CP_STALLED_STAT2__PFP_TO_MEQ_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV_MASK 0x4 +#define CP_STALLED_STAT2__PFP_TO_RCIU_NOT_RDY_TO_RCV__SHIFT 0x2 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING_MASK 0x10 +#define CP_STALLED_STAT2__PFP_TO_VGT_WRITES_PENDING__SHIFT 0x4 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING_MASK 0x20 +#define CP_STALLED_STAT2__PFP_RCIU_READ_PENDING__SHIFT 0x5 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA_MASK 0x100 +#define CP_STALLED_STAT2__PFP_WAITING_ON_BUFFER_DATA__SHIFT 0x8 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER_MASK 0x200 +#define CP_STALLED_STAT2__ME_WAIT_ON_CE_COUNTER__SHIFT 0x9 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER_MASK 0x400 +#define CP_STALLED_STAT2__ME_WAIT_ON_AVAIL_BUFFER__SHIFT 0xa +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME_MASK 0x800 +#define CP_STALLED_STAT2__GFX_CNTX_NOT_AVAIL_TO_ME__SHIFT 0xb +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV_MASK 0x1000 +#define CP_STALLED_STAT2__ME_RCIU_NOT_RDY_TO_RCV__SHIFT 0xc +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV_MASK 0x2000 +#define CP_STALLED_STAT2__ME_TO_CONST_NOT_RDY_TO_RCV__SHIFT 0xd +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP_MASK 0x4000 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_PFP__SHIFT 0xe +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH_MASK 0x8000 +#define CP_STALLED_STAT2__ME_WAITING_ON_PARTIAL_FLUSH__SHIFT 0xf +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x10000 +#define CP_STALLED_STAT2__MEQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x10 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV_MASK 0x20000 +#define CP_STALLED_STAT2__STQ_TO_ME_NOT_RDY_TO_RCV__SHIFT 0x11 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ_MASK 0x40000 +#define CP_STALLED_STAT2__ME_WAITING_DATA_FROM_STQ__SHIFT 0x12 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM_MASK 0x80000 +#define CP_STALLED_STAT2__PFP_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x13 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x100000 +#define CP_STALLED_STAT2__PFP_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x14 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE_MASK 0x200000 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_SC_EOP_DONE__SHIFT 0x15 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM_MASK 0x400000 +#define CP_STALLED_STAT2__EOPD_FIFO_NEEDS_WR_CONFIRM__SHIFT 0x16 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING_MASK 0x800000 +#define CP_STALLED_STAT2__STRMO_WR_OF_PRIM_DATA_PENDING__SHIFT 0x17 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING_MASK 0x1000000 +#define CP_STALLED_STAT2__PIPE_STATS_WR_DATA_PENDING__SHIFT 0x18 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE_MASK 0x2000000 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_CS_DONE__SHIFT 0x19 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE_MASK 0x4000000 +#define CP_STALLED_STAT2__APPEND_RDY_WAIT_ON_PS_DONE__SHIFT 0x1a +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM_MASK 0x8000000 +#define CP_STALLED_STAT2__APPEND_WAIT_ON_WR_CONFIRM__SHIFT 0x1b +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION_MASK 0x10000000 +#define CP_STALLED_STAT2__APPEND_ACTIVE_PARTITION__SHIFT 0x1c +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE_MASK 0x20000000 +#define CP_STALLED_STAT2__APPEND_WAITING_TO_SEND_MEMWRITE__SHIFT 0x1d +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS_MASK 0x40000000 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_IDLE_CNTXS__SHIFT 0x1e +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN_MASK 0x80000000 +#define CP_STALLED_STAT2__SURF_SYNC_NEEDS_ALL_CLEAN__SHIFT 0x1f +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV_MASK 0x1 +#define CP_STALLED_STAT3__CE_TO_CSF_NOT_RDY_TO_RCV__SHIFT 0x0 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV_MASK 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_FETCHER_NOT_RDY_TO_RCV__SHIFT 0x1 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER_MASK 0x4 +#define CP_STALLED_STAT3__CE_WAITING_ON_DATA_FROM_RAM_INIT_FETCHER__SHIFT 0x2 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY_MASK 0x8 +#define CP_STALLED_STAT3__CE_TO_RAM_INIT_NOT_RDY__SHIFT 0x3 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY_MASK 0x10 +#define CP_STALLED_STAT3__CE_TO_RAM_DUMP_NOT_RDY__SHIFT 0x4 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY_MASK 0x20 +#define CP_STALLED_STAT3__CE_TO_RAM_WRITE_NOT_RDY__SHIFT 0x5 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV_MASK 0x40 +#define CP_STALLED_STAT3__CE_TO_INC_FIFO_NOT_RDY_TO_RCV__SHIFT 0x6 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV_MASK 0x80 +#define CP_STALLED_STAT3__CE_TO_WR_FIFO_NOT_RDY_TO_RCV__SHIFT 0x7 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA_MASK 0x400 +#define CP_STALLED_STAT3__CE_WAITING_ON_BUFFER_DATA__SHIFT 0xa +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG_MASK 0x800 +#define CP_STALLED_STAT3__CE_WAITING_ON_CE_BUFFER_FLAG__SHIFT 0xb +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_MASK 0x1000 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER__SHIFT 0xc +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW_MASK 0x2000 +#define CP_STALLED_STAT3__CE_WAITING_ON_DE_COUNTER_UNDERFLOW__SHIFT 0xd +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE_MASK 0x4000 +#define CP_STALLED_STAT3__TCIU_WAITING_ON_FREE__SHIFT 0xe +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS_MASK 0x8000 +#define CP_STALLED_STAT3__TCIU_WAITING_ON_TAGS__SHIFT 0xf +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM_MASK 0x10000 +#define CP_STALLED_STAT3__CE_STALLED_ON_TC_WR_CONFIRM__SHIFT 0x10 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA_MASK 0x20000 +#define CP_STALLED_STAT3__CE_STALLED_ON_ATOMIC_RTN_DATA__SHIFT 0x11 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE_MASK 0x40000 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_FREE__SHIFT 0x12 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS_MASK 0x80000 +#define CP_STALLED_STAT3__ATCL2IU_WAITING_ON_TAGS__SHIFT 0x13 +#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS_MASK 0x100000 +#define CP_STALLED_STAT3__ATCL1_WAITING_ON_TRANS__SHIFT 0x14 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY_MASK 0x1 +#define CP_BUSY_STAT__REG_BUS_FIFO_BUSY__SHIFT 0x0 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO_MASK 0x40 +#define CP_BUSY_STAT__COHER_CNT_NEQ_ZERO__SHIFT 0x6 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS_MASK 0x80 +#define CP_BUSY_STAT__PFP_PARSING_PACKETS__SHIFT 0x7 +#define CP_BUSY_STAT__ME_PARSING_PACKETS_MASK 0x100 +#define CP_BUSY_STAT__ME_PARSING_PACKETS__SHIFT 0x8 +#define CP_BUSY_STAT__RCIU_PFP_BUSY_MASK 0x200 +#define CP_BUSY_STAT__RCIU_PFP_BUSY__SHIFT 0x9 +#define CP_BUSY_STAT__RCIU_ME_BUSY_MASK 0x400 +#define CP_BUSY_STAT__RCIU_ME_BUSY__SHIFT 0xa +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY_MASK 0x1000 +#define CP_BUSY_STAT__SEM_CMDFIFO_NOT_EMPTY__SHIFT 0xc +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING_MASK 0x2000 +#define CP_BUSY_STAT__SEM_FAILED_AND_HOLDING__SHIFT 0xd +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS_MASK 0x4000 +#define CP_BUSY_STAT__SEM_POLLING_FOR_PASS__SHIFT 0xe +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY_MASK 0x8000 +#define CP_BUSY_STAT__GFX_CONTEXT_BUSY__SHIFT 0xf +#define CP_BUSY_STAT__ME_PARSER_BUSY_MASK 0x20000 +#define CP_BUSY_STAT__ME_PARSER_BUSY__SHIFT 0x11 +#define CP_BUSY_STAT__EOP_DONE_BUSY_MASK 0x40000 +#define CP_BUSY_STAT__EOP_DONE_BUSY__SHIFT 0x12 +#define CP_BUSY_STAT__STRM_OUT_BUSY_MASK 0x80000 +#define CP_BUSY_STAT__STRM_OUT_BUSY__SHIFT 0x13 +#define CP_BUSY_STAT__PIPE_STATS_BUSY_MASK 0x100000 +#define CP_BUSY_STAT__PIPE_STATS_BUSY__SHIFT 0x14 +#define CP_BUSY_STAT__RCIU_CE_BUSY_MASK 0x200000 +#define CP_BUSY_STAT__RCIU_CE_BUSY__SHIFT 0x15 +#define CP_BUSY_STAT__CE_PARSING_PACKETS_MASK 0x400000 +#define CP_BUSY_STAT__CE_PARSING_PACKETS__SHIFT 0x16 +#define CP_STAT__ROQ_RING_BUSY_MASK 0x200 +#define CP_STAT__ROQ_RING_BUSY__SHIFT 0x9 +#define CP_STAT__ROQ_INDIRECT1_BUSY_MASK 0x400 +#define CP_STAT__ROQ_INDIRECT1_BUSY__SHIFT 0xa +#define CP_STAT__ROQ_INDIRECT2_BUSY_MASK 0x800 +#define CP_STAT__ROQ_INDIRECT2_BUSY__SHIFT 0xb +#define CP_STAT__ROQ_STATE_BUSY_MASK 0x1000 +#define CP_STAT__ROQ_STATE_BUSY__SHIFT 0xc +#define CP_STAT__DC_BUSY_MASK 0x2000 +#define CP_STAT__DC_BUSY__SHIFT 0xd +#define CP_STAT__ATCL2IU_BUSY_MASK 0x4000 +#define CP_STAT__ATCL2IU_BUSY__SHIFT 0xe +#define CP_STAT__PFP_BUSY_MASK 0x8000 +#define CP_STAT__PFP_BUSY__SHIFT 0xf +#define CP_STAT__MEQ_BUSY_MASK 0x10000 +#define CP_STAT__MEQ_BUSY__SHIFT 0x10 +#define CP_STAT__ME_BUSY_MASK 0x20000 +#define CP_STAT__ME_BUSY__SHIFT 0x11 +#define CP_STAT__QUERY_BUSY_MASK 0x40000 +#define CP_STAT__QUERY_BUSY__SHIFT 0x12 +#define CP_STAT__SEMAPHORE_BUSY_MASK 0x80000 +#define CP_STAT__SEMAPHORE_BUSY__SHIFT 0x13 +#define CP_STAT__INTERRUPT_BUSY_MASK 0x100000 +#define CP_STAT__INTERRUPT_BUSY__SHIFT 0x14 +#define CP_STAT__SURFACE_SYNC_BUSY_MASK 0x200000 +#define CP_STAT__SURFACE_SYNC_BUSY__SHIFT 0x15 +#define CP_STAT__DMA_BUSY_MASK 0x400000 +#define CP_STAT__DMA_BUSY__SHIFT 0x16 +#define CP_STAT__RCIU_BUSY_MASK 0x800000 +#define CP_STAT__RCIU_BUSY__SHIFT 0x17 +#define CP_STAT__SCRATCH_RAM_BUSY_MASK 0x1000000 +#define CP_STAT__SCRATCH_RAM_BUSY__SHIFT 0x18 +#define CP_STAT__CPC_CPG_BUSY_MASK 0x2000000 +#define CP_STAT__CPC_CPG_BUSY__SHIFT 0x19 +#define CP_STAT__CE_BUSY_MASK 0x4000000 +#define CP_STAT__CE_BUSY__SHIFT 0x1a +#define CP_STAT__TCIU_BUSY_MASK 0x8000000 +#define CP_STAT__TCIU_BUSY__SHIFT 0x1b +#define CP_STAT__ROQ_CE_RING_BUSY_MASK 0x10000000 +#define CP_STAT__ROQ_CE_RING_BUSY__SHIFT 0x1c +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY_MASK 0x20000000 +#define CP_STAT__ROQ_CE_INDIRECT1_BUSY__SHIFT 0x1d +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY_MASK 0x40000000 +#define CP_STAT__ROQ_CE_INDIRECT2_BUSY__SHIFT 0x1e +#define CP_STAT__CP_BUSY_MASK 0x80000000 +#define CP_STAT__CP_BUSY__SHIFT 0x1f +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP_MASK 0xffffffff +#define CP_ME_HEADER_DUMP__ME_HEADER_DUMP__SHIFT 0x0 +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP_MASK 0xffffffff +#define CP_PFP_HEADER_DUMP__PFP_HEADER_DUMP__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_MASK 0x3f +#define CP_GRBM_FREE_COUNT__FREE_COUNT__SHIFT 0x0 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS_MASK 0x3f00 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_GDS__SHIFT 0x8 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP_MASK 0x3f0000 +#define CP_GRBM_FREE_COUNT__FREE_COUNT_PFP__SHIFT 0x10 +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP_MASK 0xffffffff +#define CP_CE_HEADER_DUMP__CE_HEADER_DUMP__SHIFT 0x0 +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED_MASK 0xf +#define CP_CSF_STAT__BUFFER_SLOTS_ALLOCATED__SHIFT 0x0 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT_MASK 0x1ff00 +#define CP_CSF_STAT__BUFFER_REQUEST_COUNT__SHIFT 0x8 +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH_MASK 0xf +#define CP_CSF_CNTL__FETCH_BUFFER_DEPTH__SHIFT 0x0 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE_MASK 0x10 +#define CP_ME_CNTL__CE_INVALIDATE_ICACHE__SHIFT 0x4 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE_MASK 0x40 +#define CP_ME_CNTL__PFP_INVALIDATE_ICACHE__SHIFT 0x6 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE_MASK 0x100 +#define CP_ME_CNTL__ME_INVALIDATE_ICACHE__SHIFT 0x8 +#define CP_ME_CNTL__CE_PIPE0_RESET_MASK 0x10000 +#define CP_ME_CNTL__CE_PIPE0_RESET__SHIFT 0x10 +#define CP_ME_CNTL__PFP_PIPE0_RESET_MASK 0x40000 +#define CP_ME_CNTL__PFP_PIPE0_RESET__SHIFT 0x12 +#define CP_ME_CNTL__ME_PIPE0_RESET_MASK 0x100000 +#define CP_ME_CNTL__ME_PIPE0_RESET__SHIFT 0x14 +#define CP_ME_CNTL__CE_HALT_MASK 0x1000000 +#define CP_ME_CNTL__CE_HALT__SHIFT 0x18 +#define CP_ME_CNTL__CE_STEP_MASK 0x2000000 +#define CP_ME_CNTL__CE_STEP__SHIFT 0x19 +#define CP_ME_CNTL__PFP_HALT_MASK 0x4000000 +#define CP_ME_CNTL__PFP_HALT__SHIFT 0x1a +#define CP_ME_CNTL__PFP_STEP_MASK 0x8000000 +#define CP_ME_CNTL__PFP_STEP__SHIFT 0x1b +#define CP_ME_CNTL__ME_HALT_MASK 0x10000000 +#define CP_ME_CNTL__ME_HALT__SHIFT 0x1c +#define CP_ME_CNTL__ME_STEP_MASK 0x20000000 +#define CP_ME_CNTL__ME_STEP__SHIFT 0x1d +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS_MASK 0xff +#define CP_CNTX_STAT__ACTIVE_HP3D_CONTEXTS__SHIFT 0x0 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT_MASK 0x700 +#define CP_CNTX_STAT__CURRENT_HP3D_CONTEXT__SHIFT 0x8 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS_MASK 0xff00000 +#define CP_CNTX_STAT__ACTIVE_GFX_CONTEXTS__SHIFT 0x14 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT_MASK 0x70000000 +#define CP_CNTX_STAT__CURRENT_GFX_CONTEXT__SHIFT 0x1c +#define CP_ME_PREEMPTION__OBSOLETE_MASK 0x1 +#define CP_ME_PREEMPTION__OBSOLETE__SHIFT 0x0 +#define CP_RB0_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB0_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB1_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB1_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB2_RPTR__RB_RPTR_MASK 0xfffff +#define CP_RB2_RPTR__RB_RPTR__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER_MASK 0xfffffff +#define CP_RB_WPTR_DELAY__PRE_WRITE_TIMER__SHIFT 0x0 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT_MASK 0xf0000000 +#define CP_RB_WPTR_DELAY__PRE_WRITE_LIMIT__SHIFT 0x1c +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK 0xffff +#define CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT 0x0 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xffff0000 +#define CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO_MASK 0xffffffe0 +#define CP_CE_INIT_BASE_LO__INIT_BASE_LO__SHIFT 0x5 +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI_MASK 0xffff +#define CP_CE_INIT_BASE_HI__INIT_BASE_HI__SHIFT 0x0 +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ_MASK 0xfff +#define CP_CE_INIT_BUFSZ__INIT_BUFSZ__SHIFT 0x0 +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc +#define CP_CE_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff +#define CP_CE_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff +#define CP_CE_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc +#define CP_CE_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff +#define CP_CE_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff +#define CP_CE_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_IB1_BASE_LO__IB1_BASE_LO_MASK 0xfffffffc +#define CP_IB1_BASE_LO__IB1_BASE_LO__SHIFT 0x2 +#define CP_IB1_BASE_HI__IB1_BASE_HI_MASK 0xffff +#define CP_IB1_BASE_HI__IB1_BASE_HI__SHIFT 0x0 +#define CP_IB1_BUFSZ__IB1_BUFSZ_MASK 0xfffff +#define CP_IB1_BUFSZ__IB1_BUFSZ__SHIFT 0x0 +#define CP_IB2_BASE_LO__IB2_BASE_LO_MASK 0xfffffffc +#define CP_IB2_BASE_LO__IB2_BASE_LO__SHIFT 0x2 +#define CP_IB2_BASE_HI__IB2_BASE_HI_MASK 0xffff +#define CP_IB2_BASE_HI__IB2_BASE_HI__SHIFT 0x0 +#define CP_IB2_BUFSZ__IB2_BUFSZ_MASK 0xfffff +#define CP_IB2_BUFSZ__IB2_BUFSZ__SHIFT 0x0 +#define CP_ST_BASE_LO__ST_BASE_LO_MASK 0xfffffffc +#define CP_ST_BASE_LO__ST_BASE_LO__SHIFT 0x2 +#define CP_ST_BASE_HI__ST_BASE_HI_MASK 0xffff +#define CP_ST_BASE_HI__ST_BASE_HI__SHIFT 0x0 +#define CP_ST_BUFSZ__ST_BUFSZ_MASK 0xfffff +#define CP_ST_BUFSZ__ST_BUFSZ__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB1_START_MASK 0xff +#define CP_ROQ_THRESHOLDS__IB1_START__SHIFT 0x0 +#define CP_ROQ_THRESHOLDS__IB2_START_MASK 0xff00 +#define CP_ROQ_THRESHOLDS__IB2_START__SHIFT 0x8 +#define CP_MEQ_STQ_THRESHOLD__STQ_START_MASK 0xff +#define CP_MEQ_STQ_THRESHOLD__STQ_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB1_START_MASK 0xff +#define CP_ROQ1_THRESHOLDS__RB1_START__SHIFT 0x0 +#define CP_ROQ1_THRESHOLDS__RB2_START_MASK 0xff00 +#define CP_ROQ1_THRESHOLDS__RB2_START__SHIFT 0x8 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START_MASK 0xff0000 +#define CP_ROQ1_THRESHOLDS__R0_IB1_START__SHIFT 0x10 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START_MASK 0xff000000 +#define CP_ROQ1_THRESHOLDS__R1_IB1_START__SHIFT 0x18 +#define CP_ROQ2_THRESHOLDS__R2_IB1_START_MASK 0xff +#define CP_ROQ2_THRESHOLDS__R2_IB1_START__SHIFT 0x0 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START_MASK 0xff00 +#define CP_ROQ2_THRESHOLDS__R0_IB2_START__SHIFT 0x8 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START_MASK 0xff0000 +#define CP_ROQ2_THRESHOLDS__R1_IB2_START__SHIFT 0x10 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START_MASK 0xff000000 +#define CP_ROQ2_THRESHOLDS__R2_IB2_START__SHIFT 0x18 +#define CP_STQ_THRESHOLDS__STQ0_START_MASK 0xff +#define CP_STQ_THRESHOLDS__STQ0_START__SHIFT 0x0 +#define CP_STQ_THRESHOLDS__STQ1_START_MASK 0xff00 +#define CP_STQ_THRESHOLDS__STQ1_START__SHIFT 0x8 +#define CP_STQ_THRESHOLDS__STQ2_START_MASK 0xff0000 +#define CP_STQ_THRESHOLDS__STQ2_START__SHIFT 0x10 +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START_MASK 0x3f +#define CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT 0x0 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START_MASK 0x3f00 +#define CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT 0x8 +#define CP_MEQ_THRESHOLDS__MEQ1_START_MASK 0xff +#define CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT 0x0 +#define CP_MEQ_THRESHOLDS__MEQ2_START_MASK 0xff00 +#define CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT 0x8 +#define CP_ROQ_AVAIL__ROQ_CNT_RING_MASK 0x7ff +#define CP_ROQ_AVAIL__ROQ_CNT_RING__SHIFT 0x0 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1_MASK 0x7ff0000 +#define CP_ROQ_AVAIL__ROQ_CNT_IB1__SHIFT 0x10 +#define CP_STQ_AVAIL__STQ_CNT_MASK 0x1ff +#define CP_STQ_AVAIL__STQ_CNT__SHIFT 0x0 +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2_MASK 0x7ff +#define CP_ROQ2_AVAIL__ROQ_CNT_IB2__SHIFT 0x0 +#define CP_MEQ_AVAIL__MEQ_CNT_MASK 0x3ff +#define CP_MEQ_AVAIL__MEQ_CNT__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_INDEX_MASK 0x7ff +#define CP_CMD_INDEX__CMD_INDEX__SHIFT 0x0 +#define CP_CMD_INDEX__CMD_ME_SEL_MASK 0x3000 +#define CP_CMD_INDEX__CMD_ME_SEL__SHIFT 0xc +#define CP_CMD_INDEX__CMD_QUEUE_SEL_MASK 0x70000 +#define CP_CMD_INDEX__CMD_QUEUE_SEL__SHIFT 0x10 +#define CP_CMD_DATA__CMD_DATA_MASK 0xffffffff +#define CP_CMD_DATA__CMD_DATA__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY_MASK 0x3ff +#define CP_ROQ_RB_STAT__ROQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY_MASK 0x3ff0000 +#define CP_ROQ_RB_STAT__ROQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1_MASK 0x3ff +#define CP_ROQ_IB1_STAT__ROQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1_MASK 0x3ff0000 +#define CP_ROQ_IB1_STAT__ROQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2_MASK 0x3ff +#define CP_ROQ_IB2_STAT__ROQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2_MASK 0x3ff0000 +#define CP_ROQ_IB2_STAT__ROQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_STQ_STAT__STQ_RPTR_MASK 0x3ff +#define CP_STQ_STAT__STQ_RPTR__SHIFT 0x0 +#define CP_STQ_WR_STAT__STQ_WPTR_MASK 0x3ff +#define CP_STQ_WR_STAT__STQ_WPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_RPTR_MASK 0x3ff +#define CP_MEQ_STAT__MEQ_RPTR__SHIFT 0x0 +#define CP_MEQ_STAT__MEQ_WPTR_MASK 0x3ff0000 +#define CP_MEQ_STAT__MEQ_WPTR__SHIFT 0x10 +#define CP_CEQ1_AVAIL__CEQ_CNT_RING_MASK 0x7ff +#define CP_CEQ1_AVAIL__CEQ_CNT_RING__SHIFT 0x0 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1_MASK 0x7ff0000 +#define CP_CEQ1_AVAIL__CEQ_CNT_IB1__SHIFT 0x10 +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2_MASK 0x7ff +#define CP_CEQ2_AVAIL__CEQ_CNT_IB2__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY_MASK 0x3ff +#define CP_CE_ROQ_RB_STAT__CEQ_RPTR_PRIMARY__SHIFT 0x0 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY_MASK 0x3ff0000 +#define CP_CE_ROQ_RB_STAT__CEQ_WPTR_PRIMARY__SHIFT 0x10 +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1_MASK 0x3ff +#define CP_CE_ROQ_IB1_STAT__CEQ_RPTR_INDIRECT1__SHIFT 0x0 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1_MASK 0x3ff0000 +#define CP_CE_ROQ_IB1_STAT__CEQ_WPTR_INDIRECT1__SHIFT 0x10 +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2_MASK 0x3ff +#define CP_CE_ROQ_IB2_STAT__CEQ_RPTR_INDIRECT2__SHIFT 0x0 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2_MASK 0x3ff0000 +#define CP_CE_ROQ_IB2_STAT__CEQ_WPTR_INDIRECT2__SHIFT 0x10 +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED_MASK 0x800 +#define CP_INT_STAT_DEBUG__CP_VM_DOORBELL_WR_INT_ASSERTED__SHIFT 0xb +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED_MASK 0x4000 +#define CP_INT_STAT_DEBUG__CP_ECC_ERROR_INT_ASSERTED__SHIFT 0xe +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED_MASK 0x20000 +#define CP_INT_STAT_DEBUG__WRM_POLL_TIMEOUT_INT_ASSERTED__SHIFT 0x11 +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED_MASK 0x40000 +#define CP_INT_STAT_DEBUG__CMP_BUSY_INT_ASSERTED__SHIFT 0x12 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED_MASK 0x80000 +#define CP_INT_STAT_DEBUG__CNTX_BUSY_INT_ASSERTED__SHIFT 0x13 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED_MASK 0x100000 +#define CP_INT_STAT_DEBUG__CNTX_EMPTY_INT_ASSERTED__SHIFT 0x14 +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED_MASK 0x200000 +#define CP_INT_STAT_DEBUG__GFX_IDLE_INT_ASSERTED__SHIFT 0x15 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED_MASK 0x400000 +#define CP_INT_STAT_DEBUG__PRIV_INSTR_INT_ASSERTED__SHIFT 0x16 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED_MASK 0x800000 +#define CP_INT_STAT_DEBUG__PRIV_REG_INT_ASSERTED__SHIFT 0x17 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED_MASK 0x1000000 +#define CP_INT_STAT_DEBUG__OPCODE_ERROR_INT_ASSERTED__SHIFT 0x18 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED_MASK 0x4000000 +#define CP_INT_STAT_DEBUG__TIME_STAMP_INT_ASSERTED__SHIFT 0x1a +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED_MASK 0x8000000 +#define CP_INT_STAT_DEBUG__RESERVED_BIT_ERROR_INT_ASSERTED__SHIFT 0x1b +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED_MASK 0x20000000 +#define CP_INT_STAT_DEBUG__GENERIC2_INT_ASSERTED__SHIFT 0x1d +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED_MASK 0x40000000 +#define CP_INT_STAT_DEBUG__GENERIC1_INT_ASSERTED__SHIFT 0x1e +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED_MASK 0x80000000 +#define CP_INT_STAT_DEBUG__GENERIC0_INT_ASSERTED__SHIFT 0x1f +#define CP_PERFMON_CNTL__PERFMON_STATE_MASK 0xf +#define CP_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE_MASK 0xf0 +#define CP_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT 0x4 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK 0x300 +#define CP_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT 0x8 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define CP_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000 +#define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f +#define CP_RINGID__RINGID_MASK 0x3 +#define CP_RINGID__RINGID__SHIFT 0x0 +#define CP_PIPEID__PIPE_ID_MASK 0x3 +#define CP_PIPEID__PIPE_ID__SHIFT 0x0 +#define CP_VMID__VMID_MASK 0xf +#define CP_VMID__VMID__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET_MASK 0x7 +#define CP_HPD_ROQ_OFFSETS__IQ_OFFSET__SHIFT 0x0 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET_MASK 0x3f00 +#define CP_HPD_ROQ_OFFSETS__PQ_OFFSET__SHIFT 0x8 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET_MASK 0x3f0000 +#define CP_HPD_ROQ_OFFSETS__IB_OFFSET__SHIFT 0x10 +#define CP_HPD_STATUS0__QUEUE_STATE_MASK 0x1f +#define CP_HPD_STATUS0__QUEUE_STATE__SHIFT 0x0 +#define CP_HPD_STATUS0__MAPPED_QUEUE_MASK 0xe0 +#define CP_HPD_STATUS0__MAPPED_QUEUE__SHIFT 0x5 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE_MASK 0xff00 +#define CP_HPD_STATUS0__QUEUE_AVAILABLE__SHIFT 0x8 +#define CP_MQD_BASE_ADDR__BASE_ADDR_MASK 0xfffffffc +#define CP_MQD_BASE_ADDR__BASE_ADDR__SHIFT 0x2 +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xffff +#define CP_MQD_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_ACTIVE__ACTIVE_MASK 0x1 +#define CP_HQD_ACTIVE__ACTIVE__SHIFT 0x0 +#define CP_HQD_ACTIVE__BUSY_GATE_MASK 0x2 +#define CP_HQD_ACTIVE__BUSY_GATE__SHIFT 0x1 +#define CP_HQD_VMID__VMID_MASK 0xf +#define CP_HQD_VMID__VMID__SHIFT 0x0 +#define CP_HQD_VMID__IB_VMID_MASK 0xf00 +#define CP_HQD_VMID__IB_VMID__SHIFT 0x8 +#define CP_HQD_VMID__VQID_MASK 0x3ff0000 +#define CP_HQD_VMID__VQID__SHIFT 0x10 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ_MASK 0x1 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_REQ__SHIFT 0x0 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE_MASK 0x3ff00 +#define CP_HQD_PERSISTENT_STATE__PRELOAD_SIZE__SHIFT 0x8 +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE_MASK 0x10000000 +#define CP_HQD_PERSISTENT_STATE__RESTORE_ACTIVE__SHIFT 0x1c +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES_MASK 0x20000000 +#define CP_HQD_PERSISTENT_STATE__RELAUNCH_WAVES__SHIFT 0x1d +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE_MASK 0x40000000 +#define CP_HQD_PERSISTENT_STATE__QSWITCH_MODE__SHIFT 0x1e +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE_MASK 0x80000000 +#define CP_HQD_PERSISTENT_STATE__DISP_ACTIVE__SHIFT 0x1f +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY_MASK 0x3 +#define CP_HQD_PIPE_PRIORITY__PIPE_PRIORITY__SHIFT 0x0 +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL_MASK 0xf +#define CP_HQD_QUEUE_PRIORITY__PRIORITY_LEVEL__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_EN_MASK 0x1 +#define CP_HQD_QUANTUM__QUANTUM_EN__SHIFT 0x0 +#define CP_HQD_QUANTUM__QUANTUM_SCALE_MASK 0x10 +#define CP_HQD_QUANTUM__QUANTUM_SCALE__SHIFT 0x4 +#define CP_HQD_QUANTUM__QUANTUM_DURATION_MASK 0x3f00 +#define CP_HQD_QUANTUM__QUANTUM_DURATION__SHIFT 0x8 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE_MASK 0x80000000 +#define CP_HQD_QUANTUM__QUANTUM_ACTIVE__SHIFT 0x1f +#define CP_HQD_PQ_BASE__ADDR_MASK 0xffffffff +#define CP_HQD_PQ_BASE__ADDR__SHIFT 0x0 +#define CP_HQD_PQ_BASE_HI__ADDR_HI_MASK 0xff +#define CP_HQD_PQ_BASE_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET_MASK 0xffffffff +#define CP_HQD_PQ_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR_MASK 0xfffffffc +#define CP_HQD_PQ_RPTR_REPORT_ADDR__RPTR_REPORT_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI_MASK 0xffff +#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI__RPTR_REPORT_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR_MASK 0xfffffffc +#define CP_HQD_PQ_WPTR_POLL_ADDR__WPTR_ADDR__SHIFT 0x2 +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI_MASK 0xffff +#define CP_HQD_PQ_WPTR_POLL_ADDR_HI__WPTR_ADDR_HI__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE_MASK 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_MODE__SHIFT 0x0 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP_MASK 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT 0x1 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK 0x7ffffc +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT 0x2 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS_MASK 0x3800000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_CARRY_BITS__SHIFT 0x17 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE_MASK 0x10000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SOURCE__SHIFT 0x1c +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT_MASK 0x20000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_SCHD_HIT__SHIFT 0x1d +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN_MASK 0x40000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_EN__SHIFT 0x1e +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT_MASK 0x80000000 +#define CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_HIT__SHIFT 0x1f +#define CP_HQD_PQ_WPTR__OFFSET_MASK 0xffffffff +#define CP_HQD_PQ_WPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE_MASK 0x3f +#define CP_HQD_PQ_CONTROL__QUEUE_SIZE__SHIFT 0x0 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE_MASK 0x3f00 +#define CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT 0x8 +#define CP_HQD_PQ_CONTROL__MTYPE_MASK 0x18000 +#define CP_HQD_PQ_CONTROL__MTYPE__SHIFT 0xf +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP_MASK 0x60000 +#define CP_HQD_PQ_CONTROL__ENDIAN_SWAP__SHIFT 0x11 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE_MASK 0x300000 +#define CP_HQD_PQ_CONTROL__MIN_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_PQ_CONTROL__PQ_ATC_MASK 0x800000 +#define CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT 0x17 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_PQ_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR_MASK 0x6000000 +#define CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT 0x19 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK 0x8000000 +#define CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR__SHIFT 0x1b +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK 0x10000000 +#define CP_HQD_PQ_CONTROL__UNORD_DISPATCH__SHIFT 0x1c +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP_MASK 0x20000000 +#define CP_HQD_PQ_CONTROL__ROQ_PQ_IB_FLIP__SHIFT 0x1d +#define CP_HQD_PQ_CONTROL__PRIV_STATE_MASK 0x40000000 +#define CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT 0x1e +#define CP_HQD_PQ_CONTROL__KMD_QUEUE_MASK 0x80000000 +#define CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT 0x1f +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR_MASK 0xfffffffc +#define CP_HQD_IB_BASE_ADDR__IB_BASE_ADDR__SHIFT 0x2 +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI_MASK 0xffff +#define CP_HQD_IB_BASE_ADDR_HI__IB_BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET_MASK 0xfffff +#define CP_HQD_IB_RPTR__CONSUMED_OFFSET__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__IB_SIZE_MASK 0xfffff +#define CP_HQD_IB_CONTROL__IB_SIZE__SHIFT 0x0 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE_MASK 0x300000 +#define CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT 0x14 +#define CP_HQD_IB_CONTROL__IB_ATC_MASK 0x800000 +#define CP_HQD_IB_CONTROL__IB_ATC__SHIFT 0x17 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_IB_CONTROL__IB_CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IB_CONTROL__MTYPE_MASK 0x18000000 +#define CP_HQD_IB_CONTROL__MTYPE__SHIFT 0x1b +#define CP_HQD_IB_CONTROL__PROCESSING_IB_MASK 0x80000000 +#define CP_HQD_IB_CONTROL__PROCESSING_IB__SHIFT 0x1f +#define CP_HQD_IQ_TIMER__WAIT_TIME_MASK 0xff +#define CP_HQD_IQ_TIMER__WAIT_TIME__SHIFT 0x0 +#define CP_HQD_IQ_TIMER__RETRY_TYPE_MASK 0x700 +#define CP_HQD_IQ_TIMER__RETRY_TYPE__SHIFT 0x8 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE_MASK 0x800 +#define CP_HQD_IQ_TIMER__IMMEDIATE_EXPIRE__SHIFT 0xb +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE_MASK 0x3000 +#define CP_HQD_IQ_TIMER__INTERRUPT_TYPE__SHIFT 0xc +#define CP_HQD_IQ_TIMER__CLOCK_COUNT_MASK 0xc000 +#define CP_HQD_IQ_TIMER__CLOCK_COUNT__SHIFT 0xe +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE_MASK 0x3f0000 +#define CP_HQD_IQ_TIMER__INTERRUPT_SIZE__SHIFT 0x10 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER_MASK 0x400000 +#define CP_HQD_IQ_TIMER__QUANTUM_TIMER__SHIFT 0x16 +#define CP_HQD_IQ_TIMER__IQ_ATC_MASK 0x800000 +#define CP_HQD_IQ_TIMER__IQ_ATC__SHIFT 0x17 +#define CP_HQD_IQ_TIMER__CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_IQ_TIMER__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_IQ_TIMER__MTYPE_MASK 0x18000000 +#define CP_HQD_IQ_TIMER__MTYPE__SHIFT 0x1b +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN_MASK 0x20000000 +#define CP_HQD_IQ_TIMER__PROCESS_IQ_EN__SHIFT 0x1d +#define CP_HQD_IQ_TIMER__PROCESSING_IQ_MASK 0x40000000 +#define CP_HQD_IQ_TIMER__PROCESSING_IQ__SHIFT 0x1e +#define CP_HQD_IQ_TIMER__ACTIVE_MASK 0x80000000 +#define CP_HQD_IQ_TIMER__ACTIVE__SHIFT 0x1f +#define CP_HQD_IQ_RPTR__OFFSET_MASK 0x3f +#define CP_HQD_IQ_RPTR__OFFSET__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_MASK 0x7 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ__SHIFT 0x0 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK 0x10 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND__SHIFT 0x4 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT_MASK 0x100 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_INT__SHIFT 0x8 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN_MASK 0x200 +#define CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_EN__SHIFT 0x9 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN_MASK 0x400 +#define CP_HQD_DEQUEUE_REQUEST__DEQUEUE_REQ_EN__SHIFT 0xa +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD_MASK 0x1 +#define CP_HQD_DMA_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_MASK 0x1 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD__SHIFT 0x0 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN_MASK 0x2 +#define CP_HQD_OFFLOAD__DMA_OFFLOAD_EN__SHIFT 0x1 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_MASK 0x10 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD__SHIFT 0x4 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN_MASK 0x20 +#define CP_HQD_OFFLOAD__EOP_OFFLOAD_EN__SHIFT 0x5 +#define CP_HQD_SEMA_CMD__RETRY_MASK 0x1 +#define CP_HQD_SEMA_CMD__RETRY__SHIFT 0x0 +#define CP_HQD_SEMA_CMD__RESULT_MASK 0x6 +#define CP_HQD_SEMA_CMD__RESULT__SHIFT 0x1 +#define CP_HQD_MSG_TYPE__ACTION_MASK 0x7 +#define CP_HQD_MSG_TYPE__ACTION__SHIFT 0x0 +#define CP_HQD_MSG_TYPE__SAVE_STATE_MASK 0x70 +#define CP_HQD_MSG_TYPE__SAVE_STATE__SHIFT 0x4 +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO_MASK 0xffffffff +#define CP_HQD_ATOMIC0_PREOP_LO__ATOMIC0_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI_MASK 0xffffffff +#define CP_HQD_ATOMIC0_PREOP_HI__ATOMIC0_PREOP_HI__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO_MASK 0xffffffff +#define CP_HQD_ATOMIC1_PREOP_LO__ATOMIC1_PREOP_LO__SHIFT 0x0 +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI_MASK 0xffffffff +#define CP_HQD_ATOMIC1_PREOP_HI__ATOMIC1_PREOP_HI__SHIFT 0x0 +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER_MASK 0xffffffff +#define CP_HQD_HQ_SCHEDULER0__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS_MASK 0x3 +#define CP_HQD_HQ_STATUS0__DEQUEUE_STATUS__SHIFT 0x0 +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT_MASK 0xc +#define CP_HQD_HQ_STATUS0__DEQUEUE_RETRY_CNT__SHIFT 0x2 +#define CP_HQD_HQ_STATUS0__RSV_6_4_MASK 0x70 +#define CP_HQD_HQ_STATUS0__RSV_6_4__SHIFT 0x4 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT_MASK 0x80 +#define CP_HQD_HQ_STATUS0__SCRATCH_RAM_INIT__SHIFT 0x7 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY_MASK 0x100 +#define CP_HQD_HQ_STATUS0__TCL2_DIRTY__SHIFT 0x8 +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED_MASK 0x200 +#define CP_HQD_HQ_STATUS0__PG_ACTIVATED__SHIFT 0x9 +#define CP_HQD_HQ_STATUS0__RSVR_31_10_MASK 0xfffffc00 +#define CP_HQD_HQ_STATUS0__RSVR_31_10__SHIFT 0xa +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER_MASK 0xffffffff +#define CP_HQD_HQ_SCHEDULER1__SCHEDULER__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL0__CONTROL_MASK 0xffffffff +#define CP_HQD_HQ_CONTROL0__CONTROL__SHIFT 0x0 +#define CP_MQD_CONTROL__VMID_MASK 0xf +#define CP_MQD_CONTROL__VMID__SHIFT 0x0 +#define CP_MQD_CONTROL__PROCESSING_MQD_MASK 0x1000 +#define CP_MQD_CONTROL__PROCESSING_MQD__SHIFT 0xc +#define CP_MQD_CONTROL__PROCESSING_MQD_EN_MASK 0x2000 +#define CP_MQD_CONTROL__PROCESSING_MQD_EN__SHIFT 0xd +#define CP_MQD_CONTROL__MQD_ATC_MASK 0x800000 +#define CP_MQD_CONTROL__MQD_ATC__SHIFT 0x17 +#define CP_MQD_CONTROL__CACHE_POLICY_MASK 0x1000000 +#define CP_MQD_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_MQD_CONTROL__MTYPE_MASK 0x18000000 +#define CP_MQD_CONTROL__MTYPE__SHIFT 0x1b +#define CP_HQD_HQ_STATUS1__STATUS_MASK 0xffffffff +#define CP_HQD_HQ_STATUS1__STATUS__SHIFT 0x0 +#define CP_HQD_HQ_CONTROL1__CONTROL_MASK 0xffffffff +#define CP_HQD_HQ_CONTROL1__CONTROL__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR_MASK 0xffffffff +#define CP_HQD_EOP_BASE_ADDR__BASE_ADDR__SHIFT 0x0 +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI_MASK 0xff +#define CP_HQD_EOP_BASE_ADDR_HI__BASE_ADDR_HI__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__EOP_SIZE_MASK 0x3f +#define CP_HQD_EOP_CONTROL__EOP_SIZE__SHIFT 0x0 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP_MASK 0x100 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOP__SHIFT 0x8 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN_MASK 0x1000 +#define CP_HQD_EOP_CONTROL__PROCESS_EOP_EN__SHIFT 0xc +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB_MASK 0x2000 +#define CP_HQD_EOP_CONTROL__PROCESSING_EOPIB__SHIFT 0xd +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN_MASK 0x4000 +#define CP_HQD_EOP_CONTROL__PROCESS_EOPIB_EN__SHIFT 0xe +#define CP_HQD_EOP_CONTROL__MTYPE_MASK 0x18000 +#define CP_HQD_EOP_CONTROL__MTYPE__SHIFT 0xf +#define CP_HQD_EOP_CONTROL__EOP_ATC_MASK 0x800000 +#define CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT 0x17 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY_MASK 0x1000000 +#define CP_HQD_EOP_CONTROL__CACHE_POLICY__SHIFT 0x18 +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT_MASK 0x60000000 +#define CP_HQD_EOP_CONTROL__SIG_SEM_RESULT__SHIFT 0x1d +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM_MASK 0x80000000 +#define CP_HQD_EOP_CONTROL__PEND_SIG_SEM__SHIFT 0x1f +#define CP_HQD_EOP_RPTR__RPTR_MASK 0x1fff +#define CP_HQD_EOP_RPTR__RPTR__SHIFT 0x0 +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR_MASK 0x40000000 +#define CP_HQD_EOP_RPTR__RPTR_EQ_CSMD_WPTR__SHIFT 0x1e +#define CP_HQD_EOP_RPTR__INIT_FETCHER_MASK 0x80000000 +#define CP_HQD_EOP_RPTR__INIT_FETCHER__SHIFT 0x1f +#define CP_HQD_EOP_WPTR__WPTR_MASK 0x1fff +#define CP_HQD_EOP_WPTR__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_WPTR__EOP_AVAIL_MASK 0x1fff0000 +#define CP_HQD_EOP_WPTR__EOP_AVAIL__SHIFT 0x10 +#define CP_HQD_EOP_EVENTS__EVENT_COUNT_MASK 0xfff +#define CP_HQD_EOP_EVENTS__EVENT_COUNT__SHIFT 0x0 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND_MASK 0x10000 +#define CP_HQD_EOP_EVENTS__CS_PARTIAL_FLUSH_PEND__SHIFT 0x10 +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR_MASK 0xfffff000 +#define CP_HQD_CTX_SAVE_BASE_ADDR_LO__ADDR__SHIFT 0xc +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI_MASK 0xffff +#define CP_HQD_CTX_SAVE_BASE_ADDR_HI__ADDR_HI__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_CONTROL__ATC_MASK 0x1 +#define CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT 0x0 +#define CP_HQD_CTX_SAVE_CONTROL__MTYPE_MASK 0x6 +#define CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT 0x1 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY_MASK 0x8 +#define CP_HQD_CTX_SAVE_CONTROL__POLICY__SHIFT 0x3 +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET_MASK 0x7ffc +#define CP_HQD_CNTL_STACK_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CNTL_STACK_SIZE__SIZE_MASK 0x7000 +#define CP_HQD_CNTL_STACK_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_WG_STATE_OFFSET__OFFSET_MASK 0x1fffffc +#define CP_HQD_WG_STATE_OFFSET__OFFSET__SHIFT 0x2 +#define CP_HQD_CTX_SAVE_SIZE__SIZE_MASK 0x1fff000 +#define CP_HQD_CTX_SAVE_SIZE__SIZE__SHIFT 0xc +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED_MASK 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__OA_REQUIRED__SHIFT 0x0 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED_MASK 0x2 +#define CP_HQD_GDS_RESOURCE_STATE__OA_ACQUIRED__SHIFT 0x1 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE_MASK 0x3f0 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_SIZE__SHIFT 0x4 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR_MASK 0x3f000 +#define CP_HQD_GDS_RESOURCE_STATE__GWS_PNTR__SHIFT 0xc +#define CP_HQD_ERROR__EDC_ERROR_ID_MASK 0xf +#define CP_HQD_ERROR__EDC_ERROR_ID__SHIFT 0x0 +#define CP_HQD_ERROR__SUA_ERROR_MASK 0x10 +#define CP_HQD_ERROR__SUA_ERROR__SHIFT 0x4 +#define CP_HQD_EOP_WPTR_MEM__WPTR_MASK 0x1fff +#define CP_HQD_EOP_WPTR_MEM__WPTR__SHIFT 0x0 +#define CP_HQD_EOP_DONES__DONE_COUNT_MASK 0xffffffff +#define CP_HQD_EOP_DONES__DONE_COUNT__SHIFT 0x0 +#define DB_Z_READ_BASE__BASE_256B_MASK 0xffffffff +#define DB_Z_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_READ_BASE__BASE_256B_MASK 0xffffffff +#define DB_STENCIL_READ_BASE__BASE_256B__SHIFT 0x0 +#define DB_Z_WRITE_BASE__BASE_256B_MASK 0xffffffff +#define DB_Z_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_STENCIL_WRITE_BASE__BASE_256B_MASK 0xffffffff +#define DB_STENCIL_WRITE_BASE__BASE_256B__SHIFT 0x0 +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK_MASK 0xf +#define DB_DEPTH_INFO__ADDR5_SWIZZLE_MASK__SHIFT 0x0 +#define DB_DEPTH_INFO__ARRAY_MODE_MASK 0xf0 +#define DB_DEPTH_INFO__ARRAY_MODE__SHIFT 0x4 +#define DB_DEPTH_INFO__PIPE_CONFIG_MASK 0x1f00 +#define DB_DEPTH_INFO__PIPE_CONFIG__SHIFT 0x8 +#define DB_DEPTH_INFO__BANK_WIDTH_MASK 0x6000 +#define DB_DEPTH_INFO__BANK_WIDTH__SHIFT 0xd +#define DB_DEPTH_INFO__BANK_HEIGHT_MASK 0x18000 +#define DB_DEPTH_INFO__BANK_HEIGHT__SHIFT 0xf +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT_MASK 0x60000 +#define DB_DEPTH_INFO__MACRO_TILE_ASPECT__SHIFT 0x11 +#define DB_DEPTH_INFO__NUM_BANKS_MASK 0x180000 +#define DB_DEPTH_INFO__NUM_BANKS__SHIFT 0x13 +#define DB_Z_INFO__FORMAT_MASK 0x3 +#define DB_Z_INFO__FORMAT__SHIFT 0x0 +#define DB_Z_INFO__NUM_SAMPLES_MASK 0xc +#define DB_Z_INFO__NUM_SAMPLES__SHIFT 0x2 +#define DB_Z_INFO__TILE_SPLIT_MASK 0xe000 +#define DB_Z_INFO__TILE_SPLIT__SHIFT 0xd +#define DB_Z_INFO__TILE_MODE_INDEX_MASK 0x700000 +#define DB_Z_INFO__TILE_MODE_INDEX__SHIFT 0x14 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES_MASK 0x7800000 +#define DB_Z_INFO__DECOMPRESS_ON_N_ZPLANES__SHIFT 0x17 +#define DB_Z_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 +#define DB_Z_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_Z_INFO__READ_SIZE_MASK 0x10000000 +#define DB_Z_INFO__READ_SIZE__SHIFT 0x1c +#define DB_Z_INFO__TILE_SURFACE_ENABLE_MASK 0x20000000 +#define DB_Z_INFO__TILE_SURFACE_ENABLE__SHIFT 0x1d +#define DB_Z_INFO__CLEAR_DISALLOWED_MASK 0x40000000 +#define DB_Z_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_Z_INFO__ZRANGE_PRECISION_MASK 0x80000000 +#define DB_Z_INFO__ZRANGE_PRECISION__SHIFT 0x1f +#define DB_STENCIL_INFO__FORMAT_MASK 0x1 +#define DB_STENCIL_INFO__FORMAT__SHIFT 0x0 +#define DB_STENCIL_INFO__TILE_SPLIT_MASK 0xe000 +#define DB_STENCIL_INFO__TILE_SPLIT__SHIFT 0xd +#define DB_STENCIL_INFO__TILE_MODE_INDEX_MASK 0x700000 +#define DB_STENCIL_INFO__TILE_MODE_INDEX__SHIFT 0x14 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR_MASK 0x8000000 +#define DB_STENCIL_INFO__ALLOW_EXPCLEAR__SHIFT 0x1b +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE_MASK 0x20000000 +#define DB_STENCIL_INFO__TILE_STENCIL_DISABLE__SHIFT 0x1d +#define DB_STENCIL_INFO__CLEAR_DISALLOWED_MASK 0x40000000 +#define DB_STENCIL_INFO__CLEAR_DISALLOWED__SHIFT 0x1e +#define DB_DEPTH_SIZE__PITCH_TILE_MAX_MASK 0x7ff +#define DB_DEPTH_SIZE__PITCH_TILE_MAX__SHIFT 0x0 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX_MASK 0x3ff800 +#define DB_DEPTH_SIZE__HEIGHT_TILE_MAX__SHIFT 0xb +#define DB_DEPTH_SLICE__SLICE_TILE_MAX_MASK 0x3fffff +#define DB_DEPTH_SLICE__SLICE_TILE_MAX__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_START_MASK 0x7ff +#define DB_DEPTH_VIEW__SLICE_START__SHIFT 0x0 +#define DB_DEPTH_VIEW__SLICE_MAX_MASK 0xffe000 +#define DB_DEPTH_VIEW__SLICE_MAX__SHIFT 0xd +#define DB_DEPTH_VIEW__Z_READ_ONLY_MASK 0x1000000 +#define DB_DEPTH_VIEW__Z_READ_ONLY__SHIFT 0x18 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY_MASK 0x2000000 +#define DB_DEPTH_VIEW__STENCIL_READ_ONLY__SHIFT 0x19 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE_MASK 0x1 +#define DB_RENDER_CONTROL__DEPTH_CLEAR_ENABLE__SHIFT 0x0 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE_MASK 0x2 +#define DB_RENDER_CONTROL__STENCIL_CLEAR_ENABLE__SHIFT 0x1 +#define DB_RENDER_CONTROL__DEPTH_COPY_MASK 0x4 +#define DB_RENDER_CONTROL__DEPTH_COPY__SHIFT 0x2 +#define DB_RENDER_CONTROL__STENCIL_COPY_MASK 0x8 +#define DB_RENDER_CONTROL__STENCIL_COPY__SHIFT 0x3 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE_MASK 0x10 +#define DB_RENDER_CONTROL__RESUMMARIZE_ENABLE__SHIFT 0x4 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE_MASK 0x20 +#define DB_RENDER_CONTROL__STENCIL_COMPRESS_DISABLE__SHIFT 0x5 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE_MASK 0x40 +#define DB_RENDER_CONTROL__DEPTH_COMPRESS_DISABLE__SHIFT 0x6 +#define DB_RENDER_CONTROL__COPY_CENTROID_MASK 0x80 +#define DB_RENDER_CONTROL__COPY_CENTROID__SHIFT 0x7 +#define DB_RENDER_CONTROL__COPY_SAMPLE_MASK 0xf00 +#define DB_RENDER_CONTROL__COPY_SAMPLE__SHIFT 0x8 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE_MASK 0x1000 +#define DB_RENDER_CONTROL__DECOMPRESS_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE_MASK 0x1 +#define DB_COUNT_CONTROL__ZPASS_INCREMENT_DISABLE__SHIFT 0x0 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS_MASK 0x2 +#define DB_COUNT_CONTROL__PERFECT_ZPASS_COUNTS__SHIFT 0x1 +#define DB_COUNT_CONTROL__SAMPLE_RATE_MASK 0x70 +#define DB_COUNT_CONTROL__SAMPLE_RATE__SHIFT 0x4 +#define DB_COUNT_CONTROL__ZPASS_ENABLE_MASK 0xf00 +#define DB_COUNT_CONTROL__ZPASS_ENABLE__SHIFT 0x8 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE_MASK 0xf000 +#define DB_COUNT_CONTROL__ZFAIL_ENABLE__SHIFT 0xc +#define DB_COUNT_CONTROL__SFAIL_ENABLE_MASK 0xf0000 +#define DB_COUNT_CONTROL__SFAIL_ENABLE__SHIFT 0x10 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE_MASK 0xf00000 +#define DB_COUNT_CONTROL__DBFAIL_ENABLE__SHIFT 0x14 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE_MASK 0xf000000 +#define DB_COUNT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x18 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE_MASK 0xf0000000 +#define DB_COUNT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE_MASK 0x3 +#define DB_RENDER_OVERRIDE__FORCE_HIZ_ENABLE__SHIFT 0x0 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0_MASK 0xc +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE0__SHIFT 0x2 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1_MASK 0x30 +#define DB_RENDER_OVERRIDE__FORCE_HIS_ENABLE1__SHIFT 0x4 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER_MASK 0x40 +#define DB_RENDER_OVERRIDE__FORCE_SHADER_Z_ORDER__SHIFT 0x6 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE_MASK 0x80 +#define DB_RENDER_OVERRIDE__FAST_Z_DISABLE__SHIFT 0x7 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE_MASK 0x100 +#define DB_RENDER_OVERRIDE__FAST_STENCIL_DISABLE__SHIFT 0x8 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE_MASK 0x200 +#define DB_RENDER_OVERRIDE__NOOP_CULL_DISABLE__SHIFT 0x9 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL_MASK 0x400 +#define DB_RENDER_OVERRIDE__FORCE_COLOR_KILL__SHIFT 0xa +#define DB_RENDER_OVERRIDE__FORCE_Z_READ_MASK 0x800 +#define DB_RENDER_OVERRIDE__FORCE_Z_READ__SHIFT 0xb +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ_MASK 0x1000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_READ__SHIFT 0xc +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE_MASK 0x6000 +#define DB_RENDER_OVERRIDE__FORCE_FULL_Z_RANGE__SHIFT 0xd +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT_MASK 0x8000 +#define DB_RENDER_OVERRIDE__FORCE_QC_SMASK_CONFLICT__SHIFT 0xf +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP_MASK 0x10000 +#define DB_RENDER_OVERRIDE__DISABLE_VIEWPORT_CLAMP__SHIFT 0x10 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE_MASK 0x20000 +#define DB_RENDER_OVERRIDE__IGNORE_SC_ZRANGE__SHIFT 0x11 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED_MASK 0x40000 +#define DB_RENDER_OVERRIDE__DISABLE_FULLY_COVERED__SHIFT 0x12 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM_MASK 0x180000 +#define DB_RENDER_OVERRIDE__FORCE_Z_LIMIT_SUMM__SHIFT 0x13 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT_MASK 0x3e00000 +#define DB_RENDER_OVERRIDE__MAX_TILES_IN_DTT__SHIFT 0x15 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES_MASK 0x4000000 +#define DB_RENDER_OVERRIDE__DISABLE_TILE_RATE_TILES__SHIFT 0x1a +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY_MASK 0x8000000 +#define DB_RENDER_OVERRIDE__FORCE_Z_DIRTY__SHIFT 0x1b +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY_MASK 0x10000000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_DIRTY__SHIFT 0x1c +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID_MASK 0x20000000 +#define DB_RENDER_OVERRIDE__FORCE_Z_VALID__SHIFT 0x1d +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID_MASK 0x40000000 +#define DB_RENDER_OVERRIDE__FORCE_STENCIL_VALID__SHIFT 0x1e +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION_MASK 0x80000000 +#define DB_RENDER_OVERRIDE__PRESERVE_COMPRESSION__SHIFT 0x1f +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL_MASK 0x3 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_CONTROL__SHIFT 0x0 +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN_MASK 0x1c +#define DB_RENDER_OVERRIDE2__PARTIAL_SQUAD_LAUNCH_COUNTDOWN__SHIFT 0x2 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION_MASK 0x20 +#define DB_RENDER_OVERRIDE2__DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION__SHIFT 0x5 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION_MASK 0x40 +#define DB_RENDER_OVERRIDE2__DISABLE_SMEM_EXPCLEAR_OPTIMIZATION__SHIFT 0x6 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION_MASK 0x80 +#define DB_RENDER_OVERRIDE2__DISABLE_COLOR_ON_VALIDATION__SHIFT 0x7 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH_MASK 0x100 +#define DB_RENDER_OVERRIDE2__DECOMPRESS_Z_ON_FLUSH__SHIFT 0x8 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP_MASK 0x200 +#define DB_RENDER_OVERRIDE2__DISABLE_REG_SNOOP__SHIFT 0x9 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE_MASK 0x400 +#define DB_RENDER_OVERRIDE2__DEPTH_BOUNDS_HIER_DEPTH_DISABLE__SHIFT 0xa +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE_MASK 0x800 +#define DB_RENDER_OVERRIDE2__SEPARATE_HIZS_FUNC_ENABLE__SHIFT 0xb +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC_MASK 0x7000 +#define DB_RENDER_OVERRIDE2__HIZ_ZFUNC__SHIFT 0xc +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF_MASK 0x38000 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_FF__SHIFT 0xf +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF_MASK 0x1c0000 +#define DB_RENDER_OVERRIDE2__HIS_SFUNC_BF__SHIFT 0x12 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE_MASK 0x200000 +#define DB_RENDER_OVERRIDE2__PRESERVE_ZRANGE__SHIFT 0x15 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS_MASK 0x400000 +#define DB_RENDER_OVERRIDE2__PRESERVE_SRESULTS__SHIFT 0x16 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS_MASK 0x800000 +#define DB_RENDER_OVERRIDE2__DISABLE_FAST_PASS__SHIFT 0x17 +#define DB_EQAA__MAX_ANCHOR_SAMPLES_MASK 0x7 +#define DB_EQAA__MAX_ANCHOR_SAMPLES__SHIFT 0x0 +#define DB_EQAA__PS_ITER_SAMPLES_MASK 0x70 +#define DB_EQAA__PS_ITER_SAMPLES__SHIFT 0x4 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES_MASK 0x700 +#define DB_EQAA__MASK_EXPORT_NUM_SAMPLES__SHIFT 0x8 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES_MASK 0x7000 +#define DB_EQAA__ALPHA_TO_MASK_NUM_SAMPLES__SHIFT 0xc +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS_MASK 0x10000 +#define DB_EQAA__HIGH_QUALITY_INTERSECTIONS__SHIFT 0x10 +#define DB_EQAA__INCOHERENT_EQAA_READS_MASK 0x20000 +#define DB_EQAA__INCOHERENT_EQAA_READS__SHIFT 0x11 +#define DB_EQAA__INTERPOLATE_COMP_Z_MASK 0x40000 +#define DB_EQAA__INTERPOLATE_COMP_Z__SHIFT 0x12 +#define DB_EQAA__INTERPOLATE_SRC_Z_MASK 0x80000 +#define DB_EQAA__INTERPOLATE_SRC_Z__SHIFT 0x13 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS_MASK 0x100000 +#define DB_EQAA__STATIC_ANCHOR_ASSOCIATIONS__SHIFT 0x14 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE_MASK 0x200000 +#define DB_EQAA__ALPHA_TO_MASK_EQAA_DISABLE__SHIFT 0x15 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT_MASK 0x7000000 +#define DB_EQAA__OVERRASTERIZATION_AMOUNT__SHIFT 0x18 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION_MASK 0x8000000 +#define DB_EQAA__ENABLE_POSTZ_OVERRASTERIZATION__SHIFT 0x1b +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE_MASK 0x1 +#define DB_SHADER_CONTROL__Z_EXPORT_ENABLE__SHIFT 0x0 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE_MASK 0x2 +#define DB_SHADER_CONTROL__STENCIL_TEST_VAL_EXPORT_ENABLE__SHIFT 0x1 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE_MASK 0x4 +#define DB_SHADER_CONTROL__STENCIL_OP_VAL_EXPORT_ENABLE__SHIFT 0x2 +#define DB_SHADER_CONTROL__Z_ORDER_MASK 0x30 +#define DB_SHADER_CONTROL__Z_ORDER__SHIFT 0x4 +#define DB_SHADER_CONTROL__KILL_ENABLE_MASK 0x40 +#define DB_SHADER_CONTROL__KILL_ENABLE__SHIFT 0x6 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE_MASK 0x80 +#define DB_SHADER_CONTROL__COVERAGE_TO_MASK_ENABLE__SHIFT 0x7 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE_MASK 0x100 +#define DB_SHADER_CONTROL__MASK_EXPORT_ENABLE__SHIFT 0x8 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL_MASK 0x200 +#define DB_SHADER_CONTROL__EXEC_ON_HIER_FAIL__SHIFT 0x9 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP_MASK 0x400 +#define DB_SHADER_CONTROL__EXEC_ON_NOOP__SHIFT 0xa +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE_MASK 0x800 +#define DB_SHADER_CONTROL__ALPHA_TO_MASK_DISABLE__SHIFT 0xb +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER_MASK 0x1000 +#define DB_SHADER_CONTROL__DEPTH_BEFORE_SHADER__SHIFT 0xc +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT_MASK 0x6000 +#define DB_SHADER_CONTROL__CONSERVATIVE_Z_EXPORT__SHIFT 0xd +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE_MASK 0x8000 +#define DB_SHADER_CONTROL__DUAL_QUAD_DISABLE__SHIFT 0xf +#define DB_DEPTH_BOUNDS_MIN__MIN_MASK 0xffffffff +#define DB_DEPTH_BOUNDS_MIN__MIN__SHIFT 0x0 +#define DB_DEPTH_BOUNDS_MAX__MAX_MASK 0xffffffff +#define DB_DEPTH_BOUNDS_MAX__MAX__SHIFT 0x0 +#define DB_STENCIL_CLEAR__CLEAR_MASK 0xff +#define DB_STENCIL_CLEAR__CLEAR__SHIFT 0x0 +#define DB_DEPTH_CLEAR__DEPTH_CLEAR_MASK 0xffffffff +#define DB_DEPTH_CLEAR__DEPTH_CLEAR__SHIFT 0x0 +#define DB_HTILE_DATA_BASE__BASE_256B_MASK 0xffffffff +#define DB_HTILE_DATA_BASE__BASE_256B__SHIFT 0x0 +#define DB_HTILE_SURFACE__LINEAR_MASK 0x1 +#define DB_HTILE_SURFACE__LINEAR__SHIFT 0x0 +#define DB_HTILE_SURFACE__FULL_CACHE_MASK 0x2 +#define DB_HTILE_SURFACE__FULL_CACHE__SHIFT 0x1 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN_MASK 0x4 +#define DB_HTILE_SURFACE__HTILE_USES_PRELOAD_WIN__SHIFT 0x2 +#define DB_HTILE_SURFACE__PRELOAD_MASK 0x8 +#define DB_HTILE_SURFACE__PRELOAD__SHIFT 0x3 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH_MASK 0x3f0 +#define DB_HTILE_SURFACE__PREFETCH_WIDTH__SHIFT 0x4 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT_MASK 0xfc00 +#define DB_HTILE_SURFACE__PREFETCH_HEIGHT__SHIFT 0xa +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE_MASK 0x10000 +#define DB_HTILE_SURFACE__DST_OUTSIDE_ZERO_TO_ONE__SHIFT 0x10 +#define DB_HTILE_SURFACE__TC_COMPATIBLE_MASK 0x20000 +#define DB_HTILE_SURFACE__TC_COMPATIBLE__SHIFT 0x11 +#define DB_PRELOAD_CONTROL__START_X_MASK 0xff +#define DB_PRELOAD_CONTROL__START_X__SHIFT 0x0 +#define DB_PRELOAD_CONTROL__START_Y_MASK 0xff00 +#define DB_PRELOAD_CONTROL__START_Y__SHIFT 0x8 +#define DB_PRELOAD_CONTROL__MAX_X_MASK 0xff0000 +#define DB_PRELOAD_CONTROL__MAX_X__SHIFT 0x10 +#define DB_PRELOAD_CONTROL__MAX_Y_MASK 0xff000000 +#define DB_PRELOAD_CONTROL__MAX_Y__SHIFT 0x18 +#define DB_STENCILREFMASK__STENCILTESTVAL_MASK 0xff +#define DB_STENCILREFMASK__STENCILTESTVAL__SHIFT 0x0 +#define DB_STENCILREFMASK__STENCILMASK_MASK 0xff00 +#define DB_STENCILREFMASK__STENCILMASK__SHIFT 0x8 +#define DB_STENCILREFMASK__STENCILWRITEMASK_MASK 0xff0000 +#define DB_STENCILREFMASK__STENCILWRITEMASK__SHIFT 0x10 +#define DB_STENCILREFMASK__STENCILOPVAL_MASK 0xff000000 +#define DB_STENCILREFMASK__STENCILOPVAL__SHIFT 0x18 +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF_MASK 0xff +#define DB_STENCILREFMASK_BF__STENCILTESTVAL_BF__SHIFT 0x0 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF_MASK 0xff00 +#define DB_STENCILREFMASK_BF__STENCILMASK_BF__SHIFT 0x8 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF_MASK 0xff0000 +#define DB_STENCILREFMASK_BF__STENCILWRITEMASK_BF__SHIFT 0x10 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF_MASK 0xff000000 +#define DB_STENCILREFMASK_BF__STENCILOPVAL_BF__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0_MASK 0x7 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREFUNC0__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0_MASK 0xff0 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREVALUE0__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0_MASK 0xff000 +#define DB_SRESULTS_COMPARE_STATE0__COMPAREMASK0__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0_MASK 0x1000000 +#define DB_SRESULTS_COMPARE_STATE0__ENABLE0__SHIFT 0x18 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1_MASK 0x7 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREFUNC1__SHIFT 0x0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1_MASK 0xff0 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREVALUE1__SHIFT 0x4 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1_MASK 0xff000 +#define DB_SRESULTS_COMPARE_STATE1__COMPAREMASK1__SHIFT 0xc +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1_MASK 0x1000000 +#define DB_SRESULTS_COMPARE_STATE1__ENABLE1__SHIFT 0x18 +#define DB_DEPTH_CONTROL__STENCIL_ENABLE_MASK 0x1 +#define DB_DEPTH_CONTROL__STENCIL_ENABLE__SHIFT 0x0 +#define DB_DEPTH_CONTROL__Z_ENABLE_MASK 0x2 +#define DB_DEPTH_CONTROL__Z_ENABLE__SHIFT 0x1 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE_MASK 0x4 +#define DB_DEPTH_CONTROL__Z_WRITE_ENABLE__SHIFT 0x2 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE_MASK 0x8 +#define DB_DEPTH_CONTROL__DEPTH_BOUNDS_ENABLE__SHIFT 0x3 +#define DB_DEPTH_CONTROL__ZFUNC_MASK 0x70 +#define DB_DEPTH_CONTROL__ZFUNC__SHIFT 0x4 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE_MASK 0x80 +#define DB_DEPTH_CONTROL__BACKFACE_ENABLE__SHIFT 0x7 +#define DB_DEPTH_CONTROL__STENCILFUNC_MASK 0x700 +#define DB_DEPTH_CONTROL__STENCILFUNC__SHIFT 0x8 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF_MASK 0x700000 +#define DB_DEPTH_CONTROL__STENCILFUNC_BF__SHIFT 0x14 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK 0x40000000 +#define DB_DEPTH_CONTROL__ENABLE_COLOR_WRITES_ON_DEPTH_FAIL__SHIFT 0x1e +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK 0x80000000 +#define DB_DEPTH_CONTROL__DISABLE_COLOR_WRITES_ON_DEPTH_PASS__SHIFT 0x1f +#define DB_STENCIL_CONTROL__STENCILFAIL_MASK 0xf +#define DB_STENCIL_CONTROL__STENCILFAIL__SHIFT 0x0 +#define DB_STENCIL_CONTROL__STENCILZPASS_MASK 0xf0 +#define DB_STENCIL_CONTROL__STENCILZPASS__SHIFT 0x4 +#define DB_STENCIL_CONTROL__STENCILZFAIL_MASK 0xf00 +#define DB_STENCIL_CONTROL__STENCILZFAIL__SHIFT 0x8 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF_MASK 0xf000 +#define DB_STENCIL_CONTROL__STENCILFAIL_BF__SHIFT 0xc +#define DB_STENCIL_CONTROL__STENCILZPASS_BF_MASK 0xf0000 +#define DB_STENCIL_CONTROL__STENCILZPASS_BF__SHIFT 0x10 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF_MASK 0xf00000 +#define DB_STENCIL_CONTROL__STENCILZFAIL_BF__SHIFT 0x14 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE_MASK 0x1 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_ENABLE__SHIFT 0x0 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0_MASK 0x300 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET0__SHIFT 0x8 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1_MASK 0xc00 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET1__SHIFT 0xa +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2_MASK 0x3000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET2__SHIFT 0xc +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3_MASK 0xc000 +#define DB_ALPHA_TO_MASK__ALPHA_TO_MASK_OFFSET3__SHIFT 0xe +#define DB_ALPHA_TO_MASK__OFFSET_ROUND_MASK 0x10000 +#define DB_ALPHA_TO_MASK__OFFSET_ROUND__SHIFT 0x10 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define DB_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 +#define DB_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define DB_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1_MASK 0xf000000 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT 0x18 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define DB_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define DB_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define DB_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define DB_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define DB_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define DB_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define DB_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE_MASK 0x1 +#define DB_DEBUG__DEBUG_STENCIL_COMPRESS_DISABLE__SHIFT 0x0 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE_MASK 0x2 +#define DB_DEBUG__DEBUG_DEPTH_COMPRESS_DISABLE__SHIFT 0x1 +#define DB_DEBUG__FETCH_FULL_Z_TILE_MASK 0x4 +#define DB_DEBUG__FETCH_FULL_Z_TILE__SHIFT 0x2 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE_MASK 0x8 +#define DB_DEBUG__FETCH_FULL_STENCIL_TILE__SHIFT 0x3 +#define DB_DEBUG__FORCE_Z_MODE_MASK 0x30 +#define DB_DEBUG__FORCE_Z_MODE__SHIFT 0x4 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ_MASK 0x40 +#define DB_DEBUG__DEBUG_FORCE_DEPTH_READ__SHIFT 0x6 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ_MASK 0x80 +#define DB_DEBUG__DEBUG_FORCE_STENCIL_READ__SHIFT 0x7 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE_MASK 0x300 +#define DB_DEBUG__DEBUG_FORCE_HIZ_ENABLE__SHIFT 0x8 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0_MASK 0xc00 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE0__SHIFT 0xa +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1_MASK 0x3000 +#define DB_DEBUG__DEBUG_FORCE_HIS_ENABLE1__SHIFT 0xc +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE_MASK 0x4000 +#define DB_DEBUG__DEBUG_FAST_Z_DISABLE__SHIFT 0xe +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE_MASK 0x8000 +#define DB_DEBUG__DEBUG_FAST_STENCIL_DISABLE__SHIFT 0xf +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE_MASK 0x10000 +#define DB_DEBUG__DEBUG_NOOP_CULL_DISABLE__SHIFT 0x10 +#define DB_DEBUG__DISABLE_SUMM_SQUADS_MASK 0x20000 +#define DB_DEBUG__DISABLE_SUMM_SQUADS__SHIFT 0x11 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS_MASK 0x40000 +#define DB_DEBUG__DEPTH_CACHE_FORCE_MISS__SHIFT 0x12 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE_MASK 0x180000 +#define DB_DEBUG__DEBUG_FORCE_FULL_Z_RANGE__SHIFT 0x13 +#define DB_DEBUG__NEVER_FREE_Z_ONLY_MASK 0x200000 +#define DB_DEBUG__NEVER_FREE_Z_ONLY__SHIFT 0x15 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS_MASK 0x400000 +#define DB_DEBUG__ZPASS_COUNTS_LOOK_AT_PIPE_STAT_EVENTS__SHIFT 0x16 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION_MASK 0x800000 +#define DB_DEBUG__DISABLE_VPORT_ZPLANE_OPTIMIZATION__SHIFT 0x17 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES_MASK 0xf000000 +#define DB_DEBUG__DECOMPRESS_AFTER_N_ZPLANES__SHIFT 0x18 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT_MASK 0x10000000 +#define DB_DEBUG__ONE_FREE_IN_FLIGHT__SHIFT 0x1c +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT_MASK 0x20000000 +#define DB_DEBUG__FORCE_MISS_IF_NOT_INFLIGHT__SHIFT 0x1d +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC_MASK 0x40000000 +#define DB_DEBUG__DISABLE_DEPTH_SURFACE_SYNC__SHIFT 0x1e +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC_MASK 0x80000000 +#define DB_DEBUG__DISABLE_HTILE_SURFACE_SYNC__SHIFT 0x1f +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING_MASK 0x1 +#define DB_DEBUG2__ALLOW_COMPZ_BYTE_MASKING__SHIFT 0x0 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE_MASK 0x2 +#define DB_DEBUG2__DISABLE_TC_ZRANGE_L0_CACHE__SHIFT 0x1 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE_MASK 0x4 +#define DB_DEBUG2__DISABLE_TC_MASK_L0_CACHE__SHIFT 0x2 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB_MASK 0x8 +#define DB_DEBUG2__DTR_ROUND_ROBIN_ARB__SHIFT 0x3 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM_MASK 0x10 +#define DB_DEBUG2__DTR_PREZ_STALLS_FOR_ETF_ROOM__SHIFT 0x4 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_MASK 0x20 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL__SHIFT 0x5 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL_MASK 0x40 +#define DB_DEBUG2__ENABLE_PREZL_CB_STALL__SHIFT 0x6 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ_MASK 0x80 +#define DB_DEBUG2__DISABLE_PREZL_LPF_STALL_REZ__SHIFT 0x7 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ_MASK 0x100 +#define DB_DEBUG2__DISABLE_PREZL_CB_STALL_REZ__SHIFT 0x8 +#define DB_DEBUG2__CLK_OFF_DELAY_MASK 0x3e00 +#define DB_DEBUG2__CLK_OFF_DELAY__SHIFT 0x9 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER_MASK 0x4000 +#define DB_DEBUG2__DISABLE_TILE_COVERED_FOR_PS_ITER__SHIFT 0xe +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING_MASK 0x8000 +#define DB_DEBUG2__ENABLE_SUBTILE_GROUPING__SHIFT 0xf +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES_MASK 0x10000 +#define DB_DEBUG2__DISABLE_HTILE_PAIRED_PIPES__SHIFT 0x10 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING_MASK 0x20000 +#define DB_DEBUG2__DISABLE_NULL_EOT_FORWARDING__SHIFT 0x11 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING_MASK 0x40000 +#define DB_DEBUG2__DISABLE_DTT_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL_MASK 0x80000 +#define DB_DEBUG2__DISABLE_QUAD_COHERENCY_STALL__SHIFT 0x13 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM_MASK 0x10000000 +#define DB_DEBUG2__ENABLE_PREZ_OF_REZ_SUMM__SHIFT 0x1c +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL_MASK 0x20000000 +#define DB_DEBUG2__DISABLE_PREZL_VIEWPORT_STALL__SHIFT 0x1d +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM_MASK 0x40000000 +#define DB_DEBUG2__DISABLE_SINGLE_STENCIL_QUAD_SUMM__SHIFT 0x1e +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT_MASK 0x80000000 +#define DB_DEBUG2__DISABLE_WRITE_STALL_ON_RDWR_CONFLICT__SHIFT 0x1f +#define DB_DEBUG3__FORCE_DB_IS_GOOD_MASK 0x4 +#define DB_DEBUG3__FORCE_DB_IS_GOOD__SHIFT 0x2 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION_MASK 0x8 +#define DB_DEBUG3__DISABLE_TL_SSO_NULL_SUPPRESSION__SHIFT 0x3 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP_MASK 0x10 +#define DB_DEBUG3__DISABLE_HIZ_ON_VPORT_CLAMP__SHIFT 0x4 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z_MASK 0x20 +#define DB_DEBUG3__EQAA_INTERPOLATE_COMP_Z__SHIFT 0x5 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z_MASK 0x40 +#define DB_DEBUG3__EQAA_INTERPOLATE_SRC_Z__SHIFT 0x6 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS_MASK 0x80 +#define DB_DEBUG3__DISABLE_TCP_CAM_BYPASS__SHIFT 0x7 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION_MASK 0x100 +#define DB_DEBUG3__DISABLE_ZCMP_DIRTY_SUPPRESSION__SHIFT 0x8 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT_MASK 0x200 +#define DB_DEBUG3__DISABLE_REDUNDANT_PLANE_FLUSHES_OPT__SHIFT 0x9 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP_MASK 0x400 +#define DB_DEBUG3__DISABLE_RECOMP_TO_1ZPLANE_WITHOUT_FASTOP__SHIFT 0xa +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS_MASK 0x800 +#define DB_DEBUG3__ENABLE_INCOHERENT_EQAA_READS__SHIFT 0xb +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING_MASK 0x1000 +#define DB_DEBUG3__DISABLE_OP_Z_DATA_FORWARDING__SHIFT 0xc +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS_MASK 0x2000 +#define DB_DEBUG3__DISABLE_OP_DF_BYPASS__SHIFT 0xd +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE_MASK 0x4000 +#define DB_DEBUG3__DISABLE_OP_DF_WRITE_COMBINE__SHIFT 0xe +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK_MASK 0x8000 +#define DB_DEBUG3__DISABLE_OP_DF_DIRECT_FEEDBACK__SHIFT 0xf +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION_MASK 0x10000 +#define DB_DEBUG3__ALLOW_RF2P_RW_COLLISION__SHIFT 0x10 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE_MASK 0x20000 +#define DB_DEBUG3__SLOW_PREZ_TO_A2M_OMASK_RATE__SHIFT 0x11 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING_MASK 0x40000 +#define DB_DEBUG3__DISABLE_OP_S_DATA_FORWARDING__SHIFT 0x12 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE_MASK 0x80000 +#define DB_DEBUG3__DISABLE_TC_UPDATE_WRITE_COMBINE__SHIFT 0x13 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE_MASK 0x100000 +#define DB_DEBUG3__DISABLE_HZ_TC_WRITE_COMBINE__SHIFT 0x14 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT_MASK 0x200000 +#define DB_DEBUG3__ENABLE_RECOMP_ZDIRTY_SUPPRESSION_OPT__SHIFT 0x15 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB_MASK 0x400000 +#define DB_DEBUG3__ENABLE_TC_MA_ROUND_ROBIN_ARB__SHIFT 0x16 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD_MASK 0x800000 +#define DB_DEBUG3__DISABLE_RAM_READ_SUPPRESION_ON_FWD__SHIFT 0x17 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT_MASK 0x1000000 +#define DB_DEBUG3__DISABLE_EQAA_A2M_PERF_OPT__SHIFT 0x18 +#define DB_DEBUG3__DISABLE_DI_DT_STALL_MASK 0x2000000 +#define DB_DEBUG3__DISABLE_DI_DT_STALL__SHIFT 0x19 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET_MASK 0x4000000 +#define DB_DEBUG3__ENABLE_DB_PROCESS_RESET__SHIFT 0x1a +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX_MASK 0x8000000 +#define DB_DEBUG3__DISABLE_OVERRASTERIZATION_FIX__SHIFT 0x1b +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND_MASK 0x10000000 +#define DB_DEBUG3__DONT_INSERT_CONTEXT_SUSPEND__SHIFT 0x1c +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND_MASK 0x20000000 +#define DB_DEBUG3__DONT_DELETE_CONTEXT_SUSPEND__SHIFT 0x1d +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE_MASK 0x40000000 +#define DB_DEBUG3__DISABLE_4XAA_2P_DELAYED_WRITE__SHIFT 0x1e +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK_MASK 0x80000000 +#define DB_DEBUG3__DISABLE_4XAA_2P_INTERLEAVED_PMASK__SHIFT 0x1f +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION_MASK 0x1 +#define DB_DEBUG4__DISABLE_QC_Z_MASK_SUMMATION__SHIFT 0x0 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION_MASK 0x2 +#define DB_DEBUG4__DISABLE_QC_STENCIL_MASK_SUMMATION__SHIFT 0x1 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL_MASK 0x4 +#define DB_DEBUG4__DISABLE_RESUMM_TO_SINGLE_STENCIL__SHIFT 0x2 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL_MASK 0x8 +#define DB_DEBUG4__DISABLE_PREZ_POSTZ_DTILE_CONFLICT_STALL__SHIFT 0x3 +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF_MASK 0x10 +#define DB_DEBUG4__DISABLE_4XAA_2P_ZD_HOLDOFF__SHIFT 0x4 +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION_MASK 0x20 +#define DB_DEBUG4__ENABLE_A2M_DQUAD_OPTIMIZATION__SHIFT 0x5 +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE_MASK 0x40 +#define DB_DEBUG4__ENABLE_DBCB_SLOW_FORMAT_COLLAPSE__SHIFT 0x6 +#define DB_DEBUG4__DB_EXTRA_DEBUG4_MASK 0xffffff80 +#define DB_DEBUG4__DB_EXTRA_DEBUG4__SHIFT 0x7 +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS_MASK 0x1f +#define DB_CREDIT_LIMIT__DB_SC_TILE_CREDITS__SHIFT 0x0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS_MASK 0x3e0 +#define DB_CREDIT_LIMIT__DB_SC_QUAD_CREDITS__SHIFT 0x5 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS_MASK 0x1c00 +#define DB_CREDIT_LIMIT__DB_CB_LQUAD_CREDITS__SHIFT 0xa +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS_MASK 0x7f000000 +#define DB_CREDIT_LIMIT__DB_CB_TILE_CREDITS__SHIFT 0x18 +#define DB_WATERMARKS__DEPTH_FREE_MASK 0x1f +#define DB_WATERMARKS__DEPTH_FREE__SHIFT 0x0 +#define DB_WATERMARKS__DEPTH_FLUSH_MASK 0x7e0 +#define DB_WATERMARKS__DEPTH_FLUSH__SHIFT 0x5 +#define DB_WATERMARKS__FORCE_SUMMARIZE_MASK 0x7800 +#define DB_WATERMARKS__FORCE_SUMMARIZE__SHIFT 0xb +#define DB_WATERMARKS__DEPTH_PENDING_FREE_MASK 0xf8000 +#define DB_WATERMARKS__DEPTH_PENDING_FREE__SHIFT 0xf +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE_MASK 0x7f00000 +#define DB_WATERMARKS__DEPTH_CACHELINE_FREE__SHIFT 0x14 +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE_MASK 0x8000000 +#define DB_WATERMARKS__EARLY_Z_PANIC_DISABLE__SHIFT 0x1b +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE_MASK 0x10000000 +#define DB_WATERMARKS__LATE_Z_PANIC_DISABLE__SHIFT 0x1c +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE_MASK 0x20000000 +#define DB_WATERMARKS__RE_Z_PANIC_DISABLE__SHIFT 0x1d +#define DB_WATERMARKS__AUTO_FLUSH_HTILE_MASK 0x40000000 +#define DB_WATERMARKS__AUTO_FLUSH_HTILE__SHIFT 0x1e +#define DB_WATERMARKS__AUTO_FLUSH_QUAD_MASK 0x80000000 +#define DB_WATERMARKS__AUTO_FLUSH_QUAD__SHIFT 0x1f +#define DB_SUBTILE_CONTROL__MSAA1_X_MASK 0x3 +#define DB_SUBTILE_CONTROL__MSAA1_X__SHIFT 0x0 +#define DB_SUBTILE_CONTROL__MSAA1_Y_MASK 0xc +#define DB_SUBTILE_CONTROL__MSAA1_Y__SHIFT 0x2 +#define DB_SUBTILE_CONTROL__MSAA2_X_MASK 0x30 +#define DB_SUBTILE_CONTROL__MSAA2_X__SHIFT 0x4 +#define DB_SUBTILE_CONTROL__MSAA2_Y_MASK 0xc0 +#define DB_SUBTILE_CONTROL__MSAA2_Y__SHIFT 0x6 +#define DB_SUBTILE_CONTROL__MSAA4_X_MASK 0x300 +#define DB_SUBTILE_CONTROL__MSAA4_X__SHIFT 0x8 +#define DB_SUBTILE_CONTROL__MSAA4_Y_MASK 0xc00 +#define DB_SUBTILE_CONTROL__MSAA4_Y__SHIFT 0xa +#define DB_SUBTILE_CONTROL__MSAA8_X_MASK 0x3000 +#define DB_SUBTILE_CONTROL__MSAA8_X__SHIFT 0xc +#define DB_SUBTILE_CONTROL__MSAA8_Y_MASK 0xc000 +#define DB_SUBTILE_CONTROL__MSAA8_Y__SHIFT 0xe +#define DB_SUBTILE_CONTROL__MSAA16_X_MASK 0x30000 +#define DB_SUBTILE_CONTROL__MSAA16_X__SHIFT 0x10 +#define DB_SUBTILE_CONTROL__MSAA16_Y_MASK 0xc0000 +#define DB_SUBTILE_CONTROL__MSAA16_Y__SHIFT 0x12 +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH_MASK 0x7f +#define DB_FREE_CACHELINES__FREE_DTILE_DEPTH__SHIFT 0x0 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH_MASK 0x3f80 +#define DB_FREE_CACHELINES__FREE_PLANE_DEPTH__SHIFT 0x7 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH_MASK 0x1fc000 +#define DB_FREE_CACHELINES__FREE_Z_DEPTH__SHIFT 0xe +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH_MASK 0x1e00000 +#define DB_FREE_CACHELINES__FREE_HTILE_DEPTH__SHIFT 0x15 +#define DB_FREE_CACHELINES__QUAD_READ_REQS_MASK 0xfe000000 +#define DB_FREE_CACHELINES__QUAD_READ_REQS__SHIFT 0x19 +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH_MASK 0x1f +#define DB_FIFO_DEPTH1__MI_RDREQ_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH_MASK 0x3e0 +#define DB_FIFO_DEPTH1__MI_WRREQ_FIFO_DEPTH__SHIFT 0x5 +#define DB_FIFO_DEPTH1__MCC_DEPTH_MASK 0xfc00 +#define DB_FIFO_DEPTH1__MCC_DEPTH__SHIFT 0xa +#define DB_FIFO_DEPTH1__QC_DEPTH_MASK 0x1f0000 +#define DB_FIFO_DEPTH1__QC_DEPTH__SHIFT 0x10 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH_MASK 0x1fe00000 +#define DB_FIFO_DEPTH1__LTILE_PROBE_FIFO_DEPTH__SHIFT 0x15 +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH_MASK 0xff +#define DB_FIFO_DEPTH2__EQUAD_FIFO_DEPTH__SHIFT 0x0 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH_MASK 0x7f00 +#define DB_FIFO_DEPTH2__ETILE_OP_FIFO_DEPTH__SHIFT 0x8 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH_MASK 0x1ff8000 +#define DB_FIFO_DEPTH2__LQUAD_FIFO_DEPTH__SHIFT 0xf +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH_MASK 0xfe000000 +#define DB_FIFO_DEPTH2__LTILE_OP_FIFO_DEPTH__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__ON_DELAY_MASK 0xf +#define DB_CGTT_CLK_CTRL_0__ON_DELAY__SHIFT 0x0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS_MASK 0xff0 +#define DB_CGTT_CLK_CTRL_0__OFF_HYSTERESIS__SHIFT 0x4 +#define DB_CGTT_CLK_CTRL_0__RESERVED_MASK 0xfff000 +#define DB_CGTT_CLK_CTRL_0__RESERVED__SHIFT 0xc +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7_MASK 0x1000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE7__SHIFT 0x18 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6_MASK 0x2000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE6__SHIFT 0x19 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5_MASK 0x4000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE5__SHIFT 0x1a +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4_MASK 0x8000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE4__SHIFT 0x1b +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3_MASK 0x10000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE3__SHIFT 0x1c +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2_MASK 0x20000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE2__SHIFT 0x1d +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1_MASK 0x40000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE1__SHIFT 0x1e +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0_MASK 0x80000000 +#define DB_CGTT_CLK_CTRL_0__SOFT_OVERRIDE0__SHIFT 0x1f +#define DB_ZPASS_COUNT_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_ZPASS_COUNT_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_ZPASS_COUNT_HI__COUNT_HI_MASK 0x7fffffff +#define DB_ZPASS_COUNT_HI__COUNT_HI__SHIFT 0x0 +#define DB_RING_CONTROL__COUNTER_CONTROL_MASK 0x3 +#define DB_RING_CONTROL__COUNTER_CONTROL__SHIFT 0x0 +#define DB_READ_DEBUG_0__BUSY_DATA0_MASK 0xffffffff +#define DB_READ_DEBUG_0__BUSY_DATA0__SHIFT 0x0 +#define DB_READ_DEBUG_1__BUSY_DATA1_MASK 0xffffffff +#define DB_READ_DEBUG_1__BUSY_DATA1__SHIFT 0x0 +#define DB_READ_DEBUG_2__BUSY_DATA2_MASK 0xffffffff +#define DB_READ_DEBUG_2__BUSY_DATA2__SHIFT 0x0 +#define DB_READ_DEBUG_3__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_3__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_4__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_4__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_5__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_5__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_6__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_6__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_7__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_7__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_8__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_8__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_9__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_9__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_A__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_A__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_B__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_B__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_C__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_C__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_D__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_D__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_E__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_E__DEBUG_DATA__SHIFT 0x0 +#define DB_READ_DEBUG_F__DEBUG_DATA_MASK 0xffffffff +#define DB_READ_DEBUG_F__DEBUG_DATA__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT0_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT1_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT1_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT2_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT2_HI__COUNT_HI__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW_MASK 0xffffffff +#define DB_OCCLUSION_COUNT3_LOW__COUNT_LOW__SHIFT 0x0 +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI_MASK 0x7fffffff +#define DB_OCCLUSION_COUNT3_HI__COUNT_HI__SHIFT 0x0 +#define CC_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define CC_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define CC_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define CC_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define CC_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define CC_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0_MASK 0xf00 +#define GC_USER_RB_REDUNDANCY__FAILED_RB0__SHIFT 0x8 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0_MASK 0x1000 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY0__SHIFT 0xc +#define GC_USER_RB_REDUNDANCY__FAILED_RB1_MASK 0xf0000 +#define GC_USER_RB_REDUNDANCY__FAILED_RB1__SHIFT 0x10 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1_MASK 0x100000 +#define GC_USER_RB_REDUNDANCY__EN_REDUNDANCY1__SHIFT 0x14 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0xff0000 +#define GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_PIPES_MASK 0x7 +#define GB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70 +#define GB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700 +#define GB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000 +#define GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000 +#define GB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 +#define GB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000 +#define GB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000 +#define GB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 +#define GB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000 +#define GB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000 +#define GB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e +#define GB_BACKEND_MAP__BACKEND_MAP_MASK 0xffffffff +#define GB_BACKEND_MAP__BACKEND_MAP__SHIFT 0x0 +#define GB_GPU_ID__GPU_ID_MASK 0xf +#define GB_GPU_ID__GPU_ID__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_0_MASK 0xf +#define CC_RB_DAISY_CHAIN__RB_0__SHIFT 0x0 +#define CC_RB_DAISY_CHAIN__RB_1_MASK 0xf0 +#define CC_RB_DAISY_CHAIN__RB_1__SHIFT 0x4 +#define CC_RB_DAISY_CHAIN__RB_2_MASK 0xf00 +#define CC_RB_DAISY_CHAIN__RB_2__SHIFT 0x8 +#define CC_RB_DAISY_CHAIN__RB_3_MASK 0xf000 +#define CC_RB_DAISY_CHAIN__RB_3__SHIFT 0xc +#define CC_RB_DAISY_CHAIN__RB_4_MASK 0xf0000 +#define CC_RB_DAISY_CHAIN__RB_4__SHIFT 0x10 +#define CC_RB_DAISY_CHAIN__RB_5_MASK 0xf00000 +#define CC_RB_DAISY_CHAIN__RB_5__SHIFT 0x14 +#define CC_RB_DAISY_CHAIN__RB_6_MASK 0xf000000 +#define CC_RB_DAISY_CHAIN__RB_6__SHIFT 0x18 +#define CC_RB_DAISY_CHAIN__RB_7_MASK 0xf0000000 +#define CC_RB_DAISY_CHAIN__RB_7__SHIFT 0x1c +#define GB_TILE_MODE0__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE0__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE0__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE0__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE0__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE0__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE0__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE0__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE1__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE1__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE1__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE1__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE1__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE1__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE1__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE1__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE1__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE2__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE2__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE2__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE2__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE2__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE2__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE2__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE2__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE2__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE3__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE3__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE3__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE3__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE3__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE3__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE3__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE3__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE3__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE4__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE4__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE4__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE4__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE4__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE4__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE4__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE4__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE4__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE5__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE5__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE5__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE5__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE5__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE5__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE5__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE5__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE5__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE6__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE6__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE6__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE6__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE6__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE6__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE6__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE6__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE6__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE7__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE7__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE7__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE7__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE7__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE7__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE7__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE7__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE7__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE8__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE8__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE8__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE8__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE8__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE8__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE8__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE8__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE8__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE9__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE9__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE9__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE9__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE9__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE9__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE9__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE9__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE9__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE10__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE10__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE10__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE10__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE10__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE10__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE10__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE10__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE10__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE11__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE11__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE11__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE11__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE11__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE11__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE11__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE11__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE11__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE12__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE12__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE12__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE12__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE12__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE12__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE12__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE12__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE12__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE13__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE13__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE13__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE13__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE13__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE13__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE13__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE13__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE13__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE14__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE14__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE14__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE14__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE14__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE14__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE14__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE14__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE14__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE15__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE15__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE15__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE15__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE15__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE15__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE15__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE15__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE15__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE16__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE16__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE16__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE16__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE16__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE16__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE16__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE16__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE16__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE17__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE17__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE17__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE17__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE17__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE17__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE17__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE17__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE17__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE18__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE18__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE18__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE18__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE18__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE18__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE18__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE18__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE18__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE19__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE19__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE19__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE19__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE19__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE19__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE19__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE19__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE19__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE20__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE20__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE20__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE20__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE20__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE20__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE20__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE20__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE20__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE21__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE21__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE21__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE21__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE21__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE21__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE21__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE21__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE21__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE22__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE22__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE22__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE22__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE22__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE22__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE22__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE22__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE22__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE23__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE23__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE23__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE23__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE23__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE23__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE23__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE23__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE23__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE24__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE24__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE24__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE24__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE24__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE24__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE24__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE24__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE24__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE25__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE25__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE25__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE25__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE25__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE25__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE25__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE25__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE25__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE26__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE26__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE26__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE26__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE26__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE26__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE26__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE26__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE26__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE27__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE27__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE27__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE27__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE27__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE27__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE27__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE27__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE27__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE28__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE28__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE28__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE28__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE28__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE28__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE28__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE28__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE28__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE29__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE29__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE29__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE29__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE29__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE29__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE29__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE29__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE29__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE30__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE30__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE30__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE30__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE30__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE30__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE30__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE30__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE30__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_TILE_MODE31__ARRAY_MODE_MASK 0x3c +#define GB_TILE_MODE31__ARRAY_MODE__SHIFT 0x2 +#define GB_TILE_MODE31__PIPE_CONFIG_MASK 0x7c0 +#define GB_TILE_MODE31__PIPE_CONFIG__SHIFT 0x6 +#define GB_TILE_MODE31__TILE_SPLIT_MASK 0x3800 +#define GB_TILE_MODE31__TILE_SPLIT__SHIFT 0xb +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW_MASK 0x1c00000 +#define GB_TILE_MODE31__MICRO_TILE_MODE_NEW__SHIFT 0x16 +#define GB_TILE_MODE31__SAMPLE_SPLIT_MASK 0x6000000 +#define GB_TILE_MODE31__SAMPLE_SPLIT__SHIFT 0x19 +#define GB_MACROTILE_MODE0__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE0__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE0__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE0__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE0__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE0__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE0__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE1__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE1__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE1__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE1__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE1__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE1__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE1__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE2__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE2__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE2__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE2__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE2__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE2__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE2__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE3__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE3__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE3__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE3__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE3__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE3__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE3__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE4__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE4__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE4__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE4__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE4__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE4__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE4__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE5__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE5__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE5__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE5__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE5__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE5__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE5__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE6__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE6__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE6__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE6__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE6__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE6__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE6__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE7__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE7__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE7__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE7__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE7__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE7__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE7__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE8__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE8__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE8__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE8__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE8__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE8__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE8__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE9__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE9__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE9__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE9__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE9__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE9__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE9__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE10__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE10__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE10__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE10__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE10__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE10__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE10__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE11__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE11__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE11__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE11__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE11__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE11__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE11__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE12__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE12__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE12__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE12__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE12__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE12__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE12__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE13__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE13__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE13__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE13__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE13__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE13__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE13__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE14__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE14__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE14__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE14__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE14__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE14__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE14__NUM_BANKS__SHIFT 0x6 +#define GB_MACROTILE_MODE15__BANK_WIDTH_MASK 0x3 +#define GB_MACROTILE_MODE15__BANK_WIDTH__SHIFT 0x0 +#define GB_MACROTILE_MODE15__BANK_HEIGHT_MASK 0xc +#define GB_MACROTILE_MODE15__BANK_HEIGHT__SHIFT 0x2 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT_MASK 0x30 +#define GB_MACROTILE_MODE15__MACRO_TILE_ASPECT__SHIFT 0x4 +#define GB_MACROTILE_MODE15__NUM_BANKS_MASK 0xc0 +#define GB_MACROTILE_MODE15__NUM_BANKS__SHIFT 0x6 +#define GB_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x10000 +#define GB_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0x10 +#define GB_EDC_MODE__DED_MODE_MASK 0x300000 +#define GB_EDC_MODE__DED_MODE__SHIFT 0x14 +#define GB_EDC_MODE__PROP_FED_MASK 0x20000000 +#define GB_EDC_MODE__PROP_FED__SHIFT 0x1d +#define GB_EDC_MODE__BYPASS_MASK 0x80000000 +#define GB_EDC_MODE__BYPASS__SHIFT 0x1f +#define CC_GC_EDC_CONFIG__DIS_EDC_MASK 0x2 +#define CC_GC_EDC_CONFIG__DIS_EDC__SHIFT 0x1 +#define RAS_SIGNATURE_CONTROL__ENABLE_MASK 0x1 +#define RAS_SIGNATURE_CONTROL__ENABLE__SHIFT 0x0 +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK_MASK 0xffffffff +#define RAS_SIGNATURE_MASK__INPUT_BUS_MASK__SHIFT 0x0 +#define RAS_SX_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE2__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SX_SIGNATURE3__SIGNATURE_MASK 0xffffffff +#define RAS_SX_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_DB_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_DB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_PA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_PA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_VGT_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_VGT_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE2__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE2__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE3__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE3__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE4__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE4__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE5__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE5__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE6__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE6__SIGNATURE__SHIFT 0x0 +#define RAS_SC_SIGNATURE7__SIGNATURE_MASK 0xffffffff +#define RAS_SC_SIGNATURE7__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_IA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_IA_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_IA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_SPI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_SPI_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_SPI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_TA_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_TD_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_TD_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_CB_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_CB_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE0__SIGNATURE_MASK 0xffffffff +#define RAS_BCI_SIGNATURE0__SIGNATURE__SHIFT 0x0 +#define RAS_BCI_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_BCI_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define RAS_TA_SIGNATURE1__SIGNATURE_MASK 0xffffffff +#define RAS_TA_SIGNATURE1__SIGNATURE__SHIFT 0x0 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX_MASK 0x7 +#define GRBM_HYP_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_CAM_INDEX__CAM_INDEX_MASK 0x7 +#define GRBM_CAM_INDEX__CAM_INDEX__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_ADDR_MASK 0xffff +#define GRBM_HYP_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define GRBM_HYP_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CAM_DATA__CAM_ADDR_MASK 0xffff +#define GRBM_CAM_DATA__CAM_ADDR__SHIFT 0x0 +#define GRBM_CAM_DATA__CAM_REMAPADDR_MASK 0xffff0000 +#define GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT 0x10 +#define GRBM_CNTL__READ_TIMEOUT_MASK 0xff +#define GRBM_CNTL__READ_TIMEOUT__SHIFT 0x0 +#define GRBM_CNTL__REPORT_LAST_RDERR_MASK 0x80000000 +#define GRBM_CNTL__REPORT_LAST_RDERR__SHIFT 0x1f +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD_MASK 0x3f +#define GRBM_SKEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0 +#define GRBM_SKEW_CNTL__SKEW_COUNT_MASK 0xfc0 +#define GRBM_SKEW_CNTL__SKEW_COUNT__SHIFT 0x6 +#define GRBM_PWR_CNTL__ALL_REQ_TYPE_MASK 0x3 +#define GRBM_PWR_CNTL__ALL_REQ_TYPE__SHIFT 0x0 +#define GRBM_PWR_CNTL__GFX_REQ_TYPE_MASK 0xc +#define GRBM_PWR_CNTL__GFX_REQ_TYPE__SHIFT 0x2 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE_MASK 0x30 +#define GRBM_PWR_CNTL__ALL_RSP_TYPE__SHIFT 0x4 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE_MASK 0xc0 +#define GRBM_PWR_CNTL__GFX_RSP_TYPE__SHIFT 0x6 +#define GRBM_PWR_CNTL__GFX_REQ_EN_MASK 0x4000 +#define GRBM_PWR_CNTL__GFX_REQ_EN__SHIFT 0xe +#define GRBM_PWR_CNTL__ALL_REQ_EN_MASK 0x8000 +#define GRBM_PWR_CNTL__ALL_REQ_EN__SHIFT 0xf +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL_MASK 0xf +#define GRBM_STATUS__ME0PIPE0_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS__SRBM_RQ_PENDING_MASK 0x20 +#define GRBM_STATUS__SRBM_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING_MASK 0x80 +#define GRBM_STATUS__ME0PIPE0_CF_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING_MASK 0x100 +#define GRBM_STATUS__ME0PIPE0_PF_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING_MASK 0x200 +#define GRBM_STATUS__GDS_DMA_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS__DB_CLEAN_MASK 0x1000 +#define GRBM_STATUS__DB_CLEAN__SHIFT 0xc +#define GRBM_STATUS__CB_CLEAN_MASK 0x2000 +#define GRBM_STATUS__CB_CLEAN__SHIFT 0xd +#define GRBM_STATUS__TA_BUSY_MASK 0x4000 +#define GRBM_STATUS__TA_BUSY__SHIFT 0xe +#define GRBM_STATUS__GDS_BUSY_MASK 0x8000 +#define GRBM_STATUS__GDS_BUSY__SHIFT 0xf +#define GRBM_STATUS__WD_BUSY_NO_DMA_MASK 0x10000 +#define GRBM_STATUS__WD_BUSY_NO_DMA__SHIFT 0x10 +#define GRBM_STATUS__VGT_BUSY_MASK 0x20000 +#define GRBM_STATUS__VGT_BUSY__SHIFT 0x11 +#define GRBM_STATUS__IA_BUSY_NO_DMA_MASK 0x40000 +#define GRBM_STATUS__IA_BUSY_NO_DMA__SHIFT 0x12 +#define GRBM_STATUS__IA_BUSY_MASK 0x80000 +#define GRBM_STATUS__IA_BUSY__SHIFT 0x13 +#define GRBM_STATUS__SX_BUSY_MASK 0x100000 +#define GRBM_STATUS__SX_BUSY__SHIFT 0x14 +#define GRBM_STATUS__WD_BUSY_MASK 0x200000 +#define GRBM_STATUS__WD_BUSY__SHIFT 0x15 +#define GRBM_STATUS__SPI_BUSY_MASK 0x400000 +#define GRBM_STATUS__SPI_BUSY__SHIFT 0x16 +#define GRBM_STATUS__BCI_BUSY_MASK 0x800000 +#define GRBM_STATUS__BCI_BUSY__SHIFT 0x17 +#define GRBM_STATUS__SC_BUSY_MASK 0x1000000 +#define GRBM_STATUS__SC_BUSY__SHIFT 0x18 +#define GRBM_STATUS__PA_BUSY_MASK 0x2000000 +#define GRBM_STATUS__PA_BUSY__SHIFT 0x19 +#define GRBM_STATUS__DB_BUSY_MASK 0x4000000 +#define GRBM_STATUS__DB_BUSY__SHIFT 0x1a +#define GRBM_STATUS__CP_COHERENCY_BUSY_MASK 0x10000000 +#define GRBM_STATUS__CP_COHERENCY_BUSY__SHIFT 0x1c +#define GRBM_STATUS__CP_BUSY_MASK 0x20000000 +#define GRBM_STATUS__CP_BUSY__SHIFT 0x1d +#define GRBM_STATUS__CB_BUSY_MASK 0x40000000 +#define GRBM_STATUS__CB_BUSY__SHIFT 0x1e +#define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000 +#define GRBM_STATUS__GUI_ACTIVE__SHIFT 0x1f +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL_MASK 0xf +#define GRBM_STATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING_MASK 0x10 +#define GRBM_STATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING_MASK 0x20 +#define GRBM_STATUS2__ME0PIPE1_PF_RQ_PENDING__SHIFT 0x5 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING_MASK 0x40 +#define GRBM_STATUS2__ME1PIPE0_RQ_PENDING__SHIFT 0x6 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING_MASK 0x80 +#define GRBM_STATUS2__ME1PIPE1_RQ_PENDING__SHIFT 0x7 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING_MASK 0x100 +#define GRBM_STATUS2__ME1PIPE2_RQ_PENDING__SHIFT 0x8 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING_MASK 0x200 +#define GRBM_STATUS2__ME1PIPE3_RQ_PENDING__SHIFT 0x9 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING_MASK 0x400 +#define GRBM_STATUS2__ME2PIPE0_RQ_PENDING__SHIFT 0xa +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING_MASK 0x800 +#define GRBM_STATUS2__ME2PIPE1_RQ_PENDING__SHIFT 0xb +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING_MASK 0x1000 +#define GRBM_STATUS2__ME2PIPE2_RQ_PENDING__SHIFT 0xc +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING_MASK 0x2000 +#define GRBM_STATUS2__ME2PIPE3_RQ_PENDING__SHIFT 0xd +#define GRBM_STATUS2__RLC_RQ_PENDING_MASK 0x4000 +#define GRBM_STATUS2__RLC_RQ_PENDING__SHIFT 0xe +#define GRBM_STATUS2__RLC_BUSY_MASK 0x1000000 +#define GRBM_STATUS2__RLC_BUSY__SHIFT 0x18 +#define GRBM_STATUS2__TC_BUSY_MASK 0x2000000 +#define GRBM_STATUS2__TC_BUSY__SHIFT 0x19 +#define GRBM_STATUS2__TCC_CC_RESIDENT_MASK 0x4000000 +#define GRBM_STATUS2__TCC_CC_RESIDENT__SHIFT 0x1a +#define GRBM_STATUS2__CPF_BUSY_MASK 0x10000000 +#define GRBM_STATUS2__CPF_BUSY__SHIFT 0x1c +#define GRBM_STATUS2__CPC_BUSY_MASK 0x20000000 +#define GRBM_STATUS2__CPC_BUSY__SHIFT 0x1d +#define GRBM_STATUS2__CPG_BUSY_MASK 0x40000000 +#define GRBM_STATUS2__CPG_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE0__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE0__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE0__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE0__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE0__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE0__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE0__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE0__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE0__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE0__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE0__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE0__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE0__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE0__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE0__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE0__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE0__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE0__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE0__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE0__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE0__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE1__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE1__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE1__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE1__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE1__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE1__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE1__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE1__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE1__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE1__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE1__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE1__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE1__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE1__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE1__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE1__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE1__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE1__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE1__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE1__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE1__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE1__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE2__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE2__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE2__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE2__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE2__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE2__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE2__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE2__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE2__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE2__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE2__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE2__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE2__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE2__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE2__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE2__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE2__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE2__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE2__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE2__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE2__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE2__CB_BUSY__SHIFT 0x1f +#define GRBM_STATUS_SE3__DB_CLEAN_MASK 0x2 +#define GRBM_STATUS_SE3__DB_CLEAN__SHIFT 0x1 +#define GRBM_STATUS_SE3__CB_CLEAN_MASK 0x4 +#define GRBM_STATUS_SE3__CB_CLEAN__SHIFT 0x2 +#define GRBM_STATUS_SE3__BCI_BUSY_MASK 0x400000 +#define GRBM_STATUS_SE3__BCI_BUSY__SHIFT 0x16 +#define GRBM_STATUS_SE3__VGT_BUSY_MASK 0x800000 +#define GRBM_STATUS_SE3__VGT_BUSY__SHIFT 0x17 +#define GRBM_STATUS_SE3__PA_BUSY_MASK 0x1000000 +#define GRBM_STATUS_SE3__PA_BUSY__SHIFT 0x18 +#define GRBM_STATUS_SE3__TA_BUSY_MASK 0x2000000 +#define GRBM_STATUS_SE3__TA_BUSY__SHIFT 0x19 +#define GRBM_STATUS_SE3__SX_BUSY_MASK 0x4000000 +#define GRBM_STATUS_SE3__SX_BUSY__SHIFT 0x1a +#define GRBM_STATUS_SE3__SPI_BUSY_MASK 0x8000000 +#define GRBM_STATUS_SE3__SPI_BUSY__SHIFT 0x1b +#define GRBM_STATUS_SE3__SC_BUSY_MASK 0x20000000 +#define GRBM_STATUS_SE3__SC_BUSY__SHIFT 0x1d +#define GRBM_STATUS_SE3__DB_BUSY_MASK 0x40000000 +#define GRBM_STATUS_SE3__DB_BUSY__SHIFT 0x1e +#define GRBM_STATUS_SE3__CB_BUSY_MASK 0x80000000 +#define GRBM_STATUS_SE3__CB_BUSY__SHIFT 0x1f +#define GRBM_SOFT_RESET__SOFT_RESET_CP_MASK 0x1 +#define GRBM_SOFT_RESET__SOFT_RESET_CP__SHIFT 0x0 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK 0x4 +#define GRBM_SOFT_RESET__SOFT_RESET_RLC__SHIFT 0x2 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK 0x10000 +#define GRBM_SOFT_RESET__SOFT_RESET_GFX__SHIFT 0x10 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF_MASK 0x20000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPF__SHIFT 0x11 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC_MASK 0x40000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPC__SHIFT 0x12 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG_MASK 0x80000 +#define GRBM_SOFT_RESET__SOFT_RESET_CPG__SHIFT 0x13 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC_MASK 0x100000 +#define GRBM_SOFT_RESET__SOFT_RESET_CAC__SHIFT 0x14 +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX_MASK 0x3f +#define GRBM_DEBUG_CNTL__GRBM_DEBUG_INDEX__SHIFT 0x0 +#define GRBM_DEBUG_DATA__DATA_MASK 0xffffffff +#define GRBM_DEBUG_DATA__DATA__SHIFT 0x0 +#define GRBM_CGTT_CLK_CNTL__ON_DELAY_MASK 0xf +#define GRBM_CGTT_CLK_CNTL__ON_DELAY__SHIFT 0x0 +#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS_MASK 0xff0 +#define GRBM_CGTT_CLK_CNTL__OFF_HYSTERESIS__SHIFT 0x4 +#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define GRBM_CGTT_CLK_CNTL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define GRBM_GFX_INDEX__INSTANCE_INDEX_MASK 0xff +#define GRBM_GFX_INDEX__INSTANCE_INDEX__SHIFT 0x0 +#define GRBM_GFX_INDEX__SH_INDEX_MASK 0xff00 +#define GRBM_GFX_INDEX__SH_INDEX__SHIFT 0x8 +#define GRBM_GFX_INDEX__SE_INDEX_MASK 0xff0000 +#define GRBM_GFX_INDEX__SE_INDEX__SHIFT 0x10 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK 0x20000000 +#define GRBM_GFX_INDEX__SH_BROADCAST_WRITES__SHIFT 0x1d +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK 0x40000000 +#define GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT 0x1e +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK 0x80000000 +#define GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT 0x1f +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT_MASK 0xf +#define GRBM_GFX_CLKEN_CNTL__PREFIX_DELAY_CNT__SHIFT 0x0 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT_MASK 0x1f00 +#define GRBM_GFX_CLKEN_CNTL__POST_DELAY_CNT__SHIFT 0x8 +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS_MASK 0xff +#define GRBM_WAIT_IDLE_CLOCKS__WAIT_IDLE_CLOCKS__SHIFT 0x0 +#define GRBM_DEBUG__IGNORE_RDY_MASK 0x2 +#define GRBM_DEBUG__IGNORE_RDY__SHIFT 0x1 +#define GRBM_DEBUG__IGNORE_FAO_MASK 0x20 +#define GRBM_DEBUG__IGNORE_FAO__SHIFT 0x5 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT_MASK 0x40 +#define GRBM_DEBUG__DISABLE_READ_TIMEOUT__SHIFT 0x6 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS_MASK 0x80 +#define GRBM_DEBUG__SNAPSHOT_FREE_CNTRS__SHIFT 0x7 +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE_MASK 0xf00 +#define GRBM_DEBUG__HYSTERESIS_GUI_ACTIVE__SHIFT 0x8 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE_MASK 0x1000 +#define GRBM_DEBUG__GFX_CLOCK_DOMAIN_OVERRIDE__SHIFT 0xc +#define GRBM_DEBUG__GRBM_TRAP_ENABLE_MASK 0x2000 +#define GRBM_DEBUG__GRBM_TRAP_ENABLE__SHIFT 0xd +#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN_MASK 0x80000000 +#define GRBM_DEBUG__DEBUG_BUS_FGCG_EN__SHIFT 0x1f +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY_MASK 0x1 +#define GRBM_DEBUG_SNAPSHOT__CPF_RDY__SHIFT 0x0 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY_MASK 0x2 +#define GRBM_DEBUG_SNAPSHOT__CPG_RDY__SHIFT 0x1 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY_MASK 0x4 +#define GRBM_DEBUG_SNAPSHOT__SRBM_RDY__SHIFT 0x2 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY_MASK 0x8 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE0_RDY__SHIFT 0x3 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY_MASK 0x10 +#define GRBM_DEBUG_SNAPSHOT__WD_ME0PIPE1_RDY__SHIFT 0x4 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY_MASK 0x20 +#define GRBM_DEBUG_SNAPSHOT__GDS_RDY__SHIFT 0x5 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0_MASK 0x40 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY0__SHIFT 0x6 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0_MASK 0x80 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY0__SHIFT 0x7 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0_MASK 0x100 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY0__SHIFT 0x8 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0_MASK 0x200 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY0__SHIFT 0x9 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0_MASK 0x400 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY0__SHIFT 0xa +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0_MASK 0x800 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY0__SHIFT 0xb +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0_MASK 0x1000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY0__SHIFT 0xc +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0_MASK 0x2000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY0__SHIFT 0xd +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1_MASK 0x4000 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE0_RDY1__SHIFT 0xe +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1_MASK 0x8000 +#define GRBM_DEBUG_SNAPSHOT__SE0SPI_ME0PIPE1_RDY1__SHIFT 0xf +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1_MASK 0x10000 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE0_RDY1__SHIFT 0x10 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1_MASK 0x20000 +#define GRBM_DEBUG_SNAPSHOT__SE1SPI_ME0PIPE1_RDY1__SHIFT 0x11 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1_MASK 0x40000 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE0_RDY1__SHIFT 0x12 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1_MASK 0x80000 +#define GRBM_DEBUG_SNAPSHOT__SE2SPI_ME0PIPE1_RDY1__SHIFT 0x13 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1_MASK 0x100000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE0_RDY1__SHIFT 0x14 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1_MASK 0x200000 +#define GRBM_DEBUG_SNAPSHOT__SE3SPI_ME0PIPE1_RDY1__SHIFT 0x15 +#define GRBM_READ_ERROR__READ_ADDRESS_MASK 0x3fffc +#define GRBM_READ_ERROR__READ_ADDRESS__SHIFT 0x2 +#define GRBM_READ_ERROR__READ_PIPEID_MASK 0x300000 +#define GRBM_READ_ERROR__READ_PIPEID__SHIFT 0x14 +#define GRBM_READ_ERROR__READ_MEID_MASK 0xc00000 +#define GRBM_READ_ERROR__READ_MEID__SHIFT 0x16 +#define GRBM_READ_ERROR__READ_ERROR_MASK 0x80000000 +#define GRBM_READ_ERROR__READ_ERROR__SHIFT 0x1f +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM_MASK 0x20000 +#define GRBM_READ_ERROR2__READ_REQUESTER_SRBM__SHIFT 0x11 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC_MASK 0x40000 +#define GRBM_READ_ERROR2__READ_REQUESTER_RLC__SHIFT 0x12 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA_MASK 0x80000 +#define GRBM_READ_ERROR2__READ_REQUESTER_GDS_DMA__SHIFT 0x13 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF_MASK 0x100000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_CF__SHIFT 0x14 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF_MASK 0x200000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE0_PF__SHIFT 0x15 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF_MASK 0x400000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_CF__SHIFT 0x16 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF_MASK 0x800000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME0PIPE1_PF__SHIFT 0x17 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0_MASK 0x1000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE0__SHIFT 0x18 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1_MASK 0x2000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE1__SHIFT 0x19 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2_MASK 0x4000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE2__SHIFT 0x1a +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3_MASK 0x8000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME1PIPE3__SHIFT 0x1b +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0_MASK 0x10000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE0__SHIFT 0x1c +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1_MASK 0x20000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE1__SHIFT 0x1d +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2_MASK 0x40000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE2__SHIFT 0x1e +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3_MASK 0x80000000 +#define GRBM_READ_ERROR2__READ_REQUESTER_ME2PIPE3__SHIFT 0x1f +#define GRBM_INT_CNTL__RDERR_INT_ENABLE_MASK 0x1 +#define GRBM_INT_CNTL__RDERR_INT_ENABLE__SHIFT 0x0 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE_MASK 0x80000 +#define GRBM_INT_CNTL__GUI_IDLE_INT_ENABLE__SHIFT 0x13 +#define GRBM_TRAP_OP__RW_MASK 0x1 +#define GRBM_TRAP_OP__RW__SHIFT 0x0 +#define GRBM_TRAP_ADDR__DATA_MASK 0xffff +#define GRBM_TRAP_ADDR__DATA__SHIFT 0x0 +#define GRBM_TRAP_ADDR_MSK__DATA_MASK 0xffff +#define GRBM_TRAP_ADDR_MSK__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD__DATA_MASK 0xffffffff +#define GRBM_TRAP_WD__DATA__SHIFT 0x0 +#define GRBM_TRAP_WD_MSK__DATA_MASK 0xffffffff +#define GRBM_TRAP_WD_MSK__DATA__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_BITS_MASK 0x3 +#define GRBM_DSM_BYPASS__BYPASS_BITS__SHIFT 0x0 +#define GRBM_DSM_BYPASS__BYPASS_EN_MASK 0x4 +#define GRBM_DSM_BYPASS__BYPASS_EN__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC_MASK 0x1 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_RLC__SHIFT 0x0 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM_MASK 0x2 +#define GRBM_WRITE_ERROR__WRITE_REQUESTER_SRBM__SHIFT 0x1 +#define GRBM_WRITE_ERROR__WRITE_SSRCID_MASK 0x1c +#define GRBM_WRITE_ERROR__WRITE_SSRCID__SHIFT 0x2 +#define GRBM_WRITE_ERROR__WRITE_VFID_MASK 0x1e0 +#define GRBM_WRITE_ERROR__WRITE_VFID__SHIFT 0x5 +#define GRBM_WRITE_ERROR__WRITE_VF_MASK 0x1000 +#define GRBM_WRITE_ERROR__WRITE_VF__SHIFT 0xc +#define GRBM_WRITE_ERROR__WRITE_VMID_MASK 0x1e000 +#define GRBM_WRITE_ERROR__WRITE_VMID__SHIFT 0xd +#define GRBM_WRITE_ERROR__WRITE_PIPEID_MASK 0x300000 +#define GRBM_WRITE_ERROR__WRITE_PIPEID__SHIFT 0x14 +#define GRBM_WRITE_ERROR__WRITE_MEID_MASK 0xc00000 +#define GRBM_WRITE_ERROR__WRITE_MEID__SHIFT 0x16 +#define GRBM_WRITE_ERROR__WRITE_ERROR_MASK 0x80000000 +#define GRBM_WRITE_ERROR__WRITE_ERROR__SHIFT 0x1f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_PERFCOUNTER0_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 +#define GRBM_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_PERFCOUNTER0_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_PERFCOUNTER0_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 +#define GRBM_PERFCOUNTER0_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 +#define GRBM_PERFCOUNTER0_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 +#define GRBM_PERFCOUNTER0_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 +#define GRBM_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 +#define GRBM_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 +#define GRBM_PERFCOUNTER0_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 +#define GRBM_PERFCOUNTER0_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_PERFCOUNTER1_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x4000 +#define GRBM_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xe +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_PERFCOUNTER1_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_PERFCOUNTER1_SELECT__GRBM_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK_MASK 0x400000 +#define GRBM_PERFCOUNTER1_SELECT__CP_BUSY_USER_DEFINED_MASK__SHIFT 0x16 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK_MASK 0x800000 +#define GRBM_PERFCOUNTER1_SELECT__IA_BUSY_USER_DEFINED_MASK__SHIFT 0x17 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK_MASK 0x1000000 +#define GRBM_PERFCOUNTER1_SELECT__GDS_BUSY_USER_DEFINED_MASK__SHIFT 0x18 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x2000000 +#define GRBM_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x19 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK 0x4000000 +#define GRBM_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT 0x1a +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK_MASK 0x8000000 +#define GRBM_PERFCOUNTER1_SELECT__TC_BUSY_USER_DEFINED_MASK__SHIFT 0x1b +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK_MASK 0x10000000 +#define GRBM_PERFCOUNTER1_SELECT__WD_BUSY_USER_DEFINED_MASK__SHIFT 0x1c +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE0_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE0_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE0_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE0_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE0_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE0_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE0_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE0_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE1_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE1_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE1_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE1_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE1_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE1_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE1_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE1_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE2_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE2_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE2_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE2_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE2_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE2_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE2_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE2_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL_MASK 0x3f +#define GRBM_SE3_PERFCOUNTER_SELECT__PERF_SEL__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK 0x400 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT 0xa +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK 0x800 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT 0xb +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK 0x1000 +#define GRBM_SE3_PERFCOUNTER_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT 0xc +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK 0x2000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT 0xd +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK 0x8000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT 0xf +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK_MASK 0x10000 +#define GRBM_SE3_PERFCOUNTER_SELECT__SC_BUSY_USER_DEFINED_MASK__SHIFT 0x10 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK 0x20000 +#define GRBM_SE3_PERFCOUNTER_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT 0x11 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK 0x40000 +#define GRBM_SE3_PERFCOUNTER_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT 0x12 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK_MASK 0x80000 +#define GRBM_SE3_PERFCOUNTER_SELECT__VGT_BUSY_USER_DEFINED_MASK__SHIFT 0x13 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK 0x100000 +#define GRBM_SE3_PERFCOUNTER_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT 0x14 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK 0x200000 +#define GRBM_SE3_PERFCOUNTER_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT 0x15 +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE0_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE0_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE1_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE1_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE2_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE2_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GRBM_SE3_PERFCOUNTER_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GRBM_SE3_PERFCOUNTER_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GRBM_SCRATCH_REG0__SCRATCH_REG0_MASK 0xffffffff +#define GRBM_SCRATCH_REG0__SCRATCH_REG0__SHIFT 0x0 +#define GRBM_SCRATCH_REG1__SCRATCH_REG1_MASK 0xffffffff +#define GRBM_SCRATCH_REG1__SCRATCH_REG1__SHIFT 0x0 +#define GRBM_SCRATCH_REG2__SCRATCH_REG2_MASK 0xffffffff +#define GRBM_SCRATCH_REG2__SCRATCH_REG2__SHIFT 0x0 +#define GRBM_SCRATCH_REG3__SCRATCH_REG3_MASK 0xffffffff +#define GRBM_SCRATCH_REG3__SCRATCH_REG3__SHIFT 0x0 +#define GRBM_SCRATCH_REG4__SCRATCH_REG4_MASK 0xffffffff +#define GRBM_SCRATCH_REG4__SCRATCH_REG4__SHIFT 0x0 +#define GRBM_SCRATCH_REG5__SCRATCH_REG5_MASK 0xffffffff +#define GRBM_SCRATCH_REG5__SCRATCH_REG5__SHIFT 0x0 +#define GRBM_SCRATCH_REG6__SCRATCH_REG6_MASK 0xffffffff +#define GRBM_SCRATCH_REG6__SCRATCH_REG6__SHIFT 0x0 +#define GRBM_SCRATCH_REG7__SCRATCH_REG7_MASK 0xffffffff +#define GRBM_SCRATCH_REG7__SCRATCH_REG7__SHIFT 0x0 +#define DEBUG_INDEX__DEBUG_INDEX_MASK 0x3ffff +#define DEBUG_INDEX__DEBUG_INDEX__SHIFT 0x0 +#define DEBUG_DATA__DEBUG_DATA_MASK 0xffffffff +#define DEBUG_DATA__DEBUG_DATA__SHIFT 0x0 +#define GRBM_NOWHERE__DATA_MASK 0xffffffff +#define GRBM_NOWHERE__DATA__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_1__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_2__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_3__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_4__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_5__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_6__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_7__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_8__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_9__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_10__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_11__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_12__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_13__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_14__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE_MASK 0xffffffff +#define PA_CL_VPORT_XSCALE_15__VPORT_XSCALE__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_1__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_2__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_3__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_4__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_5__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_6__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_7__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_8__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_9__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_10__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_11__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_12__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_13__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_14__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_XOFFSET_15__VPORT_XOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_1__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_2__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_3__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_4__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_5__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_6__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_7__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_8__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_9__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_10__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_11__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_12__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_13__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_14__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE_MASK 0xffffffff +#define PA_CL_VPORT_YSCALE_15__VPORT_YSCALE__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_1__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_2__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_3__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_4__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_5__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_6__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_7__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_8__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_9__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_10__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_11__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_12__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_13__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_14__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_YOFFSET_15__VPORT_YOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_1__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_2__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_3__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_4__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_5__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_6__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_7__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_8__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_9__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_10__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_11__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_12__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_13__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_14__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE_MASK 0xffffffff +#define PA_CL_VPORT_ZSCALE_15__VPORT_ZSCALE__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_1__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_2__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_3__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_4__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_5__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_6__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_7__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_8__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_9__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_10__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_11__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_12__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_13__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_14__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET_MASK 0xffffffff +#define PA_CL_VPORT_ZOFFSET_15__VPORT_ZOFFSET__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA_MASK 0x1 +#define PA_CL_VTE_CNTL__VPORT_X_SCALE_ENA__SHIFT 0x0 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA_MASK 0x2 +#define PA_CL_VTE_CNTL__VPORT_X_OFFSET_ENA__SHIFT 0x1 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA_MASK 0x4 +#define PA_CL_VTE_CNTL__VPORT_Y_SCALE_ENA__SHIFT 0x2 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA_MASK 0x8 +#define PA_CL_VTE_CNTL__VPORT_Y_OFFSET_ENA__SHIFT 0x3 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA_MASK 0x10 +#define PA_CL_VTE_CNTL__VPORT_Z_SCALE_ENA__SHIFT 0x4 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA_MASK 0x20 +#define PA_CL_VTE_CNTL__VPORT_Z_OFFSET_ENA__SHIFT 0x5 +#define PA_CL_VTE_CNTL__VTX_XY_FMT_MASK 0x100 +#define PA_CL_VTE_CNTL__VTX_XY_FMT__SHIFT 0x8 +#define PA_CL_VTE_CNTL__VTX_Z_FMT_MASK 0x200 +#define PA_CL_VTE_CNTL__VTX_Z_FMT__SHIFT 0x9 +#define PA_CL_VTE_CNTL__VTX_W0_FMT_MASK 0x400 +#define PA_CL_VTE_CNTL__VTX_W0_FMT__SHIFT 0xa +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF_MASK 0x800 +#define PA_CL_VTE_CNTL__PERFCOUNTER_REF__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0_MASK 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_0__SHIFT 0x0 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1_MASK 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_1__SHIFT 0x1 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2_MASK 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_2__SHIFT 0x2 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3_MASK 0x8 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_3__SHIFT 0x3 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4_MASK 0x10 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_4__SHIFT 0x4 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5_MASK 0x20 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_5__SHIFT 0x5 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6_MASK 0x40 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_6__SHIFT 0x6 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7_MASK 0x80 +#define PA_CL_VS_OUT_CNTL__CLIP_DIST_ENA_7__SHIFT 0x7 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0_MASK 0x100 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_0__SHIFT 0x8 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1_MASK 0x200 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_1__SHIFT 0x9 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2_MASK 0x400 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_2__SHIFT 0xa +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3_MASK 0x800 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_3__SHIFT 0xb +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4_MASK 0x1000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_4__SHIFT 0xc +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5_MASK 0x2000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_5__SHIFT 0xd +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6_MASK 0x4000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_6__SHIFT 0xe +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7_MASK 0x8000 +#define PA_CL_VS_OUT_CNTL__CULL_DIST_ENA_7__SHIFT 0xf +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE_MASK 0x10000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_POINT_SIZE__SHIFT 0x10 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG_MASK 0x20000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_EDGE_FLAG__SHIFT 0x11 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX_MASK 0x40000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_RENDER_TARGET_INDX__SHIFT 0x12 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX_MASK 0x80000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_VIEWPORT_INDX__SHIFT 0x13 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG_MASK 0x100000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_KILL_FLAG__SHIFT 0x14 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA_MASK 0x200000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_VEC_ENA__SHIFT 0x15 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA_MASK 0x400000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST0_VEC_ENA__SHIFT 0x16 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA_MASK 0x800000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_CCDIST1_VEC_ENA__SHIFT 0x17 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA_MASK 0x1000000 +#define PA_CL_VS_OUT_CNTL__VS_OUT_MISC_SIDE_BUS_ENA__SHIFT 0x18 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG_MASK 0x2000000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_GS_CUT_FLAG__SHIFT 0x19 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH_MASK 0x4000000 +#define PA_CL_VS_OUT_CNTL__USE_VTX_LINE_WIDTH__SHIFT 0x1a +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD_MASK 0x1 +#define PA_CL_NANINF_CNTL__VTE_XY_INF_DISCARD__SHIFT 0x0 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD_MASK 0x2 +#define PA_CL_NANINF_CNTL__VTE_Z_INF_DISCARD__SHIFT 0x1 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD_MASK 0x4 +#define PA_CL_NANINF_CNTL__VTE_W_INF_DISCARD__SHIFT 0x2 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0_MASK 0x8 +#define PA_CL_NANINF_CNTL__VTE_0XNANINF_IS_0__SHIFT 0x3 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN_MASK 0x10 +#define PA_CL_NANINF_CNTL__VTE_XY_NAN_RETAIN__SHIFT 0x4 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN_MASK 0x20 +#define PA_CL_NANINF_CNTL__VTE_Z_NAN_RETAIN__SHIFT 0x5 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN_MASK 0x40 +#define PA_CL_NANINF_CNTL__VTE_W_NAN_RETAIN__SHIFT 0x6 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0_MASK 0x80 +#define PA_CL_NANINF_CNTL__VTE_W_RECIP_NAN_IS_0__SHIFT 0x7 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF_MASK 0x100 +#define PA_CL_NANINF_CNTL__VS_XY_NAN_TO_INF__SHIFT 0x8 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN_MASK 0x200 +#define PA_CL_NANINF_CNTL__VS_XY_INF_RETAIN__SHIFT 0x9 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF_MASK 0x400 +#define PA_CL_NANINF_CNTL__VS_Z_NAN_TO_INF__SHIFT 0xa +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN_MASK 0x800 +#define PA_CL_NANINF_CNTL__VS_Z_INF_RETAIN__SHIFT 0xb +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF_MASK 0x1000 +#define PA_CL_NANINF_CNTL__VS_W_NAN_TO_INF__SHIFT 0xc +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN_MASK 0x2000 +#define PA_CL_NANINF_CNTL__VS_W_INF_RETAIN__SHIFT 0xd +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD_MASK 0x4000 +#define PA_CL_NANINF_CNTL__VS_CLIP_DIST_INF_DISCARD__SHIFT 0xe +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0_MASK 0x100000 +#define PA_CL_NANINF_CNTL__VTE_NO_OUTPUT_NEG_0__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__UCP_ENA_0_MASK 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_0__SHIFT 0x0 +#define PA_CL_CLIP_CNTL__UCP_ENA_1_MASK 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_1__SHIFT 0x1 +#define PA_CL_CLIP_CNTL__UCP_ENA_2_MASK 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_2__SHIFT 0x2 +#define PA_CL_CLIP_CNTL__UCP_ENA_3_MASK 0x8 +#define PA_CL_CLIP_CNTL__UCP_ENA_3__SHIFT 0x3 +#define PA_CL_CLIP_CNTL__UCP_ENA_4_MASK 0x10 +#define PA_CL_CLIP_CNTL__UCP_ENA_4__SHIFT 0x4 +#define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 +#define PA_CL_CLIP_CNTL__UCP_ENA_5__SHIFT 0x5 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG_MASK 0x2000 +#define PA_CL_CLIP_CNTL__PS_UCP_Y_SCALE_NEG__SHIFT 0xd +#define PA_CL_CLIP_CNTL__PS_UCP_MODE_MASK 0xc000 +#define PA_CL_CLIP_CNTL__PS_UCP_MODE__SHIFT 0xe +#define PA_CL_CLIP_CNTL__CLIP_DISABLE_MASK 0x10000 +#define PA_CL_CLIP_CNTL__CLIP_DISABLE__SHIFT 0x10 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA_MASK 0x20000 +#define PA_CL_CLIP_CNTL__UCP_CULL_ONLY_ENA__SHIFT 0x11 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA_MASK 0x40000 +#define PA_CL_CLIP_CNTL__BOUNDARY_EDGE_FLAG_ENA__SHIFT 0x12 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF_MASK 0x80000 +#define PA_CL_CLIP_CNTL__DX_CLIP_SPACE_DEF__SHIFT 0x13 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT_MASK 0x100000 +#define PA_CL_CLIP_CNTL__DIS_CLIP_ERR_DETECT__SHIFT 0x14 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR_MASK 0x200000 +#define PA_CL_CLIP_CNTL__VTX_KILL_OR__SHIFT 0x15 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL_MASK 0x400000 +#define PA_CL_CLIP_CNTL__DX_RASTERIZATION_KILL__SHIFT 0x16 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA_MASK 0x1000000 +#define PA_CL_CLIP_CNTL__DX_LINEAR_ATTR_CLIP_ENA__SHIFT 0x18 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE_MASK 0x2000000 +#define PA_CL_CLIP_CNTL__VTE_VPORT_PROVOKE_DISABLE__SHIFT 0x19 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE_MASK 0x4000000 +#define PA_CL_CLIP_CNTL__ZCLIP_NEAR_DISABLE__SHIFT 0x1a +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE_MASK 0x8000000 +#define PA_CL_CLIP_CNTL__ZCLIP_FAR_DISABLE__SHIFT 0x1b +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_VERT_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_VERT_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_HORZ_CLIP_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_GB_HORZ_DISC_ADJ__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_0_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_0_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_1_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_1_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_2_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_2_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_3_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_3_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_4_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_4_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_X__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_X__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Y__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_Y__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_Z__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_Z__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_UCP_5_W__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_UCP_5_W__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_X_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_X_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_Y_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_Y_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_SIZE__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_SIZE__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER_MASK 0xffffffff +#define PA_CL_POINT_CULL_RAD__DATA_REGISTER__SHIFT 0x0 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK 0x1 +#define PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA__SHIFT 0x0 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ_MASK 0x6 +#define PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT 0x1 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL_MASK 0x8 +#define PA_CL_ENHANCE__CLIPPED_PRIM_SEQ_STALL__SHIFT 0x3 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE_MASK 0x10 +#define PA_CL_ENHANCE__VE_NAN_PROC_DISABLE__SHIFT 0x4 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL_MASK 0x20 +#define PA_CL_ENHANCE__XTRA_DEBUG_REG_SEL__SHIFT 0x5 +#define PA_CL_ENHANCE__ECO_SPARE3_MASK 0x10000000 +#define PA_CL_ENHANCE__ECO_SPARE3__SHIFT 0x1c +#define PA_CL_ENHANCE__ECO_SPARE2_MASK 0x20000000 +#define PA_CL_ENHANCE__ECO_SPARE2__SHIFT 0x1d +#define PA_CL_ENHANCE__ECO_SPARE1_MASK 0x40000000 +#define PA_CL_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_CL_ENHANCE__ECO_SPARE0_MASK 0x80000000 +#define PA_CL_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE_MASK 0x1 +#define PA_CL_RESET_DEBUG__CL_TRIV_DISC_DISABLE__SHIFT 0x0 +#define PA_SU_VTX_CNTL__PIX_CENTER_MASK 0x1 +#define PA_SU_VTX_CNTL__PIX_CENTER__SHIFT 0x0 +#define PA_SU_VTX_CNTL__ROUND_MODE_MASK 0x6 +#define PA_SU_VTX_CNTL__ROUND_MODE__SHIFT 0x1 +#define PA_SU_VTX_CNTL__QUANT_MODE_MASK 0x38 +#define PA_SU_VTX_CNTL__QUANT_MODE__SHIFT 0x3 +#define PA_SU_POINT_SIZE__HEIGHT_MASK 0xffff +#define PA_SU_POINT_SIZE__HEIGHT__SHIFT 0x0 +#define PA_SU_POINT_SIZE__WIDTH_MASK 0xffff0000 +#define PA_SU_POINT_SIZE__WIDTH__SHIFT 0x10 +#define PA_SU_POINT_MINMAX__MIN_SIZE_MASK 0xffff +#define PA_SU_POINT_MINMAX__MIN_SIZE__SHIFT 0x0 +#define PA_SU_POINT_MINMAX__MAX_SIZE_MASK 0xffff0000 +#define PA_SU_POINT_MINMAX__MAX_SIZE__SHIFT 0x10 +#define PA_SU_LINE_CNTL__WIDTH_MASK 0xffff +#define PA_SU_LINE_CNTL__WIDTH__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET_MASK 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__LINE_STIPPLE_RESET__SHIFT 0x0 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH_MASK 0x4 +#define PA_SU_LINE_STIPPLE_CNTL__EXPAND_FULL_LENGTH__SHIFT 0x2 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM_MASK 0x8 +#define PA_SU_LINE_STIPPLE_CNTL__FRACTIONAL_ACCUM__SHIFT 0x3 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST_MASK 0x10 +#define PA_SU_LINE_STIPPLE_CNTL__DIAMOND_ADJUST__SHIFT 0x4 +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE_MASK 0xffffffff +#define PA_SU_LINE_STIPPLE_SCALE__LINE_STIPPLE_SCALE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x1 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE__SHIFT 0x0 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x2 +#define PA_SU_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x1 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x4 +#define PA_SU_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x2 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x8 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x3 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA_MASK 0x10 +#define PA_SU_PRIM_FILTER_CNTL__TRIANGLE_EXPAND_ENA__SHIFT 0x4 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA_MASK 0x20 +#define PA_SU_PRIM_FILTER_CNTL__LINE_EXPAND_ENA__SHIFT 0x5 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA_MASK 0x40 +#define PA_SU_PRIM_FILTER_CNTL__POINT_EXPAND_ENA__SHIFT 0x6 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA_MASK 0x80 +#define PA_SU_PRIM_FILTER_CNTL__RECTANGLE_EXPAND_ENA__SHIFT 0x7 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT_MASK 0xff00 +#define PA_SU_PRIM_FILTER_CNTL__PRIM_EXPAND_CONSTANT__SHIFT 0x8 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION_MASK 0x40000000 +#define PA_SU_PRIM_FILTER_CNTL__XMAX_RIGHT_EXCLUSION__SHIFT 0x1e +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION_MASK 0x80000000 +#define PA_SU_PRIM_FILTER_CNTL__YMAX_BOTTOM_EXCLUSION__SHIFT 0x1f +#define PA_SU_SC_MODE_CNTL__CULL_FRONT_MASK 0x1 +#define PA_SU_SC_MODE_CNTL__CULL_FRONT__SHIFT 0x0 +#define PA_SU_SC_MODE_CNTL__CULL_BACK_MASK 0x2 +#define PA_SU_SC_MODE_CNTL__CULL_BACK__SHIFT 0x1 +#define PA_SU_SC_MODE_CNTL__FACE_MASK 0x4 +#define PA_SU_SC_MODE_CNTL__FACE__SHIFT 0x2 +#define PA_SU_SC_MODE_CNTL__POLY_MODE_MASK 0x18 +#define PA_SU_SC_MODE_CNTL__POLY_MODE__SHIFT 0x3 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE_MASK 0xe0 +#define PA_SU_SC_MODE_CNTL__POLYMODE_FRONT_PTYPE__SHIFT 0x5 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE_MASK 0x700 +#define PA_SU_SC_MODE_CNTL__POLYMODE_BACK_PTYPE__SHIFT 0x8 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE_MASK 0x800 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_FRONT_ENABLE__SHIFT 0xb +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE_MASK 0x1000 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_BACK_ENABLE__SHIFT 0xc +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE_MASK 0x2000 +#define PA_SU_SC_MODE_CNTL__POLY_OFFSET_PARA_ENABLE__SHIFT 0xd +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE_MASK 0x10000 +#define PA_SU_SC_MODE_CNTL__VTX_WINDOW_OFFSET_ENABLE__SHIFT 0x10 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST_MASK 0x80000 +#define PA_SU_SC_MODE_CNTL__PROVOKING_VTX_LAST__SHIFT 0x13 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS_MASK 0x100000 +#define PA_SU_SC_MODE_CNTL__PERSP_CORR_DIS__SHIFT 0x14 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA_MASK 0x200000 +#define PA_SU_SC_MODE_CNTL__MULTI_PRIM_IB_ENA__SHIFT 0x15 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS_MASK 0xff +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_NEG_NUM_DB_BITS__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT_MASK 0x100 +#define PA_SU_POLY_OFFSET_DB_FMT_CNTL__POLY_OFFSET_DB_IS_FLOAT_FMT__SHIFT 0x8 +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_CLAMP__CLAMP__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_FRONT_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_FRONT_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_BACK_SCALE__SCALE__SHIFT 0x0 +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET_MASK 0xffffffff +#define PA_SU_POLY_OFFSET_BACK_OFFSET__OFFSET__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X_MASK 0x1ff +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_X__SHIFT 0x0 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y_MASK 0x1ff0000 +#define PA_SU_HARDWARE_SCREEN_OFFSET__HW_SCREEN_OFFSET_Y__SHIFT 0x10 +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE_MASK 0xffffff +#define PA_SU_LINE_STIPPLE_VALUE__LINE_STIPPLE_VALUE__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SU_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SU_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SU_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SU_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SU_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SU_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffff +#define PA_SU_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES_MASK 0x7 +#define PA_SC_AA_CONFIG__MSAA_NUM_SAMPLES__SHIFT 0x0 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN_MASK 0x10 +#define PA_SC_AA_CONFIG__AA_MASK_CENTROID_DTMN__SHIFT 0x4 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST_MASK 0x1e000 +#define PA_SC_AA_CONFIG__MAX_SAMPLE_DIST__SHIFT 0xd +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES_MASK 0x700000 +#define PA_SC_AA_CONFIG__MSAA_EXPOSED_SAMPLES__SHIFT 0x14 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE_MASK 0x3000000 +#define PA_SC_AA_CONFIG__DETAIL_TO_EXPOSED_MODE__SHIFT 0x18 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0_MASK 0xffff +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X0Y0__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0_MASK 0xffff0000 +#define PA_SC_AA_MASK_X0Y0_X1Y0__AA_MASK_X1Y0__SHIFT 0x10 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1_MASK 0xffff +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X0Y1__SHIFT 0x0 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1_MASK 0xffff0000 +#define PA_SC_AA_MASK_X0Y1_X1Y1__AA_MASK_X1Y1__SHIFT 0x10 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES_MASK 0x3 +#define PA_SC_SHADER_CONTROL__REALIGN_DQUADS_AFTER_N_WAVES__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S0_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S1_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S2_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0__S3_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S4_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S5_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S6_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1__S7_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S8_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S9_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S10_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2__S11_Y__SHIFT 0x1c +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X_MASK 0xf +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_X__SHIFT 0x0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y_MASK 0xf0 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S12_Y__SHIFT 0x4 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X_MASK 0xf00 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_X__SHIFT 0x8 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y_MASK 0xf000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S13_Y__SHIFT 0xc +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X_MASK 0xf0000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_X__SHIFT 0x10 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y_MASK 0xf00000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S14_Y__SHIFT 0x14 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X_MASK 0xf000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_X__SHIFT 0x18 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y_MASK 0xf0000000 +#define PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3__S15_Y__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0_MASK 0xf +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_0__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1_MASK 0xf0 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_1__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2_MASK 0xf00 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_2__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3_MASK 0xf000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_3__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4_MASK 0xf0000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_4__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5_MASK 0xf00000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_5__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6_MASK 0xf000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_6__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7_MASK 0xf0000000 +#define PA_SC_CENTROID_PRIORITY_0__DISTANCE_7__SHIFT 0x1c +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8_MASK 0xf +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_8__SHIFT 0x0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9_MASK 0xf0 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_9__SHIFT 0x4 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10_MASK 0xf00 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_10__SHIFT 0x8 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11_MASK 0xf000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_11__SHIFT 0xc +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12_MASK 0xf0000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_12__SHIFT 0x10 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13_MASK 0xf00000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_13__SHIFT 0x14 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14_MASK 0xf000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_14__SHIFT 0x18 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15_MASK 0xf0000000 +#define PA_SC_CENTROID_PRIORITY_1__DISTANCE_15__SHIFT 0x1c +#define PA_SC_CLIPRECT_0_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_0_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_0_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_1_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_1_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_2_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_2_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_TL__TL_X_MASK 0x7fff +#define PA_SC_CLIPRECT_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_3_BR__BR_X_MASK 0x7fff +#define PA_SC_CLIPRECT_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_CLIPRECT_3_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_CLIPRECT_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_CLIPRECT_RULE__CLIP_RULE_MASK 0xffff +#define PA_SC_CLIPRECT_RULE__CLIP_RULE__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_TRI_MASK 0xf +#define PA_SC_EDGERULE__ER_TRI__SHIFT 0x0 +#define PA_SC_EDGERULE__ER_POINT_MASK 0xf0 +#define PA_SC_EDGERULE__ER_POINT__SHIFT 0x4 +#define PA_SC_EDGERULE__ER_RECT_MASK 0xf00 +#define PA_SC_EDGERULE__ER_RECT__SHIFT 0x8 +#define PA_SC_EDGERULE__ER_LINE_LR_MASK 0x3f000 +#define PA_SC_EDGERULE__ER_LINE_LR__SHIFT 0xc +#define PA_SC_EDGERULE__ER_LINE_RL_MASK 0xfc0000 +#define PA_SC_EDGERULE__ER_LINE_RL__SHIFT 0x12 +#define PA_SC_EDGERULE__ER_LINE_TB_MASK 0xf000000 +#define PA_SC_EDGERULE__ER_LINE_TB__SHIFT 0x18 +#define PA_SC_EDGERULE__ER_LINE_BT_MASK 0xf0000000 +#define PA_SC_EDGERULE__ER_LINE_BT__SHIFT 0x1c +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH_MASK 0x200 +#define PA_SC_LINE_CNTL__EXPAND_LINE_WIDTH__SHIFT 0x9 +#define PA_SC_LINE_CNTL__LAST_PIXEL_MASK 0x400 +#define PA_SC_LINE_CNTL__LAST_PIXEL__SHIFT 0xa +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA_MASK 0x800 +#define PA_SC_LINE_CNTL__PERPENDICULAR_ENDCAP_ENA__SHIFT 0xb +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA_MASK 0x1000 +#define PA_SC_LINE_CNTL__DX10_DIAMOND_TEST_ENA__SHIFT 0xc +#define PA_SC_LINE_STIPPLE__LINE_PATTERN_MASK 0xffff +#define PA_SC_LINE_STIPPLE__LINE_PATTERN__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT_MASK 0xff0000 +#define PA_SC_LINE_STIPPLE__REPEAT_COUNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER_MASK 0x10000000 +#define PA_SC_LINE_STIPPLE__PATTERN_BIT_ORDER__SHIFT 0x1c +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL_MASK 0x60000000 +#define PA_SC_LINE_STIPPLE__AUTO_RESET_CNTL__SHIFT 0x1d +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE_MASK 0x1 +#define PA_SC_MODE_CNTL_0__MSAA_ENABLE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE_MASK 0x2 +#define PA_SC_MODE_CNTL_0__VPORT_SCISSOR_ENABLE__SHIFT 0x1 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE_MASK 0x4 +#define PA_SC_MODE_CNTL_0__LINE_STIPPLE_ENABLE__SHIFT 0x2 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR_MASK 0x8 +#define PA_SC_MODE_CNTL_0__SEND_UNLIT_STILES_TO_PKR__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_SIZE_MASK 0x1 +#define PA_SC_MODE_CNTL_1__WALK_SIZE__SHIFT 0x0 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT_MASK 0x2 +#define PA_SC_MODE_CNTL_1__WALK_ALIGNMENT__SHIFT 0x1 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST_MASK 0x4 +#define PA_SC_MODE_CNTL_1__WALK_ALIGN8_PRIM_FITS_ST__SHIFT 0x2 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE_MASK 0x8 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_ENABLE__SHIFT 0x3 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE_MASK 0x70 +#define PA_SC_MODE_CNTL_1__WALK_FENCE_SIZE__SHIFT 0x4 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE_MASK 0x80 +#define PA_SC_MODE_CNTL_1__SUPERTILE_WALK_ORDER_ENABLE__SHIFT 0x7 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE_MASK 0x100 +#define PA_SC_MODE_CNTL_1__TILE_WALK_ORDER_ENABLE__SHIFT 0x8 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE_MASK 0x200 +#define PA_SC_MODE_CNTL_1__TILE_COVER_DISABLE__SHIFT 0x9 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR_MASK 0x400 +#define PA_SC_MODE_CNTL_1__TILE_COVER_NO_SCISSOR__SHIFT 0xa +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT_MASK 0x800 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_EXTENT__SHIFT 0xb +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET_MASK 0x1000 +#define PA_SC_MODE_CNTL_1__ZMM_LINE_OFFSET__SHIFT 0xc +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT_MASK 0x2000 +#define PA_SC_MODE_CNTL_1__ZMM_RECT_EXTENT__SHIFT 0xd +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z_MASK 0x4000 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_HI_Z__SHIFT 0xe +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK_MASK 0x8000 +#define PA_SC_MODE_CNTL_1__KILL_PIX_POST_DETAIL_MASK__SHIFT 0xf +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE_MASK 0x10000 +#define PA_SC_MODE_CNTL_1__PS_ITER_SAMPLE__SHIFT 0x10 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE_MASK 0x20000 +#define PA_SC_MODE_CNTL_1__MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE__SHIFT 0x11 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE_MASK 0x40000 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_SUPERTILE_ENABLE__SHIFT 0x12 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE_MASK 0x80000 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_ENABLE__SHIFT 0x13 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE_MASK 0xf00000 +#define PA_SC_MODE_CNTL_1__GPU_ID_OVERRIDE__SHIFT 0x14 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE_MASK 0x1000000 +#define PA_SC_MODE_CNTL_1__MULTI_GPU_PRIM_DISCARD_ENABLE__SHIFT 0x18 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE_MASK 0x2000000 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_CNTDWN_ENABLE__SHIFT 0x19 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE_MASK 0x4000000 +#define PA_SC_MODE_CNTL_1__FORCE_EOV_REZ_ENABLE__SHIFT 0x1a +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE_MASK 0x8000000 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_PRIMITIVE_ENABLE__SHIFT 0x1b +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK_MASK 0x70000000 +#define PA_SC_MODE_CNTL_1__OUT_OF_ORDER_WATER_MARK__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK 0x3 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK 0xc +#define PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG__RB_XSEL2_MASK 0x30 +#define PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT 0x4 +#define PA_SC_RASTER_CONFIG__RB_XSEL_MASK 0x40 +#define PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT 0x6 +#define PA_SC_RASTER_CONFIG__RB_YSEL_MASK 0x80 +#define PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT 0x7 +#define PA_SC_RASTER_CONFIG__PKR_MAP_MASK 0x300 +#define PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT 0x8 +#define PA_SC_RASTER_CONFIG__PKR_XSEL_MASK 0xc00 +#define PA_SC_RASTER_CONFIG__PKR_XSEL__SHIFT 0xa +#define PA_SC_RASTER_CONFIG__PKR_YSEL_MASK 0x3000 +#define PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT 0xc +#define PA_SC_RASTER_CONFIG__PKR_XSEL2_MASK 0xc000 +#define PA_SC_RASTER_CONFIG__PKR_XSEL2__SHIFT 0xe +#define PA_SC_RASTER_CONFIG__SC_MAP_MASK 0x30000 +#define PA_SC_RASTER_CONFIG__SC_MAP__SHIFT 0x10 +#define PA_SC_RASTER_CONFIG__SC_XSEL_MASK 0xc0000 +#define PA_SC_RASTER_CONFIG__SC_XSEL__SHIFT 0x12 +#define PA_SC_RASTER_CONFIG__SC_YSEL_MASK 0x300000 +#define PA_SC_RASTER_CONFIG__SC_YSEL__SHIFT 0x14 +#define PA_SC_RASTER_CONFIG__SE_MAP_MASK 0x3000000 +#define PA_SC_RASTER_CONFIG__SE_MAP__SHIFT 0x18 +#define PA_SC_RASTER_CONFIG__SE_XSEL_MASK 0xc000000 +#define PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT 0x1a +#define PA_SC_RASTER_CONFIG__SE_YSEL_MASK 0x30000000 +#define PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT 0x1c +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP_MASK 0x3 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_MAP__SHIFT 0x0 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL_MASK 0xc +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_XSEL__SHIFT 0x2 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL_MASK 0x30 +#define PA_SC_RASTER_CONFIG_1__SE_PAIR_YSEL__SHIFT 0x4 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE_MASK 0x3 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_EVEN_ENABLE__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE_MASK 0xc +#define PA_SC_SCREEN_EXTENT_CONTROL__SLICE_ODD_ENABLE__SHIFT 0x2 +#define PA_SC_GENERIC_SCISSOR_TL__TL_X_MASK 0x7fff +#define PA_SC_GENERIC_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_GENERIC_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_GENERIC_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_GENERIC_SCISSOR_BR__BR_X_MASK 0x7fff +#define PA_SC_GENERIC_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_GENERIC_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_TL__TL_X_MASK 0xffff +#define PA_SC_SCREEN_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y_MASK 0xffff0000 +#define PA_SC_SCREEN_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_SCREEN_SCISSOR_BR__BR_X_MASK 0xffff +#define PA_SC_SCREEN_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y_MASK 0xffff0000 +#define PA_SC_SCREEN_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET_MASK 0xffff +#define PA_SC_WINDOW_OFFSET__WINDOW_X_OFFSET__SHIFT 0x0 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET_MASK 0xffff0000 +#define PA_SC_WINDOW_OFFSET__WINDOW_Y_OFFSET__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__TL_X_MASK 0x7fff +#define PA_SC_WINDOW_SCISSOR_TL__TL_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_WINDOW_SCISSOR_TL__TL_Y__SHIFT 0x10 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_WINDOW_SCISSOR_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_WINDOW_SCISSOR_BR__BR_X_MASK 0x7fff +#define PA_SC_WINDOW_SCISSOR_BR__BR_X__SHIFT 0x0 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_WINDOW_SCISSOR_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_0_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_0_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_0_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_1_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_1_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_1_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_2_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_2_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_2_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_3_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_3_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_3_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_4_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_4_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_4_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_5_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_5_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_5_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_6_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_6_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_6_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_7_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_7_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_7_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_8_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_8_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_8_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_9_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_9_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_9_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_10_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_10_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_10_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_11_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_11_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_11_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_12_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_12_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_12_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_13_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_13_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_13_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_14_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_14_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_14_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_15_TL__TL_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_15_TL__TL_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE_MASK 0x80000000 +#define PA_SC_VPORT_SCISSOR_15_TL__WINDOW_OFFSET_DISABLE__SHIFT 0x1f +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_0_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_0_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_1_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_1_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_2_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_2_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_3_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_3_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_4_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_4_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_5_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_5_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_6_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_6_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_7_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_7_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_8_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_8_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_9_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_9_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_10_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_10_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_11_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_11_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_12_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_12_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_13_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_13_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_14_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_14_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X_MASK 0x7fff +#define PA_SC_VPORT_SCISSOR_15_BR__BR_X__SHIFT 0x0 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y_MASK 0x7fff0000 +#define PA_SC_VPORT_SCISSOR_15_BR__BR_Y__SHIFT 0x10 +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_0__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_1__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_2__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_3__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_4__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_5__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_6__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_7__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_8__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_9__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_10__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_11__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_12__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_13__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_14__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN_MASK 0xffffffff +#define PA_SC_VPORT_ZMIN_15__VPORT_ZMIN__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_0__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_1__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_2__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_3__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_4__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_5__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_6__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_7__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_8__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_9__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_10__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_11__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_12__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_13__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_14__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX_MASK 0xffffffff +#define PA_SC_VPORT_ZMAX_15__VPORT_ZMAX__SHIFT 0x0 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER_MASK 0x1 +#define PA_SC_ENHANCE__ENABLE_PA_SC_OUT_OF_ORDER__SHIFT 0x0 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX_MASK 0x2 +#define PA_SC_ENHANCE__DISABLE_SC_DB_TILE_FIX__SHIFT 0x1 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX_MASK 0x4 +#define PA_SC_ENHANCE__DISABLE_AA_MASK_FULL_FIX__SHIFT 0x2 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS_MASK 0x8 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOCATIONS__SHIFT 0x3 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID_MASK 0x10 +#define PA_SC_ENHANCE__ENABLE_1XMSAA_SAMPLE_LOC_CENTROID__SHIFT 0x4 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX_MASK 0x20 +#define PA_SC_ENHANCE__DISABLE_SCISSOR_FIX__SHIFT 0x5 +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE_MASK 0xc0 +#define PA_SC_ENHANCE__DISABLE_PW_BUBBLE_COLLAPSE__SHIFT 0x6 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER_MASK 0x100 +#define PA_SC_ENHANCE__SEND_UNLIT_STILES_TO_PACKER__SHIFT 0x8 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION_MASK 0x200 +#define PA_SC_ENHANCE__DISABLE_DUALGRAD_PERF_OPTIMIZATION__SHIFT 0x9 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM_MASK 0x400 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_PRIM__SHIFT 0xa +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE_MASK 0x800 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_SUPERTILE__SHIFT 0xb +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 +#define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE__SHIFT 0xc +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE_MASK 0x2000 +#define PA_SC_ENHANCE__DISABLE_PA_SC_GUIDANCE__SHIFT 0xd +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS_MASK 0x4000 +#define PA_SC_ENHANCE__DISABLE_EOV_ALL_CTRL_ONLY_COMBINATIONS__SHIFT 0xe +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE_MASK 0x8000 +#define PA_SC_ENHANCE__ENABLE_MULTICYCLE_BUBBLE_FREEZE__SHIFT 0xf +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE_MASK 0x10000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_PA_SC_GUIDANCE__SHIFT 0x10 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE_MASK 0x20000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_POLY_MODE__SHIFT 0x11 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST_MASK 0x40000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EOP_SYNC_NULL_PRIMS_LAST__SHIFT 0x12 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING_MASK 0x80000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_THRESHOLD_SWITCHING__SHIFT 0x13 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY_MASK 0x100000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_THRESHOLD_SWITCH_AT_EOPG_ONLY__SHIFT 0x14 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING_MASK 0x200000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_DESIRED_FIFO_EMPTY_SWITCHING__SHIFT 0x15 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING_MASK 0x400000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_SELECTED_FIFO_EMPTY_SWITCHING__SHIFT 0x16 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS_MASK 0x800000 +#define PA_SC_ENHANCE__DISABLE_OUT_OF_ORDER_EMPTY_SWITCHING_HYSTERYSIS__SHIFT 0x17 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID_MASK 0x1000000 +#define PA_SC_ENHANCE__ENABLE_OUT_OF_ORDER_DESIRED_FIFO_IS_NEXT_FEID__SHIFT 0x18 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO_MASK 0x2000000 +#define PA_SC_ENHANCE__DISABLE_OOO_NO_EOPG_SKEW_DESIRED_FIFO_IS_CURRENT_FIFO__SHIFT 0x19 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT_MASK 0x4000000 +#define PA_SC_ENHANCE__OOO_DISABLE_EOP_ON_FIRST_LIVE_PRIM_HIT__SHIFT 0x1a +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING_MASK 0x8000000 +#define PA_SC_ENHANCE__OOO_DISABLE_EOPG_SKEW_THRESHOLD_SWITCHING__SHIFT 0x1b +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET_MASK 0x10000000 +#define PA_SC_ENHANCE__DISABLE_EOP_LINE_STIPPLE_RESET__SHIFT 0x1c +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET_MASK 0x20000000 +#define PA_SC_ENHANCE__DISABLE_VPZ_EOP_LINE_STIPPLE_RESET__SHIFT 0x1d +#define PA_SC_ENHANCE__ECO_SPARE1_MASK 0x40000000 +#define PA_SC_ENHANCE__ECO_SPARE1__SHIFT 0x1e +#define PA_SC_ENHANCE__ECO_SPARE0_MASK 0x80000000 +#define PA_SC_ENHANCE__ECO_SPARE0__SHIFT 0x1f +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE_MASK 0x1 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_ENABLE__SHIFT 0x0 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE_MASK 0x6 +#define PA_SC_ENHANCE_1__REALIGN_DQUADS_OVERRIDE__SHIFT 0x1 +#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING_MASK 0x8 +#define PA_SC_ENHANCE_1__ENABLE_SC_BINNING__SHIFT 0x3 +#define PA_SC_ENHANCE_1__ECO_SPARE0_MASK 0x10 +#define PA_SC_ENHANCE_1__ECO_SPARE0__SHIFT 0x4 +#define PA_SC_ENHANCE_1__ECO_SPARE1_MASK 0x20 +#define PA_SC_ENHANCE_1__ECO_SPARE1__SHIFT 0x5 +#define PA_SC_ENHANCE_1__ECO_SPARE2_MASK 0x40 +#define PA_SC_ENHANCE_1__ECO_SPARE2__SHIFT 0x6 +#define PA_SC_ENHANCE_1__ECO_SPARE3_MASK 0x80 +#define PA_SC_ENHANCE_1__ECO_SPARE3__SHIFT 0x7 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0_MASK 0x1 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_0__SHIFT 0x0 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1_MASK 0x2 +#define PA_SC_DSM_CNTL__FORCE_EOV_REZ_1__SHIFT 0x1 +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE_MASK 0x3f +#define PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE_MASK 0x7fc0 +#define PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE_MASK 0x1f8000 +#define PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT 0xf +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE_MASK 0xff800000 +#define PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT 0x17 +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE_MASK 0x3f +#define PA_SC_IF_FIFO_SIZE__SC_DB_TILE_IF_FIFO_SIZE__SHIFT 0x0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE_MASK 0xfc0 +#define PA_SC_IF_FIFO_SIZE__SC_DB_QUAD_IF_FIFO_SIZE__SHIFT 0x6 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE_MASK 0x3f000 +#define PA_SC_IF_FIFO_SIZE__SC_SPI_IF_FIFO_SIZE__SHIFT 0xc +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE_MASK 0xfc0000 +#define PA_SC_IF_FIFO_SIZE__SC_BCI_IF_FIFO_SIZE__SHIFT 0x12 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT_MASK 0xffff +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT 0x0 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT_MASK 0xffff0000 +#define PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT 0x10 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR_MASK 0xf +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_PTR__SHIFT 0x0 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT_MASK 0xff00 +#define PA_SC_LINE_STIPPLE_STATE__CURRENT_COUNT__SHIFT 0x8 +#define PA_SC_SCREEN_EXTENT_MIN_0__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MIN_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MIN_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_0__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MAX_0__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MAX_0__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MIN_1__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MIN_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MIN_1__Y__SHIFT 0x10 +#define PA_SC_SCREEN_EXTENT_MAX_1__X_MASK 0xffff +#define PA_SC_SCREEN_EXTENT_MAX_1__X__SHIFT 0x0 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y_MASK 0xffff0000 +#define PA_SC_SCREEN_EXTENT_MAX_1__Y__SHIFT 0x10 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define PA_SC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define PA_SC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define PA_SC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x3ff +#define PA_SC_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define PA_SC_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define PA_SC_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_P3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_P3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_P3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_P3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_P3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_HP3D_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_HP3D_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_HP3D_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_HP3D_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_HP3D_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER_MASK 0x1 +#define PA_SC_TRAP_SCREEN_HV_EN__ENABLE_HV_PRE_SHADER__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS_MASK 0x2 +#define PA_SC_TRAP_SCREEN_HV_EN__FORCE_PRE_SHADER_ALL_PIXELS__SHIFT 0x1 +#define PA_SC_TRAP_SCREEN_H__X_COORD_MASK 0x3fff +#define PA_SC_TRAP_SCREEN_H__X_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_V__Y_COORD_MASK 0x3fff +#define PA_SC_TRAP_SCREEN_V__Y_COORD__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT_MASK 0xffff +#define PA_SC_TRAP_SCREEN_OCCURRENCE__COUNT__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_COUNT__COUNT_MASK 0xffff +#define PA_SC_TRAP_SCREEN_COUNT__COUNT__SHIFT 0x0 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_P3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_HP3D_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES_MASK 0x1 +#define PA_SC_TRAP_SCREEN_HV_LOCK__DISABLE_NON_PRIV_WRITES__SHIFT 0x0 +#define PA_CL_CNTL_STATUS__CL_BUSY_MASK 0x80000000 +#define PA_CL_CNTL_STATUS__CL_BUSY__SHIFT 0x1f +#define PA_SU_CNTL_STATUS__SU_BUSY_MASK 0x80000000 +#define PA_SU_CNTL_STATUS__SU_BUSY__SHIFT 0x1f +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH_MASK 0x3ff +#define PA_SC_FIFO_DEPTH_CNTL__DEPTH__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_PA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_PA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_PA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE_MASK 0x20000000 +#define CGTT_PA_CLK_CTRL__SU_CLK_OVERRIDE__SHIFT 0x1d +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE_MASK 0x40000000 +#define CGTT_PA_CLK_CTRL__CL_CLK_OVERRIDE__SHIFT 0x1e +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE_MASK 0x80000000 +#define CGTT_PA_CLK_CTRL__REG_CLK_OVERRIDE__SHIFT 0x1f +#define CGTT_SC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SC_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX_MASK 0x1f +#define PA_SU_DEBUG_CNTL__SU_DEBUG_INDX__SHIFT 0x0 +#define PA_SU_DEBUG_DATA__DATA_MASK 0xffffffff +#define PA_SU_DEBUG_DATA__DATA__SHIFT 0x0 +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX_MASK 0x3f +#define PA_SC_DEBUG_CNTL__SC_DEBUG_INDX__SHIFT 0x0 +#define PA_SC_DEBUG_DATA__DATA_MASK 0xffffffff +#define PA_SC_DEBUG_DATA__DATA__SHIFT 0x0 +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG00__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write_MASK 0x100 +#define CLIPPER_DEBUG_REG00__clip_ga_bc_fifo_write__SHIFT 0x8 +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free_MASK 0x600 +#define CLIPPER_DEBUG_REG00__su_clip_baryc_free__SHIFT 0x9 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write_MASK 0x800 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_write__SHIFT 0xb +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full_MASK 0x1000 +#define CLIPPER_DEBUG_REG00__clip_to_ga_fifo_full__SHIFT 0xc +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty_MASK 0x2000 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_empty__SHIFT 0xd +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full_MASK 0x4000 +#define CLIPPER_DEBUG_REG00__primic_to_clprim_fifo_full__SHIFT 0xe +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty_MASK 0x8000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_empty__SHIFT 0xf +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full_MASK 0x10000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_full__SHIFT 0x10 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty_MASK 0x20000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_empty__SHIFT 0x11 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full_MASK 0x40000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_full__SHIFT 0x12 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty_MASK 0x80000 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_empty__SHIFT 0x13 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full_MASK 0x100000 +#define CLIPPER_DEBUG_REG00__vgt_to_clips_fifo_full__SHIFT 0x14 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty_MASK 0x200000 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_fifo_empty__SHIFT 0x15 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full_MASK 0x400000 +#define CLIPPER_DEBUG_REG00__clipcode_fifo_full__SHIFT 0x16 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty_MASK 0x800000 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_empty__SHIFT 0x17 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full_MASK 0x1000000 +#define CLIPPER_DEBUG_REG00__vte_out_clip_fifo_fifo_full__SHIFT 0x18 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty_MASK 0x2000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_empty__SHIFT 0x19 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full_MASK 0x4000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_full__SHIFT 0x1a +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty_MASK 0x8000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_empty__SHIFT 0x1b +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG00__ccgen_to_clipcc_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG00__clip_to_outsm_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write_MASK 0x40000000 +#define CLIPPER_DEBUG_REG00__vte_out_orig_fifo_fifo_write__SHIFT 0x1e +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write_MASK 0x80000000 +#define CLIPPER_DEBUG_REG00__vgt_to_clipp_fifo_write__SHIFT 0x1f +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG01__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid_MASK 0x700 +#define CLIPPER_DEBUG_REG01__clip_extra_bc_valid__SHIFT 0x8 +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid_MASK 0x3800 +#define CLIPPER_DEBUG_REG01__clip_vert_vte_valid__SHIFT 0xb +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate_MASK 0x1c000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_vertex_deallocate__SHIFT 0xe +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot_MASK 0xe0000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_deallocate_slot__SHIFT 0x11 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive_MASK 0x100000 +#define CLIPPER_DEBUG_REG01__clip_to_outsm_null_primitive__SHIFT 0x14 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2_MASK 0x200000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_2__SHIFT 0x15 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1_MASK 0x400000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_1__SHIFT 0x16 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0_MASK 0x800000 +#define CLIPPER_DEBUG_REG01__vte_positions_vte_clip_vte_naninf_kill_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid_MASK 0x1000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_extra_bc_valid__SHIFT 0x18 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill_MASK 0x2000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vte_naninf_kill__SHIFT 0x19 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx_MASK 0xc000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_rd_vertex_store_indx__SHIFT 0x1a +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write_MASK 0x10000000 +#define CLIPPER_DEBUG_REG01__clip_ga_bc_fifo_write__SHIFT 0x1c +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG01__clip_to_ga_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty_MASK 0x80000000 +#define CLIPPER_DEBUG_REG01__vte_out_clip_fifo_fifo_empty__SHIFT 0x1f +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid_MASK 0x7 +#define CLIPPER_DEBUG_REG02__clip_extra_bc_valid__SHIFT 0x0 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid_MASK 0x38 +#define CLIPPER_DEBUG_REG02__clip_vert_vte_valid__SHIFT 0x3 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx_MASK 0xc0 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clip_seq_indx__SHIFT 0x6 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2_MASK 0xf00 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_2__SHIFT 0x8 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1_MASK 0xf000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_1__SHIFT 0xc +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0_MASK 0xf0000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_vertex_store_indx_0__SHIFT 0x10 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords_MASK 0x100000 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_extra_bc_coords__SHIFT 0x14 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill_MASK 0x200000 +#define CLIPPER_DEBUG_REG02__clip_to_clipga_vte_naninf_kill__SHIFT 0x15 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet_MASK 0x400000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_end_of_packet__SHIFT 0x16 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot_MASK 0x800000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_first_prim_of_slot__SHIFT 0x17 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim_MASK 0x1000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_clipped_prim__SHIFT 0x18 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive_MASK 0x2000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_null_primitive__SHIFT 0x19 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full_MASK 0x4000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_full__SHIFT 0x1a +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full_MASK 0x8000000 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_full__SHIFT 0x1b +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write_MASK 0x10000000 +#define CLIPPER_DEBUG_REG02__clip_ga_bc_fifo_write__SHIFT 0x1c +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write_MASK 0x20000000 +#define CLIPPER_DEBUG_REG02__clip_to_ga_fifo_write__SHIFT 0x1d +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty_MASK 0x80000000 +#define CLIPPER_DEBUG_REG02__clip_to_outsm_fifo_empty__SHIFT 0x1f +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG03__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG04__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG05__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG06__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG07__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG08__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or_MASK 0x3fff +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_code_or__SHIFT 0x0 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id_MASK 0xfc000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_id__SHIFT 0xe +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx_MASK 0x700000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_state_var_indx__SHIFT 0x14 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive_MASK 0x800000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x17 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot_MASK 0x7000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_deallocate_slot__SHIFT 0x18 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot_MASK 0x8000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_first_prim_of_slot__SHIFT 0x1b +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet_MASK 0x10000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_end_of_packet__SHIFT 0x1c +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG09__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0_MASK 0x7fe +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_param_cache_indx_0__SHIFT 0x1 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2_MASK 0x1f800 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_2__SHIFT 0xb +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1_MASK 0x7e0000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_1__SHIFT 0x11 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0_MASK 0x1f800000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_vertex_store_indx_0__SHIFT 0x17 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event_MASK 0x20000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_event__SHIFT 0x1d +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_null_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG10__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event_MASK 0x1 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_event__SHIFT 0x0 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event_MASK 0x2 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_event__SHIFT 0x1 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event_MASK 0x4 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_event__SHIFT 0x2 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event_MASK 0x8 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_event__SHIFT 0x3 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive_MASK 0x10 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_primitive__SHIFT 0x4 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive_MASK 0x20 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_primitive__SHIFT 0x5 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive_MASK 0x40 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_primitive__SHIFT 0x6 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive_MASK 0x80 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_primitive__SHIFT 0x7 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf000 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0xc +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf0000 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x10 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt_MASK 0xf00000 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x14 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid_MASK 0x1000000 +#define CLIPPER_DEBUG_REG11__clipsm3_clip_to_clipga_prim_valid__SHIFT 0x18 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid_MASK 0x2000000 +#define CLIPPER_DEBUG_REG11__clipsm2_clip_to_clipga_prim_valid__SHIFT 0x19 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid_MASK 0x4000000 +#define CLIPPER_DEBUG_REG11__clipsm1_clip_to_clipga_prim_valid__SHIFT 0x1a +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid_MASK 0x8000000 +#define CLIPPER_DEBUG_REG11__clipsm0_clip_to_clipga_prim_valid__SHIFT 0x1b +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x10000000 +#define CLIPPER_DEBUG_REG11__clipsm3_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1c +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x20000000 +#define CLIPPER_DEBUG_REG11__clipsm2_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1d +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x40000000 +#define CLIPPER_DEBUG_REG11__clipsm1_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1e +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt_MASK 0x80000000 +#define CLIPPER_DEBUG_REG11__clipsm0_inc_clip_to_clipga_clip_to_outsm_cnt__SHIFT 0x1f +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO_MASK 0xff +#define CLIPPER_DEBUG_REG12__ALWAYS_ZERO__SHIFT 0x0 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip_MASK 0x1f00 +#define CLIPPER_DEBUG_REG12__clip_priority_available_vte_out_clip__SHIFT 0x8 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts_MASK 0x3e000 +#define CLIPPER_DEBUG_REG12__clip_priority_available_clip_verts__SHIFT 0xd +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out_MASK 0xc0000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_out__SHIFT 0x12 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert_MASK 0x300000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_vert__SHIFT 0x14 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load_MASK 0xc00000 +#define CLIPPER_DEBUG_REG12__clip_priority_seq_indx_load__SHIFT 0x16 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive_MASK 0x1000000 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_clip_primitive__SHIFT 0x18 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid_MASK 0x2000000 +#define CLIPPER_DEBUG_REG12__clipsm3_clprim_to_clip_prim_valid__SHIFT 0x19 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive_MASK 0x4000000 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_clip_primitive__SHIFT 0x1a +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid_MASK 0x8000000 +#define CLIPPER_DEBUG_REG12__clipsm2_clprim_to_clip_prim_valid__SHIFT 0x1b +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive_MASK 0x10000000 +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_clip_primitive__SHIFT 0x1c +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid_MASK 0x20000000 +#define CLIPPER_DEBUG_REG12__clipsm1_clprim_to_clip_prim_valid__SHIFT 0x1d +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive_MASK 0x40000000 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_clip_primitive__SHIFT 0x1e +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG12__clipsm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx_MASK 0x7 +#define CLIPPER_DEBUG_REG13__clprim_in_back_state_var_indx__SHIFT 0x0 +#define CLIPPER_DEBUG_REG13__point_clip_candidate_MASK 0x8 +#define CLIPPER_DEBUG_REG13__point_clip_candidate__SHIFT 0x3 +#define CLIPPER_DEBUG_REG13__prim_nan_kill_MASK 0x10 +#define CLIPPER_DEBUG_REG13__prim_nan_kill__SHIFT 0x4 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive_MASK 0x20 +#define CLIPPER_DEBUG_REG13__clprim_clip_primitive__SHIFT 0x5 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive_MASK 0x40 +#define CLIPPER_DEBUG_REG13__clprim_cull_primitive__SHIFT 0x6 +#define CLIPPER_DEBUG_REG13__prim_back_valid_MASK 0x80 +#define CLIPPER_DEBUG_REG13__prim_back_valid__SHIFT 0x7 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid_MASK 0xf00 +#define CLIPPER_DEBUG_REG13__vertval_bits_vertex_cc_next_valid__SHIFT 0x8 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx_MASK 0x3000 +#define CLIPPER_DEBUG_REG13__clipcc_vertex_store_indx__SHIFT 0xc +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty_MASK 0x4000 +#define CLIPPER_DEBUG_REG13__vte_out_orig_fifo_fifo_empty__SHIFT 0xe +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty_MASK 0x8000 +#define CLIPPER_DEBUG_REG13__clipcode_fifo_fifo_empty__SHIFT 0xf +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty_MASK 0x10000 +#define CLIPPER_DEBUG_REG13__ccgen_to_clipcc_fifo_empty__SHIFT 0x10 +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt_MASK 0x1e0000 +#define CLIPPER_DEBUG_REG13__clip_priority_seq_indx_out_cnt__SHIFT 0x11 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices_MASK 0x600000 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_orig_vertices__SHIFT 0x15 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait_MASK 0x800000 +#define CLIPPER_DEBUG_REG13__outsm_clr_rd_clipsm_wait__SHIFT 0x17 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents_MASK 0x1f000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_contents__SHIFT 0x18 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full_MASK 0x20000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_full__SHIFT 0x1d +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread_MASK 0x40000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_advanceread__SHIFT 0x1e +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write_MASK 0x80000000 +#define CLIPPER_DEBUG_REG13__outsm_clr_fifo_write__SHIFT 0x1f +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2_MASK 0x3f +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_2__SHIFT 0x0 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1_MASK 0xfc0 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_1__SHIFT 0x6 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0_MASK 0x3f000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_vertex_store_indx_0__SHIFT 0xc +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive_MASK 0x40000 +#define CLIPPER_DEBUG_REG14__outputclprimtoclip_null_primitive__SHIFT 0x12 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet_MASK 0x80000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_end_of_packet__SHIFT 0x13 +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot_MASK 0x100000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_first_prim_of_slot__SHIFT 0x14 +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot_MASK 0xe00000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_deallocate_slot__SHIFT 0x15 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id_MASK 0x3f000000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_id__SHIFT 0x18 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event_MASK 0x40000000 +#define CLIPPER_DEBUG_REG14__clprim_in_back_event__SHIFT 0x1e +#define CLIPPER_DEBUG_REG14__prim_back_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG14__prim_back_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb_MASK 0xffff +#define CLIPPER_DEBUG_REG15__vertval_bits_vertex_vertex_store_msb__SHIFT 0x0 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2_MASK 0x1f0000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_2__SHIFT 0x10 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1_MASK 0x3e00000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_1__SHIFT 0x15 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0_MASK 0x7c000000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_fifo_vertex_store_indx_0__SHIFT 0x1a +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG15__primic_to_clprim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG16__sm0_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG16__sm0_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG16__sm0_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG16__sm0_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG16__sm0_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG16__sm0_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG16__sm0_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG16__sm0_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG16__sm0_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG16__sm0_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG16__sm0_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG17__sm1_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG17__sm1_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG17__sm1_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG17__sm1_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG17__sm1_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG17__sm1_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG17__sm1_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG17__sm1_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG17__sm1_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG17__sm1_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG17__sm1_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG18__sm2_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG18__sm2_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG18__sm2_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG18__sm2_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG18__sm2_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG18__sm2_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG18__sm2_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG18__sm2_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG18__sm2_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG18__sm2_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG18__sm2_clprim_to_clip_prim_valid__SHIFT 0x1f +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state_MASK 0x7f +#define CLIPPER_DEBUG_REG19__sm3_prim_end_state__SHIFT 0x0 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand_MASK 0x80 +#define CLIPPER_DEBUG_REG19__sm3_ps_expand__SHIFT 0x7 +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt_MASK 0x1f00 +#define CLIPPER_DEBUG_REG19__sm3_clip_vert_cnt__SHIFT 0x8 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt_MASK 0x3e000 +#define CLIPPER_DEBUG_REG19__sm3_vertex_clip_cnt__SHIFT 0xd +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1_MASK 0x40000 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_1__SHIFT 0x12 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0_MASK 0x80000 +#define CLIPPER_DEBUG_REG19__sm3_inv_to_clip_data_valid_0__SHIFT 0x13 +#define CLIPPER_DEBUG_REG19__sm3_current_state_MASK 0x7f00000 +#define CLIPPER_DEBUG_REG19__sm3_current_state__SHIFT 0x14 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0_MASK 0x8000000 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_clipga_clip_to_outsm_cnt_eq0__SHIFT 0x1b +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full_MASK 0x10000000 +#define CLIPPER_DEBUG_REG19__sm3_clip_to_outsm_fifo_full__SHIFT 0x1c +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq_MASK 0x20000000 +#define CLIPPER_DEBUG_REG19__sm3_highest_priority_seq__SHIFT 0x1d +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0_MASK 0x40000000 +#define CLIPPER_DEBUG_REG19__sm3_outputcliptoclipga_0__SHIFT 0x1e +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid_MASK 0x80000000 +#define CLIPPER_DEBUG_REG19__sm3_clprim_to_clip_prim_valid__SHIFT 0x1f +#define SXIFCCG_DEBUG_REG0__position_address_MASK 0x3f +#define SXIFCCG_DEBUG_REG0__position_address__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG0__point_address_MASK 0x1c0 +#define SXIFCCG_DEBUG_REG0__point_address__SHIFT 0x6 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx_MASK 0xe00 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_state_var_indx__SHIFT 0x9 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask_MASK 0xf000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_req_mask__SHIFT 0xc +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci_MASK 0x3ff0000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_pci__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel_MASK 0xc000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_sel__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id_MASK 0x30000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_sp_id__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_aux_inc__SHIFT 0x1e +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance_MASK 0x80000000 +#define SXIFCCG_DEBUG_REG0__sx_pending_rd_advance__SHIFT 0x1f +#define SXIFCCG_DEBUG_REG1__available_positions_MASK 0x7f +#define SXIFCCG_DEBUG_REG1__available_positions__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG1__sx_receive_indx_MASK 0x380 +#define SXIFCCG_DEBUG_REG1__sx_receive_indx__SHIFT 0x7 +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents_MASK 0x7c00 +#define SXIFCCG_DEBUG_REG1__sx_pending_fifo_contents__SHIFT 0xa +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena_MASK 0x8000 +#define SXIFCCG_DEBUG_REG1__statevar_bits_vs_out_misc_vec_ena__SHIFT 0xf +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp_MASK 0xf0000 +#define SXIFCCG_DEBUG_REG1__statevar_bits_disable_sp__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG1__aux_sel_MASK 0x300000 +#define SXIFCCG_DEBUG_REG1__aux_sel__SHIFT 0x14 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1_MASK 0x400000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_1__SHIFT 0x16 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0_MASK 0x800000 +#define SXIFCCG_DEBUG_REG1__sx_to_pa_empty_0__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1_MASK 0xf000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_1__SHIFT 0x18 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0_MASK 0xf0000000 +#define SXIFCCG_DEBUG_REG1__pasx_req_cnt_0__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG2__param_cache_base_MASK 0x7f +#define SXIFCCG_DEBUG_REG2__param_cache_base__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG2__sx_aux_MASK 0x180 +#define SXIFCCG_DEBUG_REG2__sx_aux__SHIFT 0x7 +#define SXIFCCG_DEBUG_REG2__sx_request_indx_MASK 0x7e00 +#define SXIFCCG_DEBUG_REG2__sx_request_indx__SHIFT 0x9 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded_MASK 0x8000 +#define SXIFCCG_DEBUG_REG2__req_active_verts_loaded__SHIFT 0xf +#define SXIFCCG_DEBUG_REG2__req_active_verts_MASK 0x7f0000 +#define SXIFCCG_DEBUG_REG2__req_active_verts__SHIFT 0x10 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx_MASK 0x3800000 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_state_var_indx__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts_MASK 0xfc000000 +#define SXIFCCG_DEBUG_REG2__vgt_to_ccgen_active_verts__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO_MASK 0xff +#define SXIFCCG_DEBUG_REG3__ALWAYS_ZERO__SHIFT 0x0 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable_MASK 0xf00 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_entriesavailable__SHIFT 0x8 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena_MASK 0x1000 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist1_vec_ena__SHIFT 0xc +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena_MASK 0x2000 +#define SXIFCCG_DEBUG_REG3__statevar_bits_vs_out_ccdist0_vec_ena__SHIFT 0xd +#define SXIFCCG_DEBUG_REG3__available_positions_MASK 0x1fc000 +#define SXIFCCG_DEBUG_REG3__available_positions__SHIFT 0xe +#define SXIFCCG_DEBUG_REG3__current_state_MASK 0x600000 +#define SXIFCCG_DEBUG_REG3__current_state__SHIFT 0x15 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty_MASK 0x800000 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_empty__SHIFT 0x17 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full_MASK 0x1000000 +#define SXIFCCG_DEBUG_REG3__vertex_fifo_full__SHIFT 0x18 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty_MASK 0x2000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_empty__SHIFT 0x19 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full_MASK 0x4000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_full__SHIFT 0x1a +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty_MASK 0x8000000 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_empty__SHIFT 0x1b +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full_MASK 0x10000000 +#define SXIFCCG_DEBUG_REG3__vgt_to_ccgen_fifo_full__SHIFT 0x1c +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full_MASK 0x20000000 +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_fifo_full__SHIFT 0x1d +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write_MASK 0x40000000 +#define SXIFCCG_DEBUG_REG3__sx0_receive_fifo_write__SHIFT 0x1e +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write_MASK 0x80000000 +#define SXIFCCG_DEBUG_REG3__ccgen_to_clipcc_write__SHIFT 0x1f +#define SETUP_DEBUG_REG0__su_baryc_cntl_state_MASK 0x3 +#define SETUP_DEBUG_REG0__su_baryc_cntl_state__SHIFT 0x0 +#define SETUP_DEBUG_REG0__su_cntl_state_MASK 0x3c +#define SETUP_DEBUG_REG0__su_cntl_state__SHIFT 0x2 +#define SETUP_DEBUG_REG0__pmode_state_MASK 0x3f00 +#define SETUP_DEBUG_REG0__pmode_state__SHIFT 0x8 +#define SETUP_DEBUG_REG0__ge_stallb_MASK 0x4000 +#define SETUP_DEBUG_REG0__ge_stallb__SHIFT 0xe +#define SETUP_DEBUG_REG0__geom_enable_MASK 0x8000 +#define SETUP_DEBUG_REG0__geom_enable__SHIFT 0xf +#define SETUP_DEBUG_REG0__su_clip_baryc_free_MASK 0x30000 +#define SETUP_DEBUG_REG0__su_clip_baryc_free__SHIFT 0x10 +#define SETUP_DEBUG_REG0__su_clip_rtr_MASK 0x40000 +#define SETUP_DEBUG_REG0__su_clip_rtr__SHIFT 0x12 +#define SETUP_DEBUG_REG0__pfifo_busy_MASK 0x80000 +#define SETUP_DEBUG_REG0__pfifo_busy__SHIFT 0x13 +#define SETUP_DEBUG_REG0__su_cntl_busy_MASK 0x100000 +#define SETUP_DEBUG_REG0__su_cntl_busy__SHIFT 0x14 +#define SETUP_DEBUG_REG0__geom_busy_MASK 0x200000 +#define SETUP_DEBUG_REG0__geom_busy__SHIFT 0x15 +#define SETUP_DEBUG_REG0__event_id_gated_MASK 0xfc00000 +#define SETUP_DEBUG_REG0__event_id_gated__SHIFT 0x16 +#define SETUP_DEBUG_REG0__event_gated_MASK 0x10000000 +#define SETUP_DEBUG_REG0__event_gated__SHIFT 0x1c +#define SETUP_DEBUG_REG0__pmode_prim_gated_MASK 0x20000000 +#define SETUP_DEBUG_REG0__pmode_prim_gated__SHIFT 0x1d +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld_MASK 0x40000000 +#define SETUP_DEBUG_REG0__su_dyn_sclk_vld__SHIFT 0x1e +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld_MASK 0x80000000 +#define SETUP_DEBUG_REG0__cl_dyn_sclk_vld__SHIFT 0x1f +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG1__y_sort0_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG1__x_sort0_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG2__y_sort1_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG2__x_sort1_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8_MASK 0xffff +#define SETUP_DEBUG_REG3__y_sort2_gated_23_8__SHIFT 0x0 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8_MASK 0xffff0000 +#define SETUP_DEBUG_REG3__x_sort2_gated_23_8__SHIFT 0x10 +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated_MASK 0x3fff +#define SETUP_DEBUG_REG4__attr_indx_sort0_gated__SHIFT 0x0 +#define SETUP_DEBUG_REG4__null_prim_gated_MASK 0x4000 +#define SETUP_DEBUG_REG4__null_prim_gated__SHIFT 0xe +#define SETUP_DEBUG_REG4__backfacing_gated_MASK 0x8000 +#define SETUP_DEBUG_REG4__backfacing_gated__SHIFT 0xf +#define SETUP_DEBUG_REG4__st_indx_gated_MASK 0x70000 +#define SETUP_DEBUG_REG4__st_indx_gated__SHIFT 0x10 +#define SETUP_DEBUG_REG4__clipped_gated_MASK 0x80000 +#define SETUP_DEBUG_REG4__clipped_gated__SHIFT 0x13 +#define SETUP_DEBUG_REG4__dealloc_slot_gated_MASK 0x700000 +#define SETUP_DEBUG_REG4__dealloc_slot_gated__SHIFT 0x14 +#define SETUP_DEBUG_REG4__xmajor_gated_MASK 0x800000 +#define SETUP_DEBUG_REG4__xmajor_gated__SHIFT 0x17 +#define SETUP_DEBUG_REG4__diamond_rule_gated_MASK 0x3000000 +#define SETUP_DEBUG_REG4__diamond_rule_gated__SHIFT 0x18 +#define SETUP_DEBUG_REG4__type_gated_MASK 0x1c000000 +#define SETUP_DEBUG_REG4__type_gated__SHIFT 0x1a +#define SETUP_DEBUG_REG4__fpov_gated_MASK 0x60000000 +#define SETUP_DEBUG_REG4__fpov_gated__SHIFT 0x1d +#define SETUP_DEBUG_REG4__eop_gated_MASK 0x80000000 +#define SETUP_DEBUG_REG4__eop_gated__SHIFT 0x1f +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated_MASK 0x3fff +#define SETUP_DEBUG_REG5__attr_indx_sort2_gated__SHIFT 0x0 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated_MASK 0xfffc000 +#define SETUP_DEBUG_REG5__attr_indx_sort1_gated__SHIFT 0xe +#define SETUP_DEBUG_REG5__provoking_vtx_gated_MASK 0x30000000 +#define SETUP_DEBUG_REG5__provoking_vtx_gated__SHIFT 0x1c +#define SETUP_DEBUG_REG5__valid_prim_gated_MASK 0x40000000 +#define SETUP_DEBUG_REG5__valid_prim_gated__SHIFT 0x1e +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld_MASK 0x80000000 +#define SETUP_DEBUG_REG5__pa_reg_sclk_vld__SHIFT 0x1f +#define PA_SC_DEBUG_REG0__REG0_FIELD0_MASK 0x3 +#define PA_SC_DEBUG_REG0__REG0_FIELD0__SHIFT 0x0 +#define PA_SC_DEBUG_REG0__REG0_FIELD1_MASK 0xc +#define PA_SC_DEBUG_REG0__REG0_FIELD1__SHIFT 0x2 +#define PA_SC_DEBUG_REG1__REG1_FIELD0_MASK 0x3 +#define PA_SC_DEBUG_REG1__REG1_FIELD0__SHIFT 0x0 +#define PA_SC_DEBUG_REG1__REG1_FIELD1_MASK 0xc +#define PA_SC_DEBUG_REG1__REG1_FIELD1__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN_MASK 0x1 +#define COMPUTE_DISPATCH_INITIATOR__COMPUTE_SHADER_EN__SHIFT 0x0 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN_MASK 0x2 +#define COMPUTE_DISPATCH_INITIATOR__PARTIAL_TG_EN__SHIFT 0x1 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000_MASK 0x4 +#define COMPUTE_DISPATCH_INITIATOR__FORCE_START_AT_000__SHIFT 0x2 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL_MASK 0x8 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_ENBL__SHIFT 0x3 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE_MASK 0x10 +#define COMPUTE_DISPATCH_INITIATOR__ORDERED_APPEND_MODE__SHIFT 0x4 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS_MASK 0x20 +#define COMPUTE_DISPATCH_INITIATOR__USE_THREAD_DIMENSIONS__SHIFT 0x5 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE_MASK 0x40 +#define COMPUTE_DISPATCH_INITIATOR__ORDER_MODE__SHIFT 0x6 +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL_MASK 0x380 +#define COMPUTE_DISPATCH_INITIATOR__DISPATCH_CACHE_CNTL__SHIFT 0x7 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL_MASK 0x400 +#define COMPUTE_DISPATCH_INITIATOR__SCALAR_L1_INV_VOL__SHIFT 0xa +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL_MASK 0x800 +#define COMPUTE_DISPATCH_INITIATOR__VECTOR_L1_INV_VOL__SHIFT 0xb +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC_MASK 0x1000 +#define COMPUTE_DISPATCH_INITIATOR__DATA_ATC__SHIFT 0xc +#define COMPUTE_DISPATCH_INITIATOR__RESTORE_MASK 0x4000 +#define COMPUTE_DISPATCH_INITIATOR__RESTORE__SHIFT 0xe +#define COMPUTE_DIM_X__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_X__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Y__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_Y__SIZE__SHIFT 0x0 +#define COMPUTE_DIM_Z__SIZE_MASK 0xffffffff +#define COMPUTE_DIM_Z__SIZE__SHIFT 0x0 +#define COMPUTE_START_X__START_MASK 0xffffffff +#define COMPUTE_START_X__START__SHIFT 0x0 +#define COMPUTE_START_Y__START_MASK 0xffffffff +#define COMPUTE_START_Y__START__SHIFT 0x0 +#define COMPUTE_START_Z__START_MASK 0xffffffff +#define COMPUTE_START_Z__START__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_X__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_Y__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL_MASK 0xffff +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_FULL__SHIFT 0x0 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL_MASK 0xffff0000 +#define COMPUTE_NUM_THREAD_Z__NUM_THREAD_PARTIAL__SHIFT 0x10 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE_MASK 0x1 +#define COMPUTE_PIPELINESTAT_ENABLE__PIPELINESTAT_ENABLE__SHIFT 0x0 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE_MASK 0x1 +#define COMPUTE_PERFCOUNT_ENABLE__PERFCOUNT_ENABLE__SHIFT 0x0 +#define COMPUTE_PGM_LO__DATA_MASK 0xffffffff +#define COMPUTE_PGM_LO__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__DATA_MASK 0xff +#define COMPUTE_PGM_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_HI__INST_ATC_MASK 0x100 +#define COMPUTE_PGM_HI__INST_ATC__SHIFT 0x8 +#define COMPUTE_TBA_LO__DATA_MASK 0xffffffff +#define COMPUTE_TBA_LO__DATA__SHIFT 0x0 +#define COMPUTE_TBA_HI__DATA_MASK 0xff +#define COMPUTE_TBA_HI__DATA__SHIFT 0x0 +#define COMPUTE_TMA_LO__DATA_MASK 0xffffffff +#define COMPUTE_TMA_LO__DATA__SHIFT 0x0 +#define COMPUTE_TMA_HI__DATA_MASK 0xff +#define COMPUTE_TMA_HI__DATA__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__VGPRS_MASK 0x3f +#define COMPUTE_PGM_RSRC1__VGPRS__SHIFT 0x0 +#define COMPUTE_PGM_RSRC1__SGPRS_MASK 0x3c0 +#define COMPUTE_PGM_RSRC1__SGPRS__SHIFT 0x6 +#define COMPUTE_PGM_RSRC1__PRIORITY_MASK 0xc00 +#define COMPUTE_PGM_RSRC1__PRIORITY__SHIFT 0xa +#define COMPUTE_PGM_RSRC1__FLOAT_MODE_MASK 0xff000 +#define COMPUTE_PGM_RSRC1__FLOAT_MODE__SHIFT 0xc +#define COMPUTE_PGM_RSRC1__PRIV_MASK 0x100000 +#define COMPUTE_PGM_RSRC1__PRIV__SHIFT 0x14 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP_MASK 0x200000 +#define COMPUTE_PGM_RSRC1__DX10_CLAMP__SHIFT 0x15 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE_MASK 0x400000 +#define COMPUTE_PGM_RSRC1__DEBUG_MODE__SHIFT 0x16 +#define COMPUTE_PGM_RSRC1__IEEE_MODE_MASK 0x800000 +#define COMPUTE_PGM_RSRC1__IEEE_MODE__SHIFT 0x17 +#define COMPUTE_PGM_RSRC1__BULKY_MASK 0x1000000 +#define COMPUTE_PGM_RSRC1__BULKY__SHIFT 0x18 +#define COMPUTE_PGM_RSRC1__CDBG_USER_MASK 0x2000000 +#define COMPUTE_PGM_RSRC1__CDBG_USER__SHIFT 0x19 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN_MASK 0x1 +#define COMPUTE_PGM_RSRC2__SCRATCH_EN__SHIFT 0x0 +#define COMPUTE_PGM_RSRC2__USER_SGPR_MASK 0x3e +#define COMPUTE_PGM_RSRC2__USER_SGPR__SHIFT 0x1 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT_MASK 0x40 +#define COMPUTE_PGM_RSRC2__TRAP_PRESENT__SHIFT 0x6 +#define COMPUTE_PGM_RSRC2__TGID_X_EN_MASK 0x80 +#define COMPUTE_PGM_RSRC2__TGID_X_EN__SHIFT 0x7 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN_MASK 0x100 +#define COMPUTE_PGM_RSRC2__TGID_Y_EN__SHIFT 0x8 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN_MASK 0x200 +#define COMPUTE_PGM_RSRC2__TGID_Z_EN__SHIFT 0x9 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN_MASK 0x400 +#define COMPUTE_PGM_RSRC2__TG_SIZE_EN__SHIFT 0xa +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT_MASK 0x1800 +#define COMPUTE_PGM_RSRC2__TIDIG_COMP_CNT__SHIFT 0xb +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB_MASK 0x6000 +#define COMPUTE_PGM_RSRC2__EXCP_EN_MSB__SHIFT 0xd +#define COMPUTE_PGM_RSRC2__LDS_SIZE_MASK 0xff8000 +#define COMPUTE_PGM_RSRC2__LDS_SIZE__SHIFT 0xf +#define COMPUTE_PGM_RSRC2__EXCP_EN_MASK 0x7f000000 +#define COMPUTE_PGM_RSRC2__EXCP_EN__SHIFT 0x18 +#define COMPUTE_VMID__DATA_MASK 0xf +#define COMPUTE_VMID__DATA__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH_MASK 0x3ff +#define COMPUTE_RESOURCE_LIMITS__WAVES_PER_SH__SHIFT 0x0 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU_MASK 0xf000 +#define COMPUTE_RESOURCE_LIMITS__TG_PER_CU__SHIFT 0xc +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD_MASK 0x3f0000 +#define COMPUTE_RESOURCE_LIMITS__LOCK_THRESHOLD__SHIFT 0x10 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL_MASK 0x400000 +#define COMPUTE_RESOURCE_LIMITS__SIMD_DEST_CNTL__SHIFT 0x16 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST_MASK 0x800000 +#define COMPUTE_RESOURCE_LIMITS__FORCE_SIMD_DIST__SHIFT 0x17 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT_MASK 0x7000000 +#define COMPUTE_RESOURCE_LIMITS__CU_GROUP_COUNT__SHIFT 0x18 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE0__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE1__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_TMPRING_SIZE__WAVES_MASK 0xfff +#define COMPUTE_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define COMPUTE_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 +#define COMPUTE_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE2__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN_MASK 0xffff +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH0_CU_EN__SHIFT 0x0 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN_MASK 0xffff0000 +#define COMPUTE_STATIC_THREAD_MGMT_SE3__SH1_CU_EN__SHIFT 0x10 +#define COMPUTE_RESTART_X__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_X__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Y__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_Y__RESTART__SHIFT 0x0 +#define COMPUTE_RESTART_Z__RESTART_MASK 0xffffffff +#define COMPUTE_RESTART_Z__RESTART__SHIFT 0x0 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE_MASK 0x1 +#define COMPUTE_THREAD_TRACE_ENABLE__THREAD_TRACE_ENABLE__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__SEND_SEID_MASK 0x3 +#define COMPUTE_MISC_RESERVED__SEND_SEID__SHIFT 0x0 +#define COMPUTE_MISC_RESERVED__RESERVED2_MASK 0x4 +#define COMPUTE_MISC_RESERVED__RESERVED2__SHIFT 0x2 +#define COMPUTE_MISC_RESERVED__RESERVED3_MASK 0x8 +#define COMPUTE_MISC_RESERVED__RESERVED3__SHIFT 0x3 +#define COMPUTE_MISC_RESERVED__RESERVED4_MASK 0x10 +#define COMPUTE_MISC_RESERVED__RESERVED4__SHIFT 0x4 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE_MASK 0x1ffe0 +#define COMPUTE_MISC_RESERVED__WAVE_ID_BASE__SHIFT 0x5 +#define COMPUTE_DISPATCH_ID__DISPATCH_ID_MASK 0xffffffff +#define COMPUTE_DISPATCH_ID__DISPATCH_ID__SHIFT 0x0 +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID_MASK 0xffffffff +#define COMPUTE_THREADGROUP_ID__THREADGROUP_ID__SHIFT 0x0 +#define COMPUTE_RELAUNCH__PAYLOAD_MASK 0x3fffffff +#define COMPUTE_RELAUNCH__PAYLOAD__SHIFT 0x0 +#define COMPUTE_RELAUNCH__IS_EVENT_MASK 0x40000000 +#define COMPUTE_RELAUNCH__IS_EVENT__SHIFT 0x1e +#define COMPUTE_RELAUNCH__IS_STATE_MASK 0x80000000 +#define COMPUTE_RELAUNCH__IS_STATE__SHIFT 0x1f +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR_MASK 0xffffffff +#define COMPUTE_WAVE_RESTORE_ADDR_LO__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR_MASK 0xffff +#define COMPUTE_WAVE_RESTORE_ADDR_HI__ADDR__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_CONTROL__ATC_MASK 0x1 +#define COMPUTE_WAVE_RESTORE_CONTROL__ATC__SHIFT 0x0 +#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE_MASK 0x6 +#define COMPUTE_WAVE_RESTORE_CONTROL__MTYPE__SHIFT 0x1 +#define COMPUTE_USER_DATA_0__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_0__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_1__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_1__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_2__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_2__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_3__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_3__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_4__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_4__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_5__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_5__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_6__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_6__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_7__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_7__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_8__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_8__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_9__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_9__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_10__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_10__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_11__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_11__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_12__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_12__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_13__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_13__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_14__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_14__DATA__SHIFT 0x0 +#define COMPUTE_USER_DATA_15__DATA_MASK 0xffffffff +#define COMPUTE_USER_DATA_15__DATA__SHIFT 0x0 +#define COMPUTE_NOWHERE__DATA_MASK 0xffffffff +#define COMPUTE_NOWHERE__DATA__SHIFT 0x0 +#define CSPRIV_CONNECT__DOORBELL_OFFSET_MASK 0x1fffff +#define CSPRIV_CONNECT__DOORBELL_OFFSET__SHIFT 0x0 +#define CSPRIV_CONNECT__QUEUE_ID_MASK 0xe00000 +#define CSPRIV_CONNECT__QUEUE_ID__SHIFT 0x15 +#define CSPRIV_CONNECT__VMID_MASK 0x3c000000 +#define CSPRIV_CONNECT__VMID__SHIFT 0x1a +#define CSPRIV_CONNECT__UNORD_DISP_MASK 0x80000000 +#define CSPRIV_CONNECT__UNORD_DISP__SHIFT 0x1f +#define CSPRIV_THREAD_TRACE_TG0__TGID_X_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG0__TGID_X__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG1__TGID_Y_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG1__TGID_Y__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG2__TGID_Z_MASK 0xffffffff +#define CSPRIV_THREAD_TRACE_TG2__TGID_Z__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE_MASK 0xfff +#define CSPRIV_THREAD_TRACE_TG3__WAVE_ID_BASE__SHIFT 0x0 +#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP_MASK 0xfff000 +#define CSPRIV_THREAD_TRACE_TG3__THREADS_IN_GROUP__SHIFT 0xc +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG_MASK 0x1000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_X_FLAG__SHIFT 0x18 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG_MASK 0x2000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Y_FLAG__SHIFT 0x19 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG_MASK 0x4000000 +#define CSPRIV_THREAD_TRACE_TG3__PARTIAL_Z_FLAG__SHIFT 0x1a +#define CSPRIV_THREAD_TRACE_TG3__LAST_TG_MASK 0x8000000 +#define CSPRIV_THREAD_TRACE_TG3__LAST_TG__SHIFT 0x1b +#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG_MASK 0x10000000 +#define CSPRIV_THREAD_TRACE_TG3__FIRST_TG__SHIFT 0x1c +#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID_MASK 0x1f +#define CSPRIV_THREAD_TRACE_EVENT__EVENT_ID__SHIFT 0x0 +#define RLC_CNTL__RLC_ENABLE_F32_MASK 0x1 +#define RLC_CNTL__RLC_ENABLE_F32__SHIFT 0x0 +#define RLC_CNTL__FORCE_RETRY_MASK 0x2 +#define RLC_CNTL__FORCE_RETRY__SHIFT 0x1 +#define RLC_CNTL__READ_CACHE_DISABLE_MASK 0x4 +#define RLC_CNTL__READ_CACHE_DISABLE__SHIFT 0x2 +#define RLC_CNTL__RLC_STEP_F32_MASK 0x8 +#define RLC_CNTL__RLC_STEP_F32__SHIFT 0x3 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE_MASK 0x10 +#define RLC_CNTL__SOFT_RESET_DEBUG_MODE__SHIFT 0x4 +#define RLC_CNTL__RESERVED_MASK 0xffffff00 +#define RLC_CNTL__RESERVED__SHIFT 0x8 +#define RLC_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_DEBUG_SELECT__RESERVED_MASK 0xffffff00 +#define RLC_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_DEBUG__DATA_MASK 0xffffffff +#define RLC_DEBUG__DATA__SHIFT 0x0 +#define RLC_MC_CNTL__WRREQ_SWAP_MASK 0x3 +#define RLC_MC_CNTL__WRREQ_SWAP__SHIFT 0x0 +#define RLC_MC_CNTL__WRREQ_TRAN_MASK 0x4 +#define RLC_MC_CNTL__WRREQ_TRAN__SHIFT 0x2 +#define RLC_MC_CNTL__WRREQ_PRIV_MASK 0x8 +#define RLC_MC_CNTL__WRREQ_PRIV__SHIFT 0x3 +#define RLC_MC_CNTL__WRNFO_STALL_MASK 0x10 +#define RLC_MC_CNTL__WRNFO_STALL__SHIFT 0x4 +#define RLC_MC_CNTL__WRNFO_URG_MASK 0x1e0 +#define RLC_MC_CNTL__WRNFO_URG__SHIFT 0x5 +#define RLC_MC_CNTL__WRREQ_DW_IMASK_MASK 0x1e00 +#define RLC_MC_CNTL__WRREQ_DW_IMASK__SHIFT 0x9 +#define RLC_MC_CNTL__RESERVED_B_MASK 0xfe000 +#define RLC_MC_CNTL__RESERVED_B__SHIFT 0xd +#define RLC_MC_CNTL__RDNFO_URG_MASK 0xf00000 +#define RLC_MC_CNTL__RDNFO_URG__SHIFT 0x14 +#define RLC_MC_CNTL__RDREQ_SWAP_MASK 0x3000000 +#define RLC_MC_CNTL__RDREQ_SWAP__SHIFT 0x18 +#define RLC_MC_CNTL__RDREQ_TRAN_MASK 0x4000000 +#define RLC_MC_CNTL__RDREQ_TRAN__SHIFT 0x1a +#define RLC_MC_CNTL__RDREQ_PRIV_MASK 0x8000000 +#define RLC_MC_CNTL__RDREQ_PRIV__SHIFT 0x1b +#define RLC_MC_CNTL__RDNFO_STALL_MASK 0x10000000 +#define RLC_MC_CNTL__RDNFO_STALL__SHIFT 0x1c +#define RLC_MC_CNTL__RESERVED_MASK 0xe0000000 +#define RLC_MC_CNTL__RESERVED__SHIFT 0x1d +#define RLC_STAT__RLC_BUSY_MASK 0x1 +#define RLC_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_STAT__RLC_GPM_BUSY_MASK 0x2 +#define RLC_STAT__RLC_GPM_BUSY__SHIFT 0x1 +#define RLC_STAT__RLC_SPM_BUSY_MASK 0x4 +#define RLC_STAT__RLC_SPM_BUSY__SHIFT 0x2 +#define RLC_STAT__RLC_SRM_BUSY_MASK 0x8 +#define RLC_STAT__RLC_SRM_BUSY__SHIFT 0x3 +#define RLC_STAT__RESERVED_MASK 0xfffffff0 +#define RLC_STAT__RESERVED__SHIFT 0x4 +#define RLC_SAFE_MODE__CMD_MASK 0x1 +#define RLC_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SAFE_MODE__MESSAGE_MASK 0x1e +#define RLC_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SAFE_MODE__RESERVED1_MASK 0xe0 +#define RLC_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SAFE_MODE__RESPONSE_MASK 0xf00 +#define RLC_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SAFE_MODE__RESERVED_MASK 0xfffff000 +#define RLC_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK 0x1 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN__SHIFT 0x0 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN_MASK 0x2 +#define RLC_MEM_SLP_CNTL__RLC_MEM_DS_EN__SHIFT 0x1 +#define RLC_MEM_SLP_CNTL__RESERVED_MASK 0x7c +#define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE_MASK 0x80 +#define RLC_MEM_SLP_CNTL__RLC_LS_DS_BUSY_OVERRIDE__SHIFT 0x7 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY_MASK 0xff00 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_ON_DELAY__SHIFT 0x8 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY_MASK 0xff0000 +#define RLC_MEM_SLP_CNTL__RLC_MEM_LS_OFF_DELAY__SHIFT 0x10 +#define RLC_MEM_SLP_CNTL__RESERVED1_MASK 0xff000000 +#define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 +#define SMU_RLC_RESPONSE__RESP_MASK 0xffffffff +#define SMU_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__CMD_MASK 0x1 +#define RLC_RLCV_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_RLCV_SAFE_MODE__MESSAGE_MASK 0x1e +#define RLC_RLCV_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_RLCV_SAFE_MODE__RESERVED1_MASK 0xe0 +#define RLC_RLCV_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_RLCV_SAFE_MODE__RESPONSE_MASK 0xf00 +#define RLC_RLCV_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_RLCV_SAFE_MODE__RESERVED_MASK 0xfffff000 +#define RLC_RLCV_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_SMU_SAFE_MODE__CMD_MASK 0x1 +#define RLC_SMU_SAFE_MODE__CMD__SHIFT 0x0 +#define RLC_SMU_SAFE_MODE__MESSAGE_MASK 0x1e +#define RLC_SMU_SAFE_MODE__MESSAGE__SHIFT 0x1 +#define RLC_SMU_SAFE_MODE__RESERVED1_MASK 0xe0 +#define RLC_SMU_SAFE_MODE__RESERVED1__SHIFT 0x5 +#define RLC_SMU_SAFE_MODE__RESPONSE_MASK 0xf00 +#define RLC_SMU_SAFE_MODE__RESPONSE__SHIFT 0x8 +#define RLC_SMU_SAFE_MODE__RESERVED_MASK 0xfffff000 +#define RLC_SMU_SAFE_MODE__RESERVED__SHIFT 0xc +#define RLC_RLCV_COMMAND__CMD_MASK 0xf +#define RLC_RLCV_COMMAND__CMD__SHIFT 0x0 +#define RLC_RLCV_COMMAND__RESERVED_MASK 0xfffffff0 +#define RLC_RLCV_COMMAND__RESERVED__SHIFT 0x4 +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL_MASK 0x1 +#define RLC_CLK_CNTL__RLC_SRM_CLK_CNTL__SHIFT 0x0 +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL_MASK 0x2 +#define RLC_CLK_CNTL__RLC_SPM_CLK_CNTL__SHIFT 0x1 +#define RLC_CLK_CNTL__RESERVED_MASK 0xfffffffc +#define RLC_CLK_CNTL__RESERVED__SHIFT 0x2 +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK 0x1 +#define RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_STATE_MASK 0x7 +#define RLC_PERFMON_CNTL__PERFMON_STATE__SHIFT 0x0 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK 0x400 +#define RLC_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT 0xa +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0xff +#define RLC_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0xff +#define RLC_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define RLC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define RLC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define RLC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define RLC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_RLC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_RLC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN_MASK 0x40000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_DYN__SHIFT 0x1e +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG_MASK 0x80000000 +#define CGTT_RLC_CLK_CTRL__SOFT_OVERRIDE_REG__SHIFT 0x1f +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE_MASK 0x1 +#define RLC_LB_CNTL__LOAD_BALANCE_ENABLE__SHIFT 0x0 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY_MASK 0x2 +#define RLC_LB_CNTL__LB_CNT_CP_BUSY__SHIFT 0x1 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK 0x4 +#define RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE__SHIFT 0x2 +#define RLC_LB_CNTL__LB_CNT_REG_INC_MASK 0x8 +#define RLC_LB_CNTL__LB_CNT_REG_INC__SHIFT 0x3 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST_MASK 0xff0 +#define RLC_LB_CNTL__CU_MASK_USED_OFF_HYST__SHIFT 0x4 +#define RLC_LB_CNTL__RESERVED_MASK 0xfffff000 +#define RLC_LB_CNTL__RESERVED__SHIFT 0xc +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX_MASK 0xffffffff +#define RLC_LB_CNTR_MAX__LB_CNTR_MAX__SHIFT 0x0 +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT_MASK 0xffffffff +#define RLC_LB_CNTR_INIT__LB_CNTR_INIT__SHIFT 0x0 +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR_MASK 0xffffffff +#define RLC_LOAD_BALANCE_CNTR__RLC_LOAD_BALANCE_CNTR__SHIFT 0x0 +#define RLC_JUMP_TABLE_RESTORE__ADDR_MASK 0xffffffff +#define RLC_JUMP_TABLE_RESTORE__ADDR__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE_MASK 0xff +#define RLC_PG_DELAY_2__SERDES_TIMEOUT_VALUE__SHIFT 0x0 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK 0xff00 +#define RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE_MASK 0xffff0000 +#define RLC_PG_DELAY_2__PERCU_TIMEOUT_VALUE__SHIFT 0x10 +#define RLC_GPM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_GPM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT_MASK 0x300 +#define RLC_GPM_DEBUG_SELECT__F32_DEBUG_SELECT__SHIFT 0x8 +#define RLC_GPM_DEBUG_SELECT__RESERVED_MASK 0xfffffc00 +#define RLC_GPM_DEBUG_SELECT__RESERVED__SHIFT 0xa +#define RLC_GPM_DEBUG__DATA_MASK 0xffffffff +#define RLC_GPM_DEBUG__DATA__SHIFT 0x0 +#define RLC_GPM_DEBUG_INST_A__INST_A_MASK 0xffffffff +#define RLC_GPM_DEBUG_INST_A__INST_A__SHIFT 0x0 +#define RLC_GPM_DEBUG_INST_B__INST_B_MASK 0xffffffff +#define RLC_GPM_DEBUG_INST_B__INST_B__SHIFT 0x0 +#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A_MASK 0xffff +#define RLC_GPM_DEBUG_INST_ADDR__ADRR_A__SHIFT 0x0 +#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B_MASK 0xffff0000 +#define RLC_GPM_DEBUG_INST_ADDR__ADDR_B__SHIFT 0x10 +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR_MASK 0xfff +#define RLC_GPM_UCODE_ADDR__UCODE_ADDR__SHIFT 0x0 +#define RLC_GPM_UCODE_ADDR__RESERVED_MASK 0xfffff000 +#define RLC_GPM_UCODE_ADDR__RESERVED__SHIFT 0xc +#define RLC_GPM_UCODE_DATA__UCODE_DATA_MASK 0xffffffff +#define RLC_GPM_UCODE_DATA__UCODE_DATA__SHIFT 0x0 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW_MASK 0x1 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_HW__SHIFT 0x0 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV_MASK 0x2 +#define GPU_BIST_CONTROL__STOP_ON_FAIL_CU_HARV__SHIFT 0x1 +#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT_MASK 0x3c +#define GPU_BIST_CONTROL__CU_HARV_LOOP_COUNT__SHIFT 0x2 +#define GPU_BIST_CONTROL__RESERVED_MASK 0xffff80 +#define GPU_BIST_CONTROL__RESERVED__SHIFT 0x7 +#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT_MASK 0xff000000 +#define GPU_BIST_CONTROL__GLOBAL_LOOP_COUNT__SHIFT 0x18 +#define RLC_ROM_CNTL__USE_ROM_MASK 0x1 +#define RLC_ROM_CNTL__USE_ROM__SHIFT 0x0 +#define RLC_ROM_CNTL__SLP_MODE_EN_MASK 0x2 +#define RLC_ROM_CNTL__SLP_MODE_EN__SHIFT 0x1 +#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN_MASK 0x4 +#define RLC_ROM_CNTL__EFUSE_DISTRIB_EN__SHIFT 0x2 +#define RLC_ROM_CNTL__HELLOWORLD_EN_MASK 0x8 +#define RLC_ROM_CNTL__HELLOWORLD_EN__SHIFT 0x3 +#define RLC_ROM_CNTL__CU_HARVEST_EN_MASK 0x10 +#define RLC_ROM_CNTL__CU_HARVEST_EN__SHIFT 0x4 +#define RLC_ROM_CNTL__RESERVED_MASK 0xffffffe0 +#define RLC_ROM_CNTL__RESERVED__SHIFT 0x5 +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB_MASK 0xffffffff +#define RLC_GPU_CLOCK_COUNT_LSB__GPU_CLOCKS_LSB__SHIFT 0x0 +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB_MASK 0xffffffff +#define RLC_GPU_CLOCK_COUNT_MSB__GPU_CLOCKS_MSB__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE_MASK 0x1 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__CAPTURE__SHIFT 0x0 +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED_MASK 0xfffffffe +#define RLC_CAPTURE_GPU_CLOCK_COUNT__RESERVED__SHIFT 0x1 +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS_MASK 0xffffffff +#define RLC_UCODE_CNTL__RLC_UCODE_FLAGS__SHIFT 0x0 +#define RLC_GPM_STAT__RLC_BUSY_MASK 0x1 +#define RLC_GPM_STAT__RLC_BUSY__SHIFT 0x0 +#define RLC_GPM_STAT__GFX_POWER_STATUS_MASK 0x2 +#define RLC_GPM_STAT__GFX_POWER_STATUS__SHIFT 0x1 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS_MASK 0x4 +#define RLC_GPM_STAT__GFX_CLOCK_STATUS__SHIFT 0x2 +#define RLC_GPM_STAT__GFX_LS_STATUS_MASK 0x8 +#define RLC_GPM_STAT__GFX_LS_STATUS__SHIFT 0x3 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10 +#define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS__SHIFT 0x4 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED_MASK 0x20 +#define RLC_GPM_STAT__CNTX_IDLE_BEING_PROCESSED__SHIFT 0x5 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED_MASK 0x40 +#define RLC_GPM_STAT__CNTX_BUSY_BEING_PROCESSED__SHIFT 0x6 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED_MASK 0x80 +#define RLC_GPM_STAT__GFX_IDLE_BEING_PROCESSED__SHIFT 0x7 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED_MASK 0x100 +#define RLC_GPM_STAT__CMP_BUSY_BEING_PROCESSED__SHIFT 0x8 +#define RLC_GPM_STAT__SAVING_REGISTERS_MASK 0x200 +#define RLC_GPM_STAT__SAVING_REGISTERS__SHIFT 0x9 +#define RLC_GPM_STAT__RESTORING_REGISTERS_MASK 0x400 +#define RLC_GPM_STAT__RESTORING_REGISTERS__SHIFT 0xa +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE_MASK 0x800 +#define RLC_GPM_STAT__GFX3D_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xb +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE_MASK 0x1000 +#define RLC_GPM_STAT__CMP_BLOCKS_CHANGING_POWER_STATE__SHIFT 0xc +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP_MASK 0x2000 +#define RLC_GPM_STAT__STATIC_CU_POWERING_UP__SHIFT 0xd +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN_MASK 0x4000 +#define RLC_GPM_STAT__STATIC_CU_POWERING_DOWN__SHIFT 0xe +#define RLC_GPM_STAT__DYN_CU_POWERING_UP_MASK 0x8000 +#define RLC_GPM_STAT__DYN_CU_POWERING_UP__SHIFT 0xf +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN_MASK 0x10000 +#define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000 +#define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 +#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000 +#define RLC_GPM_STAT__RESERVED__SHIFT 0x12 +#define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000 +#define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f +#define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED_MASK 0xffffffc0 +#define RLC_GPU_CLOCK_32_RES_SEL__RESERVED__SHIFT 0x6 +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32_MASK 0xffffffff +#define RLC_GPU_CLOCK_32__GPU_CLOCK_32__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK 0x1 +#define RLC_PG_CNTL__GFX_POWER_GATING_ENABLE__SHIFT 0x0 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC_MASK 0x2 +#define RLC_PG_CNTL__GFX_POWER_GATING_SRC__SHIFT 0x1 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK 0x4 +#define RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE__SHIFT 0x2 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK 0x8 +#define RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE__SHIFT 0x3 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK 0x10 +#define RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE__SHIFT 0x4 +#define RLC_PG_CNTL__RESERVED_MASK 0x3fe0 +#define RLC_PG_CNTL__RESERVED__SHIFT 0x5 +#define RLC_PG_CNTL__PG_OVERRIDE_MASK 0x4000 +#define RLC_PG_CNTL__PG_OVERRIDE__SHIFT 0xe +#define RLC_PG_CNTL__CP_PG_DISABLE_MASK 0x8000 +#define RLC_PG_CNTL__CP_PG_DISABLE__SHIFT 0xf +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE_MASK 0x10000 +#define RLC_PG_CNTL__CHUB_HANDSHAKE_ENABLE__SHIFT 0x10 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK 0x20000 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE__SHIFT 0x11 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK 0x40000 +#define RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE__SHIFT 0x12 +#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE_MASK 0x80000 +#define RLC_PG_CNTL__SMU_HANDSHAKE_ENABLE__SHIFT 0x13 +#define RLC_PG_CNTL__RESERVED1_MASK 0xf00000 +#define RLC_PG_CNTL__RESERVED1__SHIFT 0x14 +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY_MASK 0xff +#define RLC_GPM_THREAD_PRIORITY__THREAD0_PRIORITY__SHIFT 0x0 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY_MASK 0xff00 +#define RLC_GPM_THREAD_PRIORITY__THREAD1_PRIORITY__SHIFT 0x8 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY_MASK 0xff0000 +#define RLC_GPM_THREAD_PRIORITY__THREAD2_PRIORITY__SHIFT 0x10 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY_MASK 0xff000000 +#define RLC_GPM_THREAD_PRIORITY__THREAD3_PRIORITY__SHIFT 0x18 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE_MASK 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD0_ENABLE__SHIFT 0x0 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE_MASK 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD1_ENABLE__SHIFT 0x1 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE_MASK 0x4 +#define RLC_GPM_THREAD_ENABLE__THREAD2_ENABLE__SHIFT 0x2 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE_MASK 0x8 +#define RLC_GPM_THREAD_ENABLE__THREAD3_ENABLE__SHIFT 0x3 +#define RLC_GPM_THREAD_ENABLE__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_THREAD_ENABLE__RESERVED__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD0__RLC_VMID_MASK 0xf +#define RLC_GPM_VMID_THREAD0__RLC_VMID__SHIFT 0x0 +#define RLC_GPM_VMID_THREAD0__RESERVED0_MASK 0xf0 +#define RLC_GPM_VMID_THREAD0__RESERVED0__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID_MASK 0x700 +#define RLC_GPM_VMID_THREAD0__RLC_QUEUEID__SHIFT 0x8 +#define RLC_GPM_VMID_THREAD0__RESERVED1_MASK 0xfffff800 +#define RLC_GPM_VMID_THREAD0__RESERVED1__SHIFT 0xb +#define RLC_GPM_VMID_THREAD1__RLC_VMID_MASK 0xf +#define RLC_GPM_VMID_THREAD1__RLC_VMID__SHIFT 0x0 +#define RLC_GPM_VMID_THREAD1__RESERVED0_MASK 0xf0 +#define RLC_GPM_VMID_THREAD1__RESERVED0__SHIFT 0x4 +#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID_MASK 0x700 +#define RLC_GPM_VMID_THREAD1__RLC_QUEUEID__SHIFT 0x8 +#define RLC_GPM_VMID_THREAD1__RESERVED1_MASK 0xfffff800 +#define RLC_GPM_VMID_THREAD1__RESERVED1__SHIFT 0xb +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE_MASK 0xffffffff +#define RLC_CGTT_MGCG_OVERRIDE__OVERRIDE__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK 0x1 +#define RLC_CGCG_CGLS_CTRL__CGCG_EN__SHIFT 0x0 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 +#define RLC_CGCG_CGLS_CTRL__CGLS_EN__SHIFT 0x1 +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK 0xfc +#define RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT 0x2 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 +#define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT 0x8 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER_MASK 0x8000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_CONTROLLER__SHIFT 0x1b +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL_MASK 0x10000000 +#define RLC_CGCG_CGLS_CTRL__CGCG_REG_CTRL__SHIFT 0x1c +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE_MASK 0x60000000 +#define RLC_CGCG_CGLS_CTRL__SLEEP_MODE__SHIFT 0x1d +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN_MASK 0x80000000 +#define RLC_CGCG_CGLS_CTRL__SIM_SILICON_EN__SHIFT 0x1f +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT_MASK 0xf +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_START_UNIT__SHIFT 0x0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT_MASK 0xf0 +#define RLC_CGCG_RAMP_CTRL__DOWN_DIV_STEP_UNIT__SHIFT 0x4 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT_MASK 0xf00 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_START_UNIT__SHIFT 0x8 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT_MASK 0xf000 +#define RLC_CGCG_RAMP_CTRL__UP_DIV_STEP_UNIT__SHIFT 0xc +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT_MASK 0xfff0000 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_CNT__SHIFT 0x10 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT_MASK 0xf0000000 +#define RLC_CGCG_RAMP_CTRL__STEP_DELAY_UNIT__SHIFT 0x1c +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff +#define RLC_DYN_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK_MASK 0xffffffff +#define RLC_DYN_PG_REQUEST__PG_REQUEST_CU_MASK__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_UP_DELAY_MASK 0xff +#define RLC_PG_DELAY__POWER_UP_DELAY__SHIFT 0x0 +#define RLC_PG_DELAY__POWER_DOWN_DELAY_MASK 0xff00 +#define RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT 0x8 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY_MASK 0xff0000 +#define RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT 0x10 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY_MASK 0xff000000 +#define RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT 0x18 +#define RLC_CU_STATUS__WORK_PENDING_MASK 0xffffffff +#define RLC_CU_STATUS__WORK_PENDING__SHIFT 0x0 +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK_MASK 0xffffffff +#define RLC_LB_INIT_CU_MASK__INIT_CU_MASK__SHIFT 0x0 +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK_MASK 0xffffffff +#define RLC_LB_ALWAYS_ACTIVE_CU_MASK__ALWAYS_ACTIVE_CU_MASK__SHIFT 0x0 +#define RLC_LB_PARAMS__SKIP_L2_CHECK_MASK 0x1 +#define RLC_LB_PARAMS__SKIP_L2_CHECK__SHIFT 0x0 +#define RLC_LB_PARAMS__FIFO_SAMPLES_MASK 0xfe +#define RLC_LB_PARAMS__FIFO_SAMPLES__SHIFT 0x1 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES_MASK 0xff00 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLES__SHIFT 0x8 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL_MASK 0xffff0000 +#define RLC_LB_PARAMS__PG_IDLE_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY_MASK 0xff +#define RLC_THREAD1_DELAY__CU_IDEL_DELAY__SHIFT 0x0 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY_MASK 0xff00 +#define RLC_THREAD1_DELAY__LBPW_INNER_LOOP_DELAY__SHIFT 0x8 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY_MASK 0xff0000 +#define RLC_THREAD1_DELAY__LBPW_OUTER_LOOP_DELAY__SHIFT 0x10 +#define RLC_THREAD1_DELAY__SPARE_MASK 0xff000000 +#define RLC_THREAD1_DELAY__SPARE__SHIFT 0x18 +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK_MASK 0xffffffff +#define RLC_PG_ALWAYS_ON_CU_MASK__AON_CU_MASK__SHIFT 0x0 +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK 0xff +#define RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT 0x0 +#define RLC_MAX_PG_CU__SPARE_MASK 0xffffff00 +#define RLC_MAX_PG_CU__SPARE__SHIFT 0x8 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN_MASK 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_PG_EN__SHIFT 0x0 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN_MASK 0x2 +#define RLC_AUTO_PG_CTRL__AUTO_GRBM_REG_SAVE_ON_IDLE_EN__SHIFT 0x1 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN_MASK 0x4 +#define RLC_AUTO_PG_CTRL__AUTO_WAKE_UP_EN__SHIFT 0x2 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK 0x7fff8 +#define RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT 0x3 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK 0xfff80000 +#define RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD__SHIFT 0x13 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE_MASK 0x1 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__START_GRBM_REG_SAVE__SHIFT 0x0 +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE_MASK 0xfffffffe +#define RLC_SMU_GRBM_REG_SAVE_CTRL__SPARE__SHIFT 0x1 +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID_MASK 0xf +#define RLC_SERDES_RD_MASTER_INDEX__CU_ID__SHIFT 0x0 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID_MASK 0x30 +#define RLC_SERDES_RD_MASTER_INDEX__SH_ID__SHIFT 0x4 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID_MASK 0x1c0 +#define RLC_SERDES_RD_MASTER_INDEX__SE_ID__SHIFT 0x6 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID_MASK 0x200 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_ID__SHIFT 0x9 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU_MASK 0x400 +#define RLC_SERDES_RD_MASTER_INDEX__SE_NONCU__SHIFT 0xa +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE_MASK 0x7800 +#define RLC_SERDES_RD_MASTER_INDEX__NON_SE__SHIFT 0xb +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID_MASK 0x18000 +#define RLC_SERDES_RD_MASTER_INDEX__DATA_REG_ID__SHIFT 0xf +#define RLC_SERDES_RD_MASTER_INDEX__SPARE_MASK 0xfffe0000 +#define RLC_SERDES_RD_MASTER_INDEX__SPARE__SHIFT 0x11 +#define RLC_SERDES_RD_DATA_0__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_0__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_1__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_1__DATA__SHIFT 0x0 +#define RLC_SERDES_RD_DATA_2__DATA_MASK 0xffffffff +#define RLC_SERDES_RD_DATA_2__DATA__SHIFT 0x0 +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK_MASK 0xffffffff +#define RLC_SERDES_WR_CU_MASTER_MASK__MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK_MASK 0xffff +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SE_MASTER_MASK__SHIFT 0x0 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK_MASK 0x10000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_MASTER_MASK__SHIFT 0x10 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK_MASK 0x20000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__GC_GFX_MASTER_MASK__SHIFT 0x11 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK_MASK 0x40000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC0_MASTER_MASK__SHIFT 0x12 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK_MASK 0x80000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__TC1_MASTER_MASK__SHIFT 0x13 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK_MASK 0x100000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE0_MASTER_MASK__SHIFT 0x14 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK_MASK 0x200000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE1_MASTER_MASK__SHIFT 0x15 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK_MASK 0x400000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE2_MASTER_MASK__SHIFT 0x16 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK_MASK 0x800000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__SPARE3_MASTER_MASK__SHIFT 0x17 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED_MASK 0xff000000 +#define RLC_SERDES_WR_NONCU_MASTER_MASK__RESERVED__SHIFT 0x18 +#define RLC_SERDES_WR_CTRL__BPM_ADDR_MASK 0xff +#define RLC_SERDES_WR_CTRL__BPM_ADDR__SHIFT 0x0 +#define RLC_SERDES_WR_CTRL__POWER_DOWN_MASK 0x100 +#define RLC_SERDES_WR_CTRL__POWER_DOWN__SHIFT 0x8 +#define RLC_SERDES_WR_CTRL__POWER_UP_MASK 0x200 +#define RLC_SERDES_WR_CTRL__POWER_UP__SHIFT 0x9 +#define RLC_SERDES_WR_CTRL__P1_SELECT_MASK 0x400 +#define RLC_SERDES_WR_CTRL__P1_SELECT__SHIFT 0xa +#define RLC_SERDES_WR_CTRL__P2_SELECT_MASK 0x800 +#define RLC_SERDES_WR_CTRL__P2_SELECT__SHIFT 0xb +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND_MASK 0x1000 +#define RLC_SERDES_WR_CTRL__WRITE_COMMAND__SHIFT 0xc +#define RLC_SERDES_WR_CTRL__READ_COMMAND_MASK 0x2000 +#define RLC_SERDES_WR_CTRL__READ_COMMAND__SHIFT 0xd +#define RLC_SERDES_WR_CTRL__RDDATA_RESET_MASK 0x4000 +#define RLC_SERDES_WR_CTRL__RDDATA_RESET__SHIFT 0xe +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT_MASK 0x8000 +#define RLC_SERDES_WR_CTRL__SHORT_FORMAT__SHIFT 0xf +#define RLC_SERDES_WR_CTRL__BPM_DATA_MASK 0x3ff0000 +#define RLC_SERDES_WR_CTRL__BPM_DATA__SHIFT 0x10 +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE_MASK 0x4000000 +#define RLC_SERDES_WR_CTRL__SRBM_OVERRIDE__SHIFT 0x1a +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR_MASK 0x8000000 +#define RLC_SERDES_WR_CTRL__RSVD_BPM_ADDR__SHIFT 0x1b +#define RLC_SERDES_WR_CTRL__REG_ADDR_MASK 0xf0000000 +#define RLC_SERDES_WR_CTRL__REG_ADDR__SHIFT 0x1c +#define RLC_SERDES_WR_DATA__DATA_MASK 0xffffffff +#define RLC_SERDES_WR_DATA__DATA__SHIFT 0x0 +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY_MASK 0xffffffff +#define RLC_SERDES_CU_MASTER_BUSY__BUSY_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK 0xffff +#define RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY__SHIFT 0x0 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK 0x10000 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY__SHIFT 0x10 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY_MASK 0x20000 +#define RLC_SERDES_NONCU_MASTER_BUSY__GC_GFX_MASTER_BUSY__SHIFT 0x11 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK 0x40000 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY__SHIFT 0x12 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK 0x80000 +#define RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY__SHIFT 0x13 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY_MASK 0x100000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE0_MASTER_BUSY__SHIFT 0x14 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY_MASK 0x200000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE1_MASTER_BUSY__SHIFT 0x15 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY_MASK 0x400000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE2_MASTER_BUSY__SHIFT 0x16 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY_MASK 0x800000 +#define RLC_SERDES_NONCU_MASTER_BUSY__SPARE3_MASTER_BUSY__SHIFT 0x17 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED_MASK 0xff000000 +#define RLC_SERDES_NONCU_MASTER_BUSY__RESERVED__SHIFT 0x18 +#define RLC_GPM_GENERAL_0__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_0__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_1__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_1__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_2__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_2__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_3__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_3__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_4__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_4__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_5__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_5__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_6__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_6__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_7__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_7__DATA__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__ADDR_MASK 0x1ff +#define RLC_GPM_SCRATCH_ADDR__ADDR__SHIFT 0x0 +#define RLC_GPM_SCRATCH_ADDR__RESERVED_MASK 0xfffffe00 +#define RLC_GPM_SCRATCH_ADDR__RESERVED__SHIFT 0x9 +#define RLC_GPM_SCRATCH_DATA__DATA_MASK 0xffffffff +#define RLC_GPM_SCRATCH_DATA__DATA__SHIFT 0x0 +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK_MASK 0xffffffff +#define RLC_STATIC_PG_STATUS__PG_STATUS_CU_MASK__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL_MASK 0xf +#define RLC_GPM_PERF_COUNT_0__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX_MASK 0xf0 +#define RLC_GPM_PERF_COUNT_0__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX_MASK 0xf00 +#define RLC_GPM_PERF_COUNT_0__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX_MASK 0xf000 +#define RLC_GPM_PERF_COUNT_0__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL_MASK 0x30000 +#define RLC_GPM_PERF_COUNT_0__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_0__UNUSED_MASK 0xc0000 +#define RLC_GPM_PERF_COUNT_0__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_0__ENABLE_MASK 0x100000 +#define RLC_GPM_PERF_COUNT_0__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_0__RESERVED_MASK 0xffe00000 +#define RLC_GPM_PERF_COUNT_0__RESERVED__SHIFT 0x15 +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL_MASK 0xf +#define RLC_GPM_PERF_COUNT_1__FEATURE_SEL__SHIFT 0x0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX_MASK 0xf0 +#define RLC_GPM_PERF_COUNT_1__SE_INDEX__SHIFT 0x4 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX_MASK 0xf00 +#define RLC_GPM_PERF_COUNT_1__SH_INDEX__SHIFT 0x8 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX_MASK 0xf000 +#define RLC_GPM_PERF_COUNT_1__CU_INDEX__SHIFT 0xc +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL_MASK 0x30000 +#define RLC_GPM_PERF_COUNT_1__EVENT_SEL__SHIFT 0x10 +#define RLC_GPM_PERF_COUNT_1__UNUSED_MASK 0xc0000 +#define RLC_GPM_PERF_COUNT_1__UNUSED__SHIFT 0x12 +#define RLC_GPM_PERF_COUNT_1__ENABLE_MASK 0x100000 +#define RLC_GPM_PERF_COUNT_1__ENABLE__SHIFT 0x14 +#define RLC_GPM_PERF_COUNT_1__RESERVED_MASK 0xffe00000 +#define RLC_GPM_PERF_COUNT_1__RESERVED__SHIFT 0x15 +#define RLC_GPR_REG1__DATA_MASK 0xffffffff +#define RLC_GPR_REG1__DATA__SHIFT 0x0 +#define RLC_GPR_REG2__DATA_MASK 0xffffffff +#define RLC_GPR_REG2__DATA__SHIFT 0x0 +#define RLC_MGCG_CTRL__MGCG_EN_MASK 0x1 +#define RLC_MGCG_CTRL__MGCG_EN__SHIFT 0x0 +#define RLC_MGCG_CTRL__SILICON_EN_MASK 0x2 +#define RLC_MGCG_CTRL__SILICON_EN__SHIFT 0x1 +#define RLC_MGCG_CTRL__SIMULATION_EN_MASK 0x4 +#define RLC_MGCG_CTRL__SIMULATION_EN__SHIFT 0x2 +#define RLC_MGCG_CTRL__ON_DELAY_MASK 0x78 +#define RLC_MGCG_CTRL__ON_DELAY__SHIFT 0x3 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS_MASK 0x7f80 +#define RLC_MGCG_CTRL__OFF_HYSTERESIS__SHIFT 0x7 +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL_MASK 0x8000 +#define RLC_MGCG_CTRL__GC_CAC_MGCG_CLK_CNTL__SHIFT 0xf +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL_MASK 0x10000 +#define RLC_MGCG_CTRL__SE_CAC_MGCG_CLK_CNTL__SHIFT 0x10 +#define RLC_MGCG_CTRL__SPARE_MASK 0xfffe0000 +#define RLC_MGCG_CTRL__SPARE__SHIFT 0x11 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET_MASK 0x1 +#define RLC_GPM_THREAD_RESET__THREAD0_RESET__SHIFT 0x0 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET_MASK 0x2 +#define RLC_GPM_THREAD_RESET__THREAD1_RESET__SHIFT 0x1 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET_MASK 0x4 +#define RLC_GPM_THREAD_RESET__THREAD2_RESET__SHIFT 0x2 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET_MASK 0x8 +#define RLC_GPM_THREAD_RESET__THREAD3_RESET__SHIFT 0x3 +#define RLC_GPM_THREAD_RESET__RESERVED_MASK 0xfffffff0 +#define RLC_GPM_THREAD_RESET__RESERVED__SHIFT 0x4 +#define RLC_SPM_VMID__RLC_SPM_VMID_MASK 0xf +#define RLC_SPM_VMID__RLC_SPM_VMID__SHIFT 0x0 +#define RLC_SPM_VMID__RESERVED_MASK 0xfffffff0 +#define RLC_SPM_VMID__RESERVED__SHIFT 0x4 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL_MASK 0x1 +#define RLC_SPM_INT_CNTL__RLC_SPM_INT_CNTL__SHIFT 0x0 +#define RLC_SPM_INT_CNTL__RESERVED_MASK 0xfffffffe +#define RLC_SPM_INT_CNTL__RESERVED__SHIFT 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS_MASK 0x1 +#define RLC_SPM_INT_STATUS__RLC_SPM_INT_STATUS__SHIFT 0x0 +#define RLC_SPM_INT_STATUS__RESERVED_MASK 0xfffffffe +#define RLC_SPM_INT_STATUS__RESERVED__SHIFT 0x1 +#define RLC_SPM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_SPM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_SPM_DEBUG_SELECT__RESERVED_MASK 0x7f00 +#define RLC_SPM_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE_MASK 0x8000 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_DEBUG_MODE__SHIFT 0xf +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE_MASK 0xffff0000 +#define RLC_SPM_DEBUG_SELECT__RLC_SPM_NUM_SAMPLE__SHIFT 0x10 +#define RLC_SPM_DEBUG__DATA_MASK 0xffffffff +#define RLC_SPM_DEBUG__DATA__SHIFT 0x0 +#define RLC_SMU_MESSAGE__CMD_MASK 0xffffffff +#define RLC_SMU_MESSAGE__CMD__SHIFT 0x0 +#define RLC_GPM_LOG_SIZE__SIZE_MASK 0xffffffff +#define RLC_GPM_LOG_SIZE__SIZE__SHIFT 0x0 +#define RLC_GPM_LOG_CONT__CONT_MASK 0xffffffff +#define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff +#define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 +#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00 +#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 +#define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff +#define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff +#define RLC_GPM_INT_DISABLE_TH1__DISABLE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH0__FORCE_MASK 0xffffffff +#define RLC_GPM_INT_FORCE_TH0__FORCE__SHIFT 0x0 +#define RLC_GPM_INT_FORCE_TH1__FORCE_MASK 0xffffffff +#define RLC_GPM_INT_FORCE_TH1__FORCE__SHIFT 0x0 +#define RLC_SRM_CNTL__SRM_ENABLE_MASK 0x1 +#define RLC_SRM_CNTL__SRM_ENABLE__SHIFT 0x0 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK 0x2 +#define RLC_SRM_CNTL__AUTO_INCR_ADDR__SHIFT 0x1 +#define RLC_SRM_CNTL__RESERVED_MASK 0xfffffffc +#define RLC_SRM_CNTL__RESERVED__SHIFT 0x2 +#define RLC_SRM_DEBUG_SELECT__SELECT_MASK 0xff +#define RLC_SRM_DEBUG_SELECT__SELECT__SHIFT 0x0 +#define RLC_SRM_DEBUG_SELECT__RESERVED_MASK 0xffffff00 +#define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8 +#define RLC_SRM_DEBUG__DATA_MASK 0xffffffff +#define RLC_SRM_DEBUG__DATA__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff +#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00 +#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa +#define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff +#define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff +#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 +#define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00 +#define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa +#define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff +#define RLC_SRM_DRAM_DATA__DATA__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__OP_MASK 0x1 +#define RLC_SRM_GPM_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_MASK 0x2 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM_MASK 0x1c +#define RLC_SRM_GPM_COMMAND__INDEX_CNTL_NUM__SHIFT 0x2 +#define RLC_SRM_GPM_COMMAND__SIZE_MASK 0x1ffe0 +#define RLC_SRM_GPM_COMMAND__SIZE__SHIFT 0x5 +#define RLC_SRM_GPM_COMMAND__START_OFFSET_MASK 0x1ffe0000 +#define RLC_SRM_GPM_COMMAND__START_OFFSET__SHIFT 0x11 +#define RLC_SRM_GPM_COMMAND__RESERVED1_MASK 0x60000000 +#define RLC_SRM_GPM_COMMAND__RESERVED1__SHIFT 0x1d +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY_MASK 0x80000000 +#define RLC_SRM_GPM_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL_MASK 0x2 +#define RLC_SRM_GPM_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED_MASK 0xfffffffc +#define RLC_SRM_GPM_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_RLCV_COMMAND__OP_MASK 0x1 +#define RLC_SRM_RLCV_COMMAND__OP__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND__RESERVED_MASK 0xe +#define RLC_SRM_RLCV_COMMAND__RESERVED__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND__SIZE_MASK 0xfff0 +#define RLC_SRM_RLCV_COMMAND__SIZE__SHIFT 0x4 +#define RLC_SRM_RLCV_COMMAND__START_OFFSET_MASK 0xfff0000 +#define RLC_SRM_RLCV_COMMAND__START_OFFSET__SHIFT 0x10 +#define RLC_SRM_RLCV_COMMAND__RESERVED1_MASK 0x70000000 +#define RLC_SRM_RLCV_COMMAND__RESERVED1__SHIFT 0x1c +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY_MASK 0x80000000 +#define RLC_SRM_RLCV_COMMAND__DEST_MEMORY__SHIFT 0x1f +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY_MASK 0x1 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_EMPTY__SHIFT 0x0 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL_MASK 0x2 +#define RLC_SRM_RLCV_COMMAND_STATUS__FIFO_FULL__SHIFT 0x1 +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED_MASK 0xfffffffc +#define RLC_SRM_RLCV_COMMAND_STATUS__RESERVED__SHIFT 0x2 +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_0__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_0__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_1__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_1__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_2__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_2__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_3__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_3__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_4__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_4__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_5__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_5__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_6__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_6__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS_MASK 0xffff +#define RLC_SRM_INDEX_CNTL_ADDR_7__ADDRESS__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED_MASK 0xffff0000 +#define RLC_SRM_INDEX_CNTL_ADDR_7__RESERVED__SHIFT 0x10 +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_0__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_1__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_2__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_3__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_4__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_5__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_6__DATA__SHIFT 0x0 +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA_MASK 0xffffffff +#define RLC_SRM_INDEX_CNTL_DATA_7__DATA__SHIFT 0x0 +#define RLC_SRM_STAT__SRM_STATUS_MASK 0x1 +#define RLC_SRM_STAT__SRM_STATUS__SHIFT 0x0 +#define RLC_SRM_STAT__RESERVED_MASK 0xfffffffe +#define RLC_SRM_STAT__RESERVED__SHIFT 0x1 +#define RLC_SRM_GPM_ABORT__ABORT_MASK 0x1 +#define RLC_SRM_GPM_ABORT__ABORT__SHIFT 0x0 +#define RLC_SRM_GPM_ABORT__RESERVED_MASK 0xfffffffe +#define RLC_SRM_GPM_ABORT__RESERVED__SHIFT 0x1 +#define RLC_CSIB_ADDR_LO__ADDRESS_MASK 0xffffffff +#define RLC_CSIB_ADDR_LO__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_ADDR_HI__ADDRESS_MASK 0xffff +#define RLC_CSIB_ADDR_HI__ADDRESS__SHIFT 0x0 +#define RLC_CSIB_LENGTH__LENGTH_MASK 0xffffffff +#define RLC_CSIB_LENGTH__LENGTH__SHIFT 0x0 +#define RLC_CP_RESPONSE0__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE0__RESPONSE__SHIFT 0x0 +#define RLC_CP_RESPONSE1__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE1__RESPONSE__SHIFT 0x0 +#define RLC_CP_RESPONSE2__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE2__RESPONSE__SHIFT 0x0 +#define RLC_CP_RESPONSE3__RESPONSE_MASK 0xffffffff +#define RLC_CP_RESPONSE3__RESPONSE__SHIFT 0x0 +#define RLC_SMU_COMMAND__CMD_MASK 0xffffffff +#define RLC_SMU_COMMAND__CMD__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler0_MASK 0xff +#define RLC_CP_SCHEDULERS__scheduler0__SHIFT 0x0 +#define RLC_CP_SCHEDULERS__scheduler1_MASK 0xff00 +#define RLC_CP_SCHEDULERS__scheduler1__SHIFT 0x8 +#define RLC_CP_SCHEDULERS__scheduler2_MASK 0xff0000 +#define RLC_CP_SCHEDULERS__scheduler2__SHIFT 0x10 +#define RLC_CP_SCHEDULERS__scheduler3_MASK 0xff000000 +#define RLC_CP_SCHEDULERS__scheduler3__SHIFT 0x18 +#define RLC_SMU_ARGUMENT_1__ARG_MASK 0xffffffff +#define RLC_SMU_ARGUMENT_1__ARG__SHIFT 0x0 +#define RLC_SMU_ARGUMENT_2__ARG_MASK 0xffffffff +#define RLC_SMU_ARGUMENT_2__ARG__SHIFT 0x0 +#define RLC_GPM_GENERAL_8__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_8__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_9__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_9__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_10__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_10__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_11__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_11__DATA__SHIFT 0x0 +#define RLC_GPM_GENERAL_12__DATA_MASK 0xffffffff +#define RLC_GPM_GENERAL_12__DATA__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__RESERVED1_MASK 0xfff +#define RLC_SPM_PERFMON_CNTL__RESERVED1__SHIFT 0x0 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK 0x3000 +#define RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE__SHIFT 0xc +#define RLC_SPM_PERFMON_CNTL__RESERVED_MASK 0xc000 +#define RLC_SPM_PERFMON_CNTL__RESERVED__SHIFT 0xe +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL_MASK 0xffff0000 +#define RLC_SPM_PERFMON_CNTL__PERFMON_SAMPLE_INTERVAL__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO_MASK 0xffffffff +#define RLC_SPM_PERFMON_RING_BASE_LO__RING_BASE_LO__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI_MASK 0xffff +#define RLC_SPM_PERFMON_RING_BASE_HI__RING_BASE_HI__SHIFT 0x0 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED_MASK 0xffff0000 +#define RLC_SPM_PERFMON_RING_BASE_HI__RESERVED__SHIFT 0x10 +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE_MASK 0xffffffff +#define RLC_SPM_PERFMON_RING_SIZE__RING_BASE_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE_MASK 0xff +#define RLC_SPM_PERFMON_SEGMENT_SIZE__PERFMON_SEGMENT_SIZE__SHIFT 0x0 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1_MASK 0x700 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED1__SHIFT 0x8 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE_MASK 0xf800 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__GLOBAL_NUM_LINE__SHIFT 0xb +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE_MASK 0x1f0000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE0_NUM_LINE__SHIFT 0x10 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE_MASK 0x3e00000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE1_NUM_LINE__SHIFT 0x15 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE_MASK 0x7c000000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__SE2_NUM_LINE__SHIFT 0x1a +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED_MASK 0x80000000 +#define RLC_SPM_PERFMON_SEGMENT_SIZE__RESERVED__SHIFT 0x1f +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff +#define RLC_SPM_SE_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff +#define RLC_SPM_SE_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CPF_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_CB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_DB_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_PA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_GDS_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_IA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCC_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TCP_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TA_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_TD_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_VGT_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SPI_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SQG_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY_MASK 0xff +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__PERFMON_SAMPLE_DELAY__SHIFT 0x0 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED_MASK 0xffffff00 +#define RLC_SPM_SX_PERFMON_SAMPLE_DELAY__RESERVED__SHIFT 0x8 +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR_MASK 0xffffffff +#define RLC_SPM_GLOBAL_MUXSEL_ADDR__PERFMON_SEL_ADDR__SHIFT 0x0 +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA_MASK 0xffffffff +#define RLC_SPM_GLOBAL_MUXSEL_DATA__PERFMON_SEL_DATA__SHIFT 0x0 +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR_MASK 0xffffffff +#define RLC_SPM_RING_RDPTR__PERFMON_RING_RDPTR__SHIFT 0x0 +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD_MASK 0xffffffff +#define RLC_SPM_SEGMENT_THRESHOLD__NUM_SEGMENT_THRESHOLD__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE_MASK 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_ENABLE__SHIFT 0x0 +#define RLC_GPU_IOV_VF_ENABLE__RESERVED_MASK 0xfffe +#define RLC_GPU_IOV_VF_ENABLE__RESERVED__SHIFT 0x1 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM_MASK 0xffff0000 +#define RLC_GPU_IOV_VF_ENABLE__VF_NUM__SHIFT 0x10 +#define RLC_GPU_IOV_RLC_RESPONSE__RESP_MASK 0xffffffff +#define RLC_GPU_IOV_RLC_RESPONSE__RESP__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID_MASK 0xf +#define RLC_GPU_IOV_ACTIVE_FCN_ID__VF_ID__SHIFT 0x0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED_MASK 0x7ffffff0 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__RESERVED__SHIFT 0x4 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF_MASK 0x80000000 +#define RLC_GPU_IOV_ACTIVE_FCN_ID__PF_VF__SHIFT 0x1f +#define SPI_PS_INPUT_CNTL_0__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_0__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_0__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_0__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_0__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_0__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_0__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_0__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_0__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_0__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_0__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_0__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_1__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_1__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_1__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_1__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_1__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_1__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_1__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_1__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_1__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_1__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_1__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_1__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_2__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_2__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_2__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_2__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_2__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_2__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_2__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_2__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_2__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_2__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_2__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_2__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_3__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_3__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_3__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_3__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_3__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_3__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_3__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_3__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_3__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_3__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_3__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_3__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_4__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_4__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_4__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_4__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_4__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_4__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_4__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_4__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_4__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_4__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_4__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_4__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_5__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_5__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_5__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_5__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_5__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_5__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_5__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_5__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_5__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_5__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_5__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_5__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_6__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_6__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_6__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_6__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_6__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_6__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_6__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_6__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_6__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_6__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_6__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_6__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_7__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_7__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_7__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_7__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_7__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_7__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_7__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_7__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_7__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_7__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_7__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_7__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_8__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_8__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_8__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_8__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_8__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_8__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_8__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_8__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_8__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_8__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_8__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_8__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_9__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_9__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_9__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_9__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_9__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_9__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_9__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_9__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_9__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_9__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_9__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_9__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_10__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_10__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_10__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_10__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_10__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_10__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_10__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_10__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_10__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_10__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_10__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_10__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_11__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_11__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_11__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_11__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_11__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_11__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_11__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_11__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_11__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_11__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_11__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_11__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_12__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_12__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_12__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_12__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_12__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_12__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_12__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_12__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_12__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_12__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_12__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_12__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_13__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_13__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_13__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_13__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_13__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_13__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_13__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_13__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_13__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_13__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_13__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_13__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_14__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_14__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_14__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_14__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_14__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_14__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_14__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_14__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_14__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_14__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_14__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_14__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_15__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_15__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_15__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_15__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_15__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_15__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_15__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_15__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_15__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_15__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_15__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_15__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_16__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_16__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_16__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_16__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_16__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_16__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_16__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_16__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_16__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_16__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_16__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_16__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_17__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_17__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_17__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_17__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_17__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_17__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_17__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_17__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_17__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_17__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_17__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_17__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_18__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_18__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_18__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_18__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_18__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_18__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_18__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_18__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_18__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_18__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_18__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_18__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_19__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_19__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_19__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP_MASK 0x1e000 +#define SPI_PS_INPUT_CNTL_19__CYL_WRAP__SHIFT 0xd +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_MASK 0x20000 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX__SHIFT 0x11 +#define SPI_PS_INPUT_CNTL_19__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_19__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_19__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_19__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_19__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1_MASK 0x800000 +#define SPI_PS_INPUT_CNTL_19__PT_SPRITE_TEX_ATTR1__SHIFT 0x17 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_19__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_19__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_20__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_20__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_20__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_20__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_20__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_20__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_20__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_20__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_20__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_20__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_21__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_21__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_21__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_21__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_21__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_21__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_21__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_21__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_21__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_21__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_22__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_22__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_22__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_22__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_22__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_22__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_22__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_22__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_22__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_22__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_23__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_23__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_23__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_23__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_23__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_23__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_23__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_23__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_23__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_23__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_24__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_24__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_24__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_24__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_24__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_24__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_24__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_24__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_24__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_24__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_25__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_25__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_25__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_25__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_25__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_25__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_25__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_25__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_25__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_25__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_26__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_26__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_26__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_26__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_26__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_26__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_26__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_26__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_26__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_26__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_27__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_27__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_27__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_27__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_27__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_27__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_27__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_27__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_27__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_27__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_28__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_28__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_28__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_28__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_28__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_28__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_28__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_28__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_28__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_28__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_29__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_29__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_29__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_29__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_29__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_29__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_29__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_29__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_29__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_29__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_30__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_30__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_30__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_30__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_30__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_30__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_30__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_30__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_30__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_30__ATTR1_VALID__SHIFT 0x19 +#define SPI_PS_INPUT_CNTL_31__OFFSET_MASK 0x3f +#define SPI_PS_INPUT_CNTL_31__OFFSET__SHIFT 0x0 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_MASK 0x300 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL__SHIFT 0x8 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE_MASK 0x400 +#define SPI_PS_INPUT_CNTL_31__FLAT_SHADE__SHIFT 0xa +#define SPI_PS_INPUT_CNTL_31__DUP_MASK 0x40000 +#define SPI_PS_INPUT_CNTL_31__DUP__SHIFT 0x12 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE_MASK 0x80000 +#define SPI_PS_INPUT_CNTL_31__FP16_INTERP_MODE__SHIFT 0x13 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1_MASK 0x100000 +#define SPI_PS_INPUT_CNTL_31__USE_DEFAULT_ATTR1__SHIFT 0x14 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1_MASK 0x600000 +#define SPI_PS_INPUT_CNTL_31__DEFAULT_VAL_ATTR1__SHIFT 0x15 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID_MASK 0x1000000 +#define SPI_PS_INPUT_CNTL_31__ATTR0_VALID__SHIFT 0x18 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID_MASK 0x2000000 +#define SPI_PS_INPUT_CNTL_31__ATTR1_VALID__SHIFT 0x19 +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT_MASK 0x3e +#define SPI_VS_OUT_CONFIG__VS_EXPORT_COUNT__SHIFT 0x1 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK_MASK 0x40 +#define SPI_VS_OUT_CONFIG__VS_HALF_PACK__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA_MASK 0x1 +#define SPI_PS_INPUT_ENA__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA_MASK 0x2 +#define SPI_PS_INPUT_ENA__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA_MASK 0x4 +#define SPI_PS_INPUT_ENA__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA_MASK 0x8 +#define SPI_PS_INPUT_ENA__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA_MASK 0x10 +#define SPI_PS_INPUT_ENA__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA_MASK 0x20 +#define SPI_PS_INPUT_ENA__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA_MASK 0x40 +#define SPI_PS_INPUT_ENA__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA_MASK 0x80 +#define SPI_PS_INPUT_ENA__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA_MASK 0x100 +#define SPI_PS_INPUT_ENA__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA_MASK 0x200 +#define SPI_PS_INPUT_ENA__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA_MASK 0x400 +#define SPI_PS_INPUT_ENA__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA_MASK 0x800 +#define SPI_PS_INPUT_ENA__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA_MASK 0x1000 +#define SPI_PS_INPUT_ENA__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA_MASK 0x2000 +#define SPI_PS_INPUT_ENA__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA_MASK 0x4000 +#define SPI_PS_INPUT_ENA__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA_MASK 0x8000 +#define SPI_PS_INPUT_ENA__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA_MASK 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_SAMPLE_ENA__SHIFT 0x0 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA_MASK 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_CENTER_ENA__SHIFT 0x1 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA_MASK 0x4 +#define SPI_PS_INPUT_ADDR__PERSP_CENTROID_ENA__SHIFT 0x2 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA_MASK 0x8 +#define SPI_PS_INPUT_ADDR__PERSP_PULL_MODEL_ENA__SHIFT 0x3 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA_MASK 0x10 +#define SPI_PS_INPUT_ADDR__LINEAR_SAMPLE_ENA__SHIFT 0x4 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA_MASK 0x20 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTER_ENA__SHIFT 0x5 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA_MASK 0x40 +#define SPI_PS_INPUT_ADDR__LINEAR_CENTROID_ENA__SHIFT 0x6 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA_MASK 0x80 +#define SPI_PS_INPUT_ADDR__LINE_STIPPLE_TEX_ENA__SHIFT 0x7 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA_MASK 0x100 +#define SPI_PS_INPUT_ADDR__POS_X_FLOAT_ENA__SHIFT 0x8 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA_MASK 0x200 +#define SPI_PS_INPUT_ADDR__POS_Y_FLOAT_ENA__SHIFT 0x9 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA_MASK 0x400 +#define SPI_PS_INPUT_ADDR__POS_Z_FLOAT_ENA__SHIFT 0xa +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA_MASK 0x800 +#define SPI_PS_INPUT_ADDR__POS_W_FLOAT_ENA__SHIFT 0xb +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA_MASK 0x1000 +#define SPI_PS_INPUT_ADDR__FRONT_FACE_ENA__SHIFT 0xc +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA_MASK 0x2000 +#define SPI_PS_INPUT_ADDR__ANCILLARY_ENA__SHIFT 0xd +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA_MASK 0x4000 +#define SPI_PS_INPUT_ADDR__SAMPLE_COVERAGE_ENA__SHIFT 0xe +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA_MASK 0x8000 +#define SPI_PS_INPUT_ADDR__POS_FIXED_PT_ENA__SHIFT 0xf +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA_MASK 0x1 +#define SPI_INTERP_CONTROL_0__FLAT_SHADE_ENA__SHIFT 0x0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA_MASK 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_ENA__SHIFT 0x1 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X_MASK 0x1c +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_X__SHIFT 0x2 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y_MASK 0xe0 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Y__SHIFT 0x5 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z_MASK 0x700 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_Z__SHIFT 0x8 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W_MASK 0x3800 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_OVRD_W__SHIFT 0xb +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1_MASK 0x4000 +#define SPI_INTERP_CONTROL_0__PNT_SPRITE_TOP_1__SHIFT 0xe +#define SPI_PS_IN_CONTROL__NUM_INTERP_MASK 0x3f +#define SPI_PS_IN_CONTROL__NUM_INTERP__SHIFT 0x0 +#define SPI_PS_IN_CONTROL__PARAM_GEN_MASK 0x40 +#define SPI_PS_IN_CONTROL__PARAM_GEN__SHIFT 0x6 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE_MASK 0x4000 +#define SPI_PS_IN_CONTROL__BC_OPTIMIZE_DISABLE__SHIFT 0xe +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL_MASK 0x1 +#define SPI_BARYC_CNTL__PERSP_CENTER_CNTL__SHIFT 0x0 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL_MASK 0x10 +#define SPI_BARYC_CNTL__PERSP_CENTROID_CNTL__SHIFT 0x4 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL_MASK 0x100 +#define SPI_BARYC_CNTL__LINEAR_CENTER_CNTL__SHIFT 0x8 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL_MASK 0x1000 +#define SPI_BARYC_CNTL__LINEAR_CENTROID_CNTL__SHIFT 0xc +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION_MASK 0x30000 +#define SPI_BARYC_CNTL__POS_FLOAT_LOCATION__SHIFT 0x10 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC_MASK 0x100000 +#define SPI_BARYC_CNTL__POS_FLOAT_ULC__SHIFT 0x14 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS_MASK 0x1000000 +#define SPI_BARYC_CNTL__FRONT_FACE_ALL_BITS__SHIFT 0x18 +#define SPI_TMPRING_SIZE__WAVES_MASK 0xfff +#define SPI_TMPRING_SIZE__WAVES__SHIFT 0x0 +#define SPI_TMPRING_SIZE__WAVESIZE_MASK 0x1fff000 +#define SPI_TMPRING_SIZE__WAVESIZE__SHIFT 0xc +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_POS_FORMAT__POS0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT_MASK 0xf0 +#define SPI_SHADER_POS_FORMAT__POS1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT_MASK 0xf00 +#define SPI_SHADER_POS_FORMAT__POS2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT_MASK 0xf000 +#define SPI_SHADER_POS_FORMAT__POS3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_Z_FORMAT__Z_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT_MASK 0xf +#define SPI_SHADER_COL_FORMAT__COL0_EXPORT_FORMAT__SHIFT 0x0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT_MASK 0xf0 +#define SPI_SHADER_COL_FORMAT__COL1_EXPORT_FORMAT__SHIFT 0x4 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT_MASK 0xf00 +#define SPI_SHADER_COL_FORMAT__COL2_EXPORT_FORMAT__SHIFT 0x8 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT_MASK 0xf000 +#define SPI_SHADER_COL_FORMAT__COL3_EXPORT_FORMAT__SHIFT 0xc +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT_MASK 0xf0000 +#define SPI_SHADER_COL_FORMAT__COL4_EXPORT_FORMAT__SHIFT 0x10 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT_MASK 0xf00000 +#define SPI_SHADER_COL_FORMAT__COL5_EXPORT_FORMAT__SHIFT 0x14 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT_MASK 0xf000000 +#define SPI_SHADER_COL_FORMAT__COL6_EXPORT_FORMAT__SHIFT 0x18 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT_MASK 0xf0000000 +#define SPI_SHADER_COL_FORMAT__COL7_EXPORT_FORMAT__SHIFT 0x1c +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0_MASK 0x7 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS0__SHIFT 0x0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1_MASK 0x38 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS1__SHIFT 0x3 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2_MASK 0x1c0 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS2__SHIFT 0x6 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3_MASK 0xe00 +#define SPI_ARB_PRIORITY__PIPE_ORDER_TS3__SHIFT 0x9 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT_MASK 0x3000 +#define SPI_ARB_PRIORITY__TS0_DUR_MULT__SHIFT 0xc +#define SPI_ARB_PRIORITY__TS1_DUR_MULT_MASK 0xc000 +#define SPI_ARB_PRIORITY__TS1_DUR_MULT__SHIFT 0xe +#define SPI_ARB_PRIORITY__TS2_DUR_MULT_MASK 0x30000 +#define SPI_ARB_PRIORITY__TS2_DUR_MULT__SHIFT 0x10 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT_MASK 0xc0000 +#define SPI_ARB_PRIORITY__TS3_DUR_MULT__SHIFT 0x12 +#define SPI_ARB_CYCLES_0__TS0_DURATION_MASK 0xffff +#define SPI_ARB_CYCLES_0__TS0_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_0__TS1_DURATION_MASK 0xffff0000 +#define SPI_ARB_CYCLES_0__TS1_DURATION__SHIFT 0x10 +#define SPI_ARB_CYCLES_1__TS2_DURATION_MASK 0xffff +#define SPI_ARB_CYCLES_1__TS2_DURATION__SHIFT 0x0 +#define SPI_ARB_CYCLES_1__TS3_DURATION_MASK 0xffff0000 +#define SPI_ARB_CYCLES_1__TS3_DURATION__SHIFT 0x10 +#define SPI_CDBG_SYS_GFX__PS_EN_MASK 0x1 +#define SPI_CDBG_SYS_GFX__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_GFX__VS_EN_MASK 0x2 +#define SPI_CDBG_SYS_GFX__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_GFX__GS_EN_MASK 0x4 +#define SPI_CDBG_SYS_GFX__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_GFX__ES_EN_MASK 0x8 +#define SPI_CDBG_SYS_GFX__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_GFX__HS_EN_MASK 0x10 +#define SPI_CDBG_SYS_GFX__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_GFX__LS_EN_MASK 0x20 +#define SPI_CDBG_SYS_GFX__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_GFX__CS_EN_MASK 0x40 +#define SPI_CDBG_SYS_GFX__CS_EN__SHIFT 0x6 +#define SPI_CDBG_SYS_HP3D__PS_EN_MASK 0x1 +#define SPI_CDBG_SYS_HP3D__PS_EN__SHIFT 0x0 +#define SPI_CDBG_SYS_HP3D__VS_EN_MASK 0x2 +#define SPI_CDBG_SYS_HP3D__VS_EN__SHIFT 0x1 +#define SPI_CDBG_SYS_HP3D__GS_EN_MASK 0x4 +#define SPI_CDBG_SYS_HP3D__GS_EN__SHIFT 0x2 +#define SPI_CDBG_SYS_HP3D__ES_EN_MASK 0x8 +#define SPI_CDBG_SYS_HP3D__ES_EN__SHIFT 0x3 +#define SPI_CDBG_SYS_HP3D__HS_EN_MASK 0x10 +#define SPI_CDBG_SYS_HP3D__HS_EN__SHIFT 0x4 +#define SPI_CDBG_SYS_HP3D__LS_EN_MASK 0x20 +#define SPI_CDBG_SYS_HP3D__LS_EN__SHIFT 0x5 +#define SPI_CDBG_SYS_CS0__PIPE0_MASK 0xff +#define SPI_CDBG_SYS_CS0__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS0__PIPE1_MASK 0xff00 +#define SPI_CDBG_SYS_CS0__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS0__PIPE2_MASK 0xff0000 +#define SPI_CDBG_SYS_CS0__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS0__PIPE3_MASK 0xff000000 +#define SPI_CDBG_SYS_CS0__PIPE3__SHIFT 0x18 +#define SPI_CDBG_SYS_CS1__PIPE0_MASK 0xff +#define SPI_CDBG_SYS_CS1__PIPE0__SHIFT 0x0 +#define SPI_CDBG_SYS_CS1__PIPE1_MASK 0xff00 +#define SPI_CDBG_SYS_CS1__PIPE1__SHIFT 0x8 +#define SPI_CDBG_SYS_CS1__PIPE2_MASK 0xff0000 +#define SPI_CDBG_SYS_CS1__PIPE2__SHIFT 0x10 +#define SPI_CDBG_SYS_CS1__PIPE3_MASK 0xff000000 +#define SPI_CDBG_SYS_CS1__PIPE3__SHIFT 0x18 +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_GFX__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE_MASK 0xf80 +#define SPI_WCL_PIPE_PERCENT_GFX__LS_GRP_VALUE__SHIFT 0x7 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE_MASK 0x1f000 +#define SPI_WCL_PIPE_PERCENT_GFX__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE_MASK 0x3e0000 +#define SPI_WCL_PIPE_PERCENT_GFX__ES_GRP_VALUE__SHIFT 0x11 +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE_MASK 0x7c00000 +#define SPI_WCL_PIPE_PERCENT_GFX__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_HP3D__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE_MASK 0xf80 +#define SPI_WCL_PIPE_PERCENT_HP3D__LS_GRP_VALUE__SHIFT 0x7 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE_MASK 0x1f000 +#define SPI_WCL_PIPE_PERCENT_HP3D__HS_GRP_VALUE__SHIFT 0xc +#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE_MASK 0x3e0000 +#define SPI_WCL_PIPE_PERCENT_HP3D__ES_GRP_VALUE__SHIFT 0x11 +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE_MASK 0x7c00000 +#define SPI_WCL_PIPE_PERCENT_HP3D__GS_GRP_VALUE__SHIFT 0x16 +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS0__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS1__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS2__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS3__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS4__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS5__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS6__VALUE__SHIFT 0x0 +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE_MASK 0x7f +#define SPI_WCL_PIPE_PERCENT_CS7__VALUE__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_RA_MASK 0x1 +#define SPI_GDBG_WAVE_CNTL__STALL_RA__SHIFT 0x0 +#define SPI_GDBG_WAVE_CNTL__STALL_VMID_MASK 0x1fffe +#define SPI_GDBG_WAVE_CNTL__STALL_VMID__SHIFT 0x1 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL_MASK 0x3 +#define SPI_GDBG_TRAP_CONFIG__ME_SEL__SHIFT 0x0 +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL_MASK 0xc +#define SPI_GDBG_TRAP_CONFIG__PIPE_SEL__SHIFT 0x2 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL_MASK 0x70 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_SEL__SHIFT 0x4 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH_MASK 0x80 +#define SPI_GDBG_TRAP_CONFIG__ME_MATCH__SHIFT 0x7 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH_MASK 0x100 +#define SPI_GDBG_TRAP_CONFIG__PIPE_MATCH__SHIFT 0x8 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH_MASK 0x200 +#define SPI_GDBG_TRAP_CONFIG__QUEUE_MATCH__SHIFT 0x9 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN_MASK 0x8000 +#define SPI_GDBG_TRAP_CONFIG__TRAP_EN__SHIFT 0xf +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL_MASK 0xffff0000 +#define SPI_GDBG_TRAP_CONFIG__VMID_SEL__SHIFT 0x10 +#define SPI_GDBG_TRAP_MASK__EXCP_EN_MASK 0x1ff +#define SPI_GDBG_TRAP_MASK__EXCP_EN__SHIFT 0x0 +#define SPI_GDBG_TRAP_MASK__REPLACE_MASK 0x200 +#define SPI_GDBG_TRAP_MASK__REPLACE__SHIFT 0x9 +#define SPI_GDBG_TBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_GDBG_TBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TBA_HI__MEM_BASE_MASK 0xff +#define SPI_GDBG_TBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_GDBG_TMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TMA_HI__MEM_BASE_MASK 0xff +#define SPI_GDBG_TMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA0__DATA_MASK 0xffffffff +#define SPI_GDBG_TRAP_DATA0__DATA__SHIFT 0x0 +#define SPI_GDBG_TRAP_DATA1__DATA_MASK 0xffffffff +#define SPI_GDBG_TRAP_DATA1__DATA__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_MASK 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET__SHIFT 0x0 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID_MASK 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PER_VMID__SHIFT 0x1 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID_MASK 0x4 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_ALL_VMID__SHIFT 0x2 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE_MASK 0x8 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_RESOURCE__SHIFT 0x3 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY_MASK 0x10 +#define SPI_RESET_DEBUG__DISABLE_GFX_RESET_PRIORITY__SHIFT 0x4 +#define SPI_COMPUTE_QUEUE_RESET__RESET_MASK 0x1 +#define SPI_COMPUTE_QUEUE_RESET__RESET__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_0__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_0__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_0__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_0__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_0__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_0__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_1__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_1__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_1__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_1__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_1__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_1__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_2__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_2__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_2__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_2__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_2__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_2__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_3__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_3__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_3__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_3__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_3__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_3__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_4__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_4__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_4__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_4__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_4__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_4__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_5__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_5__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_5__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_5__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_5__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_5__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_6__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_6__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_6__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_6__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_6__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_6__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_7__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_7__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_7__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_7__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_7__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_7__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_8__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_8__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_8__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_8__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_8__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_8__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_9__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_9__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_9__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_9__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_9__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_9__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_10__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_10__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_10__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_10__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_10__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_10__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_11__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_11__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_11__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_11__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_11__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_11__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_12__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_12__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_12__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_12__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_12__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_12__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_13__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_13__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_13__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_13__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_13__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_13__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_14__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_14__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_14__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_14__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_14__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_14__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR_MASK 0xf +#define SPI_RESOURCE_RESERVE_CU_15__VGPR__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR_MASK 0xf0 +#define SPI_RESOURCE_RESERVE_CU_15__SGPR__SHIFT 0x4 +#define SPI_RESOURCE_RESERVE_CU_15__LDS_MASK 0xf00 +#define SPI_RESOURCE_RESERVE_CU_15__LDS__SHIFT 0x8 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES_MASK 0x7000 +#define SPI_RESOURCE_RESERVE_CU_15__WAVES__SHIFT 0xc +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS_MASK 0x78000 +#define SPI_RESOURCE_RESERVE_CU_15__BARRIERS__SHIFT 0xf +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_0__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_0__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_0__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_1__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_1__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_1__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_2__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_2__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_2__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_3__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_3__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_3__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_4__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_4__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_4__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_5__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_5__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_5__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_6__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_6__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_6__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_7__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_7__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_7__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_8__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_8__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_8__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_9__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_9__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_9__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_10__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_10__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_10__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_11__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_11__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_11__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_12__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_12__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_12__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_13__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_13__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_13__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_14__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_14__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_14__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN_MASK 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__EN__SHIFT 0x0 +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK_MASK 0xfffe +#define SPI_RESOURCE_RESERVE_EN_CU_15__TYPE_MASK__SHIFT 0x1 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK_MASK 0xff0000 +#define SPI_RESOURCE_RESERVE_EN_CU_15__QUEUE_MASK__SHIFT 0x10 +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY_MASK 0x1000000 +#define SPI_RESOURCE_RESERVE_EN_CU_15__RESERVE_SPACE_ONLY__SHIFT 0x18 +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE_MASK 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__INITIATE__SHIFT 0x0 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN_MASK 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_INTERRUPT_EN__SHIFT 0x1 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN_MASK 0x4 +#define SPI_COMPUTE_WF_CTX_SAVE__DONE_INTERRUPT_EN__SHIFT 0x2 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY_MASK 0x40000000 +#define SPI_COMPUTE_WF_CTX_SAVE__GDS_REQ_BUSY__SHIFT 0x1e +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY_MASK 0x80000000 +#define SPI_COMPUTE_WF_CTX_SAVE__SAVE_BUSY__SHIFT 0x1f +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define SPI_PS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define SPI_START_PHASE__VGPR_START_PHASE_MASK 0x3 +#define SPI_START_PHASE__VGPR_START_PHASE__SHIFT 0x0 +#define SPI_START_PHASE__SGPR_START_PHASE_MASK 0xc +#define SPI_START_PHASE__SGPR_START_PHASE__SHIFT 0x2 +#define SPI_START_PHASE__WAVE_START_PHASE_MASK 0x30 +#define SPI_START_PHASE__WAVE_START_PHASE__SHIFT 0x4 +#define SPI_GFX_CNTL__RESET_COUNTS_MASK 0x1 +#define SPI_GFX_CNTL__RESET_COUNTS__SHIFT 0x0 +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY_MASK 0x1fffff +#define SPI_CONFIG_CNTL__GPR_WRITE_PRIORITY__SHIFT 0x0 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER_MASK 0xe00000 +#define SPI_CONFIG_CNTL__EXP_PRIORITY_ORDER__SHIFT 0x15 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS_MASK 0x1000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_TOP_EVENTS__SHIFT 0x18 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS_MASK 0x2000000 +#define SPI_CONFIG_CNTL__ENABLE_SQG_BOP_EVENTS__SHIFT 0x19 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET_MASK 0x4000000 +#define SPI_CONFIG_CNTL__RSRC_MGMT_RESET__SHIFT 0x1a +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL_MASK 0x8000000 +#define SPI_CONFIG_CNTL__TTRACE_STALL_ALL__SHIFT 0x1b +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE_MASK 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GRBM_OVERRIDE__SHIFT 0x0 +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL_MASK 0xe +#define SPI_DEBUG_CNTL__DEBUG_THREAD_TYPE_SEL__SHIFT 0x1 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL_MASK 0x3f0 +#define SPI_DEBUG_CNTL__DEBUG_GROUP_SEL__SHIFT 0x4 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL_MASK 0xfc00 +#define SPI_DEBUG_CNTL__DEBUG_SIMD_SEL__SHIFT 0xa +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL_MASK 0x10000 +#define SPI_DEBUG_CNTL__DEBUG_SH_SEL__SHIFT 0x10 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0_MASK 0x20000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_0__SHIFT 0x11 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1_MASK 0x40000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_1__SHIFT 0x12 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2_MASK 0x80000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_2__SHIFT 0x13 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3_MASK 0x100000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_3__SHIFT 0x14 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4_MASK 0x200000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_4__SHIFT 0x15 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5_MASK 0x400000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_5__SHIFT 0x16 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6_MASK 0x800000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_6__SHIFT 0x17 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7_MASK 0x1000000 +#define SPI_DEBUG_CNTL__SPI_ECO_SPARE_7__SHIFT 0x18 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL_MASK 0xe000000 +#define SPI_DEBUG_CNTL__DEBUG_PIPE_SEL__SHIFT 0x19 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN_MASK 0x80000000 +#define SPI_DEBUG_CNTL__DEBUG_REG_EN__SHIFT 0x1f +#define SPI_DEBUG_READ__DATA_MASK 0xffffff +#define SPI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0_MASK 0x1 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data0__SHIFT 0x0 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1_MASK 0x2 +#define SPI_DSM_CNTL__Sel_DSM_SPI_Irritator_data1__SHIFT 0x1 +#define SPI_DSM_CNTL__SPI_Enable_Single_Write_MASK 0x4 +#define SPI_DSM_CNTL__SPI_Enable_Single_Write__SHIFT 0x2 +#define SPI_DSM_CNTL__UNUSED_MASK 0xfffffff8 +#define SPI_DSM_CNTL__UNUSED__SHIFT 0x3 +#define SPI_EDC_CNT__SED_MASK 0xff +#define SPI_EDC_CNT__SED__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1_MASK 0xffc00 +#define SPI_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define SPI_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK 0x3ff +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT 0x0 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK 0xffc00 +#define SPI_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT 0xa +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0xff +#define SPI_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0xff +#define SPI_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MIN_MASK 0xf +#define SPI_PERFCOUNTER_BINS__BIN0_MIN__SHIFT 0x0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX_MASK 0xf0 +#define SPI_PERFCOUNTER_BINS__BIN0_MAX__SHIFT 0x4 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN_MASK 0xf00 +#define SPI_PERFCOUNTER_BINS__BIN1_MIN__SHIFT 0x8 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 +#define SPI_PERFCOUNTER_BINS__BIN1_MAX__SHIFT 0xc +#define SPI_PERFCOUNTER_BINS__BIN2_MIN_MASK 0xf0000 +#define SPI_PERFCOUNTER_BINS__BIN2_MIN__SHIFT 0x10 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX_MASK 0xf00000 +#define SPI_PERFCOUNTER_BINS__BIN2_MAX__SHIFT 0x14 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN_MASK 0xf000000 +#define SPI_PERFCOUNTER_BINS__BIN3_MIN__SHIFT 0x18 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX_MASK 0xf0000000 +#define SPI_PERFCOUNTER_BINS__BIN3_MAX__SHIFT 0x1c +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SPI_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SPI_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY_MASK 0xf +#define SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT 0x0 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW_MASK 0x10 +#define SPI_CONFIG_CNTL_1__INTERP_ONE_PRIM_PER_ROW__SHIFT 0x4 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE__SHIFT 0x6 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT_MASK 0x80 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_STRICT__SHIFT 0x7 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE_MASK 0x100 +#define SPI_CONFIG_CNTL_1__CRC_SIMD_ID_WADDR_DISABLE__SHIFT 0x8 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE_MASK 0x200 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_MODE__SHIFT 0x9 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT_MASK 0x3c00 +#define SPI_CONFIG_CNTL_1__LBPW_CU_CHK_CNT__SHIFT 0xa +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE_MASK 0xffff0000 +#define SPI_CONFIG_CNTL_1__PC_LIMIT_SIZE__SHIFT 0x10 +#define SPI_DEBUG_BUSY__LS_BUSY_MASK 0x1 +#define SPI_DEBUG_BUSY__LS_BUSY__SHIFT 0x0 +#define SPI_DEBUG_BUSY__HS_BUSY_MASK 0x2 +#define SPI_DEBUG_BUSY__HS_BUSY__SHIFT 0x1 +#define SPI_DEBUG_BUSY__ES_BUSY_MASK 0x4 +#define SPI_DEBUG_BUSY__ES_BUSY__SHIFT 0x2 +#define SPI_DEBUG_BUSY__GS_BUSY_MASK 0x8 +#define SPI_DEBUG_BUSY__GS_BUSY__SHIFT 0x3 +#define SPI_DEBUG_BUSY__VS_BUSY_MASK 0x10 +#define SPI_DEBUG_BUSY__VS_BUSY__SHIFT 0x4 +#define SPI_DEBUG_BUSY__PS0_BUSY_MASK 0x20 +#define SPI_DEBUG_BUSY__PS0_BUSY__SHIFT 0x5 +#define SPI_DEBUG_BUSY__PS1_BUSY_MASK 0x40 +#define SPI_DEBUG_BUSY__PS1_BUSY__SHIFT 0x6 +#define SPI_DEBUG_BUSY__CSG_BUSY_MASK 0x80 +#define SPI_DEBUG_BUSY__CSG_BUSY__SHIFT 0x7 +#define SPI_DEBUG_BUSY__CS0_BUSY_MASK 0x100 +#define SPI_DEBUG_BUSY__CS0_BUSY__SHIFT 0x8 +#define SPI_DEBUG_BUSY__CS1_BUSY_MASK 0x200 +#define SPI_DEBUG_BUSY__CS1_BUSY__SHIFT 0x9 +#define SPI_DEBUG_BUSY__CS2_BUSY_MASK 0x400 +#define SPI_DEBUG_BUSY__CS2_BUSY__SHIFT 0xa +#define SPI_DEBUG_BUSY__CS3_BUSY_MASK 0x800 +#define SPI_DEBUG_BUSY__CS3_BUSY__SHIFT 0xb +#define SPI_DEBUG_BUSY__CS4_BUSY_MASK 0x1000 +#define SPI_DEBUG_BUSY__CS4_BUSY__SHIFT 0xc +#define SPI_DEBUG_BUSY__CS5_BUSY_MASK 0x2000 +#define SPI_DEBUG_BUSY__CS5_BUSY__SHIFT 0xd +#define SPI_DEBUG_BUSY__CS6_BUSY_MASK 0x4000 +#define SPI_DEBUG_BUSY__CS6_BUSY__SHIFT 0xe +#define SPI_DEBUG_BUSY__CS7_BUSY_MASK 0x8000 +#define SPI_DEBUG_BUSY__CS7_BUSY__SHIFT 0xf +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY_MASK 0x10000 +#define SPI_DEBUG_BUSY__LDS_WR_CTL0_BUSY__SHIFT 0x10 +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY_MASK 0x20000 +#define SPI_DEBUG_BUSY__LDS_WR_CTL1_BUSY__SHIFT 0x11 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY_MASK 0x40000 +#define SPI_DEBUG_BUSY__RSRC_ALLOC0_BUSY__SHIFT 0x12 +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY_MASK 0x80000 +#define SPI_DEBUG_BUSY__RSRC_ALLOC1_BUSY__SHIFT 0x13 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY_MASK 0x100000 +#define SPI_DEBUG_BUSY__PC_DEALLOC_BUSY__SHIFT 0x14 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY_MASK 0x200000 +#define SPI_DEBUG_BUSY__EVENT_CLCTR_BUSY__SHIFT 0x15 +#define SPI_DEBUG_BUSY__GRBM_BUSY_MASK 0x400000 +#define SPI_DEBUG_BUSY__GRBM_BUSY__SHIFT 0x16 +#define SPI_DEBUG_BUSY__SPIS_BUSY_MASK 0x800000 +#define SPI_DEBUG_BUSY__SPIS_BUSY__SHIFT 0x17 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD_MASK 0xf +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_REQUEST_CYCLE_OVHD__SHIFT 0x0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD_MASK 0xf0 +#define SPI_CONFIG_CNTL_2__CONTEXT_SAVE_WAIT_GDS_GRANT_CYCLE_OVHD__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY_MASK 0xf +#define CGTS_SM_CTRL_REG__ON_SEQ_DELAY__SHIFT 0x0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY_MASK 0xff0 +#define CGTS_SM_CTRL_REG__OFF_SEQ_DELAY__SHIFT 0x4 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED_MASK 0x1000 +#define CGTS_SM_CTRL_REG__MGCG_ENABLED__SHIFT 0xc +#define CGTS_SM_CTRL_REG__BASE_MODE_MASK 0x10000 +#define CGTS_SM_CTRL_REG__BASE_MODE__SHIFT 0x10 +#define CGTS_SM_CTRL_REG__SM_MODE_MASK 0xe0000 +#define CGTS_SM_CTRL_REG__SM_MODE__SHIFT 0x11 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE_MASK 0x100000 +#define CGTS_SM_CTRL_REG__SM_MODE_ENABLE__SHIFT 0x14 +#define CGTS_SM_CTRL_REG__OVERRIDE_MASK 0x200000 +#define CGTS_SM_CTRL_REG__OVERRIDE__SHIFT 0x15 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK 0x400000 +#define CGTS_SM_CTRL_REG__LS_OVERRIDE__SHIFT 0x16 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN_MASK 0x800000 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_EN__SHIFT 0x17 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD_MASK 0xff000000 +#define CGTS_SM_CTRL_REG__ON_MONITOR_ADD__SHIFT 0x18 +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL_MASK 0x1f +#define CGTS_RD_CTRL_REG__ROW_MUX_SEL__SHIFT 0x0 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL_MASK 0x1f00 +#define CGTS_RD_CTRL_REG__REG_MUX_SEL__SHIFT 0x8 +#define CGTS_RD_REG__READ_DATA_MASK 0x3fff +#define CGTS_RD_REG__READ_DATA__SHIFT 0x0 +#define CGTS_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 +#define CGTS_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE_MASK 0xffff0000 +#define CGTS_USER_TCC_DISABLE__TCC_DISABLE__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU0_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU0_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU0_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU0_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU0_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU0_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU0_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU0_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU0_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU0_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU1_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU1_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU1_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU1_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU1_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU1_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU1_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU1_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU1_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU1_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU1_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU2_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU2_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU2_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU2_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU2_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU2_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU2_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU2_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU2_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU2_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU2_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU3_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU3_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU3_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU3_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU3_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU3_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU3_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU3_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU3_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU3_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU3_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU4_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU4_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU4_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU4_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU4_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU4_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU4_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU4_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU4_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU4_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU5_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU5_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU5_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU5_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU5_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU5_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU5_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU5_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU5_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU5_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU5_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU6_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU6_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU6_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU6_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU6_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU6_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU6_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU6_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU6_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU6_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU6_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU7_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU7_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU7_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU7_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU7_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU7_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU7_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU7_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU7_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU7_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU7_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU8_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU8_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU8_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU8_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU8_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU8_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU8_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU8_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU8_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU8_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU9_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU9_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU9_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU9_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU9_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU9_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU9_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU9_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU9_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU9_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU9_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU10_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU10_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU10_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU10_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU10_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU10_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU10_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU10_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU10_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU10_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU10_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU11_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU11_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU11_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU11_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU11_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU11_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU11_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU11_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU11_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU11_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU11_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU12_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU12_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU12_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU12_TA_SQC_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_TA_SQC_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_MASK 0x7f0000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC__SHIFT 0x10 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_TA_SQC_CTRL_REG__SQC_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU12_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU12_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU12_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU12_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU12_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU12_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU13_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU13_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU13_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU13_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU13_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU13_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU13_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU13_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU13_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU13_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU13_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU14_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU14_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU14_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU14_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU14_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU14_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU14_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU14_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU14_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU14_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU14_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_SP0_CTRL_REG__SP00_MASK 0x7f +#define CGTS_CU15_SP0_CTRL_REG__SP00__SHIFT 0x0 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE_MASK 0x80 +#define CGTS_CU15_SP0_CTRL_REG__SP00_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_SP0_CTRL_REG__SP00_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_SP0_CTRL_REG__SP00_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_SP0_CTRL_REG__SP00_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP0_CTRL_REG__SP01_MASK 0x7f0000 +#define CGTS_CU15_SP0_CTRL_REG__SP01__SHIFT 0x10 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_SP0_CTRL_REG__SP01_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_MASK 0x7f +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS__SHIFT 0x0 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE_MASK 0x80 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_LDS_SQ_CTRL_REG__LDS_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_MASK 0x7f0000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ__SHIFT 0x10 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_LDS_SQ_CTRL_REG__SQ_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TA_CTRL_REG__TA_MASK 0x7f +#define CGTS_CU15_TA_CTRL_REG__TA__SHIFT 0x0 +#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE_MASK 0x80 +#define CGTS_CU15_TA_CTRL_REG__TA_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_TA_CTRL_REG__TA_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_TA_CTRL_REG__TA_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_TA_CTRL_REG__TA_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP10_MASK 0x7f +#define CGTS_CU15_SP1_CTRL_REG__SP10__SHIFT 0x0 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE_MASK 0x80 +#define CGTS_CU15_SP1_CTRL_REG__SP10_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_SP1_CTRL_REG__SP10_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_SP1_CTRL_REG__SP10_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_SP1_CTRL_REG__SP10_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_SP1_CTRL_REG__SP11_MASK 0x7f0000 +#define CGTS_CU15_SP1_CTRL_REG__SP11__SHIFT 0x10 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_SP1_CTRL_REG__SP11_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_MASK 0x7f +#define CGTS_CU15_TD_TCP_CTRL_REG__TD__SHIFT 0x0 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE_MASK 0x80 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_OVERRIDE__SHIFT 0x7 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE_MASK 0x300 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_BUSY_OVERRIDE__SHIFT 0x8 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE_MASK 0x400 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_LS_OVERRIDE__SHIFT 0xa +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE_MASK 0x800 +#define CGTS_CU15_TD_TCP_CTRL_REG__TD_SIMDBUSY_OVERRIDE__SHIFT 0xb +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_MASK 0x7f0000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP__SHIFT 0x10 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE_MASK 0x800000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_OVERRIDE__SHIFT 0x17 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE_MASK 0x3000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_BUSY_OVERRIDE__SHIFT 0x18 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE_MASK 0x4000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_LS_OVERRIDE__SHIFT 0x1a +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE_MASK 0x8000000 +#define CGTS_CU15_TD_TCP_CTRL_REG__TCP_SIMDBUSY_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SPI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SPI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 +#define CGTT_SPI_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE_MASK 0x4000000 +#define CGTT_SPI_CLK_CTRL__ALL_CLK_ON_OVERRIDE__SHIFT 0x1a +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE_MASK 0x8000000 +#define CGTT_SPI_CLK_CTRL__GRP3_OVERRIDE__SHIFT 0x1b +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE_MASK 0x10000000 +#define CGTT_SPI_CLK_CTRL__GRP2_OVERRIDE__SHIFT 0x1c +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE_MASK 0x20000000 +#define CGTT_SPI_CLK_CTRL__GRP1_OVERRIDE__SHIFT 0x1d +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE_MASK 0x40000000 +#define CGTT_SPI_CLK_CTRL__GRP0_OVERRIDE__SHIFT 0x1e +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SPI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_PC_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_PC_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_PC_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST_MASK 0xfc0000 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OFF_HYST__SHIFT 0x12 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE_MASK 0x1000000 +#define CGTT_PC_CLK_CTRL__GRP5_CG_OVERRIDE__SHIFT 0x18 +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE_MASK 0x2000000 +#define CGTT_PC_CLK_CTRL__BACK_CLK_ON_OVERRIDE__SHIFT 0x19 +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE_MASK 0x4000000 +#define CGTT_PC_CLK_CTRL__FRONT_CLK_ON_OVERRIDE__SHIFT 0x1a +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 +#define CGTT_PC_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 +#define CGTT_PC_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 +#define CGTT_PC_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 +#define CGTT_PC_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_PC_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_BCI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_BCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_BCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_BCI_CLK_CTRL__RESERVED_MASK 0xfff000 +#define CGTT_BCI_CLK_CTRL__RESERVED__SHIFT 0xc +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE_MASK 0x1000000 +#define CGTT_BCI_CLK_CTRL__CORE6_OVERRIDE__SHIFT 0x18 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE_MASK 0x2000000 +#define CGTT_BCI_CLK_CTRL__CORE5_OVERRIDE__SHIFT 0x19 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE_MASK 0x4000000 +#define CGTT_BCI_CLK_CTRL__CORE4_OVERRIDE__SHIFT 0x1a +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE_MASK 0x8000000 +#define CGTT_BCI_CLK_CTRL__CORE3_OVERRIDE__SHIFT 0x1b +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE_MASK 0x10000000 +#define CGTT_BCI_CLK_CTRL__CORE2_OVERRIDE__SHIFT 0x1c +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE_MASK 0x20000000 +#define CGTT_BCI_CLK_CTRL__CORE1_OVERRIDE__SHIFT 0x1d +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE_MASK 0x40000000 +#define CGTT_BCI_CLK_CTRL__CORE0_OVERRIDE__SHIFT 0x1e +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_BCI_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD_MASK 0xf +#define SPI_WF_LIFETIME_CNTL__SAMPLE_PERIOD__SHIFT 0x0 +#define SPI_WF_LIFETIME_CNTL__EN_MASK 0x10 +#define SPI_WF_LIFETIME_CNTL__EN__SHIFT 0x4 +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_0__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_1__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_2__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_3__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_4__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_5__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_6__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_7__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_8__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_LIMIT_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN_MASK 0x80000000 +#define SPI_WF_LIFETIME_LIMIT_9__EN_WARN__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_0__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_0__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_1__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_1__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_2__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_2__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_3__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_3__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_4__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_4__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_5__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_5__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_6__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_6__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_7__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_7__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_8__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_8__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_9__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_9__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_10__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_10__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_11__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_11__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_12__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_12__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_13__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_13__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_14__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_14__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_15__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_15__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_16__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_16__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_17__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_17__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_18__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_18__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_19__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_19__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT_MASK 0x7fffffff +#define SPI_WF_LIFETIME_STATUS_20__MAX_CNT__SHIFT 0x0 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT_MASK 0x80000000 +#define SPI_WF_LIFETIME_STATUS_20__INT_SENT__SHIFT 0x1f +#define SPI_WF_LIFETIME_DEBUG__START_VALUE_MASK 0x7fffffff +#define SPI_WF_LIFETIME_DEBUG__START_VALUE__SHIFT 0x0 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN_MASK 0x80000000 +#define SPI_WF_LIFETIME_DEBUG__OVERRIDE_EN__SHIFT 0x1f +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY_MASK 0x1 +#define SPI_SLAVE_DEBUG_BUSY__LS_VTX_BUSY__SHIFT 0x0 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY_MASK 0x2 +#define SPI_SLAVE_DEBUG_BUSY__HS_VTX_BUSY__SHIFT 0x1 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY_MASK 0x4 +#define SPI_SLAVE_DEBUG_BUSY__ES_VTX_BUSY__SHIFT 0x2 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY_MASK 0x8 +#define SPI_SLAVE_DEBUG_BUSY__GS_VTX_BUSY__SHIFT 0x3 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY_MASK 0x10 +#define SPI_SLAVE_DEBUG_BUSY__VS_VTX_BUSY__SHIFT 0x4 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY_MASK 0x20 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC00_BUSY__SHIFT 0x5 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY_MASK 0x40 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC01_BUSY__SHIFT 0x6 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY_MASK 0x80 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC10_BUSY__SHIFT 0x7 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY_MASK 0x100 +#define SPI_SLAVE_DEBUG_BUSY__VGPR_WC11_BUSY__SHIFT 0x8 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY_MASK 0x200 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC00_BUSY__SHIFT 0x9 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY_MASK 0x400 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC01_BUSY__SHIFT 0xa +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY_MASK 0x800 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC02_BUSY__SHIFT 0xb +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY_MASK 0x1000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC03_BUSY__SHIFT 0xc +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY_MASK 0x2000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC10_BUSY__SHIFT 0xd +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY_MASK 0x4000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC11_BUSY__SHIFT 0xe +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY_MASK 0x8000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC12_BUSY__SHIFT 0xf +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY_MASK 0x10000 +#define SPI_SLAVE_DEBUG_BUSY__SGPR_WC13_BUSY__SHIFT 0x10 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY_MASK 0x20000 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER0_BUSY__SHIFT 0x11 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY_MASK 0x40000 +#define SPI_SLAVE_DEBUG_BUSY__WAVEBUFFER1_BUSY__SHIFT 0x12 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY_MASK 0x80000 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC0_BUSY__SHIFT 0x13 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY_MASK 0x100000 +#define SPI_SLAVE_DEBUG_BUSY__WAVE_WC1_BUSY__SHIFT 0x14 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY_MASK 0x200000 +#define SPI_SLAVE_DEBUG_BUSY__EVENT_CNTL_BUSY__SHIFT 0x15 +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY_MASK 0x400000 +#define SPI_SLAVE_DEBUG_BUSY__SAVE_CTX_BUSY__SHIFT 0x16 +#define SPI_LB_CTR_CTRL__LOAD_MASK 0x1 +#define SPI_LB_CTR_CTRL__LOAD__SHIFT 0x0 +#define SPI_LB_CU_MASK__CU_MASK_MASK 0xffff +#define SPI_LB_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_LB_DATA_REG__CNT_DATA_MASK 0xffffffff +#define SPI_LB_DATA_REG__CNT_DATA__SHIFT 0x0 +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK_MASK 0xffff +#define SPI_PG_ENABLE_STATIC_CU_MASK__CU_MASK__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_DATA_CREDITS_MASK 0xff +#define SPI_GDS_CREDITS__DS_DATA_CREDITS__SHIFT 0x0 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS_MASK 0xff00 +#define SPI_GDS_CREDITS__DS_CMD_CREDITS__SHIFT 0x8 +#define SPI_GDS_CREDITS__UNUSED_MASK 0xffff0000 +#define SPI_GDS_CREDITS__UNUSED__SHIFT 0x10 +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE_MASK 0xffff +#define SPI_SX_EXPORT_BUFFER_SIZES__COLOR_BUFFER_SIZE__SHIFT 0x0 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE_MASK 0xffff0000 +#define SPI_SX_EXPORT_BUFFER_SIZES__POSITION_BUFFER_SIZE__SHIFT 0x10 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE_MASK 0xffff +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__COLOR_SCOREBOARD_SIZE__SHIFT 0x0 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE_MASK 0xffff0000 +#define SPI_SX_SCOREBOARD_BUFFER_SIZES__POSITION_SCOREBOARD_SIZE__SHIFT 0x10 +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE_MASK 0xffffffff +#define SPI_CSQ_WF_ACTIVE_STATUS__ACTIVE__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_1__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_2__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_3__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_4__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_5__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_6__COUNT__SHIFT 0x0 +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT_MASK 0x7ff +#define SPI_CSQ_WF_ACTIVE_COUNT_7__COUNT__SHIFT 0x0 +#define BCI_DEBUG_READ__DATA_MASK 0xffffff +#define BCI_DEBUG_READ__DATA__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P0_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff +#define SPI_P0_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P0_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff +#define SPI_P0_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f +#define SPI_P0_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 +#define SPI_P0_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P1_TRAP_SCREEN_PSBA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE_MASK 0xff +#define SPI_P1_TRAP_SCREEN_PSBA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE_MASK 0xffffffff +#define SPI_P1_TRAP_SCREEN_PSMA_LO__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE_MASK 0xff +#define SPI_P1_TRAP_SCREEN_PSMA_HI__MEM_BASE__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN_MASK 0x3f +#define SPI_P1_TRAP_SCREEN_GPR_MIN__VGPR_MIN__SHIFT 0x0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN_MASK 0x3c0 +#define SPI_P1_TRAP_SCREEN_GPR_MIN__SGPR_MIN__SHIFT 0x6 +#define SPI_SHADER_TBA_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_PS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_PS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_PS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_PS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_PS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_PS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_PS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_PS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_PS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_PS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_PS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_PS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC1_PS__CU_GROUP_DISABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL_MASK 0xe000000 +#define SPI_SHADER_PGM_RSRC1_PS__CACHE_CTL__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER_MASK 0x10000000 +#define SPI_SHADER_PGM_RSRC1_PS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_PS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_PS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_PS__WAVE_CNT_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE_MASK 0xff00 +#define SPI_SHADER_PGM_RSRC2_PS__EXTRA_LDS_SIZE__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_PS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_PS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_PS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_PS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_USER_DATA_PS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_PS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_PS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_TBA_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_VS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_VS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_VS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_VS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_VS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_VS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_VS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_VS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_VS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_VS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_VS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_VS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_VS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE_MASK 0x4000000 +#define SPI_SHADER_PGM_RSRC1_VS__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL_MASK 0x38000000 +#define SPI_SHADER_PGM_RSRC1_VS__CACHE_CTL__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER_MASK 0x40000000 +#define SPI_SHADER_PGM_RSRC1_VS__CDBG_USER__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN_MASK 0x100 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE0_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN_MASK 0x200 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE1_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN_MASK 0x400 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE2_EN__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN_MASK 0x800 +#define SPI_SHADER_PGM_RSRC2_VS__SO_BASE3_EN__SHIFT 0xb +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN_MASK 0x1000 +#define SPI_SHADER_PGM_RSRC2_VS__SO_EN__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN_MASK 0x3fe000 +#define SPI_SHADER_PGM_RSRC2_VS__EXCP_EN__SHIFT 0xd +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC2_VS__DISPATCH_DRAW_EN__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_VS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_VS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_VS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT_MASK 0x3f +#define SPI_SHADER_LATE_ALLOC_VS__LIMIT__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_VS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_VS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES_VS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES_VS__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES_VS__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_VS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_VS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_VS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_VS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_VS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_GS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_GS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_GS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_GS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_GS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_GS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_GS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_GS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_GS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_GS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_GS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_GS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE_MASK 0x1000000 +#define SPI_SHADER_PGM_RSRC1_GS__CU_GROUP_ENABLE__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL_MASK 0xe000000 +#define SPI_SHADER_PGM_RSRC1_GS__CACHE_CTL__SHIFT 0x19 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER_MASK 0x10000000 +#define SPI_SHADER_PGM_RSRC1_GS__CDBG_USER__SHIFT 0x1c +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_GS__EXCP_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_GS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_GS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_GS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH_MASK 0xfc000000 +#define SPI_SHADER_PGM_RSRC3_GS__GROUP_FIFO_DEPTH__SHIFT 0x1a +#define SPI_SHADER_USER_DATA_GS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_GS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_GS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_GS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES_GS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES_GS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES_GS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES_GS__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES_GS__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_TBA_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_ES__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_ES__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_ES__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_ES__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_ES__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_ES__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_ES__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_ES__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_ES__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_ES__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_ES__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_ES__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_ES__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE_MASK 0x4000000 +#define SPI_SHADER_PGM_RSRC1_ES__CU_GROUP_ENABLE__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL_MASK 0x38000000 +#define SPI_SHADER_PGM_RSRC1_ES__CACHE_CTL__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER_MASK 0x40000000 +#define SPI_SHADER_PGM_RSRC1_ES__CDBG_USER__SHIFT 0x1e +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_ES__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_ES__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_ES__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_ES__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN_MASK 0x1ff00 +#define SPI_SHADER_PGM_RSRC2_ES__EXCP_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE_MASK 0x1ff00000 +#define SPI_SHADER_PGM_RSRC2_ES__LDS_SIZE__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC3_ES__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_ES__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_ES__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_ES__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH_MASK 0xfc000000 +#define SPI_SHADER_PGM_RSRC3_ES__GROUP_FIFO_DEPTH__SHIFT 0x1a +#define SPI_SHADER_USER_DATA_ES_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_ES_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_ES_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_ES__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_ES__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_ES__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_ES__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_ES__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_HS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_HS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_HS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_HS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_HS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_HS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_HS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_HS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_HS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_HS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_HS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_HS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL_MASK 0x7000000 +#define SPI_SHADER_PGM_RSRC1_HS__CACHE_CTL__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER_MASK 0x8000000 +#define SPI_SHADER_PGM_RSRC1_HS__CDBG_USER__SHIFT 0x1b +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN_MASK 0x80 +#define SPI_SHADER_PGM_RSRC2_HS__OC_LDS_EN__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN_MASK 0x100 +#define SPI_SHADER_PGM_RSRC2_HS__TG_SIZE_EN__SHIFT 0x8 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN_MASK 0x3fe00 +#define SPI_SHADER_PGM_RSRC2_HS__EXCP_EN__SHIFT 0x9 +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT_MASK 0x3f +#define SPI_SHADER_PGM_RSRC3_HS__WAVE_LIMIT__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC3_HS__LOCK_LOW_THRESHOLD__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH_MASK 0xfc00 +#define SPI_SHADER_PGM_RSRC3_HS__GROUP_FIFO_DEPTH__SHIFT 0xa +#define SPI_SHADER_USER_DATA_HS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_HS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_HS_15__DATA__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_HS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS_HS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS_HS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS_HS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS_HS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_TBA_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TBA_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TBA_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TBA_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_TMA_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_TMA_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_TMA_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_LO_LS__MEM_BASE_MASK 0xffffffff +#define SPI_SHADER_PGM_LO_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_HI_LS__MEM_BASE_MASK 0xff +#define SPI_SHADER_PGM_HI_LS__MEM_BASE__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS_MASK 0x3f +#define SPI_SHADER_PGM_RSRC1_LS__VGPRS__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS_MASK 0x3c0 +#define SPI_SHADER_PGM_RSRC1_LS__SGPRS__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY_MASK 0xc00 +#define SPI_SHADER_PGM_RSRC1_LS__PRIORITY__SHIFT 0xa +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE_MASK 0xff000 +#define SPI_SHADER_PGM_RSRC1_LS__FLOAT_MODE__SHIFT 0xc +#define SPI_SHADER_PGM_RSRC1_LS__PRIV_MASK 0x100000 +#define SPI_SHADER_PGM_RSRC1_LS__PRIV__SHIFT 0x14 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP_MASK 0x200000 +#define SPI_SHADER_PGM_RSRC1_LS__DX10_CLAMP__SHIFT 0x15 +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE_MASK 0x400000 +#define SPI_SHADER_PGM_RSRC1_LS__DEBUG_MODE__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE_MASK 0x800000 +#define SPI_SHADER_PGM_RSRC1_LS__IEEE_MODE__SHIFT 0x17 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT_MASK 0x3000000 +#define SPI_SHADER_PGM_RSRC1_LS__VGPR_COMP_CNT__SHIFT 0x18 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL_MASK 0x1c000000 +#define SPI_SHADER_PGM_RSRC1_LS__CACHE_CTL__SHIFT 0x1a +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER_MASK 0x20000000 +#define SPI_SHADER_PGM_RSRC1_LS__CDBG_USER__SHIFT 0x1d +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN_MASK 0x1 +#define SPI_SHADER_PGM_RSRC2_LS__SCRATCH_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR_MASK 0x3e +#define SPI_SHADER_PGM_RSRC2_LS__USER_SGPR__SHIFT 0x1 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT_MASK 0x40 +#define SPI_SHADER_PGM_RSRC2_LS__TRAP_PRESENT__SHIFT 0x6 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE_MASK 0xff80 +#define SPI_SHADER_PGM_RSRC2_LS__LDS_SIZE__SHIFT 0x7 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN_MASK 0x1ff0000 +#define SPI_SHADER_PGM_RSRC2_LS__EXCP_EN__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_LS__CU_EN_MASK 0xffff +#define SPI_SHADER_PGM_RSRC3_LS__CU_EN__SHIFT 0x0 +#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT_MASK 0x3f0000 +#define SPI_SHADER_PGM_RSRC3_LS__WAVE_LIMIT__SHIFT 0x10 +#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD_MASK 0x3c00000 +#define SPI_SHADER_PGM_RSRC3_LS__LOCK_LOW_THRESHOLD__SHIFT 0x16 +#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH_MASK 0xfc000000 +#define SPI_SHADER_PGM_RSRC3_LS__GROUP_FIFO_DEPTH__SHIFT 0x1a +#define SPI_SHADER_USER_DATA_LS_0__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_0__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_1__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_1__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_2__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_2__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_3__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_3__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_4__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_4__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_5__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_5__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_6__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_6__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_7__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_7__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_8__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_8__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_9__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_9__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_10__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_10__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_11__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_11__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_12__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_12__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_13__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_13__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_14__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_14__DATA__SHIFT 0x0 +#define SPI_SHADER_USER_DATA_LS_15__DATA_MASK 0xffffffff +#define SPI_SHADER_USER_DATA_LS_15__DATA__SHIFT 0x0 +#define SQ_CONFIG__UNUSED_MASK 0xff +#define SQ_CONFIG__UNUSED__SHIFT 0x0 +#define SQ_CONFIG__DEBUG_EN_MASK 0x100 +#define SQ_CONFIG__DEBUG_EN__SHIFT 0x8 +#define SQ_CONFIG__DEBUG_SINGLE_MEMOP_MASK 0x200 +#define SQ_CONFIG__DEBUG_SINGLE_MEMOP__SHIFT 0x9 +#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE_MASK 0x400 +#define SQ_CONFIG__DEBUG_ONE_INST_CLAUSE__SHIFT 0xa +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE_MASK 0x1000 +#define SQ_CONFIG__EARLY_TA_DONE_DISABLE__SHIFT 0xc +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE_MASK 0x2000 +#define SQ_CONFIG__DUA_FLAT_LOCK_ENABLE__SHIFT 0xd +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE_MASK 0x4000 +#define SQ_CONFIG__DUA_LDS_BYPASS_DISABLE__SHIFT 0xe +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE_MASK 0x8000 +#define SQ_CONFIG__DUA_FLAT_LDS_PINGPONG_DISABLE__SHIFT 0xf +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE_MASK 0x10000 +#define SQ_CONFIG__DISABLE_VMEM_SOFT_CLAUSE__SHIFT 0x10 +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE_MASK 0x20000 +#define SQ_CONFIG__DISABLE_SMEM_SOFT_CLAUSE__SHIFT 0x11 +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS_MASK 0x40000 +#define SQ_CONFIG__ENABLE_HIPRIO_ON_EXP_RDY_VS__SHIFT 0x12 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS_MASK 0x180000 +#define SQ_CONFIG__PRIO_VAL_ON_EXP_RDY_VS__SHIFT 0x13 +#define SQ_CONFIG__REPLAY_SLEEP_CNT_MASK 0x1e00000 +#define SQ_CONFIG__REPLAY_SLEEP_CNT__SHIFT 0x15 +#define SQC_CONFIG__INST_CACHE_SIZE_MASK 0x3 +#define SQC_CONFIG__INST_CACHE_SIZE__SHIFT 0x0 +#define SQC_CONFIG__DATA_CACHE_SIZE_MASK 0xc +#define SQC_CONFIG__DATA_CACHE_SIZE__SHIFT 0x2 +#define SQC_CONFIG__MISS_FIFO_DEPTH_MASK 0x30 +#define SQC_CONFIG__MISS_FIFO_DEPTH__SHIFT 0x4 +#define SQC_CONFIG__HIT_FIFO_DEPTH_MASK 0x40 +#define SQC_CONFIG__HIT_FIFO_DEPTH__SHIFT 0x6 +#define SQC_CONFIG__FORCE_ALWAYS_MISS_MASK 0x80 +#define SQC_CONFIG__FORCE_ALWAYS_MISS__SHIFT 0x7 +#define SQC_CONFIG__FORCE_IN_ORDER_MASK 0x100 +#define SQC_CONFIG__FORCE_IN_ORDER__SHIFT 0x8 +#define SQC_CONFIG__IDENTITY_HASH_BANK_MASK 0x200 +#define SQC_CONFIG__IDENTITY_HASH_BANK__SHIFT 0x9 +#define SQC_CONFIG__IDENTITY_HASH_SET_MASK 0x400 +#define SQC_CONFIG__IDENTITY_HASH_SET__SHIFT 0xa +#define SQC_CONFIG__PER_VMID_INV_DISABLE_MASK 0x800 +#define SQC_CONFIG__PER_VMID_INV_DISABLE__SHIFT 0xb +#define SQC_CONFIG__EVICT_LRU_MASK 0x3000 +#define SQC_CONFIG__EVICT_LRU__SHIFT 0xc +#define SQC_CONFIG__FORCE_2_BANK_MASK 0x4000 +#define SQC_CONFIG__FORCE_2_BANK__SHIFT 0xe +#define SQC_CONFIG__FORCE_1_BANK_MASK 0x8000 +#define SQC_CONFIG__FORCE_1_BANK__SHIFT 0xf +#define SQC_CONFIG__LS_DISABLE_CLOCKS_MASK 0xff0000 +#define SQC_CONFIG__LS_DISABLE_CLOCKS__SHIFT 0x10 +#define SQC_CACHES__TARGET_INST_MASK 0x1 +#define SQC_CACHES__TARGET_INST__SHIFT 0x0 +#define SQC_CACHES__TARGET_DATA_MASK 0x2 +#define SQC_CACHES__TARGET_DATA__SHIFT 0x1 +#define SQC_CACHES__INVALIDATE_MASK 0x4 +#define SQC_CACHES__INVALIDATE__SHIFT 0x2 +#define SQC_CACHES__WRITEBACK_MASK 0x8 +#define SQC_CACHES__WRITEBACK__SHIFT 0x3 +#define SQC_CACHES__VOL_MASK 0x10 +#define SQC_CACHES__VOL__SHIFT 0x4 +#define SQC_CACHES__COMPLETE_MASK 0x10000 +#define SQC_CACHES__COMPLETE__SHIFT 0x10 +#define SQC_WRITEBACK__DWB_MASK 0x1 +#define SQC_WRITEBACK__DWB__SHIFT 0x0 +#define SQC_WRITEBACK__DIRTY_MASK 0x2 +#define SQC_WRITEBACK__DIRTY__SHIFT 0x1 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA_MASK 0x3 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKA__SHIFT 0x0 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA_MASK 0x4 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKA__SHIFT 0x2 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB_MASK 0x18 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKB__SHIFT 0x3 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB_MASK 0x20 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKB__SHIFT 0x5 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC_MASK 0xc0 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKC__SHIFT 0x6 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC_MASK 0x100 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKC__SHIFT 0x8 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD_MASK 0x600 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_BANKD__SHIFT 0x9 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD_MASK 0x800 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_BANKD__SHIFT 0xb +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1_MASK 0x3000 +#define SQC_DSM_CNTL__SEL_DATA_ICACHE_GATCL1__SHIFT 0xc +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1_MASK 0x4000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_ICACHE_GATCL1__SHIFT 0xe +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA_MASK 0x18000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKA__SHIFT 0xf +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA_MASK 0x20000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKA__SHIFT 0x11 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB_MASK 0xc0000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKB__SHIFT 0x12 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB_MASK 0x100000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKB__SHIFT 0x14 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC_MASK 0x600000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKC__SHIFT 0x15 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC_MASK 0x800000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKC__SHIFT 0x17 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD_MASK 0x3000000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_BANKD__SHIFT 0x18 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD_MASK 0x4000000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_BANKD__SHIFT 0x1a +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1_MASK 0x18000000 +#define SQC_DSM_CNTL__SEL_DATA_DCACHE_GATCL1__SHIFT 0x1b +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1_MASK 0x20000000 +#define SQC_DSM_CNTL__EN_SINGLE_WR_DCACHE_GATCL1__SHIFT 0x1d +#define SQ_RANDOM_WAVE_PRI__RET_MASK 0x7f +#define SQ_RANDOM_WAVE_PRI__RET__SHIFT 0x0 +#define SQ_RANDOM_WAVE_PRI__RUI_MASK 0x380 +#define SQ_RANDOM_WAVE_PRI__RUI__SHIFT 0x7 +#define SQ_RANDOM_WAVE_PRI__RNG_MASK 0x1ffc00 +#define SQ_RANDOM_WAVE_PRI__RNG__SHIFT 0xa +#define SQ_REG_CREDITS__SRBM_CREDITS_MASK 0x3f +#define SQ_REG_CREDITS__SRBM_CREDITS__SHIFT 0x0 +#define SQ_REG_CREDITS__CMD_CREDITS_MASK 0xf00 +#define SQ_REG_CREDITS__CMD_CREDITS__SHIFT 0x8 +#define SQ_REG_CREDITS__REG_BUSY_MASK 0x10000000 +#define SQ_REG_CREDITS__REG_BUSY__SHIFT 0x1c +#define SQ_REG_CREDITS__SRBM_OVERFLOW_MASK 0x20000000 +#define SQ_REG_CREDITS__SRBM_OVERFLOW__SHIFT 0x1d +#define SQ_REG_CREDITS__IMMED_OVERFLOW_MASK 0x40000000 +#define SQ_REG_CREDITS__IMMED_OVERFLOW__SHIFT 0x1e +#define SQ_REG_CREDITS__CMD_OVERFLOW_MASK 0x80000000 +#define SQ_REG_CREDITS__CMD_OVERFLOW__SHIFT 0x1f +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE_MASK 0xf +#define SQ_FIFO_SIZES__INTERRUPT_FIFO_SIZE__SHIFT 0x0 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE_MASK 0xf00 +#define SQ_FIFO_SIZES__TTRACE_FIFO_SIZE__SHIFT 0x8 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE_MASK 0x30000 +#define SQ_FIFO_SIZES__EXPORT_BUF_SIZE__SHIFT 0x10 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE_MASK 0xc0000 +#define SQ_FIFO_SIZES__VMEM_DATA_FIFO_SIZE__SHIFT 0x12 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0_MASK 0x1 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_0__SHIFT 0x0 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1_MASK 0x2 +#define SQ_DSM_CNTL__WAVEFRONT_STALL_1__SHIFT 0x1 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0_MASK 0x4 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1_MASK 0x8 +#define SQ_DSM_CNTL__SPI_BACKPRESSURE_1__SHIFT 0x3 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0_MASK 0x100 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA0__SHIFT 0x8 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1_MASK 0x200 +#define SQ_DSM_CNTL__SEL_DSM_SGPR_IRRITATOR_DATA1__SHIFT 0x9 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE_MASK 0x400 +#define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0_MASK 0x10000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA0__SHIFT 0x10 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1_MASK 0x20000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA1__SHIFT 0x11 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01_MASK 0x40000 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE01__SHIFT 0x12 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2_MASK 0x80000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA2__SHIFT 0x13 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3_MASK 0x100000 +#define SQ_DSM_CNTL__SEL_DSM_LDS_IRRITATOR_DATA3__SHIFT 0x14 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23_MASK 0x200000 +#define SQ_DSM_CNTL__LDS_ENABLE_SINGLE_WRITE23__SHIFT 0x15 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0_MASK 0x1000000 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA0__SHIFT 0x18 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1_MASK 0x2000000 +#define SQ_DSM_CNTL__SEL_DSM_SP_IRRITATOR_DATA1__SHIFT 0x19 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE_MASK 0x4000000 +#define SQ_DSM_CNTL__SP_ENABLE_SINGLE_WRITE__SHIFT 0x1a +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 +#define CC_GC_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 +#define CC_GC_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 +#define CC_GC_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE_MASK 0x6 +#define GC_USER_SHADER_RATE_CONFIG__DPFP_RATE__SHIFT 0x1 +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE_MASK 0x8 +#define GC_USER_SHADER_RATE_CONFIG__SQC_BALANCE_DISABLE__SHIFT 0x3 +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS_MASK 0x10 +#define GC_USER_SHADER_RATE_CONFIG__HALF_LDS__SHIFT 0x4 +#define SQ_INTERRUPT_AUTO_MASK__MASK_MASK 0xffffff +#define SQ_INTERRUPT_AUTO_MASK__MASK__SHIFT 0x0 +#define SQ_INTERRUPT_MSG_CTRL__STALL_MASK 0x1 +#define SQ_INTERRUPT_MSG_CTRL__STALL__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__PS_EN_MASK 0x1 +#define SQ_PERFCOUNTER_CTRL__PS_EN__SHIFT 0x0 +#define SQ_PERFCOUNTER_CTRL__VS_EN_MASK 0x2 +#define SQ_PERFCOUNTER_CTRL__VS_EN__SHIFT 0x1 +#define SQ_PERFCOUNTER_CTRL__GS_EN_MASK 0x4 +#define SQ_PERFCOUNTER_CTRL__GS_EN__SHIFT 0x2 +#define SQ_PERFCOUNTER_CTRL__ES_EN_MASK 0x8 +#define SQ_PERFCOUNTER_CTRL__ES_EN__SHIFT 0x3 +#define SQ_PERFCOUNTER_CTRL__HS_EN_MASK 0x10 +#define SQ_PERFCOUNTER_CTRL__HS_EN__SHIFT 0x4 +#define SQ_PERFCOUNTER_CTRL__LS_EN_MASK 0x20 +#define SQ_PERFCOUNTER_CTRL__LS_EN__SHIFT 0x5 +#define SQ_PERFCOUNTER_CTRL__CS_EN_MASK 0x40 +#define SQ_PERFCOUNTER_CTRL__CS_EN__SHIFT 0x6 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE_MASK 0x1f00 +#define SQ_PERFCOUNTER_CTRL__CNTR_RATE__SHIFT 0x8 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH_MASK 0x2000 +#define SQ_PERFCOUNTER_CTRL__DISABLE_FLUSH__SHIFT 0xd +#define SQ_PERFCOUNTER_MASK__SH0_MASK_MASK 0xffff +#define SQ_PERFCOUNTER_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_PERFCOUNTER_MASK__SH1_MASK_MASK 0xffff0000 +#define SQ_PERFCOUNTER_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN_MASK 0x1 +#define SQ_PERFCOUNTER_CTRL2__FORCE_EN__SHIFT 0x0 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 +#define CC_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 +#define CC_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 +#define CC_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 +#define CC_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE_MASK 0xf0000 +#define USER_SQC_BANK_DISABLE__SQC0_BANK_DISABLE__SHIFT 0x10 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE_MASK 0xf00000 +#define USER_SQC_BANK_DISABLE__SQC1_BANK_DISABLE__SHIFT 0x14 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE_MASK 0xf000000 +#define USER_SQC_BANK_DISABLE__SQC2_BANK_DISABLE__SHIFT 0x18 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE_MASK 0xf0000000 +#define USER_SQC_BANK_DISABLE__SQC3_BANK_DISABLE__SHIFT 0x1c +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER4_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER5_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER6_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER7_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER8_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER9_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER10_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER11_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER12_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER13_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER14_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SQ_PERFCOUNTER15_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER4_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER5_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER6_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER7_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER8_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER9_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER10_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER11_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER12_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER13_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER14_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SQ_PERFCOUNTER15_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER0_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER0_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER0_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER0_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER1_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER1_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER1_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER1_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER2_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER2_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER2_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER2_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER3_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER3_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER3_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER3_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER4_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER4_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER4_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER4_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER4_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER4_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER5_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER5_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER5_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER5_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER5_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER5_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER6_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER6_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER6_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER6_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER6_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER6_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER7_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER7_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER7_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER7_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER7_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER7_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER8_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER8_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER8_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER8_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER8_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER8_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER9_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER9_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER9_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER9_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER9_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER9_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER10_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER10_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER10_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER10_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER10_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER10_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER11_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER11_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER11_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER11_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER11_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER11_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER12_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER12_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER12_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER12_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER12_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER12_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER13_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER13_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER13_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER13_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER13_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER13_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER14_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER14_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER14_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER14_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER14_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER14_SELECT__PERF_MODE__SHIFT 0x1c +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL_MASK 0x1ff +#define SQ_PERFCOUNTER15_SELECT__PERF_SEL__SHIFT 0x0 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK_MASK 0xf000 +#define SQ_PERFCOUNTER15_SELECT__SQC_BANK_MASK__SHIFT 0xc +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK_MASK 0xf0000 +#define SQ_PERFCOUNTER15_SELECT__SQC_CLIENT_MASK__SHIFT 0x10 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE_MASK 0xf00000 +#define SQ_PERFCOUNTER15_SELECT__SPM_MODE__SHIFT 0x14 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK_MASK 0xf000000 +#define SQ_PERFCOUNTER15_SELECT__SIMD_MASK__SHIFT 0x18 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE_MASK 0xf0000000 +#define SQ_PERFCOUNTER15_SELECT__PERF_MODE__SHIFT 0x1c +#define CGTT_SQ_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SQ_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SQ_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 +#define CGTT_SQ_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_SQ_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SQ_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_SQG_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_SQG_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SQG_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE_MASK 0x10000000 +#define CGTT_SQG_CLK_CTRL__TTRACE_OVERRIDE__SHIFT 0x1c +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE_MASK 0x20000000 +#define CGTT_SQG_CLK_CTRL__PERFMON_OVERRIDE__SHIFT 0x1d +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_SQG_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_SQG_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_ALU_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_TEX_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0_MASK 0xffff +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH0__SHIFT 0x0 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1_MASK 0xffff0000 +#define SQ_LDS_CLK_CTRL__FORCE_CU_ON_SH1__SHIFT 0x10 +#define SQ_POWER_THROTTLE__MIN_POWER_MASK 0x3fff +#define SQ_POWER_THROTTLE__MIN_POWER__SHIFT 0x0 +#define SQ_POWER_THROTTLE__MAX_POWER_MASK 0x3fff0000 +#define SQ_POWER_THROTTLE__MAX_POWER__SHIFT 0x10 +#define SQ_POWER_THROTTLE__PHASE_OFFSET_MASK 0xc0000000 +#define SQ_POWER_THROTTLE__PHASE_OFFSET__SHIFT 0x1e +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA_MASK 0x3fff +#define SQ_POWER_THROTTLE2__MAX_POWER_DELTA__SHIFT 0x0 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define SQ_POWER_THROTTLE2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define SQ_POWER_THROTTLE2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK_MASK 0x80000000 +#define SQ_POWER_THROTTLE2__USE_REF_CLOCK__SHIFT 0x1f +#define SQ_TIME_HI__TIME_MASK 0xffffffff +#define SQ_TIME_HI__TIME__SHIFT 0x0 +#define SQ_TIME_LO__TIME_MASK 0xffffffff +#define SQ_TIME_LO__TIME__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE__ADDR_MASK 0xffffffff +#define SQ_THREAD_TRACE_BASE__ADDR__SHIFT 0x0 +#define SQ_THREAD_TRACE_BASE2__ADDR_HI_MASK 0xf +#define SQ_THREAD_TRACE_BASE2__ADDR_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_SIZE__SIZE_MASK 0x3fffff +#define SQ_THREAD_TRACE_SIZE__SIZE__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__CU_SEL_MASK 0x1f +#define SQ_THREAD_TRACE_MASK__CU_SEL__SHIFT 0x0 +#define SQ_THREAD_TRACE_MASK__SH_SEL_MASK 0x20 +#define SQ_THREAD_TRACE_MASK__SH_SEL__SHIFT 0x5 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN_MASK 0x80 +#define SQ_THREAD_TRACE_MASK__REG_STALL_EN__SHIFT 0x7 +#define SQ_THREAD_TRACE_MASK__SIMD_EN_MASK 0xf00 +#define SQ_THREAD_TRACE_MASK__SIMD_EN__SHIFT 0x8 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK_MASK 0x3000 +#define SQ_THREAD_TRACE_MASK__VM_ID_MASK__SHIFT 0xc +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN_MASK 0x4000 +#define SQ_THREAD_TRACE_MASK__SPI_STALL_EN__SHIFT 0xe +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN_MASK 0x8000 +#define SQ_THREAD_TRACE_MASK__SQ_STALL_EN__SHIFT 0xf +#define SQ_THREAD_TRACE_USERDATA_0__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_0__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_1__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_1__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_2__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_USERDATA_3__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_USERDATA_3__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_PS_MASK 0x7 +#define SQ_THREAD_TRACE_MODE__MASK_PS__SHIFT 0x0 +#define SQ_THREAD_TRACE_MODE__MASK_VS_MASK 0x38 +#define SQ_THREAD_TRACE_MODE__MASK_VS__SHIFT 0x3 +#define SQ_THREAD_TRACE_MODE__MASK_GS_MASK 0x1c0 +#define SQ_THREAD_TRACE_MODE__MASK_GS__SHIFT 0x6 +#define SQ_THREAD_TRACE_MODE__MASK_ES_MASK 0xe00 +#define SQ_THREAD_TRACE_MODE__MASK_ES__SHIFT 0x9 +#define SQ_THREAD_TRACE_MODE__MASK_HS_MASK 0x7000 +#define SQ_THREAD_TRACE_MODE__MASK_HS__SHIFT 0xc +#define SQ_THREAD_TRACE_MODE__MASK_LS_MASK 0x38000 +#define SQ_THREAD_TRACE_MODE__MASK_LS__SHIFT 0xf +#define SQ_THREAD_TRACE_MODE__MASK_CS_MASK 0x1c0000 +#define SQ_THREAD_TRACE_MODE__MASK_CS__SHIFT 0x12 +#define SQ_THREAD_TRACE_MODE__MODE_MASK 0x600000 +#define SQ_THREAD_TRACE_MODE__MODE__SHIFT 0x15 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE_MASK 0x1800000 +#define SQ_THREAD_TRACE_MODE__CAPTURE_MODE__SHIFT 0x17 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN_MASK 0x2000000 +#define SQ_THREAD_TRACE_MODE__AUTOFLUSH_EN__SHIFT 0x19 +#define SQ_THREAD_TRACE_MODE__PRIV_MASK 0x4000000 +#define SQ_THREAD_TRACE_MODE__PRIV__SHIFT 0x1a +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK_MASK 0x18000000 +#define SQ_THREAD_TRACE_MODE__ISSUE_MASK__SHIFT 0x1b +#define SQ_THREAD_TRACE_MODE__TEST_MODE_MASK 0x20000000 +#define SQ_THREAD_TRACE_MODE__TEST_MODE__SHIFT 0x1d +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN_MASK 0x40000000 +#define SQ_THREAD_TRACE_MODE__INTERRUPT_EN__SHIFT 0x1e +#define SQ_THREAD_TRACE_MODE__WRAP_MASK 0x80000000 +#define SQ_THREAD_TRACE_MODE__WRAP__SHIFT 0x1f +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER_MASK 0x80000000 +#define SQ_THREAD_TRACE_CTRL__RESET_BUFFER__SHIFT 0x1f +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK_MASK 0xffff +#define SQ_THREAD_TRACE_TOKEN_MASK__TOKEN_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK_MASK 0xff0000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL_MASK 0x1000000 +#define SQ_THREAD_TRACE_TOKEN_MASK__REG_DROP_ON_STALL__SHIFT 0x18 +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK_MASK 0xffffffff +#define SQ_THREAD_TRACE_TOKEN_MASK2__INST_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK_MASK 0xffff +#define SQ_THREAD_TRACE_PERF_MASK__SH0_MASK__SHIFT 0x0 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK_MASK 0xffff0000 +#define SQ_THREAD_TRACE_PERF_MASK__SH1_MASK__SHIFT 0x10 +#define SQ_THREAD_TRACE_WPTR__WPTR_MASK 0x3fffffff +#define SQ_THREAD_TRACE_WPTR__WPTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET_MASK 0xc0000000 +#define SQ_THREAD_TRACE_WPTR__READ_OFFSET__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING_MASK 0x3ff +#define SQ_THREAD_TRACE_STATUS__FINISH_PENDING__SHIFT 0x0 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE_MASK 0x3ff0000 +#define SQ_THREAD_TRACE_STATUS__FINISH_DONE__SHIFT 0x10 +#define SQ_THREAD_TRACE_STATUS__NEW_BUF_MASK 0x20000000 +#define SQ_THREAD_TRACE_STATUS__NEW_BUF__SHIFT 0x1d +#define SQ_THREAD_TRACE_STATUS__BUSY_MASK 0x40000000 +#define SQ_THREAD_TRACE_STATUS__BUSY__SHIFT 0x1e +#define SQ_THREAD_TRACE_STATUS__FULL_MASK 0x80000000 +#define SQ_THREAD_TRACE_STATUS__FULL__SHIFT 0x1f +#define SQ_THREAD_TRACE_CNTR__CNTR_MASK 0xffffffff +#define SQ_THREAD_TRACE_CNTR__CNTR__SHIFT 0x0 +#define SQ_THREAD_TRACE_HIWATER__HIWATER_MASK 0x7 +#define SQ_THREAD_TRACE_HIWATER__HIWATER__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__START_MASK 0x1 +#define SQ_LB_CTR_CTRL__START__SHIFT 0x0 +#define SQ_LB_CTR_CTRL__LOAD_MASK 0x2 +#define SQ_LB_CTR_CTRL__LOAD__SHIFT 0x1 +#define SQ_LB_CTR_CTRL__CLEAR_MASK 0x4 +#define SQ_LB_CTR_CTRL__CLEAR__SHIFT 0x2 +#define SQ_LB_DATA_ALU_CYCLES__DATA_MASK 0xffffffff +#define SQ_LB_DATA_ALU_CYCLES__DATA__SHIFT 0x0 +#define SQ_LB_DATA_TEX_CYCLES__DATA_MASK 0xffffffff +#define SQ_LB_DATA_TEX_CYCLES__DATA__SHIFT 0x0 +#define SQ_LB_DATA_ALU_STALLS__DATA_MASK 0xffffffff +#define SQ_LB_DATA_ALU_STALLS__DATA__SHIFT 0x0 +#define SQ_LB_DATA_TEX_STALLS__DATA_MASK 0xffffffff +#define SQ_LB_DATA_TEX_STALLS__DATA__SHIFT 0x0 +#define SQC_EDC_CNT__INST_SEC_MASK 0xff +#define SQC_EDC_CNT__INST_SEC__SHIFT 0x0 +#define SQC_EDC_CNT__INST_DED_MASK 0xff00 +#define SQC_EDC_CNT__INST_DED__SHIFT 0x8 +#define SQC_EDC_CNT__DATA_SEC_MASK 0xff0000 +#define SQC_EDC_CNT__DATA_SEC__SHIFT 0x10 +#define SQC_EDC_CNT__DATA_DED_MASK 0xff000000 +#define SQC_EDC_CNT__DATA_DED__SHIFT 0x18 +#define SQ_EDC_SEC_CNT__LDS_SEC_MASK 0xff +#define SQ_EDC_SEC_CNT__LDS_SEC__SHIFT 0x0 +#define SQ_EDC_SEC_CNT__SGPR_SEC_MASK 0xff00 +#define SQ_EDC_SEC_CNT__SGPR_SEC__SHIFT 0x8 +#define SQ_EDC_SEC_CNT__VGPR_SEC_MASK 0xff0000 +#define SQ_EDC_SEC_CNT__VGPR_SEC__SHIFT 0x10 +#define SQ_EDC_DED_CNT__LDS_DED_MASK 0xff +#define SQ_EDC_DED_CNT__LDS_DED__SHIFT 0x0 +#define SQ_EDC_DED_CNT__SGPR_DED_MASK 0xff00 +#define SQ_EDC_DED_CNT__SGPR_DED__SHIFT 0x8 +#define SQ_EDC_DED_CNT__VGPR_DED_MASK 0xff0000 +#define SQ_EDC_DED_CNT__VGPR_DED__SHIFT 0x10 +#define SQ_EDC_INFO__WAVE_ID_MASK 0xf +#define SQ_EDC_INFO__WAVE_ID__SHIFT 0x0 +#define SQ_EDC_INFO__SIMD_ID_MASK 0x30 +#define SQ_EDC_INFO__SIMD_ID__SHIFT 0x4 +#define SQ_EDC_INFO__SOURCE_MASK 0x1c0 +#define SQ_EDC_INFO__SOURCE__SHIFT 0x6 +#define SQ_EDC_INFO__VM_ID_MASK 0x1e00 +#define SQ_EDC_INFO__VM_ID__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff +#define SQ_BUF_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xffff +#define SQ_BUF_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD1__STRIDE_MASK 0x3fff0000 +#define SQ_BUF_RSRC_WORD1__STRIDE__SHIFT 0x10 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE_MASK 0x40000000 +#define SQ_BUF_RSRC_WORD1__CACHE_SWIZZLE__SHIFT 0x1e +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE_MASK 0x80000000 +#define SQ_BUF_RSRC_WORD1__SWIZZLE_ENABLE__SHIFT 0x1f +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS_MASK 0xffffffff +#define SQ_BUF_RSRC_WORD2__NUM_RECORDS__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X_MASK 0x7 +#define SQ_BUF_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y_MASK 0x38 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 +#define SQ_BUF_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W_MASK 0xe00 +#define SQ_BUF_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT_MASK 0x7000 +#define SQ_BUF_RSRC_WORD3__NUM_FORMAT__SHIFT 0xc +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT_MASK 0x78000 +#define SQ_BUF_RSRC_WORD3__DATA_FORMAT__SHIFT 0xf +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE_MASK 0x180000 +#define SQ_BUF_RSRC_WORD3__ELEMENT_SIZE__SHIFT 0x13 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE_MASK 0x600000 +#define SQ_BUF_RSRC_WORD3__INDEX_STRIDE__SHIFT 0x15 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE_MASK 0x800000 +#define SQ_BUF_RSRC_WORD3__ADD_TID_ENABLE__SHIFT 0x17 +#define SQ_BUF_RSRC_WORD3__ATC_MASK 0x1000000 +#define SQ_BUF_RSRC_WORD3__ATC__SHIFT 0x18 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE_MASK 0x2000000 +#define SQ_BUF_RSRC_WORD3__HASH_ENABLE__SHIFT 0x19 +#define SQ_BUF_RSRC_WORD3__HEAP_MASK 0x4000000 +#define SQ_BUF_RSRC_WORD3__HEAP__SHIFT 0x1a +#define SQ_BUF_RSRC_WORD3__MTYPE_MASK 0x38000000 +#define SQ_BUF_RSRC_WORD3__MTYPE__SHIFT 0x1b +#define SQ_BUF_RSRC_WORD3__TYPE_MASK 0xc0000000 +#define SQ_BUF_RSRC_WORD3__TYPE__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS_MASK 0xffffffff +#define SQ_IMG_RSRC_WORD0__BASE_ADDRESS__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI_MASK 0xff +#define SQ_IMG_RSRC_WORD1__BASE_ADDRESS_HI__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD1__MIN_LOD_MASK 0xfff00 +#define SQ_IMG_RSRC_WORD1__MIN_LOD__SHIFT 0x8 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT_MASK 0x3f00000 +#define SQ_IMG_RSRC_WORD1__DATA_FORMAT__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT_MASK 0x3c000000 +#define SQ_IMG_RSRC_WORD1__NUM_FORMAT__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD1__MTYPE_MASK 0xc0000000 +#define SQ_IMG_RSRC_WORD1__MTYPE__SHIFT 0x1e +#define SQ_IMG_RSRC_WORD2__WIDTH_MASK 0x3fff +#define SQ_IMG_RSRC_WORD2__WIDTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD2__HEIGHT_MASK 0xfffc000 +#define SQ_IMG_RSRC_WORD2__HEIGHT__SHIFT 0xe +#define SQ_IMG_RSRC_WORD2__PERF_MOD_MASK 0x70000000 +#define SQ_IMG_RSRC_WORD2__PERF_MOD__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD2__INTERLACED_MASK 0x80000000 +#define SQ_IMG_RSRC_WORD2__INTERLACED__SHIFT 0x1f +#define SQ_IMG_RSRC_WORD3__DST_SEL_X_MASK 0x7 +#define SQ_IMG_RSRC_WORD3__DST_SEL_X__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y_MASK 0x38 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Y__SHIFT 0x3 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z_MASK 0x1c0 +#define SQ_IMG_RSRC_WORD3__DST_SEL_Z__SHIFT 0x6 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W_MASK 0xe00 +#define SQ_IMG_RSRC_WORD3__DST_SEL_W__SHIFT 0x9 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL_MASK 0xf000 +#define SQ_IMG_RSRC_WORD3__BASE_LEVEL__SHIFT 0xc +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL_MASK 0xf0000 +#define SQ_IMG_RSRC_WORD3__LAST_LEVEL__SHIFT 0x10 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX_MASK 0x1f00000 +#define SQ_IMG_RSRC_WORD3__TILING_INDEX__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD3__POW2_PAD_MASK 0x2000000 +#define SQ_IMG_RSRC_WORD3__POW2_PAD__SHIFT 0x19 +#define SQ_IMG_RSRC_WORD3__MTYPE_MASK 0x4000000 +#define SQ_IMG_RSRC_WORD3__MTYPE__SHIFT 0x1a +#define SQ_IMG_RSRC_WORD3__ATC_MASK 0x8000000 +#define SQ_IMG_RSRC_WORD3__ATC__SHIFT 0x1b +#define SQ_IMG_RSRC_WORD3__TYPE_MASK 0xf0000000 +#define SQ_IMG_RSRC_WORD3__TYPE__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD4__DEPTH_MASK 0x1fff +#define SQ_IMG_RSRC_WORD4__DEPTH__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD4__PITCH_MASK 0x7ffe000 +#define SQ_IMG_RSRC_WORD4__PITCH__SHIFT 0xd +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY_MASK 0x1fff +#define SQ_IMG_RSRC_WORD5__BASE_ARRAY__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY_MASK 0x3ffe000 +#define SQ_IMG_RSRC_WORD5__LAST_ARRAY__SHIFT 0xd +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN_MASK 0xfff +#define SQ_IMG_RSRC_WORD6__MIN_LOD_WARN__SHIFT 0x0 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID_MASK 0xff000 +#define SQ_IMG_RSRC_WORD6__COUNTER_BANK_ID__SHIFT 0xc +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN_MASK 0x100000 +#define SQ_IMG_RSRC_WORD6__LOD_HDW_CNT_EN__SHIFT 0x14 +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN_MASK 0x200000 +#define SQ_IMG_RSRC_WORD6__COMPRESSION_EN__SHIFT 0x15 +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB_MASK 0x400000 +#define SQ_IMG_RSRC_WORD6__ALPHA_IS_ON_MSB__SHIFT 0x16 +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM_MASK 0x800000 +#define SQ_IMG_RSRC_WORD6__COLOR_TRANSFORM__SHIFT 0x17 +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS_MASK 0xf000000 +#define SQ_IMG_RSRC_WORD6__LOST_ALPHA_BITS__SHIFT 0x18 +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS_MASK 0xf0000000 +#define SQ_IMG_RSRC_WORD6__LOST_COLOR_BITS__SHIFT 0x1c +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS_MASK 0xffffffff +#define SQ_IMG_RSRC_WORD7__META_DATA_ADDRESS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_X_MASK 0x7 +#define SQ_IMG_SAMP_WORD0__CLAMP_X__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y_MASK 0x38 +#define SQ_IMG_SAMP_WORD0__CLAMP_Y__SHIFT 0x3 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z_MASK 0x1c0 +#define SQ_IMG_SAMP_WORD0__CLAMP_Z__SHIFT 0x6 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO_MASK 0xe00 +#define SQ_IMG_SAMP_WORD0__MAX_ANISO_RATIO__SHIFT 0x9 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC_MASK 0x7000 +#define SQ_IMG_SAMP_WORD0__DEPTH_COMPARE_FUNC__SHIFT 0xc +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED_MASK 0x8000 +#define SQ_IMG_SAMP_WORD0__FORCE_UNNORMALIZED__SHIFT 0xf +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD_MASK 0x70000 +#define SQ_IMG_SAMP_WORD0__ANISO_THRESHOLD__SHIFT 0x10 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC_MASK 0x80000 +#define SQ_IMG_SAMP_WORD0__MC_COORD_TRUNC__SHIFT 0x13 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA_MASK 0x100000 +#define SQ_IMG_SAMP_WORD0__FORCE_DEGAMMA__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS_MASK 0x7e00000 +#define SQ_IMG_SAMP_WORD0__ANISO_BIAS__SHIFT 0x15 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD_MASK 0x8000000 +#define SQ_IMG_SAMP_WORD0__TRUNC_COORD__SHIFT 0x1b +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP_MASK 0x10000000 +#define SQ_IMG_SAMP_WORD0__DISABLE_CUBE_WRAP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD0__FILTER_MODE_MASK 0x60000000 +#define SQ_IMG_SAMP_WORD0__FILTER_MODE__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE_MASK 0x80000000 +#define SQ_IMG_SAMP_WORD0__COMPAT_MODE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD1__MIN_LOD_MASK 0xfff +#define SQ_IMG_SAMP_WORD1__MIN_LOD__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD1__MAX_LOD_MASK 0xfff000 +#define SQ_IMG_SAMP_WORD1__MAX_LOD__SHIFT 0xc +#define SQ_IMG_SAMP_WORD1__PERF_MIP_MASK 0xf000000 +#define SQ_IMG_SAMP_WORD1__PERF_MIP__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD1__PERF_Z_MASK 0xf0000000 +#define SQ_IMG_SAMP_WORD1__PERF_Z__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_MASK 0x3fff +#define SQ_IMG_SAMP_WORD2__LOD_BIAS__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC_MASK 0xfc000 +#define SQ_IMG_SAMP_WORD2__LOD_BIAS_SEC__SHIFT 0xe +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER_MASK 0x300000 +#define SQ_IMG_SAMP_WORD2__XY_MAG_FILTER__SHIFT 0x14 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER_MASK 0xc00000 +#define SQ_IMG_SAMP_WORD2__XY_MIN_FILTER__SHIFT 0x16 +#define SQ_IMG_SAMP_WORD2__Z_FILTER_MASK 0x3000000 +#define SQ_IMG_SAMP_WORD2__Z_FILTER__SHIFT 0x18 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER_MASK 0xc000000 +#define SQ_IMG_SAMP_WORD2__MIP_FILTER__SHIFT 0x1a +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP_MASK 0x10000000 +#define SQ_IMG_SAMP_WORD2__MIP_POINT_PRECLAMP__SHIFT 0x1c +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL_MASK 0x20000000 +#define SQ_IMG_SAMP_WORD2__DISABLE_LSB_CEIL__SHIFT 0x1d +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX_MASK 0x40000000 +#define SQ_IMG_SAMP_WORD2__FILTER_PREC_FIX__SHIFT 0x1e +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE_MASK 0x80000000 +#define SQ_IMG_SAMP_WORD2__ANISO_OVERRIDE__SHIFT 0x1f +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR_MASK 0xfff +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_PTR__SHIFT 0x0 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE_MASK 0xc0000000 +#define SQ_IMG_SAMP_WORD3__BORDER_COLOR_TYPE__SHIFT 0x1e +#define SQ_FLAT_SCRATCH_WORD0__SIZE_MASK 0x7ffff +#define SQ_FLAT_SCRATCH_WORD0__SIZE__SHIFT 0x0 +#define SQ_FLAT_SCRATCH_WORD1__OFFSET_MASK 0xffffff +#define SQ_FLAT_SCRATCH_WORD1__OFFSET__SHIFT 0x0 +#define SQ_M0_GPR_IDX_WORD__INDEX_MASK 0xff +#define SQ_M0_GPR_IDX_WORD__INDEX__SHIFT 0x0 +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL_MASK 0x1000 +#define SQ_M0_GPR_IDX_WORD__VSRC0_REL__SHIFT 0xc +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL_MASK 0x2000 +#define SQ_M0_GPR_IDX_WORD__VSRC1_REL__SHIFT 0xd +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL_MASK 0x4000 +#define SQ_M0_GPR_IDX_WORD__VSRC2_REL__SHIFT 0xe +#define SQ_M0_GPR_IDX_WORD__VDST_REL_MASK 0x8000 +#define SQ_M0_GPR_IDX_WORD__VDST_REL__SHIFT 0xf +#define SQ_IND_INDEX__WAVE_ID_MASK 0xf +#define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 +#define SQ_IND_INDEX__SIMD_ID_MASK 0x30 +#define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 +#define SQ_IND_INDEX__THREAD_ID_MASK 0xfc0 +#define SQ_IND_INDEX__THREAD_ID__SHIFT 0x6 +#define SQ_IND_INDEX__AUTO_INCR_MASK 0x1000 +#define SQ_IND_INDEX__AUTO_INCR__SHIFT 0xc +#define SQ_IND_INDEX__FORCE_READ_MASK 0x2000 +#define SQ_IND_INDEX__FORCE_READ__SHIFT 0xd +#define SQ_IND_INDEX__READ_TIMEOUT_MASK 0x4000 +#define SQ_IND_INDEX__READ_TIMEOUT__SHIFT 0xe +#define SQ_IND_INDEX__UNINDEXED_MASK 0x8000 +#define SQ_IND_INDEX__UNINDEXED__SHIFT 0xf +#define SQ_IND_INDEX__INDEX_MASK 0xffff0000 +#define SQ_IND_INDEX__INDEX__SHIFT 0x10 +#define SQ_CMD__CMD_MASK 0x7 +#define SQ_CMD__CMD__SHIFT 0x0 +#define SQ_CMD__MODE_MASK 0x70 +#define SQ_CMD__MODE__SHIFT 0x4 +#define SQ_CMD__CHECK_VMID_MASK 0x80 +#define SQ_CMD__CHECK_VMID__SHIFT 0x7 +#define SQ_CMD__DATA_MASK 0x700 +#define SQ_CMD__DATA__SHIFT 0x8 +#define SQ_CMD__WAVE_ID_MASK 0xf0000 +#define SQ_CMD__WAVE_ID__SHIFT 0x10 +#define SQ_CMD__SIMD_ID_MASK 0x300000 +#define SQ_CMD__SIMD_ID__SHIFT 0x14 +#define SQ_CMD__QUEUE_ID_MASK 0x7000000 +#define SQ_CMD__QUEUE_ID__SHIFT 0x18 +#define SQ_CMD__VM_ID_MASK 0xf0000000 +#define SQ_CMD__VM_ID__SHIFT 0x1c +#define SQ_IND_DATA__DATA_MASK 0xffffffff +#define SQ_IND_DATA__DATA__SHIFT 0x0 +#define SQ_REG_TIMESTAMP__TIMESTAMP_MASK 0xff +#define SQ_REG_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0xff +#define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 +#define SQ_HV_VMID_CTRL__DEFAULT_VMID_MASK 0xf +#define SQ_HV_VMID_CTRL__DEFAULT_VMID__SHIFT 0x0 +#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK_MASK 0xffff0 +#define SQ_HV_VMID_CTRL__ALLOWED_VMID_MASK__SHIFT 0x4 +#define SQ_WAVE_INST_DW0__INST_DW0_MASK 0xffffffff +#define SQ_WAVE_INST_DW0__INST_DW0__SHIFT 0x0 +#define SQ_WAVE_INST_DW1__INST_DW1_MASK 0xffffffff +#define SQ_WAVE_INST_DW1__INST_DW1__SHIFT 0x0 +#define SQ_WAVE_PC_LO__PC_LO_MASK 0xffffffff +#define SQ_WAVE_PC_LO__PC_LO__SHIFT 0x0 +#define SQ_WAVE_PC_HI__PC_HI_MASK 0xffff +#define SQ_WAVE_PC_HI__PC_HI__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__IBUF_ST_MASK 0x7 +#define SQ_WAVE_IB_DBG0__IBUF_ST__SHIFT 0x0 +#define SQ_WAVE_IB_DBG0__PC_INVALID_MASK 0x8 +#define SQ_WAVE_IB_DBG0__PC_INVALID__SHIFT 0x3 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW_MASK 0x10 +#define SQ_WAVE_IB_DBG0__NEED_NEXT_DW__SHIFT 0x4 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT_MASK 0xe0 +#define SQ_WAVE_IB_DBG0__NO_PREFETCH_CNT__SHIFT 0x5 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR_MASK 0x300 +#define SQ_WAVE_IB_DBG0__IBUF_RPTR__SHIFT 0x8 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR_MASK 0xc00 +#define SQ_WAVE_IB_DBG0__IBUF_WPTR__SHIFT 0xa +#define SQ_WAVE_IB_DBG0__INST_STR_ST_MASK 0xf0000 +#define SQ_WAVE_IB_DBG0__INST_STR_ST__SHIFT 0x10 +#define SQ_WAVE_IB_DBG0__MISC_CNT_MASK 0xf00000 +#define SQ_WAVE_IB_DBG0__MISC_CNT__SHIFT 0x14 +#define SQ_WAVE_IB_DBG0__ECC_ST_MASK 0x3000000 +#define SQ_WAVE_IB_DBG0__ECC_ST__SHIFT 0x18 +#define SQ_WAVE_IB_DBG0__IS_HYB_MASK 0x4000000 +#define SQ_WAVE_IB_DBG0__IS_HYB__SHIFT 0x1a +#define SQ_WAVE_IB_DBG0__HYB_CNT_MASK 0x18000000 +#define SQ_WAVE_IB_DBG0__HYB_CNT__SHIFT 0x1b +#define SQ_WAVE_IB_DBG0__KILL_MASK 0x20000000 +#define SQ_WAVE_IB_DBG0__KILL__SHIFT 0x1d +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH_MASK 0x40000000 +#define SQ_WAVE_IB_DBG0__NEED_KILL_IFETCH__SHIFT 0x1e +#define SQ_WAVE_IB_DBG1__IXNACK_MASK 0x1 +#define SQ_WAVE_IB_DBG1__IXNACK__SHIFT 0x0 +#define SQ_WAVE_IB_DBG1__XNACK_MASK 0x2 +#define SQ_WAVE_IB_DBG1__XNACK__SHIFT 0x1 +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET_MASK 0x4 +#define SQ_WAVE_IB_DBG1__TA_NEED_RESET__SHIFT 0x2 +#define SQ_WAVE_IB_DBG1__XCNT_MASK 0xf0 +#define SQ_WAVE_IB_DBG1__XCNT__SHIFT 0x4 +#define SQ_WAVE_IB_DBG1__QCNT_MASK 0xf00 +#define SQ_WAVE_IB_DBG1__QCNT__SHIFT 0x8 +#define SQ_WAVE_EXEC_LO__EXEC_LO_MASK 0xffffffff +#define SQ_WAVE_EXEC_LO__EXEC_LO__SHIFT 0x0 +#define SQ_WAVE_EXEC_HI__EXEC_HI_MASK 0xffffffff +#define SQ_WAVE_EXEC_HI__EXEC_HI__SHIFT 0x0 +#define SQ_WAVE_STATUS__SCC_MASK 0x1 +#define SQ_WAVE_STATUS__SCC__SHIFT 0x0 +#define SQ_WAVE_STATUS__SPI_PRIO_MASK 0x6 +#define SQ_WAVE_STATUS__SPI_PRIO__SHIFT 0x1 +#define SQ_WAVE_STATUS__USER_PRIO_MASK 0x18 +#define SQ_WAVE_STATUS__USER_PRIO__SHIFT 0x3 +#define SQ_WAVE_STATUS__PRIV_MASK 0x20 +#define SQ_WAVE_STATUS__PRIV__SHIFT 0x5 +#define SQ_WAVE_STATUS__TRAP_EN_MASK 0x40 +#define SQ_WAVE_STATUS__TRAP_EN__SHIFT 0x6 +#define SQ_WAVE_STATUS__TTRACE_EN_MASK 0x80 +#define SQ_WAVE_STATUS__TTRACE_EN__SHIFT 0x7 +#define SQ_WAVE_STATUS__EXPORT_RDY_MASK 0x100 +#define SQ_WAVE_STATUS__EXPORT_RDY__SHIFT 0x8 +#define SQ_WAVE_STATUS__EXECZ_MASK 0x200 +#define SQ_WAVE_STATUS__EXECZ__SHIFT 0x9 +#define SQ_WAVE_STATUS__VCCZ_MASK 0x400 +#define SQ_WAVE_STATUS__VCCZ__SHIFT 0xa +#define SQ_WAVE_STATUS__IN_TG_MASK 0x800 +#define SQ_WAVE_STATUS__IN_TG__SHIFT 0xb +#define SQ_WAVE_STATUS__IN_BARRIER_MASK 0x1000 +#define SQ_WAVE_STATUS__IN_BARRIER__SHIFT 0xc +#define SQ_WAVE_STATUS__HALT_MASK 0x2000 +#define SQ_WAVE_STATUS__HALT__SHIFT 0xd +#define SQ_WAVE_STATUS__TRAP_MASK 0x4000 +#define SQ_WAVE_STATUS__TRAP__SHIFT 0xe +#define SQ_WAVE_STATUS__TTRACE_CU_EN_MASK 0x8000 +#define SQ_WAVE_STATUS__TTRACE_CU_EN__SHIFT 0xf +#define SQ_WAVE_STATUS__VALID_MASK 0x10000 +#define SQ_WAVE_STATUS__VALID__SHIFT 0x10 +#define SQ_WAVE_STATUS__ECC_ERR_MASK 0x20000 +#define SQ_WAVE_STATUS__ECC_ERR__SHIFT 0x11 +#define SQ_WAVE_STATUS__SKIP_EXPORT_MASK 0x40000 +#define SQ_WAVE_STATUS__SKIP_EXPORT__SHIFT 0x12 +#define SQ_WAVE_STATUS__PERF_EN_MASK 0x80000 +#define SQ_WAVE_STATUS__PERF_EN__SHIFT 0x13 +#define SQ_WAVE_STATUS__COND_DBG_USER_MASK 0x100000 +#define SQ_WAVE_STATUS__COND_DBG_USER__SHIFT 0x14 +#define SQ_WAVE_STATUS__COND_DBG_SYS_MASK 0x200000 +#define SQ_WAVE_STATUS__COND_DBG_SYS__SHIFT 0x15 +#define SQ_WAVE_STATUS__ALLOW_REPLAY_MASK 0x400000 +#define SQ_WAVE_STATUS__ALLOW_REPLAY__SHIFT 0x16 +#define SQ_WAVE_STATUS__INST_ATC_MASK 0x800000 +#define SQ_WAVE_STATUS__INST_ATC__SHIFT 0x17 +#define SQ_WAVE_STATUS__MUST_EXPORT_MASK 0x8000000 +#define SQ_WAVE_STATUS__MUST_EXPORT__SHIFT 0x1b +#define SQ_WAVE_MODE__FP_ROUND_MASK 0xf +#define SQ_WAVE_MODE__FP_ROUND__SHIFT 0x0 +#define SQ_WAVE_MODE__FP_DENORM_MASK 0xf0 +#define SQ_WAVE_MODE__FP_DENORM__SHIFT 0x4 +#define SQ_WAVE_MODE__DX10_CLAMP_MASK 0x100 +#define SQ_WAVE_MODE__DX10_CLAMP__SHIFT 0x8 +#define SQ_WAVE_MODE__IEEE_MASK 0x200 +#define SQ_WAVE_MODE__IEEE__SHIFT 0x9 +#define SQ_WAVE_MODE__LOD_CLAMPED_MASK 0x400 +#define SQ_WAVE_MODE__LOD_CLAMPED__SHIFT 0xa +#define SQ_WAVE_MODE__DEBUG_EN_MASK 0x800 +#define SQ_WAVE_MODE__DEBUG_EN__SHIFT 0xb +#define SQ_WAVE_MODE__EXCP_EN_MASK 0x1ff000 +#define SQ_WAVE_MODE__EXCP_EN__SHIFT 0xc +#define SQ_WAVE_MODE__GPR_IDX_EN_MASK 0x8000000 +#define SQ_WAVE_MODE__GPR_IDX_EN__SHIFT 0x1b +#define SQ_WAVE_MODE__VSKIP_MASK 0x10000000 +#define SQ_WAVE_MODE__VSKIP__SHIFT 0x1c +#define SQ_WAVE_MODE__CSP_MASK 0xe0000000 +#define SQ_WAVE_MODE__CSP__SHIFT 0x1d +#define SQ_WAVE_TRAPSTS__EXCP_MASK 0x1ff +#define SQ_WAVE_TRAPSTS__EXCP__SHIFT 0x0 +#define SQ_WAVE_TRAPSTS__SAVECTX_MASK 0x400 +#define SQ_WAVE_TRAPSTS__SAVECTX__SHIFT 0xa +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE_MASK 0x3f0000 +#define SQ_WAVE_TRAPSTS__EXCP_CYCLE__SHIFT 0x10 +#define SQ_WAVE_TRAPSTS__DP_RATE_MASK 0xe0000000 +#define SQ_WAVE_TRAPSTS__DP_RATE__SHIFT 0x1d +#define SQ_WAVE_HW_ID__WAVE_ID_MASK 0xf +#define SQ_WAVE_HW_ID__WAVE_ID__SHIFT 0x0 +#define SQ_WAVE_HW_ID__SIMD_ID_MASK 0x30 +#define SQ_WAVE_HW_ID__SIMD_ID__SHIFT 0x4 +#define SQ_WAVE_HW_ID__PIPE_ID_MASK 0xc0 +#define SQ_WAVE_HW_ID__PIPE_ID__SHIFT 0x6 +#define SQ_WAVE_HW_ID__CU_ID_MASK 0xf00 +#define SQ_WAVE_HW_ID__CU_ID__SHIFT 0x8 +#define SQ_WAVE_HW_ID__SH_ID_MASK 0x1000 +#define SQ_WAVE_HW_ID__SH_ID__SHIFT 0xc +#define SQ_WAVE_HW_ID__SE_ID_MASK 0x6000 +#define SQ_WAVE_HW_ID__SE_ID__SHIFT 0xd +#define SQ_WAVE_HW_ID__TG_ID_MASK 0xf0000 +#define SQ_WAVE_HW_ID__TG_ID__SHIFT 0x10 +#define SQ_WAVE_HW_ID__VM_ID_MASK 0xf00000 +#define SQ_WAVE_HW_ID__VM_ID__SHIFT 0x14 +#define SQ_WAVE_HW_ID__QUEUE_ID_MASK 0x7000000 +#define SQ_WAVE_HW_ID__QUEUE_ID__SHIFT 0x18 +#define SQ_WAVE_HW_ID__STATE_ID_MASK 0x38000000 +#define SQ_WAVE_HW_ID__STATE_ID__SHIFT 0x1b +#define SQ_WAVE_HW_ID__ME_ID_MASK 0xc0000000 +#define SQ_WAVE_HW_ID__ME_ID__SHIFT 0x1e +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE_MASK 0x3f +#define SQ_WAVE_GPR_ALLOC__VGPR_BASE__SHIFT 0x0 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE_MASK 0x3f00 +#define SQ_WAVE_GPR_ALLOC__VGPR_SIZE__SHIFT 0x8 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE_MASK 0x3f0000 +#define SQ_WAVE_GPR_ALLOC__SGPR_BASE__SHIFT 0x10 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE_MASK 0xf000000 +#define SQ_WAVE_GPR_ALLOC__SGPR_SIZE__SHIFT 0x18 +#define SQ_WAVE_LDS_ALLOC__LDS_BASE_MASK 0xff +#define SQ_WAVE_LDS_ALLOC__LDS_BASE__SHIFT 0x0 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE_MASK 0x1ff000 +#define SQ_WAVE_LDS_ALLOC__LDS_SIZE__SHIFT 0xc +#define SQ_WAVE_IB_STS__VM_CNT_MASK 0xf +#define SQ_WAVE_IB_STS__VM_CNT__SHIFT 0x0 +#define SQ_WAVE_IB_STS__EXP_CNT_MASK 0x70 +#define SQ_WAVE_IB_STS__EXP_CNT__SHIFT 0x4 +#define SQ_WAVE_IB_STS__LGKM_CNT_MASK 0xf00 +#define SQ_WAVE_IB_STS__LGKM_CNT__SHIFT 0x8 +#define SQ_WAVE_IB_STS__VALU_CNT_MASK 0x7000 +#define SQ_WAVE_IB_STS__VALU_CNT__SHIFT 0xc +#define SQ_WAVE_IB_STS__FIRST_REPLAY_MASK 0x8000 +#define SQ_WAVE_IB_STS__FIRST_REPLAY__SHIFT 0xf +#define SQ_WAVE_IB_STS__RCNT_MASK 0xf0000 +#define SQ_WAVE_IB_STS__RCNT__SHIFT 0x10 +#define SQ_WAVE_M0__M0_MASK 0xffffffff +#define SQ_WAVE_M0__M0__SHIFT 0x0 +#define SQ_WAVE_TBA_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WAVE_TBA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WAVE_TBA_HI__ADDR_HI_MASK 0xff +#define SQ_WAVE_TBA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WAVE_TMA_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WAVE_TMA_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WAVE_TMA_HI__ADDR_HI_MASK 0xff +#define SQ_WAVE_TMA_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WAVE_TTMP0__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP0__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP1__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP1__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP2__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP2__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP3__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP3__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP4__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP4__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP5__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP5__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP6__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP6__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP7__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP7__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP8__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP8__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP9__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP9__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP10__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP10__DATA__SHIFT 0x0 +#define SQ_WAVE_TTMP11__DATA_MASK 0xffffffff +#define SQ_WAVE_TTMP11__DATA__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__BUSY_MASK 0x1 +#define SQ_DEBUG_STS_GLOBAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY_MASK 0x2 +#define SQ_DEBUG_STS_GLOBAL__INTERRUPT_MSG_BUSY__SHIFT 0x1 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0_MASK 0xfff0 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH0__SHIFT 0x4 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1_MASK 0xfff0000 +#define SQ_DEBUG_STS_GLOBAL__WAVE_LEVEL_SH1__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0_MASK 0xff +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX0__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1_MASK 0xff00 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_GFX1__SHIFT 0x8 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED_MASK 0xff0000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_IMMED__SHIFT 0x10 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST_MASK 0xff000000 +#define SQ_DEBUG_STS_GLOBAL2__FIFO_LEVEL_HOST__SHIFT 0x18 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD_MASK 0xf +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_CMD__SHIFT 0x0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG_MASK 0x3f0 +#define SQ_DEBUG_STS_GLOBAL3__FIFO_LEVEL_HOST_REG__SHIFT 0x4 +#define SQ_DEBUG_STS_LOCAL__BUSY_MASK 0x1 +#define SQ_DEBUG_STS_LOCAL__BUSY__SHIFT 0x0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL_MASK 0x3f0 +#define SQ_DEBUG_STS_LOCAL__WAVE_LEVEL__SHIFT 0x4 +#define SQ_DEBUG_CTRL_LOCAL__UNUSED_MASK 0xff +#define SQ_DEBUG_CTRL_LOCAL__UNUSED__SHIFT 0x0 +#define SH_MEM_BASES__PRIVATE_BASE_MASK 0xffff +#define SH_MEM_BASES__PRIVATE_BASE__SHIFT 0x0 +#define SH_MEM_BASES__SHARED_BASE_MASK 0xffff0000 +#define SH_MEM_BASES__SHARED_BASE__SHIFT 0x10 +#define SH_MEM_APE1_BASE__BASE_MASK 0xffffffff +#define SH_MEM_APE1_BASE__BASE__SHIFT 0x0 +#define SH_MEM_APE1_LIMIT__LIMIT_MASK 0xffffffff +#define SH_MEM_APE1_LIMIT__LIMIT__SHIFT 0x0 +#define SH_MEM_CONFIG__ADDRESS_MODE_MASK 0x3 +#define SH_MEM_CONFIG__ADDRESS_MODE__SHIFT 0x0 +#define SH_MEM_CONFIG__PRIVATE_ATC_MASK 0x4 +#define SH_MEM_CONFIG__PRIVATE_ATC__SHIFT 0x2 +#define SH_MEM_CONFIG__ALIGNMENT_MODE_MASK 0x18 +#define SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT 0x3 +#define SH_MEM_CONFIG__DEFAULT_MTYPE_MASK 0xe0 +#define SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT 0x5 +#define SH_MEM_CONFIG__APE1_MTYPE_MASK 0x700 +#define SH_MEM_CONFIG__APE1_MTYPE__SHIFT 0x8 +#define SH_MEM_CONFIG__APE1_ATC_MASK 0x800 +#define SH_MEM_CONFIG__APE1_ATC__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_CMN__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_CMN__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID_MASK 0x1e0 +#define SQ_THREAD_TRACE_WORD_INST__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID_MASK 0x600 +#define SQ_THREAD_TRACE_WORD_INST__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE_MASK 0xf800 +#define SQ_THREAD_TRACE_WORD_INST__INST_TYPE__SHIFT 0xb +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID_MASK 0x1e0 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__WAVE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID_MASK 0x600 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__SIMD_ID__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_INST_PC_1_OF_2__PC_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI_MASK 0xffffff +#define SQ_THREAD_TRACE_WORD_INST_PC_2_OF_2__PC_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI_MASK 0xffff +#define SQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2__TIME_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI_MASK 0xffffffff +#define SQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2__TIME_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_WAVE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_WAVE__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_WAVE__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_WAVE__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_WAVE__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_MISC__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA_MASK 0xff0 +#define SQ_THREAD_TRACE_WORD_MISC__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID_MASK 0x1000 +#define SQ_THREAD_TRACE_WORD_MISC__SH_ID__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE_MASK 0xe000 +#define SQ_THREAD_TRACE_WORD_MISC__MISC_TOKEN_TYPE__SHIFT 0xd +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_WAVE_START__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_WAVE_START__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID_MASK 0x3c00 +#define SQ_THREAD_TRACE_WORD_WAVE_START__WAVE_ID__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__SIMD_ID__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER_MASK 0x1f0000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__DISPATCHER__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED_MASK 0x200000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__VS_NO_ALLOC_OR_GROUPED__SHIFT 0x15 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT_MASK 0x1fc00000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__COUNT__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID_MASK 0xe0000000 +#define SQ_THREAD_TRACE_WORD_WAVE_START__TG_ID__SHIFT 0x1d +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID_MASK 0x180 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV_MASK 0x200 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_DROPPED_PREV__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE_MASK 0x1c00 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV_MASK 0x4000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_PRIV__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP_MASK 0x8000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_OP__SHIFT 0xf +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_REG_1_OF_2__REG_ADDR__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA_MASK 0xffffffff +#define SQ_THREAD_TRACE_WORD_REG_2_OF_2__DATA__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__PIPE_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID_MASK 0x180 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__ME_ID__SHIFT 0x7 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR_MASK 0xfe00 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__REG_ADDR__SHIFT 0x9 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO_MASK 0xffff0000 +#define SQ_THREAD_TRACE_WORD_REG_CS_1_OF_2__DATA_LO__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI_MASK 0xffff +#define SQ_THREAD_TRACE_WORD_REG_CS_2_OF_2__DATA_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_EVENT__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_EVENT__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_EVENT__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE_MASK 0x1c0 +#define SQ_THREAD_TRACE_WORD_EVENT__STAGE__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE_MASK 0xfc00 +#define SQ_THREAD_TRACE_WORD_EVENT__EVENT_TYPE__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_ISSUE__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID_MASK 0x60 +#define SQ_THREAD_TRACE_WORD_ISSUE__SIMD_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0_MASK 0x300 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST0__SHIFT 0x8 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1_MASK 0xc00 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST1__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2_MASK 0x3000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST2__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3_MASK 0xc000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST3__SHIFT 0xe +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4_MASK 0x30000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST4__SHIFT 0x10 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5_MASK 0xc0000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST5__SHIFT 0x12 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6_MASK 0x300000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST6__SHIFT 0x14 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7_MASK 0xc00000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST7__SHIFT 0x16 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8_MASK 0x3000000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST8__SHIFT 0x18 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9_MASK 0xc000000 +#define SQ_THREAD_TRACE_WORD_ISSUE__INST9__SHIFT 0x1a +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE_MASK 0xf +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TOKEN_TYPE__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA_MASK 0x10 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__TIME_DELTA__SHIFT 0x4 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID_MASK 0x20 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__SH_ID__SHIFT 0x5 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID_MASK 0x3c0 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CU_ID__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK_MASK 0xc00 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR_BANK__SHIFT 0xa +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0_MASK 0x1fff000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR0__SHIFT 0xc +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO_MASK 0xfe000000 +#define SQ_THREAD_TRACE_WORD_PERF_1_OF_2__CNTR1_LO__SHIFT 0x19 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI_MASK 0x3f +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR1_HI__SHIFT 0x0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2_MASK 0x7ffc0 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR2__SHIFT 0x6 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3_MASK 0xfff80000 +#define SQ_THREAD_TRACE_WORD_PERF_2_OF_2__CNTR3__SHIFT 0x13 +#define SQ_WREXEC_EXEC_LO__ADDR_LO_MASK 0xffffffff +#define SQ_WREXEC_EXEC_LO__ADDR_LO__SHIFT 0x0 +#define SQ_WREXEC_EXEC_HI__ADDR_HI_MASK 0xffff +#define SQ_WREXEC_EXEC_HI__ADDR_HI__SHIFT 0x0 +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE_MASK 0x4000000 +#define SQ_WREXEC_EXEC_HI__FIRST_WAVE__SHIFT 0x1a +#define SQ_WREXEC_EXEC_HI__ATC_MASK 0x8000000 +#define SQ_WREXEC_EXEC_HI__ATC__SHIFT 0x1b +#define SQ_WREXEC_EXEC_HI__MTYPE_MASK 0x70000000 +#define SQ_WREXEC_EXEC_HI__MTYPE__SHIFT 0x1c +#define SQ_WREXEC_EXEC_HI__MSB_MASK 0x80000000 +#define SQ_WREXEC_EXEC_HI__MSB__SHIFT 0x1f +#define SQC_GATCL1_CNTL__RESERVED_MASK 0x3ffff +#define SQC_GATCL1_CNTL__RESERVED__SHIFT 0x0 +#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID_MASK 0x40000 +#define SQC_GATCL1_CNTL__DCACHE_INVALIDATE_ALL_VMID__SHIFT 0x12 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS_MASK 0x80000 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_MISS__SHIFT 0x13 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER_MASK 0x100000 +#define SQC_GATCL1_CNTL__DCACHE_FORCE_IN_ORDER__SHIFT 0x14 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x600000 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x15 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0x1800000 +#define SQC_GATCL1_CNTL__DCACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x17 +#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID_MASK 0x2000000 +#define SQC_GATCL1_CNTL__ICACHE_INVALIDATE_ALL_VMID__SHIFT 0x19 +#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS_MASK 0x4000000 +#define SQC_GATCL1_CNTL__ICACHE_FORCE_MISS__SHIFT 0x1a +#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER_MASK 0x8000000 +#define SQC_GATCL1_CNTL__ICACHE_FORCE_IN_ORDER__SHIFT 0x1b +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 +#define SQC_GATCL1_CNTL__ICACHE_REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC_MASK 0xff +#define SQC_ATC_EDC_GATCL1_CNT__ICACHE_DATA_SEC__SHIFT 0x0 +#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC_MASK 0xff0000 +#define SQC_ATC_EDC_GATCL1_CNT__DCACHE_DATA_SEC__SHIFT 0x10 +#define SQ_INTERRUPT_WORD_CMN__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_CMN__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_CMN__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_CMN__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_MASK 0x1 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_AUTO__WLT_MASK 0x2 +#define SQ_INTERRUPT_WORD_AUTO__WLT__SHIFT 0x1 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL_MASK 0x4 +#define SQ_INTERRUPT_WORD_AUTO__THREAD_TRACE_BUF_FULL__SHIFT 0x2 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP_MASK 0x8 +#define SQ_INTERRUPT_WORD_AUTO__REG_TIMESTAMP__SHIFT 0x3 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP_MASK 0x10 +#define SQ_INTERRUPT_WORD_AUTO__CMD_TIMESTAMP__SHIFT 0x4 +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW_MASK 0x20 +#define SQ_INTERRUPT_WORD_AUTO__HOST_CMD_OVERFLOW__SHIFT 0x5 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW_MASK 0x40 +#define SQ_INTERRUPT_WORD_AUTO__HOST_REG_OVERFLOW__SHIFT 0x6 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW_MASK 0x80 +#define SQ_INTERRUPT_WORD_AUTO__IMMED_OVERFLOW__SHIFT 0x7 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_AUTO__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_AUTO__ENCODING__SHIFT 0x1a +#define SQ_INTERRUPT_WORD_WAVE__DATA_MASK 0xff +#define SQ_INTERRUPT_WORD_WAVE__DATA__SHIFT 0x0 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID_MASK 0x100 +#define SQ_INTERRUPT_WORD_WAVE__SH_ID__SHIFT 0x8 +#define SQ_INTERRUPT_WORD_WAVE__PRIV_MASK 0x200 +#define SQ_INTERRUPT_WORD_WAVE__PRIV__SHIFT 0x9 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID_MASK 0x3c00 +#define SQ_INTERRUPT_WORD_WAVE__VM_ID__SHIFT 0xa +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID_MASK 0x3c000 +#define SQ_INTERRUPT_WORD_WAVE__WAVE_ID__SHIFT 0xe +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID_MASK 0xc0000 +#define SQ_INTERRUPT_WORD_WAVE__SIMD_ID__SHIFT 0x12 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID_MASK 0xf00000 +#define SQ_INTERRUPT_WORD_WAVE__CU_ID__SHIFT 0x14 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID_MASK 0x3000000 +#define SQ_INTERRUPT_WORD_WAVE__SE_ID__SHIFT 0x18 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING_MASK 0xc000000 +#define SQ_INTERRUPT_WORD_WAVE__ENCODING__SHIFT 0x1a +#define SQ_SOP2__SSRC0_MASK 0xff +#define SQ_SOP2__SSRC0__SHIFT 0x0 +#define SQ_SOP2__SSRC1_MASK 0xff00 +#define SQ_SOP2__SSRC1__SHIFT 0x8 +#define SQ_SOP2__SDST_MASK 0x7f0000 +#define SQ_SOP2__SDST__SHIFT 0x10 +#define SQ_SOP2__OP_MASK 0x3f800000 +#define SQ_SOP2__OP__SHIFT 0x17 +#define SQ_SOP2__ENCODING_MASK 0xc0000000 +#define SQ_SOP2__ENCODING__SHIFT 0x1e +#define SQ_VOP1__SRC0_MASK 0x1ff +#define SQ_VOP1__SRC0__SHIFT 0x0 +#define SQ_VOP1__OP_MASK 0x1fe00 +#define SQ_VOP1__OP__SHIFT 0x9 +#define SQ_VOP1__VDST_MASK 0x1fe0000 +#define SQ_VOP1__VDST__SHIFT 0x11 +#define SQ_VOP1__ENCODING_MASK 0xfe000000 +#define SQ_VOP1__ENCODING__SHIFT 0x19 +#define SQ_MTBUF_1__VADDR_MASK 0xff +#define SQ_MTBUF_1__VADDR__SHIFT 0x0 +#define SQ_MTBUF_1__VDATA_MASK 0xff00 +#define SQ_MTBUF_1__VDATA__SHIFT 0x8 +#define SQ_MTBUF_1__SRSRC_MASK 0x1f0000 +#define SQ_MTBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MTBUF_1__SLC_MASK 0x400000 +#define SQ_MTBUF_1__SLC__SHIFT 0x16 +#define SQ_MTBUF_1__TFE_MASK 0x800000 +#define SQ_MTBUF_1__TFE__SHIFT 0x17 +#define SQ_MTBUF_1__SOFFSET_MASK 0xff000000 +#define SQ_MTBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_EXP_1__VSRC0_MASK 0xff +#define SQ_EXP_1__VSRC0__SHIFT 0x0 +#define SQ_EXP_1__VSRC1_MASK 0xff00 +#define SQ_EXP_1__VSRC1__SHIFT 0x8 +#define SQ_EXP_1__VSRC2_MASK 0xff0000 +#define SQ_EXP_1__VSRC2__SHIFT 0x10 +#define SQ_EXP_1__VSRC3_MASK 0xff000000 +#define SQ_EXP_1__VSRC3__SHIFT 0x18 +#define SQ_MUBUF_1__VADDR_MASK 0xff +#define SQ_MUBUF_1__VADDR__SHIFT 0x0 +#define SQ_MUBUF_1__VDATA_MASK 0xff00 +#define SQ_MUBUF_1__VDATA__SHIFT 0x8 +#define SQ_MUBUF_1__SRSRC_MASK 0x1f0000 +#define SQ_MUBUF_1__SRSRC__SHIFT 0x10 +#define SQ_MUBUF_1__TFE_MASK 0x800000 +#define SQ_MUBUF_1__TFE__SHIFT 0x17 +#define SQ_MUBUF_1__SOFFSET_MASK 0xff000000 +#define SQ_MUBUF_1__SOFFSET__SHIFT 0x18 +#define SQ_SMEM_1__OFFSET_MASK 0xfffff +#define SQ_SMEM_1__OFFSET__SHIFT 0x0 +#define SQ_INST__ENCODING_MASK 0xffffffff +#define SQ_INST__ENCODING__SHIFT 0x0 +#define SQ_EXP_0__EN_MASK 0xf +#define SQ_EXP_0__EN__SHIFT 0x0 +#define SQ_EXP_0__TGT_MASK 0x3f0 +#define SQ_EXP_0__TGT__SHIFT 0x4 +#define SQ_EXP_0__COMPR_MASK 0x400 +#define SQ_EXP_0__COMPR__SHIFT 0xa +#define SQ_EXP_0__DONE_MASK 0x800 +#define SQ_EXP_0__DONE__SHIFT 0xb +#define SQ_EXP_0__VM_MASK 0x1000 +#define SQ_EXP_0__VM__SHIFT 0xc +#define SQ_EXP_0__ENCODING_MASK 0xfc000000 +#define SQ_EXP_0__ENCODING__SHIFT 0x1a +#define SQ_MUBUF_0__OFFSET_MASK 0xfff +#define SQ_MUBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MUBUF_0__OFFEN_MASK 0x1000 +#define SQ_MUBUF_0__OFFEN__SHIFT 0xc +#define SQ_MUBUF_0__IDXEN_MASK 0x2000 +#define SQ_MUBUF_0__IDXEN__SHIFT 0xd +#define SQ_MUBUF_0__GLC_MASK 0x4000 +#define SQ_MUBUF_0__GLC__SHIFT 0xe +#define SQ_MUBUF_0__LDS_MASK 0x10000 +#define SQ_MUBUF_0__LDS__SHIFT 0x10 +#define SQ_MUBUF_0__SLC_MASK 0x20000 +#define SQ_MUBUF_0__SLC__SHIFT 0x11 +#define SQ_MUBUF_0__OP_MASK 0x1fc0000 +#define SQ_MUBUF_0__OP__SHIFT 0x12 +#define SQ_MUBUF_0__ENCODING_MASK 0xfc000000 +#define SQ_MUBUF_0__ENCODING__SHIFT 0x1a +#define SQ_VOP_SDWA__SRC0_MASK 0xff +#define SQ_VOP_SDWA__SRC0__SHIFT 0x0 +#define SQ_VOP_SDWA__DST_SEL_MASK 0x700 +#define SQ_VOP_SDWA__DST_SEL__SHIFT 0x8 +#define SQ_VOP_SDWA__DST_UNUSED_MASK 0x1800 +#define SQ_VOP_SDWA__DST_UNUSED__SHIFT 0xb +#define SQ_VOP_SDWA__CLAMP_MASK 0x2000 +#define SQ_VOP_SDWA__CLAMP__SHIFT 0xd +#define SQ_VOP_SDWA__SRC0_SEL_MASK 0x70000 +#define SQ_VOP_SDWA__SRC0_SEL__SHIFT 0x10 +#define SQ_VOP_SDWA__SRC0_SEXT_MASK 0x80000 +#define SQ_VOP_SDWA__SRC0_SEXT__SHIFT 0x13 +#define SQ_VOP_SDWA__SRC0_NEG_MASK 0x100000 +#define SQ_VOP_SDWA__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_SDWA__SRC0_ABS_MASK 0x200000 +#define SQ_VOP_SDWA__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_SDWA__SRC1_SEL_MASK 0x7000000 +#define SQ_VOP_SDWA__SRC1_SEL__SHIFT 0x18 +#define SQ_VOP_SDWA__SRC1_SEXT_MASK 0x8000000 +#define SQ_VOP_SDWA__SRC1_SEXT__SHIFT 0x1b +#define SQ_VOP_SDWA__SRC1_NEG_MASK 0x10000000 +#define SQ_VOP_SDWA__SRC1_NEG__SHIFT 0x1c +#define SQ_VOP_SDWA__SRC1_ABS_MASK 0x20000000 +#define SQ_VOP_SDWA__SRC1_ABS__SHIFT 0x1d +#define SQ_VOP3_0__VDST_MASK 0xff +#define SQ_VOP3_0__VDST__SHIFT 0x0 +#define SQ_VOP3_0__ABS_MASK 0x700 +#define SQ_VOP3_0__ABS__SHIFT 0x8 +#define SQ_VOP3_0__CLAMP_MASK 0x8000 +#define SQ_VOP3_0__CLAMP__SHIFT 0xf +#define SQ_VOP3_0__OP_MASK 0x3ff0000 +#define SQ_VOP3_0__OP__SHIFT 0x10 +#define SQ_VOP3_0__ENCODING_MASK 0xfc000000 +#define SQ_VOP3_0__ENCODING__SHIFT 0x1a +#define SQ_VOP2__SRC0_MASK 0x1ff +#define SQ_VOP2__SRC0__SHIFT 0x0 +#define SQ_VOP2__VSRC1_MASK 0x1fe00 +#define SQ_VOP2__VSRC1__SHIFT 0x9 +#define SQ_VOP2__VDST_MASK 0x1fe0000 +#define SQ_VOP2__VDST__SHIFT 0x11 +#define SQ_VOP2__OP_MASK 0x7e000000 +#define SQ_VOP2__OP__SHIFT 0x19 +#define SQ_VOP2__ENCODING_MASK 0x80000000 +#define SQ_VOP2__ENCODING__SHIFT 0x1f +#define SQ_MTBUF_0__OFFSET_MASK 0xfff +#define SQ_MTBUF_0__OFFSET__SHIFT 0x0 +#define SQ_MTBUF_0__OFFEN_MASK 0x1000 +#define SQ_MTBUF_0__OFFEN__SHIFT 0xc +#define SQ_MTBUF_0__IDXEN_MASK 0x2000 +#define SQ_MTBUF_0__IDXEN__SHIFT 0xd +#define SQ_MTBUF_0__GLC_MASK 0x4000 +#define SQ_MTBUF_0__GLC__SHIFT 0xe +#define SQ_MTBUF_0__OP_MASK 0x78000 +#define SQ_MTBUF_0__OP__SHIFT 0xf +#define SQ_MTBUF_0__DFMT_MASK 0x780000 +#define SQ_MTBUF_0__DFMT__SHIFT 0x13 +#define SQ_MTBUF_0__NFMT_MASK 0x3800000 +#define SQ_MTBUF_0__NFMT__SHIFT 0x17 +#define SQ_MTBUF_0__ENCODING_MASK 0xfc000000 +#define SQ_MTBUF_0__ENCODING__SHIFT 0x1a +#define SQ_SOPP__SIMM16_MASK 0xffff +#define SQ_SOPP__SIMM16__SHIFT 0x0 +#define SQ_SOPP__OP_MASK 0x7f0000 +#define SQ_SOPP__OP__SHIFT 0x10 +#define SQ_SOPP__ENCODING_MASK 0xff800000 +#define SQ_SOPP__ENCODING__SHIFT 0x17 +#define SQ_FLAT_0__GLC_MASK 0x10000 +#define SQ_FLAT_0__GLC__SHIFT 0x10 +#define SQ_FLAT_0__SLC_MASK 0x20000 +#define SQ_FLAT_0__SLC__SHIFT 0x11 +#define SQ_FLAT_0__OP_MASK 0x1fc0000 +#define SQ_FLAT_0__OP__SHIFT 0x12 +#define SQ_FLAT_0__ENCODING_MASK 0xfc000000 +#define SQ_FLAT_0__ENCODING__SHIFT 0x1a +#define SQ_VOP3_0_SDST_ENC__VDST_MASK 0xff +#define SQ_VOP3_0_SDST_ENC__VDST__SHIFT 0x0 +#define SQ_VOP3_0_SDST_ENC__SDST_MASK 0x7f00 +#define SQ_VOP3_0_SDST_ENC__SDST__SHIFT 0x8 +#define SQ_VOP3_0_SDST_ENC__CLAMP_MASK 0x8000 +#define SQ_VOP3_0_SDST_ENC__CLAMP__SHIFT 0xf +#define SQ_VOP3_0_SDST_ENC__OP_MASK 0x3ff0000 +#define SQ_VOP3_0_SDST_ENC__OP__SHIFT 0x10 +#define SQ_VOP3_0_SDST_ENC__ENCODING_MASK 0xfc000000 +#define SQ_VOP3_0_SDST_ENC__ENCODING__SHIFT 0x1a +#define SQ_MIMG_1__VADDR_MASK 0xff +#define SQ_MIMG_1__VADDR__SHIFT 0x0 +#define SQ_MIMG_1__VDATA_MASK 0xff00 +#define SQ_MIMG_1__VDATA__SHIFT 0x8 +#define SQ_MIMG_1__SRSRC_MASK 0x1f0000 +#define SQ_MIMG_1__SRSRC__SHIFT 0x10 +#define SQ_MIMG_1__SSAMP_MASK 0x3e00000 +#define SQ_MIMG_1__SSAMP__SHIFT 0x15 +#define SQ_MIMG_1__D16_MASK 0x80000000 +#define SQ_MIMG_1__D16__SHIFT 0x1f +#define SQ_SOP1__SSRC0_MASK 0xff +#define SQ_SOP1__SSRC0__SHIFT 0x0 +#define SQ_SOP1__OP_MASK 0xff00 +#define SQ_SOP1__OP__SHIFT 0x8 +#define SQ_SOP1__SDST_MASK 0x7f0000 +#define SQ_SOP1__SDST__SHIFT 0x10 +#define SQ_SOP1__ENCODING_MASK 0xff800000 +#define SQ_SOP1__ENCODING__SHIFT 0x17 +#define SQ_SOPC__SSRC0_MASK 0xff +#define SQ_SOPC__SSRC0__SHIFT 0x0 +#define SQ_SOPC__SSRC1_MASK 0xff00 +#define SQ_SOPC__SSRC1__SHIFT 0x8 +#define SQ_SOPC__OP_MASK 0x7f0000 +#define SQ_SOPC__OP__SHIFT 0x10 +#define SQ_SOPC__ENCODING_MASK 0xff800000 +#define SQ_SOPC__ENCODING__SHIFT 0x17 +#define SQ_FLAT_1__ADDR_MASK 0xff +#define SQ_FLAT_1__ADDR__SHIFT 0x0 +#define SQ_FLAT_1__DATA_MASK 0xff00 +#define SQ_FLAT_1__DATA__SHIFT 0x8 +#define SQ_FLAT_1__TFE_MASK 0x800000 +#define SQ_FLAT_1__TFE__SHIFT 0x17 +#define SQ_FLAT_1__VDST_MASK 0xff000000 +#define SQ_FLAT_1__VDST__SHIFT 0x18 +#define SQ_DS_1__ADDR_MASK 0xff +#define SQ_DS_1__ADDR__SHIFT 0x0 +#define SQ_DS_1__DATA0_MASK 0xff00 +#define SQ_DS_1__DATA0__SHIFT 0x8 +#define SQ_DS_1__DATA1_MASK 0xff0000 +#define SQ_DS_1__DATA1__SHIFT 0x10 +#define SQ_DS_1__VDST_MASK 0xff000000 +#define SQ_DS_1__VDST__SHIFT 0x18 +#define SQ_VOP3_1__SRC0_MASK 0x1ff +#define SQ_VOP3_1__SRC0__SHIFT 0x0 +#define SQ_VOP3_1__SRC1_MASK 0x3fe00 +#define SQ_VOP3_1__SRC1__SHIFT 0x9 +#define SQ_VOP3_1__SRC2_MASK 0x7fc0000 +#define SQ_VOP3_1__SRC2__SHIFT 0x12 +#define SQ_VOP3_1__OMOD_MASK 0x18000000 +#define SQ_VOP3_1__OMOD__SHIFT 0x1b +#define SQ_VOP3_1__NEG_MASK 0xe0000000 +#define SQ_VOP3_1__NEG__SHIFT 0x1d +#define SQ_SMEM_0__SBASE_MASK 0x3f +#define SQ_SMEM_0__SBASE__SHIFT 0x0 +#define SQ_SMEM_0__SDATA_MASK 0x1fc0 +#define SQ_SMEM_0__SDATA__SHIFT 0x6 +#define SQ_SMEM_0__GLC_MASK 0x10000 +#define SQ_SMEM_0__GLC__SHIFT 0x10 +#define SQ_SMEM_0__IMM_MASK 0x20000 +#define SQ_SMEM_0__IMM__SHIFT 0x11 +#define SQ_SMEM_0__OP_MASK 0x3fc0000 +#define SQ_SMEM_0__OP__SHIFT 0x12 +#define SQ_SMEM_0__ENCODING_MASK 0xfc000000 +#define SQ_SMEM_0__ENCODING__SHIFT 0x1a +#define SQ_MIMG_0__DMASK_MASK 0xf00 +#define SQ_MIMG_0__DMASK__SHIFT 0x8 +#define SQ_MIMG_0__UNORM_MASK 0x1000 +#define SQ_MIMG_0__UNORM__SHIFT 0xc +#define SQ_MIMG_0__GLC_MASK 0x2000 +#define SQ_MIMG_0__GLC__SHIFT 0xd +#define SQ_MIMG_0__DA_MASK 0x4000 +#define SQ_MIMG_0__DA__SHIFT 0xe +#define SQ_MIMG_0__R128_MASK 0x8000 +#define SQ_MIMG_0__R128__SHIFT 0xf +#define SQ_MIMG_0__TFE_MASK 0x10000 +#define SQ_MIMG_0__TFE__SHIFT 0x10 +#define SQ_MIMG_0__LWE_MASK 0x20000 +#define SQ_MIMG_0__LWE__SHIFT 0x11 +#define SQ_MIMG_0__OP_MASK 0x1fc0000 +#define SQ_MIMG_0__OP__SHIFT 0x12 +#define SQ_MIMG_0__SLC_MASK 0x2000000 +#define SQ_MIMG_0__SLC__SHIFT 0x19 +#define SQ_MIMG_0__ENCODING_MASK 0xfc000000 +#define SQ_MIMG_0__ENCODING__SHIFT 0x1a +#define SQ_SOPK__SIMM16_MASK 0xffff +#define SQ_SOPK__SIMM16__SHIFT 0x0 +#define SQ_SOPK__SDST_MASK 0x7f0000 +#define SQ_SOPK__SDST__SHIFT 0x10 +#define SQ_SOPK__OP_MASK 0xf800000 +#define SQ_SOPK__OP__SHIFT 0x17 +#define SQ_SOPK__ENCODING_MASK 0xf0000000 +#define SQ_SOPK__ENCODING__SHIFT 0x1c +#define SQ_DS_0__OFFSET0_MASK 0xff +#define SQ_DS_0__OFFSET0__SHIFT 0x0 +#define SQ_DS_0__OFFSET1_MASK 0xff00 +#define SQ_DS_0__OFFSET1__SHIFT 0x8 +#define SQ_DS_0__GDS_MASK 0x10000 +#define SQ_DS_0__GDS__SHIFT 0x10 +#define SQ_DS_0__OP_MASK 0x1fe0000 +#define SQ_DS_0__OP__SHIFT 0x11 +#define SQ_DS_0__ENCODING_MASK 0xfc000000 +#define SQ_DS_0__ENCODING__SHIFT 0x1a +#define SQ_VOP_DPP__SRC0_MASK 0xff +#define SQ_VOP_DPP__SRC0__SHIFT 0x0 +#define SQ_VOP_DPP__DPP_CTRL_MASK 0x1ff00 +#define SQ_VOP_DPP__DPP_CTRL__SHIFT 0x8 +#define SQ_VOP_DPP__BOUND_CTRL_MASK 0x80000 +#define SQ_VOP_DPP__BOUND_CTRL__SHIFT 0x13 +#define SQ_VOP_DPP__SRC0_NEG_MASK 0x100000 +#define SQ_VOP_DPP__SRC0_NEG__SHIFT 0x14 +#define SQ_VOP_DPP__SRC0_ABS_MASK 0x200000 +#define SQ_VOP_DPP__SRC0_ABS__SHIFT 0x15 +#define SQ_VOP_DPP__SRC1_NEG_MASK 0x400000 +#define SQ_VOP_DPP__SRC1_NEG__SHIFT 0x16 +#define SQ_VOP_DPP__SRC1_ABS_MASK 0x800000 +#define SQ_VOP_DPP__SRC1_ABS__SHIFT 0x17 +#define SQ_VOP_DPP__BANK_MASK_MASK 0xf000000 +#define SQ_VOP_DPP__BANK_MASK__SHIFT 0x18 +#define SQ_VOP_DPP__ROW_MASK_MASK 0xf0000000 +#define SQ_VOP_DPP__ROW_MASK__SHIFT 0x1c +#define SQ_VOPC__SRC0_MASK 0x1ff +#define SQ_VOPC__SRC0__SHIFT 0x0 +#define SQ_VOPC__VSRC1_MASK 0x1fe00 +#define SQ_VOPC__VSRC1__SHIFT 0x9 +#define SQ_VOPC__OP_MASK 0x1fe0000 +#define SQ_VOPC__OP__SHIFT 0x11 +#define SQ_VOPC__ENCODING_MASK 0xfe000000 +#define SQ_VOPC__ENCODING__SHIFT 0x19 +#define SQ_VINTRP__VSRC_MASK 0xff +#define SQ_VINTRP__VSRC__SHIFT 0x0 +#define SQ_VINTRP__ATTRCHAN_MASK 0x300 +#define SQ_VINTRP__ATTRCHAN__SHIFT 0x8 +#define SQ_VINTRP__ATTR_MASK 0xfc00 +#define SQ_VINTRP__ATTR__SHIFT 0xa +#define SQ_VINTRP__OP_MASK 0x30000 +#define SQ_VINTRP__OP__SHIFT 0x10 +#define SQ_VINTRP__VDST_MASK 0x3fc0000 +#define SQ_VINTRP__VDST__SHIFT 0x12 +#define SQ_VINTRP__ENCODING_MASK 0xfc000000 +#define SQ_VINTRP__ENCODING__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL0__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL0__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL0__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL0__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL0__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL1__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL1__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL1__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL1__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL1__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL1__DBG_EN_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL1__DBG_EN__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL1__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL2__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL2__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL2__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL2__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL2__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL2__DBG_EN_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL2__DBG_EN__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL2__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL3__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL3__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL3__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL3__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL3__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL3__DBG_EN_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL3__DBG_EN__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL3__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_SX_CLK_CTRL4__ON_DELAY_MASK 0xf +#define CGTT_SX_CLK_CTRL4__ON_DELAY__SHIFT 0x0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_SX_CLK_CTRL4__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_SX_CLK_CTRL4__RESERVED_MASK 0xfff000 +#define CGTT_SX_CLK_CTRL4__RESERVED__SHIFT 0xc +#define CGTT_SX_CLK_CTRL4__DBG_EN_MASK 0x1000000 +#define CGTT_SX_CLK_CTRL4__DBG_EN__SHIFT 0x18 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_SX_CLK_CTRL4__SOFT_OVERRIDE0__SHIFT 0x1f +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS_MASK 0x1 +#define SX_DEBUG_BUSY__POS_FREE_OR_VALIDS__SHIFT 0x0 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY__POS_REQUESTER_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY__PA_SX_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY__PA_SX_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY__POS_SCBD_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY__POS_BANK3VAL3_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY__POS_BANK3VAL2_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY__POS_BANK3VAL1_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY__POS_BANK3VAL0_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY__POS_BANK2VAL3_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY__POS_BANK2VAL2_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY__POS_BANK2VAL1_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY__POS_BANK2VAL0_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY__POS_BANK1VAL3_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY__POS_BANK1VAL2_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY__POS_BANK1VAL1_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY__POS_BANK1VAL0_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY__POS_BANK0VAL3_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY__POS_BANK0VAL2_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY__POS_BANK0VAL1_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY__POS_BANK0VAL0_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY__POS_INMUX_VALID_MASK 0x100000 +#define SX_DEBUG_BUSY__POS_INMUX_VALID__SHIFT 0x14 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3_MASK 0x200000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ3__SHIFT 0x15 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2_MASK 0x400000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ2__SHIFT 0x16 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1_MASK 0x800000 +#define SX_DEBUG_BUSY__WRCTRL1_VALIDQ1__SHIFT 0x17 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3_MASK 0x1000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ3__SHIFT 0x18 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2_MASK 0x2000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ2__SHIFT 0x19 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1_MASK 0x4000000 +#define SX_DEBUG_BUSY__WRCTRL0_VALIDQ1__SHIFT 0x1a +#define SX_DEBUG_BUSY__PCCMD_VALID_MASK 0x8000000 +#define SX_DEBUG_BUSY__PCCMD_VALID__SHIFT 0x1b +#define SX_DEBUG_BUSY__VDATA1_VALID_MASK 0x10000000 +#define SX_DEBUG_BUSY__VDATA1_VALID__SHIFT 0x1c +#define SX_DEBUG_BUSY__VDATA0_VALID_MASK 0x20000000 +#define SX_DEBUG_BUSY__VDATA0_VALID__SHIFT 0x1d +#define SX_DEBUG_BUSY__CMD_BUSYORVAL_MASK 0x40000000 +#define SX_DEBUG_BUSY__CMD_BUSYORVAL__SHIFT 0x1e +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL_MASK 0x80000000 +#define SX_DEBUG_BUSY__ADDR_BUSYORVAL__SHIFT 0x1f +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_2__COL_SCBD_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0_MASK 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_FREECNT_NE0__SHIFT 0x1 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE_MASK 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ3_IDLE__SHIFT 0x2 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ3_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0_MASK 0x10 +#define SX_DEBUG_BUSY_2__COL_REQ2_FREECNT_NE0__SHIFT 0x4 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE_MASK 0x20 +#define SX_DEBUG_BUSY_2__COL_REQ2_IDLE__SHIFT 0x5 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_2__COL_REQ2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0_MASK 0x80 +#define SX_DEBUG_BUSY_2__COL_REQ1_FREECNT_NE0__SHIFT 0x7 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE_MASK 0x100 +#define SX_DEBUG_BUSY_2__COL_REQ1_IDLE__SHIFT 0x8 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_2__COL_REQ1_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0_MASK 0x400 +#define SX_DEBUG_BUSY_2__COL_REQ0_FREECNT_NE0__SHIFT 0xa +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE_MASK 0x800 +#define SX_DEBUG_BUSY_2__COL_REQ0_IDLE__SHIFT 0xb +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_2__COL_REQ0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_SENDFREE_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_FIFO_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID_MASK 0x8000 +#define SX_DEBUG_BUSY_2__COL_DBIF3_READ_VALID__SHIFT 0xf +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_SENDFREE_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_FIFO_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID_MASK 0x40000 +#define SX_DEBUG_BUSY_2__COL_DBIF2_READ_VALID__SHIFT 0x12 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_SENDFREE_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_FIFO_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID_MASK 0x200000 +#define SX_DEBUG_BUSY_2__COL_DBIF1_READ_VALID__SHIFT 0x15 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_SENDFREE_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_FIFO_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID_MASK 0x1000000 +#define SX_DEBUG_BUSY_2__COL_DBIF0_READ_VALID__SHIFT 0x18 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY_MASK 0x2000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY_MASK 0x4000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY_MASK 0x8000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY_MASK 0x10000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY_MASK 0x20000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY_MASK 0x40000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY_MASK 0x80000000 +#define SX_DEBUG_BUSY_2__COL_BUFF3_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY_3__COL_BUFF3_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY_MASK 0x200000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY_MASK 0x1000000 +#define SX_DEBUG_BUSY_3__COL_BUFF2_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY_MASK 0x2000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL3_BUSY__SHIFT 0x19 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY_MASK 0x4000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL2_BUSY__SHIFT 0x1a +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY_MASK 0x8000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL1_BUSY__SHIFT 0x1b +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY_MASK 0x10000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK3_VAL0_BUSY__SHIFT 0x1c +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY_MASK 0x20000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL3_BUSY__SHIFT 0x1d +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY_MASK 0x40000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL2_BUSY__SHIFT 0x1e +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY_MASK 0x80000000 +#define SX_DEBUG_BUSY_3__COL_BUFF1_BANK2_VAL1_BUSY__SHIFT 0x1f +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY_MASK 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK2_VAL0_BUSY__SHIFT 0x0 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY_MASK 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL3_BUSY__SHIFT 0x1 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY_MASK 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL2_BUSY__SHIFT 0x2 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY_MASK 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL1_BUSY__SHIFT 0x3 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY_MASK 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK1_VAL0_BUSY__SHIFT 0x4 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY_MASK 0x20 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL3_BUSY__SHIFT 0x5 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY_MASK 0x40 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL2_BUSY__SHIFT 0x6 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY_MASK 0x80 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL1_BUSY__SHIFT 0x7 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY_MASK 0x100 +#define SX_DEBUG_BUSY_4__COL_BUFF1_BANK0_VAL0_BUSY__SHIFT 0x8 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY_MASK 0x200 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL3_BUSY__SHIFT 0x9 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY_MASK 0x400 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL2_BUSY__SHIFT 0xa +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY_MASK 0x800 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL1_BUSY__SHIFT 0xb +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY_MASK 0x1000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK3_VAL0_BUSY__SHIFT 0xc +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY_MASK 0x2000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL3_BUSY__SHIFT 0xd +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY_MASK 0x4000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL2_BUSY__SHIFT 0xe +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY_MASK 0x8000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL1_BUSY__SHIFT 0xf +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY_MASK 0x10000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK2_VAL0_BUSY__SHIFT 0x10 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY_MASK 0x20000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL3_BUSY__SHIFT 0x11 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY_MASK 0x40000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL2_BUSY__SHIFT 0x12 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY_MASK 0x80000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL1_BUSY__SHIFT 0x13 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY_MASK 0x100000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK1_VAL0_BUSY__SHIFT 0x14 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY_MASK 0x200000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL3_BUSY__SHIFT 0x15 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY_MASK 0x400000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL2_BUSY__SHIFT 0x16 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY_MASK 0x800000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL1_BUSY__SHIFT 0x17 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY_MASK 0x1000000 +#define SX_DEBUG_BUSY_4__COL_BUFF0_BANK0_VAL0_BUSY__SHIFT 0x18 +#define SX_DEBUG_BUSY_4__RESERVED_MASK 0xfe000000 +#define SX_DEBUG_BUSY_4__RESERVED__SHIFT 0x19 +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT_MASK 0x7f +#define SX_DEBUG_1__SX_DB_QUAD_CREDIT__SHIFT 0x0 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST_MASK 0x100 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DONT_RD_DST__SHIFT 0x8 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS_MASK 0x200 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_BYPASS__SHIFT 0x9 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL_MASK 0x400 +#define SX_DEBUG_1__DISABLE_BLEND_OPT_DISCARD_PIXEL__SHIFT 0xa +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT_MASK 0x800 +#define SX_DEBUG_1__DISABLE_QUAD_PAIR_OPT__SHIFT 0xb +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT_MASK 0x1000 +#define SX_DEBUG_1__DISABLE_PIX_EN_ZERO_OPT__SHIFT 0xc +#define SX_DEBUG_1__DEBUG_DATA_MASK 0xffffe000 +#define SX_DEBUG_1__DEBUG_DATA__SHIFT 0xd +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define SX_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define SX_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define SX_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define SX_PERFCOUNTER1_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define SX_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define SX_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define SX_PS_DOWNCONVERT__MRT0_MASK 0xf +#define SX_PS_DOWNCONVERT__MRT0__SHIFT 0x0 +#define SX_PS_DOWNCONVERT__MRT1_MASK 0xf0 +#define SX_PS_DOWNCONVERT__MRT1__SHIFT 0x4 +#define SX_PS_DOWNCONVERT__MRT2_MASK 0xf00 +#define SX_PS_DOWNCONVERT__MRT2__SHIFT 0x8 +#define SX_PS_DOWNCONVERT__MRT3_MASK 0xf000 +#define SX_PS_DOWNCONVERT__MRT3__SHIFT 0xc +#define SX_PS_DOWNCONVERT__MRT4_MASK 0xf0000 +#define SX_PS_DOWNCONVERT__MRT4__SHIFT 0x10 +#define SX_PS_DOWNCONVERT__MRT5_MASK 0xf00000 +#define SX_PS_DOWNCONVERT__MRT5__SHIFT 0x14 +#define SX_PS_DOWNCONVERT__MRT6_MASK 0xf000000 +#define SX_PS_DOWNCONVERT__MRT6__SHIFT 0x18 +#define SX_PS_DOWNCONVERT__MRT7_MASK 0xf0000000 +#define SX_PS_DOWNCONVERT__MRT7__SHIFT 0x1c +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON_MASK 0xf +#define SX_BLEND_OPT_EPSILON__MRT0_EPSILON__SHIFT 0x0 +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON_MASK 0xf0 +#define SX_BLEND_OPT_EPSILON__MRT1_EPSILON__SHIFT 0x4 +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON_MASK 0xf00 +#define SX_BLEND_OPT_EPSILON__MRT2_EPSILON__SHIFT 0x8 +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON_MASK 0xf000 +#define SX_BLEND_OPT_EPSILON__MRT3_EPSILON__SHIFT 0xc +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON_MASK 0xf0000 +#define SX_BLEND_OPT_EPSILON__MRT4_EPSILON__SHIFT 0x10 +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON_MASK 0xf00000 +#define SX_BLEND_OPT_EPSILON__MRT5_EPSILON__SHIFT 0x14 +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON_MASK 0xf000000 +#define SX_BLEND_OPT_EPSILON__MRT6_EPSILON__SHIFT 0x18 +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON_MASK 0xf0000000 +#define SX_BLEND_OPT_EPSILON__MRT7_EPSILON__SHIFT 0x1c +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE_MASK 0x1 +#define SX_BLEND_OPT_CONTROL__MRT0_COLOR_OPT_DISABLE__SHIFT 0x0 +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE_MASK 0x2 +#define SX_BLEND_OPT_CONTROL__MRT0_ALPHA_OPT_DISABLE__SHIFT 0x1 +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE_MASK 0x10 +#define SX_BLEND_OPT_CONTROL__MRT1_COLOR_OPT_DISABLE__SHIFT 0x4 +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE_MASK 0x20 +#define SX_BLEND_OPT_CONTROL__MRT1_ALPHA_OPT_DISABLE__SHIFT 0x5 +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE_MASK 0x100 +#define SX_BLEND_OPT_CONTROL__MRT2_COLOR_OPT_DISABLE__SHIFT 0x8 +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE_MASK 0x200 +#define SX_BLEND_OPT_CONTROL__MRT2_ALPHA_OPT_DISABLE__SHIFT 0x9 +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE_MASK 0x1000 +#define SX_BLEND_OPT_CONTROL__MRT3_COLOR_OPT_DISABLE__SHIFT 0xc +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE_MASK 0x2000 +#define SX_BLEND_OPT_CONTROL__MRT3_ALPHA_OPT_DISABLE__SHIFT 0xd +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE_MASK 0x10000 +#define SX_BLEND_OPT_CONTROL__MRT4_COLOR_OPT_DISABLE__SHIFT 0x10 +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE_MASK 0x20000 +#define SX_BLEND_OPT_CONTROL__MRT4_ALPHA_OPT_DISABLE__SHIFT 0x11 +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE_MASK 0x100000 +#define SX_BLEND_OPT_CONTROL__MRT5_COLOR_OPT_DISABLE__SHIFT 0x14 +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE_MASK 0x200000 +#define SX_BLEND_OPT_CONTROL__MRT5_ALPHA_OPT_DISABLE__SHIFT 0x15 +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE_MASK 0x1000000 +#define SX_BLEND_OPT_CONTROL__MRT6_COLOR_OPT_DISABLE__SHIFT 0x18 +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE_MASK 0x2000000 +#define SX_BLEND_OPT_CONTROL__MRT6_ALPHA_OPT_DISABLE__SHIFT 0x19 +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE_MASK 0x10000000 +#define SX_BLEND_OPT_CONTROL__MRT7_COLOR_OPT_DISABLE__SHIFT 0x1c +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE_MASK 0x20000000 +#define SX_BLEND_OPT_CONTROL__MRT7_ALPHA_OPT_DISABLE__SHIFT 0x1d +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE_MASK 0x80000000 +#define SX_BLEND_OPT_CONTROL__PIXEN_ZERO_OPT_DISABLE__SHIFT 0x1f +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT0_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT0_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT0_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT0_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT0_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT0_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT1_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT1_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT1_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT1_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT1_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT1_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT2_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT2_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT2_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT2_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT2_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT2_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT3_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT3_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT3_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT3_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT3_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT3_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT4_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT4_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT4_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT4_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT4_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT4_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT5_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT5_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT5_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT5_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT5_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT5_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT6_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT6_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT6_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT6_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT6_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT6_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT_MASK 0x7 +#define SX_MRT7_BLEND_OPT__COLOR_SRC_OPT__SHIFT 0x0 +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT_MASK 0x70 +#define SX_MRT7_BLEND_OPT__COLOR_DST_OPT__SHIFT 0x4 +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN_MASK 0x700 +#define SX_MRT7_BLEND_OPT__COLOR_COMB_FCN__SHIFT 0x8 +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT_MASK 0x70000 +#define SX_MRT7_BLEND_OPT__ALPHA_SRC_OPT__SHIFT 0x10 +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT_MASK 0x700000 +#define SX_MRT7_BLEND_OPT__ALPHA_DST_OPT__SHIFT 0x14 +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN_MASK 0x7000000 +#define SX_MRT7_BLEND_OPT__ALPHA_COMB_FCN__SHIFT 0x18 +#define TCC_CTRL__CACHE_SIZE_MASK 0x3 +#define TCC_CTRL__CACHE_SIZE__SHIFT 0x0 +#define TCC_CTRL__RATE_MASK 0xc +#define TCC_CTRL__RATE__SHIFT 0x2 +#define TCC_CTRL__WRITEBACK_MARGIN_MASK 0xf0 +#define TCC_CTRL__WRITEBACK_MARGIN__SHIFT 0x4 +#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE_MASK 0xf00 +#define TCC_CTRL__METADATA_LATENCY_FIFO_SIZE__SHIFT 0x8 +#define TCC_CTRL__SRC_FIFO_SIZE_MASK 0xf000 +#define TCC_CTRL__SRC_FIFO_SIZE__SHIFT 0xc +#define TCC_CTRL__LATENCY_FIFO_SIZE_MASK 0xf0000 +#define TCC_CTRL__LATENCY_FIFO_SIZE__SHIFT 0x10 +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS_MASK 0x100000 +#define TCC_CTRL__WB_OR_INV_ALL_VMIDS__SHIFT 0x14 +#define TCC_CTRL__MDC_SIZE_MASK 0x3000000 +#define TCC_CTRL__MDC_SIZE__SHIFT 0x18 +#define TCC_CTRL__MDC_SECTOR_SIZE_MASK 0xc000000 +#define TCC_CTRL__MDC_SECTOR_SIZE__SHIFT 0x1a +#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE_MASK 0xf0000000 +#define TCC_CTRL__MDC_SIDEBAND_FIFO_SIZE__SHIFT 0x1c +#define TCC_EDC_CNT__SEC_COUNT_MASK 0xff +#define TCC_EDC_CNT__SEC_COUNT__SHIFT 0x0 +#define TCC_EDC_CNT__DED_COUNT_MASK 0xff0000 +#define TCC_EDC_CNT__DED_COUNT__SHIFT 0x10 +#define TCC_REDUNDANCY__MC_SEL0_MASK 0x1 +#define TCC_REDUNDANCY__MC_SEL0__SHIFT 0x0 +#define TCC_REDUNDANCY__MC_SEL1_MASK 0x2 +#define TCC_REDUNDANCY__MC_SEL1__SHIFT 0x1 +#define TCC_EXE_DISABLE__EXE_DISABLE_MASK 0x2 +#define TCC_EXE_DISABLE__EXE_DISABLE__SHIFT 0x1 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 +#define TCC_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCC_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define TCC_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TCC_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TCC_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCA_CGTT_SCLK_CTRL__ON_DELAY_MASK 0xf +#define TCA_CGTT_SCLK_CTRL__ON_DELAY__SHIFT 0x0 +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TCA_CGTT_SCLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TCA_CGTT_SCLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCC_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCC_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCC_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCC_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCC_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCC_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCC_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCC_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCC_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCC_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCC_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_CTRL__HOLE_TIMEOUT_MASK 0xf +#define TCA_CTRL__HOLE_TIMEOUT__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCA_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x18 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf0000000 +#define TCA_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x1c +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCA_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff +#define TA_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff +#define TA_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TD_CNTL__SYNC_PHASE_SH_MASK 0x3 +#define TD_CNTL__SYNC_PHASE_SH__SHIFT 0x0 +#define TD_CNTL__SYNC_PHASE_VC_SMX_MASK 0x30 +#define TD_CNTL__SYNC_PHASE_VC_SMX__SHIFT 0x4 +#define TD_CNTL__PAD_STALL_EN_MASK 0x100 +#define TD_CNTL__PAD_STALL_EN__SHIFT 0x8 +#define TD_CNTL__EXTEND_LDS_STALL_MASK 0x600 +#define TD_CNTL__EXTEND_LDS_STALL__SHIFT 0x9 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST_MASK 0x1800 +#define TD_CNTL__LDS_STALL_PHASE_ADJUST__SHIFT 0xb +#define TD_CNTL__PRECISION_COMPATIBILITY_MASK 0x8000 +#define TD_CNTL__PRECISION_COMPATIBILITY__SHIFT 0xf +#define TD_CNTL__GATHER4_FLOAT_MODE_MASK 0x10000 +#define TD_CNTL__GATHER4_FLOAT_MODE__SHIFT 0x10 +#define TD_CNTL__LD_FLOAT_MODE_MASK 0x40000 +#define TD_CNTL__LD_FLOAT_MODE__SHIFT 0x12 +#define TD_CNTL__GATHER4_DX9_MODE_MASK 0x80000 +#define TD_CNTL__GATHER4_DX9_MODE__SHIFT 0x13 +#define TD_CNTL__DISABLE_POWER_THROTTLE_MASK 0x100000 +#define TD_CNTL__DISABLE_POWER_THROTTLE__SHIFT 0x14 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO_MASK 0x200000 +#define TD_CNTL__ENABLE_ROUND_TO_ZERO__SHIFT 0x15 +#define TD_CNTL__DISABLE_D16_PACKING_MASK 0x400000 +#define TD_CNTL__DISABLE_D16_PACKING__SHIFT 0x16 +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT_MASK 0x800000 +#define TD_CNTL__DISABLE_2BIT_SIGNED_FORMAT__SHIFT 0x17 +#define TD_STATUS__BUSY_MASK 0x80000000 +#define TD_STATUS__BUSY__SHIFT 0x1f +#define TD_DEBUG_INDEX__INDEX_MASK 0x1f +#define TD_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define TD_DEBUG_DATA__DATA_MASK 0xffffffff +#define TD_DEBUG_DATA__DATA__SHIFT 0x0 +#define TD_DSM_CNTL__FORCE_SEDB_0_MASK 0x1 +#define TD_DSM_CNTL__FORCE_SEDB_0__SHIFT 0x0 +#define TD_DSM_CNTL__FORCE_SEDB_1_MASK 0x2 +#define TD_DSM_CNTL__FORCE_SEDB_1__SHIFT 0x1 +#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB_MASK 0x4 +#define TD_DSM_CNTL__EN_SINGLE_WR_SEDB__SHIFT 0x2 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define TD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TD_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TD_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define TD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TD_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TD_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 +#define TD_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TD_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TD_SCRATCH__SCRATCH_MASK 0xffffffff +#define TD_SCRATCH__SCRATCH__SHIFT 0x0 +#define TA_CNTL__FX_XNACK_CREDIT_MASK 0x7f +#define TA_CNTL__FX_XNACK_CREDIT__SHIFT 0x0 +#define TA_CNTL__SQ_XNACK_CREDIT_MASK 0x1e00 +#define TA_CNTL__SQ_XNACK_CREDIT__SHIFT 0x9 +#define TA_CNTL__TC_DATA_CREDIT_MASK 0xe000 +#define TA_CNTL__TC_DATA_CREDIT__SHIFT 0xd +#define TA_CNTL__ALIGNER_CREDIT_MASK 0x1f0000 +#define TA_CNTL__ALIGNER_CREDIT__SHIFT 0x10 +#define TA_CNTL__TD_FIFO_CREDIT_MASK 0xffc00000 +#define TA_CNTL__TD_FIFO_CREDIT__SHIFT 0x16 +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N_MASK 0x1 +#define TA_CNTL_AUX__SCOAL_DSWIZZLE_N__SHIFT 0x0 +#define TA_CNTL_AUX__RESERVED_MASK 0xe +#define TA_CNTL_AUX__RESERVED__SHIFT 0x1 +#define TA_CNTL_AUX__D16_PACK_DISABLE_MASK 0x10 +#define TA_CNTL_AUX__D16_PACK_DISABLE__SHIFT 0x4 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE_MASK 0x10000 +#define TA_CNTL_AUX__ANISO_WEIGHT_MODE__SHIFT 0x10 +#define TA_CNTL_AUX__ANISO_RATIO_LUT_MASK 0x20000 +#define TA_CNTL_AUX__ANISO_RATIO_LUT__SHIFT 0x11 +#define TA_CNTL_AUX__ANISO_TAP_MASK 0x40000 +#define TA_CNTL_AUX__ANISO_TAP__SHIFT 0x12 +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE_MASK 0x80000 +#define TA_CNTL_AUX__ANISO_MIP_ADJ_MODE__SHIFT 0x13 +#define TA_RESERVED_010C__Unused_MASK 0xffffffff +#define TA_RESERVED_010C__Unused__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR__ADDRESS_MASK 0xffffffff +#define TA_CS_BC_BASE_ADDR__ADDRESS__SHIFT 0x0 +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0xff +#define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 +#define TA_STATUS__FG_PFIFO_EMPTYB_MASK 0x1000 +#define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc +#define TA_STATUS__FG_LFIFO_EMPTYB_MASK 0x2000 +#define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd +#define TA_STATUS__FG_SFIFO_EMPTYB_MASK 0x4000 +#define TA_STATUS__FG_SFIFO_EMPTYB__SHIFT 0xe +#define TA_STATUS__FL_PFIFO_EMPTYB_MASK 0x10000 +#define TA_STATUS__FL_PFIFO_EMPTYB__SHIFT 0x10 +#define TA_STATUS__FL_LFIFO_EMPTYB_MASK 0x20000 +#define TA_STATUS__FL_LFIFO_EMPTYB__SHIFT 0x11 +#define TA_STATUS__FL_SFIFO_EMPTYB_MASK 0x40000 +#define TA_STATUS__FL_SFIFO_EMPTYB__SHIFT 0x12 +#define TA_STATUS__FA_PFIFO_EMPTYB_MASK 0x100000 +#define TA_STATUS__FA_PFIFO_EMPTYB__SHIFT 0x14 +#define TA_STATUS__FA_LFIFO_EMPTYB_MASK 0x200000 +#define TA_STATUS__FA_LFIFO_EMPTYB__SHIFT 0x15 +#define TA_STATUS__FA_SFIFO_EMPTYB_MASK 0x400000 +#define TA_STATUS__FA_SFIFO_EMPTYB__SHIFT 0x16 +#define TA_STATUS__IN_BUSY_MASK 0x1000000 +#define TA_STATUS__IN_BUSY__SHIFT 0x18 +#define TA_STATUS__FG_BUSY_MASK 0x2000000 +#define TA_STATUS__FG_BUSY__SHIFT 0x19 +#define TA_STATUS__LA_BUSY_MASK 0x4000000 +#define TA_STATUS__LA_BUSY__SHIFT 0x1a +#define TA_STATUS__FL_BUSY_MASK 0x8000000 +#define TA_STATUS__FL_BUSY__SHIFT 0x1b +#define TA_STATUS__TA_BUSY_MASK 0x10000000 +#define TA_STATUS__TA_BUSY__SHIFT 0x1c +#define TA_STATUS__FA_BUSY_MASK 0x20000000 +#define TA_STATUS__FA_BUSY__SHIFT 0x1d +#define TA_STATUS__AL_BUSY_MASK 0x40000000 +#define TA_STATUS__AL_BUSY__SHIFT 0x1e +#define TA_STATUS__BUSY_MASK 0x80000000 +#define TA_STATUS__BUSY__SHIFT 0x1f +#define TA_DEBUG_INDEX__INDEX_MASK 0x1f +#define TA_DEBUG_INDEX__INDEX__SHIFT 0x0 +#define TA_DEBUG_DATA__DATA_MASK 0xffffffff +#define TA_DEBUG_DATA__DATA__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define TA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define TA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0x3fc00 +#define TA_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0xff +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0x3fc00 +#define TA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TA_SCRATCH__SCRATCH_MASK 0xffffffff +#define TA_SCRATCH__SCRATCH__SHIFT 0x0 +#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS_MASK 0xffffffff +#define SH_HIDDEN_PRIVATE_BASE_VMID__ADDRESS__SHIFT 0x0 +#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE_MASK 0x1 +#define SH_STATIC_MEM_CONFIG__SWIZZLE_ENABLE__SHIFT 0x0 +#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE_MASK 0x6 +#define SH_STATIC_MEM_CONFIG__ELEMENT_SIZE__SHIFT 0x1 +#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE_MASK 0x18 +#define SH_STATIC_MEM_CONFIG__INDEX_STRIDE__SHIFT 0x3 +#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE_MASK 0xe0 +#define SH_STATIC_MEM_CONFIG__PRIVATE_MTYPE__SHIFT 0x5 +#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL_MASK 0xff00 +#define SH_STATIC_MEM_CONFIG__READ_ONLY_CNTL__SHIFT 0x8 +#define TCP_INVALIDATE__START_MASK 0x1 +#define TCP_INVALIDATE__START__SHIFT 0x0 +#define TCP_STATUS__TCP_BUSY_MASK 0x1 +#define TCP_STATUS__TCP_BUSY__SHIFT 0x0 +#define TCP_STATUS__INPUT_BUSY_MASK 0x2 +#define TCP_STATUS__INPUT_BUSY__SHIFT 0x1 +#define TCP_STATUS__ADRS_BUSY_MASK 0x4 +#define TCP_STATUS__ADRS_BUSY__SHIFT 0x2 +#define TCP_STATUS__TAGRAMS_BUSY_MASK 0x8 +#define TCP_STATUS__TAGRAMS_BUSY__SHIFT 0x3 +#define TCP_STATUS__CNTRL_BUSY_MASK 0x10 +#define TCP_STATUS__CNTRL_BUSY__SHIFT 0x4 +#define TCP_STATUS__LFIFO_BUSY_MASK 0x20 +#define TCP_STATUS__LFIFO_BUSY__SHIFT 0x5 +#define TCP_STATUS__READ_BUSY_MASK 0x40 +#define TCP_STATUS__READ_BUSY__SHIFT 0x6 +#define TCP_STATUS__FORMAT_BUSY_MASK 0x80 +#define TCP_STATUS__FORMAT_BUSY__SHIFT 0x7 +#define TCP_CNTL__FORCE_HIT_MASK 0x1 +#define TCP_CNTL__FORCE_HIT__SHIFT 0x0 +#define TCP_CNTL__FORCE_MISS_MASK 0x2 +#define TCP_CNTL__FORCE_MISS__SHIFT 0x1 +#define TCP_CNTL__L1_SIZE_MASK 0xc +#define TCP_CNTL__L1_SIZE__SHIFT 0x2 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE_MASK 0x10 +#define TCP_CNTL__FLAT_BUF_HASH_ENABLE__SHIFT 0x4 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE_MASK 0x20 +#define TCP_CNTL__FLAT_BUF_CACHE_SWIZZLE__SHIFT 0x5 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT_MASK 0x1f8000 +#define TCP_CNTL__FORCE_EOW_TOTAL_CNT__SHIFT 0xf +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT_MASK 0xfc00000 +#define TCP_CNTL__FORCE_EOW_TAGRAM_CNT__SHIFT 0x16 +#define TCP_CNTL__DISABLE_Z_MAP_MASK 0x10000000 +#define TCP_CNTL__DISABLE_Z_MAP__SHIFT 0x1c +#define TCP_CNTL__INV_ALL_VMIDS_MASK 0x20000000 +#define TCP_CNTL__INV_ALL_VMIDS__SHIFT 0x1d +#define TCP_CHAN_STEER_LO__CHAN0_MASK 0xf +#define TCP_CHAN_STEER_LO__CHAN0__SHIFT 0x0 +#define TCP_CHAN_STEER_LO__CHAN1_MASK 0xf0 +#define TCP_CHAN_STEER_LO__CHAN1__SHIFT 0x4 +#define TCP_CHAN_STEER_LO__CHAN2_MASK 0xf00 +#define TCP_CHAN_STEER_LO__CHAN2__SHIFT 0x8 +#define TCP_CHAN_STEER_LO__CHAN3_MASK 0xf000 +#define TCP_CHAN_STEER_LO__CHAN3__SHIFT 0xc +#define TCP_CHAN_STEER_LO__CHAN4_MASK 0xf0000 +#define TCP_CHAN_STEER_LO__CHAN4__SHIFT 0x10 +#define TCP_CHAN_STEER_LO__CHAN5_MASK 0xf00000 +#define TCP_CHAN_STEER_LO__CHAN5__SHIFT 0x14 +#define TCP_CHAN_STEER_LO__CHAN6_MASK 0xf000000 +#define TCP_CHAN_STEER_LO__CHAN6__SHIFT 0x18 +#define TCP_CHAN_STEER_LO__CHAN7_MASK 0xf0000000 +#define TCP_CHAN_STEER_LO__CHAN7__SHIFT 0x1c +#define TCP_CHAN_STEER_HI__CHAN8_MASK 0xf +#define TCP_CHAN_STEER_HI__CHAN8__SHIFT 0x0 +#define TCP_CHAN_STEER_HI__CHAN9_MASK 0xf0 +#define TCP_CHAN_STEER_HI__CHAN9__SHIFT 0x4 +#define TCP_CHAN_STEER_HI__CHANA_MASK 0xf00 +#define TCP_CHAN_STEER_HI__CHANA__SHIFT 0x8 +#define TCP_CHAN_STEER_HI__CHANB_MASK 0xf000 +#define TCP_CHAN_STEER_HI__CHANB__SHIFT 0xc +#define TCP_CHAN_STEER_HI__CHANC_MASK 0xf0000 +#define TCP_CHAN_STEER_HI__CHANC__SHIFT 0x10 +#define TCP_CHAN_STEER_HI__CHAND_MASK 0xf00000 +#define TCP_CHAN_STEER_HI__CHAND__SHIFT 0x14 +#define TCP_CHAN_STEER_HI__CHANE_MASK 0xf000000 +#define TCP_CHAN_STEER_HI__CHANE__SHIFT 0x18 +#define TCP_CHAN_STEER_HI__CHANF_MASK 0xf0000000 +#define TCP_CHAN_STEER_HI__CHANF__SHIFT 0x1c +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS_MASK 0xf +#define TCP_ADDR_CONFIG__NUM_TCC_BANKS__SHIFT 0x0 +#define TCP_ADDR_CONFIG__NUM_BANKS_MASK 0x30 +#define TCP_ADDR_CONFIG__NUM_BANKS__SHIFT 0x4 +#define TCP_ADDR_CONFIG__COLHI_WIDTH_MASK 0x1c0 +#define TCP_ADDR_CONFIG__COLHI_WIDTH__SHIFT 0x6 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI_MASK 0x200 +#define TCP_ADDR_CONFIG__RB_SPLIT_COLHI__SHIFT 0x9 +#define TCP_CREDIT__LFIFO_CREDIT_MASK 0x3ff +#define TCP_CREDIT__LFIFO_CREDIT__SHIFT 0x0 +#define TCP_CREDIT__REQ_FIFO_CREDIT_MASK 0x7f0000 +#define TCP_CREDIT__REQ_FIFO_CREDIT__SHIFT 0x10 +#define TCP_CREDIT__TD_CREDIT_MASK 0xe0000000 +#define TCP_CREDIT__TD_CREDIT__SHIFT 0x1d +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCP_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define TCP_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCP_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TCP_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define TCP_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define TCP_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0x3ff +#define TCP_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define TCP_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define TCP_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define TCP_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define TCP_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS_MASK 0x7 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_BITS__SHIFT 0x0 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS_MASK 0x700 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_BITS__SHIFT 0x8 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT_MASK 0x70000 +#define TCP_BUFFER_ADDR_HASH_CNTL__CHANNEL_XOR_COUNT__SHIFT 0x10 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT_MASK 0x7000000 +#define TCP_BUFFER_ADDR_HASH_CNTL__BANK_XOR_COUNT__SHIFT 0x18 +#define TCP_EDC_CNT__SEC_COUNT_MASK 0xff +#define TCP_EDC_CNT__SEC_COUNT__SHIFT 0x0 +#define TCP_EDC_CNT__LFIFO_SED_COUNT_MASK 0xff00 +#define TCP_EDC_CNT__LFIFO_SED_COUNT__SHIFT 0x8 +#define TCP_EDC_CNT__DED_COUNT_MASK 0xff0000 +#define TCP_EDC_CNT__DED_COUNT__SHIFT 0x10 +#define TCP_EDC_CNT__UNUSED_MASK 0xff000000 +#define TCP_EDC_CNT__UNUSED__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L1_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L1_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_0_MASK 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L1_STORE_POLICY__POLICY_1_MASK 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_1__SHIFT 0x1 +#define TC_CFG_L1_STORE_POLICY__POLICY_2_MASK 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_2__SHIFT 0x2 +#define TC_CFG_L1_STORE_POLICY__POLICY_3_MASK 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_3__SHIFT 0x3 +#define TC_CFG_L1_STORE_POLICY__POLICY_4_MASK 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_4__SHIFT 0x4 +#define TC_CFG_L1_STORE_POLICY__POLICY_5_MASK 0x20 +#define TC_CFG_L1_STORE_POLICY__POLICY_5__SHIFT 0x5 +#define TC_CFG_L1_STORE_POLICY__POLICY_6_MASK 0x40 +#define TC_CFG_L1_STORE_POLICY__POLICY_6__SHIFT 0x6 +#define TC_CFG_L1_STORE_POLICY__POLICY_7_MASK 0x80 +#define TC_CFG_L1_STORE_POLICY__POLICY_7__SHIFT 0x7 +#define TC_CFG_L1_STORE_POLICY__POLICY_8_MASK 0x100 +#define TC_CFG_L1_STORE_POLICY__POLICY_8__SHIFT 0x8 +#define TC_CFG_L1_STORE_POLICY__POLICY_9_MASK 0x200 +#define TC_CFG_L1_STORE_POLICY__POLICY_9__SHIFT 0x9 +#define TC_CFG_L1_STORE_POLICY__POLICY_10_MASK 0x400 +#define TC_CFG_L1_STORE_POLICY__POLICY_10__SHIFT 0xa +#define TC_CFG_L1_STORE_POLICY__POLICY_11_MASK 0x800 +#define TC_CFG_L1_STORE_POLICY__POLICY_11__SHIFT 0xb +#define TC_CFG_L1_STORE_POLICY__POLICY_12_MASK 0x1000 +#define TC_CFG_L1_STORE_POLICY__POLICY_12__SHIFT 0xc +#define TC_CFG_L1_STORE_POLICY__POLICY_13_MASK 0x2000 +#define TC_CFG_L1_STORE_POLICY__POLICY_13__SHIFT 0xd +#define TC_CFG_L1_STORE_POLICY__POLICY_14_MASK 0x4000 +#define TC_CFG_L1_STORE_POLICY__POLICY_14__SHIFT 0xe +#define TC_CFG_L1_STORE_POLICY__POLICY_15_MASK 0x8000 +#define TC_CFG_L1_STORE_POLICY__POLICY_15__SHIFT 0xf +#define TC_CFG_L1_STORE_POLICY__POLICY_16_MASK 0x10000 +#define TC_CFG_L1_STORE_POLICY__POLICY_16__SHIFT 0x10 +#define TC_CFG_L1_STORE_POLICY__POLICY_17_MASK 0x20000 +#define TC_CFG_L1_STORE_POLICY__POLICY_17__SHIFT 0x11 +#define TC_CFG_L1_STORE_POLICY__POLICY_18_MASK 0x40000 +#define TC_CFG_L1_STORE_POLICY__POLICY_18__SHIFT 0x12 +#define TC_CFG_L1_STORE_POLICY__POLICY_19_MASK 0x80000 +#define TC_CFG_L1_STORE_POLICY__POLICY_19__SHIFT 0x13 +#define TC_CFG_L1_STORE_POLICY__POLICY_20_MASK 0x100000 +#define TC_CFG_L1_STORE_POLICY__POLICY_20__SHIFT 0x14 +#define TC_CFG_L1_STORE_POLICY__POLICY_21_MASK 0x200000 +#define TC_CFG_L1_STORE_POLICY__POLICY_21__SHIFT 0x15 +#define TC_CFG_L1_STORE_POLICY__POLICY_22_MASK 0x400000 +#define TC_CFG_L1_STORE_POLICY__POLICY_22__SHIFT 0x16 +#define TC_CFG_L1_STORE_POLICY__POLICY_23_MASK 0x800000 +#define TC_CFG_L1_STORE_POLICY__POLICY_23__SHIFT 0x17 +#define TC_CFG_L1_STORE_POLICY__POLICY_24_MASK 0x1000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_24__SHIFT 0x18 +#define TC_CFG_L1_STORE_POLICY__POLICY_25_MASK 0x2000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_25__SHIFT 0x19 +#define TC_CFG_L1_STORE_POLICY__POLICY_26_MASK 0x4000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_26__SHIFT 0x1a +#define TC_CFG_L1_STORE_POLICY__POLICY_27_MASK 0x8000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_27__SHIFT 0x1b +#define TC_CFG_L1_STORE_POLICY__POLICY_28_MASK 0x10000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_28__SHIFT 0x1c +#define TC_CFG_L1_STORE_POLICY__POLICY_29_MASK 0x20000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_29__SHIFT 0x1d +#define TC_CFG_L1_STORE_POLICY__POLICY_30_MASK 0x40000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_30__SHIFT 0x1e +#define TC_CFG_L1_STORE_POLICY__POLICY_31_MASK 0x80000000 +#define TC_CFG_L1_STORE_POLICY__POLICY_31__SHIFT 0x1f +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_LOAD_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L2_LOAD_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY0__POLICY_0_MASK 0x3 +#define TC_CFG_L2_STORE_POLICY0__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_1_MASK 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2_MASK 0x30 +#define TC_CFG_L2_STORE_POLICY0__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_STORE_POLICY0__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4_MASK 0x300 +#define TC_CFG_L2_STORE_POLICY0__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_STORE_POLICY0__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY0__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY0__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY0__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY0__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY0__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_STORE_POLICY0__POLICY_15__SHIFT 0x1e +#define TC_CFG_L2_STORE_POLICY1__POLICY_16_MASK 0x3 +#define TC_CFG_L2_STORE_POLICY1__POLICY_16__SHIFT 0x0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_17_MASK 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_17__SHIFT 0x2 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18_MASK 0x30 +#define TC_CFG_L2_STORE_POLICY1__POLICY_18__SHIFT 0x4 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19_MASK 0xc0 +#define TC_CFG_L2_STORE_POLICY1__POLICY_19__SHIFT 0x6 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20_MASK 0x300 +#define TC_CFG_L2_STORE_POLICY1__POLICY_20__SHIFT 0x8 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21_MASK 0xc00 +#define TC_CFG_L2_STORE_POLICY1__POLICY_21__SHIFT 0xa +#define TC_CFG_L2_STORE_POLICY1__POLICY_22_MASK 0x3000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_22__SHIFT 0xc +#define TC_CFG_L2_STORE_POLICY1__POLICY_23_MASK 0xc000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_23__SHIFT 0xe +#define TC_CFG_L2_STORE_POLICY1__POLICY_24_MASK 0x30000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_24__SHIFT 0x10 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25_MASK 0xc0000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_25__SHIFT 0x12 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26_MASK 0x300000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_26__SHIFT 0x14 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27_MASK 0xc00000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_27__SHIFT 0x16 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28_MASK 0x3000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_28__SHIFT 0x18 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29_MASK 0xc000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_29__SHIFT 0x1a +#define TC_CFG_L2_STORE_POLICY1__POLICY_30_MASK 0x30000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_30__SHIFT 0x1c +#define TC_CFG_L2_STORE_POLICY1__POLICY_31_MASK 0xc0000000 +#define TC_CFG_L2_STORE_POLICY1__POLICY_31__SHIFT 0x1e +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0_MASK 0x3 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_0__SHIFT 0x0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1_MASK 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_1__SHIFT 0x2 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2_MASK 0x30 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_2__SHIFT 0x4 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3_MASK 0xc0 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_3__SHIFT 0x6 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4_MASK 0x300 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_4__SHIFT 0x8 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5_MASK 0xc00 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_5__SHIFT 0xa +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6_MASK 0x3000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_6__SHIFT 0xc +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7_MASK 0xc000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_7__SHIFT 0xe +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8_MASK 0x30000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_8__SHIFT 0x10 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9_MASK 0xc0000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_9__SHIFT 0x12 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10_MASK 0x300000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_10__SHIFT 0x14 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11_MASK 0xc00000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_11__SHIFT 0x16 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12_MASK 0x3000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_12__SHIFT 0x18 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13_MASK 0xc000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_13__SHIFT 0x1a +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14_MASK 0x30000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_14__SHIFT 0x1c +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15_MASK 0xc0000000 +#define TC_CFG_L2_ATOMIC_POLICY__POLICY_15__SHIFT 0x1e +#define TC_CFG_L1_VOLATILE__VOL_MASK 0xf +#define TC_CFG_L1_VOLATILE__VOL__SHIFT 0x0 +#define TC_CFG_L2_VOLATILE__VOL_MASK 0xf +#define TC_CFG_L2_VOLATILE__VOL__SHIFT 0x0 +#define TCP_WATCH0_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH0_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH1_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH1_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH2_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH2_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH3_ADDR_H__ADDR_MASK 0xffff +#define TCP_WATCH3_ADDR_H__ADDR__SHIFT 0x0 +#define TCP_WATCH0_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH0_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH1_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH1_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH2_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH2_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH3_ADDR_L__ADDR_MASK 0xffffffc0 +#define TCP_WATCH3_ADDR_L__ADDR__SHIFT 0x6 +#define TCP_WATCH0_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH0_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH0_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH0_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH0_CNTL__ATC_MASK 0x10000000 +#define TCP_WATCH0_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH0_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH0_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH0_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH0_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH1_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH1_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH1_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH1_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH1_CNTL__ATC_MASK 0x10000000 +#define TCP_WATCH1_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH1_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH1_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH1_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH1_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH2_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH2_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH2_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH2_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH2_CNTL__ATC_MASK 0x10000000 +#define TCP_WATCH2_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH2_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH2_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH2_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH2_CNTL__VALID__SHIFT 0x1f +#define TCP_WATCH3_CNTL__MASK_MASK 0xffffff +#define TCP_WATCH3_CNTL__MASK__SHIFT 0x0 +#define TCP_WATCH3_CNTL__VMID_MASK 0xf000000 +#define TCP_WATCH3_CNTL__VMID__SHIFT 0x18 +#define TCP_WATCH3_CNTL__ATC_MASK 0x10000000 +#define TCP_WATCH3_CNTL__ATC__SHIFT 0x1c +#define TCP_WATCH3_CNTL__MODE_MASK 0x60000000 +#define TCP_WATCH3_CNTL__MODE__SHIFT 0x1d +#define TCP_WATCH3_CNTL__VALID_MASK 0x80000000 +#define TCP_WATCH3_CNTL__VALID__SHIFT 0x1f +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID_MASK 0x2000000 +#define TCP_GATCL1_CNTL__INVALIDATE_ALL_VMID__SHIFT 0x19 +#define TCP_GATCL1_CNTL__FORCE_MISS_MASK 0x4000000 +#define TCP_GATCL1_CNTL__FORCE_MISS__SHIFT 0x1a +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER_MASK 0x8000000 +#define TCP_GATCL1_CNTL__FORCE_IN_ORDER__SHIFT 0x1b +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2_MASK 0x30000000 +#define TCP_GATCL1_CNTL__REDUCE_FIFO_DEPTH_BY_2__SHIFT 0x1c +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2_MASK 0xc0000000 +#define TCP_GATCL1_CNTL__REDUCE_CACHE_SIZE_BY_2__SHIFT 0x1e +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC_MASK 0xff +#define TCP_ATC_EDC_GATCL1_CNT__DATA_SEC__SHIFT 0x0 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0_MASK 0x1 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A0__SHIFT 0x0 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1_MASK 0x2 +#define TCP_GATCL1_DSM_CNTL__SEL_DSM_TCP_GATCL1_IRRITATOR_DATA_A1__SHIFT 0x1 +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A_MASK 0x4 +#define TCP_GATCL1_DSM_CNTL__TCP_GATCL1_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL_MASK 0x3 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_DATA_SEL__SHIFT 0x0 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x4 +#define TCP_DSM_CNTL__CACHE_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x2 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL_MASK 0x18 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_DATA_SEL__SHIFT 0x3 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE_MASK 0x20 +#define TCP_DSM_CNTL__LFIFO_RAM_IRRITATOR_SINGLE_WRITE__SHIFT 0x5 +#define TCP_CNTL2__LS_DISABLE_CLOCKS_MASK 0xff +#define TCP_CNTL2__LS_DISABLE_CLOCKS__SHIFT 0x0 +#define TD_CGTT_CTRL__ON_DELAY_MASK 0xf +#define TD_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TD_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TD_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TD_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TD_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TD_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TD_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TD_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TA_CGTT_CTRL__ON_DELAY_MASK 0xf +#define TA_CGTT_CTRL__ON_DELAY__SHIFT 0x0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define TA_CGTT_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define TA_CGTT_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define TA_CGTT_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define TA_CGTT_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define TA_CGTT_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define TA_CGTT_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define TA_CGTT_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCP_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_TCP_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_TCP_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_TCP_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define CGTT_TCI_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_TCI_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_TCI_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_TCI_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define TCI_STATUS__TCI_BUSY_MASK 0x1 +#define TCI_STATUS__TCI_BUSY__SHIFT 0x0 +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES_MASK 0xffff +#define TCI_CNTL_1__WBINVL1_NUM_CYCLES__SHIFT 0x0 +#define TCI_CNTL_1__REQ_FIFO_DEPTH_MASK 0xff0000 +#define TCI_CNTL_1__REQ_FIFO_DEPTH__SHIFT 0x10 +#define TCI_CNTL_1__WDATA_RAM_DEPTH_MASK 0xff000000 +#define TCI_CNTL_1__WDATA_RAM_DEPTH__SHIFT 0x18 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2_MASK 0x1 +#define TCI_CNTL_2__L1_INVAL_ON_WBINVL2__SHIFT 0x0 +#define TCI_CNTL_2__TCA_MAX_CREDIT_MASK 0x1fe +#define TCI_CNTL_2__TCA_MAX_CREDIT__SHIFT 0x1 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL_MASK 0x6 +#define GDS_CONFIG__SH0_GPR_PHASE_SEL__SHIFT 0x1 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL_MASK 0x18 +#define GDS_CONFIG__SH1_GPR_PHASE_SEL__SHIFT 0x3 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL_MASK 0x60 +#define GDS_CONFIG__SH2_GPR_PHASE_SEL__SHIFT 0x5 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL_MASK 0x180 +#define GDS_CONFIG__SH3_GPR_PHASE_SEL__SHIFT 0x7 +#define GDS_CNTL_STATUS__GDS_BUSY_MASK 0x1 +#define GDS_CNTL_STATUS__GDS_BUSY__SHIFT 0x0 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY_MASK 0x2 +#define GDS_CNTL_STATUS__GRBM_WBUF_BUSY__SHIFT 0x1 +#define GDS_CNTL_STATUS__ORD_APP_BUSY_MASK 0x4 +#define GDS_CNTL_STATUS__ORD_APP_BUSY__SHIFT 0x2 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT_MASK 0x8 +#define GDS_CNTL_STATUS__DS_BANK_CONFLICT__SHIFT 0x3 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT_MASK 0x10 +#define GDS_CNTL_STATUS__DS_ADDR_CONFLICT__SHIFT 0x4 +#define GDS_CNTL_STATUS__DS_WR_CLAMP_MASK 0x20 +#define GDS_CNTL_STATUS__DS_WR_CLAMP__SHIFT 0x5 +#define GDS_CNTL_STATUS__DS_RD_CLAMP_MASK 0x40 +#define GDS_CNTL_STATUS__DS_RD_CLAMP__SHIFT 0x6 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY_MASK 0x80 +#define GDS_CNTL_STATUS__GRBM_RBUF_BUSY__SHIFT 0x7 +#define GDS_CNTL_STATUS__DS_BUSY_MASK 0x100 +#define GDS_CNTL_STATUS__DS_BUSY__SHIFT 0x8 +#define GDS_CNTL_STATUS__GWS_BUSY_MASK 0x200 +#define GDS_CNTL_STATUS__GWS_BUSY__SHIFT 0x9 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY_MASK 0x400 +#define GDS_CNTL_STATUS__ORD_FIFO_BUSY__SHIFT 0xa +#define GDS_CNTL_STATUS__CREDIT_BUSY0_MASK 0x800 +#define GDS_CNTL_STATUS__CREDIT_BUSY0__SHIFT 0xb +#define GDS_CNTL_STATUS__CREDIT_BUSY1_MASK 0x1000 +#define GDS_CNTL_STATUS__CREDIT_BUSY1__SHIFT 0xc +#define GDS_CNTL_STATUS__CREDIT_BUSY2_MASK 0x2000 +#define GDS_CNTL_STATUS__CREDIT_BUSY2__SHIFT 0xd +#define GDS_CNTL_STATUS__CREDIT_BUSY3_MASK 0x4000 +#define GDS_CNTL_STATUS__CREDIT_BUSY3__SHIFT 0xe +#define GDS_ENHANCE2__MISC_MASK 0xffff +#define GDS_ENHANCE2__MISC__SHIFT 0x0 +#define GDS_ENHANCE2__UNUSED_MASK 0xffff0000 +#define GDS_ENHANCE2__UNUSED__SHIFT 0x10 +#define GDS_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 +#define GDS_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 +#define GDS_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_PROTECTION_FAULT__GRBM_MASK 0x4 +#define GDS_PROTECTION_FAULT__GRBM__SHIFT 0x2 +#define GDS_PROTECTION_FAULT__SH_ID_MASK 0x38 +#define GDS_PROTECTION_FAULT__SH_ID__SHIFT 0x3 +#define GDS_PROTECTION_FAULT__CU_ID_MASK 0x3c0 +#define GDS_PROTECTION_FAULT__CU_ID__SHIFT 0x6 +#define GDS_PROTECTION_FAULT__SIMD_ID_MASK 0xc00 +#define GDS_PROTECTION_FAULT__SIMD_ID__SHIFT 0xa +#define GDS_PROTECTION_FAULT__WAVE_ID_MASK 0xf000 +#define GDS_PROTECTION_FAULT__WAVE_ID__SHIFT 0xc +#define GDS_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 +#define GDS_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS_MASK 0x1 +#define GDS_VM_PROTECTION_FAULT__WRITE_DIS__SHIFT 0x0 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED_MASK 0x2 +#define GDS_VM_PROTECTION_FAULT__FAULT_DETECTED__SHIFT 0x1 +#define GDS_VM_PROTECTION_FAULT__GWS_MASK 0x4 +#define GDS_VM_PROTECTION_FAULT__GWS__SHIFT 0x2 +#define GDS_VM_PROTECTION_FAULT__OA_MASK 0x8 +#define GDS_VM_PROTECTION_FAULT__OA__SHIFT 0x3 +#define GDS_VM_PROTECTION_FAULT__GRBM_MASK 0x10 +#define GDS_VM_PROTECTION_FAULT__GRBM__SHIFT 0x4 +#define GDS_VM_PROTECTION_FAULT__VMID_MASK 0xf00 +#define GDS_VM_PROTECTION_FAULT__VMID__SHIFT 0x8 +#define GDS_VM_PROTECTION_FAULT__ADDRESS_MASK 0xffff0000 +#define GDS_VM_PROTECTION_FAULT__ADDRESS__SHIFT 0x10 +#define GDS_EDC_CNT__DED_MASK 0xff +#define GDS_EDC_CNT__DED__SHIFT 0x0 +#define GDS_EDC_CNT__SED_MASK 0xff00 +#define GDS_EDC_CNT__SED__SHIFT 0x8 +#define GDS_EDC_CNT__SEC_MASK 0xff0000 +#define GDS_EDC_CNT__SEC__SHIFT 0x10 +#define GDS_EDC_GRBM_CNT__DED_MASK 0xff +#define GDS_EDC_GRBM_CNT__DED__SHIFT 0x0 +#define GDS_EDC_GRBM_CNT__SEC_MASK 0xff0000 +#define GDS_EDC_GRBM_CNT__SEC__SHIFT 0x10 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED_MASK 0x1 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_PIX_DED__SHIFT 0x0 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED_MASK 0x2 +#define GDS_EDC_OA_DED__ME0_GFXHP3D_VTX_DED__SHIFT 0x1 +#define GDS_EDC_OA_DED__ME0_CS_DED_MASK 0x4 +#define GDS_EDC_OA_DED__ME0_CS_DED__SHIFT 0x2 +#define GDS_EDC_OA_DED__UNUSED0_MASK 0x8 +#define GDS_EDC_OA_DED__UNUSED0__SHIFT 0x3 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED_MASK 0x10 +#define GDS_EDC_OA_DED__ME1_PIPE0_DED__SHIFT 0x4 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED_MASK 0x20 +#define GDS_EDC_OA_DED__ME1_PIPE1_DED__SHIFT 0x5 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED_MASK 0x40 +#define GDS_EDC_OA_DED__ME1_PIPE2_DED__SHIFT 0x6 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED_MASK 0x80 +#define GDS_EDC_OA_DED__ME1_PIPE3_DED__SHIFT 0x7 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED_MASK 0x100 +#define GDS_EDC_OA_DED__ME2_PIPE0_DED__SHIFT 0x8 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED_MASK 0x200 +#define GDS_EDC_OA_DED__ME2_PIPE1_DED__SHIFT 0x9 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED_MASK 0x400 +#define GDS_EDC_OA_DED__ME2_PIPE2_DED__SHIFT 0xa +#define GDS_EDC_OA_DED__ME2_PIPE3_DED_MASK 0x800 +#define GDS_EDC_OA_DED__ME2_PIPE3_DED__SHIFT 0xb +#define GDS_EDC_OA_DED__UNUSED1_MASK 0xfffff000 +#define GDS_EDC_OA_DED__UNUSED1__SHIFT 0xc +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX_MASK 0x1f +#define GDS_DEBUG_CNTL__GDS_DEBUG_INDX__SHIFT 0x0 +#define GDS_DEBUG_CNTL__UNUSED_MASK 0xffffffe0 +#define GDS_DEBUG_CNTL__UNUSED__SHIFT 0x5 +#define GDS_DEBUG_DATA__DATA_MASK 0xffffffff +#define GDS_DEBUG_DATA__DATA__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0_MASK 0x1 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_0__SHIFT 0x0 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1_MASK 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_A_1__SHIFT 0x1 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A_MASK 0x4 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_A__SHIFT 0x2 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0_MASK 0x8 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_0__SHIFT 0x3 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1_MASK 0x10 +#define GDS_DSM_CNTL__SEL_DSM_GDS_IRRITATOR_DATA_B_1__SHIFT 0x4 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B_MASK 0x20 +#define GDS_DSM_CNTL__GDS_ENABLE_SINGLE_WRITE_B__SHIFT 0x5 +#define GDS_DSM_CNTL__UNUSED_MASK 0xffffffc0 +#define GDS_DSM_CNTL__UNUSED__SHIFT 0x6 +#define CGTT_GDS_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_GDS_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_GDS_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6_MASK 0x2000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE6__SHIFT 0x19 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5_MASK 0x4000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE5__SHIFT 0x1a +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1_MASK 0x40000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE1__SHIFT 0x1e +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0_MASK 0x80000000 +#define CGTT_GDS_CLK_CTRL__SOFT_OVERRIDE0__SHIFT 0x1f +#define GDS_RD_ADDR__READ_ADDR_MASK 0xffffffff +#define GDS_RD_ADDR__READ_ADDR__SHIFT 0x0 +#define GDS_RD_DATA__READ_DATA_MASK 0xffffffff +#define GDS_RD_DATA__READ_DATA__SHIFT 0x0 +#define GDS_RD_BURST_ADDR__BURST_ADDR_MASK 0xffffffff +#define GDS_RD_BURST_ADDR__BURST_ADDR__SHIFT 0x0 +#define GDS_RD_BURST_COUNT__BURST_COUNT_MASK 0xffffffff +#define GDS_RD_BURST_COUNT__BURST_COUNT__SHIFT 0x0 +#define GDS_RD_BURST_DATA__BURST_DATA_MASK 0xffffffff +#define GDS_RD_BURST_DATA__BURST_DATA__SHIFT 0x0 +#define GDS_WR_ADDR__WRITE_ADDR_MASK 0xffffffff +#define GDS_WR_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_DATA__WRITE_DATA_MASK 0xffffffff +#define GDS_WR_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WR_BURST_ADDR__WRITE_ADDR_MASK 0xffffffff +#define GDS_WR_BURST_ADDR__WRITE_ADDR__SHIFT 0x0 +#define GDS_WR_BURST_DATA__WRITE_DATA_MASK 0xffffffff +#define GDS_WR_BURST_DATA__WRITE_DATA__SHIFT 0x0 +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE_MASK 0xffffffff +#define GDS_WRITE_COMPLETE__WRITE_COMPLETE__SHIFT 0x0 +#define GDS_ATOM_CNTL__AINC_MASK 0x3f +#define GDS_ATOM_CNTL__AINC__SHIFT 0x0 +#define GDS_ATOM_CNTL__UNUSED1_MASK 0xc0 +#define GDS_ATOM_CNTL__UNUSED1__SHIFT 0x6 +#define GDS_ATOM_CNTL__DMODE_MASK 0x300 +#define GDS_ATOM_CNTL__DMODE__SHIFT 0x8 +#define GDS_ATOM_CNTL__UNUSED2_MASK 0xfffffc00 +#define GDS_ATOM_CNTL__UNUSED2__SHIFT 0xa +#define GDS_ATOM_COMPLETE__COMPLETE_MASK 0x1 +#define GDS_ATOM_COMPLETE__COMPLETE__SHIFT 0x0 +#define GDS_ATOM_COMPLETE__UNUSED_MASK 0xfffffffe +#define GDS_ATOM_COMPLETE__UNUSED__SHIFT 0x1 +#define GDS_ATOM_BASE__BASE_MASK 0xffff +#define GDS_ATOM_BASE__BASE__SHIFT 0x0 +#define GDS_ATOM_BASE__UNUSED_MASK 0xffff0000 +#define GDS_ATOM_BASE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_SIZE__SIZE_MASK 0xffff +#define GDS_ATOM_SIZE__SIZE__SHIFT 0x0 +#define GDS_ATOM_SIZE__UNUSED_MASK 0xffff0000 +#define GDS_ATOM_SIZE__UNUSED__SHIFT 0x10 +#define GDS_ATOM_OFFSET0__OFFSET0_MASK 0xff +#define GDS_ATOM_OFFSET0__OFFSET0__SHIFT 0x0 +#define GDS_ATOM_OFFSET0__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OFFSET0__UNUSED__SHIFT 0x8 +#define GDS_ATOM_OFFSET1__OFFSET1_MASK 0xff +#define GDS_ATOM_OFFSET1__OFFSET1__SHIFT 0x0 +#define GDS_ATOM_OFFSET1__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OFFSET1__UNUSED__SHIFT 0x8 +#define GDS_ATOM_DST__DST_MASK 0xffffffff +#define GDS_ATOM_DST__DST__SHIFT 0x0 +#define GDS_ATOM_OP__OP_MASK 0xff +#define GDS_ATOM_OP__OP__SHIFT 0x0 +#define GDS_ATOM_OP__UNUSED_MASK 0xffffff00 +#define GDS_ATOM_OP__UNUSED__SHIFT 0x8 +#define GDS_ATOM_SRC0__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC0__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC0_U__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC1__DATA__SHIFT 0x0 +#define GDS_ATOM_SRC1_U__DATA_MASK 0xffffffff +#define GDS_ATOM_SRC1_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0__DATA_MASK 0xffffffff +#define GDS_ATOM_READ0__DATA__SHIFT 0x0 +#define GDS_ATOM_READ0_U__DATA_MASK 0xffffffff +#define GDS_ATOM_READ0_U__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1__DATA_MASK 0xffffffff +#define GDS_ATOM_READ1__DATA__SHIFT 0x0 +#define GDS_ATOM_READ1_U__DATA_MASK 0xffffffff +#define GDS_ATOM_READ1_U__DATA__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__INDEX_MASK 0x3f +#define GDS_GWS_RESOURCE_CNTL__INDEX__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED_MASK 0xffffffc0 +#define GDS_GWS_RESOURCE_CNTL__UNUSED__SHIFT 0x6 +#define GDS_GWS_RESOURCE__FLAG_MASK 0x1 +#define GDS_GWS_RESOURCE__FLAG__SHIFT 0x0 +#define GDS_GWS_RESOURCE__COUNTER_MASK 0x1ffe +#define GDS_GWS_RESOURCE__COUNTER__SHIFT 0x1 +#define GDS_GWS_RESOURCE__TYPE_MASK 0x2000 +#define GDS_GWS_RESOURCE__TYPE__SHIFT 0xd +#define GDS_GWS_RESOURCE__DED_MASK 0x4000 +#define GDS_GWS_RESOURCE__DED__SHIFT 0xe +#define GDS_GWS_RESOURCE__RELEASE_ALL_MASK 0x8000 +#define GDS_GWS_RESOURCE__RELEASE_ALL__SHIFT 0xf +#define GDS_GWS_RESOURCE__HEAD_QUEUE_MASK 0xfff0000 +#define GDS_GWS_RESOURCE__HEAD_QUEUE__SHIFT 0x10 +#define GDS_GWS_RESOURCE__HEAD_VALID_MASK 0x10000000 +#define GDS_GWS_RESOURCE__HEAD_VALID__SHIFT 0x1c +#define GDS_GWS_RESOURCE__HEAD_FLAG_MASK 0x20000000 +#define GDS_GWS_RESOURCE__HEAD_FLAG__SHIFT 0x1d +#define GDS_GWS_RESOURCE__UNUSED1_MASK 0xc0000000 +#define GDS_GWS_RESOURCE__UNUSED1__SHIFT 0x1e +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT_MASK 0xffff +#define GDS_GWS_RESOURCE_CNT__RESOURCE_CNT__SHIFT 0x0 +#define GDS_GWS_RESOURCE_CNT__UNUSED_MASK 0xffff0000 +#define GDS_GWS_RESOURCE_CNT__UNUSED__SHIFT 0x10 +#define GDS_OA_CNTL__INDEX_MASK 0xf +#define GDS_OA_CNTL__INDEX__SHIFT 0x0 +#define GDS_OA_CNTL__UNUSED_MASK 0xfffffff0 +#define GDS_OA_CNTL__UNUSED__SHIFT 0x4 +#define GDS_OA_COUNTER__SPACE_AVAILABLE_MASK 0xffffffff +#define GDS_OA_COUNTER__SPACE_AVAILABLE__SHIFT 0x0 +#define GDS_OA_ADDRESS__DS_ADDRESS_MASK 0xffff +#define GDS_OA_ADDRESS__DS_ADDRESS__SHIFT 0x0 +#define GDS_OA_ADDRESS__CRAWLER_MASK 0xf0000 +#define GDS_OA_ADDRESS__CRAWLER__SHIFT 0x10 +#define GDS_OA_ADDRESS__CRAWLER_TYPE_MASK 0x300000 +#define GDS_OA_ADDRESS__CRAWLER_TYPE__SHIFT 0x14 +#define GDS_OA_ADDRESS__UNUSED_MASK 0x3fc00000 +#define GDS_OA_ADDRESS__UNUSED__SHIFT 0x16 +#define GDS_OA_ADDRESS__NO_ALLOC_MASK 0x40000000 +#define GDS_OA_ADDRESS__NO_ALLOC__SHIFT 0x1e +#define GDS_OA_ADDRESS__ENABLE_MASK 0x80000000 +#define GDS_OA_ADDRESS__ENABLE__SHIFT 0x1f +#define GDS_OA_INCDEC__VALUE_MASK 0x7fffffff +#define GDS_OA_INCDEC__VALUE__SHIFT 0x0 +#define GDS_OA_INCDEC__INCDEC_MASK 0x80000000 +#define GDS_OA_INCDEC__INCDEC__SHIFT 0x1f +#define GDS_OA_RING_SIZE__RING_SIZE_MASK 0xffffffff +#define GDS_OA_RING_SIZE__RING_SIZE__SHIFT 0x0 +#define GDS_DEBUG_REG0__spare1_MASK 0x3f +#define GDS_DEBUG_REG0__spare1__SHIFT 0x0 +#define GDS_DEBUG_REG0__write_buff_valid_MASK 0x40 +#define GDS_DEBUG_REG0__write_buff_valid__SHIFT 0x6 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr_MASK 0xf80 +#define GDS_DEBUG_REG0__wr_pixel_nxt_ptr__SHIFT 0x7 +#define GDS_DEBUG_REG0__last_pixel_ptr_MASK 0x1000 +#define GDS_DEBUG_REG0__last_pixel_ptr__SHIFT 0xc +#define GDS_DEBUG_REG0__cstate_MASK 0x1e000 +#define GDS_DEBUG_REG0__cstate__SHIFT 0xd +#define GDS_DEBUG_REG0__buff_write_MASK 0x20000 +#define GDS_DEBUG_REG0__buff_write__SHIFT 0x11 +#define GDS_DEBUG_REG0__flush_request_MASK 0x40000 +#define GDS_DEBUG_REG0__flush_request__SHIFT 0x12 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete_MASK 0x80000 +#define GDS_DEBUG_REG0__wr_buffer_wr_complete__SHIFT 0x13 +#define GDS_DEBUG_REG0__wbuf_fifo_empty_MASK 0x100000 +#define GDS_DEBUG_REG0__wbuf_fifo_empty__SHIFT 0x14 +#define GDS_DEBUG_REG0__wbuf_fifo_full_MASK 0x200000 +#define GDS_DEBUG_REG0__wbuf_fifo_full__SHIFT 0x15 +#define GDS_DEBUG_REG0__spare_MASK 0xffc00000 +#define GDS_DEBUG_REG0__spare__SHIFT 0x16 +#define GDS_DEBUG_REG1__tag_hit_MASK 0x1 +#define GDS_DEBUG_REG1__tag_hit__SHIFT 0x0 +#define GDS_DEBUG_REG1__tag_miss_MASK 0x2 +#define GDS_DEBUG_REG1__tag_miss__SHIFT 0x1 +#define GDS_DEBUG_REG1__pixel_addr_MASK 0x1fffc +#define GDS_DEBUG_REG1__pixel_addr__SHIFT 0x2 +#define GDS_DEBUG_REG1__pixel_vld_MASK 0x20000 +#define GDS_DEBUG_REG1__pixel_vld__SHIFT 0x11 +#define GDS_DEBUG_REG1__data_ready_MASK 0x40000 +#define GDS_DEBUG_REG1__data_ready__SHIFT 0x12 +#define GDS_DEBUG_REG1__awaiting_data_MASK 0x80000 +#define GDS_DEBUG_REG1__awaiting_data__SHIFT 0x13 +#define GDS_DEBUG_REG1__addr_fifo_full_MASK 0x100000 +#define GDS_DEBUG_REG1__addr_fifo_full__SHIFT 0x14 +#define GDS_DEBUG_REG1__addr_fifo_empty_MASK 0x200000 +#define GDS_DEBUG_REG1__addr_fifo_empty__SHIFT 0x15 +#define GDS_DEBUG_REG1__buffer_loaded_MASK 0x400000 +#define GDS_DEBUG_REG1__buffer_loaded__SHIFT 0x16 +#define GDS_DEBUG_REG1__buffer_invalid_MASK 0x800000 +#define GDS_DEBUG_REG1__buffer_invalid__SHIFT 0x17 +#define GDS_DEBUG_REG1__spare_MASK 0xff000000 +#define GDS_DEBUG_REG1__spare__SHIFT 0x18 +#define GDS_DEBUG_REG2__ds_full_MASK 0x1 +#define GDS_DEBUG_REG2__ds_full__SHIFT 0x0 +#define GDS_DEBUG_REG2__ds_credit_avail_MASK 0x2 +#define GDS_DEBUG_REG2__ds_credit_avail__SHIFT 0x1 +#define GDS_DEBUG_REG2__ord_idx_free_MASK 0x4 +#define GDS_DEBUG_REG2__ord_idx_free__SHIFT 0x2 +#define GDS_DEBUG_REG2__cmd_write_MASK 0x8 +#define GDS_DEBUG_REG2__cmd_write__SHIFT 0x3 +#define GDS_DEBUG_REG2__app_sel_MASK 0xf0 +#define GDS_DEBUG_REG2__app_sel__SHIFT 0x4 +#define GDS_DEBUG_REG2__req_MASK 0x7fff00 +#define GDS_DEBUG_REG2__req__SHIFT 0x8 +#define GDS_DEBUG_REG2__spare_MASK 0xff800000 +#define GDS_DEBUG_REG2__spare__SHIFT 0x17 +#define GDS_DEBUG_REG3__pipe_num_busy_MASK 0x7ff +#define GDS_DEBUG_REG3__pipe_num_busy__SHIFT 0x0 +#define GDS_DEBUG_REG3__pipe0_busy_num_MASK 0x7800 +#define GDS_DEBUG_REG3__pipe0_busy_num__SHIFT 0xb +#define GDS_DEBUG_REG3__spare_MASK 0xffff8000 +#define GDS_DEBUG_REG3__spare__SHIFT 0xf +#define GDS_DEBUG_REG4__gws_busy_MASK 0x1 +#define GDS_DEBUG_REG4__gws_busy__SHIFT 0x0 +#define GDS_DEBUG_REG4__gws_req_MASK 0x2 +#define GDS_DEBUG_REG4__gws_req__SHIFT 0x1 +#define GDS_DEBUG_REG4__gws_out_stall_MASK 0x4 +#define GDS_DEBUG_REG4__gws_out_stall__SHIFT 0x2 +#define GDS_DEBUG_REG4__cur_reso_MASK 0x1f8 +#define GDS_DEBUG_REG4__cur_reso__SHIFT 0x3 +#define GDS_DEBUG_REG4__cur_reso_head_valid_MASK 0x200 +#define GDS_DEBUG_REG4__cur_reso_head_valid__SHIFT 0x9 +#define GDS_DEBUG_REG4__cur_reso_head_dirty_MASK 0x400 +#define GDS_DEBUG_REG4__cur_reso_head_dirty__SHIFT 0xa +#define GDS_DEBUG_REG4__cur_reso_head_flag_MASK 0x800 +#define GDS_DEBUG_REG4__cur_reso_head_flag__SHIFT 0xb +#define GDS_DEBUG_REG4__cur_reso_fed_MASK 0x1000 +#define GDS_DEBUG_REG4__cur_reso_fed__SHIFT 0xc +#define GDS_DEBUG_REG4__cur_reso_barrier_MASK 0x2000 +#define GDS_DEBUG_REG4__cur_reso_barrier__SHIFT 0xd +#define GDS_DEBUG_REG4__cur_reso_flag_MASK 0x4000 +#define GDS_DEBUG_REG4__cur_reso_flag__SHIFT 0xe +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0_MASK 0x8000 +#define GDS_DEBUG_REG4__cur_reso_cnt_gt0__SHIFT 0xf +#define GDS_DEBUG_REG4__credit_cnt_gt0_MASK 0x10000 +#define GDS_DEBUG_REG4__credit_cnt_gt0__SHIFT 0x10 +#define GDS_DEBUG_REG4__cmd_write_MASK 0x20000 +#define GDS_DEBUG_REG4__cmd_write__SHIFT 0x11 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr_MASK 0x40000 +#define GDS_DEBUG_REG4__grbm_gws_reso_wr__SHIFT 0x12 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd_MASK 0x80000 +#define GDS_DEBUG_REG4__grbm_gws_reso_rd__SHIFT 0x13 +#define GDS_DEBUG_REG4__ram_read_busy_MASK 0x100000 +#define GDS_DEBUG_REG4__ram_read_busy__SHIFT 0x14 +#define GDS_DEBUG_REG4__gws_bulkfree_MASK 0x200000 +#define GDS_DEBUG_REG4__gws_bulkfree__SHIFT 0x15 +#define GDS_DEBUG_REG4__ram_gws_re_MASK 0x400000 +#define GDS_DEBUG_REG4__ram_gws_re__SHIFT 0x16 +#define GDS_DEBUG_REG4__ram_gws_we_MASK 0x800000 +#define GDS_DEBUG_REG4__ram_gws_we__SHIFT 0x17 +#define GDS_DEBUG_REG4__spare_MASK 0xff000000 +#define GDS_DEBUG_REG4__spare__SHIFT 0x18 +#define GDS_DEBUG_REG5__write_dis_MASK 0x1 +#define GDS_DEBUG_REG5__write_dis__SHIFT 0x0 +#define GDS_DEBUG_REG5__dec_error_MASK 0x2 +#define GDS_DEBUG_REG5__dec_error__SHIFT 0x1 +#define GDS_DEBUG_REG5__alloc_opco_error_MASK 0x4 +#define GDS_DEBUG_REG5__alloc_opco_error__SHIFT 0x2 +#define GDS_DEBUG_REG5__dealloc_opco_error_MASK 0x8 +#define GDS_DEBUG_REG5__dealloc_opco_error__SHIFT 0x3 +#define GDS_DEBUG_REG5__wrap_opco_error_MASK 0x10 +#define GDS_DEBUG_REG5__wrap_opco_error__SHIFT 0x4 +#define GDS_DEBUG_REG5__spare_MASK 0xe0 +#define GDS_DEBUG_REG5__spare__SHIFT 0x5 +#define GDS_DEBUG_REG5__error_ds_address_MASK 0x3fff00 +#define GDS_DEBUG_REG5__error_ds_address__SHIFT 0x8 +#define GDS_DEBUG_REG5__spare1_MASK 0xffc00000 +#define GDS_DEBUG_REG5__spare1__SHIFT 0x16 +#define GDS_DEBUG_REG6__oa_busy_MASK 0x1 +#define GDS_DEBUG_REG6__oa_busy__SHIFT 0x0 +#define GDS_DEBUG_REG6__counters_enabled_MASK 0x1e +#define GDS_DEBUG_REG6__counters_enabled__SHIFT 0x1 +#define GDS_DEBUG_REG6__counters_busy_MASK 0x1fffe0 +#define GDS_DEBUG_REG6__counters_busy__SHIFT 0x5 +#define GDS_DEBUG_REG6__spare_MASK 0xffe00000 +#define GDS_DEBUG_REG6__spare__SHIFT 0x15 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER0_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER1_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER2_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT_MASK 0x3ff +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT__SHIFT 0x0 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1_MASK 0xffc00 +#define GDS_PERFCOUNTER3_SELECT__PERFCOUNTER_SELECT1__SHIFT 0xa +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE_MASK 0xf00000 +#define GDS_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT 0x14 +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define GDS_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define GDS_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2_MASK 0x3ff +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT2__SHIFT 0x0 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3_MASK 0xffc00 +#define GDS_PERFCOUNTER0_SELECT1__PERFCOUNTER_SELECT3__SHIFT 0xa +#define GDS_VMID0_BASE__BASE_MASK 0xffff +#define GDS_VMID0_BASE__BASE__SHIFT 0x0 +#define GDS_VMID1_BASE__BASE_MASK 0xffff +#define GDS_VMID1_BASE__BASE__SHIFT 0x0 +#define GDS_VMID2_BASE__BASE_MASK 0xffff +#define GDS_VMID2_BASE__BASE__SHIFT 0x0 +#define GDS_VMID3_BASE__BASE_MASK 0xffff +#define GDS_VMID3_BASE__BASE__SHIFT 0x0 +#define GDS_VMID4_BASE__BASE_MASK 0xffff +#define GDS_VMID4_BASE__BASE__SHIFT 0x0 +#define GDS_VMID5_BASE__BASE_MASK 0xffff +#define GDS_VMID5_BASE__BASE__SHIFT 0x0 +#define GDS_VMID6_BASE__BASE_MASK 0xffff +#define GDS_VMID6_BASE__BASE__SHIFT 0x0 +#define GDS_VMID7_BASE__BASE_MASK 0xffff +#define GDS_VMID7_BASE__BASE__SHIFT 0x0 +#define GDS_VMID8_BASE__BASE_MASK 0xffff +#define GDS_VMID8_BASE__BASE__SHIFT 0x0 +#define GDS_VMID9_BASE__BASE_MASK 0xffff +#define GDS_VMID9_BASE__BASE__SHIFT 0x0 +#define GDS_VMID10_BASE__BASE_MASK 0xffff +#define GDS_VMID10_BASE__BASE__SHIFT 0x0 +#define GDS_VMID11_BASE__BASE_MASK 0xffff +#define GDS_VMID11_BASE__BASE__SHIFT 0x0 +#define GDS_VMID12_BASE__BASE_MASK 0xffff +#define GDS_VMID12_BASE__BASE__SHIFT 0x0 +#define GDS_VMID13_BASE__BASE_MASK 0xffff +#define GDS_VMID13_BASE__BASE__SHIFT 0x0 +#define GDS_VMID14_BASE__BASE_MASK 0xffff +#define GDS_VMID14_BASE__BASE__SHIFT 0x0 +#define GDS_VMID15_BASE__BASE_MASK 0xffff +#define GDS_VMID15_BASE__BASE__SHIFT 0x0 +#define GDS_VMID0_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID0_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID1_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID1_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID2_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID2_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID3_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID3_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID4_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID4_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID5_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID5_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID6_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID6_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID7_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID7_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID8_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID8_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID9_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID9_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID10_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID10_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID11_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID11_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID12_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID12_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID13_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID13_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID14_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID14_SIZE__SIZE__SHIFT 0x0 +#define GDS_VMID15_SIZE__SIZE_MASK 0x1ffff +#define GDS_VMID15_SIZE__SIZE__SHIFT 0x0 +#define GDS_GWS_VMID0__BASE_MASK 0x3f +#define GDS_GWS_VMID0__BASE__SHIFT 0x0 +#define GDS_GWS_VMID0__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID0__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID1__BASE_MASK 0x3f +#define GDS_GWS_VMID1__BASE__SHIFT 0x0 +#define GDS_GWS_VMID1__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID1__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID2__BASE_MASK 0x3f +#define GDS_GWS_VMID2__BASE__SHIFT 0x0 +#define GDS_GWS_VMID2__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID2__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID3__BASE_MASK 0x3f +#define GDS_GWS_VMID3__BASE__SHIFT 0x0 +#define GDS_GWS_VMID3__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID3__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID4__BASE_MASK 0x3f +#define GDS_GWS_VMID4__BASE__SHIFT 0x0 +#define GDS_GWS_VMID4__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID4__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID5__BASE_MASK 0x3f +#define GDS_GWS_VMID5__BASE__SHIFT 0x0 +#define GDS_GWS_VMID5__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID5__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID6__BASE_MASK 0x3f +#define GDS_GWS_VMID6__BASE__SHIFT 0x0 +#define GDS_GWS_VMID6__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID6__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID7__BASE_MASK 0x3f +#define GDS_GWS_VMID7__BASE__SHIFT 0x0 +#define GDS_GWS_VMID7__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID7__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID8__BASE_MASK 0x3f +#define GDS_GWS_VMID8__BASE__SHIFT 0x0 +#define GDS_GWS_VMID8__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID8__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID9__BASE_MASK 0x3f +#define GDS_GWS_VMID9__BASE__SHIFT 0x0 +#define GDS_GWS_VMID9__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID9__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID10__BASE_MASK 0x3f +#define GDS_GWS_VMID10__BASE__SHIFT 0x0 +#define GDS_GWS_VMID10__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID10__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID11__BASE_MASK 0x3f +#define GDS_GWS_VMID11__BASE__SHIFT 0x0 +#define GDS_GWS_VMID11__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID11__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID12__BASE_MASK 0x3f +#define GDS_GWS_VMID12__BASE__SHIFT 0x0 +#define GDS_GWS_VMID12__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID12__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID13__BASE_MASK 0x3f +#define GDS_GWS_VMID13__BASE__SHIFT 0x0 +#define GDS_GWS_VMID13__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID13__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID14__BASE_MASK 0x3f +#define GDS_GWS_VMID14__BASE__SHIFT 0x0 +#define GDS_GWS_VMID14__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID14__SIZE__SHIFT 0x10 +#define GDS_GWS_VMID15__BASE_MASK 0x3f +#define GDS_GWS_VMID15__BASE__SHIFT 0x0 +#define GDS_GWS_VMID15__SIZE_MASK 0x7f0000 +#define GDS_GWS_VMID15__SIZE__SHIFT 0x10 +#define GDS_OA_VMID0__MASK_MASK 0xffff +#define GDS_OA_VMID0__MASK__SHIFT 0x0 +#define GDS_OA_VMID0__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID0__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID1__MASK_MASK 0xffff +#define GDS_OA_VMID1__MASK__SHIFT 0x0 +#define GDS_OA_VMID1__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID1__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID2__MASK_MASK 0xffff +#define GDS_OA_VMID2__MASK__SHIFT 0x0 +#define GDS_OA_VMID2__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID2__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID3__MASK_MASK 0xffff +#define GDS_OA_VMID3__MASK__SHIFT 0x0 +#define GDS_OA_VMID3__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID3__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID4__MASK_MASK 0xffff +#define GDS_OA_VMID4__MASK__SHIFT 0x0 +#define GDS_OA_VMID4__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID4__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID5__MASK_MASK 0xffff +#define GDS_OA_VMID5__MASK__SHIFT 0x0 +#define GDS_OA_VMID5__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID5__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID6__MASK_MASK 0xffff +#define GDS_OA_VMID6__MASK__SHIFT 0x0 +#define GDS_OA_VMID6__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID6__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID7__MASK_MASK 0xffff +#define GDS_OA_VMID7__MASK__SHIFT 0x0 +#define GDS_OA_VMID7__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID7__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID8__MASK_MASK 0xffff +#define GDS_OA_VMID8__MASK__SHIFT 0x0 +#define GDS_OA_VMID8__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID8__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID9__MASK_MASK 0xffff +#define GDS_OA_VMID9__MASK__SHIFT 0x0 +#define GDS_OA_VMID9__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID9__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID10__MASK_MASK 0xffff +#define GDS_OA_VMID10__MASK__SHIFT 0x0 +#define GDS_OA_VMID10__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID10__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID11__MASK_MASK 0xffff +#define GDS_OA_VMID11__MASK__SHIFT 0x0 +#define GDS_OA_VMID11__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID11__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID12__MASK_MASK 0xffff +#define GDS_OA_VMID12__MASK__SHIFT 0x0 +#define GDS_OA_VMID12__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID12__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID13__MASK_MASK 0xffff +#define GDS_OA_VMID13__MASK__SHIFT 0x0 +#define GDS_OA_VMID13__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID13__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID14__MASK_MASK 0xffff +#define GDS_OA_VMID14__MASK__SHIFT 0x0 +#define GDS_OA_VMID14__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID14__UNUSED__SHIFT 0x10 +#define GDS_OA_VMID15__MASK_MASK 0xffff +#define GDS_OA_VMID15__MASK__SHIFT 0x0 +#define GDS_OA_VMID15__UNUSED_MASK 0xffff0000 +#define GDS_OA_VMID15__UNUSED__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE0_RESET_MASK 0x1 +#define GDS_GWS_RESET0__RESOURCE0_RESET__SHIFT 0x0 +#define GDS_GWS_RESET0__RESOURCE1_RESET_MASK 0x2 +#define GDS_GWS_RESET0__RESOURCE1_RESET__SHIFT 0x1 +#define GDS_GWS_RESET0__RESOURCE2_RESET_MASK 0x4 +#define GDS_GWS_RESET0__RESOURCE2_RESET__SHIFT 0x2 +#define GDS_GWS_RESET0__RESOURCE3_RESET_MASK 0x8 +#define GDS_GWS_RESET0__RESOURCE3_RESET__SHIFT 0x3 +#define GDS_GWS_RESET0__RESOURCE4_RESET_MASK 0x10 +#define GDS_GWS_RESET0__RESOURCE4_RESET__SHIFT 0x4 +#define GDS_GWS_RESET0__RESOURCE5_RESET_MASK 0x20 +#define GDS_GWS_RESET0__RESOURCE5_RESET__SHIFT 0x5 +#define GDS_GWS_RESET0__RESOURCE6_RESET_MASK 0x40 +#define GDS_GWS_RESET0__RESOURCE6_RESET__SHIFT 0x6 +#define GDS_GWS_RESET0__RESOURCE7_RESET_MASK 0x80 +#define GDS_GWS_RESET0__RESOURCE7_RESET__SHIFT 0x7 +#define GDS_GWS_RESET0__RESOURCE8_RESET_MASK 0x100 +#define GDS_GWS_RESET0__RESOURCE8_RESET__SHIFT 0x8 +#define GDS_GWS_RESET0__RESOURCE9_RESET_MASK 0x200 +#define GDS_GWS_RESET0__RESOURCE9_RESET__SHIFT 0x9 +#define GDS_GWS_RESET0__RESOURCE10_RESET_MASK 0x400 +#define GDS_GWS_RESET0__RESOURCE10_RESET__SHIFT 0xa +#define GDS_GWS_RESET0__RESOURCE11_RESET_MASK 0x800 +#define GDS_GWS_RESET0__RESOURCE11_RESET__SHIFT 0xb +#define GDS_GWS_RESET0__RESOURCE12_RESET_MASK 0x1000 +#define GDS_GWS_RESET0__RESOURCE12_RESET__SHIFT 0xc +#define GDS_GWS_RESET0__RESOURCE13_RESET_MASK 0x2000 +#define GDS_GWS_RESET0__RESOURCE13_RESET__SHIFT 0xd +#define GDS_GWS_RESET0__RESOURCE14_RESET_MASK 0x4000 +#define GDS_GWS_RESET0__RESOURCE14_RESET__SHIFT 0xe +#define GDS_GWS_RESET0__RESOURCE15_RESET_MASK 0x8000 +#define GDS_GWS_RESET0__RESOURCE15_RESET__SHIFT 0xf +#define GDS_GWS_RESET0__RESOURCE16_RESET_MASK 0x10000 +#define GDS_GWS_RESET0__RESOURCE16_RESET__SHIFT 0x10 +#define GDS_GWS_RESET0__RESOURCE17_RESET_MASK 0x20000 +#define GDS_GWS_RESET0__RESOURCE17_RESET__SHIFT 0x11 +#define GDS_GWS_RESET0__RESOURCE18_RESET_MASK 0x40000 +#define GDS_GWS_RESET0__RESOURCE18_RESET__SHIFT 0x12 +#define GDS_GWS_RESET0__RESOURCE19_RESET_MASK 0x80000 +#define GDS_GWS_RESET0__RESOURCE19_RESET__SHIFT 0x13 +#define GDS_GWS_RESET0__RESOURCE20_RESET_MASK 0x100000 +#define GDS_GWS_RESET0__RESOURCE20_RESET__SHIFT 0x14 +#define GDS_GWS_RESET0__RESOURCE21_RESET_MASK 0x200000 +#define GDS_GWS_RESET0__RESOURCE21_RESET__SHIFT 0x15 +#define GDS_GWS_RESET0__RESOURCE22_RESET_MASK 0x400000 +#define GDS_GWS_RESET0__RESOURCE22_RESET__SHIFT 0x16 +#define GDS_GWS_RESET0__RESOURCE23_RESET_MASK 0x800000 +#define GDS_GWS_RESET0__RESOURCE23_RESET__SHIFT 0x17 +#define GDS_GWS_RESET0__RESOURCE24_RESET_MASK 0x1000000 +#define GDS_GWS_RESET0__RESOURCE24_RESET__SHIFT 0x18 +#define GDS_GWS_RESET0__RESOURCE25_RESET_MASK 0x2000000 +#define GDS_GWS_RESET0__RESOURCE25_RESET__SHIFT 0x19 +#define GDS_GWS_RESET0__RESOURCE26_RESET_MASK 0x4000000 +#define GDS_GWS_RESET0__RESOURCE26_RESET__SHIFT 0x1a +#define GDS_GWS_RESET0__RESOURCE27_RESET_MASK 0x8000000 +#define GDS_GWS_RESET0__RESOURCE27_RESET__SHIFT 0x1b +#define GDS_GWS_RESET0__RESOURCE28_RESET_MASK 0x10000000 +#define GDS_GWS_RESET0__RESOURCE28_RESET__SHIFT 0x1c +#define GDS_GWS_RESET0__RESOURCE29_RESET_MASK 0x20000000 +#define GDS_GWS_RESET0__RESOURCE29_RESET__SHIFT 0x1d +#define GDS_GWS_RESET0__RESOURCE30_RESET_MASK 0x40000000 +#define GDS_GWS_RESET0__RESOURCE30_RESET__SHIFT 0x1e +#define GDS_GWS_RESET0__RESOURCE31_RESET_MASK 0x80000000 +#define GDS_GWS_RESET0__RESOURCE31_RESET__SHIFT 0x1f +#define GDS_GWS_RESET1__RESOURCE32_RESET_MASK 0x1 +#define GDS_GWS_RESET1__RESOURCE32_RESET__SHIFT 0x0 +#define GDS_GWS_RESET1__RESOURCE33_RESET_MASK 0x2 +#define GDS_GWS_RESET1__RESOURCE33_RESET__SHIFT 0x1 +#define GDS_GWS_RESET1__RESOURCE34_RESET_MASK 0x4 +#define GDS_GWS_RESET1__RESOURCE34_RESET__SHIFT 0x2 +#define GDS_GWS_RESET1__RESOURCE35_RESET_MASK 0x8 +#define GDS_GWS_RESET1__RESOURCE35_RESET__SHIFT 0x3 +#define GDS_GWS_RESET1__RESOURCE36_RESET_MASK 0x10 +#define GDS_GWS_RESET1__RESOURCE36_RESET__SHIFT 0x4 +#define GDS_GWS_RESET1__RESOURCE37_RESET_MASK 0x20 +#define GDS_GWS_RESET1__RESOURCE37_RESET__SHIFT 0x5 +#define GDS_GWS_RESET1__RESOURCE38_RESET_MASK 0x40 +#define GDS_GWS_RESET1__RESOURCE38_RESET__SHIFT 0x6 +#define GDS_GWS_RESET1__RESOURCE39_RESET_MASK 0x80 +#define GDS_GWS_RESET1__RESOURCE39_RESET__SHIFT 0x7 +#define GDS_GWS_RESET1__RESOURCE40_RESET_MASK 0x100 +#define GDS_GWS_RESET1__RESOURCE40_RESET__SHIFT 0x8 +#define GDS_GWS_RESET1__RESOURCE41_RESET_MASK 0x200 +#define GDS_GWS_RESET1__RESOURCE41_RESET__SHIFT 0x9 +#define GDS_GWS_RESET1__RESOURCE42_RESET_MASK 0x400 +#define GDS_GWS_RESET1__RESOURCE42_RESET__SHIFT 0xa +#define GDS_GWS_RESET1__RESOURCE43_RESET_MASK 0x800 +#define GDS_GWS_RESET1__RESOURCE43_RESET__SHIFT 0xb +#define GDS_GWS_RESET1__RESOURCE44_RESET_MASK 0x1000 +#define GDS_GWS_RESET1__RESOURCE44_RESET__SHIFT 0xc +#define GDS_GWS_RESET1__RESOURCE45_RESET_MASK 0x2000 +#define GDS_GWS_RESET1__RESOURCE45_RESET__SHIFT 0xd +#define GDS_GWS_RESET1__RESOURCE46_RESET_MASK 0x4000 +#define GDS_GWS_RESET1__RESOURCE46_RESET__SHIFT 0xe +#define GDS_GWS_RESET1__RESOURCE47_RESET_MASK 0x8000 +#define GDS_GWS_RESET1__RESOURCE47_RESET__SHIFT 0xf +#define GDS_GWS_RESET1__RESOURCE48_RESET_MASK 0x10000 +#define GDS_GWS_RESET1__RESOURCE48_RESET__SHIFT 0x10 +#define GDS_GWS_RESET1__RESOURCE49_RESET_MASK 0x20000 +#define GDS_GWS_RESET1__RESOURCE49_RESET__SHIFT 0x11 +#define GDS_GWS_RESET1__RESOURCE50_RESET_MASK 0x40000 +#define GDS_GWS_RESET1__RESOURCE50_RESET__SHIFT 0x12 +#define GDS_GWS_RESET1__RESOURCE51_RESET_MASK 0x80000 +#define GDS_GWS_RESET1__RESOURCE51_RESET__SHIFT 0x13 +#define GDS_GWS_RESET1__RESOURCE52_RESET_MASK 0x100000 +#define GDS_GWS_RESET1__RESOURCE52_RESET__SHIFT 0x14 +#define GDS_GWS_RESET1__RESOURCE53_RESET_MASK 0x200000 +#define GDS_GWS_RESET1__RESOURCE53_RESET__SHIFT 0x15 +#define GDS_GWS_RESET1__RESOURCE54_RESET_MASK 0x400000 +#define GDS_GWS_RESET1__RESOURCE54_RESET__SHIFT 0x16 +#define GDS_GWS_RESET1__RESOURCE55_RESET_MASK 0x800000 +#define GDS_GWS_RESET1__RESOURCE55_RESET__SHIFT 0x17 +#define GDS_GWS_RESET1__RESOURCE56_RESET_MASK 0x1000000 +#define GDS_GWS_RESET1__RESOURCE56_RESET__SHIFT 0x18 +#define GDS_GWS_RESET1__RESOURCE57_RESET_MASK 0x2000000 +#define GDS_GWS_RESET1__RESOURCE57_RESET__SHIFT 0x19 +#define GDS_GWS_RESET1__RESOURCE58_RESET_MASK 0x4000000 +#define GDS_GWS_RESET1__RESOURCE58_RESET__SHIFT 0x1a +#define GDS_GWS_RESET1__RESOURCE59_RESET_MASK 0x8000000 +#define GDS_GWS_RESET1__RESOURCE59_RESET__SHIFT 0x1b +#define GDS_GWS_RESET1__RESOURCE60_RESET_MASK 0x10000000 +#define GDS_GWS_RESET1__RESOURCE60_RESET__SHIFT 0x1c +#define GDS_GWS_RESET1__RESOURCE61_RESET_MASK 0x20000000 +#define GDS_GWS_RESET1__RESOURCE61_RESET__SHIFT 0x1d +#define GDS_GWS_RESET1__RESOURCE62_RESET_MASK 0x40000000 +#define GDS_GWS_RESET1__RESOURCE62_RESET__SHIFT 0x1e +#define GDS_GWS_RESET1__RESOURCE63_RESET_MASK 0x80000000 +#define GDS_GWS_RESET1__RESOURCE63_RESET__SHIFT 0x1f +#define GDS_GWS_RESOURCE_RESET__RESET_MASK 0x1 +#define GDS_GWS_RESOURCE_RESET__RESET__SHIFT 0x0 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID_MASK 0xff00 +#define GDS_GWS_RESOURCE_RESET__RESOURCE_ID__SHIFT 0x8 +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define GDS_COMPUTE_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET_MASK 0x1 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_PIX_RESET__SHIFT 0x0 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET_MASK 0x2 +#define GDS_OA_RESET_MASK__ME0_GFXHP3D_VTX_RESET__SHIFT 0x1 +#define GDS_OA_RESET_MASK__ME0_CS_RESET_MASK 0x4 +#define GDS_OA_RESET_MASK__ME0_CS_RESET__SHIFT 0x2 +#define GDS_OA_RESET_MASK__UNUSED0_MASK 0x8 +#define GDS_OA_RESET_MASK__UNUSED0__SHIFT 0x3 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET_MASK 0x10 +#define GDS_OA_RESET_MASK__ME1_PIPE0_RESET__SHIFT 0x4 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET_MASK 0x20 +#define GDS_OA_RESET_MASK__ME1_PIPE1_RESET__SHIFT 0x5 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET_MASK 0x40 +#define GDS_OA_RESET_MASK__ME1_PIPE2_RESET__SHIFT 0x6 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET_MASK 0x80 +#define GDS_OA_RESET_MASK__ME1_PIPE3_RESET__SHIFT 0x7 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET_MASK 0x100 +#define GDS_OA_RESET_MASK__ME2_PIPE0_RESET__SHIFT 0x8 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET_MASK 0x200 +#define GDS_OA_RESET_MASK__ME2_PIPE1_RESET__SHIFT 0x9 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET_MASK 0x400 +#define GDS_OA_RESET_MASK__ME2_PIPE2_RESET__SHIFT 0xa +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET_MASK 0x800 +#define GDS_OA_RESET_MASK__ME2_PIPE3_RESET__SHIFT 0xb +#define GDS_OA_RESET_MASK__UNUSED1_MASK 0xfffff000 +#define GDS_OA_RESET_MASK__UNUSED1__SHIFT 0xc +#define GDS_OA_RESET__RESET_MASK 0x1 +#define GDS_OA_RESET__RESET__SHIFT 0x0 +#define GDS_OA_RESET__PIPE_ID_MASK 0xff00 +#define GDS_OA_RESET__PIPE_ID__SHIFT 0x8 +#define GDS_ENHANCE__MISC_MASK 0xffff +#define GDS_ENHANCE__MISC__SHIFT 0x0 +#define GDS_ENHANCE__AUTO_INC_INDEX_MASK 0x10000 +#define GDS_ENHANCE__AUTO_INC_INDEX__SHIFT 0x10 +#define GDS_ENHANCE__CGPG_RESTORE_MASK 0x20000 +#define GDS_ENHANCE__CGPG_RESTORE__SHIFT 0x11 +#define GDS_ENHANCE__UNUSED_MASK 0xfffc0000 +#define GDS_ENHANCE__UNUSED__SHIFT 0x12 +#define GDS_OA_CGPG_RESTORE__VMID_MASK 0xff +#define GDS_OA_CGPG_RESTORE__VMID__SHIFT 0x0 +#define GDS_OA_CGPG_RESTORE__MEID_MASK 0xf00 +#define GDS_OA_CGPG_RESTORE__MEID__SHIFT 0x8 +#define GDS_OA_CGPG_RESTORE__PIPEID_MASK 0xf000 +#define GDS_OA_CGPG_RESTORE__PIPEID__SHIFT 0xc +#define GDS_OA_CGPG_RESTORE__QUEUEID_MASK 0xf0000 +#define GDS_OA_CGPG_RESTORE__QUEUEID__SHIFT 0x10 +#define GDS_OA_CGPG_RESTORE__UNUSED_MASK 0xfff00000 +#define GDS_OA_CGPG_RESTORE__UNUSED__SHIFT 0x14 +#define GDS_CS_CTXSW_STATUS__R_MASK 0x1 +#define GDS_CS_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_CS_CTXSW_STATUS__W_MASK 0x2 +#define GDS_CS_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_CS_CTXSW_STATUS__UNUSED_MASK 0xfffffffc +#define GDS_CS_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_CS_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_CS_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_CS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_CS_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_CS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_GFX_CTXSW_STATUS__R_MASK 0x1 +#define GDS_GFX_CTXSW_STATUS__R__SHIFT 0x0 +#define GDS_GFX_CTXSW_STATUS__W_MASK 0x2 +#define GDS_GFX_CTXSW_STATUS__W__SHIFT 0x1 +#define GDS_GFX_CTXSW_STATUS__UNUSED_MASK 0xfffffffc +#define GDS_GFX_CTXSW_STATUS__UNUSED__SHIFT 0x2 +#define GDS_VS_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_VS_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_VS_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_VS_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_VS_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT0__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT0__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT0__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT0__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT1__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT1__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT1__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT1__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT2__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT2__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT2__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT2__PTR__SHIFT 0x10 +#define GDS_PS0_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS0_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS0_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS0_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS1_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS1_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS1_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS1_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS2_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS2_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS2_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS2_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS3_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS3_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS3_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS3_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS4_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS4_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS4_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS4_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS5_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS5_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS5_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS5_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS6_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS6_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS6_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS6_CTXSW_CNT3__PTR__SHIFT 0x10 +#define GDS_PS7_CTXSW_CNT3__UPDN_MASK 0xffff +#define GDS_PS7_CTXSW_CNT3__UPDN__SHIFT 0x0 +#define GDS_PS7_CTXSW_CNT3__PTR_MASK 0xffff0000 +#define GDS_PS7_CTXSW_CNT3__PTR__SHIFT 0x10 +#define CS_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define CS_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define GFX_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define GFX_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT_MASK 0x3 +#define VGT_DRAW_INITIATOR__SOURCE_SELECT__SHIFT 0x0 +#define VGT_DRAW_INITIATOR__MAJOR_MODE_MASK 0xc +#define VGT_DRAW_INITIATOR__MAJOR_MODE__SHIFT 0x2 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX_MASK 0x10 +#define VGT_DRAW_INITIATOR__SPRITE_EN_R6XX__SHIFT 0x4 +#define VGT_DRAW_INITIATOR__NOT_EOP_MASK 0x20 +#define VGT_DRAW_INITIATOR__NOT_EOP__SHIFT 0x5 +#define VGT_DRAW_INITIATOR__USE_OPAQUE_MASK 0x40 +#define VGT_DRAW_INITIATOR__USE_OPAQUE__SHIFT 0x6 +#define VGT_EVENT_INITIATOR__EVENT_TYPE_MASK 0x3f +#define VGT_EVENT_INITIATOR__EVENT_TYPE__SHIFT 0x0 +#define VGT_EVENT_INITIATOR__ADDRESS_HI_MASK 0x7fc0000 +#define VGT_EVENT_INITIATOR__ADDRESS_HI__SHIFT 0x12 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT_MASK 0x8000000 +#define VGT_EVENT_INITIATOR__EXTENDED_EVENT__SHIFT 0x1b +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW_MASK 0xfffffff +#define VGT_EVENT_ADDRESS_REG__ADDRESS_LOW__SHIFT 0x0 +#define VGT_DMA_BASE_HI__BASE_ADDR_MASK 0xff +#define VGT_DMA_BASE_HI__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_BASE__BASE_ADDR_MASK 0xffffffff +#define VGT_DMA_BASE__BASE_ADDR__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define VGT_DMA_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_DMA_INDEX_TYPE__SWAP_MODE_MASK 0xc +#define VGT_DMA_INDEX_TYPE__SWAP_MODE__SHIFT 0x2 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE_MASK 0x30 +#define VGT_DMA_INDEX_TYPE__BUF_TYPE__SHIFT 0x4 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY_MASK 0x40 +#define VGT_DMA_INDEX_TYPE__RDREQ_POLICY__SHIFT 0x6 +#define VGT_DMA_INDEX_TYPE__NOT_EOP_MASK 0x200 +#define VGT_DMA_INDEX_TYPE__NOT_EOP__SHIFT 0x9 +#define VGT_DMA_INDEX_TYPE__REQ_PATH_MASK 0x400 +#define VGT_DMA_INDEX_TYPE__REQ_PATH__SHIFT 0xa +#define VGT_DMA_INDEX_TYPE__MTYPE_MASK 0x1800 +#define VGT_DMA_INDEX_TYPE__MTYPE__SHIFT 0xb +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff +#define VGT_DMA_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define IA_ENHANCE__MISC_MASK 0xffffffff +#define IA_ENHANCE__MISC__SHIFT 0x0 +#define VGT_DMA_SIZE__NUM_INDICES_MASK 0xffffffff +#define VGT_DMA_SIZE__NUM_INDICES__SHIFT 0x0 +#define VGT_DMA_MAX_SIZE__MAX_SIZE_MASK 0xffffffff +#define VGT_DMA_MAX_SIZE__MAX_SIZE__SHIFT 0x0 +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f +#define VGT_DMA_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE_MASK 0xffff +#define VGT_DMA_CONTROL__PRIMGROUP_SIZE__SHIFT 0x0 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP_MASK 0x20000 +#define VGT_DMA_CONTROL__IA_SWITCH_ON_EOP__SHIFT 0x11 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP_MASK 0x100000 +#define VGT_DMA_CONTROL__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define VGT_IMMED_DATA__DATA_MASK 0xffffffff +#define VGT_IMMED_DATA__DATA__SHIFT 0x0 +#define VGT_INDEX_TYPE__INDEX_TYPE_MASK 0x3 +#define VGT_INDEX_TYPE__INDEX_TYPE__SHIFT 0x0 +#define VGT_NUM_INDICES__NUM_INDICES_MASK 0xffffffff +#define VGT_NUM_INDICES__NUM_INDICES__SHIFT 0x0 +#define VGT_NUM_INSTANCES__NUM_INSTANCES_MASK 0xffffffff +#define VGT_NUM_INSTANCES__NUM_INSTANCES__SHIFT 0x0 +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE_MASK 0x3f +#define VGT_PRIMITIVE_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN_MASK 0x1 +#define VGT_PRIMITIVEID_EN__PRIMITIVEID_EN__SHIFT 0x0 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI_MASK 0x2 +#define VGT_PRIMITIVEID_EN__DISABLE_RESET_ON_EOI__SHIFT 0x1 +#define VGT_PRIMITIVEID_RESET__VALUE_MASK 0xffffffff +#define VGT_PRIMITIVEID_RESET__VALUE__SHIFT 0x0 +#define VGT_VTX_CNT_EN__VTX_CNT_EN_MASK 0x1 +#define VGT_VTX_CNT_EN__VTX_CNT_EN__SHIFT 0x0 +#define VGT_REUSE_OFF__REUSE_OFF_MASK 0x1 +#define VGT_REUSE_OFF__REUSE_OFF__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xffffffff +#define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE_MASK 0xffffffff +#define VGT_INSTANCE_STEP_RATE_1__STEP_RATE__SHIFT 0x0 +#define VGT_MAX_VTX_INDX__MAX_INDX_MASK 0xffffffff +#define VGT_MAX_VTX_INDX__MAX_INDX__SHIFT 0x0 +#define VGT_MIN_VTX_INDX__MIN_INDX_MASK 0xffffffff +#define VGT_MIN_VTX_INDX__MIN_INDX__SHIFT 0x0 +#define VGT_INDX_OFFSET__INDX_OFFSET_MASK 0xffffffff +#define VGT_INDX_OFFSET__INDX_OFFSET__SHIFT 0x0 +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH_MASK 0xff +#define VGT_VERTEX_REUSE_BLOCK_CNTL__VTX_REUSE_DEPTH__SHIFT 0x0 +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST_MASK 0x7f +#define VGT_OUT_DEALLOC_CNTL__DEALLOC_DIST__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xffffffff +#define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN_MASK 0x1 +#define VGT_MULTI_PRIM_IB_RESET_EN__RESET_EN__SHIFT 0x0 +#define VGT_ENHANCE__MISC_MASK 0xffffffff +#define VGT_ENHANCE__MISC__SHIFT 0x0 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT_MASK 0x7 +#define VGT_OUTPUT_PATH_CNTL__PATH_SELECT__SHIFT 0x0 +#define VGT_HOS_CNTL__TESS_MODE_MASK 0x3 +#define VGT_HOS_CNTL__TESS_MODE__SHIFT 0x0 +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS_MASK 0xffffffff +#define VGT_HOS_MAX_TESS_LEVEL__MAX_TESS__SHIFT 0x0 +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS_MASK 0xffffffff +#define VGT_HOS_MIN_TESS_LEVEL__MIN_TESS__SHIFT 0x0 +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH_MASK 0xff +#define VGT_HOS_REUSE_DEPTH__REUSE_DEPTH__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE_MASK 0x1f +#define VGT_GROUP_PRIM_TYPE__PRIM_TYPE__SHIFT 0x0 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER_MASK 0x4000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_ORDER__SHIFT 0xe +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS_MASK 0x8000 +#define VGT_GROUP_PRIM_TYPE__RETAIN_QUADS__SHIFT 0xf +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER_MASK 0x70000 +#define VGT_GROUP_PRIM_TYPE__PRIM_ORDER__SHIFT 0x10 +#define VGT_GROUP_FIRST_DECR__FIRST_DECR_MASK 0xf +#define VGT_GROUP_FIRST_DECR__FIRST_DECR__SHIFT 0x0 +#define VGT_GROUP_DECR__DECR_MASK 0xf +#define VGT_GROUP_DECR__DECR__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN_MASK 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN_MASK 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN_MASK 0x4 +#define VGT_GROUP_VECT_0_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN_MASK 0x8 +#define VGT_GROUP_VECT_0_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_0_CNTL__STRIDE_MASK 0xff00 +#define VGT_GROUP_VECT_0_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_0_CNTL__SHIFT_MASK 0xff0000 +#define VGT_GROUP_VECT_0_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN_MASK 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_X_EN__SHIFT 0x0 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN_MASK 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_Y_EN__SHIFT 0x1 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN_MASK 0x4 +#define VGT_GROUP_VECT_1_CNTL__COMP_Z_EN__SHIFT 0x2 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN_MASK 0x8 +#define VGT_GROUP_VECT_1_CNTL__COMP_W_EN__SHIFT 0x3 +#define VGT_GROUP_VECT_1_CNTL__STRIDE_MASK 0xff00 +#define VGT_GROUP_VECT_1_CNTL__STRIDE__SHIFT 0x8 +#define VGT_GROUP_VECT_1_CNTL__SHIFT_MASK 0xff0000 +#define VGT_GROUP_VECT_1_CNTL__SHIFT__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV_MASK 0xf +#define VGT_GROUP_VECT_0_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET_MASK 0xf0 +#define VGT_GROUP_VECT_0_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV_MASK 0xf00 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET_MASK 0xf000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV_MASK 0xf0000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET_MASK 0xf00000 +#define VGT_GROUP_VECT_0_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV_MASK 0xf000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET_MASK 0xf0000000 +#define VGT_GROUP_VECT_0_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV_MASK 0xf +#define VGT_GROUP_VECT_1_FMT_CNTL__X_CONV__SHIFT 0x0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET_MASK 0xf0 +#define VGT_GROUP_VECT_1_FMT_CNTL__X_OFFSET__SHIFT 0x4 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV_MASK 0xf00 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_CONV__SHIFT 0x8 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET_MASK 0xf000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Y_OFFSET__SHIFT 0xc +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV_MASK 0xf0000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_CONV__SHIFT 0x10 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET_MASK 0xf00000 +#define VGT_GROUP_VECT_1_FMT_CNTL__Z_OFFSET__SHIFT 0x14 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV_MASK 0xf000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_CONV__SHIFT 0x18 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET_MASK 0xf0000000 +#define VGT_GROUP_VECT_1_FMT_CNTL__W_OFFSET__SHIFT 0x1c +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT_MASK 0x3ff +#define VGT_VTX_VECT_EJECT_REG__PRIM_COUNT__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH_MASK 0x1ff +#define VGT_DMA_DATA_FIFO_DEPTH__DMA_DATA_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH_MASK 0x7fe00 +#define VGT_DMA_DATA_FIFO_DEPTH__DMA2DRAW_FIFO_DEPTH__SHIFT 0x9 +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH_MASK 0x3f +#define VGT_DMA_REQ_FIFO_DEPTH__DMA_REQ_FIFO_DEPTH__SHIFT 0x0 +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH_MASK 0x3f +#define VGT_DRAW_INIT_FIFO_DEPTH__DRAW_INIT_FIFO_DEPTH__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID_MASK 0x7 +#define VGT_LAST_COPY_STATE__SRC_STATE_ID__SHIFT 0x0 +#define VGT_LAST_COPY_STATE__DST_STATE_ID_MASK 0x70000 +#define VGT_LAST_COPY_STATE__DST_STATE_ID__SHIFT 0x10 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 +#define CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK 0xffff0000 +#define GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT 0x10 +#define VGT_GS_MODE__MODE_MASK 0x7 +#define VGT_GS_MODE__MODE__SHIFT 0x0 +#define VGT_GS_MODE__RESERVED_0_MASK 0x8 +#define VGT_GS_MODE__RESERVED_0__SHIFT 0x3 +#define VGT_GS_MODE__CUT_MODE_MASK 0x30 +#define VGT_GS_MODE__CUT_MODE__SHIFT 0x4 +#define VGT_GS_MODE__RESERVED_1_MASK 0x7c0 +#define VGT_GS_MODE__RESERVED_1__SHIFT 0x6 +#define VGT_GS_MODE__GS_C_PACK_EN_MASK 0x800 +#define VGT_GS_MODE__GS_C_PACK_EN__SHIFT 0xb +#define VGT_GS_MODE__RESERVED_2_MASK 0x1000 +#define VGT_GS_MODE__RESERVED_2__SHIFT 0xc +#define VGT_GS_MODE__ES_PASSTHRU_MASK 0x2000 +#define VGT_GS_MODE__ES_PASSTHRU__SHIFT 0xd +#define VGT_GS_MODE__RESERVED_3_MASK 0x4000 +#define VGT_GS_MODE__RESERVED_3__SHIFT 0xe +#define VGT_GS_MODE__RESERVED_4_MASK 0x8000 +#define VGT_GS_MODE__RESERVED_4__SHIFT 0xf +#define VGT_GS_MODE__RESERVED_5_MASK 0x10000 +#define VGT_GS_MODE__RESERVED_5__SHIFT 0x10 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI_MASK 0x20000 +#define VGT_GS_MODE__PARTIAL_THD_AT_EOI__SHIFT 0x11 +#define VGT_GS_MODE__SUPPRESS_CUTS_MASK 0x40000 +#define VGT_GS_MODE__SUPPRESS_CUTS__SHIFT 0x12 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE_MASK 0x80000 +#define VGT_GS_MODE__ES_WRITE_OPTIMIZE__SHIFT 0x13 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE_MASK 0x100000 +#define VGT_GS_MODE__GS_WRITE_OPTIMIZE__SHIFT 0x14 +#define VGT_GS_MODE__ONCHIP_MASK 0x600000 +#define VGT_GS_MODE__ONCHIP__SHIFT 0x15 +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP_MASK 0x7ff +#define VGT_GS_ONCHIP_CNTL__ES_VERTS_PER_SUBGRP__SHIFT 0x0 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP_MASK 0x3ff800 +#define VGT_GS_ONCHIP_CNTL__GS_PRIMS_PER_SUBGRP__SHIFT 0xb +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_MASK 0x3f +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE__SHIFT 0x0 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1_MASK 0x3f00 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_1__SHIFT 0x8 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2_MASK 0x3f0000 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_2__SHIFT 0x10 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3_MASK 0xfc00000 +#define VGT_GS_OUT_PRIM_TYPE__OUTPRIM_TYPE_3__SHIFT 0x16 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM_MASK 0x80000000 +#define VGT_GS_OUT_PRIM_TYPE__UNIQUE_TYPE_PER_STREAM__SHIFT 0x1f +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION_MASK 0x3 +#define VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT 0x0 +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT_MASK 0x10 +#define VGT_CACHE_INVALIDATION__DIS_INSTANCING_OPT__SHIFT 0x4 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER_MASK 0x20 +#define VGT_CACHE_INVALIDATION__VS_NO_EXTRA_BUFFER__SHIFT 0x5 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN_MASK 0xc0 +#define VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT 0x6 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE_MASK 0x200 +#define VGT_CACHE_INVALIDATION__USE_GS_DONE__SHIFT 0x9 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD_MASK 0x800 +#define VGT_CACHE_INVALIDATION__DIS_RANGE_FULL_INVLD__SHIFT 0xb +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN_MASK 0x1000 +#define VGT_CACHE_INVALIDATION__GS_LATE_ALLOC_EN__SHIFT 0xc +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH_MASK 0x2000 +#define VGT_CACHE_INVALIDATION__STREAMOUT_FULL_FLUSH__SHIFT 0xd +#define VGT_CACHE_INVALIDATION__ES_LIMIT_MASK 0x1f0000 +#define VGT_CACHE_INVALIDATION__ES_LIMIT__SHIFT 0x10 +#define VGT_RESET_DEBUG__GS_DISABLE_MASK 0x1 +#define VGT_RESET_DEBUG__GS_DISABLE__SHIFT 0x0 +#define VGT_RESET_DEBUG__TESS_DISABLE_MASK 0x2 +#define VGT_RESET_DEBUG__TESS_DISABLE__SHIFT 0x1 +#define VGT_RESET_DEBUG__WD_DISABLE_MASK 0x4 +#define VGT_RESET_DEBUG__WD_DISABLE__SHIFT 0x2 +#define VGT_STRMOUT_DELAY__SKIP_DELAY_MASK 0xff +#define VGT_STRMOUT_DELAY__SKIP_DELAY__SHIFT 0x0 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY_MASK 0x700 +#define VGT_STRMOUT_DELAY__SE0_WD_DELAY__SHIFT 0x8 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY_MASK 0x3800 +#define VGT_STRMOUT_DELAY__SE1_WD_DELAY__SHIFT 0xb +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY_MASK 0x1c000 +#define VGT_STRMOUT_DELAY__SE2_WD_DELAY__SHIFT 0xe +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY_MASK 0xe0000 +#define VGT_STRMOUT_DELAY__SE3_WD_DELAY__SHIFT 0x11 +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH_MASK 0x7f +#define VGT_FIFO_DEPTHS__VS_DEALLOC_TBL_DEPTH__SHIFT 0x0 +#define VGT_FIFO_DEPTHS__RESERVED_0_MASK 0x80 +#define VGT_FIFO_DEPTHS__RESERVED_0__SHIFT 0x7 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH_MASK 0x3fff00 +#define VGT_FIFO_DEPTHS__CLIPP_FIFO_DEPTH__SHIFT 0x8 +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH_MASK 0xfc00000 +#define VGT_FIFO_DEPTHS__HSINPUT_FIFO_DEPTH__SHIFT 0x16 +#define VGT_GS_PER_ES__GS_PER_ES_MASK 0x7ff +#define VGT_GS_PER_ES__GS_PER_ES__SHIFT 0x0 +#define VGT_ES_PER_GS__ES_PER_GS_MASK 0x7ff +#define VGT_ES_PER_GS__ES_PER_GS__SHIFT 0x0 +#define VGT_GS_PER_VS__GS_PER_VS_MASK 0xf +#define VGT_GS_PER_VS__GS_PER_VS__SHIFT 0x0 +#define VGT_GS_VERTEX_REUSE__VERT_REUSE_MASK 0x1f +#define VGT_GS_VERTEX_REUSE__VERT_REUSE__SHIFT 0x0 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES_MASK 0x3 +#define VGT_MC_LAT_CNTL__MC_TIME_STAMP_RES__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_BUSY_MASK 0x1 +#define IA_CNTL_STATUS__IA_BUSY__SHIFT 0x0 +#define IA_CNTL_STATUS__IA_DMA_BUSY_MASK 0x2 +#define IA_CNTL_STATUS__IA_DMA_BUSY__SHIFT 0x1 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY_MASK 0x4 +#define IA_CNTL_STATUS__IA_DMA_REQ_BUSY__SHIFT 0x2 +#define IA_CNTL_STATUS__IA_GRP_BUSY_MASK 0x8 +#define IA_CNTL_STATUS__IA_GRP_BUSY__SHIFT 0x3 +#define IA_CNTL_STATUS__IA_ADC_BUSY_MASK 0x10 +#define IA_CNTL_STATUS__IA_ADC_BUSY__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN_MASK 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_0_EN__SHIFT 0x0 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN_MASK 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_1_EN__SHIFT 0x1 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN_MASK 0x4 +#define VGT_STRMOUT_CONFIG__STREAMOUT_2_EN__SHIFT 0x2 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN_MASK 0x8 +#define VGT_STRMOUT_CONFIG__STREAMOUT_3_EN__SHIFT 0x3 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK 0x70 +#define VGT_STRMOUT_CONFIG__RAST_STREAM__SHIFT 0x4 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK_MASK 0xf00 +#define VGT_STRMOUT_CONFIG__RAST_STREAM_MASK__SHIFT 0x8 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK_MASK 0x80000000 +#define VGT_STRMOUT_CONFIG__USE_RAST_STREAM_MASK__SHIFT 0x1f +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_0__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_0__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_1__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_2__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE_MASK 0x3ff +#define VGT_STRMOUT_VTX_STRIDE_3__STRIDE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN_MASK 0xf +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_0_BUFFER_EN__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN_MASK 0xf0 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_1_BUFFER_EN__SHIFT 0x4 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN_MASK 0xf00 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_2_BUFFER_EN__SHIFT 0x8 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN_MASK 0xf000 +#define VGT_STRMOUT_BUFFER_CONFIG__STREAM_3_BUFFER_EN__SHIFT 0xc +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_0__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_1__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_2__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_BUFFER_FILLED_SIZE_3__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET_MASK 0xffffffff +#define VGT_STRMOUT_DRAW_OPAQUE_OFFSET__OFFSET__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE_MASK 0xffffffff +#define VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE__SIZE__SHIFT 0x0 +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE_MASK 0x1ff +#define VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE__VERTEX_STRIDE__SHIFT 0x0 +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT_MASK 0x7ff +#define VGT_GS_MAX_VERT_OUT__MAX_VERT_OUT__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__LS_EN_MASK 0x3 +#define VGT_SHADER_STAGES_EN__LS_EN__SHIFT 0x0 +#define VGT_SHADER_STAGES_EN__HS_EN_MASK 0x4 +#define VGT_SHADER_STAGES_EN__HS_EN__SHIFT 0x2 +#define VGT_SHADER_STAGES_EN__ES_EN_MASK 0x18 +#define VGT_SHADER_STAGES_EN__ES_EN__SHIFT 0x3 +#define VGT_SHADER_STAGES_EN__GS_EN_MASK 0x20 +#define VGT_SHADER_STAGES_EN__GS_EN__SHIFT 0x5 +#define VGT_SHADER_STAGES_EN__VS_EN_MASK 0xc0 +#define VGT_SHADER_STAGES_EN__VS_EN__SHIFT 0x6 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS_MASK 0x100 +#define VGT_SHADER_STAGES_EN__DYNAMIC_HS__SHIFT 0x8 +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN_MASK 0x200 +#define VGT_SHADER_STAGES_EN__DISPATCH_DRAW_EN__SHIFT 0x9 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0_MASK 0x400 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_0__SHIFT 0xa +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1_MASK 0x800 +#define VGT_SHADER_STAGES_EN__DIS_DEALLOC_ACCUM_1__SHIFT 0xb +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN_MASK 0x1000 +#define VGT_SHADER_STAGES_EN__VS_WAVE_ID_EN__SHIFT 0xc +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX_MASK 0xffffffff +#define VGT_DISPATCH_DRAW_INDEX__MATCH_INDEX__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__NUM_PATCHES_MASK 0xff +#define VGT_LS_HS_CONFIG__NUM_PATCHES__SHIFT 0x0 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 +#define VGT_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP_MASK 0xfc000 +#define VGT_LS_HS_CONFIG__HS_NUM_OUTPUT_CP__SHIFT 0xe +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP_MASK 0x3f00 +#define VGT_DMA_LS_HS_CONFIG__HS_NUM_INPUT_CP__SHIFT 0x8 +#define VGT_TF_PARAM__TYPE_MASK 0x3 +#define VGT_TF_PARAM__TYPE__SHIFT 0x0 +#define VGT_TF_PARAM__PARTITIONING_MASK 0x1c +#define VGT_TF_PARAM__PARTITIONING__SHIFT 0x2 +#define VGT_TF_PARAM__TOPOLOGY_MASK 0xe0 +#define VGT_TF_PARAM__TOPOLOGY__SHIFT 0x5 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS_MASK 0x100 +#define VGT_TF_PARAM__RESERVED_REDUC_AXIS__SHIFT 0x8 +#define VGT_TF_PARAM__DEPRECATED_MASK 0x200 +#define VGT_TF_PARAM__DEPRECATED__SHIFT 0x9 +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD_MASK 0x3c00 +#define VGT_TF_PARAM__NUM_DS_WAVES_PER_SIMD__SHIFT 0xa +#define VGT_TF_PARAM__DISABLE_DONUTS_MASK 0x4000 +#define VGT_TF_PARAM__DISABLE_DONUTS__SHIFT 0xe +#define VGT_TF_PARAM__RDREQ_POLICY_MASK 0x8000 +#define VGT_TF_PARAM__RDREQ_POLICY__SHIFT 0xf +#define VGT_TF_PARAM__DISTRIBUTION_MODE_MASK 0x60000 +#define VGT_TF_PARAM__DISTRIBUTION_MODE__SHIFT 0x11 +#define VGT_TF_PARAM__MTYPE_MASK 0x180000 +#define VGT_TF_PARAM__MTYPE__SHIFT 0x13 +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE_MASK 0xff +#define VGT_TESS_DISTRIBUTION__ACCUM_ISOLINE__SHIFT 0x0 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI_MASK 0xff00 +#define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 +#define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000 +#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 +#define VGT_TF_RING_SIZE__SIZE_MASK 0xffff +#define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 +#define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 +#define VGT_SYS_CONFIG__DUAL_CORE_EN__SHIFT 0x0 +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP_MASK 0x7e +#define VGT_SYS_CONFIG__MAX_LS_HS_THDGRP__SHIFT 0x1 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE_MASK 0x80 +#define VGT_SYS_CONFIG__ADC_EVENT_FILTER_DISABLE__SHIFT 0x7 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING_MASK 0x1ff +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_BUFFERING__SHIFT 0x0 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY_MASK 0x600 +#define VGT_HS_OFFCHIP_PARAM__OFFCHIP_GRANULARITY__SHIFT 0x9 +#define VGT_TF_MEMORY_BASE__BASE_MASK 0xffffffff +#define VGT_TF_MEMORY_BASE__BASE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__ENABLE_MASK 0x1 +#define VGT_GS_INSTANCE_CNT__ENABLE__SHIFT 0x0 +#define VGT_GS_INSTANCE_CNT__CNT_MASK 0x1fc +#define VGT_GS_INSTANCE_CNT__CNT__SHIFT 0x2 +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE_MASK 0xffff +#define IA_MULTI_VGT_PARAM__PRIMGROUP_SIZE__SHIFT 0x0 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON_MASK 0x10000 +#define IA_MULTI_VGT_PARAM__PARTIAL_VS_WAVE_ON__SHIFT 0x10 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP_MASK 0x20000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOP__SHIFT 0x11 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON_MASK 0x40000 +#define IA_MULTI_VGT_PARAM__PARTIAL_ES_WAVE_ON__SHIFT 0x12 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI_MASK 0x80000 +#define IA_MULTI_VGT_PARAM__SWITCH_ON_EOI__SHIFT 0x13 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP_MASK 0x100000 +#define IA_MULTI_VGT_PARAM__WD_SWITCH_ON_EOP__SHIFT 0x14 +#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE_MASK 0xf0000000 +#define IA_MULTI_VGT_PARAM__MAX_PRIMGRP_IN_WAVE__SHIFT 0x1c +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID_MASK 0xfff +#define VGT_VS_MAX_WAVE_ID__MAX_WAVE_ID__SHIFT 0x0 +#define VGT_ESGS_RING_SIZE__MEM_SIZE_MASK 0xffffffff +#define VGT_ESGS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_SIZE__MEM_SIZE_MASK 0xffffffff +#define VGT_GSVS_RING_SIZE__MEM_SIZE__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_1__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_1__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_2__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_2__OFFSET__SHIFT 0x0 +#define VGT_GSVS_RING_OFFSET_3__OFFSET_MASK 0x7fff +#define VGT_GSVS_RING_OFFSET_3__OFFSET__SHIFT 0x0 +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_ESGS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_GSVS_RING_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_1__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_2__ITEMSIZE__SHIFT 0x0 +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE_MASK 0x7fff +#define VGT_GS_VERT_ITEMSIZE_3__ITEMSIZE__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_BUSY_MASK 0x1 +#define WD_CNTL_STATUS__WD_BUSY__SHIFT 0x0 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY_MASK 0x2 +#define WD_CNTL_STATUS__WD_SPL_DMA_BUSY__SHIFT 0x1 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY_MASK 0x4 +#define WD_CNTL_STATUS__WD_SPL_DI_BUSY__SHIFT 0x2 +#define WD_CNTL_STATUS__WD_ADC_BUSY_MASK 0x8 +#define WD_CNTL_STATUS__WD_ADC_BUSY__SHIFT 0x3 +#define WD_ENHANCE__MISC_MASK 0xffffffff +#define WD_ENHANCE__MISC__SHIFT 0x0 +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT_MASK 0x1fff +#define GFX_PIPE_CONTROL__HYSTERESIS_CNT__SHIFT 0x0 +#define GFX_PIPE_CONTROL__RESERVED_MASK 0xe000 +#define GFX_PIPE_CONTROL__RESERVED__SHIFT 0xd +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN_MASK 0x10000 +#define GFX_PIPE_CONTROL__CONTEXT_SUSPEND_EN__SHIFT 0x10 +#define CGTT_VGT_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_VGT_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_VGT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_VGT_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_VGT_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_VGT_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000 +#define CGTT_VGT_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE_MASK 0x20000000 +#define CGTT_VGT_CLK_CTRL__GS_OVERRIDE__SHIFT 0x1d +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_VGT_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_VGT_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_IA_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_IA_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_IA_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_IA_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_IA_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_IA_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3_MASK 0x10000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE3__SHIFT 0x1c +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2_MASK 0x20000000 +#define CGTT_IA_CLK_CTRL__SOFT_OVERRIDE2__SHIFT 0x1d +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE_MASK 0x40000000 +#define CGTT_IA_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1e +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_IA_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define CGTT_WD_CLK_CTRL__ON_DELAY_MASK 0xf +#define CGTT_WD_CLK_CTRL__ON_DELAY__SHIFT 0x0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS_MASK 0xff0 +#define CGTT_WD_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7_MASK 0x1000000 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE7__SHIFT 0x18 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE_MASK 0x2000000 +#define CGTT_WD_CLK_CTRL__PERF_ENABLE__SHIFT 0x19 +#define CGTT_WD_CLK_CTRL__DBG_ENABLE_MASK 0x4000000 +#define CGTT_WD_CLK_CTRL__DBG_ENABLE__SHIFT 0x1a +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4_MASK 0x8000000 +#define CGTT_WD_CLK_CTRL__SOFT_OVERRIDE4__SHIFT 0x1b +#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE_MASK 0x10000000 +#define CGTT_WD_CLK_CTRL__TESS_OVERRIDE__SHIFT 0x1c +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE_MASK 0x20000000 +#define CGTT_WD_CLK_CTRL__CORE_OVERRIDE__SHIFT 0x1d +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE_MASK 0x40000000 +#define CGTT_WD_CLK_CTRL__RBIU_INPUT_OVERRIDE__SHIFT 0x1e +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE_MASK 0x80000000 +#define CGTT_WD_CLK_CTRL__REG_OVERRIDE__SHIFT 0x1f +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX_MASK 0x3f +#define VGT_DEBUG_CNTL__VGT_DEBUG_INDX__SHIFT 0x0 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B_MASK 0x40 +#define VGT_DEBUG_CNTL__VGT_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define VGT_DEBUG_DATA__DATA_MASK 0xffffffff +#define VGT_DEBUG_DATA__DATA__SHIFT 0x0 +#define IA_DEBUG_CNTL__IA_DEBUG_INDX_MASK 0x3f +#define IA_DEBUG_CNTL__IA_DEBUG_INDX__SHIFT 0x0 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B_MASK 0x40 +#define IA_DEBUG_CNTL__IA_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define IA_DEBUG_DATA__DATA_MASK 0xffffffff +#define IA_DEBUG_DATA__DATA__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_BUSY_MASK 0x1 +#define VGT_CNTL_STATUS__VGT_BUSY__SHIFT 0x0 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY_MASK 0x2 +#define VGT_CNTL_STATUS__VGT_OUT_INDX_BUSY__SHIFT 0x1 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY_MASK 0x4 +#define VGT_CNTL_STATUS__VGT_OUT_BUSY__SHIFT 0x2 +#define VGT_CNTL_STATUS__VGT_PT_BUSY_MASK 0x8 +#define VGT_CNTL_STATUS__VGT_PT_BUSY__SHIFT 0x3 +#define VGT_CNTL_STATUS__VGT_TE_BUSY_MASK 0x10 +#define VGT_CNTL_STATUS__VGT_TE_BUSY__SHIFT 0x4 +#define VGT_CNTL_STATUS__VGT_VR_BUSY_MASK 0x20 +#define VGT_CNTL_STATUS__VGT_VR_BUSY__SHIFT 0x5 +#define VGT_CNTL_STATUS__VGT_PI_BUSY_MASK 0x40 +#define VGT_CNTL_STATUS__VGT_PI_BUSY__SHIFT 0x6 +#define VGT_CNTL_STATUS__VGT_GS_BUSY_MASK 0x80 +#define VGT_CNTL_STATUS__VGT_GS_BUSY__SHIFT 0x7 +#define VGT_CNTL_STATUS__VGT_HS_BUSY_MASK 0x100 +#define VGT_CNTL_STATUS__VGT_HS_BUSY__SHIFT 0x8 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY_MASK 0x200 +#define VGT_CNTL_STATUS__VGT_TE11_BUSY__SHIFT 0x9 +#define WD_DEBUG_CNTL__WD_DEBUG_INDX_MASK 0x3f +#define WD_DEBUG_CNTL__WD_DEBUG_INDX__SHIFT 0x0 +#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B_MASK 0x40 +#define WD_DEBUG_CNTL__WD_DEBUG_SEL_BUS_B__SHIFT 0x6 +#define WD_DEBUG_DATA__DATA_MASK 0xffffffff +#define WD_DEBUG_DATA__DATA__SHIFT 0x0 +#define WD_QOS__DRAW_STALL_MASK 0x1 +#define WD_QOS__DRAW_STALL__SHIFT 0x0 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 +#define CC_GC_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 +#define CC_GC_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA_MASK 0x30000 +#define GC_USER_PRIM_CONFIG__INACTIVE_IA__SHIFT 0x10 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA_MASK 0xf000000 +#define GC_USER_PRIM_CONFIG__INACTIVE_VGT_PA__SHIFT 0x18 +#define WD_DEBUG_REG0__wd_busy_extended_MASK 0x1 +#define WD_DEBUG_REG0__wd_busy_extended__SHIFT 0x0 +#define WD_DEBUG_REG0__wd_nodma_busy_extended_MASK 0x2 +#define WD_DEBUG_REG0__wd_nodma_busy_extended__SHIFT 0x1 +#define WD_DEBUG_REG0__wd_busy_MASK 0x4 +#define WD_DEBUG_REG0__wd_busy__SHIFT 0x2 +#define WD_DEBUG_REG0__wd_nodma_busy_MASK 0x8 +#define WD_DEBUG_REG0__wd_nodma_busy__SHIFT 0x3 +#define WD_DEBUG_REG0__rbiu_busy_MASK 0x10 +#define WD_DEBUG_REG0__rbiu_busy__SHIFT 0x4 +#define WD_DEBUG_REG0__spl_dma_busy_MASK 0x20 +#define WD_DEBUG_REG0__spl_dma_busy__SHIFT 0x5 +#define WD_DEBUG_REG0__spl_di_busy_MASK 0x40 +#define WD_DEBUG_REG0__spl_di_busy__SHIFT 0x6 +#define WD_DEBUG_REG0__vgt0_active_q_MASK 0x80 +#define WD_DEBUG_REG0__vgt0_active_q__SHIFT 0x7 +#define WD_DEBUG_REG0__vgt1_active_q_MASK 0x100 +#define WD_DEBUG_REG0__vgt1_active_q__SHIFT 0x8 +#define WD_DEBUG_REG0__spl_dma_p1_busy_MASK 0x200 +#define WD_DEBUG_REG0__spl_dma_p1_busy__SHIFT 0x9 +#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy_MASK 0x400 +#define WD_DEBUG_REG0__rbiu_dr_p1_fifo_busy__SHIFT 0xa +#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy_MASK 0x800 +#define WD_DEBUG_REG0__rbiu_di_p1_fifo_busy__SHIFT 0xb +#define WD_DEBUG_REG0__SPARE2_MASK 0x1000 +#define WD_DEBUG_REG0__SPARE2__SHIFT 0xc +#define WD_DEBUG_REG0__rbiu_dr_fifo_busy_MASK 0x2000 +#define WD_DEBUG_REG0__rbiu_dr_fifo_busy__SHIFT 0xd +#define WD_DEBUG_REG0__rbiu_spl_dr_valid_MASK 0x4000 +#define WD_DEBUG_REG0__rbiu_spl_dr_valid__SHIFT 0xe +#define WD_DEBUG_REG0__spl_rbiu_dr_read_MASK 0x8000 +#define WD_DEBUG_REG0__spl_rbiu_dr_read__SHIFT 0xf +#define WD_DEBUG_REG0__SPARE3_MASK 0x10000 +#define WD_DEBUG_REG0__SPARE3__SHIFT 0x10 +#define WD_DEBUG_REG0__rbiu_di_fifo_busy_MASK 0x20000 +#define WD_DEBUG_REG0__rbiu_di_fifo_busy__SHIFT 0x11 +#define WD_DEBUG_REG0__rbiu_spl_di_valid_MASK 0x40000 +#define WD_DEBUG_REG0__rbiu_spl_di_valid__SHIFT 0x12 +#define WD_DEBUG_REG0__spl_rbiu_di_read_MASK 0x80000 +#define WD_DEBUG_REG0__spl_rbiu_di_read__SHIFT 0x13 +#define WD_DEBUG_REG0__se0_synced_q_MASK 0x100000 +#define WD_DEBUG_REG0__se0_synced_q__SHIFT 0x14 +#define WD_DEBUG_REG0__se1_synced_q_MASK 0x200000 +#define WD_DEBUG_REG0__se1_synced_q__SHIFT 0x15 +#define WD_DEBUG_REG0__se2_synced_q_MASK 0x400000 +#define WD_DEBUG_REG0__se2_synced_q__SHIFT 0x16 +#define WD_DEBUG_REG0__se3_synced_q_MASK 0x800000 +#define WD_DEBUG_REG0__se3_synced_q__SHIFT 0x17 +#define WD_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define WD_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define WD_DEBUG_REG0__input_clk_busy_MASK 0x2000000 +#define WD_DEBUG_REG0__input_clk_busy__SHIFT 0x19 +#define WD_DEBUG_REG0__core_clk_busy_MASK 0x4000000 +#define WD_DEBUG_REG0__core_clk_busy__SHIFT 0x1a +#define WD_DEBUG_REG0__vgt2_active_q_MASK 0x8000000 +#define WD_DEBUG_REG0__vgt2_active_q__SHIFT 0x1b +#define WD_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 +#define WD_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c +#define WD_DEBUG_REG0__sclk_input_vld_MASK 0x20000000 +#define WD_DEBUG_REG0__sclk_input_vld__SHIFT 0x1d +#define WD_DEBUG_REG0__sclk_core_vld_MASK 0x40000000 +#define WD_DEBUG_REG0__sclk_core_vld__SHIFT 0x1e +#define WD_DEBUG_REG0__vgt3_active_q_MASK 0x80000000 +#define WD_DEBUG_REG0__vgt3_active_q__SHIFT 0x1f +#define WD_DEBUG_REG1__grbm_fifo_empty_MASK 0x1 +#define WD_DEBUG_REG1__grbm_fifo_empty__SHIFT 0x0 +#define WD_DEBUG_REG1__grbm_fifo_full_MASK 0x2 +#define WD_DEBUG_REG1__grbm_fifo_full__SHIFT 0x1 +#define WD_DEBUG_REG1__grbm_fifo_we_MASK 0x4 +#define WD_DEBUG_REG1__grbm_fifo_we__SHIFT 0x2 +#define WD_DEBUG_REG1__grbm_fifo_re_MASK 0x8 +#define WD_DEBUG_REG1__grbm_fifo_re__SHIFT 0x3 +#define WD_DEBUG_REG1__draw_initiator_valid_q_MASK 0x10 +#define WD_DEBUG_REG1__draw_initiator_valid_q__SHIFT 0x4 +#define WD_DEBUG_REG1__event_initiator_valid_q_MASK 0x20 +#define WD_DEBUG_REG1__event_initiator_valid_q__SHIFT 0x5 +#define WD_DEBUG_REG1__event_addr_valid_q_MASK 0x40 +#define WD_DEBUG_REG1__event_addr_valid_q__SHIFT 0x6 +#define WD_DEBUG_REG1__dma_request_valid_q_MASK 0x80 +#define WD_DEBUG_REG1__dma_request_valid_q__SHIFT 0x7 +#define WD_DEBUG_REG1__SPARE0_MASK 0x100 +#define WD_DEBUG_REG1__SPARE0__SHIFT 0x8 +#define WD_DEBUG_REG1__min_indx_valid_q_MASK 0x200 +#define WD_DEBUG_REG1__min_indx_valid_q__SHIFT 0x9 +#define WD_DEBUG_REG1__max_indx_valid_q_MASK 0x400 +#define WD_DEBUG_REG1__max_indx_valid_q__SHIFT 0xa +#define WD_DEBUG_REG1__indx_offset_valid_q_MASK 0x800 +#define WD_DEBUG_REG1__indx_offset_valid_q__SHIFT 0xb +#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id_MASK 0x1f000 +#define WD_DEBUG_REG1__grbm_fifo_rdata_reg_id__SHIFT 0xc +#define WD_DEBUG_REG1__grbm_fifo_rdata_state_MASK 0xe0000 +#define WD_DEBUG_REG1__grbm_fifo_rdata_state__SHIFT 0x11 +#define WD_DEBUG_REG1__free_cnt_q_MASK 0x3f00000 +#define WD_DEBUG_REG1__free_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG1__rbiu_di_fifo_we_MASK 0x4000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_we__SHIFT 0x1a +#define WD_DEBUG_REG1__rbiu_dr_fifo_we_MASK 0x8000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_we__SHIFT 0x1b +#define WD_DEBUG_REG1__rbiu_di_fifo_empty_MASK 0x10000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_empty__SHIFT 0x1c +#define WD_DEBUG_REG1__rbiu_di_fifo_full_MASK 0x20000000 +#define WD_DEBUG_REG1__rbiu_di_fifo_full__SHIFT 0x1d +#define WD_DEBUG_REG1__rbiu_dr_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG1__rbiu_dr_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG1__rbiu_dr_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG2__p1_grbm_fifo_empty_MASK 0x1 +#define WD_DEBUG_REG2__p1_grbm_fifo_empty__SHIFT 0x0 +#define WD_DEBUG_REG2__p1_grbm_fifo_full_MASK 0x2 +#define WD_DEBUG_REG2__p1_grbm_fifo_full__SHIFT 0x1 +#define WD_DEBUG_REG2__p1_grbm_fifo_we_MASK 0x4 +#define WD_DEBUG_REG2__p1_grbm_fifo_we__SHIFT 0x2 +#define WD_DEBUG_REG2__p1_grbm_fifo_re_MASK 0x8 +#define WD_DEBUG_REG2__p1_grbm_fifo_re__SHIFT 0x3 +#define WD_DEBUG_REG2__p1_draw_initiator_valid_q_MASK 0x10 +#define WD_DEBUG_REG2__p1_draw_initiator_valid_q__SHIFT 0x4 +#define WD_DEBUG_REG2__p1_event_initiator_valid_q_MASK 0x20 +#define WD_DEBUG_REG2__p1_event_initiator_valid_q__SHIFT 0x5 +#define WD_DEBUG_REG2__p1_event_addr_valid_q_MASK 0x40 +#define WD_DEBUG_REG2__p1_event_addr_valid_q__SHIFT 0x6 +#define WD_DEBUG_REG2__p1_dma_request_valid_q_MASK 0x80 +#define WD_DEBUG_REG2__p1_dma_request_valid_q__SHIFT 0x7 +#define WD_DEBUG_REG2__SPARE0_MASK 0x100 +#define WD_DEBUG_REG2__SPARE0__SHIFT 0x8 +#define WD_DEBUG_REG2__p1_min_indx_valid_q_MASK 0x200 +#define WD_DEBUG_REG2__p1_min_indx_valid_q__SHIFT 0x9 +#define WD_DEBUG_REG2__p1_max_indx_valid_q_MASK 0x400 +#define WD_DEBUG_REG2__p1_max_indx_valid_q__SHIFT 0xa +#define WD_DEBUG_REG2__p1_indx_offset_valid_q_MASK 0x800 +#define WD_DEBUG_REG2__p1_indx_offset_valid_q__SHIFT 0xb +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id_MASK 0x1f000 +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_reg_id__SHIFT 0xc +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state_MASK 0xe0000 +#define WD_DEBUG_REG2__p1_grbm_fifo_rdata_state__SHIFT 0x11 +#define WD_DEBUG_REG2__p1_free_cnt_q_MASK 0x3f00000 +#define WD_DEBUG_REG2__p1_free_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we_MASK 0x4000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_we__SHIFT 0x1a +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we_MASK 0x8000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_we__SHIFT 0x1b +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty_MASK 0x10000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_empty__SHIFT 0x1c +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full_MASK 0x20000000 +#define WD_DEBUG_REG2__p1_rbiu_di_fifo_full__SHIFT 0x1d +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG2__p1_rbiu_dr_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG3__rbiu_spl_dr_valid_MASK 0x1 +#define WD_DEBUG_REG3__rbiu_spl_dr_valid__SHIFT 0x0 +#define WD_DEBUG_REG3__SPARE0_MASK 0x2 +#define WD_DEBUG_REG3__SPARE0__SHIFT 0x1 +#define WD_DEBUG_REG3__pipe0_dr_MASK 0x4 +#define WD_DEBUG_REG3__pipe0_dr__SHIFT 0x2 +#define WD_DEBUG_REG3__pipe0_rtr_MASK 0x8 +#define WD_DEBUG_REG3__pipe0_rtr__SHIFT 0x3 +#define WD_DEBUG_REG3__pipe1_dr_MASK 0x10 +#define WD_DEBUG_REG3__pipe1_dr__SHIFT 0x4 +#define WD_DEBUG_REG3__pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG3__pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG3__wd_subdma_fifo_empty_MASK 0x40 +#define WD_DEBUG_REG3__wd_subdma_fifo_empty__SHIFT 0x6 +#define WD_DEBUG_REG3__wd_subdma_fifo_full_MASK 0x80 +#define WD_DEBUG_REG3__wd_subdma_fifo_full__SHIFT 0x7 +#define WD_DEBUG_REG3__dma_buf_type_p0_q_MASK 0x300 +#define WD_DEBUG_REG3__dma_buf_type_p0_q__SHIFT 0x8 +#define WD_DEBUG_REG3__dma_zero_indices_p0_q_MASK 0x400 +#define WD_DEBUG_REG3__dma_zero_indices_p0_q__SHIFT 0xa +#define WD_DEBUG_REG3__dma_req_path_p3_q_MASK 0x800 +#define WD_DEBUG_REG3__dma_req_path_p3_q__SHIFT 0xb +#define WD_DEBUG_REG3__dma_not_eop_p1_q_MASK 0x1000 +#define WD_DEBUG_REG3__dma_not_eop_p1_q__SHIFT 0xc +#define WD_DEBUG_REG3__out_of_range_p4_MASK 0x2000 +#define WD_DEBUG_REG3__out_of_range_p4__SHIFT 0xd +#define WD_DEBUG_REG3__last_sub_dma_p3_q_MASK 0x4000 +#define WD_DEBUG_REG3__last_sub_dma_p3_q__SHIFT 0xe +#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4_MASK 0x8000 +#define WD_DEBUG_REG3__last_rdreq_of_sub_dma_p4__SHIFT 0xf +#define WD_DEBUG_REG3__WD_IA_dma_send_d_MASK 0x10000 +#define WD_DEBUG_REG3__WD_IA_dma_send_d__SHIFT 0x10 +#define WD_DEBUG_REG3__WD_IA_dma_rtr_MASK 0x20000 +#define WD_DEBUG_REG3__WD_IA_dma_rtr__SHIFT 0x11 +#define WD_DEBUG_REG3__WD_IA1_dma_send_d_MASK 0x40000 +#define WD_DEBUG_REG3__WD_IA1_dma_send_d__SHIFT 0x12 +#define WD_DEBUG_REG3__WD_IA1_dma_rtr_MASK 0x80000 +#define WD_DEBUG_REG3__WD_IA1_dma_rtr__SHIFT 0x13 +#define WD_DEBUG_REG3__last_inst_of_dma_p2_MASK 0x100000 +#define WD_DEBUG_REG3__last_inst_of_dma_p2__SHIFT 0x14 +#define WD_DEBUG_REG3__last_sd_of_inst_p2_MASK 0x200000 +#define WD_DEBUG_REG3__last_sd_of_inst_p2__SHIFT 0x15 +#define WD_DEBUG_REG3__last_sd_of_dma_p2_MASK 0x400000 +#define WD_DEBUG_REG3__last_sd_of_dma_p2__SHIFT 0x16 +#define WD_DEBUG_REG3__SPARE1_MASK 0x800000 +#define WD_DEBUG_REG3__SPARE1__SHIFT 0x17 +#define WD_DEBUG_REG3__WD_IA_dma_busy_MASK 0x1000000 +#define WD_DEBUG_REG3__WD_IA_dma_busy__SHIFT 0x18 +#define WD_DEBUG_REG3__WD_IA1_dma_busy_MASK 0x2000000 +#define WD_DEBUG_REG3__WD_IA1_dma_busy__SHIFT 0x19 +#define WD_DEBUG_REG3__send_to_ia1_p3_q_MASK 0x4000000 +#define WD_DEBUG_REG3__send_to_ia1_p3_q__SHIFT 0x1a +#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q_MASK 0x8000000 +#define WD_DEBUG_REG3__dma_wd_switch_on_eop_p3_q__SHIFT 0x1b +#define WD_DEBUG_REG3__pipe3_dr_MASK 0x10000000 +#define WD_DEBUG_REG3__pipe3_dr__SHIFT 0x1c +#define WD_DEBUG_REG3__pipe3_rtr_MASK 0x20000000 +#define WD_DEBUG_REG3__pipe3_rtr__SHIFT 0x1d +#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG3__wd_dma2draw_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG3__wd_dma2draw_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG3__wd_dma2draw_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG4__rbiu_spl_di_valid_MASK 0x1 +#define WD_DEBUG_REG4__rbiu_spl_di_valid__SHIFT 0x0 +#define WD_DEBUG_REG4__spl_rbiu_di_read_MASK 0x2 +#define WD_DEBUG_REG4__spl_rbiu_di_read__SHIFT 0x1 +#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid_MASK 0x4 +#define WD_DEBUG_REG4__rbiu_spl_p1_di_valid__SHIFT 0x2 +#define WD_DEBUG_REG4__spl_rbiu_p1_di_read_MASK 0x8 +#define WD_DEBUG_REG4__spl_rbiu_p1_di_read__SHIFT 0x3 +#define WD_DEBUG_REG4__pipe0_dr_MASK 0x10 +#define WD_DEBUG_REG4__pipe0_dr__SHIFT 0x4 +#define WD_DEBUG_REG4__pipe0_rtr_MASK 0x20 +#define WD_DEBUG_REG4__pipe0_rtr__SHIFT 0x5 +#define WD_DEBUG_REG4__pipe1_dr_MASK 0x40 +#define WD_DEBUG_REG4__pipe1_dr__SHIFT 0x6 +#define WD_DEBUG_REG4__pipe1_rtr_MASK 0x80 +#define WD_DEBUG_REG4__pipe1_rtr__SHIFT 0x7 +#define WD_DEBUG_REG4__pipe2_dr_MASK 0x100 +#define WD_DEBUG_REG4__pipe2_dr__SHIFT 0x8 +#define WD_DEBUG_REG4__pipe2_rtr_MASK 0x200 +#define WD_DEBUG_REG4__pipe2_rtr__SHIFT 0x9 +#define WD_DEBUG_REG4__pipe3_ld_MASK 0x400 +#define WD_DEBUG_REG4__pipe3_ld__SHIFT 0xa +#define WD_DEBUG_REG4__pipe3_rtr_MASK 0x800 +#define WD_DEBUG_REG4__pipe3_rtr__SHIFT 0xb +#define WD_DEBUG_REG4__WD_IA_draw_send_d_MASK 0x1000 +#define WD_DEBUG_REG4__WD_IA_draw_send_d__SHIFT 0xc +#define WD_DEBUG_REG4__WD_IA_draw_rtr_MASK 0x2000 +#define WD_DEBUG_REG4__WD_IA_draw_rtr__SHIFT 0xd +#define WD_DEBUG_REG4__di_type_p0_MASK 0xc000 +#define WD_DEBUG_REG4__di_type_p0__SHIFT 0xe +#define WD_DEBUG_REG4__di_state_sel_p1_q_MASK 0x70000 +#define WD_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x10 +#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q_MASK 0x80000 +#define WD_DEBUG_REG4__di_wd_switch_on_eop_p1_q__SHIFT 0x13 +#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout_MASK 0x100000 +#define WD_DEBUG_REG4__rbiu_spl_pipe0_lockout__SHIFT 0x14 +#define WD_DEBUG_REG4__last_inst_of_di_p2_MASK 0x200000 +#define WD_DEBUG_REG4__last_inst_of_di_p2__SHIFT 0x15 +#define WD_DEBUG_REG4__last_sd_of_inst_p2_MASK 0x400000 +#define WD_DEBUG_REG4__last_sd_of_inst_p2__SHIFT 0x16 +#define WD_DEBUG_REG4__last_sd_of_di_p2_MASK 0x800000 +#define WD_DEBUG_REG4__last_sd_of_di_p2__SHIFT 0x17 +#define WD_DEBUG_REG4__not_eop_wait_p1_q_MASK 0x1000000 +#define WD_DEBUG_REG4__not_eop_wait_p1_q__SHIFT 0x18 +#define WD_DEBUG_REG4__not_eop_wait_q_MASK 0x2000000 +#define WD_DEBUG_REG4__not_eop_wait_q__SHIFT 0x19 +#define WD_DEBUG_REG4__ext_event_wait_p1_q_MASK 0x4000000 +#define WD_DEBUG_REG4__ext_event_wait_p1_q__SHIFT 0x1a +#define WD_DEBUG_REG4__ext_event_wait_q_MASK 0x8000000 +#define WD_DEBUG_REG4__ext_event_wait_q__SHIFT 0x1b +#define WD_DEBUG_REG4__WD_IA1_draw_send_d_MASK 0x10000000 +#define WD_DEBUG_REG4__WD_IA1_draw_send_d__SHIFT 0x1c +#define WD_DEBUG_REG4__WD_IA1_draw_rtr_MASK 0x20000000 +#define WD_DEBUG_REG4__WD_IA1_draw_rtr__SHIFT 0x1d +#define WD_DEBUG_REG4__send_to_ia1_q_MASK 0x40000000 +#define WD_DEBUG_REG4__send_to_ia1_q__SHIFT 0x1e +#define WD_DEBUG_REG4__dual_ia_mode_MASK 0x80000000 +#define WD_DEBUG_REG4__dual_ia_mode__SHIFT 0x1f +#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid_MASK 0x1 +#define WD_DEBUG_REG5__p1_rbiu_spl_dr_valid__SHIFT 0x0 +#define WD_DEBUG_REG5__SPARE0_MASK 0x2 +#define WD_DEBUG_REG5__SPARE0__SHIFT 0x1 +#define WD_DEBUG_REG5__p1_pipe0_dr_MASK 0x4 +#define WD_DEBUG_REG5__p1_pipe0_dr__SHIFT 0x2 +#define WD_DEBUG_REG5__p1_pipe0_rtr_MASK 0x8 +#define WD_DEBUG_REG5__p1_pipe0_rtr__SHIFT 0x3 +#define WD_DEBUG_REG5__p1_pipe1_dr_MASK 0x10 +#define WD_DEBUG_REG5__p1_pipe1_dr__SHIFT 0x4 +#define WD_DEBUG_REG5__p1_pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG5__p1_pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty_MASK 0x40 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_empty__SHIFT 0x6 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full_MASK 0x80 +#define WD_DEBUG_REG5__p1_wd_subdma_fifo_full__SHIFT 0x7 +#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q_MASK 0x300 +#define WD_DEBUG_REG5__p1_dma_buf_type_p0_q__SHIFT 0x8 +#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q_MASK 0x400 +#define WD_DEBUG_REG5__p1_dma_zero_indices_p0_q__SHIFT 0xa +#define WD_DEBUG_REG5__p1_dma_req_path_p3_q_MASK 0x800 +#define WD_DEBUG_REG5__p1_dma_req_path_p3_q__SHIFT 0xb +#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q_MASK 0x1000 +#define WD_DEBUG_REG5__p1_dma_not_eop_p1_q__SHIFT 0xc +#define WD_DEBUG_REG5__p1_out_of_range_p4_MASK 0x2000 +#define WD_DEBUG_REG5__p1_out_of_range_p4__SHIFT 0xd +#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q_MASK 0x4000 +#define WD_DEBUG_REG5__p1_last_sub_dma_p3_q__SHIFT 0xe +#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4_MASK 0x8000 +#define WD_DEBUG_REG5__p1_last_rdreq_of_sub_dma_p4__SHIFT 0xf +#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d_MASK 0x10000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_send_d__SHIFT 0x10 +#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr_MASK 0x20000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_rtr__SHIFT 0x11 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d_MASK 0x40000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_send_d__SHIFT 0x12 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr_MASK 0x80000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_rtr__SHIFT 0x13 +#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2_MASK 0x100000 +#define WD_DEBUG_REG5__p1_last_inst_of_dma_p2__SHIFT 0x14 +#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2_MASK 0x200000 +#define WD_DEBUG_REG5__p1_last_sd_of_inst_p2__SHIFT 0x15 +#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2_MASK 0x400000 +#define WD_DEBUG_REG5__p1_last_sd_of_dma_p2__SHIFT 0x16 +#define WD_DEBUG_REG5__SPARE1_MASK 0x800000 +#define WD_DEBUG_REG5__SPARE1__SHIFT 0x17 +#define WD_DEBUG_REG5__p1_WD_IA_dma_busy_MASK 0x1000000 +#define WD_DEBUG_REG5__p1_WD_IA_dma_busy__SHIFT 0x18 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy_MASK 0x2000000 +#define WD_DEBUG_REG5__p1_WD_IA1_dma_busy__SHIFT 0x19 +#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q_MASK 0x4000000 +#define WD_DEBUG_REG5__p1_send_to_ia1_p3_q__SHIFT 0x1a +#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q_MASK 0x8000000 +#define WD_DEBUG_REG5__p1_dma_wd_switch_on_eop_p3_q__SHIFT 0x1b +#define WD_DEBUG_REG5__p1_pipe3_dr_MASK 0x10000000 +#define WD_DEBUG_REG5__p1_pipe3_dr__SHIFT 0x1c +#define WD_DEBUG_REG5__p1_pipe3_rtr_MASK 0x20000000 +#define WD_DEBUG_REG5__p1_pipe3_rtr__SHIFT 0x1d +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty_MASK 0x40000000 +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_empty__SHIFT 0x1e +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full_MASK 0x80000000 +#define WD_DEBUG_REG5__p1_wd_dma2draw_fifo_full__SHIFT 0x1f +#define WD_DEBUG_REG6__WD_IA_draw_eop_MASK 0xffffffff +#define WD_DEBUG_REG6__WD_IA_draw_eop__SHIFT 0x0 +#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in_MASK 0x1 +#define WD_DEBUG_REG7__SE0VGT_WD_thdgrp_send_in__SHIFT 0x0 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re_MASK 0x2 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_re__SHIFT 0x1 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty_MASK 0x4 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_empty__SHIFT 0x2 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full_MASK 0x8 +#define WD_DEBUG_REG7__wd_arb_se0_input_fifo_full__SHIFT 0x3 +#define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in_MASK 0x10 +#define WD_DEBUG_REG7__SE1VGT_WD_thdgrp_send_in__SHIFT 0x4 +#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re_MASK 0x20 +#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_re__SHIFT 0x5 +#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty_MASK 0x40 +#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_empty__SHIFT 0x6 +#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full_MASK 0x80 +#define WD_DEBUG_REG7__wd_arb_se1_input_fifo_full__SHIFT 0x7 +#define WD_DEBUG_REG7__SPARE1_MASK 0xf00 +#define WD_DEBUG_REG7__SPARE1__SHIFT 0x8 +#define WD_DEBUG_REG7__SPARE2_MASK 0xf000 +#define WD_DEBUG_REG7__SPARE2__SHIFT 0xc +#define WD_DEBUG_REG7__te11_arb_state_q_MASK 0x70000 +#define WD_DEBUG_REG7__te11_arb_state_q__SHIFT 0x10 +#define WD_DEBUG_REG7__SPARE5_MASK 0x80000 +#define WD_DEBUG_REG7__SPARE5__SHIFT 0x13 +#define WD_DEBUG_REG7__se0_thdgrp_is_event_MASK 0x100000 +#define WD_DEBUG_REG7__se0_thdgrp_is_event__SHIFT 0x14 +#define WD_DEBUG_REG7__se0_thdgrp_eop_MASK 0x200000 +#define WD_DEBUG_REG7__se0_thdgrp_eop__SHIFT 0x15 +#define WD_DEBUG_REG7__se1_thdgrp_is_event_MASK 0x400000 +#define WD_DEBUG_REG7__se1_thdgrp_is_event__SHIFT 0x16 +#define WD_DEBUG_REG7__se1_thdgrp_eop_MASK 0x800000 +#define WD_DEBUG_REG7__se1_thdgrp_eop__SHIFT 0x17 +#define WD_DEBUG_REG7__SPARE6_MASK 0xf000000 +#define WD_DEBUG_REG7__SPARE6__SHIFT 0x18 +#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr_MASK 0x10000000 +#define WD_DEBUG_REG7__tfreq_arb_tgroup_rtr__SHIFT 0x1c +#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts_MASK 0x20000000 +#define WD_DEBUG_REG7__arb_tfreq_tgroup_rts__SHIFT 0x1d +#define WD_DEBUG_REG7__arb_tfreq_tgroup_event_MASK 0x40000000 +#define WD_DEBUG_REG7__arb_tfreq_tgroup_event__SHIFT 0x1e +#define WD_DEBUG_REG7__te11_arb_busy_MASK 0x80000000 +#define WD_DEBUG_REG7__te11_arb_busy__SHIFT 0x1f +#define WD_DEBUG_REG8__pipe0_dr_MASK 0x1 +#define WD_DEBUG_REG8__pipe0_dr__SHIFT 0x0 +#define WD_DEBUG_REG8__pipe1_dr_MASK 0x2 +#define WD_DEBUG_REG8__pipe1_dr__SHIFT 0x1 +#define WD_DEBUG_REG8__pipe0_rtr_MASK 0x4 +#define WD_DEBUG_REG8__pipe0_rtr__SHIFT 0x2 +#define WD_DEBUG_REG8__pipe1_rtr_MASK 0x8 +#define WD_DEBUG_REG8__pipe1_rtr__SHIFT 0x3 +#define WD_DEBUG_REG8__tfreq_tg_fifo_empty_MASK 0x10 +#define WD_DEBUG_REG8__tfreq_tg_fifo_empty__SHIFT 0x4 +#define WD_DEBUG_REG8__tfreq_tg_fifo_full_MASK 0x20 +#define WD_DEBUG_REG8__tfreq_tg_fifo_full__SHIFT 0x5 +#define WD_DEBUG_REG8__tf_data_fifo_busy_q_MASK 0x40 +#define WD_DEBUG_REG8__tf_data_fifo_busy_q__SHIFT 0x6 +#define WD_DEBUG_REG8__tf_data_fifo_rtr_q_MASK 0x80 +#define WD_DEBUG_REG8__tf_data_fifo_rtr_q__SHIFT 0x7 +#define WD_DEBUG_REG8__tf_skid_fifo_empty_MASK 0x100 +#define WD_DEBUG_REG8__tf_skid_fifo_empty__SHIFT 0x8 +#define WD_DEBUG_REG8__tf_skid_fifo_full_MASK 0x200 +#define WD_DEBUG_REG8__tf_skid_fifo_full__SHIFT 0x9 +#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q_MASK 0x400 +#define WD_DEBUG_REG8__wd_tc_rdreq_rtr_q__SHIFT 0xa +#define WD_DEBUG_REG8__last_req_of_tg_p2_MASK 0x800 +#define WD_DEBUG_REG8__last_req_of_tg_p2__SHIFT 0xb +#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q_MASK 0x3f000 +#define WD_DEBUG_REG8__se0spi_wd_hs_done_cnt_q__SHIFT 0xc +#define WD_DEBUG_REG8__event_flag_p1_q_MASK 0x40000 +#define WD_DEBUG_REG8__event_flag_p1_q__SHIFT 0x12 +#define WD_DEBUG_REG8__null_flag_p1_q_MASK 0x80000 +#define WD_DEBUG_REG8__null_flag_p1_q__SHIFT 0x13 +#define WD_DEBUG_REG8__tf_data_fifo_cnt_q_MASK 0x7f00000 +#define WD_DEBUG_REG8__tf_data_fifo_cnt_q__SHIFT 0x14 +#define WD_DEBUG_REG8__second_tf_ret_data_q_MASK 0x8000000 +#define WD_DEBUG_REG8__second_tf_ret_data_q__SHIFT 0x1b +#define WD_DEBUG_REG8__first_req_of_tg_p1_q_MASK 0x10000000 +#define WD_DEBUG_REG8__first_req_of_tg_p1_q__SHIFT 0x1c +#define WD_DEBUG_REG8__WD_TC_rdreq_send_out_MASK 0x20000000 +#define WD_DEBUG_REG8__WD_TC_rdreq_send_out__SHIFT 0x1d +#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out_MASK 0x40000000 +#define WD_DEBUG_REG8__WD_TC_rdnfo_stall_out__SHIFT 0x1e +#define WD_DEBUG_REG8__TC_WD_rdret_valid_in_MASK 0x80000000 +#define WD_DEBUG_REG8__TC_WD_rdret_valid_in__SHIFT 0x1f +#define WD_DEBUG_REG9__pipe0_dr_MASK 0x1 +#define WD_DEBUG_REG9__pipe0_dr__SHIFT 0x0 +#define WD_DEBUG_REG9__pipec_tf_dr_MASK 0x2 +#define WD_DEBUG_REG9__pipec_tf_dr__SHIFT 0x1 +#define WD_DEBUG_REG9__pipe2_dr_MASK 0x4 +#define WD_DEBUG_REG9__pipe2_dr__SHIFT 0x2 +#define WD_DEBUG_REG9__event_or_null_flags_p0_q_MASK 0x8 +#define WD_DEBUG_REG9__event_or_null_flags_p0_q__SHIFT 0x3 +#define WD_DEBUG_REG9__pipe0_rtr_MASK 0x10 +#define WD_DEBUG_REG9__pipe0_rtr__SHIFT 0x4 +#define WD_DEBUG_REG9__pipe1_rtr_MASK 0x20 +#define WD_DEBUG_REG9__pipe1_rtr__SHIFT 0x5 +#define WD_DEBUG_REG9__pipec_tf_rtr_MASK 0x40 +#define WD_DEBUG_REG9__pipec_tf_rtr__SHIFT 0x6 +#define WD_DEBUG_REG9__pipe2_rtr_MASK 0x80 +#define WD_DEBUG_REG9__pipe2_rtr__SHIFT 0x7 +#define WD_DEBUG_REG9__ttp_patch_fifo_full_MASK 0x100 +#define WD_DEBUG_REG9__ttp_patch_fifo_full__SHIFT 0x8 +#define WD_DEBUG_REG9__ttp_patch_fifo_empty_MASK 0x200 +#define WD_DEBUG_REG9__ttp_patch_fifo_empty__SHIFT 0x9 +#define WD_DEBUG_REG9__ttp_tf_fifo_empty_MASK 0x400 +#define WD_DEBUG_REG9__ttp_tf_fifo_empty__SHIFT 0xa +#define WD_DEBUG_REG9__SPARE0_MASK 0xf800 +#define WD_DEBUG_REG9__SPARE0__SHIFT 0xb +#define WD_DEBUG_REG9__tf_fetch_state_q_MASK 0x70000 +#define WD_DEBUG_REG9__tf_fetch_state_q__SHIFT 0x10 +#define WD_DEBUG_REG9__last_patch_of_tg_MASK 0x80000 +#define WD_DEBUG_REG9__last_patch_of_tg__SHIFT 0x13 +#define WD_DEBUG_REG9__tf_pointer_p0_q_MASK 0xf00000 +#define WD_DEBUG_REG9__tf_pointer_p0_q__SHIFT 0x14 +#define WD_DEBUG_REG9__dynamic_hs_p0_q_MASK 0x1000000 +#define WD_DEBUG_REG9__dynamic_hs_p0_q__SHIFT 0x18 +#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q_MASK 0x2000000 +#define WD_DEBUG_REG9__first_fetch_of_tg_p0_q__SHIFT 0x19 +#define WD_DEBUG_REG9__mem_is_even_MASK 0x4000000 +#define WD_DEBUG_REG9__mem_is_even__SHIFT 0x1a +#define WD_DEBUG_REG9__SPARE1_MASK 0x8000000 +#define WD_DEBUG_REG9__SPARE1__SHIFT 0x1b +#define WD_DEBUG_REG9__SPARE2_MASK 0x30000000 +#define WD_DEBUG_REG9__SPARE2__SHIFT 0x1c +#define WD_DEBUG_REG9__pipe4_dr_MASK 0x40000000 +#define WD_DEBUG_REG9__pipe4_dr__SHIFT 0x1e +#define WD_DEBUG_REG9__pipe4_rtr_MASK 0x80000000 +#define WD_DEBUG_REG9__pipe4_rtr__SHIFT 0x1f +#define WD_DEBUG_REG10__ttp_pd_patch_rts_MASK 0x1 +#define WD_DEBUG_REG10__ttp_pd_patch_rts__SHIFT 0x0 +#define WD_DEBUG_REG10__ttp_pd_is_event_MASK 0x2 +#define WD_DEBUG_REG10__ttp_pd_is_event__SHIFT 0x1 +#define WD_DEBUG_REG10__ttp_pd_eopg_MASK 0x4 +#define WD_DEBUG_REG10__ttp_pd_eopg__SHIFT 0x2 +#define WD_DEBUG_REG10__ttp_pd_eop_MASK 0x8 +#define WD_DEBUG_REG10__ttp_pd_eop__SHIFT 0x3 +#define WD_DEBUG_REG10__pipe0_dr_MASK 0x10 +#define WD_DEBUG_REG10__pipe0_dr__SHIFT 0x4 +#define WD_DEBUG_REG10__pipe1_dr_MASK 0x20 +#define WD_DEBUG_REG10__pipe1_dr__SHIFT 0x5 +#define WD_DEBUG_REG10__pipe0_rtr_MASK 0x40 +#define WD_DEBUG_REG10__pipe0_rtr__SHIFT 0x6 +#define WD_DEBUG_REG10__pipe1_rtr_MASK 0x80 +#define WD_DEBUG_REG10__pipe1_rtr__SHIFT 0x7 +#define WD_DEBUG_REG10__donut_en_p1_q_MASK 0x100 +#define WD_DEBUG_REG10__donut_en_p1_q__SHIFT 0x8 +#define WD_DEBUG_REG10__donut_se_switch_p2_MASK 0x200 +#define WD_DEBUG_REG10__donut_se_switch_p2__SHIFT 0x9 +#define WD_DEBUG_REG10__patch_se_switch_p2_MASK 0x400 +#define WD_DEBUG_REG10__patch_se_switch_p2__SHIFT 0xa +#define WD_DEBUG_REG10__last_donut_switch_p2_MASK 0x800 +#define WD_DEBUG_REG10__last_donut_switch_p2__SHIFT 0xb +#define WD_DEBUG_REG10__last_donut_of_patch_p2_MASK 0x1000 +#define WD_DEBUG_REG10__last_donut_of_patch_p2__SHIFT 0xc +#define WD_DEBUG_REG10__is_event_p1_q_MASK 0x2000 +#define WD_DEBUG_REG10__is_event_p1_q__SHIFT 0xd +#define WD_DEBUG_REG10__eopg_p1_q_MASK 0x4000 +#define WD_DEBUG_REG10__eopg_p1_q__SHIFT 0xe +#define WD_DEBUG_REG10__eop_p1_q_MASK 0x8000 +#define WD_DEBUG_REG10__eop_p1_q__SHIFT 0xf +#define WD_DEBUG_REG10__patch_accum_q_MASK 0xff0000 +#define WD_DEBUG_REG10__patch_accum_q__SHIFT 0x10 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full_MASK 0x1000000 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_full__SHIFT 0x18 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty_MASK 0x2000000 +#define WD_DEBUG_REG10__wd_te11_out_se0_fifo_empty__SHIFT 0x19 +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full_MASK 0x4000000 +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_full__SHIFT 0x1a +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty_MASK 0x8000000 +#define WD_DEBUG_REG10__wd_te11_out_se1_fifo_empty__SHIFT 0x1b +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full_MASK 0x10000000 +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_full__SHIFT 0x1c +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty_MASK 0x20000000 +#define WD_DEBUG_REG10__wd_te11_out_se2_fifo_empty__SHIFT 0x1d +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full_MASK 0x40000000 +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_full__SHIFT 0x1e +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty_MASK 0x80000000 +#define WD_DEBUG_REG10__wd_te11_out_se3_fifo_empty__SHIFT 0x1f +#define IA_DEBUG_REG0__ia_busy_extended_MASK 0x1 +#define IA_DEBUG_REG0__ia_busy_extended__SHIFT 0x0 +#define IA_DEBUG_REG0__ia_nodma_busy_extended_MASK 0x2 +#define IA_DEBUG_REG0__ia_nodma_busy_extended__SHIFT 0x1 +#define IA_DEBUG_REG0__ia_busy_MASK 0x4 +#define IA_DEBUG_REG0__ia_busy__SHIFT 0x2 +#define IA_DEBUG_REG0__ia_nodma_busy_MASK 0x8 +#define IA_DEBUG_REG0__ia_nodma_busy__SHIFT 0x3 +#define IA_DEBUG_REG0__SPARE0_MASK 0x10 +#define IA_DEBUG_REG0__SPARE0__SHIFT 0x4 +#define IA_DEBUG_REG0__dma_req_busy_MASK 0x20 +#define IA_DEBUG_REG0__dma_req_busy__SHIFT 0x5 +#define IA_DEBUG_REG0__dma_busy_MASK 0x40 +#define IA_DEBUG_REG0__dma_busy__SHIFT 0x6 +#define IA_DEBUG_REG0__mc_xl8r_busy_MASK 0x80 +#define IA_DEBUG_REG0__mc_xl8r_busy__SHIFT 0x7 +#define IA_DEBUG_REG0__grp_busy_MASK 0x100 +#define IA_DEBUG_REG0__grp_busy__SHIFT 0x8 +#define IA_DEBUG_REG0__SPARE1_MASK 0x200 +#define IA_DEBUG_REG0__SPARE1__SHIFT 0x9 +#define IA_DEBUG_REG0__dma_grp_valid_MASK 0x400 +#define IA_DEBUG_REG0__dma_grp_valid__SHIFT 0xa +#define IA_DEBUG_REG0__grp_dma_read_MASK 0x800 +#define IA_DEBUG_REG0__grp_dma_read__SHIFT 0xb +#define IA_DEBUG_REG0__dma_grp_hp_valid_MASK 0x1000 +#define IA_DEBUG_REG0__dma_grp_hp_valid__SHIFT 0xc +#define IA_DEBUG_REG0__grp_dma_hp_read_MASK 0x2000 +#define IA_DEBUG_REG0__grp_dma_hp_read__SHIFT 0xd +#define IA_DEBUG_REG0__SPARE2_MASK 0xffc000 +#define IA_DEBUG_REG0__SPARE2__SHIFT 0xe +#define IA_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define IA_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define IA_DEBUG_REG0__core_clk_busy_MASK 0x2000000 +#define IA_DEBUG_REG0__core_clk_busy__SHIFT 0x19 +#define IA_DEBUG_REG0__SPARE3_MASK 0x4000000 +#define IA_DEBUG_REG0__SPARE3__SHIFT 0x1a +#define IA_DEBUG_REG0__SPARE4_MASK 0x8000000 +#define IA_DEBUG_REG0__SPARE4__SHIFT 0x1b +#define IA_DEBUG_REG0__sclk_reg_vld_MASK 0x10000000 +#define IA_DEBUG_REG0__sclk_reg_vld__SHIFT 0x1c +#define IA_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 +#define IA_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d +#define IA_DEBUG_REG0__SPARE5_MASK 0x40000000 +#define IA_DEBUG_REG0__SPARE5__SHIFT 0x1e +#define IA_DEBUG_REG0__SPARE6_MASK 0x80000000 +#define IA_DEBUG_REG0__SPARE6__SHIFT 0x1f +#define IA_DEBUG_REG1__dma_input_fifo_empty_MASK 0x1 +#define IA_DEBUG_REG1__dma_input_fifo_empty__SHIFT 0x0 +#define IA_DEBUG_REG1__dma_input_fifo_full_MASK 0x2 +#define IA_DEBUG_REG1__dma_input_fifo_full__SHIFT 0x1 +#define IA_DEBUG_REG1__start_new_packet_MASK 0x4 +#define IA_DEBUG_REG1__start_new_packet__SHIFT 0x2 +#define IA_DEBUG_REG1__dma_rdreq_dr_q_MASK 0x8 +#define IA_DEBUG_REG1__dma_rdreq_dr_q__SHIFT 0x3 +#define IA_DEBUG_REG1__dma_zero_indices_q_MASK 0x10 +#define IA_DEBUG_REG1__dma_zero_indices_q__SHIFT 0x4 +#define IA_DEBUG_REG1__dma_buf_type_q_MASK 0x60 +#define IA_DEBUG_REG1__dma_buf_type_q__SHIFT 0x5 +#define IA_DEBUG_REG1__dma_req_path_q_MASK 0x80 +#define IA_DEBUG_REG1__dma_req_path_q__SHIFT 0x7 +#define IA_DEBUG_REG1__discard_1st_chunk_MASK 0x100 +#define IA_DEBUG_REG1__discard_1st_chunk__SHIFT 0x8 +#define IA_DEBUG_REG1__discard_2nd_chunk_MASK 0x200 +#define IA_DEBUG_REG1__discard_2nd_chunk__SHIFT 0x9 +#define IA_DEBUG_REG1__second_tc_ret_data_q_MASK 0x400 +#define IA_DEBUG_REG1__second_tc_ret_data_q__SHIFT 0xa +#define IA_DEBUG_REG1__dma_tc_ret_sel_q_MASK 0x800 +#define IA_DEBUG_REG1__dma_tc_ret_sel_q__SHIFT 0xb +#define IA_DEBUG_REG1__last_rdreq_in_dma_op_MASK 0x1000 +#define IA_DEBUG_REG1__last_rdreq_in_dma_op__SHIFT 0xc +#define IA_DEBUG_REG1__dma_mask_fifo_empty_MASK 0x2000 +#define IA_DEBUG_REG1__dma_mask_fifo_empty__SHIFT 0xd +#define IA_DEBUG_REG1__dma_data_fifo_empty_q_MASK 0x4000 +#define IA_DEBUG_REG1__dma_data_fifo_empty_q__SHIFT 0xe +#define IA_DEBUG_REG1__dma_data_fifo_full_MASK 0x8000 +#define IA_DEBUG_REG1__dma_data_fifo_full__SHIFT 0xf +#define IA_DEBUG_REG1__dma_req_fifo_empty_MASK 0x10000 +#define IA_DEBUG_REG1__dma_req_fifo_empty__SHIFT 0x10 +#define IA_DEBUG_REG1__dma_req_fifo_full_MASK 0x20000 +#define IA_DEBUG_REG1__dma_req_fifo_full__SHIFT 0x11 +#define IA_DEBUG_REG1__stage2_dr_MASK 0x40000 +#define IA_DEBUG_REG1__stage2_dr__SHIFT 0x12 +#define IA_DEBUG_REG1__stage2_rtr_MASK 0x80000 +#define IA_DEBUG_REG1__stage2_rtr__SHIFT 0x13 +#define IA_DEBUG_REG1__stage3_dr_MASK 0x100000 +#define IA_DEBUG_REG1__stage3_dr__SHIFT 0x14 +#define IA_DEBUG_REG1__stage3_rtr_MASK 0x200000 +#define IA_DEBUG_REG1__stage3_rtr__SHIFT 0x15 +#define IA_DEBUG_REG1__stage4_dr_MASK 0x400000 +#define IA_DEBUG_REG1__stage4_dr__SHIFT 0x16 +#define IA_DEBUG_REG1__stage4_rtr_MASK 0x800000 +#define IA_DEBUG_REG1__stage4_rtr__SHIFT 0x17 +#define IA_DEBUG_REG1__dma_skid_fifo_empty_MASK 0x1000000 +#define IA_DEBUG_REG1__dma_skid_fifo_empty__SHIFT 0x18 +#define IA_DEBUG_REG1__dma_skid_fifo_full_MASK 0x2000000 +#define IA_DEBUG_REG1__dma_skid_fifo_full__SHIFT 0x19 +#define IA_DEBUG_REG1__dma_grp_valid_MASK 0x4000000 +#define IA_DEBUG_REG1__dma_grp_valid__SHIFT 0x1a +#define IA_DEBUG_REG1__grp_dma_read_MASK 0x8000000 +#define IA_DEBUG_REG1__grp_dma_read__SHIFT 0x1b +#define IA_DEBUG_REG1__current_data_valid_MASK 0x10000000 +#define IA_DEBUG_REG1__current_data_valid__SHIFT 0x1c +#define IA_DEBUG_REG1__out_of_range_r2_q_MASK 0x20000000 +#define IA_DEBUG_REG1__out_of_range_r2_q__SHIFT 0x1d +#define IA_DEBUG_REG1__dma_mask_fifo_we_MASK 0x40000000 +#define IA_DEBUG_REG1__dma_mask_fifo_we__SHIFT 0x1e +#define IA_DEBUG_REG1__dma_ret_data_we_q_MASK 0x80000000 +#define IA_DEBUG_REG1__dma_ret_data_we_q__SHIFT 0x1f +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty_MASK 0x1 +#define IA_DEBUG_REG2__hp_dma_input_fifo_empty__SHIFT 0x0 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full_MASK 0x2 +#define IA_DEBUG_REG2__hp_dma_input_fifo_full__SHIFT 0x1 +#define IA_DEBUG_REG2__hp_start_new_packet_MASK 0x4 +#define IA_DEBUG_REG2__hp_start_new_packet__SHIFT 0x2 +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q_MASK 0x8 +#define IA_DEBUG_REG2__hp_dma_rdreq_dr_q__SHIFT 0x3 +#define IA_DEBUG_REG2__hp_dma_zero_indices_q_MASK 0x10 +#define IA_DEBUG_REG2__hp_dma_zero_indices_q__SHIFT 0x4 +#define IA_DEBUG_REG2__hp_dma_buf_type_q_MASK 0x60 +#define IA_DEBUG_REG2__hp_dma_buf_type_q__SHIFT 0x5 +#define IA_DEBUG_REG2__hp_dma_req_path_q_MASK 0x80 +#define IA_DEBUG_REG2__hp_dma_req_path_q__SHIFT 0x7 +#define IA_DEBUG_REG2__hp_discard_1st_chunk_MASK 0x100 +#define IA_DEBUG_REG2__hp_discard_1st_chunk__SHIFT 0x8 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk_MASK 0x200 +#define IA_DEBUG_REG2__hp_discard_2nd_chunk__SHIFT 0x9 +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q_MASK 0x400 +#define IA_DEBUG_REG2__hp_second_tc_ret_data_q__SHIFT 0xa +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q_MASK 0x800 +#define IA_DEBUG_REG2__hp_dma_tc_ret_sel_q__SHIFT 0xb +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op_MASK 0x1000 +#define IA_DEBUG_REG2__hp_last_rdreq_in_dma_op__SHIFT 0xc +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty_MASK 0x2000 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_empty__SHIFT 0xd +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q_MASK 0x4000 +#define IA_DEBUG_REG2__hp_dma_data_fifo_empty_q__SHIFT 0xe +#define IA_DEBUG_REG2__hp_dma_data_fifo_full_MASK 0x8000 +#define IA_DEBUG_REG2__hp_dma_data_fifo_full__SHIFT 0xf +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty_MASK 0x10000 +#define IA_DEBUG_REG2__hp_dma_req_fifo_empty__SHIFT 0x10 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full_MASK 0x20000 +#define IA_DEBUG_REG2__hp_dma_req_fifo_full__SHIFT 0x11 +#define IA_DEBUG_REG2__hp_stage2_dr_MASK 0x40000 +#define IA_DEBUG_REG2__hp_stage2_dr__SHIFT 0x12 +#define IA_DEBUG_REG2__hp_stage2_rtr_MASK 0x80000 +#define IA_DEBUG_REG2__hp_stage2_rtr__SHIFT 0x13 +#define IA_DEBUG_REG2__hp_stage3_dr_MASK 0x100000 +#define IA_DEBUG_REG2__hp_stage3_dr__SHIFT 0x14 +#define IA_DEBUG_REG2__hp_stage3_rtr_MASK 0x200000 +#define IA_DEBUG_REG2__hp_stage3_rtr__SHIFT 0x15 +#define IA_DEBUG_REG2__hp_stage4_dr_MASK 0x400000 +#define IA_DEBUG_REG2__hp_stage4_dr__SHIFT 0x16 +#define IA_DEBUG_REG2__hp_stage4_rtr_MASK 0x800000 +#define IA_DEBUG_REG2__hp_stage4_rtr__SHIFT 0x17 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty_MASK 0x1000000 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_empty__SHIFT 0x18 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full_MASK 0x2000000 +#define IA_DEBUG_REG2__hp_dma_skid_fifo_full__SHIFT 0x19 +#define IA_DEBUG_REG2__hp_dma_grp_valid_MASK 0x4000000 +#define IA_DEBUG_REG2__hp_dma_grp_valid__SHIFT 0x1a +#define IA_DEBUG_REG2__hp_grp_dma_read_MASK 0x8000000 +#define IA_DEBUG_REG2__hp_grp_dma_read__SHIFT 0x1b +#define IA_DEBUG_REG2__hp_current_data_valid_MASK 0x10000000 +#define IA_DEBUG_REG2__hp_current_data_valid__SHIFT 0x1c +#define IA_DEBUG_REG2__hp_out_of_range_r2_q_MASK 0x20000000 +#define IA_DEBUG_REG2__hp_out_of_range_r2_q__SHIFT 0x1d +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we_MASK 0x40000000 +#define IA_DEBUG_REG2__hp_dma_mask_fifo_we__SHIFT 0x1e +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q_MASK 0x80000000 +#define IA_DEBUG_REG2__hp_dma_ret_data_we_q__SHIFT 0x1f +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid_MASK 0x1 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_valid__SHIFT 0x0 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read_MASK 0x2 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_read__SHIFT 0x1 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out_MASK 0x4 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_null_out__SHIFT 0x2 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out_MASK 0x8 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_eop_out__SHIFT 0x3 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out_MASK 0x10 +#define IA_DEBUG_REG3__dma_pipe0_rdreq_use_tc_out__SHIFT 0x4 +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0_MASK 0x20 +#define IA_DEBUG_REG3__grp_dma_draw_is_pipe0__SHIFT 0x5 +#define IA_DEBUG_REG3__must_service_pipe0_req_MASK 0x40 +#define IA_DEBUG_REG3__must_service_pipe0_req__SHIFT 0x6 +#define IA_DEBUG_REG3__send_pipe1_req_MASK 0x80 +#define IA_DEBUG_REG3__send_pipe1_req__SHIFT 0x7 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid_MASK 0x100 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_valid__SHIFT 0x8 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read_MASK 0x200 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_read__SHIFT 0x9 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out_MASK 0x400 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_null_out__SHIFT 0xa +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out_MASK 0x800 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_eop_out__SHIFT 0xb +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out_MASK 0x1000 +#define IA_DEBUG_REG3__dma_pipe1_rdreq_use_tc_out__SHIFT 0xc +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q_MASK 0x2000 +#define IA_DEBUG_REG3__ia_mc_rdreq_rtr_q__SHIFT 0xd +#define IA_DEBUG_REG3__mc_out_rtr_MASK 0x4000 +#define IA_DEBUG_REG3__mc_out_rtr__SHIFT 0xe +#define IA_DEBUG_REG3__dma_rdreq_send_out_MASK 0x8000 +#define IA_DEBUG_REG3__dma_rdreq_send_out__SHIFT 0xf +#define IA_DEBUG_REG3__pipe0_dr_MASK 0x10000 +#define IA_DEBUG_REG3__pipe0_dr__SHIFT 0x10 +#define IA_DEBUG_REG3__pipe0_rtr_MASK 0x20000 +#define IA_DEBUG_REG3__pipe0_rtr__SHIFT 0x11 +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q_MASK 0x40000 +#define IA_DEBUG_REG3__ia_tc_rdreq_rtr_q__SHIFT 0x12 +#define IA_DEBUG_REG3__tc_out_rtr_MASK 0x80000 +#define IA_DEBUG_REG3__tc_out_rtr__SHIFT 0x13 +#define IA_DEBUG_REG3__pair0_valid_p1_MASK 0x100000 +#define IA_DEBUG_REG3__pair0_valid_p1__SHIFT 0x14 +#define IA_DEBUG_REG3__pair1_valid_p1_MASK 0x200000 +#define IA_DEBUG_REG3__pair1_valid_p1__SHIFT 0x15 +#define IA_DEBUG_REG3__pair2_valid_p1_MASK 0x400000 +#define IA_DEBUG_REG3__pair2_valid_p1__SHIFT 0x16 +#define IA_DEBUG_REG3__pair3_valid_p1_MASK 0x800000 +#define IA_DEBUG_REG3__pair3_valid_p1__SHIFT 0x17 +#define IA_DEBUG_REG3__tc_req_count_q_MASK 0x3000000 +#define IA_DEBUG_REG3__tc_req_count_q__SHIFT 0x18 +#define IA_DEBUG_REG3__discard_1st_chunk_MASK 0x4000000 +#define IA_DEBUG_REG3__discard_1st_chunk__SHIFT 0x1a +#define IA_DEBUG_REG3__discard_2nd_chunk_MASK 0x8000000 +#define IA_DEBUG_REG3__discard_2nd_chunk__SHIFT 0x1b +#define IA_DEBUG_REG3__last_tc_req_p1_MASK 0x10000000 +#define IA_DEBUG_REG3__last_tc_req_p1__SHIFT 0x1c +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out_MASK 0x20000000 +#define IA_DEBUG_REG3__IA_TC_rdreq_send_out__SHIFT 0x1d +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in_MASK 0x40000000 +#define IA_DEBUG_REG3__TC_IA_rdret_valid_in__SHIFT 0x1e +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in_MASK 0x80000000 +#define IA_DEBUG_REG3__TAP_IA_rdret_vld_in__SHIFT 0x1f +#define IA_DEBUG_REG4__pipe0_dr_MASK 0x1 +#define IA_DEBUG_REG4__pipe0_dr__SHIFT 0x0 +#define IA_DEBUG_REG4__pipe1_dr_MASK 0x2 +#define IA_DEBUG_REG4__pipe1_dr__SHIFT 0x1 +#define IA_DEBUG_REG4__pipe2_dr_MASK 0x4 +#define IA_DEBUG_REG4__pipe2_dr__SHIFT 0x2 +#define IA_DEBUG_REG4__pipe3_dr_MASK 0x8 +#define IA_DEBUG_REG4__pipe3_dr__SHIFT 0x3 +#define IA_DEBUG_REG4__pipe4_dr_MASK 0x10 +#define IA_DEBUG_REG4__pipe4_dr__SHIFT 0x4 +#define IA_DEBUG_REG4__pipe5_dr_MASK 0x20 +#define IA_DEBUG_REG4__pipe5_dr__SHIFT 0x5 +#define IA_DEBUG_REG4__grp_se0_fifo_empty_MASK 0x40 +#define IA_DEBUG_REG4__grp_se0_fifo_empty__SHIFT 0x6 +#define IA_DEBUG_REG4__grp_se0_fifo_full_MASK 0x80 +#define IA_DEBUG_REG4__grp_se0_fifo_full__SHIFT 0x7 +#define IA_DEBUG_REG4__pipe0_rtr_MASK 0x100 +#define IA_DEBUG_REG4__pipe0_rtr__SHIFT 0x8 +#define IA_DEBUG_REG4__pipe1_rtr_MASK 0x200 +#define IA_DEBUG_REG4__pipe1_rtr__SHIFT 0x9 +#define IA_DEBUG_REG4__pipe2_rtr_MASK 0x400 +#define IA_DEBUG_REG4__pipe2_rtr__SHIFT 0xa +#define IA_DEBUG_REG4__pipe3_rtr_MASK 0x800 +#define IA_DEBUG_REG4__pipe3_rtr__SHIFT 0xb +#define IA_DEBUG_REG4__pipe4_rtr_MASK 0x1000 +#define IA_DEBUG_REG4__pipe4_rtr__SHIFT 0xc +#define IA_DEBUG_REG4__pipe5_rtr_MASK 0x2000 +#define IA_DEBUG_REG4__pipe5_rtr__SHIFT 0xd +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q_MASK 0x4000 +#define IA_DEBUG_REG4__ia_vgt_prim_rtr_q__SHIFT 0xe +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q_MASK 0x8000 +#define IA_DEBUG_REG4__ia_se1vgt_prim_rtr_q__SHIFT 0xf +#define IA_DEBUG_REG4__di_major_mode_p1_q_MASK 0x10000 +#define IA_DEBUG_REG4__di_major_mode_p1_q__SHIFT 0x10 +#define IA_DEBUG_REG4__gs_mode_p1_q_MASK 0xe0000 +#define IA_DEBUG_REG4__gs_mode_p1_q__SHIFT 0x11 +#define IA_DEBUG_REG4__di_event_flag_p1_q_MASK 0x100000 +#define IA_DEBUG_REG4__di_event_flag_p1_q__SHIFT 0x14 +#define IA_DEBUG_REG4__di_state_sel_p1_q_MASK 0xe00000 +#define IA_DEBUG_REG4__di_state_sel_p1_q__SHIFT 0x15 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q_MASK 0x1000000 +#define IA_DEBUG_REG4__draw_opaq_en_p1_q__SHIFT 0x18 +#define IA_DEBUG_REG4__draw_opaq_active_q_MASK 0x2000000 +#define IA_DEBUG_REG4__draw_opaq_active_q__SHIFT 0x19 +#define IA_DEBUG_REG4__di_source_select_p1_q_MASK 0xc000000 +#define IA_DEBUG_REG4__di_source_select_p1_q__SHIFT 0x1a +#define IA_DEBUG_REG4__ready_to_read_di_MASK 0x10000000 +#define IA_DEBUG_REG4__ready_to_read_di__SHIFT 0x1c +#define IA_DEBUG_REG4__di_first_group_of_draw_q_MASK 0x20000000 +#define IA_DEBUG_REG4__di_first_group_of_draw_q__SHIFT 0x1d +#define IA_DEBUG_REG4__last_shift_of_draw_MASK 0x40000000 +#define IA_DEBUG_REG4__last_shift_of_draw__SHIFT 0x1e +#define IA_DEBUG_REG4__current_shift_is_vect1_q_MASK 0x80000000 +#define IA_DEBUG_REG4__current_shift_is_vect1_q__SHIFT 0x1f +#define IA_DEBUG_REG5__di_index_counter_q_15_0_MASK 0xffff +#define IA_DEBUG_REG5__di_index_counter_q_15_0__SHIFT 0x0 +#define IA_DEBUG_REG5__instanceid_13_0_MASK 0x3fff0000 +#define IA_DEBUG_REG5__instanceid_13_0__SHIFT 0x10 +#define IA_DEBUG_REG5__draw_input_fifo_full_MASK 0x40000000 +#define IA_DEBUG_REG5__draw_input_fifo_full__SHIFT 0x1e +#define IA_DEBUG_REG5__draw_input_fifo_empty_MASK 0x80000000 +#define IA_DEBUG_REG5__draw_input_fifo_empty__SHIFT 0x1f +#define IA_DEBUG_REG6__current_shift_q_MASK 0xf +#define IA_DEBUG_REG6__current_shift_q__SHIFT 0x0 +#define IA_DEBUG_REG6__current_stride_pre_MASK 0xf0 +#define IA_DEBUG_REG6__current_stride_pre__SHIFT 0x4 +#define IA_DEBUG_REG6__current_stride_q_MASK 0x1f00 +#define IA_DEBUG_REG6__current_stride_q__SHIFT 0x8 +#define IA_DEBUG_REG6__first_group_partial_MASK 0x2000 +#define IA_DEBUG_REG6__first_group_partial__SHIFT 0xd +#define IA_DEBUG_REG6__second_group_partial_MASK 0x4000 +#define IA_DEBUG_REG6__second_group_partial__SHIFT 0xe +#define IA_DEBUG_REG6__curr_prim_partial_MASK 0x8000 +#define IA_DEBUG_REG6__curr_prim_partial__SHIFT 0xf +#define IA_DEBUG_REG6__next_stride_q_MASK 0x1f0000 +#define IA_DEBUG_REG6__next_stride_q__SHIFT 0x10 +#define IA_DEBUG_REG6__next_group_partial_MASK 0x200000 +#define IA_DEBUG_REG6__next_group_partial__SHIFT 0x15 +#define IA_DEBUG_REG6__after_group_partial_MASK 0x400000 +#define IA_DEBUG_REG6__after_group_partial__SHIFT 0x16 +#define IA_DEBUG_REG6__extract_group_MASK 0x800000 +#define IA_DEBUG_REG6__extract_group__SHIFT 0x17 +#define IA_DEBUG_REG6__grp_shift_debug_data_MASK 0xff000000 +#define IA_DEBUG_REG6__grp_shift_debug_data__SHIFT 0x18 +#define IA_DEBUG_REG7__reset_indx_state_q_MASK 0xf +#define IA_DEBUG_REG7__reset_indx_state_q__SHIFT 0x0 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q_MASK 0xf0 +#define IA_DEBUG_REG7__shift_vect_valid_p2_q__SHIFT 0x4 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q_MASK 0xf00 +#define IA_DEBUG_REG7__shift_vect1_valid_p2_q__SHIFT 0x8 +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q_MASK 0xf000 +#define IA_DEBUG_REG7__shift_vect0_reset_match_p2_q__SHIFT 0xc +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q_MASK 0xf0000 +#define IA_DEBUG_REG7__shift_vect1_reset_match_p2_q__SHIFT 0x10 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q_MASK 0x700000 +#define IA_DEBUG_REG7__num_indx_in_group_p2_q__SHIFT 0x14 +#define IA_DEBUG_REG7__last_group_of_draw_p2_q_MASK 0x800000 +#define IA_DEBUG_REG7__last_group_of_draw_p2_q__SHIFT 0x17 +#define IA_DEBUG_REG7__shift_event_flag_p2_q_MASK 0x1000000 +#define IA_DEBUG_REG7__shift_event_flag_p2_q__SHIFT 0x18 +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q_MASK 0x2000000 +#define IA_DEBUG_REG7__indx_shift_is_one_p2_q__SHIFT 0x19 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q_MASK 0x4000000 +#define IA_DEBUG_REG7__indx_shift_is_two_p2_q__SHIFT 0x1a +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q_MASK 0x8000000 +#define IA_DEBUG_REG7__indx_stride_is_four_p2_q__SHIFT 0x1b +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q_MASK 0x10000000 +#define IA_DEBUG_REG7__shift_prim1_reset_p3_q__SHIFT 0x1c +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q_MASK 0x20000000 +#define IA_DEBUG_REG7__shift_prim1_partial_p3_q__SHIFT 0x1d +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q_MASK 0x40000000 +#define IA_DEBUG_REG7__shift_prim0_reset_p3_q__SHIFT 0x1e +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q_MASK 0x80000000 +#define IA_DEBUG_REG7__shift_prim0_partial_p3_q__SHIFT 0x1f +#define IA_DEBUG_REG8__di_prim_type_p1_q_MASK 0x1f +#define IA_DEBUG_REG8__di_prim_type_p1_q__SHIFT 0x0 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q_MASK 0x20 +#define IA_DEBUG_REG8__two_cycle_xfer_p1_q__SHIFT 0x5 +#define IA_DEBUG_REG8__two_prim_input_p1_q_MASK 0x40 +#define IA_DEBUG_REG8__two_prim_input_p1_q__SHIFT 0x6 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q_MASK 0x80 +#define IA_DEBUG_REG8__shift_vect_end_of_packet_p5_q__SHIFT 0x7 +#define IA_DEBUG_REG8__last_group_of_inst_p5_q_MASK 0x100 +#define IA_DEBUG_REG8__last_group_of_inst_p5_q__SHIFT 0x8 +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q_MASK 0x200 +#define IA_DEBUG_REG8__shift_prim1_null_flag_p5_q__SHIFT 0x9 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q_MASK 0x400 +#define IA_DEBUG_REG8__shift_prim0_null_flag_p5_q__SHIFT 0xa +#define IA_DEBUG_REG8__grp_continued_MASK 0x800 +#define IA_DEBUG_REG8__grp_continued__SHIFT 0xb +#define IA_DEBUG_REG8__grp_state_sel_MASK 0x7000 +#define IA_DEBUG_REG8__grp_state_sel__SHIFT 0xc +#define IA_DEBUG_REG8__grp_sub_prim_type_MASK 0x1f8000 +#define IA_DEBUG_REG8__grp_sub_prim_type__SHIFT 0xf +#define IA_DEBUG_REG8__grp_output_path_MASK 0xe00000 +#define IA_DEBUG_REG8__grp_output_path__SHIFT 0x15 +#define IA_DEBUG_REG8__grp_null_primitive_MASK 0x1000000 +#define IA_DEBUG_REG8__grp_null_primitive__SHIFT 0x18 +#define IA_DEBUG_REG8__grp_eop_MASK 0x2000000 +#define IA_DEBUG_REG8__grp_eop__SHIFT 0x19 +#define IA_DEBUG_REG8__grp_eopg_MASK 0x4000000 +#define IA_DEBUG_REG8__grp_eopg__SHIFT 0x1a +#define IA_DEBUG_REG8__grp_event_flag_MASK 0x8000000 +#define IA_DEBUG_REG8__grp_event_flag__SHIFT 0x1b +#define IA_DEBUG_REG8__grp_components_valid_MASK 0xf0000000 +#define IA_DEBUG_REG8__grp_components_valid__SHIFT 0x1c +#define IA_DEBUG_REG9__send_to_se1_p6_MASK 0x1 +#define IA_DEBUG_REG9__send_to_se1_p6__SHIFT 0x0 +#define IA_DEBUG_REG9__gfx_se_switch_p6_MASK 0x2 +#define IA_DEBUG_REG9__gfx_se_switch_p6__SHIFT 0x1 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6_MASK 0x4 +#define IA_DEBUG_REG9__null_eoi_xfer_prim1_p6__SHIFT 0x2 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6_MASK 0x8 +#define IA_DEBUG_REG9__null_eoi_xfer_prim0_p6__SHIFT 0x3 +#define IA_DEBUG_REG9__prim1_eoi_p6_MASK 0x10 +#define IA_DEBUG_REG9__prim1_eoi_p6__SHIFT 0x4 +#define IA_DEBUG_REG9__prim0_eoi_p6_MASK 0x20 +#define IA_DEBUG_REG9__prim0_eoi_p6__SHIFT 0x5 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6_MASK 0x40 +#define IA_DEBUG_REG9__prim1_valid_eopg_p6__SHIFT 0x6 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6_MASK 0x80 +#define IA_DEBUG_REG9__prim0_valid_eopg_p6__SHIFT 0x7 +#define IA_DEBUG_REG9__prim1_to_other_se_p6_MASK 0x100 +#define IA_DEBUG_REG9__prim1_to_other_se_p6__SHIFT 0x8 +#define IA_DEBUG_REG9__eopg_on_last_prim_p6_MASK 0x200 +#define IA_DEBUG_REG9__eopg_on_last_prim_p6__SHIFT 0x9 +#define IA_DEBUG_REG9__eopg_between_prims_p6_MASK 0x400 +#define IA_DEBUG_REG9__eopg_between_prims_p6__SHIFT 0xa +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6_MASK 0x800 +#define IA_DEBUG_REG9__prim_count_eq_group_size_p6__SHIFT 0xb +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6_MASK 0x1000 +#define IA_DEBUG_REG9__prim_count_gt_group_size_p6__SHIFT 0xc +#define IA_DEBUG_REG9__two_prim_output_p5_q_MASK 0x2000 +#define IA_DEBUG_REG9__two_prim_output_p5_q__SHIFT 0xd +#define IA_DEBUG_REG9__SPARE0_MASK 0x4000 +#define IA_DEBUG_REG9__SPARE0__SHIFT 0xe +#define IA_DEBUG_REG9__SPARE1_MASK 0x8000 +#define IA_DEBUG_REG9__SPARE1__SHIFT 0xf +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q_MASK 0x10000 +#define IA_DEBUG_REG9__shift_vect_end_of_packet_p5_q__SHIFT 0x10 +#define IA_DEBUG_REG9__prim1_xfer_p6_MASK 0x20000 +#define IA_DEBUG_REG9__prim1_xfer_p6__SHIFT 0x11 +#define IA_DEBUG_REG9__grp_se1_fifo_empty_MASK 0x40000 +#define IA_DEBUG_REG9__grp_se1_fifo_empty__SHIFT 0x12 +#define IA_DEBUG_REG9__grp_se1_fifo_full_MASK 0x80000 +#define IA_DEBUG_REG9__grp_se1_fifo_full__SHIFT 0x13 +#define IA_DEBUG_REG9__prim_counter_q_MASK 0xfff00000 +#define IA_DEBUG_REG9__prim_counter_q__SHIFT 0x14 +#define VGT_DEBUG_REG0__vgt_busy_extended_MASK 0x1 +#define VGT_DEBUG_REG0__vgt_busy_extended__SHIFT 0x0 +#define VGT_DEBUG_REG0__SPARE9_MASK 0x2 +#define VGT_DEBUG_REG0__SPARE9__SHIFT 0x1 +#define VGT_DEBUG_REG0__vgt_busy_MASK 0x4 +#define VGT_DEBUG_REG0__vgt_busy__SHIFT 0x2 +#define VGT_DEBUG_REG0__SPARE8_MASK 0x8 +#define VGT_DEBUG_REG0__SPARE8__SHIFT 0x3 +#define VGT_DEBUG_REG0__SPARE7_MASK 0x10 +#define VGT_DEBUG_REG0__SPARE7__SHIFT 0x4 +#define VGT_DEBUG_REG0__SPARE6_MASK 0x20 +#define VGT_DEBUG_REG0__SPARE6__SHIFT 0x5 +#define VGT_DEBUG_REG0__SPARE5_MASK 0x40 +#define VGT_DEBUG_REG0__SPARE5__SHIFT 0x6 +#define VGT_DEBUG_REG0__SPARE4_MASK 0x80 +#define VGT_DEBUG_REG0__SPARE4__SHIFT 0x7 +#define VGT_DEBUG_REG0__pi_busy_MASK 0x100 +#define VGT_DEBUG_REG0__pi_busy__SHIFT 0x8 +#define VGT_DEBUG_REG0__vr_pi_busy_MASK 0x200 +#define VGT_DEBUG_REG0__vr_pi_busy__SHIFT 0x9 +#define VGT_DEBUG_REG0__pt_pi_busy_MASK 0x400 +#define VGT_DEBUG_REG0__pt_pi_busy__SHIFT 0xa +#define VGT_DEBUG_REG0__te_pi_busy_MASK 0x800 +#define VGT_DEBUG_REG0__te_pi_busy__SHIFT 0xb +#define VGT_DEBUG_REG0__gs_busy_MASK 0x1000 +#define VGT_DEBUG_REG0__gs_busy__SHIFT 0xc +#define VGT_DEBUG_REG0__rcm_busy_MASK 0x2000 +#define VGT_DEBUG_REG0__rcm_busy__SHIFT 0xd +#define VGT_DEBUG_REG0__tm_busy_MASK 0x4000 +#define VGT_DEBUG_REG0__tm_busy__SHIFT 0xe +#define VGT_DEBUG_REG0__cm_busy_MASK 0x8000 +#define VGT_DEBUG_REG0__cm_busy__SHIFT 0xf +#define VGT_DEBUG_REG0__gog_busy_MASK 0x10000 +#define VGT_DEBUG_REG0__gog_busy__SHIFT 0x10 +#define VGT_DEBUG_REG0__frmt_busy_MASK 0x20000 +#define VGT_DEBUG_REG0__frmt_busy__SHIFT 0x11 +#define VGT_DEBUG_REG0__SPARE10_MASK 0x40000 +#define VGT_DEBUG_REG0__SPARE10__SHIFT 0x12 +#define VGT_DEBUG_REG0__te11_pi_busy_MASK 0x80000 +#define VGT_DEBUG_REG0__te11_pi_busy__SHIFT 0x13 +#define VGT_DEBUG_REG0__SPARE3_MASK 0x100000 +#define VGT_DEBUG_REG0__SPARE3__SHIFT 0x14 +#define VGT_DEBUG_REG0__combined_out_busy_MASK 0x200000 +#define VGT_DEBUG_REG0__combined_out_busy__SHIFT 0x15 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy_MASK 0x400000 +#define VGT_DEBUG_REG0__spi_vs_interfaces_busy__SHIFT 0x16 +#define VGT_DEBUG_REG0__pa_interfaces_busy_MASK 0x800000 +#define VGT_DEBUG_REG0__pa_interfaces_busy__SHIFT 0x17 +#define VGT_DEBUG_REG0__reg_clk_busy_MASK 0x1000000 +#define VGT_DEBUG_REG0__reg_clk_busy__SHIFT 0x18 +#define VGT_DEBUG_REG0__SPARE2_MASK 0x2000000 +#define VGT_DEBUG_REG0__SPARE2__SHIFT 0x19 +#define VGT_DEBUG_REG0__core_clk_busy_MASK 0x4000000 +#define VGT_DEBUG_REG0__core_clk_busy__SHIFT 0x1a +#define VGT_DEBUG_REG0__gs_clk_busy_MASK 0x8000000 +#define VGT_DEBUG_REG0__gs_clk_busy__SHIFT 0x1b +#define VGT_DEBUG_REG0__SPARE1_MASK 0x10000000 +#define VGT_DEBUG_REG0__SPARE1__SHIFT 0x1c +#define VGT_DEBUG_REG0__sclk_core_vld_MASK 0x20000000 +#define VGT_DEBUG_REG0__sclk_core_vld__SHIFT 0x1d +#define VGT_DEBUG_REG0__sclk_gs_vld_MASK 0x40000000 +#define VGT_DEBUG_REG0__sclk_gs_vld__SHIFT 0x1e +#define VGT_DEBUG_REG0__SPARE0_MASK 0x80000000 +#define VGT_DEBUG_REG0__SPARE0__SHIFT 0x1f +#define VGT_DEBUG_REG1__SPARE9_MASK 0x1 +#define VGT_DEBUG_REG1__SPARE9__SHIFT 0x0 +#define VGT_DEBUG_REG1__SPARE8_MASK 0x2 +#define VGT_DEBUG_REG1__SPARE8__SHIFT 0x1 +#define VGT_DEBUG_REG1__SPARE7_MASK 0x4 +#define VGT_DEBUG_REG1__SPARE7__SHIFT 0x2 +#define VGT_DEBUG_REG1__SPARE6_MASK 0x8 +#define VGT_DEBUG_REG1__SPARE6__SHIFT 0x3 +#define VGT_DEBUG_REG1__SPARE5_MASK 0x10 +#define VGT_DEBUG_REG1__SPARE5__SHIFT 0x4 +#define VGT_DEBUG_REG1__SPARE4_MASK 0x20 +#define VGT_DEBUG_REG1__SPARE4__SHIFT 0x5 +#define VGT_DEBUG_REG1__SPARE3_MASK 0x40 +#define VGT_DEBUG_REG1__SPARE3__SHIFT 0x6 +#define VGT_DEBUG_REG1__SPARE2_MASK 0x80 +#define VGT_DEBUG_REG1__SPARE2__SHIFT 0x7 +#define VGT_DEBUG_REG1__SPARE1_MASK 0x100 +#define VGT_DEBUG_REG1__SPARE1__SHIFT 0x8 +#define VGT_DEBUG_REG1__SPARE0_MASK 0x200 +#define VGT_DEBUG_REG1__SPARE0__SHIFT 0x9 +#define VGT_DEBUG_REG1__pi_vr_valid_MASK 0x400 +#define VGT_DEBUG_REG1__pi_vr_valid__SHIFT 0xa +#define VGT_DEBUG_REG1__vr_pi_read_MASK 0x800 +#define VGT_DEBUG_REG1__vr_pi_read__SHIFT 0xb +#define VGT_DEBUG_REG1__pi_pt_valid_MASK 0x1000 +#define VGT_DEBUG_REG1__pi_pt_valid__SHIFT 0xc +#define VGT_DEBUG_REG1__pt_pi_read_MASK 0x2000 +#define VGT_DEBUG_REG1__pt_pi_read__SHIFT 0xd +#define VGT_DEBUG_REG1__pi_te_valid_MASK 0x4000 +#define VGT_DEBUG_REG1__pi_te_valid__SHIFT 0xe +#define VGT_DEBUG_REG1__te_grp_read_MASK 0x8000 +#define VGT_DEBUG_REG1__te_grp_read__SHIFT 0xf +#define VGT_DEBUG_REG1__vr_out_indx_valid_MASK 0x10000 +#define VGT_DEBUG_REG1__vr_out_indx_valid__SHIFT 0x10 +#define VGT_DEBUG_REG1__SPARE12_MASK 0x20000 +#define VGT_DEBUG_REG1__SPARE12__SHIFT 0x11 +#define VGT_DEBUG_REG1__vr_out_prim_valid_MASK 0x40000 +#define VGT_DEBUG_REG1__vr_out_prim_valid__SHIFT 0x12 +#define VGT_DEBUG_REG1__SPARE11_MASK 0x80000 +#define VGT_DEBUG_REG1__SPARE11__SHIFT 0x13 +#define VGT_DEBUG_REG1__pt_out_indx_valid_MASK 0x100000 +#define VGT_DEBUG_REG1__pt_out_indx_valid__SHIFT 0x14 +#define VGT_DEBUG_REG1__SPARE10_MASK 0x200000 +#define VGT_DEBUG_REG1__SPARE10__SHIFT 0x15 +#define VGT_DEBUG_REG1__pt_out_prim_valid_MASK 0x400000 +#define VGT_DEBUG_REG1__pt_out_prim_valid__SHIFT 0x16 +#define VGT_DEBUG_REG1__SPARE23_MASK 0x800000 +#define VGT_DEBUG_REG1__SPARE23__SHIFT 0x17 +#define VGT_DEBUG_REG1__te_out_data_valid_MASK 0x1000000 +#define VGT_DEBUG_REG1__te_out_data_valid__SHIFT 0x18 +#define VGT_DEBUG_REG1__SPARE25_MASK 0x2000000 +#define VGT_DEBUG_REG1__SPARE25__SHIFT 0x19 +#define VGT_DEBUG_REG1__pi_gs_valid_MASK 0x4000000 +#define VGT_DEBUG_REG1__pi_gs_valid__SHIFT 0x1a +#define VGT_DEBUG_REG1__gs_pi_read_MASK 0x8000000 +#define VGT_DEBUG_REG1__gs_pi_read__SHIFT 0x1b +#define VGT_DEBUG_REG1__gog_out_indx_valid_MASK 0x10000000 +#define VGT_DEBUG_REG1__gog_out_indx_valid__SHIFT 0x1c +#define VGT_DEBUG_REG1__out_indx_read_MASK 0x20000000 +#define VGT_DEBUG_REG1__out_indx_read__SHIFT 0x1d +#define VGT_DEBUG_REG1__gog_out_prim_valid_MASK 0x40000000 +#define VGT_DEBUG_REG1__gog_out_prim_valid__SHIFT 0x1e +#define VGT_DEBUG_REG1__out_prim_read_MASK 0x80000000 +#define VGT_DEBUG_REG1__out_prim_read__SHIFT 0x1f +#define VGT_DEBUG_REG2__hs_grp_busy_MASK 0x1 +#define VGT_DEBUG_REG2__hs_grp_busy__SHIFT 0x0 +#define VGT_DEBUG_REG2__hs_noif_busy_MASK 0x2 +#define VGT_DEBUG_REG2__hs_noif_busy__SHIFT 0x1 +#define VGT_DEBUG_REG2__tfmmIsBusy_MASK 0x4 +#define VGT_DEBUG_REG2__tfmmIsBusy__SHIFT 0x2 +#define VGT_DEBUG_REG2__lsVertIfBusy_0_MASK 0x8 +#define VGT_DEBUG_REG2__lsVertIfBusy_0__SHIFT 0x3 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr_MASK 0x10 +#define VGT_DEBUG_REG2__te11_hs_tess_input_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG2__lsWaveIfBusy_0_MASK 0x20 +#define VGT_DEBUG_REG2__lsWaveIfBusy_0__SHIFT 0x5 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts_MASK 0x40 +#define VGT_DEBUG_REG2__hs_te11_tess_input_rts__SHIFT 0x6 +#define VGT_DEBUG_REG2__grpModBusy_MASK 0x80 +#define VGT_DEBUG_REG2__grpModBusy__SHIFT 0x7 +#define VGT_DEBUG_REG2__lsVertFifoEmpty_MASK 0x100 +#define VGT_DEBUG_REG2__lsVertFifoEmpty__SHIFT 0x8 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty_MASK 0x200 +#define VGT_DEBUG_REG2__lsWaveFifoEmpty__SHIFT 0x9 +#define VGT_DEBUG_REG2__hsVertFifoEmpty_MASK 0x400 +#define VGT_DEBUG_REG2__hsVertFifoEmpty__SHIFT 0xa +#define VGT_DEBUG_REG2__hsWaveFifoEmpty_MASK 0x800 +#define VGT_DEBUG_REG2__hsWaveFifoEmpty__SHIFT 0xb +#define VGT_DEBUG_REG2__hsInputFifoEmpty_MASK 0x1000 +#define VGT_DEBUG_REG2__hsInputFifoEmpty__SHIFT 0xc +#define VGT_DEBUG_REG2__hsTifFifoEmpty_MASK 0x2000 +#define VGT_DEBUG_REG2__hsTifFifoEmpty__SHIFT 0xd +#define VGT_DEBUG_REG2__lsVertFifoFull_MASK 0x4000 +#define VGT_DEBUG_REG2__lsVertFifoFull__SHIFT 0xe +#define VGT_DEBUG_REG2__lsWaveFifoFull_MASK 0x8000 +#define VGT_DEBUG_REG2__lsWaveFifoFull__SHIFT 0xf +#define VGT_DEBUG_REG2__hsVertFifoFull_MASK 0x10000 +#define VGT_DEBUG_REG2__hsVertFifoFull__SHIFT 0x10 +#define VGT_DEBUG_REG2__hsWaveFifoFull_MASK 0x20000 +#define VGT_DEBUG_REG2__hsWaveFifoFull__SHIFT 0x11 +#define VGT_DEBUG_REG2__hsInputFifoFull_MASK 0x40000 +#define VGT_DEBUG_REG2__hsInputFifoFull__SHIFT 0x12 +#define VGT_DEBUG_REG2__hsTifFifoFull_MASK 0x80000 +#define VGT_DEBUG_REG2__hsTifFifoFull__SHIFT 0x13 +#define VGT_DEBUG_REG2__p0_rtr_MASK 0x100000 +#define VGT_DEBUG_REG2__p0_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG2__p1_rtr_MASK 0x200000 +#define VGT_DEBUG_REG2__p1_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG2__p0_dr_MASK 0x400000 +#define VGT_DEBUG_REG2__p0_dr__SHIFT 0x16 +#define VGT_DEBUG_REG2__p1_dr_MASK 0x800000 +#define VGT_DEBUG_REG2__p1_dr__SHIFT 0x17 +#define VGT_DEBUG_REG2__p0_rts_MASK 0x1000000 +#define VGT_DEBUG_REG2__p0_rts__SHIFT 0x18 +#define VGT_DEBUG_REG2__p1_rts_MASK 0x2000000 +#define VGT_DEBUG_REG2__p1_rts__SHIFT 0x19 +#define VGT_DEBUG_REG2__ls_sh_id_MASK 0x4000000 +#define VGT_DEBUG_REG2__ls_sh_id__SHIFT 0x1a +#define VGT_DEBUG_REG2__lsFwaveFlag_MASK 0x8000000 +#define VGT_DEBUG_REG2__lsFwaveFlag__SHIFT 0x1b +#define VGT_DEBUG_REG2__lsWaveSendFlush_MASK 0x10000000 +#define VGT_DEBUG_REG2__lsWaveSendFlush__SHIFT 0x1c +#define VGT_DEBUG_REG2__SPARE_MASK 0xe0000000 +#define VGT_DEBUG_REG2__SPARE__SHIFT 0x1d +#define VGT_DEBUG_REG3__lsTgRelInd_MASK 0xfff +#define VGT_DEBUG_REG3__lsTgRelInd__SHIFT 0x0 +#define VGT_DEBUG_REG3__lsWaveRelInd_MASK 0x3f000 +#define VGT_DEBUG_REG3__lsWaveRelInd__SHIFT 0xc +#define VGT_DEBUG_REG3__lsPatchCnt_MASK 0x3fc0000 +#define VGT_DEBUG_REG3__lsPatchCnt__SHIFT 0x12 +#define VGT_DEBUG_REG3__hsWaveRelInd_MASK 0xfc000000 +#define VGT_DEBUG_REG3__hsWaveRelInd__SHIFT 0x1a +#define VGT_DEBUG_REG4__hsPatchCnt_MASK 0xff +#define VGT_DEBUG_REG4__hsPatchCnt__SHIFT 0x0 +#define VGT_DEBUG_REG4__hsPrimId_15_0_MASK 0xffff00 +#define VGT_DEBUG_REG4__hsPrimId_15_0__SHIFT 0x8 +#define VGT_DEBUG_REG4__hsCpCnt_MASK 0x1f000000 +#define VGT_DEBUG_REG4__hsCpCnt__SHIFT 0x18 +#define VGT_DEBUG_REG4__hsWaveSendFlush_MASK 0x20000000 +#define VGT_DEBUG_REG4__hsWaveSendFlush__SHIFT 0x1d +#define VGT_DEBUG_REG4__hsFwaveFlag_MASK 0x40000000 +#define VGT_DEBUG_REG4__hsFwaveFlag__SHIFT 0x1e +#define VGT_DEBUG_REG4__SPARE_MASK 0x80000000 +#define VGT_DEBUG_REG4__SPARE__SHIFT 0x1f +#define VGT_DEBUG_REG5__SPARE4_MASK 0x7 +#define VGT_DEBUG_REG5__SPARE4__SHIFT 0x0 +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0_MASK 0xf8 +#define VGT_DEBUG_REG5__hsWaveCreditCnt_0__SHIFT 0x3 +#define VGT_DEBUG_REG5__SPARE3_MASK 0x700 +#define VGT_DEBUG_REG5__SPARE3__SHIFT 0x8 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0_MASK 0xf800 +#define VGT_DEBUG_REG5__hsVertCreditCnt_0__SHIFT 0xb +#define VGT_DEBUG_REG5__SPARE2_MASK 0x70000 +#define VGT_DEBUG_REG5__SPARE2__SHIFT 0x10 +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0_MASK 0xf80000 +#define VGT_DEBUG_REG5__lsWaveCreditCnt_0__SHIFT 0x13 +#define VGT_DEBUG_REG5__SPARE1_MASK 0x7000000 +#define VGT_DEBUG_REG5__SPARE1__SHIFT 0x18 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0_MASK 0xf8000000 +#define VGT_DEBUG_REG5__lsVertCreditCnt_0__SHIFT 0x1b +#define VGT_DEBUG_REG6__debug_BASE_MASK 0xffff +#define VGT_DEBUG_REG6__debug_BASE__SHIFT 0x0 +#define VGT_DEBUG_REG6__debug_SIZE_MASK 0xffff0000 +#define VGT_DEBUG_REG6__debug_SIZE__SHIFT 0x10 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty_MASK 0x1 +#define VGT_DEBUG_REG7__debug_tfmmFifoEmpty__SHIFT 0x0 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull_MASK 0x2 +#define VGT_DEBUG_REG7__debug_tfmmFifoFull__SHIFT 0x1 +#define VGT_DEBUG_REG7__hs_pipe0_dr_MASK 0x4 +#define VGT_DEBUG_REG7__hs_pipe0_dr__SHIFT 0x2 +#define VGT_DEBUG_REG7__hs_pipe0_rtr_MASK 0x8 +#define VGT_DEBUG_REG7__hs_pipe0_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG7__hs_pipe1_rtr_MASK 0x10 +#define VGT_DEBUG_REG7__hs_pipe1_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG7__SPARE_MASK 0xffe0 +#define VGT_DEBUG_REG7__SPARE__SHIFT 0x5 +#define VGT_DEBUG_REG7__TF_addr_MASK 0xffff0000 +#define VGT_DEBUG_REG7__TF_addr__SHIFT 0x10 +#define VGT_DEBUG_REG8__rcm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG8__rcm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG8__rcm_noif_busy_q_MASK 0x2 +#define VGT_DEBUG_REG8__rcm_noif_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG8__r1_inst_rtr_MASK 0x4 +#define VGT_DEBUG_REG8__r1_inst_rtr__SHIFT 0x2 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q_MASK 0x8 +#define VGT_DEBUG_REG8__spi_gsprim_fifo_busy_q__SHIFT 0x3 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q_MASK 0x10 +#define VGT_DEBUG_REG8__spi_esvert_fifo_busy_q__SHIFT 0x4 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q_MASK 0x20 +#define VGT_DEBUG_REG8__gs_tbl_valid_r3_q__SHIFT 0x5 +#define VGT_DEBUG_REG8__valid_r0_q_MASK 0x40 +#define VGT_DEBUG_REG8__valid_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG8__valid_r1_q_MASK 0x80 +#define VGT_DEBUG_REG8__valid_r1_q__SHIFT 0x7 +#define VGT_DEBUG_REG8__valid_r2_MASK 0x100 +#define VGT_DEBUG_REG8__valid_r2__SHIFT 0x8 +#define VGT_DEBUG_REG8__valid_r2_q_MASK 0x200 +#define VGT_DEBUG_REG8__valid_r2_q__SHIFT 0x9 +#define VGT_DEBUG_REG8__r0_rtr_MASK 0x400 +#define VGT_DEBUG_REG8__r0_rtr__SHIFT 0xa +#define VGT_DEBUG_REG8__r1_rtr_MASK 0x800 +#define VGT_DEBUG_REG8__r1_rtr__SHIFT 0xb +#define VGT_DEBUG_REG8__r2_indx_rtr_MASK 0x1000 +#define VGT_DEBUG_REG8__r2_indx_rtr__SHIFT 0xc +#define VGT_DEBUG_REG8__r2_rtr_MASK 0x2000 +#define VGT_DEBUG_REG8__r2_rtr__SHIFT 0xd +#define VGT_DEBUG_REG8__es_gs_rtr_MASK 0x4000 +#define VGT_DEBUG_REG8__es_gs_rtr__SHIFT 0xe +#define VGT_DEBUG_REG8__gs_event_fifo_rtr_MASK 0x8000 +#define VGT_DEBUG_REG8__gs_event_fifo_rtr__SHIFT 0xf +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr_MASK 0x10000 +#define VGT_DEBUG_REG8__tm_rcm_gs_event_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr_MASK 0x20000 +#define VGT_DEBUG_REG8__gs_tbl_r3_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty_MASK 0x40000 +#define VGT_DEBUG_REG8__prim_skid_fifo_empty__SHIFT 0x12 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q_MASK 0x80000 +#define VGT_DEBUG_REG8__VGT_SPI_gsprim_rtr_q__SHIFT 0x13 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr_MASK 0x100000 +#define VGT_DEBUG_REG8__tm_rcm_gs_tbl_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr_MASK 0x200000 +#define VGT_DEBUG_REG8__tm_rcm_es_tbl_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q_MASK 0x400000 +#define VGT_DEBUG_REG8__VGT_SPI_esvert_rtr_q__SHIFT 0x16 +#define VGT_DEBUG_REG8__r2_no_bp_rtr_MASK 0x800000 +#define VGT_DEBUG_REG8__r2_no_bp_rtr__SHIFT 0x17 +#define VGT_DEBUG_REG8__hold_for_es_flush_MASK 0x1000000 +#define VGT_DEBUG_REG8__hold_for_es_flush__SHIFT 0x18 +#define VGT_DEBUG_REG8__gs_event_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG8__gs_event_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG8__gsprim_buff_empty_q_MASK 0x4000000 +#define VGT_DEBUG_REG8__gsprim_buff_empty_q__SHIFT 0x1a +#define VGT_DEBUG_REG8__gsprim_buff_full_q_MASK 0x8000000 +#define VGT_DEBUG_REG8__gsprim_buff_full_q__SHIFT 0x1b +#define VGT_DEBUG_REG8__te_prim_fifo_empty_MASK 0x10000000 +#define VGT_DEBUG_REG8__te_prim_fifo_empty__SHIFT 0x1c +#define VGT_DEBUG_REG8__te_prim_fifo_full_MASK 0x20000000 +#define VGT_DEBUG_REG8__te_prim_fifo_full__SHIFT 0x1d +#define VGT_DEBUG_REG8__te_vert_fifo_empty_MASK 0x40000000 +#define VGT_DEBUG_REG8__te_vert_fifo_empty__SHIFT 0x1e +#define VGT_DEBUG_REG8__te_vert_fifo_full_MASK 0x80000000 +#define VGT_DEBUG_REG8__te_vert_fifo_full__SHIFT 0x1f +#define VGT_DEBUG_REG9__indices_to_send_r2_q_MASK 0x3 +#define VGT_DEBUG_REG9__indices_to_send_r2_q__SHIFT 0x0 +#define VGT_DEBUG_REG9__valid_indices_r3_MASK 0x4 +#define VGT_DEBUG_REG9__valid_indices_r3__SHIFT 0x2 +#define VGT_DEBUG_REG9__gs_eov_r3_MASK 0x8 +#define VGT_DEBUG_REG9__gs_eov_r3__SHIFT 0x3 +#define VGT_DEBUG_REG9__eop_indx_r3_MASK 0x10 +#define VGT_DEBUG_REG9__eop_indx_r3__SHIFT 0x4 +#define VGT_DEBUG_REG9__eop_prim_r3_MASK 0x20 +#define VGT_DEBUG_REG9__eop_prim_r3__SHIFT 0x5 +#define VGT_DEBUG_REG9__es_eov_r3_MASK 0x40 +#define VGT_DEBUG_REG9__es_eov_r3__SHIFT 0x6 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0_MASK 0x80 +#define VGT_DEBUG_REG9__es_tbl_state_r3_q_0__SHIFT 0x7 +#define VGT_DEBUG_REG9__pending_es_send_r3_q_MASK 0x100 +#define VGT_DEBUG_REG9__pending_es_send_r3_q__SHIFT 0x8 +#define VGT_DEBUG_REG9__pending_es_flush_r3_MASK 0x200 +#define VGT_DEBUG_REG9__pending_es_flush_r3__SHIFT 0x9 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0_MASK 0x400 +#define VGT_DEBUG_REG9__gs_tbl_num_es_per_gs_r3_q_not_0__SHIFT 0xa +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q_MASK 0x3f800 +#define VGT_DEBUG_REG9__gs_tbl_prim_cnt_r3_q__SHIFT 0xb +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q_MASK 0x40000 +#define VGT_DEBUG_REG9__gs_tbl_eop_r3_q__SHIFT 0x12 +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q_MASK 0x380000 +#define VGT_DEBUG_REG9__gs_tbl_state_r3_q__SHIFT 0x13 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q_MASK 0x400000 +#define VGT_DEBUG_REG9__gs_pending_state_r3_q__SHIFT 0x16 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q_MASK 0x800000 +#define VGT_DEBUG_REG9__invalidate_rb_roll_over_q__SHIFT 0x17 +#define VGT_DEBUG_REG9__gs_instancing_state_q_MASK 0x1000000 +#define VGT_DEBUG_REG9__gs_instancing_state_q__SHIFT 0x18 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0_MASK 0x2000000 +#define VGT_DEBUG_REG9__es_per_gs_vert_cnt_r3_q_not_0__SHIFT 0x19 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0_MASK 0x4000000 +#define VGT_DEBUG_REG9__gs_prim_per_es_ctr_r3_q_not_0__SHIFT 0x1a +#define VGT_DEBUG_REG9__pre_r0_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG9__pre_r0_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG9__valid_r3_q_MASK 0x10000000 +#define VGT_DEBUG_REG9__valid_r3_q__SHIFT 0x1c +#define VGT_DEBUG_REG9__valid_pre_r0_q_MASK 0x20000000 +#define VGT_DEBUG_REG9__valid_pre_r0_q__SHIFT 0x1d +#define VGT_DEBUG_REG9__SPARE0_MASK 0x40000000 +#define VGT_DEBUG_REG9__SPARE0__SHIFT 0x1e +#define VGT_DEBUG_REG9__off_chip_hs_r2_q_MASK 0x80000000 +#define VGT_DEBUG_REG9__off_chip_hs_r2_q__SHIFT 0x1f +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q_MASK 0x1f +#define VGT_DEBUG_REG10__index_buffer_depth_r1_q__SHIFT 0x0 +#define VGT_DEBUG_REG10__eopg_r2_q_MASK 0x20 +#define VGT_DEBUG_REG10__eopg_r2_q__SHIFT 0x5 +#define VGT_DEBUG_REG10__eotg_r2_q_MASK 0x40 +#define VGT_DEBUG_REG10__eotg_r2_q__SHIFT 0x6 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q_MASK 0x180 +#define VGT_DEBUG_REG10__onchip_gs_en_r0_q__SHIFT 0x7 +#define VGT_DEBUG_REG10__SPARE2_MASK 0x600 +#define VGT_DEBUG_REG10__SPARE2__SHIFT 0x9 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq_MASK 0x800 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_qq__SHIFT 0xb +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q_MASK 0x1000 +#define VGT_DEBUG_REG10__rcm_mem_gsprim_re_q__SHIFT 0xc +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0_MASK 0x7fe000 +#define VGT_DEBUG_REG10__gs_rb_space_avail_r3_q_9_0__SHIFT 0xd +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0_MASK 0xff800000 +#define VGT_DEBUG_REG10__es_rb_space_avail_r2_q_8_0__SHIFT 0x17 +#define VGT_DEBUG_REG11__tm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG11__tm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG11__tm_noif_busy_q_MASK 0x2 +#define VGT_DEBUG_REG11__tm_noif_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG11__tm_out_busy_q_MASK 0x4 +#define VGT_DEBUG_REG11__tm_out_busy_q__SHIFT 0x2 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy_MASK 0x8 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_busy__SHIFT 0x3 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy_MASK 0x10 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_busy__SHIFT 0x4 +#define VGT_DEBUG_REG11__SPARE1_MASK 0x20 +#define VGT_DEBUG_REG11__SPARE1__SHIFT 0x5 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy_MASK 0x40 +#define VGT_DEBUG_REG11__spi_gsthread_fifo_busy__SHIFT 0x6 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy_MASK 0x80 +#define VGT_DEBUG_REG11__spi_esthread_fifo_busy__SHIFT 0x7 +#define VGT_DEBUG_REG11__hold_eswave_MASK 0x100 +#define VGT_DEBUG_REG11__hold_eswave__SHIFT 0x8 +#define VGT_DEBUG_REG11__es_rb_roll_over_r3_MASK 0x200 +#define VGT_DEBUG_REG11__es_rb_roll_over_r3__SHIFT 0x9 +#define VGT_DEBUG_REG11__counters_busy_r0_MASK 0x400 +#define VGT_DEBUG_REG11__counters_busy_r0__SHIFT 0xa +#define VGT_DEBUG_REG11__counters_avail_r0_MASK 0x800 +#define VGT_DEBUG_REG11__counters_avail_r0__SHIFT 0xb +#define VGT_DEBUG_REG11__counters_available_r0_MASK 0x1000 +#define VGT_DEBUG_REG11__counters_available_r0__SHIFT 0xc +#define VGT_DEBUG_REG11__vs_event_fifo_rtr_MASK 0x2000 +#define VGT_DEBUG_REG11__vs_event_fifo_rtr__SHIFT 0xd +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q_MASK 0x4000 +#define VGT_DEBUG_REG11__VGT_SPI_gsthread_rtr_q__SHIFT 0xe +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q_MASK 0x8000 +#define VGT_DEBUG_REG11__VGT_SPI_esthread_rtr_q__SHIFT 0xf +#define VGT_DEBUG_REG11__gs_issue_rtr_MASK 0x10000 +#define VGT_DEBUG_REG11__gs_issue_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG11__tm_pt_event_rtr_MASK 0x20000 +#define VGT_DEBUG_REG11__tm_pt_event_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG11__SPARE0_MASK 0x40000 +#define VGT_DEBUG_REG11__SPARE0__SHIFT 0x12 +#define VGT_DEBUG_REG11__gs_r0_rtr_MASK 0x80000 +#define VGT_DEBUG_REG11__gs_r0_rtr__SHIFT 0x13 +#define VGT_DEBUG_REG11__es_r0_rtr_MASK 0x100000 +#define VGT_DEBUG_REG11__es_r0_rtr__SHIFT 0x14 +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr_MASK 0x200000 +#define VGT_DEBUG_REG11__gog_tm_vs_event_rtr__SHIFT 0x15 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr_MASK 0x400000 +#define VGT_DEBUG_REG11__tm_rcm_gs_event_rtr__SHIFT 0x16 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr_MASK 0x800000 +#define VGT_DEBUG_REG11__tm_rcm_gs_tbl_rtr__SHIFT 0x17 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr_MASK 0x1000000 +#define VGT_DEBUG_REG11__tm_rcm_es_tbl_rtr__SHIFT 0x18 +#define VGT_DEBUG_REG11__vs_event_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG11__vs_event_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG11__vs_event_fifo_full_MASK 0x4000000 +#define VGT_DEBUG_REG11__vs_event_fifo_full__SHIFT 0x1a +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full_MASK 0x8000000 +#define VGT_DEBUG_REG11__es_rb_dealloc_fifo_full__SHIFT 0x1b +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full_MASK 0x10000000 +#define VGT_DEBUG_REG11__vs_dealloc_tbl_full__SHIFT 0x1c +#define VGT_DEBUG_REG11__send_event_q_MASK 0x20000000 +#define VGT_DEBUG_REG11__send_event_q__SHIFT 0x1d +#define VGT_DEBUG_REG11__es_tbl_empty_MASK 0x40000000 +#define VGT_DEBUG_REG11__es_tbl_empty__SHIFT 0x1e +#define VGT_DEBUG_REG11__no_active_states_r0_MASK 0x80000000 +#define VGT_DEBUG_REG11__no_active_states_r0__SHIFT 0x1f +#define VGT_DEBUG_REG12__gs_state0_r0_q_MASK 0x7 +#define VGT_DEBUG_REG12__gs_state0_r0_q__SHIFT 0x0 +#define VGT_DEBUG_REG12__gs_state1_r0_q_MASK 0x38 +#define VGT_DEBUG_REG12__gs_state1_r0_q__SHIFT 0x3 +#define VGT_DEBUG_REG12__gs_state2_r0_q_MASK 0x1c0 +#define VGT_DEBUG_REG12__gs_state2_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG12__gs_state3_r0_q_MASK 0xe00 +#define VGT_DEBUG_REG12__gs_state3_r0_q__SHIFT 0x9 +#define VGT_DEBUG_REG12__gs_state4_r0_q_MASK 0x7000 +#define VGT_DEBUG_REG12__gs_state4_r0_q__SHIFT 0xc +#define VGT_DEBUG_REG12__gs_state5_r0_q_MASK 0x38000 +#define VGT_DEBUG_REG12__gs_state5_r0_q__SHIFT 0xf +#define VGT_DEBUG_REG12__gs_state6_r0_q_MASK 0x1c0000 +#define VGT_DEBUG_REG12__gs_state6_r0_q__SHIFT 0x12 +#define VGT_DEBUG_REG12__gs_state7_r0_q_MASK 0xe00000 +#define VGT_DEBUG_REG12__gs_state7_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG12__gs_state8_r0_q_MASK 0x7000000 +#define VGT_DEBUG_REG12__gs_state8_r0_q__SHIFT 0x18 +#define VGT_DEBUG_REG12__gs_state9_r0_q_MASK 0x38000000 +#define VGT_DEBUG_REG12__gs_state9_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG12__hold_eswave_eop_MASK 0x40000000 +#define VGT_DEBUG_REG12__hold_eswave_eop__SHIFT 0x1e +#define VGT_DEBUG_REG12__SPARE0_MASK 0x80000000 +#define VGT_DEBUG_REG12__SPARE0__SHIFT 0x1f +#define VGT_DEBUG_REG13__gs_state10_r0_q_MASK 0x7 +#define VGT_DEBUG_REG13__gs_state10_r0_q__SHIFT 0x0 +#define VGT_DEBUG_REG13__gs_state11_r0_q_MASK 0x38 +#define VGT_DEBUG_REG13__gs_state11_r0_q__SHIFT 0x3 +#define VGT_DEBUG_REG13__gs_state12_r0_q_MASK 0x1c0 +#define VGT_DEBUG_REG13__gs_state12_r0_q__SHIFT 0x6 +#define VGT_DEBUG_REG13__gs_state13_r0_q_MASK 0xe00 +#define VGT_DEBUG_REG13__gs_state13_r0_q__SHIFT 0x9 +#define VGT_DEBUG_REG13__gs_state14_r0_q_MASK 0x7000 +#define VGT_DEBUG_REG13__gs_state14_r0_q__SHIFT 0xc +#define VGT_DEBUG_REG13__gs_state15_r0_q_MASK 0x38000 +#define VGT_DEBUG_REG13__gs_state15_r0_q__SHIFT 0xf +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0_MASK 0x3c0000 +#define VGT_DEBUG_REG13__gs_tbl_wrptr_r0_q_3_0__SHIFT 0x12 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0_MASK 0x400000 +#define VGT_DEBUG_REG13__gsfetch_done_fifo_cnt_q_not_0__SHIFT 0x16 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0_MASK 0x800000 +#define VGT_DEBUG_REG13__gsfetch_done_cnt_q_not_0__SHIFT 0x17 +#define VGT_DEBUG_REG13__es_tbl_full_MASK 0x1000000 +#define VGT_DEBUG_REG13__es_tbl_full__SHIFT 0x18 +#define VGT_DEBUG_REG13__SPARE1_MASK 0x2000000 +#define VGT_DEBUG_REG13__SPARE1__SHIFT 0x19 +#define VGT_DEBUG_REG13__SPARE0_MASK 0x4000000 +#define VGT_DEBUG_REG13__SPARE0__SHIFT 0x1a +#define VGT_DEBUG_REG13__active_cm_sm_r0_q_MASK 0xf8000000 +#define VGT_DEBUG_REG13__active_cm_sm_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG14__SPARE3_MASK 0xf +#define VGT_DEBUG_REG14__SPARE3__SHIFT 0x0 +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full_MASK 0x10 +#define VGT_DEBUG_REG14__gsfetch_done_fifo_full__SHIFT 0x4 +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0_MASK 0x20 +#define VGT_DEBUG_REG14__gs_rb_space_avail_r0__SHIFT 0x5 +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0_MASK 0x40 +#define VGT_DEBUG_REG14__smx_es_done_cnt_r0_q_not_0__SHIFT 0x6 +#define VGT_DEBUG_REG14__SPARE8_MASK 0x180 +#define VGT_DEBUG_REG14__SPARE8__SHIFT 0x7 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0_MASK 0x200 +#define VGT_DEBUG_REG14__vs_done_cnt_q_not_0__SHIFT 0x9 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q_MASK 0x400 +#define VGT_DEBUG_REG14__es_flush_cnt_busy_q__SHIFT 0xa +#define VGT_DEBUG_REG14__gs_tbl_full_r0_MASK 0x800 +#define VGT_DEBUG_REG14__gs_tbl_full_r0__SHIFT 0xb +#define VGT_DEBUG_REG14__SPARE2_MASK 0x1ff000 +#define VGT_DEBUG_REG14__SPARE2__SHIFT 0xc +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy_MASK 0x200000 +#define VGT_DEBUG_REG14__se1spi_gsthread_fifo_busy__SHIFT 0x15 +#define VGT_DEBUG_REG14__SPARE_MASK 0x1c00000 +#define VGT_DEBUG_REG14__SPARE__SHIFT 0x16 +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q_MASK 0x2000000 +#define VGT_DEBUG_REG14__VGT_SE1SPI_gsthread_rtr_q__SHIFT 0x19 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0_MASK 0x4000000 +#define VGT_DEBUG_REG14__smx1_es_done_cnt_r0_q_not_0__SHIFT 0x1a +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy_MASK 0x8000000 +#define VGT_DEBUG_REG14__se1spi_esthread_fifo_busy__SHIFT 0x1b +#define VGT_DEBUG_REG14__SPARE1_MASK 0x10000000 +#define VGT_DEBUG_REG14__SPARE1__SHIFT 0x1c +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0_MASK 0x20000000 +#define VGT_DEBUG_REG14__gsfetch_done_se1_cnt_q_not_0__SHIFT 0x1d +#define VGT_DEBUG_REG14__SPARE0_MASK 0x40000000 +#define VGT_DEBUG_REG14__SPARE0__SHIFT 0x1e +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q_MASK 0x80000000 +#define VGT_DEBUG_REG14__VGT_SE1SPI_esthread_rtr_q__SHIFT 0x1f +#define VGT_DEBUG_REG15__cm_busy_q_MASK 0x1 +#define VGT_DEBUG_REG15__cm_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG15__counters_busy_q_MASK 0x2 +#define VGT_DEBUG_REG15__counters_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG15__output_fifo_empty_MASK 0x4 +#define VGT_DEBUG_REG15__output_fifo_empty__SHIFT 0x2 +#define VGT_DEBUG_REG15__output_fifo_full_MASK 0x8 +#define VGT_DEBUG_REG15__output_fifo_full__SHIFT 0x3 +#define VGT_DEBUG_REG15__counters_full_MASK 0x10 +#define VGT_DEBUG_REG15__counters_full__SHIFT 0x4 +#define VGT_DEBUG_REG15__active_sm_q_MASK 0x3e0 +#define VGT_DEBUG_REG15__active_sm_q__SHIFT 0x5 +#define VGT_DEBUG_REG15__entry_rdptr_q_MASK 0x7c00 +#define VGT_DEBUG_REG15__entry_rdptr_q__SHIFT 0xa +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q_MASK 0xf8000 +#define VGT_DEBUG_REG15__cntr_tbl_wrptr_q__SHIFT 0xf +#define VGT_DEBUG_REG15__SPARE25_MASK 0x3f00000 +#define VGT_DEBUG_REG15__SPARE25__SHIFT 0x14 +#define VGT_DEBUG_REG15__st_cut_mode_q_MASK 0xc000000 +#define VGT_DEBUG_REG15__st_cut_mode_q__SHIFT 0x1a +#define VGT_DEBUG_REG15__gs_done_array_q_not_0_MASK 0x10000000 +#define VGT_DEBUG_REG15__gs_done_array_q_not_0__SHIFT 0x1c +#define VGT_DEBUG_REG15__SPARE31_MASK 0xe0000000 +#define VGT_DEBUG_REG15__SPARE31__SHIFT 0x1d +#define VGT_DEBUG_REG16__gog_busy_MASK 0x1 +#define VGT_DEBUG_REG16__gog_busy__SHIFT 0x0 +#define VGT_DEBUG_REG16__gog_state_q_MASK 0xe +#define VGT_DEBUG_REG16__gog_state_q__SHIFT 0x1 +#define VGT_DEBUG_REG16__r0_rtr_MASK 0x10 +#define VGT_DEBUG_REG16__r0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG16__r1_rtr_MASK 0x20 +#define VGT_DEBUG_REG16__r1_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG16__r1_upstream_rtr_MASK 0x40 +#define VGT_DEBUG_REG16__r1_upstream_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr_MASK 0x80 +#define VGT_DEBUG_REG16__r2_vs_tbl_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG16__r2_prim_rtr_MASK 0x100 +#define VGT_DEBUG_REG16__r2_prim_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG16__r2_indx_rtr_MASK 0x200 +#define VGT_DEBUG_REG16__r2_indx_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG16__r2_rtr_MASK 0x400 +#define VGT_DEBUG_REG16__r2_rtr__SHIFT 0xa +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr_MASK 0x800 +#define VGT_DEBUG_REG16__gog_tm_vs_event_rtr__SHIFT 0xb +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr_MASK 0x1000 +#define VGT_DEBUG_REG16__r3_force_vs_tbl_we_rtr__SHIFT 0xc +#define VGT_DEBUG_REG16__indx_valid_r2_q_MASK 0x2000 +#define VGT_DEBUG_REG16__indx_valid_r2_q__SHIFT 0xd +#define VGT_DEBUG_REG16__prim_valid_r2_q_MASK 0x4000 +#define VGT_DEBUG_REG16__prim_valid_r2_q__SHIFT 0xe +#define VGT_DEBUG_REG16__valid_r2_q_MASK 0x8000 +#define VGT_DEBUG_REG16__valid_r2_q__SHIFT 0xf +#define VGT_DEBUG_REG16__prim_valid_r1_q_MASK 0x10000 +#define VGT_DEBUG_REG16__prim_valid_r1_q__SHIFT 0x10 +#define VGT_DEBUG_REG16__indx_valid_r1_q_MASK 0x20000 +#define VGT_DEBUG_REG16__indx_valid_r1_q__SHIFT 0x11 +#define VGT_DEBUG_REG16__valid_r1_q_MASK 0x40000 +#define VGT_DEBUG_REG16__valid_r1_q__SHIFT 0x12 +#define VGT_DEBUG_REG16__indx_valid_r0_q_MASK 0x80000 +#define VGT_DEBUG_REG16__indx_valid_r0_q__SHIFT 0x13 +#define VGT_DEBUG_REG16__prim_valid_r0_q_MASK 0x100000 +#define VGT_DEBUG_REG16__prim_valid_r0_q__SHIFT 0x14 +#define VGT_DEBUG_REG16__valid_r0_q_MASK 0x200000 +#define VGT_DEBUG_REG16__valid_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG16__send_event_q_MASK 0x400000 +#define VGT_DEBUG_REG16__send_event_q__SHIFT 0x16 +#define VGT_DEBUG_REG16__SPARE24_MASK 0x800000 +#define VGT_DEBUG_REG16__SPARE24__SHIFT 0x17 +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q_MASK 0x1000000 +#define VGT_DEBUG_REG16__vert_seen_since_sopg_r2_q__SHIFT 0x18 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel_MASK 0xe000000 +#define VGT_DEBUG_REG16__gog_out_prim_state_sel__SHIFT 0x19 +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q_MASK 0x10000000 +#define VGT_DEBUG_REG16__multiple_streams_en_r1_q__SHIFT 0x1c +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0_MASK 0x20000000 +#define VGT_DEBUG_REG16__vs_vert_count_r2_q_not_0__SHIFT 0x1d +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0_MASK 0x40000000 +#define VGT_DEBUG_REG16__num_gs_r2_q_not_0__SHIFT 0x1e +#define VGT_DEBUG_REG16__new_vs_thread_r2_MASK 0x80000000 +#define VGT_DEBUG_REG16__new_vs_thread_r2__SHIFT 0x1f +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0_MASK 0x3f +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx2_5_0__SHIFT 0x0 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0_MASK 0xfc0 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx1_5_0__SHIFT 0x6 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0_MASK 0x3f000 +#define VGT_DEBUG_REG17__gog_out_prim_rel_indx0_5_0__SHIFT 0xc +#define VGT_DEBUG_REG17__gog_out_indx_13_0_MASK 0xfffc0000 +#define VGT_DEBUG_REG17__gog_out_indx_13_0__SHIFT 0x12 +#define VGT_DEBUG_REG18__grp_vr_valid_MASK 0x1 +#define VGT_DEBUG_REG18__grp_vr_valid__SHIFT 0x0 +#define VGT_DEBUG_REG18__pipe0_dr_MASK 0x2 +#define VGT_DEBUG_REG18__pipe0_dr__SHIFT 0x1 +#define VGT_DEBUG_REG18__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG18__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG18__vr_grp_read_MASK 0x8 +#define VGT_DEBUG_REG18__vr_grp_read__SHIFT 0x3 +#define VGT_DEBUG_REG18__pipe0_rtr_MASK 0x10 +#define VGT_DEBUG_REG18__pipe0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG18__pipe1_rtr_MASK 0x20 +#define VGT_DEBUG_REG18__pipe1_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG18__out_vr_indx_read_MASK 0x40 +#define VGT_DEBUG_REG18__out_vr_indx_read__SHIFT 0x6 +#define VGT_DEBUG_REG18__out_vr_prim_read_MASK 0x80 +#define VGT_DEBUG_REG18__out_vr_prim_read__SHIFT 0x7 +#define VGT_DEBUG_REG18__indices_to_send_q_MASK 0x700 +#define VGT_DEBUG_REG18__indices_to_send_q__SHIFT 0x8 +#define VGT_DEBUG_REG18__valid_indices_MASK 0x800 +#define VGT_DEBUG_REG18__valid_indices__SHIFT 0xb +#define VGT_DEBUG_REG18__last_indx_of_prim_MASK 0x1000 +#define VGT_DEBUG_REG18__last_indx_of_prim__SHIFT 0xc +#define VGT_DEBUG_REG18__indx0_new_d_MASK 0x2000 +#define VGT_DEBUG_REG18__indx0_new_d__SHIFT 0xd +#define VGT_DEBUG_REG18__indx1_new_d_MASK 0x4000 +#define VGT_DEBUG_REG18__indx1_new_d__SHIFT 0xe +#define VGT_DEBUG_REG18__indx2_new_d_MASK 0x8000 +#define VGT_DEBUG_REG18__indx2_new_d__SHIFT 0xf +#define VGT_DEBUG_REG18__indx2_hit_d_MASK 0x10000 +#define VGT_DEBUG_REG18__indx2_hit_d__SHIFT 0x10 +#define VGT_DEBUG_REG18__indx1_hit_d_MASK 0x20000 +#define VGT_DEBUG_REG18__indx1_hit_d__SHIFT 0x11 +#define VGT_DEBUG_REG18__indx0_hit_d_MASK 0x40000 +#define VGT_DEBUG_REG18__indx0_hit_d__SHIFT 0x12 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q_MASK 0x80000 +#define VGT_DEBUG_REG18__st_vertex_reuse_off_r0_q__SHIFT 0x13 +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q_MASK 0x100000 +#define VGT_DEBUG_REG18__last_group_of_instance_r0_q__SHIFT 0x14 +#define VGT_DEBUG_REG18__null_primitive_r0_q_MASK 0x200000 +#define VGT_DEBUG_REG18__null_primitive_r0_q__SHIFT 0x15 +#define VGT_DEBUG_REG18__eop_r0_q_MASK 0x400000 +#define VGT_DEBUG_REG18__eop_r0_q__SHIFT 0x16 +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d_MASK 0x800000 +#define VGT_DEBUG_REG18__eject_vtx_vect_r1_d__SHIFT 0x17 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q_MASK 0x7000000 +#define VGT_DEBUG_REG18__sub_prim_type_r0_q__SHIFT 0x18 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q_MASK 0x8000000 +#define VGT_DEBUG_REG18__gs_scenario_a_r0_q__SHIFT 0x1b +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q_MASK 0x10000000 +#define VGT_DEBUG_REG18__gs_scenario_b_r0_q__SHIFT 0x1c +#define VGT_DEBUG_REG18__components_valid_r0_q_MASK 0xe0000000 +#define VGT_DEBUG_REG18__components_valid_r0_q__SHIFT 0x1d +#define VGT_DEBUG_REG19__separate_out_busy_q_MASK 0x1 +#define VGT_DEBUG_REG19__separate_out_busy_q__SHIFT 0x0 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q_MASK 0x2 +#define VGT_DEBUG_REG19__separate_out_indx_busy_q__SHIFT 0x1 +#define VGT_DEBUG_REG19__prim_buffer_empty_MASK 0x4 +#define VGT_DEBUG_REG19__prim_buffer_empty__SHIFT 0x2 +#define VGT_DEBUG_REG19__prim_buffer_full_MASK 0x8 +#define VGT_DEBUG_REG19__prim_buffer_full__SHIFT 0x3 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q_MASK 0x10 +#define VGT_DEBUG_REG19__pa_clips_fifo_busy_q__SHIFT 0x4 +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q_MASK 0x20 +#define VGT_DEBUG_REG19__pa_clipp_fifo_busy_q__SHIFT 0x5 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q_MASK 0x40 +#define VGT_DEBUG_REG19__VGT_PA_clips_rtr_q__SHIFT 0x6 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q_MASK 0x80 +#define VGT_DEBUG_REG19__VGT_PA_clipp_rtr_q__SHIFT 0x7 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q_MASK 0x100 +#define VGT_DEBUG_REG19__spi_vsthread_fifo_busy_q__SHIFT 0x8 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q_MASK 0x200 +#define VGT_DEBUG_REG19__spi_vsvert_fifo_busy_q__SHIFT 0x9 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q_MASK 0x400 +#define VGT_DEBUG_REG19__pa_clipv_fifo_busy_q__SHIFT 0xa +#define VGT_DEBUG_REG19__hold_prim_MASK 0x800 +#define VGT_DEBUG_REG19__hold_prim__SHIFT 0xb +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q_MASK 0x1000 +#define VGT_DEBUG_REG19__VGT_SPI_vsthread_rtr_q__SHIFT 0xc +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q_MASK 0x2000 +#define VGT_DEBUG_REG19__VGT_SPI_vsvert_rtr_q__SHIFT 0xd +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q_MASK 0x4000 +#define VGT_DEBUG_REG19__VGT_PA_clipv_rtr_q__SHIFT 0xe +#define VGT_DEBUG_REG19__new_packet_q_MASK 0x8000 +#define VGT_DEBUG_REG19__new_packet_q__SHIFT 0xf +#define VGT_DEBUG_REG19__buffered_prim_event_MASK 0x10000 +#define VGT_DEBUG_REG19__buffered_prim_event__SHIFT 0x10 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive_MASK 0x20000 +#define VGT_DEBUG_REG19__buffered_prim_null_primitive__SHIFT 0x11 +#define VGT_DEBUG_REG19__buffered_prim_eop_MASK 0x40000 +#define VGT_DEBUG_REG19__buffered_prim_eop__SHIFT 0x12 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect_MASK 0x80000 +#define VGT_DEBUG_REG19__buffered_prim_eject_vtx_vect__SHIFT 0x13 +#define VGT_DEBUG_REG19__buffered_prim_type_event_MASK 0x3f00000 +#define VGT_DEBUG_REG19__buffered_prim_type_event__SHIFT 0x14 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q_MASK 0x4000000 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vswave_rtr_q__SHIFT 0x1a +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q_MASK 0x8000000 +#define VGT_DEBUG_REG19__VGT_SE1SPI_vsvert_rtr_q__SHIFT 0x1b +#define VGT_DEBUG_REG19__num_new_unique_rel_indx_MASK 0x30000000 +#define VGT_DEBUG_REG19__num_new_unique_rel_indx__SHIFT 0x1c +#define VGT_DEBUG_REG19__null_terminate_vtx_vector_MASK 0x40000000 +#define VGT_DEBUG_REG19__null_terminate_vtx_vector__SHIFT 0x1e +#define VGT_DEBUG_REG19__filter_event_MASK 0x80000000 +#define VGT_DEBUG_REG19__filter_event__SHIFT 0x1f +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex_MASK 0xffff +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexindex__SHIFT 0x0 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0_MASK 0x10000 +#define VGT_DEBUG_REG20__dbg_VGT_SPI_vsthread_sovertexcount_not_0__SHIFT 0x10 +#define VGT_DEBUG_REG20__SPARE17_MASK 0x20000 +#define VGT_DEBUG_REG20__SPARE17__SHIFT 0x11 +#define VGT_DEBUG_REG20__alloc_counter_q_MASK 0x3c0000 +#define VGT_DEBUG_REG20__alloc_counter_q__SHIFT 0x12 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q_MASK 0x1fc00000 +#define VGT_DEBUG_REG20__curr_dealloc_distance_q__SHIFT 0x16 +#define VGT_DEBUG_REG20__new_allocate_q_MASK 0x20000000 +#define VGT_DEBUG_REG20__new_allocate_q__SHIFT 0x1d +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0_MASK 0x40000000 +#define VGT_DEBUG_REG20__curr_slot_in_vtx_vect_q_not_0__SHIFT 0x1e +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0_MASK 0x80000000 +#define VGT_DEBUG_REG20__int_vtx_counter_q_not_0__SHIFT 0x1f +#define VGT_DEBUG_REG21__out_indx_fifo_empty_MASK 0x1 +#define VGT_DEBUG_REG21__out_indx_fifo_empty__SHIFT 0x0 +#define VGT_DEBUG_REG21__indx_side_fifo_empty_MASK 0x2 +#define VGT_DEBUG_REG21__indx_side_fifo_empty__SHIFT 0x1 +#define VGT_DEBUG_REG21__pipe0_dr_MASK 0x4 +#define VGT_DEBUG_REG21__pipe0_dr__SHIFT 0x2 +#define VGT_DEBUG_REG21__pipe1_dr_MASK 0x8 +#define VGT_DEBUG_REG21__pipe1_dr__SHIFT 0x3 +#define VGT_DEBUG_REG21__pipe2_dr_MASK 0x10 +#define VGT_DEBUG_REG21__pipe2_dr__SHIFT 0x4 +#define VGT_DEBUG_REG21__vsthread_buff_empty_MASK 0x20 +#define VGT_DEBUG_REG21__vsthread_buff_empty__SHIFT 0x5 +#define VGT_DEBUG_REG21__out_indx_fifo_full_MASK 0x40 +#define VGT_DEBUG_REG21__out_indx_fifo_full__SHIFT 0x6 +#define VGT_DEBUG_REG21__indx_side_fifo_full_MASK 0x80 +#define VGT_DEBUG_REG21__indx_side_fifo_full__SHIFT 0x7 +#define VGT_DEBUG_REG21__pipe0_rtr_MASK 0x100 +#define VGT_DEBUG_REG21__pipe0_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG21__pipe1_rtr_MASK 0x200 +#define VGT_DEBUG_REG21__pipe1_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG21__pipe2_rtr_MASK 0x400 +#define VGT_DEBUG_REG21__pipe2_rtr__SHIFT 0xa +#define VGT_DEBUG_REG21__vsthread_buff_full_MASK 0x800 +#define VGT_DEBUG_REG21__vsthread_buff_full__SHIFT 0xb +#define VGT_DEBUG_REG21__interfaces_rtr_MASK 0x1000 +#define VGT_DEBUG_REG21__interfaces_rtr__SHIFT 0xc +#define VGT_DEBUG_REG21__indx_count_q_not_0_MASK 0x2000 +#define VGT_DEBUG_REG21__indx_count_q_not_0__SHIFT 0xd +#define VGT_DEBUG_REG21__wait_for_external_eopg_q_MASK 0x4000 +#define VGT_DEBUG_REG21__wait_for_external_eopg_q__SHIFT 0xe +#define VGT_DEBUG_REG21__full_state_p1_q_MASK 0x8000 +#define VGT_DEBUG_REG21__full_state_p1_q__SHIFT 0xf +#define VGT_DEBUG_REG21__indx_side_indx_valid_MASK 0x10000 +#define VGT_DEBUG_REG21__indx_side_indx_valid__SHIFT 0x10 +#define VGT_DEBUG_REG21__stateid_p0_q_MASK 0xe0000 +#define VGT_DEBUG_REG21__stateid_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG21__is_event_p0_q_MASK 0x100000 +#define VGT_DEBUG_REG21__is_event_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG21__lshs_dealloc_p1_MASK 0x200000 +#define VGT_DEBUG_REG21__lshs_dealloc_p1__SHIFT 0x15 +#define VGT_DEBUG_REG21__stream_id_r2_q_MASK 0x400000 +#define VGT_DEBUG_REG21__stream_id_r2_q__SHIFT 0x16 +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0_MASK 0x800000 +#define VGT_DEBUG_REG21__vtx_vect_counter_q_not_0__SHIFT 0x17 +#define VGT_DEBUG_REG21__buff_full_p1_MASK 0x1000000 +#define VGT_DEBUG_REG21__buff_full_p1__SHIFT 0x18 +#define VGT_DEBUG_REG21__strmout_valid_p1_MASK 0x2000000 +#define VGT_DEBUG_REG21__strmout_valid_p1__SHIFT 0x19 +#define VGT_DEBUG_REG21__eotg_r2_q_MASK 0x4000000 +#define VGT_DEBUG_REG21__eotg_r2_q__SHIFT 0x1a +#define VGT_DEBUG_REG21__null_r2_q_MASK 0x8000000 +#define VGT_DEBUG_REG21__null_r2_q__SHIFT 0x1b +#define VGT_DEBUG_REG21__p0_dr_MASK 0x10000000 +#define VGT_DEBUG_REG21__p0_dr__SHIFT 0x1c +#define VGT_DEBUG_REG21__p0_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG21__p0_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG21__eopg_p0_q_MASK 0x40000000 +#define VGT_DEBUG_REG21__eopg_p0_q__SHIFT 0x1e +#define VGT_DEBUG_REG21__p0_nobp_MASK 0x80000000 +#define VGT_DEBUG_REG21__p0_nobp__SHIFT 0x1f +#define VGT_DEBUG_REG22__cm_state16_MASK 0x3 +#define VGT_DEBUG_REG22__cm_state16__SHIFT 0x0 +#define VGT_DEBUG_REG22__cm_state17_MASK 0xc +#define VGT_DEBUG_REG22__cm_state17__SHIFT 0x2 +#define VGT_DEBUG_REG22__cm_state18_MASK 0x30 +#define VGT_DEBUG_REG22__cm_state18__SHIFT 0x4 +#define VGT_DEBUG_REG22__cm_state19_MASK 0xc0 +#define VGT_DEBUG_REG22__cm_state19__SHIFT 0x6 +#define VGT_DEBUG_REG22__cm_state20_MASK 0x300 +#define VGT_DEBUG_REG22__cm_state20__SHIFT 0x8 +#define VGT_DEBUG_REG22__cm_state21_MASK 0xc00 +#define VGT_DEBUG_REG22__cm_state21__SHIFT 0xa +#define VGT_DEBUG_REG22__cm_state22_MASK 0x3000 +#define VGT_DEBUG_REG22__cm_state22__SHIFT 0xc +#define VGT_DEBUG_REG22__cm_state23_MASK 0xc000 +#define VGT_DEBUG_REG22__cm_state23__SHIFT 0xe +#define VGT_DEBUG_REG22__cm_state24_MASK 0x30000 +#define VGT_DEBUG_REG22__cm_state24__SHIFT 0x10 +#define VGT_DEBUG_REG22__cm_state25_MASK 0xc0000 +#define VGT_DEBUG_REG22__cm_state25__SHIFT 0x12 +#define VGT_DEBUG_REG22__cm_state26_MASK 0x300000 +#define VGT_DEBUG_REG22__cm_state26__SHIFT 0x14 +#define VGT_DEBUG_REG22__cm_state27_MASK 0xc00000 +#define VGT_DEBUG_REG22__cm_state27__SHIFT 0x16 +#define VGT_DEBUG_REG22__cm_state28_MASK 0x3000000 +#define VGT_DEBUG_REG22__cm_state28__SHIFT 0x18 +#define VGT_DEBUG_REG22__cm_state29_MASK 0xc000000 +#define VGT_DEBUG_REG22__cm_state29__SHIFT 0x1a +#define VGT_DEBUG_REG22__cm_state30_MASK 0x30000000 +#define VGT_DEBUG_REG22__cm_state30__SHIFT 0x1c +#define VGT_DEBUG_REG22__cm_state31_MASK 0xc0000000 +#define VGT_DEBUG_REG22__cm_state31__SHIFT 0x1e +#define VGT_DEBUG_REG23__frmt_busy_MASK 0x1 +#define VGT_DEBUG_REG23__frmt_busy__SHIFT 0x0 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr_MASK 0x2 +#define VGT_DEBUG_REG23__rcm_frmt_vert_rtr__SHIFT 0x1 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr_MASK 0x4 +#define VGT_DEBUG_REG23__rcm_frmt_prim_rtr__SHIFT 0x2 +#define VGT_DEBUG_REG23__prim_r3_rtr_MASK 0x8 +#define VGT_DEBUG_REG23__prim_r3_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG23__prim_r2_rtr_MASK 0x10 +#define VGT_DEBUG_REG23__prim_r2_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG23__vert_r3_rtr_MASK 0x20 +#define VGT_DEBUG_REG23__vert_r3_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG23__vert_r2_rtr_MASK 0x40 +#define VGT_DEBUG_REG23__vert_r2_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG23__vert_r1_rtr_MASK 0x80 +#define VGT_DEBUG_REG23__vert_r1_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG23__vert_r0_rtr_MASK 0x100 +#define VGT_DEBUG_REG23__vert_r0_rtr__SHIFT 0x8 +#define VGT_DEBUG_REG23__prim_fifo_empty_MASK 0x200 +#define VGT_DEBUG_REG23__prim_fifo_empty__SHIFT 0x9 +#define VGT_DEBUG_REG23__prim_fifo_full_MASK 0x400 +#define VGT_DEBUG_REG23__prim_fifo_full__SHIFT 0xa +#define VGT_DEBUG_REG23__vert_dr_r2_q_MASK 0x800 +#define VGT_DEBUG_REG23__vert_dr_r2_q__SHIFT 0xb +#define VGT_DEBUG_REG23__prim_dr_r2_q_MASK 0x1000 +#define VGT_DEBUG_REG23__prim_dr_r2_q__SHIFT 0xc +#define VGT_DEBUG_REG23__vert_dr_r1_q_MASK 0x2000 +#define VGT_DEBUG_REG23__vert_dr_r1_q__SHIFT 0xd +#define VGT_DEBUG_REG23__vert_dr_r0_q_MASK 0x4000 +#define VGT_DEBUG_REG23__vert_dr_r0_q__SHIFT 0xe +#define VGT_DEBUG_REG23__new_verts_r2_q_MASK 0x18000 +#define VGT_DEBUG_REG23__new_verts_r2_q__SHIFT 0xf +#define VGT_DEBUG_REG23__verts_sent_r2_q_MASK 0x1e0000 +#define VGT_DEBUG_REG23__verts_sent_r2_q__SHIFT 0x11 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q_MASK 0xe00000 +#define VGT_DEBUG_REG23__prim_state_sel_r2_q__SHIFT 0x15 +#define VGT_DEBUG_REG23__SPARE_MASK 0xff000000 +#define VGT_DEBUG_REG23__SPARE__SHIFT 0x18 +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0_MASK 0xffffff +#define VGT_DEBUG_REG24__avail_es_rb_space_r0_q_23_0__SHIFT 0x0 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q_MASK 0x3000000 +#define VGT_DEBUG_REG24__dependent_st_cut_mode_q__SHIFT 0x18 +#define VGT_DEBUG_REG24__SPARE31_MASK 0xfc000000 +#define VGT_DEBUG_REG24__SPARE31__SHIFT 0x1a +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0_MASK 0x3ffffff +#define VGT_DEBUG_REG25__avail_gs_rb_space_r0_q_25_0__SHIFT 0x0 +#define VGT_DEBUG_REG25__active_sm_r0_q_MASK 0x3c000000 +#define VGT_DEBUG_REG25__active_sm_r0_q__SHIFT 0x1a +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q_MASK 0x40000000 +#define VGT_DEBUG_REG25__add_gs_rb_space_r1_q__SHIFT 0x1e +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q_MASK 0x80000000 +#define VGT_DEBUG_REG25__add_gs_rb_space_r0_q__SHIFT 0x1f +#define VGT_DEBUG_REG26__cm_state0_MASK 0x3 +#define VGT_DEBUG_REG26__cm_state0__SHIFT 0x0 +#define VGT_DEBUG_REG26__cm_state1_MASK 0xc +#define VGT_DEBUG_REG26__cm_state1__SHIFT 0x2 +#define VGT_DEBUG_REG26__cm_state2_MASK 0x30 +#define VGT_DEBUG_REG26__cm_state2__SHIFT 0x4 +#define VGT_DEBUG_REG26__cm_state3_MASK 0xc0 +#define VGT_DEBUG_REG26__cm_state3__SHIFT 0x6 +#define VGT_DEBUG_REG26__cm_state4_MASK 0x300 +#define VGT_DEBUG_REG26__cm_state4__SHIFT 0x8 +#define VGT_DEBUG_REG26__cm_state5_MASK 0xc00 +#define VGT_DEBUG_REG26__cm_state5__SHIFT 0xa +#define VGT_DEBUG_REG26__cm_state6_MASK 0x3000 +#define VGT_DEBUG_REG26__cm_state6__SHIFT 0xc +#define VGT_DEBUG_REG26__cm_state7_MASK 0xc000 +#define VGT_DEBUG_REG26__cm_state7__SHIFT 0xe +#define VGT_DEBUG_REG26__cm_state8_MASK 0x30000 +#define VGT_DEBUG_REG26__cm_state8__SHIFT 0x10 +#define VGT_DEBUG_REG26__cm_state9_MASK 0xc0000 +#define VGT_DEBUG_REG26__cm_state9__SHIFT 0x12 +#define VGT_DEBUG_REG26__cm_state10_MASK 0x300000 +#define VGT_DEBUG_REG26__cm_state10__SHIFT 0x14 +#define VGT_DEBUG_REG26__cm_state11_MASK 0xc00000 +#define VGT_DEBUG_REG26__cm_state11__SHIFT 0x16 +#define VGT_DEBUG_REG26__cm_state12_MASK 0x3000000 +#define VGT_DEBUG_REG26__cm_state12__SHIFT 0x18 +#define VGT_DEBUG_REG26__cm_state13_MASK 0xc000000 +#define VGT_DEBUG_REG26__cm_state13__SHIFT 0x1a +#define VGT_DEBUG_REG26__cm_state14_MASK 0x30000000 +#define VGT_DEBUG_REG26__cm_state14__SHIFT 0x1c +#define VGT_DEBUG_REG26__cm_state15_MASK 0xc0000000 +#define VGT_DEBUG_REG26__cm_state15__SHIFT 0x1e +#define VGT_DEBUG_REG27__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG27__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG27__gsc0_dr_MASK 0x2 +#define VGT_DEBUG_REG27__gsc0_dr__SHIFT 0x1 +#define VGT_DEBUG_REG27__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG27__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG27__tm_pt_event_rtr_MASK 0x8 +#define VGT_DEBUG_REG27__tm_pt_event_rtr__SHIFT 0x3 +#define VGT_DEBUG_REG27__pipe0_rtr_MASK 0x10 +#define VGT_DEBUG_REG27__pipe0_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG27__gsc0_rtr_MASK 0x20 +#define VGT_DEBUG_REG27__gsc0_rtr__SHIFT 0x5 +#define VGT_DEBUG_REG27__pipe1_rtr_MASK 0x40 +#define VGT_DEBUG_REG27__pipe1_rtr__SHIFT 0x6 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q_MASK 0x80 +#define VGT_DEBUG_REG27__last_indx_of_prim_p1_q__SHIFT 0x7 +#define VGT_DEBUG_REG27__indices_to_send_p0_q_MASK 0x300 +#define VGT_DEBUG_REG27__indices_to_send_p0_q__SHIFT 0x8 +#define VGT_DEBUG_REG27__event_flag_p1_q_MASK 0x400 +#define VGT_DEBUG_REG27__event_flag_p1_q__SHIFT 0xa +#define VGT_DEBUG_REG27__eop_p1_q_MASK 0x800 +#define VGT_DEBUG_REG27__eop_p1_q__SHIFT 0xb +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q_MASK 0x3000 +#define VGT_DEBUG_REG27__gs_out_prim_type_p0_q__SHIFT 0xc +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG27__gsc_null_primitive_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG27__gsc_eop_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG27__gsc_eop_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG27__gsc_2cycle_output_MASK 0x10000 +#define VGT_DEBUG_REG27__gsc_2cycle_output__SHIFT 0x10 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG27__gsc_2nd_cycle_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG27__last_indx_of_vsprim_MASK 0x40000 +#define VGT_DEBUG_REG27__last_indx_of_vsprim__SHIFT 0x12 +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q_MASK 0x80000 +#define VGT_DEBUG_REG27__first_vsprim_of_gsprim_p0_q__SHIFT 0x13 +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q_MASK 0x7ff00000 +#define VGT_DEBUG_REG27__gsc_indx_count_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim_MASK 0x80000000 +#define VGT_DEBUG_REG27__last_vsprim_of_gsprim__SHIFT 0x1f +#define VGT_DEBUG_REG28__con_state_q_MASK 0xf +#define VGT_DEBUG_REG28__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG28__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG28__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG28__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG28__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG28__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG28__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG28__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG28__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG28__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG28__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG28__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG28__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG28__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG28__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG28__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG28__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG28__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG28__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG28__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG28__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG28__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG28__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG28__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG28__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG28__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG28__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG28__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG28__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG28__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG28__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG28__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG28__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG28__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG28__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG28__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG28__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG28__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG28__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG28__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG28__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG28__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG28__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG28__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2_MASK 0x80000000 +#define VGT_DEBUG_REG28__use_stored_inner_q_ring2__SHIFT 0x1f +#define VGT_DEBUG_REG29__con_state_q_MASK 0xf +#define VGT_DEBUG_REG29__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG29__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG29__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG29__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG29__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG29__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG29__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG29__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG29__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG29__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG29__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG29__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG29__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG29__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG29__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG29__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG29__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG29__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG29__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG29__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG29__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG29__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG29__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG29__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG29__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG29__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG29__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG29__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG29__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG29__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG29__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG29__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG29__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG29__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG29__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG29__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG29__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG29__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG29__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG29__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG29__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG29__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG29__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG29__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3_MASK 0x80000000 +#define VGT_DEBUG_REG29__use_stored_inner_q_ring3__SHIFT 0x1f +#define VGT_DEBUG_REG31__pipe0_dr_MASK 0x1 +#define VGT_DEBUG_REG31__pipe0_dr__SHIFT 0x0 +#define VGT_DEBUG_REG31__pipe0_rtr_MASK 0x2 +#define VGT_DEBUG_REG31__pipe0_rtr__SHIFT 0x1 +#define VGT_DEBUG_REG31__pipe1_outer_dr_MASK 0x4 +#define VGT_DEBUG_REG31__pipe1_outer_dr__SHIFT 0x2 +#define VGT_DEBUG_REG31__pipe1_inner_dr_MASK 0x8 +#define VGT_DEBUG_REG31__pipe1_inner_dr__SHIFT 0x3 +#define VGT_DEBUG_REG31__pipe2_outer_dr_MASK 0x10 +#define VGT_DEBUG_REG31__pipe2_outer_dr__SHIFT 0x4 +#define VGT_DEBUG_REG31__pipe2_inner_dr_MASK 0x20 +#define VGT_DEBUG_REG31__pipe2_inner_dr__SHIFT 0x5 +#define VGT_DEBUG_REG31__pipe3_outer_dr_MASK 0x40 +#define VGT_DEBUG_REG31__pipe3_outer_dr__SHIFT 0x6 +#define VGT_DEBUG_REG31__pipe3_inner_dr_MASK 0x80 +#define VGT_DEBUG_REG31__pipe3_inner_dr__SHIFT 0x7 +#define VGT_DEBUG_REG31__pipe4_outer_dr_MASK 0x100 +#define VGT_DEBUG_REG31__pipe4_outer_dr__SHIFT 0x8 +#define VGT_DEBUG_REG31__pipe4_inner_dr_MASK 0x200 +#define VGT_DEBUG_REG31__pipe4_inner_dr__SHIFT 0x9 +#define VGT_DEBUG_REG31__pipe5_outer_dr_MASK 0x400 +#define VGT_DEBUG_REG31__pipe5_outer_dr__SHIFT 0xa +#define VGT_DEBUG_REG31__pipe5_inner_dr_MASK 0x800 +#define VGT_DEBUG_REG31__pipe5_inner_dr__SHIFT 0xb +#define VGT_DEBUG_REG31__pipe2_outer_rtr_MASK 0x1000 +#define VGT_DEBUG_REG31__pipe2_outer_rtr__SHIFT 0xc +#define VGT_DEBUG_REG31__pipe2_inner_rtr_MASK 0x2000 +#define VGT_DEBUG_REG31__pipe2_inner_rtr__SHIFT 0xd +#define VGT_DEBUG_REG31__pipe3_outer_rtr_MASK 0x4000 +#define VGT_DEBUG_REG31__pipe3_outer_rtr__SHIFT 0xe +#define VGT_DEBUG_REG31__pipe3_inner_rtr_MASK 0x8000 +#define VGT_DEBUG_REG31__pipe3_inner_rtr__SHIFT 0xf +#define VGT_DEBUG_REG31__pipe4_outer_rtr_MASK 0x10000 +#define VGT_DEBUG_REG31__pipe4_outer_rtr__SHIFT 0x10 +#define VGT_DEBUG_REG31__pipe4_inner_rtr_MASK 0x20000 +#define VGT_DEBUG_REG31__pipe4_inner_rtr__SHIFT 0x11 +#define VGT_DEBUG_REG31__pipe5_outer_rtr_MASK 0x40000 +#define VGT_DEBUG_REG31__pipe5_outer_rtr__SHIFT 0x12 +#define VGT_DEBUG_REG31__pipe5_inner_rtr_MASK 0x80000 +#define VGT_DEBUG_REG31__pipe5_inner_rtr__SHIFT 0x13 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts_MASK 0x100000 +#define VGT_DEBUG_REG31__pg_con_outer_point1_rts__SHIFT 0x14 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts_MASK 0x200000 +#define VGT_DEBUG_REG31__pg_con_outer_point2_rts__SHIFT 0x15 +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts_MASK 0x400000 +#define VGT_DEBUG_REG31__pg_con_inner_point1_rts__SHIFT 0x16 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts_MASK 0x800000 +#define VGT_DEBUG_REG31__pg_con_inner_point2_rts__SHIFT 0x17 +#define VGT_DEBUG_REG31__pg_patch_fifo_empty_MASK 0x1000000 +#define VGT_DEBUG_REG31__pg_patch_fifo_empty__SHIFT 0x18 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty_MASK 0x2000000 +#define VGT_DEBUG_REG31__pg_edge_fifo_empty__SHIFT 0x19 +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty_MASK 0x4000000 +#define VGT_DEBUG_REG31__pg_inner3_perp_fifo_empty__SHIFT 0x1a +#define VGT_DEBUG_REG31__pg_patch_fifo_full_MASK 0x8000000 +#define VGT_DEBUG_REG31__pg_patch_fifo_full__SHIFT 0x1b +#define VGT_DEBUG_REG31__pg_edge_fifo_full_MASK 0x10000000 +#define VGT_DEBUG_REG31__pg_edge_fifo_full__SHIFT 0x1c +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full_MASK 0x20000000 +#define VGT_DEBUG_REG31__pg_inner_perp_fifo_full__SHIFT 0x1d +#define VGT_DEBUG_REG31__outer_ring_done_q_MASK 0x40000000 +#define VGT_DEBUG_REG31__outer_ring_done_q__SHIFT 0x1e +#define VGT_DEBUG_REG31__inner_ring_done_q_MASK 0x80000000 +#define VGT_DEBUG_REG31__inner_ring_done_q__SHIFT 0x1f +#define VGT_DEBUG_REG32__first_ring_of_patch_MASK 0x1 +#define VGT_DEBUG_REG32__first_ring_of_patch__SHIFT 0x0 +#define VGT_DEBUG_REG32__last_ring_of_patch_MASK 0x2 +#define VGT_DEBUG_REG32__last_ring_of_patch__SHIFT 0x1 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring_MASK 0x4 +#define VGT_DEBUG_REG32__last_edge_of_outer_ring__SHIFT 0x2 +#define VGT_DEBUG_REG32__last_point_of_outer_edge_MASK 0x8 +#define VGT_DEBUG_REG32__last_point_of_outer_edge__SHIFT 0x3 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring_MASK 0x10 +#define VGT_DEBUG_REG32__last_edge_of_inner_ring__SHIFT 0x4 +#define VGT_DEBUG_REG32__last_point_of_inner_edge_MASK 0x20 +#define VGT_DEBUG_REG32__last_point_of_inner_edge__SHIFT 0x5 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q_MASK 0x40 +#define VGT_DEBUG_REG32__last_patch_of_tg_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG32__event_null_special_p0_q_MASK 0x80 +#define VGT_DEBUG_REG32__event_null_special_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG32__event_flag_p5_q_MASK 0x100 +#define VGT_DEBUG_REG32__event_flag_p5_q__SHIFT 0x8 +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q_MASK 0x200 +#define VGT_DEBUG_REG32__first_point_of_patch_p5_q__SHIFT 0x9 +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q_MASK 0x400 +#define VGT_DEBUG_REG32__first_point_of_edge_p5_q__SHIFT 0xa +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q_MASK 0x800 +#define VGT_DEBUG_REG32__last_patch_of_tg_p5_q__SHIFT 0xb +#define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 +#define VGT_DEBUG_REG32__tess_topology_p5_q__SHIFT 0xc +#define VGT_DEBUG_REG32__pipe5_inner3_rtr_MASK 0x4000 +#define VGT_DEBUG_REG32__pipe5_inner3_rtr__SHIFT 0xe +#define VGT_DEBUG_REG32__pipe5_inner2_rtr_MASK 0x8000 +#define VGT_DEBUG_REG32__pipe5_inner2_rtr__SHIFT 0xf +#define VGT_DEBUG_REG32__pg_edge_fifo3_full_MASK 0x10000 +#define VGT_DEBUG_REG32__pg_edge_fifo3_full__SHIFT 0x10 +#define VGT_DEBUG_REG32__pg_edge_fifo2_full_MASK 0x20000 +#define VGT_DEBUG_REG32__pg_edge_fifo2_full__SHIFT 0x11 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full_MASK 0x40000 +#define VGT_DEBUG_REG32__pg_inner3_point_fifo_full__SHIFT 0x12 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full_MASK 0x80000 +#define VGT_DEBUG_REG32__pg_outer3_point_fifo_full__SHIFT 0x13 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full_MASK 0x100000 +#define VGT_DEBUG_REG32__pg_inner2_point_fifo_full__SHIFT 0x14 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full_MASK 0x200000 +#define VGT_DEBUG_REG32__pg_outer2_point_fifo_full__SHIFT 0x15 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full_MASK 0x400000 +#define VGT_DEBUG_REG32__pg_inner_point_fifo_full__SHIFT 0x16 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full_MASK 0x800000 +#define VGT_DEBUG_REG32__pg_outer_point_fifo_full__SHIFT 0x17 +#define VGT_DEBUG_REG32__inner2_fifos_rtr_MASK 0x1000000 +#define VGT_DEBUG_REG32__inner2_fifos_rtr__SHIFT 0x18 +#define VGT_DEBUG_REG32__inner_fifos_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG32__inner_fifos_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG32__outer_fifos_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG32__outer_fifos_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG32__fifos_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG32__fifos_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG32__SPARE_MASK 0xf0000000 +#define VGT_DEBUG_REG32__SPARE__SHIFT 0x1c +#define VGT_DEBUG_REG33__pipe0_patch_dr_MASK 0x1 +#define VGT_DEBUG_REG33__pipe0_patch_dr__SHIFT 0x0 +#define VGT_DEBUG_REG33__ring3_pipe1_dr_MASK 0x2 +#define VGT_DEBUG_REG33__ring3_pipe1_dr__SHIFT 0x1 +#define VGT_DEBUG_REG33__pipe1_dr_MASK 0x4 +#define VGT_DEBUG_REG33__pipe1_dr__SHIFT 0x2 +#define VGT_DEBUG_REG33__pipe2_dr_MASK 0x8 +#define VGT_DEBUG_REG33__pipe2_dr__SHIFT 0x3 +#define VGT_DEBUG_REG33__pipe0_patch_rtr_MASK 0x10 +#define VGT_DEBUG_REG33__pipe0_patch_rtr__SHIFT 0x4 +#define VGT_DEBUG_REG33__ring2_pipe1_dr_MASK 0x20 +#define VGT_DEBUG_REG33__ring2_pipe1_dr__SHIFT 0x5 +#define VGT_DEBUG_REG33__ring1_pipe1_dr_MASK 0x40 +#define VGT_DEBUG_REG33__ring1_pipe1_dr__SHIFT 0x6 +#define VGT_DEBUG_REG33__pipe2_rtr_MASK 0x80 +#define VGT_DEBUG_REG33__pipe2_rtr__SHIFT 0x7 +#define VGT_DEBUG_REG33__pipe3_dr_MASK 0x100 +#define VGT_DEBUG_REG33__pipe3_dr__SHIFT 0x8 +#define VGT_DEBUG_REG33__pipe3_rtr_MASK 0x200 +#define VGT_DEBUG_REG33__pipe3_rtr__SHIFT 0x9 +#define VGT_DEBUG_REG33__ring2_in_sync_q_MASK 0x400 +#define VGT_DEBUG_REG33__ring2_in_sync_q__SHIFT 0xa +#define VGT_DEBUG_REG33__ring1_in_sync_q_MASK 0x800 +#define VGT_DEBUG_REG33__ring1_in_sync_q__SHIFT 0xb +#define VGT_DEBUG_REG33__pipe1_patch_rtr_MASK 0x1000 +#define VGT_DEBUG_REG33__pipe1_patch_rtr__SHIFT 0xc +#define VGT_DEBUG_REG33__ring3_in_sync_q_MASK 0x2000 +#define VGT_DEBUG_REG33__ring3_in_sync_q__SHIFT 0xd +#define VGT_DEBUG_REG33__tm_te11_event_rtr_MASK 0x4000 +#define VGT_DEBUG_REG33__tm_te11_event_rtr__SHIFT 0xe +#define VGT_DEBUG_REG33__first_prim_of_patch_q_MASK 0x8000 +#define VGT_DEBUG_REG33__first_prim_of_patch_q__SHIFT 0xf +#define VGT_DEBUG_REG33__con_prim_fifo_full_MASK 0x10000 +#define VGT_DEBUG_REG33__con_prim_fifo_full__SHIFT 0x10 +#define VGT_DEBUG_REG33__con_vert_fifo_full_MASK 0x20000 +#define VGT_DEBUG_REG33__con_vert_fifo_full__SHIFT 0x11 +#define VGT_DEBUG_REG33__con_prim_fifo_empty_MASK 0x40000 +#define VGT_DEBUG_REG33__con_prim_fifo_empty__SHIFT 0x12 +#define VGT_DEBUG_REG33__con_vert_fifo_empty_MASK 0x80000 +#define VGT_DEBUG_REG33__con_vert_fifo_empty__SHIFT 0x13 +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q_MASK 0x100000 +#define VGT_DEBUG_REG33__last_patch_of_tg_p0_q__SHIFT 0x14 +#define VGT_DEBUG_REG33__ring3_valid_p2_MASK 0x200000 +#define VGT_DEBUG_REG33__ring3_valid_p2__SHIFT 0x15 +#define VGT_DEBUG_REG33__ring2_valid_p2_MASK 0x400000 +#define VGT_DEBUG_REG33__ring2_valid_p2__SHIFT 0x16 +#define VGT_DEBUG_REG33__ring1_valid_p2_MASK 0x800000 +#define VGT_DEBUG_REG33__ring1_valid_p2__SHIFT 0x17 +#define VGT_DEBUG_REG33__tess_type_p0_q_MASK 0x3000000 +#define VGT_DEBUG_REG33__tess_type_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG33__tess_topology_p0_q_MASK 0xc000000 +#define VGT_DEBUG_REG33__tess_topology_p0_q__SHIFT 0x1a +#define VGT_DEBUG_REG33__te11_out_vert_gs_en_MASK 0x10000000 +#define VGT_DEBUG_REG33__te11_out_vert_gs_en__SHIFT 0x1c +#define VGT_DEBUG_REG33__con_ring3_busy_MASK 0x20000000 +#define VGT_DEBUG_REG33__con_ring3_busy__SHIFT 0x1d +#define VGT_DEBUG_REG33__con_ring2_busy_MASK 0x40000000 +#define VGT_DEBUG_REG33__con_ring2_busy__SHIFT 0x1e +#define VGT_DEBUG_REG33__con_ring1_busy_MASK 0x80000000 +#define VGT_DEBUG_REG33__con_ring1_busy__SHIFT 0x1f +#define VGT_DEBUG_REG34__con_state_q_MASK 0xf +#define VGT_DEBUG_REG34__con_state_q__SHIFT 0x0 +#define VGT_DEBUG_REG34__second_cycle_q_MASK 0x10 +#define VGT_DEBUG_REG34__second_cycle_q__SHIFT 0x4 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q_MASK 0x20 +#define VGT_DEBUG_REG34__process_tri_middle_p0_q__SHIFT 0x5 +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q_MASK 0x40 +#define VGT_DEBUG_REG34__process_tri_1st_2nd_half_p0_q__SHIFT 0x6 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q_MASK 0x80 +#define VGT_DEBUG_REG34__process_tri_center_poly_p0_q__SHIFT 0x7 +#define VGT_DEBUG_REG34__pipe0_patch_dr_MASK 0x100 +#define VGT_DEBUG_REG34__pipe0_patch_dr__SHIFT 0x8 +#define VGT_DEBUG_REG34__pipe0_edge_dr_MASK 0x200 +#define VGT_DEBUG_REG34__pipe0_edge_dr__SHIFT 0x9 +#define VGT_DEBUG_REG34__pipe1_dr_MASK 0x400 +#define VGT_DEBUG_REG34__pipe1_dr__SHIFT 0xa +#define VGT_DEBUG_REG34__pipe0_patch_rtr_MASK 0x800 +#define VGT_DEBUG_REG34__pipe0_patch_rtr__SHIFT 0xb +#define VGT_DEBUG_REG34__pipe0_edge_rtr_MASK 0x1000 +#define VGT_DEBUG_REG34__pipe0_edge_rtr__SHIFT 0xc +#define VGT_DEBUG_REG34__pipe1_rtr_MASK 0x2000 +#define VGT_DEBUG_REG34__pipe1_rtr__SHIFT 0xd +#define VGT_DEBUG_REG34__outer_parity_p0_q_MASK 0x4000 +#define VGT_DEBUG_REG34__outer_parity_p0_q__SHIFT 0xe +#define VGT_DEBUG_REG34__parallel_parity_p0_q_MASK 0x8000 +#define VGT_DEBUG_REG34__parallel_parity_p0_q__SHIFT 0xf +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q_MASK 0x10000 +#define VGT_DEBUG_REG34__first_ring_of_patch_p0_q__SHIFT 0x10 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q_MASK 0x20000 +#define VGT_DEBUG_REG34__last_ring_of_patch_p0_q__SHIFT 0x11 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q_MASK 0x40000 +#define VGT_DEBUG_REG34__last_edge_of_outer_ring_p0_q__SHIFT 0x12 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1_MASK 0x80000 +#define VGT_DEBUG_REG34__last_point_of_outer_ring_p1__SHIFT 0x13 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1_MASK 0x100000 +#define VGT_DEBUG_REG34__last_point_of_inner_ring_p1__SHIFT 0x14 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q_MASK 0x200000 +#define VGT_DEBUG_REG34__outer_edge_tf_eq_one_p0_q__SHIFT 0x15 +#define VGT_DEBUG_REG34__advance_outer_point_p1_MASK 0x400000 +#define VGT_DEBUG_REG34__advance_outer_point_p1__SHIFT 0x16 +#define VGT_DEBUG_REG34__advance_inner_point_p1_MASK 0x800000 +#define VGT_DEBUG_REG34__advance_inner_point_p1__SHIFT 0x17 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q_MASK 0x1000000 +#define VGT_DEBUG_REG34__next_ring_is_rect_p0_q__SHIFT 0x18 +#define VGT_DEBUG_REG34__pipe1_outer1_rtr_MASK 0x2000000 +#define VGT_DEBUG_REG34__pipe1_outer1_rtr__SHIFT 0x19 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr_MASK 0x4000000 +#define VGT_DEBUG_REG34__pipe1_outer2_rtr__SHIFT 0x1a +#define VGT_DEBUG_REG34__pipe1_inner1_rtr_MASK 0x8000000 +#define VGT_DEBUG_REG34__pipe1_inner1_rtr__SHIFT 0x1b +#define VGT_DEBUG_REG34__pipe1_inner2_rtr_MASK 0x10000000 +#define VGT_DEBUG_REG34__pipe1_inner2_rtr__SHIFT 0x1c +#define VGT_DEBUG_REG34__pipe1_patch_rtr_MASK 0x20000000 +#define VGT_DEBUG_REG34__pipe1_patch_rtr__SHIFT 0x1d +#define VGT_DEBUG_REG34__pipe1_edge_rtr_MASK 0x40000000 +#define VGT_DEBUG_REG34__pipe1_edge_rtr__SHIFT 0x1e +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1_MASK 0x80000000 +#define VGT_DEBUG_REG34__use_stored_inner_q_ring1__SHIFT 0x1f +#define VGT_DEBUG_REG36__VGT_PA_clipp_eop_MASK 0xffffffff +#define VGT_DEBUG_REG36__VGT_PA_clipp_eop__SHIFT 0x0 +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK_MASK 0xff +#define VGT_PERFCOUNTER_SEID_MASK__PERF_SEID_IGNORE_MASK__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define VGT_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define VGT_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0x3ff +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1_MASK 0xffc00 +#define VGT_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE_MASK 0xf00000 +#define VGT_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1_MASK 0xf000000 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define VGT_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define VGT_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define VGT_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define VGT_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define VGT_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK 0x3ff +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT 0x0 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK 0xffc00 +#define VGT_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT 0xa +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK 0xf000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT 0x18 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define VGT_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT 0x1c +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define VGT_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define VGT_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0x3ff +#define IA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1_MASK 0xffc00 +#define IA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE_MASK 0xf00000 +#define IA_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT 0x14 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1_MASK 0xf000000 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define IA_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define IA_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK 0x3ff +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT 0x0 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK 0xffc00 +#define IA_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK 0xf000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT 0x18 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK 0xf0000000 +#define IA_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT 0x1c +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define IA_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define IA_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER1_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER2_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER3_SELECT__PERF_SEL_MASK 0xff +#define WD_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT 0x0 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE_MASK 0xf0000000 +#define WD_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT 0x1c +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER2_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO_MASK 0xffffffff +#define WD_PERFCOUNTER3_LO__PERFCOUNTER_LO__SHIFT 0x0 +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER2_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK 0xffffffff +#define WD_PERFCOUNTER3_HI__PERFCOUNTER_HI__SHIFT 0x0 +#define DIDT_IND_INDEX__DIDT_IND_INDEX_MASK 0xffffffff +#define DIDT_IND_INDEX__DIDT_IND_INDEX__SHIFT 0x0 +#define DIDT_IND_DATA__DIDT_IND_DATA_MASK 0xffffffff +#define DIDT_IND_DATA__DIDT_IND_DATA__SHIFT 0x0 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_SQ_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_SQ_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_SQ_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_SQ_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_SQ_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_SQ_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_SQ_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_SQ_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_SQ_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DB_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_DB_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_DB_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_DB_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DB_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_DB_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DB_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_DB_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DB_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_DB_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_DB_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_DB_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_DB_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_DB_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_DB_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DB_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_DB_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DB_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_DB_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DB_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_DB_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DB_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_DB_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DB_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_DB_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DB_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_DB_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DB_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_DB_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DB_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_DB_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DB_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_DB_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DB_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_DB_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DB_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_DB_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TD_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_TD_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_TD_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TD_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_TD_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TD_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_TD_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TD_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_TD_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_TD_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_TD_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TD_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TD_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TD_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TD_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TD_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TD_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TD_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TD_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_TD_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TD_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_TD_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TD_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_TD_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TD_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_TD_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_TCP_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_TCP_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_TCP_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_TCP_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_TCP_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_TCP_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_TCP_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_TCP_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_TCP_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_TCP_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_TCP_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_TCP_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_TCP_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_TCP_WEIGHT8_11__WEIGHT11__SHIFT 0x18 +#define DIDT_DBR_CTRL0__DIDT_CTRL_EN_MASK 0x1 +#define DIDT_DBR_CTRL0__DIDT_CTRL_EN__SHIFT 0x0 +#define DIDT_DBR_CTRL0__USE_REF_CLOCK_MASK 0x2 +#define DIDT_DBR_CTRL0__USE_REF_CLOCK__SHIFT 0x1 +#define DIDT_DBR_CTRL0__PHASE_OFFSET_MASK 0xc +#define DIDT_DBR_CTRL0__PHASE_OFFSET__SHIFT 0x2 +#define DIDT_DBR_CTRL0__DIDT_CTRL_RST_MASK 0x10 +#define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 +#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 +#define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 +#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0 +#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6 +#define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff +#define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 +#define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000 +#define DIDT_DBR_CTRL1__MAX_POWER__SHIFT 0x10 +#define DIDT_DBR_CTRL2__MAX_POWER_DELTA_MASK 0x3fff +#define DIDT_DBR_CTRL2__MAX_POWER_DELTA__SHIFT 0x0 +#define DIDT_DBR_CTRL2__UNUSED_0_MASK 0xc000 +#define DIDT_DBR_CTRL2__UNUSED_0__SHIFT 0xe +#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK 0x3ff0000 +#define DIDT_DBR_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT 0x10 +#define DIDT_DBR_CTRL2__UNUSED_1_MASK 0x4000000 +#define DIDT_DBR_CTRL2__UNUSED_1__SHIFT 0x1a +#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK 0x78000000 +#define DIDT_DBR_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT 0x1b +#define DIDT_DBR_CTRL2__UNUSED_2_MASK 0x80000000 +#define DIDT_DBR_CTRL2__UNUSED_2__SHIFT 0x1f +#define DIDT_DBR_CTRL_OCP__UNUSED_0_MASK 0xffff +#define DIDT_DBR_CTRL_OCP__UNUSED_0__SHIFT 0x0 +#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER_MASK 0xffff0000 +#define DIDT_DBR_CTRL_OCP__OCP_MAX_POWER__SHIFT 0x10 +#define DIDT_DBR_WEIGHT0_3__WEIGHT0_MASK 0xff +#define DIDT_DBR_WEIGHT0_3__WEIGHT0__SHIFT 0x0 +#define DIDT_DBR_WEIGHT0_3__WEIGHT1_MASK 0xff00 +#define DIDT_DBR_WEIGHT0_3__WEIGHT1__SHIFT 0x8 +#define DIDT_DBR_WEIGHT0_3__WEIGHT2_MASK 0xff0000 +#define DIDT_DBR_WEIGHT0_3__WEIGHT2__SHIFT 0x10 +#define DIDT_DBR_WEIGHT0_3__WEIGHT3_MASK 0xff000000 +#define DIDT_DBR_WEIGHT0_3__WEIGHT3__SHIFT 0x18 +#define DIDT_DBR_WEIGHT4_7__WEIGHT4_MASK 0xff +#define DIDT_DBR_WEIGHT4_7__WEIGHT4__SHIFT 0x0 +#define DIDT_DBR_WEIGHT4_7__WEIGHT5_MASK 0xff00 +#define DIDT_DBR_WEIGHT4_7__WEIGHT5__SHIFT 0x8 +#define DIDT_DBR_WEIGHT4_7__WEIGHT6_MASK 0xff0000 +#define DIDT_DBR_WEIGHT4_7__WEIGHT6__SHIFT 0x10 +#define DIDT_DBR_WEIGHT4_7__WEIGHT7_MASK 0xff000000 +#define DIDT_DBR_WEIGHT4_7__WEIGHT7__SHIFT 0x18 +#define DIDT_DBR_WEIGHT8_11__WEIGHT8_MASK 0xff +#define DIDT_DBR_WEIGHT8_11__WEIGHT8__SHIFT 0x0 +#define DIDT_DBR_WEIGHT8_11__WEIGHT9_MASK 0xff00 +#define DIDT_DBR_WEIGHT8_11__WEIGHT9__SHIFT 0x8 +#define DIDT_DBR_WEIGHT8_11__WEIGHT10_MASK 0xff0000 +#define DIDT_DBR_WEIGHT8_11__WEIGHT10__SHIFT 0x10 +#define DIDT_DBR_WEIGHT8_11__WEIGHT11_MASK 0xff000000 +#define DIDT_DBR_WEIGHT8_11__WEIGHT11__SHIFT 0x18 + +#endif /* GFX_8_1_SH_MASK_H */ diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h index 44c5d4a4d1bf..552622675ace 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -6784,7 +6784,7 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 ULONG ulMCUcodeRomStartAddr; ULONG ulMCUcodeLength; USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. - USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY regsiter setting + USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting }ATOM_MC_INIT_PARAM_TABLE_V2_1; diff --git a/drivers/gpu/drm/amd/include/cgs_linux.h b/drivers/gpu/drm/amd/include/cgs_linux.h index 488642f08267..3b47ae313e36 100644 --- a/drivers/gpu/drm/amd/include/cgs_linux.h +++ b/drivers/gpu/drm/amd/include/cgs_linux.h @@ -27,19 +27,6 @@ #include "cgs_common.h" /** - * cgs_import_gpu_mem() - Import dmabuf handle - * @cgs_device: opaque device handle - * @dmabuf_fd: DMABuf file descriptor - * @handle: memory handle (output) - * - * Must be called in the process context that dmabuf_fd belongs to. - * - * Return: 0 on success, -errno otherwise - */ -typedef int (*cgs_import_gpu_mem_t)(void *cgs_device, int dmabuf_fd, - cgs_handle_t *handle); - -/** * cgs_irq_source_set_func() - Callback for enabling/disabling interrupt sources * @private_data: private data provided to cgs_add_irq_source * @src_id: interrupt source ID @@ -114,16 +101,12 @@ typedef int (*cgs_irq_get_t)(void *cgs_device, unsigned src_id, unsigned type); typedef int (*cgs_irq_put_t)(void *cgs_device, unsigned src_id, unsigned type); struct cgs_os_ops { - cgs_import_gpu_mem_t import_gpu_mem; - /* IRQ handling */ cgs_add_irq_source_t add_irq_source; cgs_irq_get_t irq_get; cgs_irq_put_t irq_put; }; -#define cgs_import_gpu_mem(dev,dmabuf_fd,handle) \ - CGS_OS_CALL(import_gpu_mem,dev,dmabuf_fd,handle) #define cgs_add_irq_source(dev,src_id,num_types,set,handler,private_data) \ CGS_OS_CALL(add_irq_source,dev,src_id,num_types,set,handler, \ private_data) diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c index 3697eeeecf82..89619a5a4289 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c @@ -222,6 +222,12 @@ amd_sched_entity_pop_job(struct amd_sched_entity *entity) while ((entity->dependency = sched->ops->dependency(sched_job))) { + if (entity->dependency->context == entity->fence_context) { + /* We can ignore fences from ourself */ + fence_put(entity->dependency); + continue; + } + if (fence_add_callback(entity->dependency, &entity->cb, amd_sched_entity_wakeup)) fence_put(entity->dependency); @@ -327,19 +333,49 @@ static void amd_sched_process_job(struct fence *f, struct fence_cb *cb) struct amd_sched_fence *s_fence = container_of(cb, struct amd_sched_fence, cb); struct amd_gpu_scheduler *sched = s_fence->sched; + unsigned long flags; atomic_dec(&sched->hw_rq_count); amd_sched_fence_signal(s_fence); + if (sched->timeout != MAX_SCHEDULE_TIMEOUT) { + cancel_delayed_work(&s_fence->dwork); + spin_lock_irqsave(&sched->fence_list_lock, flags); + list_del_init(&s_fence->list); + spin_unlock_irqrestore(&sched->fence_list_lock, flags); + } fence_put(&s_fence->base); wake_up_interruptible(&sched->wake_up_worker); } +static void amd_sched_fence_work_func(struct work_struct *work) +{ + struct amd_sched_fence *s_fence = + container_of(work, struct amd_sched_fence, dwork.work); + struct amd_gpu_scheduler *sched = s_fence->sched; + struct amd_sched_fence *entity, *tmp; + unsigned long flags; + + DRM_ERROR("[%s] scheduler is timeout!\n", sched->name); + + /* Clean all pending fences */ + spin_lock_irqsave(&sched->fence_list_lock, flags); + list_for_each_entry_safe(entity, tmp, &sched->fence_list, list) { + DRM_ERROR(" fence no %d\n", entity->base.seqno); + cancel_delayed_work(&entity->dwork); + list_del_init(&entity->list); + fence_put(&entity->base); + } + spin_unlock_irqrestore(&sched->fence_list_lock, flags); +} + static int amd_sched_main(void *param) { struct sched_param sparam = {.sched_priority = 1}; struct amd_gpu_scheduler *sched = (struct amd_gpu_scheduler *)param; int r, count; + spin_lock_init(&sched->fence_list_lock); + INIT_LIST_HEAD(&sched->fence_list); sched_setscheduler(current, SCHED_FIFO, &sparam); while (!kthread_should_stop()) { @@ -347,6 +383,7 @@ static int amd_sched_main(void *param) struct amd_sched_fence *s_fence; struct amd_sched_job *sched_job; struct fence *fence; + unsigned long flags; wait_event_interruptible(sched->wake_up_worker, kthread_should_stop() || @@ -357,6 +394,15 @@ static int amd_sched_main(void *param) entity = sched_job->s_entity; s_fence = sched_job->s_fence; + + if (sched->timeout != MAX_SCHEDULE_TIMEOUT) { + INIT_DELAYED_WORK(&s_fence->dwork, amd_sched_fence_work_func); + schedule_delayed_work(&s_fence->dwork, sched->timeout); + spin_lock_irqsave(&sched->fence_list_lock, flags); + list_add_tail(&s_fence->list, &sched->fence_list); + spin_unlock_irqrestore(&sched->fence_list_lock, flags); + } + atomic_inc(&sched->hw_rq_count); fence = sched->ops->run_job(sched_job); if (fence) { @@ -392,11 +438,12 @@ static int amd_sched_main(void *param) */ int amd_sched_init(struct amd_gpu_scheduler *sched, struct amd_sched_backend_ops *ops, - unsigned hw_submission, const char *name) + unsigned hw_submission, long timeout, const char *name) { sched->ops = ops; sched->hw_submission_limit = hw_submission; sched->name = name; + sched->timeout = timeout; amd_sched_rq_init(&sched->sched_rq); amd_sched_rq_init(&sched->kernel_rq); @@ -421,5 +468,6 @@ int amd_sched_init(struct amd_gpu_scheduler *sched, */ void amd_sched_fini(struct amd_gpu_scheduler *sched) { - kthread_stop(sched->thread); + if (sched->thread) + kthread_stop(sched->thread); } diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h index 80b64dc22214..929e9aced041 100644 --- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h +++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.h @@ -68,6 +68,8 @@ struct amd_sched_fence { struct amd_gpu_scheduler *sched; spinlock_t lock; void *owner; + struct delayed_work dwork; + struct list_head list; }; struct amd_sched_job { @@ -103,18 +105,21 @@ struct amd_sched_backend_ops { struct amd_gpu_scheduler { struct amd_sched_backend_ops *ops; uint32_t hw_submission_limit; + long timeout; const char *name; struct amd_sched_rq sched_rq; struct amd_sched_rq kernel_rq; wait_queue_head_t wake_up_worker; wait_queue_head_t job_scheduled; atomic_t hw_rq_count; + struct list_head fence_list; + spinlock_t fence_list_lock; struct task_struct *thread; }; int amd_sched_init(struct amd_gpu_scheduler *sched, struct amd_sched_backend_ops *ops, - uint32_t hw_submission, const char *name); + uint32_t hw_submission, long timeout, const char *name); void amd_sched_fini(struct amd_gpu_scheduler *sched); int amd_sched_entity_init(struct amd_gpu_scheduler *sched, diff --git a/drivers/gpu/drm/armada/Kconfig b/drivers/gpu/drm/armada/Kconfig index 50ae88ad4d76..eb773e9af313 100644 --- a/drivers/gpu/drm/armada/Kconfig +++ b/drivers/gpu/drm/armada/Kconfig @@ -14,12 +14,3 @@ config DRM_ARMADA This driver provides no built-in acceleration; acceleration is performed by other IP found on the SoC. This driver provides kernel mode setting and buffer management to userspace. - -config DRM_ARMADA_TDA1998X - bool "Support TDA1998X HDMI output" - depends on DRM_ARMADA != n - depends on I2C && DRM_I2C_NXP_TDA998X = y - default y - help - Support the TDA1998x HDMI output device found on the Solid-Run - CuBox. diff --git a/drivers/gpu/drm/armada/Makefile b/drivers/gpu/drm/armada/Makefile index d6f43e06150a..ffd673615772 100644 --- a/drivers/gpu/drm/armada/Makefile +++ b/drivers/gpu/drm/armada/Makefile @@ -1,6 +1,5 @@ armada-y := armada_crtc.o armada_drv.o armada_fb.o armada_fbdev.o \ - armada_gem.o armada_output.o armada_overlay.o \ - armada_slave.o + armada_gem.o armada_overlay.o armada-y += armada_510.o armada-$(CONFIG_DEBUG_FS) += armada_debugfs.o diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c index 01ffe9bffe38..cebcab560626 100644 --- a/drivers/gpu/drm/armada/armada_crtc.c +++ b/drivers/gpu/drm/armada/armada_crtc.c @@ -20,6 +20,7 @@ #include "armada_hw.h" struct armada_frame_work { + struct armada_plane_work work; struct drm_pending_vblank_event *event; struct armada_regs regs[4]; struct drm_framebuffer *old_fb; @@ -33,6 +34,23 @@ enum csc_mode { CSC_RGB_STUDIO = 2, }; +static const uint32_t armada_primary_formats[] = { + DRM_FORMAT_UYVY, + DRM_FORMAT_YUYV, + DRM_FORMAT_VYUY, + DRM_FORMAT_YVYU, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_ABGR1555, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, +}; + /* * A note about interlacing. Let's consider HDMI 1920x1080i. * The timing parameters we have from X are: @@ -173,49 +191,82 @@ static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, return i; } -static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, - struct armada_frame_work *work) +static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, + struct armada_plane *plane) +{ + struct armada_plane_work *work = xchg(&plane->work, NULL); + + /* Handle any pending frame work. */ + if (work) { + work->fn(dcrtc, plane, work); + drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); + } + + wake_up(&plane->frame_wait); +} + +int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, + struct armada_plane *plane, struct armada_plane_work *work) { - struct drm_device *dev = dcrtc->crtc.dev; - unsigned long flags; int ret; - ret = drm_vblank_get(dev, dcrtc->num); + ret = drm_vblank_get(dcrtc->crtc.dev, dcrtc->num); if (ret) { DRM_ERROR("failed to acquire vblank counter\n"); return ret; } - spin_lock_irqsave(&dev->event_lock, flags); - if (!dcrtc->frame_work) - dcrtc->frame_work = work; - else - ret = -EBUSY; - spin_unlock_irqrestore(&dev->event_lock, flags); - + ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0; if (ret) - drm_vblank_put(dev, dcrtc->num); + drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); return ret; } -static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc) +int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout) { - struct drm_device *dev = dcrtc->crtc.dev; - struct armada_frame_work *work = dcrtc->frame_work; + return wait_event_timeout(plane->frame_wait, !plane->work, timeout); +} - dcrtc->frame_work = NULL; +struct armada_plane_work *armada_drm_plane_work_cancel( + struct armada_crtc *dcrtc, struct armada_plane *plane) +{ + struct armada_plane_work *work = xchg(&plane->work, NULL); - armada_drm_crtc_update_regs(dcrtc, work->regs); + if (work) + drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); - if (work->event) - drm_send_vblank_event(dev, dcrtc->num, work->event); + return work; +} - drm_vblank_put(dev, dcrtc->num); +static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, + struct armada_frame_work *work) +{ + struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); + + return armada_drm_plane_work_queue(dcrtc, plane, &work->work); +} + +static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, + struct armada_plane *plane, struct armada_plane_work *work) +{ + struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); + struct drm_device *dev = dcrtc->crtc.dev; + unsigned long flags; + + spin_lock_irqsave(&dcrtc->irq_lock, flags); + armada_drm_crtc_update_regs(dcrtc, fwork->regs); + spin_unlock_irqrestore(&dcrtc->irq_lock, flags); + + if (fwork->event) { + spin_lock_irqsave(&dev->event_lock, flags); + drm_send_vblank_event(dev, dcrtc->num, fwork->event); + spin_unlock_irqrestore(&dev->event_lock, flags); + } /* Finally, queue the process-half of the cleanup. */ - __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb); - kfree(work); + __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb); + kfree(fwork); } static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, @@ -235,6 +286,7 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, work = kmalloc(sizeof(*work), GFP_KERNEL); if (work) { int i = 0; + work->work.fn = armada_drm_crtc_complete_frame_work; work->event = NULL; work->old_fb = fb; armada_reg_queue_end(work->regs, i); @@ -255,19 +307,14 @@ static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, static void armada_drm_vblank_off(struct armada_crtc *dcrtc) { - struct drm_device *dev = dcrtc->crtc.dev; + struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); /* * Tell the DRM core that vblank IRQs aren't going to happen for * a while. This cleans up any pending vblank events for us. */ drm_crtc_vblank_off(&dcrtc->crtc); - - /* Handle any pending flip event. */ - spin_lock_irq(&dev->event_lock); - if (dcrtc->frame_work) - armada_drm_crtc_complete_frame_work(dcrtc); - spin_unlock_irq(&dev->event_lock); + armada_drm_plane_work_run(dcrtc, plane); } void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b, @@ -287,7 +334,11 @@ static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms) if (dcrtc->dpms != dpms) { dcrtc->dpms = dpms; + if (!IS_ERR(dcrtc->clk) && !dpms_blanked(dpms)) + WARN_ON(clk_prepare_enable(dcrtc->clk)); armada_drm_crtc_update(dcrtc); + if (!IS_ERR(dcrtc->clk) && dpms_blanked(dpms)) + clk_disable_unprepare(dcrtc->clk); if (dpms_blanked(dpms)) armada_drm_vblank_off(dcrtc); else @@ -310,17 +361,11 @@ static void armada_drm_crtc_prepare(struct drm_crtc *crtc) /* * If we have an overlay plane associated with this CRTC, disable * it before the modeset to avoid its coordinates being outside - * the new mode parameters. DRM doesn't provide help with this. + * the new mode parameters. */ plane = dcrtc->plane; - if (plane) { - struct drm_framebuffer *fb = plane->fb; - - plane->funcs->disable_plane(plane); - plane->fb = NULL; - plane->crtc = NULL; - drm_framebuffer_unreference(fb); - } + if (plane) + drm_plane_force_disable(plane); } /* The mode_config.mutex will be held for this call */ @@ -356,8 +401,8 @@ static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc, static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) { - struct armada_vbl_event *e, *n; void __iomem *base = dcrtc->base; + struct drm_plane *ovl_plane; if (stat & DMA_FF_UNDERFLOW) DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); @@ -368,11 +413,10 @@ static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num); spin_lock(&dcrtc->irq_lock); - - list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) { - list_del_init(&e->node); - drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); - e->fn(dcrtc, e->data); + ovl_plane = dcrtc->plane; + if (ovl_plane) { + struct armada_plane *plane = drm_to_armada_plane(ovl_plane); + armada_drm_plane_work_run(dcrtc, plane); } if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { @@ -404,14 +448,8 @@ static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) spin_unlock(&dcrtc->irq_lock); if (stat & GRA_FRAME_IRQ) { - struct drm_device *dev = dcrtc->crtc.dev; - - spin_lock(&dev->event_lock); - if (dcrtc->frame_work) - armada_drm_crtc_complete_frame_work(dcrtc); - spin_unlock(&dev->event_lock); - - wake_up(&dcrtc->frame_wait); + struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); + armada_drm_plane_work_run(dcrtc, plane); } } @@ -527,7 +565,8 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, adj->crtc_vtotal, tm, bm); /* Wait for pending flips to complete */ - wait_event(dcrtc->frame_wait, !dcrtc->frame_work); + armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), + MAX_SCHEDULE_TIMEOUT); drm_crtc_vblank_off(crtc); @@ -537,6 +576,13 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); } + /* + * If we are blanked, we would have disabled the clock. Re-enable + * it so that compute_clock() does the right thing. + */ + if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms)) + WARN_ON(clk_prepare_enable(dcrtc->clk)); + /* Now compute the divider for real */ dcrtc->variant->compute_clock(dcrtc, adj, &sclk); @@ -637,7 +683,8 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, armada_reg_queue_end(regs, i); /* Wait for pending flips to complete */ - wait_event(dcrtc->frame_wait, !dcrtc->frame_work); + armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), + MAX_SCHEDULE_TIMEOUT); /* Take a reference to the new fb as we're using it */ drm_framebuffer_reference(crtc->primary->fb); @@ -651,18 +698,47 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, return 0; } +void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, + struct drm_plane *plane) +{ + u32 sram_para1, dma_ctrl0_mask; + + /* + * Drop our reference on any framebuffer attached to this plane. + * We don't need to NULL this out as drm_plane_force_disable(), + * and __setplane_internal() will do so for an overlay plane, and + * __drm_helper_disable_unused_functions() will do so for the + * primary plane. + */ + if (plane->fb) + drm_framebuffer_unreference(plane->fb); + + /* Power down the Y/U/V FIFOs */ + sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; + + /* Power down most RAMs and FIFOs if this is the primary plane */ + if (plane->type == DRM_PLANE_TYPE_PRIMARY) { + sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | + CFG_PDWN32x32 | CFG_PDWN64x66; + dma_ctrl0_mask = CFG_GRA_ENA; + } else { + dma_ctrl0_mask = CFG_DMA_ENA; + } + + spin_lock_irq(&dcrtc->irq_lock); + armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); + spin_unlock_irq(&dcrtc->irq_lock); + + armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); +} + /* The mode_config.mutex will be held for this call */ static void armada_drm_crtc_disable(struct drm_crtc *crtc) { struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); - armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true); - - /* Power down most RAMs and FIFOs */ - writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | - CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | - CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); + armada_drm_crtc_plane_disable(dcrtc, crtc->primary); } static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = { @@ -920,8 +996,6 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, { struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); struct armada_frame_work *work; - struct drm_device *dev = crtc->dev; - unsigned long flags; unsigned i; int ret; @@ -933,6 +1007,7 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, if (!work) return -ENOMEM; + work->work.fn = armada_drm_crtc_complete_frame_work; work->event = event; work->old_fb = dcrtc->crtc.primary->fb; @@ -966,12 +1041,8 @@ static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, * Finally, if the display is blanked, we won't receive an * interrupt, so complete it now. */ - if (dpms_blanked(dcrtc->dpms)) { - spin_lock_irqsave(&dev->event_lock, flags); - if (dcrtc->frame_work) - armada_drm_crtc_complete_frame_work(dcrtc); - spin_unlock_irqrestore(&dev->event_lock, flags); - } + if (dpms_blanked(dcrtc->dpms)) + armada_drm_plane_work_run(dcrtc, drm_to_armada_plane(dcrtc->crtc.primary)); return 0; } @@ -1012,6 +1083,19 @@ static struct drm_crtc_funcs armada_crtc_funcs = { .set_property = armada_drm_crtc_set_property, }; +static const struct drm_plane_funcs armada_primary_plane_funcs = { + .update_plane = drm_primary_helper_update, + .disable_plane = drm_primary_helper_disable, + .destroy = drm_primary_helper_destroy, +}; + +int armada_drm_plane_init(struct armada_plane *plane) +{ + init_waitqueue_head(&plane->frame_wait); + + return 0; +} + static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = { { CSC_AUTO, "Auto" }, { CSC_YUV_CCIR601, "CCIR601" }, @@ -1044,12 +1128,13 @@ static int armada_drm_crtc_create_properties(struct drm_device *dev) return 0; } -int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, +static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, struct resource *res, int irq, const struct armada_variant *variant, struct device_node *port) { struct armada_private *priv = drm->dev_private; struct armada_crtc *dcrtc; + struct armada_plane *primary; void __iomem *base; int ret; @@ -1080,8 +1165,6 @@ int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; spin_lock_init(&dcrtc->irq_lock); dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; - INIT_LIST_HEAD(&dcrtc->vbl_list); - init_waitqueue_head(&dcrtc->frame_wait); /* Initialize some registers which we don't otherwise set */ writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); @@ -1118,7 +1201,32 @@ int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, priv->dcrtc[dcrtc->num] = dcrtc; dcrtc->crtc.port = port; - drm_crtc_init(drm, &dcrtc->crtc, &armada_crtc_funcs); + + primary = kzalloc(sizeof(*primary), GFP_KERNEL); + if (!primary) + return -ENOMEM; + + ret = armada_drm_plane_init(primary); + if (ret) { + kfree(primary); + return ret; + } + + ret = drm_universal_plane_init(drm, &primary->base, 0, + &armada_primary_plane_funcs, + armada_primary_formats, + ARRAY_SIZE(armada_primary_formats), + DRM_PLANE_TYPE_PRIMARY); + if (ret) { + kfree(primary); + return ret; + } + + ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL, + &armada_crtc_funcs); + if (ret) + goto err_crtc_init; + drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop, @@ -1127,6 +1235,10 @@ int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, dcrtc->csc_rgb_mode); return armada_overlay_plane_create(drm, 1 << dcrtc->num); + +err_crtc_init: + primary->base.funcs->destroy(&primary->base); + return ret; } static int diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h index 98102a5a9af5..04fdd22d483b 100644 --- a/drivers/gpu/drm/armada/armada_crtc.h +++ b/drivers/gpu/drm/armada/armada_crtc.h @@ -31,9 +31,30 @@ struct armada_regs { #define armada_reg_queue_end(_r, _i) \ armada_reg_queue_mod(_r, _i, 0, 0, ~0) -struct armada_frame_work; +struct armada_crtc; +struct armada_plane; struct armada_variant; +struct armada_plane_work { + void (*fn)(struct armada_crtc *, + struct armada_plane *, + struct armada_plane_work *); +}; + +struct armada_plane { + struct drm_plane base; + wait_queue_head_t frame_wait; + struct armada_plane_work *work; +}; +#define drm_to_armada_plane(p) container_of(p, struct armada_plane, base) + +int armada_drm_plane_init(struct armada_plane *plane); +int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, + struct armada_plane *plane, struct armada_plane_work *work); +int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout); +struct armada_plane_work *armada_drm_plane_work_cancel( + struct armada_crtc *dcrtc, struct armada_plane *plane); + struct armada_crtc { struct drm_crtc crtc; const struct armada_variant *variant; @@ -66,25 +87,20 @@ struct armada_crtc { uint32_t dumb_ctrl; uint32_t spu_iopad_ctrl; - wait_queue_head_t frame_wait; - struct armada_frame_work *frame_work; - spinlock_t irq_lock; uint32_t irq_ena; - struct list_head vbl_list; }; #define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc) -struct device_node; -int armada_drm_crtc_create(struct drm_device *, struct device *, - struct resource *, int, const struct armada_variant *, - struct device_node *); void armada_drm_crtc_gamma_set(struct drm_crtc *, u16, u16, u16, int); void armada_drm_crtc_gamma_get(struct drm_crtc *, u16 *, u16 *, u16 *, int); void armada_drm_crtc_disable_irq(struct armada_crtc *, u32); void armada_drm_crtc_enable_irq(struct armada_crtc *, u32); void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *); +void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, + struct drm_plane *plane); + extern struct platform_driver armada_lcd_platform_driver; #endif diff --git a/drivers/gpu/drm/armada/armada_drm.h b/drivers/gpu/drm/armada/armada_drm.h index 5f6aef0dca59..4df6f2af2b21 100644 --- a/drivers/gpu/drm/armada/armada_drm.h +++ b/drivers/gpu/drm/armada/armada_drm.h @@ -37,22 +37,6 @@ static inline uint32_t armada_pitch(uint32_t width, uint32_t bpp) return ALIGN(pitch, 128); } -struct armada_vbl_event { - struct list_head node; - void *data; - void (*fn)(struct armada_crtc *, void *); -}; -void armada_drm_vbl_event_add(struct armada_crtc *, - struct armada_vbl_event *); -void armada_drm_vbl_event_remove(struct armada_crtc *, - struct armada_vbl_event *); -#define armada_drm_vbl_event_init(_e, _f, _d) do { \ - struct armada_vbl_event *__e = _e; \ - INIT_LIST_HEAD(&__e->node); \ - __e->data = _d; \ - __e->fn = _f; \ -} while (0) - struct armada_private; diff --git a/drivers/gpu/drm/armada/armada_drv.c b/drivers/gpu/drm/armada/armada_drv.c index 225034b74cda..77ab93d60125 100644 --- a/drivers/gpu/drm/armada/armada_drv.c +++ b/drivers/gpu/drm/armada/armada_drv.c @@ -11,6 +11,7 @@ #include <linux/of_graph.h> #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> +#include <drm/drm_of.h> #include "armada_crtc.h" #include "armada_drm.h" #include "armada_gem.h" @@ -18,47 +19,6 @@ #include <drm/armada_drm.h> #include "armada_ioctlP.h" -#ifdef CONFIG_DRM_ARMADA_TDA1998X -#include <drm/i2c/tda998x.h> -#include "armada_slave.h" - -static struct tda998x_encoder_params params = { - /* With 0x24, there is no translation between vp_out and int_vp - FB LCD out Pins VIP Int Vp - R:23:16 R:7:0 VPC7:0 7:0 7:0[R] - G:15:8 G:15:8 VPB7:0 23:16 23:16[G] - B:7:0 B:23:16 VPA7:0 15:8 15:8[B] - */ - .swap_a = 2, - .swap_b = 3, - .swap_c = 4, - .swap_d = 5, - .swap_e = 0, - .swap_f = 1, - .audio_cfg = BIT(2), - .audio_frame[1] = 1, - .audio_format = AFMT_SPDIF, - .audio_sample_rate = 44100, -}; - -static const struct armada_drm_slave_config tda19988_config = { - .i2c_adapter_id = 0, - .crtcs = 1 << 0, /* Only LCD0 at the moment */ - .polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT, - .interlace_allowed = true, - .info = { - .type = "tda998x", - .addr = 0x70, - .platform_data = ¶ms, - }, -}; -#endif - -static bool is_componentized(struct device *dev) -{ - return dev->of_node || dev->platform_data; -} - static void armada_drm_unref_work(struct work_struct *work) { struct armada_private *priv = @@ -91,16 +51,11 @@ void armada_drm_queue_unref_work(struct drm_device *dev, static int armada_drm_load(struct drm_device *dev, unsigned long flags) { - const struct platform_device_id *id; - const struct armada_variant *variant; struct armada_private *priv; - struct resource *res[ARRAY_SIZE(priv->dcrtc)]; struct resource *mem = NULL; - int ret, n, i; - - memset(res, 0, sizeof(res)); + int ret, n; - for (n = i = 0; ; n++) { + for (n = 0; ; n++) { struct resource *r = platform_get_resource(dev->platformdev, IORESOURCE_MEM, n); if (!r) @@ -109,8 +64,6 @@ static int armada_drm_load(struct drm_device *dev, unsigned long flags) /* Resources above 64K are graphics memory */ if (resource_size(r) > SZ_64K) mem = r; - else if (i < ARRAY_SIZE(priv->dcrtc)) - res[i++] = r; else return -EINVAL; } @@ -131,13 +84,6 @@ static int armada_drm_load(struct drm_device *dev, unsigned long flags) platform_set_drvdata(dev->platformdev, dev); dev->dev_private = priv; - /* Get the implementation specific driver data. */ - id = platform_get_device_id(dev->platformdev); - if (!id) - return -ENXIO; - - variant = (const struct armada_variant *)id->driver_data; - INIT_WORK(&priv->fb_unref_work, armada_drm_unref_work); INIT_KFIFO(priv->fb_unref); @@ -157,34 +103,9 @@ static int armada_drm_load(struct drm_device *dev, unsigned long flags) dev->mode_config.funcs = &armada_drm_mode_config_funcs; drm_mm_init(&priv->linear, mem->start, resource_size(mem)); - /* Create all LCD controllers */ - for (n = 0; n < ARRAY_SIZE(priv->dcrtc); n++) { - int irq; - - if (!res[n]) - break; - - irq = platform_get_irq(dev->platformdev, n); - if (irq < 0) - goto err_kms; - - ret = armada_drm_crtc_create(dev, dev->dev, res[n], irq, - variant, NULL); - if (ret) - goto err_kms; - } - - if (is_componentized(dev->dev)) { - ret = component_bind_all(dev->dev, dev); - if (ret) - goto err_kms; - } else { -#ifdef CONFIG_DRM_ARMADA_TDA1998X - ret = armada_drm_connector_slave_create(dev, &tda19988_config); - if (ret) - goto err_kms; -#endif - } + ret = component_bind_all(dev->dev, dev); + if (ret) + goto err_kms; ret = drm_vblank_init(dev, dev->mode_config.num_crtc); if (ret) @@ -202,8 +123,7 @@ static int armada_drm_load(struct drm_device *dev, unsigned long flags) return 0; err_comp: - if (is_componentized(dev->dev)) - component_unbind_all(dev->dev, dev); + component_unbind_all(dev->dev, dev); err_kms: drm_mode_config_cleanup(dev); drm_mm_takedown(&priv->linear); @@ -219,8 +139,7 @@ static int armada_drm_unload(struct drm_device *dev) drm_kms_helper_poll_fini(dev); armada_fbdev_fini(dev); - if (is_componentized(dev->dev)) - component_unbind_all(dev->dev, dev); + component_unbind_all(dev->dev, dev); drm_mode_config_cleanup(dev); drm_mm_takedown(&priv->linear); @@ -230,50 +149,24 @@ static int armada_drm_unload(struct drm_device *dev) return 0; } -void armada_drm_vbl_event_add(struct armada_crtc *dcrtc, - struct armada_vbl_event *evt) -{ - unsigned long flags; - - spin_lock_irqsave(&dcrtc->irq_lock, flags); - if (list_empty(&evt->node)) { - list_add_tail(&evt->node, &dcrtc->vbl_list); - - drm_vblank_get(dcrtc->crtc.dev, dcrtc->num); - } - spin_unlock_irqrestore(&dcrtc->irq_lock, flags); -} - -void armada_drm_vbl_event_remove(struct armada_crtc *dcrtc, - struct armada_vbl_event *evt) -{ - if (!list_empty(&evt->node)) { - list_del_init(&evt->node); - drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); - } -} - /* These are called under the vbl_lock. */ -static int armada_drm_enable_vblank(struct drm_device *dev, int crtc) +static int armada_drm_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct armada_private *priv = dev->dev_private; - armada_drm_crtc_enable_irq(priv->dcrtc[crtc], VSYNC_IRQ_ENA); + armada_drm_crtc_enable_irq(priv->dcrtc[pipe], VSYNC_IRQ_ENA); return 0; } -static void armada_drm_disable_vblank(struct drm_device *dev, int crtc) +static void armada_drm_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct armada_private *priv = dev->dev_private; - armada_drm_crtc_disable_irq(priv->dcrtc[crtc], VSYNC_IRQ_ENA); + armada_drm_crtc_disable_irq(priv->dcrtc[pipe], VSYNC_IRQ_ENA); } static struct drm_ioctl_desc armada_ioctls[] = { - DRM_IOCTL_DEF_DRV(ARMADA_GEM_CREATE, armada_gem_create_ioctl, - DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(ARMADA_GEM_MMAP, armada_gem_mmap_ioctl, - DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(ARMADA_GEM_PWRITE, armada_gem_pwrite_ioctl, - DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(ARMADA_GEM_CREATE, armada_gem_create_ioctl,0), + DRM_IOCTL_DEF_DRV(ARMADA_GEM_MMAP, armada_gem_mmap_ioctl, 0), + DRM_IOCTL_DEF_DRV(ARMADA_GEM_PWRITE, armada_gem_pwrite_ioctl, 0), }; static void armada_drm_lastclose(struct drm_device *dev) @@ -300,7 +193,7 @@ static struct drm_driver armada_drm_driver = { .lastclose = armada_drm_lastclose, .unload = armada_drm_unload, .set_busid = drm_platform_set_busid, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = armada_drm_enable_vblank, .disable_vblank = armada_drm_disable_vblank, #ifdef CONFIG_DEBUG_FS @@ -370,43 +263,29 @@ static void armada_add_endpoints(struct device *dev, } } -static int armada_drm_find_components(struct device *dev, - struct component_match **match) -{ - struct device_node *port; - int i; - - if (dev->of_node) { - struct device_node *np = dev->of_node; - - for (i = 0; ; i++) { - port = of_parse_phandle(np, "ports", i); - if (!port) - break; - - component_match_add(dev, match, compare_of, port); - of_node_put(port); - } +static const struct component_master_ops armada_master_ops = { + .bind = armada_drm_bind, + .unbind = armada_drm_unbind, +}; - if (i == 0) { - dev_err(dev, "missing 'ports' property\n"); - return -ENODEV; - } +static int armada_drm_probe(struct platform_device *pdev) +{ + struct component_match *match = NULL; + struct device *dev = &pdev->dev; + int ret; - for (i = 0; ; i++) { - port = of_parse_phandle(np, "ports", i); - if (!port) - break; + ret = drm_of_component_probe(dev, compare_dev_name, &armada_master_ops); + if (ret != -EINVAL) + return ret; - armada_add_endpoints(dev, match, port); - of_node_put(port); - } - } else if (dev->platform_data) { + if (dev->platform_data) { char **devices = dev->platform_data; + struct device_node *port; struct device *d; + int i; for (i = 0; devices[i]; i++) - component_match_add(dev, match, compare_dev_name, + component_match_add(dev, &match, compare_dev_name, devices[i]); if (i == 0) { @@ -416,56 +295,30 @@ static int armada_drm_find_components(struct device *dev, for (i = 0; devices[i]; i++) { d = bus_find_device_by_name(&platform_bus_type, NULL, - devices[i]); + devices[i]); if (d && d->of_node) { for_each_child_of_node(d->of_node, port) - armada_add_endpoints(dev, match, port); + armada_add_endpoints(dev, &match, port); } put_device(d); } } - return 0; -} - -static const struct component_master_ops armada_master_ops = { - .bind = armada_drm_bind, - .unbind = armada_drm_unbind, -}; - -static int armada_drm_probe(struct platform_device *pdev) -{ - if (is_componentized(&pdev->dev)) { - struct component_match *match = NULL; - int ret; - - ret = armada_drm_find_components(&pdev->dev, &match); - if (ret < 0) - return ret; - - return component_master_add_with_match(&pdev->dev, - &armada_master_ops, match); - } else { - return drm_platform_init(&armada_drm_driver, pdev); - } + return component_master_add_with_match(&pdev->dev, &armada_master_ops, + match); } static int armada_drm_remove(struct platform_device *pdev) { - if (is_componentized(&pdev->dev)) - component_master_del(&pdev->dev, &armada_master_ops); - else - drm_put_dev(platform_get_drvdata(pdev)); + component_master_del(&pdev->dev, &armada_master_ops); return 0; } static const struct platform_device_id armada_drm_platform_ids[] = { { .name = "armada-drm", - .driver_data = (unsigned long)&armada510_ops, }, { .name = "armada-510-drm", - .driver_data = (unsigned long)&armada510_ops, }, { }, }; diff --git a/drivers/gpu/drm/armada/armada_output.c b/drivers/gpu/drm/armada/armada_output.c deleted file mode 100644 index 5a9823178291..000000000000 --- a/drivers/gpu/drm/armada/armada_output.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (C) 2012 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <drm/drmP.h> -#include <drm/drm_crtc_helper.h> -#include <drm/drm_edid.h> -#include <drm/drm_encoder_slave.h> -#include "armada_output.h" -#include "armada_drm.h" - -struct armada_connector { - struct drm_connector conn; - const struct armada_output_type *type; -}; - -#define drm_to_armada_conn(c) container_of(c, struct armada_connector, conn) - -struct drm_encoder *armada_drm_connector_encoder(struct drm_connector *conn) -{ - struct drm_encoder *enc = conn->encoder; - - return enc ? enc : drm_encoder_find(conn->dev, conn->encoder_ids[0]); -} - -static enum drm_connector_status armada_drm_connector_detect( - struct drm_connector *conn, bool force) -{ - struct armada_connector *dconn = drm_to_armada_conn(conn); - enum drm_connector_status status = connector_status_disconnected; - - if (dconn->type->detect) { - status = dconn->type->detect(conn, force); - } else { - struct drm_encoder *enc = armada_drm_connector_encoder(conn); - - if (enc) - status = encoder_helper_funcs(enc)->detect(enc, conn); - } - - return status; -} - -static void armada_drm_connector_destroy(struct drm_connector *conn) -{ - struct armada_connector *dconn = drm_to_armada_conn(conn); - - drm_connector_unregister(conn); - drm_connector_cleanup(conn); - kfree(dconn); -} - -static int armada_drm_connector_set_property(struct drm_connector *conn, - struct drm_property *property, uint64_t value) -{ - struct armada_connector *dconn = drm_to_armada_conn(conn); - - if (!dconn->type->set_property) - return -EINVAL; - - return dconn->type->set_property(conn, property, value); -} - -static const struct drm_connector_funcs armada_drm_conn_funcs = { - .dpms = drm_helper_connector_dpms, - .fill_modes = drm_helper_probe_single_connector_modes, - .detect = armada_drm_connector_detect, - .destroy = armada_drm_connector_destroy, - .set_property = armada_drm_connector_set_property, -}; - -/* Shouldn't this be a generic helper function? */ -int armada_drm_slave_encoder_mode_valid(struct drm_connector *conn, - struct drm_display_mode *mode) -{ - struct drm_encoder *encoder = armada_drm_connector_encoder(conn); - int valid = MODE_BAD; - - if (encoder) { - struct drm_encoder_slave *slave = to_encoder_slave(encoder); - - valid = slave->slave_funcs->mode_valid(encoder, mode); - } - return valid; -} - -int armada_drm_slave_encoder_set_property(struct drm_connector *conn, - struct drm_property *property, uint64_t value) -{ - struct drm_encoder *encoder = armada_drm_connector_encoder(conn); - int rc = -EINVAL; - - if (encoder) { - struct drm_encoder_slave *slave = to_encoder_slave(encoder); - - rc = slave->slave_funcs->set_property(encoder, conn, property, - value); - } - return rc; -} - -int armada_output_create(struct drm_device *dev, - const struct armada_output_type *type, const void *data) -{ - struct armada_connector *dconn; - int ret; - - dconn = kzalloc(sizeof(*dconn), GFP_KERNEL); - if (!dconn) - return -ENOMEM; - - dconn->type = type; - - ret = drm_connector_init(dev, &dconn->conn, &armada_drm_conn_funcs, - type->connector_type); - if (ret) { - DRM_ERROR("unable to init connector\n"); - goto err_destroy_dconn; - } - - ret = type->create(&dconn->conn, data); - if (ret) - goto err_conn; - - ret = drm_connector_register(&dconn->conn); - if (ret) - goto err_sysfs; - - return 0; - - err_sysfs: - if (dconn->conn.encoder) - dconn->conn.encoder->funcs->destroy(dconn->conn.encoder); - err_conn: - drm_connector_cleanup(&dconn->conn); - err_destroy_dconn: - kfree(dconn); - return ret; -} diff --git a/drivers/gpu/drm/armada/armada_output.h b/drivers/gpu/drm/armada/armada_output.h deleted file mode 100644 index f448785753e8..000000000000 --- a/drivers/gpu/drm/armada/armada_output.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (C) 2012 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ARMADA_CONNETOR_H -#define ARMADA_CONNETOR_H - -#define encoder_helper_funcs(encoder) \ - ((const struct drm_encoder_helper_funcs *)encoder->helper_private) - -struct armada_output_type { - int connector_type; - enum drm_connector_status (*detect)(struct drm_connector *, bool); - int (*create)(struct drm_connector *, const void *); - int (*set_property)(struct drm_connector *, struct drm_property *, - uint64_t); -}; - -struct drm_encoder *armada_drm_connector_encoder(struct drm_connector *conn); - -int armada_drm_slave_encoder_mode_valid(struct drm_connector *conn, - struct drm_display_mode *mode); - -int armada_drm_slave_encoder_set_property(struct drm_connector *conn, - struct drm_property *property, uint64_t value); - -int armada_output_create(struct drm_device *dev, - const struct armada_output_type *type, const void *data); - -#endif diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c index e939faba7fcc..5c22b380f8f3 100644 --- a/drivers/gpu/drm/armada/armada_overlay.c +++ b/drivers/gpu/drm/armada/armada_overlay.c @@ -16,7 +16,7 @@ #include <drm/armada_drm.h> #include "armada_ioctlP.h" -struct armada_plane_properties { +struct armada_ovl_plane_properties { uint32_t colorkey_yr; uint32_t colorkey_ug; uint32_t colorkey_vb; @@ -29,26 +29,25 @@ struct armada_plane_properties { uint32_t colorkey_mode; }; -struct armada_plane { - struct drm_plane base; - spinlock_t lock; +struct armada_ovl_plane { + struct armada_plane base; struct drm_framebuffer *old_fb; uint32_t src_hw; uint32_t dst_hw; uint32_t dst_yx; uint32_t ctrl0; struct { - struct armada_vbl_event update; + struct armada_plane_work work; struct armada_regs regs[13]; - wait_queue_head_t wait; } vbl; - struct armada_plane_properties prop; + struct armada_ovl_plane_properties prop; }; -#define drm_to_armada_plane(p) container_of(p, struct armada_plane, base) +#define drm_to_armada_ovl_plane(p) \ + container_of(p, struct armada_ovl_plane, base.base) static void -armada_ovl_update_attr(struct armada_plane_properties *prop, +armada_ovl_update_attr(struct armada_ovl_plane_properties *prop, struct armada_crtc *dcrtc) { writel_relaxed(prop->colorkey_yr, dcrtc->base + LCD_SPU_COLORKEY_Y); @@ -71,32 +70,34 @@ armada_ovl_update_attr(struct armada_plane_properties *prop, spin_unlock_irq(&dcrtc->irq_lock); } -/* === Plane support === */ -static void armada_plane_vbl(struct armada_crtc *dcrtc, void *data) +static void armada_ovl_retire_fb(struct armada_ovl_plane *dplane, + struct drm_framebuffer *fb) { - struct armada_plane *dplane = data; - struct drm_framebuffer *fb; + struct drm_framebuffer *old_fb; - armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); + old_fb = xchg(&dplane->old_fb, fb); - spin_lock(&dplane->lock); - fb = dplane->old_fb; - dplane->old_fb = NULL; - spin_unlock(&dplane->lock); + if (old_fb) + armada_drm_queue_unref_work(dplane->base.base.dev, old_fb); +} - if (fb) - armada_drm_queue_unref_work(dcrtc->crtc.dev, fb); +/* === Plane support === */ +static void armada_ovl_plane_work(struct armada_crtc *dcrtc, + struct armada_plane *plane, struct armada_plane_work *work) +{ + struct armada_ovl_plane *dplane = container_of(plane, struct armada_ovl_plane, base); - wake_up(&dplane->vbl.wait); + armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); + armada_ovl_retire_fb(dplane, NULL); } static int -armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, +armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, int crtc_x, int crtc_y, unsigned crtc_w, unsigned crtc_h, uint32_t src_x, uint32_t src_y, uint32_t src_w, uint32_t src_h) { - struct armada_plane *dplane = drm_to_armada_plane(plane); + struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); struct drm_rect src = { .x1 = src_x, @@ -160,9 +161,8 @@ armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, dcrtc->base + LCD_SPU_SRAM_PARA1); } - wait_event_timeout(dplane->vbl.wait, - list_empty(&dplane->vbl.update.node), - HZ/25); + if (armada_drm_plane_work_wait(&dplane->base, HZ / 25) == 0) + armada_drm_plane_work_cancel(dcrtc, &dplane->base); if (plane->fb != fb) { struct armada_gem_object *obj = drm_fb_obj(fb); @@ -175,17 +175,8 @@ armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, */ drm_framebuffer_reference(fb); - if (plane->fb) { - struct drm_framebuffer *older_fb; - - spin_lock_irq(&dplane->lock); - older_fb = dplane->old_fb; - dplane->old_fb = plane->fb; - spin_unlock_irq(&dplane->lock); - if (older_fb) - armada_drm_queue_unref_work(dcrtc->crtc.dev, - older_fb); - } + if (plane->fb) + armada_ovl_retire_fb(dplane, plane->fb); src_y = src.y1 >> 16; src_x = src.x1 >> 16; @@ -262,60 +253,50 @@ armada_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, } if (idx) { armada_reg_queue_end(dplane->vbl.regs, idx); - armada_drm_vbl_event_add(dcrtc, &dplane->vbl.update); + armada_drm_plane_work_queue(dcrtc, &dplane->base, + &dplane->vbl.work); } return 0; } -static int armada_plane_disable(struct drm_plane *plane) +static int armada_ovl_plane_disable(struct drm_plane *plane) { - struct armada_plane *dplane = drm_to_armada_plane(plane); + struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); struct drm_framebuffer *fb; struct armada_crtc *dcrtc; - if (!dplane->base.crtc) + if (!dplane->base.base.crtc) return 0; - dcrtc = drm_to_armada_crtc(dplane->base.crtc); - dcrtc->plane = NULL; - - spin_lock_irq(&dcrtc->irq_lock); - armada_drm_vbl_event_remove(dcrtc, &dplane->vbl.update); - armada_updatel(0, CFG_DMA_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); - dplane->ctrl0 = 0; - spin_unlock_irq(&dcrtc->irq_lock); + dcrtc = drm_to_armada_crtc(dplane->base.base.crtc); - /* Power down the Y/U/V FIFOs */ - armada_updatel(CFG_PDWN16x66 | CFG_PDWN32x66, 0, - dcrtc->base + LCD_SPU_SRAM_PARA1); + armada_drm_plane_work_cancel(dcrtc, &dplane->base); + armada_drm_crtc_plane_disable(dcrtc, plane); - if (plane->fb) - drm_framebuffer_unreference(plane->fb); + dcrtc->plane = NULL; + dplane->ctrl0 = 0; - spin_lock_irq(&dplane->lock); - fb = dplane->old_fb; - dplane->old_fb = NULL; - spin_unlock_irq(&dplane->lock); + fb = xchg(&dplane->old_fb, NULL); if (fb) drm_framebuffer_unreference(fb); return 0; } -static void armada_plane_destroy(struct drm_plane *plane) +static void armada_ovl_plane_destroy(struct drm_plane *plane) { - struct armada_plane *dplane = drm_to_armada_plane(plane); + struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); drm_plane_cleanup(plane); kfree(dplane); } -static int armada_plane_set_property(struct drm_plane *plane, +static int armada_ovl_plane_set_property(struct drm_plane *plane, struct drm_property *property, uint64_t val) { struct armada_private *priv = plane->dev->dev_private; - struct armada_plane *dplane = drm_to_armada_plane(plane); + struct armada_ovl_plane *dplane = drm_to_armada_ovl_plane(plane); bool update_attr = false; if (property == priv->colorkey_prop) { @@ -372,21 +353,21 @@ static int armada_plane_set_property(struct drm_plane *plane, update_attr = true; } - if (update_attr && dplane->base.crtc) + if (update_attr && dplane->base.base.crtc) armada_ovl_update_attr(&dplane->prop, - drm_to_armada_crtc(dplane->base.crtc)); + drm_to_armada_crtc(dplane->base.base.crtc)); return 0; } -static const struct drm_plane_funcs armada_plane_funcs = { - .update_plane = armada_plane_update, - .disable_plane = armada_plane_disable, - .destroy = armada_plane_destroy, - .set_property = armada_plane_set_property, +static const struct drm_plane_funcs armada_ovl_plane_funcs = { + .update_plane = armada_ovl_plane_update, + .disable_plane = armada_ovl_plane_disable, + .destroy = armada_ovl_plane_destroy, + .set_property = armada_ovl_plane_set_property, }; -static const uint32_t armada_formats[] = { +static const uint32_t armada_ovl_formats[] = { DRM_FORMAT_UYVY, DRM_FORMAT_YUYV, DRM_FORMAT_YUV420, @@ -456,7 +437,7 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) { struct armada_private *priv = dev->dev_private; struct drm_mode_object *mobj; - struct armada_plane *dplane; + struct armada_ovl_plane *dplane; int ret; ret = armada_overlay_create_properties(dev); @@ -467,13 +448,23 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) if (!dplane) return -ENOMEM; - spin_lock_init(&dplane->lock); - init_waitqueue_head(&dplane->vbl.wait); - armada_drm_vbl_event_init(&dplane->vbl.update, armada_plane_vbl, - dplane); + ret = armada_drm_plane_init(&dplane->base); + if (ret) { + kfree(dplane); + return ret; + } + + dplane->vbl.work.fn = armada_ovl_plane_work; - drm_plane_init(dev, &dplane->base, crtcs, &armada_plane_funcs, - armada_formats, ARRAY_SIZE(armada_formats), false); + ret = drm_universal_plane_init(dev, &dplane->base.base, crtcs, + &armada_ovl_plane_funcs, + armada_ovl_formats, + ARRAY_SIZE(armada_ovl_formats), + DRM_PLANE_TYPE_OVERLAY); + if (ret) { + kfree(dplane); + return ret; + } dplane->prop.colorkey_yr = 0xfefefe00; dplane->prop.colorkey_ug = 0x01010100; @@ -483,7 +474,7 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs) dplane->prop.contrast = 0x4000; dplane->prop.saturation = 0x4000; - mobj = &dplane->base.base; + mobj = &dplane->base.base.base; drm_object_attach_property(mobj, priv->colorkey_prop, 0x0101fe); drm_object_attach_property(mobj, priv->colorkey_min_prop, diff --git a/drivers/gpu/drm/armada/armada_slave.c b/drivers/gpu/drm/armada/armada_slave.c deleted file mode 100644 index 00d0facb42f3..000000000000 --- a/drivers/gpu/drm/armada/armada_slave.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2012 Russell King - * Rewritten from the dovefb driver, and Armada510 manuals. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#include <drm/drmP.h> -#include <drm/drm_crtc_helper.h> -#include <drm/drm_edid.h> -#include <drm/drm_encoder_slave.h> -#include "armada_drm.h" -#include "armada_output.h" -#include "armada_slave.h" - -static int armada_drm_slave_get_modes(struct drm_connector *conn) -{ - struct drm_encoder *enc = armada_drm_connector_encoder(conn); - int count = 0; - - if (enc) { - struct drm_encoder_slave *slave = to_encoder_slave(enc); - - count = slave->slave_funcs->get_modes(enc, conn); - } - - return count; -} - -static void armada_drm_slave_destroy(struct drm_encoder *enc) -{ - struct drm_encoder_slave *slave = to_encoder_slave(enc); - struct i2c_client *client = drm_i2c_encoder_get_client(enc); - - if (slave->slave_funcs) - slave->slave_funcs->destroy(enc); - if (client) - i2c_put_adapter(client->adapter); - - drm_encoder_cleanup(&slave->base); - kfree(slave); -} - -static const struct drm_encoder_funcs armada_drm_slave_encoder_funcs = { - .destroy = armada_drm_slave_destroy, -}; - -static const struct drm_connector_helper_funcs armada_drm_slave_helper_funcs = { - .get_modes = armada_drm_slave_get_modes, - .mode_valid = armada_drm_slave_encoder_mode_valid, - .best_encoder = armada_drm_connector_encoder, -}; - -static const struct drm_encoder_helper_funcs drm_slave_encoder_helpers = { - .dpms = drm_i2c_encoder_dpms, - .save = drm_i2c_encoder_save, - .restore = drm_i2c_encoder_restore, - .mode_fixup = drm_i2c_encoder_mode_fixup, - .prepare = drm_i2c_encoder_prepare, - .commit = drm_i2c_encoder_commit, - .mode_set = drm_i2c_encoder_mode_set, - .detect = drm_i2c_encoder_detect, -}; - -static int -armada_drm_conn_slave_create(struct drm_connector *conn, const void *data) -{ - const struct armada_drm_slave_config *config = data; - struct drm_encoder_slave *slave; - struct i2c_adapter *adap; - int ret; - - conn->interlace_allowed = config->interlace_allowed; - conn->doublescan_allowed = config->doublescan_allowed; - conn->polled = config->polled; - - drm_connector_helper_add(conn, &armada_drm_slave_helper_funcs); - - slave = kzalloc(sizeof(*slave), GFP_KERNEL); - if (!slave) - return -ENOMEM; - - slave->base.possible_crtcs = config->crtcs; - - adap = i2c_get_adapter(config->i2c_adapter_id); - if (!adap) { - kfree(slave); - return -EPROBE_DEFER; - } - - ret = drm_encoder_init(conn->dev, &slave->base, - &armada_drm_slave_encoder_funcs, - DRM_MODE_ENCODER_TMDS); - if (ret) { - DRM_ERROR("unable to init encoder\n"); - i2c_put_adapter(adap); - kfree(slave); - return ret; - } - - ret = drm_i2c_encoder_init(conn->dev, slave, adap, &config->info); - i2c_put_adapter(adap); - if (ret) { - DRM_ERROR("unable to init encoder slave\n"); - armada_drm_slave_destroy(&slave->base); - return ret; - } - - drm_encoder_helper_add(&slave->base, &drm_slave_encoder_helpers); - - ret = slave->slave_funcs->create_resources(&slave->base, conn); - if (ret) { - armada_drm_slave_destroy(&slave->base); - return ret; - } - - ret = drm_mode_connector_attach_encoder(conn, &slave->base); - if (ret) { - armada_drm_slave_destroy(&slave->base); - return ret; - } - - conn->encoder = &slave->base; - - return ret; -} - -static const struct armada_output_type armada_drm_conn_slave = { - .connector_type = DRM_MODE_CONNECTOR_HDMIA, - .create = armada_drm_conn_slave_create, - .set_property = armada_drm_slave_encoder_set_property, -}; - -int armada_drm_connector_slave_create(struct drm_device *dev, - const struct armada_drm_slave_config *config) -{ - return armada_output_create(dev, &armada_drm_conn_slave, config); -} diff --git a/drivers/gpu/drm/armada/armada_slave.h b/drivers/gpu/drm/armada/armada_slave.h deleted file mode 100644 index bf2374c96fc1..000000000000 --- a/drivers/gpu/drm/armada/armada_slave.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (C) 2012 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef ARMADA_SLAVE_H -#define ARMADA_SLAVE_H - -#include <linux/i2c.h> -#include <drm/drmP.h> - -struct armada_drm_slave_config { - int i2c_adapter_id; - uint32_t crtcs; - uint8_t polled; - bool interlace_allowed; - bool doublescan_allowed; - struct i2c_board_info info; -}; - -int armada_drm_connector_slave_create(struct drm_device *dev, - const struct armada_drm_slave_config *); - -#endif diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c index 8bc62ec407f9..244df0a440b7 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c @@ -656,7 +656,8 @@ static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev) regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr); } -static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev, int crtc) +static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev, + unsigned int pipe) { struct atmel_hlcdc_dc *dc = dev->dev_private; @@ -666,7 +667,8 @@ static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev, int crtc) return 0; } -static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev, int crtc) +static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev, + unsigned int pipe) { struct atmel_hlcdc_dc *dc = dev->dev_private; @@ -697,7 +699,7 @@ static struct drm_driver atmel_hlcdc_dc_driver = { .irq_preinstall = atmel_hlcdc_dc_irq_uninstall, .irq_postinstall = atmel_hlcdc_dc_irq_postinstall, .irq_uninstall = atmel_hlcdc_dc_irq_uninstall, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = atmel_hlcdc_dc_enable_vblank, .disable_vblank = atmel_hlcdc_dc_disable_vblank, .gem_free_object = drm_gem_cma_free_object, diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c index 36fda86b3518..d0299aed517e 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c @@ -633,7 +633,7 @@ static int atmel_hlcdc_plane_atomic_check(struct drm_plane *p, if (!state->bpp[i]) return -EINVAL; - switch (state->base.rotation & 0xf) { + switch (state->base.rotation & DRM_ROTATE_MASK) { case BIT(DRM_ROTATE_90): offset = ((y_offset + state->src_y + patched_src_w - 1) / ydiv) * fb->pitches[i]; diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 2de52a53a803..6dddd392aa42 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -11,6 +11,18 @@ config DRM_DW_HDMI tristate select DRM_KMS_HELPER +config DRM_DW_HDMI_AHB_AUDIO + tristate "Synopsis Designware AHB Audio interface" + depends on DRM_DW_HDMI && SND + select SND_PCM + select SND_PCM_ELD + select SND_PCM_IEC958 + help + Support the AHB Audio interface which is part of the Synopsis + Designware HDMI block. This is used in conjunction with + the i.MX6 HDMI driver. + + config DRM_NXP_PTN3460 tristate "NXP PTN3460 DP/LVDS bridge" depends on OF diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index e2eef1c2f4c3..d4e28beec30e 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -1,5 +1,6 @@ ccflags-y := -Iinclude/drm obj-$(CONFIG_DRM_DW_HDMI) += dw_hdmi.o +obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw_hdmi-ahb-audio.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o diff --git a/drivers/gpu/drm/bridge/dw_hdmi-ahb-audio.c b/drivers/gpu/drm/bridge/dw_hdmi-ahb-audio.c new file mode 100644 index 000000000000..59f630f1c61a --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_hdmi-ahb-audio.c @@ -0,0 +1,653 @@ +/* + * DesignWare HDMI audio driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Written and tested against the Designware HDMI Tx found in iMX6. + */ +#include <linux/io.h> +#include <linux/interrupt.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <drm/bridge/dw_hdmi.h> +#include <drm/drm_edid.h> + +#include <sound/asoundef.h> +#include <sound/core.h> +#include <sound/initval.h> +#include <sound/pcm.h> +#include <sound/pcm_drm_eld.h> +#include <sound/pcm_iec958.h> + +#include "dw_hdmi-audio.h" + +#define DRIVER_NAME "dw-hdmi-ahb-audio" + +/* Provide some bits rather than bit offsets */ +enum { + HDMI_AHB_DMA_CONF0_SW_FIFO_RST = BIT(7), + HDMI_AHB_DMA_CONF0_EN_HLOCK = BIT(3), + HDMI_AHB_DMA_START_START = BIT(0), + HDMI_AHB_DMA_STOP_STOP = BIT(0), + HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR = BIT(5), + HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST = BIT(4), + HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY = BIT(3), + HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE = BIT(2), + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL = BIT(1), + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0), + HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL = + HDMI_IH_MUTE_AHBDMAAUD_STAT0_ERROR | + HDMI_IH_MUTE_AHBDMAAUD_STAT0_LOST | + HDMI_IH_MUTE_AHBDMAAUD_STAT0_RETRY | + HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE | + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFFULL | + HDMI_IH_MUTE_AHBDMAAUD_STAT0_BUFFEMPTY, + HDMI_IH_AHBDMAAUD_STAT0_ERROR = BIT(5), + HDMI_IH_AHBDMAAUD_STAT0_LOST = BIT(4), + HDMI_IH_AHBDMAAUD_STAT0_RETRY = BIT(3), + HDMI_IH_AHBDMAAUD_STAT0_DONE = BIT(2), + HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL = BIT(1), + HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY = BIT(0), + HDMI_IH_AHBDMAAUD_STAT0_ALL = + HDMI_IH_AHBDMAAUD_STAT0_ERROR | + HDMI_IH_AHBDMAAUD_STAT0_LOST | + HDMI_IH_AHBDMAAUD_STAT0_RETRY | + HDMI_IH_AHBDMAAUD_STAT0_DONE | + HDMI_IH_AHBDMAAUD_STAT0_BUFFFULL | + HDMI_IH_AHBDMAAUD_STAT0_BUFFEMPTY, + HDMI_AHB_DMA_CONF0_INCR16 = 2 << 1, + HDMI_AHB_DMA_CONF0_INCR8 = 1 << 1, + HDMI_AHB_DMA_CONF0_INCR4 = 0, + HDMI_AHB_DMA_CONF0_BURST_MODE = BIT(0), + HDMI_AHB_DMA_MASK_DONE = BIT(7), + + HDMI_REVISION_ID = 0x0001, + HDMI_IH_AHBDMAAUD_STAT0 = 0x0109, + HDMI_IH_MUTE_AHBDMAAUD_STAT0 = 0x0189, + HDMI_FC_AUDICONF2 = 0x1027, + HDMI_FC_AUDSCONF = 0x1063, + HDMI_FC_AUDSCONF_LAYOUT1 = 1 << 0, + HDMI_FC_AUDSCONF_LAYOUT0 = 0 << 0, + HDMI_AHB_DMA_CONF0 = 0x3600, + HDMI_AHB_DMA_START = 0x3601, + HDMI_AHB_DMA_STOP = 0x3602, + HDMI_AHB_DMA_THRSLD = 0x3603, + HDMI_AHB_DMA_STRADDR0 = 0x3604, + HDMI_AHB_DMA_STPADDR0 = 0x3608, + HDMI_AHB_DMA_MASK = 0x3614, + HDMI_AHB_DMA_POL = 0x3615, + HDMI_AHB_DMA_CONF1 = 0x3616, + HDMI_AHB_DMA_BUFFPOL = 0x361a, +}; + +struct dw_hdmi_channel_conf { + u8 conf1; + u8 ca; +}; + +/* + * The default mapping of ALSA channels to HDMI channels and speaker + * allocation bits. Note that we can't do channel remapping here - + * channels must be in the same order. + * + * Mappings for alsa-lib pcm/surround*.conf files: + * + * Front Sur4.0 Sur4.1 Sur5.0 Sur5.1 Sur7.1 + * Channels 2 4 6 6 6 8 + * + * Our mapping from ALSA channel to CEA686D speaker name and HDMI channel: + * + * Number of ALSA channels + * ALSA Channel 2 3 4 5 6 7 8 + * 0 FL:0 = = = = = = + * 1 FR:1 = = = = = = + * 2 FC:3 RL:4 LFE:2 = = = + * 3 RR:5 RL:4 FC:3 = = + * 4 RR:5 RL:4 = = + * 5 RR:5 = = + * 6 RC:6 = + * 7 RLC/FRC RLC/FRC + */ +static struct dw_hdmi_channel_conf default_hdmi_channel_config[7] = { + { 0x03, 0x00 }, /* FL,FR */ + { 0x0b, 0x02 }, /* FL,FR,FC */ + { 0x33, 0x08 }, /* FL,FR,RL,RR */ + { 0x37, 0x09 }, /* FL,FR,LFE,RL,RR */ + { 0x3f, 0x0b }, /* FL,FR,LFE,FC,RL,RR */ + { 0x7f, 0x0f }, /* FL,FR,LFE,FC,RL,RR,RC */ + { 0xff, 0x13 }, /* FL,FR,LFE,FC,RL,RR,[FR]RC,[FR]LC */ +}; + +struct snd_dw_hdmi { + struct snd_card *card; + struct snd_pcm *pcm; + spinlock_t lock; + struct dw_hdmi_audio_data data; + struct snd_pcm_substream *substream; + void (*reformat)(struct snd_dw_hdmi *, size_t, size_t); + void *buf_src; + void *buf_dst; + dma_addr_t buf_addr; + unsigned buf_offset; + unsigned buf_period; + unsigned buf_size; + unsigned channels; + u8 revision; + u8 iec_offset; + u8 cs[192][8]; +}; + +static void dw_hdmi_writel(u32 val, void __iomem *ptr) +{ + writeb_relaxed(val, ptr); + writeb_relaxed(val >> 8, ptr + 1); + writeb_relaxed(val >> 16, ptr + 2); + writeb_relaxed(val >> 24, ptr + 3); +} + +/* + * Convert to hardware format: The userspace buffer contains IEC958 samples, + * with the PCUV bits in bits 31..28 and audio samples in bits 27..4. We + * need these to be in bits 27..24, with the IEC B bit in bit 28, and audio + * samples in 23..0. + * + * Default preamble in bits 3..0: 8 = block start, 4 = even 2 = odd + * + * Ideally, we could do with having the data properly formatted in userspace. + */ +static void dw_hdmi_reformat_iec958(struct snd_dw_hdmi *dw, + size_t offset, size_t bytes) +{ + u32 *src = dw->buf_src + offset; + u32 *dst = dw->buf_dst + offset; + u32 *end = dw->buf_src + offset + bytes; + + do { + u32 b, sample = *src++; + + b = (sample & 8) << (28 - 3); + + sample >>= 4; + + *dst++ = sample | b; + } while (src < end); +} + +static u32 parity(u32 sample) +{ + sample ^= sample >> 16; + sample ^= sample >> 8; + sample ^= sample >> 4; + sample ^= sample >> 2; + sample ^= sample >> 1; + return (sample & 1) << 27; +} + +static void dw_hdmi_reformat_s24(struct snd_dw_hdmi *dw, + size_t offset, size_t bytes) +{ + u32 *src = dw->buf_src + offset; + u32 *dst = dw->buf_dst + offset; + u32 *end = dw->buf_src + offset + bytes; + + do { + unsigned i; + u8 *cs; + + cs = dw->cs[dw->iec_offset++]; + if (dw->iec_offset >= 192) + dw->iec_offset = 0; + + i = dw->channels; + do { + u32 sample = *src++; + + sample &= ~0xff000000; + sample |= *cs++ << 24; + sample |= parity(sample & ~0xf8000000); + + *dst++ = sample; + } while (--i); + } while (src < end); +} + +static void dw_hdmi_create_cs(struct snd_dw_hdmi *dw, + struct snd_pcm_runtime *runtime) +{ + u8 cs[4]; + unsigned ch, i, j; + + snd_pcm_create_iec958_consumer(runtime, cs, sizeof(cs)); + + memset(dw->cs, 0, sizeof(dw->cs)); + + for (ch = 0; ch < 8; ch++) { + cs[2] &= ~IEC958_AES2_CON_CHANNEL; + cs[2] |= (ch + 1) << 4; + + for (i = 0; i < ARRAY_SIZE(cs); i++) { + unsigned c = cs[i]; + + for (j = 0; j < 8; j++, c >>= 1) + dw->cs[i * 8 + j][ch] = (c & 1) << 2; + } + } + dw->cs[0][0] |= BIT(4); +} + +static void dw_hdmi_start_dma(struct snd_dw_hdmi *dw) +{ + void __iomem *base = dw->data.base; + unsigned offset = dw->buf_offset; + unsigned period = dw->buf_period; + u32 start, stop; + + dw->reformat(dw, offset, period); + + /* Clear all irqs before enabling irqs and starting DMA */ + writeb_relaxed(HDMI_IH_AHBDMAAUD_STAT0_ALL, + base + HDMI_IH_AHBDMAAUD_STAT0); + + start = dw->buf_addr + offset; + stop = start + period - 1; + + /* Setup the hardware start/stop addresses */ + dw_hdmi_writel(start, base + HDMI_AHB_DMA_STRADDR0); + dw_hdmi_writel(stop, base + HDMI_AHB_DMA_STPADDR0); + + writeb_relaxed((u8)~HDMI_AHB_DMA_MASK_DONE, base + HDMI_AHB_DMA_MASK); + writeb(HDMI_AHB_DMA_START_START, base + HDMI_AHB_DMA_START); + + offset += period; + if (offset >= dw->buf_size) + offset = 0; + dw->buf_offset = offset; +} + +static void dw_hdmi_stop_dma(struct snd_dw_hdmi *dw) +{ + /* Disable interrupts before disabling DMA */ + writeb_relaxed(~0, dw->data.base + HDMI_AHB_DMA_MASK); + writeb_relaxed(HDMI_AHB_DMA_STOP_STOP, dw->data.base + HDMI_AHB_DMA_STOP); +} + +static irqreturn_t snd_dw_hdmi_irq(int irq, void *data) +{ + struct snd_dw_hdmi *dw = data; + struct snd_pcm_substream *substream; + unsigned stat; + + stat = readb_relaxed(dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); + if (!stat) + return IRQ_NONE; + + writeb_relaxed(stat, dw->data.base + HDMI_IH_AHBDMAAUD_STAT0); + + substream = dw->substream; + if (stat & HDMI_IH_AHBDMAAUD_STAT0_DONE && substream) { + snd_pcm_period_elapsed(substream); + + spin_lock(&dw->lock); + if (dw->substream) + dw_hdmi_start_dma(dw); + spin_unlock(&dw->lock); + } + + return IRQ_HANDLED; +} + +static struct snd_pcm_hardware dw_hdmi_hw = { + .info = SNDRV_PCM_INFO_INTERLEAVED | + SNDRV_PCM_INFO_BLOCK_TRANSFER | + SNDRV_PCM_INFO_MMAP | + SNDRV_PCM_INFO_MMAP_VALID, + .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE | + SNDRV_PCM_FMTBIT_S24_LE, + .rates = SNDRV_PCM_RATE_32000 | + SNDRV_PCM_RATE_44100 | + SNDRV_PCM_RATE_48000 | + SNDRV_PCM_RATE_88200 | + SNDRV_PCM_RATE_96000 | + SNDRV_PCM_RATE_176400 | + SNDRV_PCM_RATE_192000, + .channels_min = 2, + .channels_max = 8, + .buffer_bytes_max = 1024 * 1024, + .period_bytes_min = 256, + .period_bytes_max = 8192, /* ERR004323: must limit to 8k */ + .periods_min = 2, + .periods_max = 16, + .fifo_size = 0, +}; + +static int dw_hdmi_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_dw_hdmi *dw = substream->private_data; + void __iomem *base = dw->data.base; + int ret; + + runtime->hw = dw_hdmi_hw; + + ret = snd_pcm_hw_constraint_eld(runtime, dw->data.eld); + if (ret < 0) + return ret; + + ret = snd_pcm_limit_hw_rates(runtime); + if (ret < 0) + return ret; + + ret = snd_pcm_hw_constraint_integer(runtime, + SNDRV_PCM_HW_PARAM_PERIODS); + if (ret < 0) + return ret; + + /* Limit the buffer size to the size of the preallocated buffer */ + ret = snd_pcm_hw_constraint_minmax(runtime, + SNDRV_PCM_HW_PARAM_BUFFER_SIZE, + 0, substream->dma_buffer.bytes); + if (ret < 0) + return ret; + + /* Clear FIFO */ + writeb_relaxed(HDMI_AHB_DMA_CONF0_SW_FIFO_RST, + base + HDMI_AHB_DMA_CONF0); + + /* Configure interrupt polarities */ + writeb_relaxed(~0, base + HDMI_AHB_DMA_POL); + writeb_relaxed(~0, base + HDMI_AHB_DMA_BUFFPOL); + + /* Keep interrupts masked, and clear any pending */ + writeb_relaxed(~0, base + HDMI_AHB_DMA_MASK); + writeb_relaxed(~0, base + HDMI_IH_AHBDMAAUD_STAT0); + + ret = request_irq(dw->data.irq, snd_dw_hdmi_irq, IRQF_SHARED, + "dw-hdmi-audio", dw); + if (ret) + return ret; + + /* Un-mute done interrupt */ + writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL & + ~HDMI_IH_MUTE_AHBDMAAUD_STAT0_DONE, + base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); + + return 0; +} + +static int dw_hdmi_close(struct snd_pcm_substream *substream) +{ + struct snd_dw_hdmi *dw = substream->private_data; + + /* Mute all interrupts */ + writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, + dw->data.base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); + + free_irq(dw->data.irq, dw); + + return 0; +} + +static int dw_hdmi_hw_free(struct snd_pcm_substream *substream) +{ + return snd_pcm_lib_free_vmalloc_buffer(substream); +} + +static int dw_hdmi_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + /* Allocate the PCM runtime buffer, which is exposed to userspace. */ + return snd_pcm_lib_alloc_vmalloc_buffer(substream, + params_buffer_bytes(params)); +} + +static int dw_hdmi_prepare(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_dw_hdmi *dw = substream->private_data; + u8 threshold, conf0, conf1, layout, ca; + + /* Setup as per 3.0.5 FSL 4.1.0 BSP */ + switch (dw->revision) { + case 0x0a: + conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE | + HDMI_AHB_DMA_CONF0_INCR4; + if (runtime->channels == 2) + threshold = 126; + else + threshold = 124; + break; + case 0x1a: + conf0 = HDMI_AHB_DMA_CONF0_BURST_MODE | + HDMI_AHB_DMA_CONF0_INCR8; + threshold = 128; + break; + default: + /* NOTREACHED */ + return -EINVAL; + } + + dw_hdmi_set_sample_rate(dw->data.hdmi, runtime->rate); + + /* Minimum number of bytes in the fifo. */ + runtime->hw.fifo_size = threshold * 32; + + conf0 |= HDMI_AHB_DMA_CONF0_EN_HLOCK; + conf1 = default_hdmi_channel_config[runtime->channels - 2].conf1; + ca = default_hdmi_channel_config[runtime->channels - 2].ca; + + /* + * For >2 channel PCM audio, we need to select layout 1 + * and set an appropriate channel map. + */ + if (runtime->channels > 2) + layout = HDMI_FC_AUDSCONF_LAYOUT1; + else + layout = HDMI_FC_AUDSCONF_LAYOUT0; + + writeb_relaxed(threshold, dw->data.base + HDMI_AHB_DMA_THRSLD); + writeb_relaxed(conf0, dw->data.base + HDMI_AHB_DMA_CONF0); + writeb_relaxed(conf1, dw->data.base + HDMI_AHB_DMA_CONF1); + writeb_relaxed(layout, dw->data.base + HDMI_FC_AUDSCONF); + writeb_relaxed(ca, dw->data.base + HDMI_FC_AUDICONF2); + + switch (runtime->format) { + case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: + dw->reformat = dw_hdmi_reformat_iec958; + break; + case SNDRV_PCM_FORMAT_S24_LE: + dw_hdmi_create_cs(dw, runtime); + dw->reformat = dw_hdmi_reformat_s24; + break; + } + dw->iec_offset = 0; + dw->channels = runtime->channels; + dw->buf_src = runtime->dma_area; + dw->buf_dst = substream->dma_buffer.area; + dw->buf_addr = substream->dma_buffer.addr; + dw->buf_period = snd_pcm_lib_period_bytes(substream); + dw->buf_size = snd_pcm_lib_buffer_bytes(substream); + + return 0; +} + +static int dw_hdmi_trigger(struct snd_pcm_substream *substream, int cmd) +{ + struct snd_dw_hdmi *dw = substream->private_data; + unsigned long flags; + int ret = 0; + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: + spin_lock_irqsave(&dw->lock, flags); + dw->buf_offset = 0; + dw->substream = substream; + dw_hdmi_start_dma(dw); + dw_hdmi_audio_enable(dw->data.hdmi); + spin_unlock_irqrestore(&dw->lock, flags); + substream->runtime->delay = substream->runtime->period_size; + break; + + case SNDRV_PCM_TRIGGER_STOP: + spin_lock_irqsave(&dw->lock, flags); + dw->substream = NULL; + dw_hdmi_stop_dma(dw); + dw_hdmi_audio_disable(dw->data.hdmi); + spin_unlock_irqrestore(&dw->lock, flags); + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static snd_pcm_uframes_t dw_hdmi_pointer(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct snd_dw_hdmi *dw = substream->private_data; + + /* + * We are unable to report the exact hardware position as + * reading the 32-bit DMA position using 8-bit reads is racy. + */ + return bytes_to_frames(runtime, dw->buf_offset); +} + +static struct snd_pcm_ops snd_dw_hdmi_ops = { + .open = dw_hdmi_open, + .close = dw_hdmi_close, + .ioctl = snd_pcm_lib_ioctl, + .hw_params = dw_hdmi_hw_params, + .hw_free = dw_hdmi_hw_free, + .prepare = dw_hdmi_prepare, + .trigger = dw_hdmi_trigger, + .pointer = dw_hdmi_pointer, + .page = snd_pcm_lib_get_vmalloc_page, +}; + +static int snd_dw_hdmi_probe(struct platform_device *pdev) +{ + const struct dw_hdmi_audio_data *data = pdev->dev.platform_data; + struct device *dev = pdev->dev.parent; + struct snd_dw_hdmi *dw; + struct snd_card *card; + struct snd_pcm *pcm; + unsigned revision; + int ret; + + writeb_relaxed(HDMI_IH_MUTE_AHBDMAAUD_STAT0_ALL, + data->base + HDMI_IH_MUTE_AHBDMAAUD_STAT0); + revision = readb_relaxed(data->base + HDMI_REVISION_ID); + if (revision != 0x0a && revision != 0x1a) { + dev_err(dev, "dw-hdmi-audio: unknown revision 0x%02x\n", + revision); + return -ENXIO; + } + + ret = snd_card_new(dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1, + THIS_MODULE, sizeof(struct snd_dw_hdmi), &card); + if (ret < 0) + return ret; + + strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver)); + strlcpy(card->shortname, "DW-HDMI", sizeof(card->shortname)); + snprintf(card->longname, sizeof(card->longname), + "%s rev 0x%02x, irq %d", card->shortname, revision, + data->irq); + + dw = card->private_data; + dw->card = card; + dw->data = *data; + dw->revision = revision; + + spin_lock_init(&dw->lock); + + ret = snd_pcm_new(card, "DW HDMI", 0, 1, 0, &pcm); + if (ret < 0) + goto err; + + dw->pcm = pcm; + pcm->private_data = dw; + strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name)); + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dw_hdmi_ops); + + /* + * To support 8-channel 96kHz audio reliably, we need 512k + * to satisfy alsa with our restricted period (ERR004323). + */ + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, + dev, 128 * 1024, 1024 * 1024); + + ret = snd_card_register(card); + if (ret < 0) + goto err; + + platform_set_drvdata(pdev, dw); + + return 0; + +err: + snd_card_free(card); + return ret; +} + +static int snd_dw_hdmi_remove(struct platform_device *pdev) +{ + struct snd_dw_hdmi *dw = platform_get_drvdata(pdev); + + snd_card_free(dw->card); + + return 0; +} + +#if defined(CONFIG_PM_SLEEP) && defined(IS_NOT_BROKEN) +/* + * This code is fine, but requires implementation in the dw_hdmi_trigger() + * method which is currently missing as I have no way to test this. + */ +static int snd_dw_hdmi_suspend(struct device *dev) +{ + struct snd_dw_hdmi *dw = dev_get_drvdata(dev); + + snd_power_change_state(dw->card, SNDRV_CTL_POWER_D3cold); + snd_pcm_suspend_all(dw->pcm); + + return 0; +} + +static int snd_dw_hdmi_resume(struct device *dev) +{ + struct snd_dw_hdmi *dw = dev_get_drvdata(dev); + + snd_power_change_state(dw->card, SNDRV_CTL_POWER_D0); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(snd_dw_hdmi_pm, snd_dw_hdmi_suspend, + snd_dw_hdmi_resume); +#define PM_OPS &snd_dw_hdmi_pm +#else +#define PM_OPS NULL +#endif + +static struct platform_driver snd_dw_hdmi_driver = { + .probe = snd_dw_hdmi_probe, + .remove = snd_dw_hdmi_remove, + .driver = { + .name = DRIVER_NAME, + .owner = THIS_MODULE, + .pm = PM_OPS, + }, +}; + +module_platform_driver(snd_dw_hdmi_driver); + +MODULE_AUTHOR("Russell King <rmk+kernel@arm.linux.org.uk>"); +MODULE_DESCRIPTION("Synopsis Designware HDMI AHB ALSA interface"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRIVER_NAME); diff --git a/drivers/gpu/drm/bridge/dw_hdmi-audio.h b/drivers/gpu/drm/bridge/dw_hdmi-audio.h new file mode 100644 index 000000000000..91f631beecc7 --- /dev/null +++ b/drivers/gpu/drm/bridge/dw_hdmi-audio.h @@ -0,0 +1,14 @@ +#ifndef DW_HDMI_AUDIO_H +#define DW_HDMI_AUDIO_H + +struct dw_hdmi; + +struct dw_hdmi_audio_data { + phys_addr_t phys; + void __iomem *base; + int irq; + struct dw_hdmi *hdmi; + u8 *eld; +}; + +#endif diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c b/drivers/gpu/drm/bridge/dw_hdmi.c index 0083d4e7e7e2..56de9f1c95fc 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.c +++ b/drivers/gpu/drm/bridge/dw_hdmi.c @@ -28,6 +28,7 @@ #include <drm/bridge/dw_hdmi.h> #include "dw_hdmi.h" +#include "dw_hdmi-audio.h" #define HDMI_EDID_LEN 512 @@ -104,6 +105,7 @@ struct dw_hdmi { struct drm_encoder *encoder; struct drm_bridge *bridge; + struct platform_device *audio; enum dw_hdmi_devtype dev_type; struct device *dev; struct clk *isfr_clk; @@ -126,7 +128,11 @@ struct dw_hdmi { bool sink_has_audio; struct mutex mutex; /* for state below and previous_mode */ + enum drm_connector_force force; /* mutex-protected force state */ bool disabled; /* DRM has disabled our bridge */ + bool bridge_is_on; /* indicates the bridge is on */ + bool rxsense; /* rxsense state */ + u8 phy_mask; /* desired phy int mask settings */ spinlock_t audio_lock; struct mutex audio_mutex; @@ -134,12 +140,19 @@ struct dw_hdmi { unsigned int audio_cts; unsigned int audio_n; bool audio_enable; - int ratio; void (*write)(struct dw_hdmi *hdmi, u8 val, int offset); u8 (*read)(struct dw_hdmi *hdmi, int offset); }; +#define HDMI_IH_PHY_STAT0_RX_SENSE \ + (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ + HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) + +#define HDMI_PHY_RX_SENSE \ + (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ + HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) + static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset) { writel(val, hdmi->regs + (offset << 2)); @@ -203,61 +216,53 @@ static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); } -static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk, - unsigned int ratio) +static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) { unsigned int n = (128 * freq) / 1000; + unsigned int mult = 1; + + while (freq > 48000) { + mult *= 2; + freq /= 2; + } switch (freq) { case 32000: - if (pixel_clk == 25170000) - n = (ratio == 150) ? 9152 : 4576; - else if (pixel_clk == 27020000) - n = (ratio == 150) ? 8192 : 4096; - else if (pixel_clk == 74170000 || pixel_clk == 148350000) + if (pixel_clk == 25175000) + n = 4576; + else if (pixel_clk == 27027000) + n = 4096; + else if (pixel_clk == 74176000 || pixel_clk == 148352000) n = 11648; else n = 4096; + n *= mult; break; case 44100: - if (pixel_clk == 25170000) + if (pixel_clk == 25175000) n = 7007; - else if (pixel_clk == 74170000) + else if (pixel_clk == 74176000) n = 17836; - else if (pixel_clk == 148350000) - n = (ratio == 150) ? 17836 : 8918; + else if (pixel_clk == 148352000) + n = 8918; else n = 6272; + n *= mult; break; case 48000: - if (pixel_clk == 25170000) - n = (ratio == 150) ? 9152 : 6864; - else if (pixel_clk == 27020000) - n = (ratio == 150) ? 8192 : 6144; - else if (pixel_clk == 74170000) + if (pixel_clk == 25175000) + n = 6864; + else if (pixel_clk == 27027000) + n = 6144; + else if (pixel_clk == 74176000) n = 11648; - else if (pixel_clk == 148350000) - n = (ratio == 150) ? 11648 : 5824; + else if (pixel_clk == 148352000) + n = 5824; else n = 6144; - break; - - case 88200: - n = hdmi_compute_n(44100, pixel_clk, ratio) * 2; - break; - - case 96000: - n = hdmi_compute_n(48000, pixel_clk, ratio) * 2; - break; - - case 176400: - n = hdmi_compute_n(44100, pixel_clk, ratio) * 4; - break; - - case 192000: - n = hdmi_compute_n(48000, pixel_clk, ratio) * 4; + n *= mult; break; default: @@ -267,93 +272,29 @@ static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk, return n; } -static unsigned int hdmi_compute_cts(unsigned int freq, unsigned long pixel_clk, - unsigned int ratio) -{ - unsigned int cts = 0; - - pr_debug("%s: freq: %d pixel_clk: %ld ratio: %d\n", __func__, freq, - pixel_clk, ratio); - - switch (freq) { - case 32000: - if (pixel_clk == 297000000) { - cts = 222750; - break; - } - case 48000: - case 96000: - case 192000: - switch (pixel_clk) { - case 25200000: - case 27000000: - case 54000000: - case 74250000: - case 148500000: - cts = pixel_clk / 1000; - break; - case 297000000: - cts = 247500; - break; - /* - * All other TMDS clocks are not supported by - * DWC_hdmi_tx. The TMDS clocks divided or - * multiplied by 1,001 coefficients are not - * supported. - */ - default: - break; - } - break; - case 44100: - case 88200: - case 176400: - switch (pixel_clk) { - case 25200000: - cts = 28000; - break; - case 27000000: - cts = 30000; - break; - case 54000000: - cts = 60000; - break; - case 74250000: - cts = 82500; - break; - case 148500000: - cts = 165000; - break; - case 297000000: - cts = 247500; - break; - default: - break; - } - break; - default: - break; - } - if (ratio == 100) - return cts; - return (cts * ratio) / 100; -} - static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, - unsigned long pixel_clk, unsigned int sample_rate, unsigned int ratio) + unsigned long pixel_clk, unsigned int sample_rate) { + unsigned long ftdms = pixel_clk; unsigned int n, cts; + u64 tmp; - n = hdmi_compute_n(sample_rate, pixel_clk, ratio); - cts = hdmi_compute_cts(sample_rate, pixel_clk, ratio); - if (!cts) { - dev_err(hdmi->dev, - "%s: pixel clock/sample rate not supported: %luMHz / %ukHz\n", - __func__, pixel_clk, sample_rate); - } + n = hdmi_compute_n(sample_rate, pixel_clk); + + /* + * Compute the CTS value from the N value. Note that CTS and N + * can be up to 20 bits in total, so we need 64-bit math. Also + * note that our TDMS clock is not fully accurate; it is accurate + * to kHz. This can introduce an unnecessary remainder in the + * calculation below, so we don't try to warn about that. + */ + tmp = (u64)ftdms * n; + do_div(tmp, 128 * sample_rate); + cts = tmp; - dev_dbg(hdmi->dev, "%s: samplerate=%ukHz ratio=%d pixelclk=%luMHz N=%d cts=%d\n", - __func__, sample_rate, ratio, pixel_clk, n, cts); + dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", + __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, + n, cts); spin_lock_irq(&hdmi->audio_lock); hdmi->audio_n = n; @@ -365,8 +306,7 @@ static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) { mutex_lock(&hdmi->audio_mutex); - hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate, - hdmi->ratio); + hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); mutex_unlock(&hdmi->audio_mutex); } @@ -374,7 +314,7 @@ static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) { mutex_lock(&hdmi->audio_mutex); hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, - hdmi->sample_rate, hdmi->ratio); + hdmi->sample_rate); mutex_unlock(&hdmi->audio_mutex); } @@ -383,7 +323,7 @@ void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) mutex_lock(&hdmi->audio_mutex); hdmi->sample_rate = rate; hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, - hdmi->sample_rate, hdmi->ratio); + hdmi->sample_rate); mutex_unlock(&hdmi->audio_mutex); } EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); @@ -1063,6 +1003,7 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, u8 inv_val; struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; + unsigned int vdisplay; vmode->mpixelclock = mode->clock * 1000; @@ -1102,13 +1043,29 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); + vdisplay = mode->vdisplay; + vblank = mode->vtotal - mode->vdisplay; + v_de_vs = mode->vsync_start - mode->vdisplay; + vsync_len = mode->vsync_end - mode->vsync_start; + + /* + * When we're setting an interlaced mode, we need + * to adjust the vertical timing to suit. + */ + if (mode->flags & DRM_MODE_FLAG_INTERLACE) { + vdisplay /= 2; + vblank /= 2; + v_de_vs /= 2; + vsync_len /= 2; + } + /* Set up horizontal active pixel width */ hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); /* Set up vertical active lines */ - hdmi_writeb(hdmi, mode->vdisplay >> 8, HDMI_FC_INVACTV1); - hdmi_writeb(hdmi, mode->vdisplay, HDMI_FC_INVACTV0); + hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); + hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); /* Set up horizontal blanking pixel region width */ hblank = mode->htotal - mode->hdisplay; @@ -1116,7 +1073,6 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); /* Set up vertical blanking pixel region width */ - vblank = mode->vtotal - mode->vdisplay; hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); /* Set up HSYNC active edge delay width (in pixel clks) */ @@ -1125,7 +1081,6 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); /* Set up VSYNC active edge delay (in lines) */ - v_de_vs = mode->vsync_start - mode->vdisplay; hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); /* Set up HSYNC active pulse width (in pixel clks) */ @@ -1134,7 +1089,6 @@ static void hdmi_av_composer(struct dw_hdmi *hdmi, hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); /* Set up VSYNC active edge delay (in lines) */ - vsync_len = mode->vsync_end - mode->vsync_start; hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); } @@ -1302,10 +1256,11 @@ static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi) HDMI_PHY_I2CM_CTLINT_ADDR); /* enable cable hot plug irq */ - hdmi_writeb(hdmi, (u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); + hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); /* Clear Hotplug interrupts */ - hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, + HDMI_IH_PHY_STAT0); return 0; } @@ -1364,12 +1319,61 @@ static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) static void dw_hdmi_poweron(struct dw_hdmi *hdmi) { + hdmi->bridge_is_on = true; dw_hdmi_setup(hdmi, &hdmi->previous_mode); } static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) { dw_hdmi_phy_disable(hdmi); + hdmi->bridge_is_on = false; +} + +static void dw_hdmi_update_power(struct dw_hdmi *hdmi) +{ + int force = hdmi->force; + + if (hdmi->disabled) { + force = DRM_FORCE_OFF; + } else if (force == DRM_FORCE_UNSPECIFIED) { + if (hdmi->rxsense) + force = DRM_FORCE_ON; + else + force = DRM_FORCE_OFF; + } + + if (force == DRM_FORCE_OFF) { + if (hdmi->bridge_is_on) + dw_hdmi_poweroff(hdmi); + } else { + if (!hdmi->bridge_is_on) + dw_hdmi_poweron(hdmi); + } +} + +/* + * Adjust the detection of RXSENSE according to whether we have a forced + * connection mode enabled, or whether we have been disabled. There is + * no point processing RXSENSE interrupts if we have a forced connection + * state, or DRM has us disabled. + * + * We also disable rxsense interrupts when we think we're disconnected + * to avoid floating TDMS signals giving false rxsense interrupts. + * + * Note: we still need to listen for HPD interrupts even when DRM has us + * disabled so that we can detect a connect event. + */ +static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) +{ + u8 old_mask = hdmi->phy_mask; + + if (hdmi->force || hdmi->disabled || !hdmi->rxsense) + hdmi->phy_mask |= HDMI_PHY_RX_SENSE; + else + hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; + + if (old_mask != hdmi->phy_mask) + hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); } static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, @@ -1399,7 +1403,8 @@ static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) mutex_lock(&hdmi->mutex); hdmi->disabled = true; - dw_hdmi_poweroff(hdmi); + dw_hdmi_update_power(hdmi); + dw_hdmi_update_phy_mask(hdmi); mutex_unlock(&hdmi->mutex); } @@ -1408,8 +1413,9 @@ static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) struct dw_hdmi *hdmi = bridge->driver_private; mutex_lock(&hdmi->mutex); - dw_hdmi_poweron(hdmi); hdmi->disabled = false; + dw_hdmi_update_power(hdmi); + dw_hdmi_update_phy_mask(hdmi); mutex_unlock(&hdmi->mutex); } @@ -1424,6 +1430,12 @@ dw_hdmi_connector_detect(struct drm_connector *connector, bool force) struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, connector); + mutex_lock(&hdmi->mutex); + hdmi->force = DRM_FORCE_UNSPECIFIED; + dw_hdmi_update_power(hdmi); + dw_hdmi_update_phy_mask(hdmi); + mutex_unlock(&hdmi->mutex); + return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? connector_status_connected : connector_status_disconnected; } @@ -1447,6 +1459,8 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) hdmi->sink_has_audio = drm_detect_monitor_audio(edid); drm_mode_connector_update_edid_property(connector, edid); ret = drm_add_edid_modes(connector, edid); + /* Store the ELD */ + drm_edid_to_eld(connector, edid); kfree(edid); } else { dev_dbg(hdmi->dev, "failed to get edid\n"); @@ -1488,11 +1502,24 @@ static void dw_hdmi_connector_destroy(struct drm_connector *connector) drm_connector_cleanup(connector); } +static void dw_hdmi_connector_force(struct drm_connector *connector) +{ + struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, + connector); + + mutex_lock(&hdmi->mutex); + hdmi->force = connector->force; + dw_hdmi_update_power(hdmi); + dw_hdmi_update_phy_mask(hdmi); + mutex_unlock(&hdmi->mutex); +} + static struct drm_connector_funcs dw_hdmi_connector_funcs = { .dpms = drm_helper_connector_dpms, .fill_modes = drm_helper_probe_single_connector_modes, .detect = dw_hdmi_connector_detect, .destroy = dw_hdmi_connector_destroy, + .force = dw_hdmi_connector_force, }; static struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { @@ -1525,33 +1552,69 @@ static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) { struct dw_hdmi *hdmi = dev_id; - u8 intr_stat; - u8 phy_int_pol; + u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); - phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); + phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); + + phy_pol_mask = 0; + if (intr_stat & HDMI_IH_PHY_STAT0_HPD) + phy_pol_mask |= HDMI_PHY_HPD; + if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) + phy_pol_mask |= HDMI_PHY_RX_SENSE0; + if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) + phy_pol_mask |= HDMI_PHY_RX_SENSE1; + if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) + phy_pol_mask |= HDMI_PHY_RX_SENSE2; + if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) + phy_pol_mask |= HDMI_PHY_RX_SENSE3; + + if (phy_pol_mask) + hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); - if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { - hdmi_modb(hdmi, ~phy_int_pol, HDMI_PHY_HPD, HDMI_PHY_POL0); + /* + * RX sense tells us whether the TDMS transmitters are detecting + * load - in other words, there's something listening on the + * other end of the link. Use this to decide whether we should + * power on the phy as HPD may be toggled by the sink to merely + * ask the source to re-read the EDID. + */ + if (intr_stat & + (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { mutex_lock(&hdmi->mutex); - if (phy_int_pol & HDMI_PHY_HPD) { - dev_dbg(hdmi->dev, "EVENT=plugin\n"); - - if (!hdmi->disabled) - dw_hdmi_poweron(hdmi); - } else { - dev_dbg(hdmi->dev, "EVENT=plugout\n"); - - if (!hdmi->disabled) - dw_hdmi_poweroff(hdmi); + if (!hdmi->disabled && !hdmi->force) { + /* + * If the RX sense status indicates we're disconnected, + * clear the software rxsense status. + */ + if (!(phy_stat & HDMI_PHY_RX_SENSE)) + hdmi->rxsense = false; + + /* + * Only set the software rxsense status when both + * rxsense and hpd indicates we're connected. + * This avoids what seems to be bad behaviour in + * at least iMX6S versions of the phy. + */ + if (phy_stat & HDMI_PHY_HPD) + hdmi->rxsense = true; + + dw_hdmi_update_power(hdmi); + dw_hdmi_update_phy_mask(hdmi); } mutex_unlock(&hdmi->mutex); + } + + if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { + dev_dbg(hdmi->dev, "EVENT=%s\n", + phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); drm_helper_hpd_irq_event(hdmi->bridge->dev); } hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); - hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); + hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), + HDMI_IH_MUTE_PHY_STAT0); return IRQ_HANDLED; } @@ -1599,7 +1662,9 @@ int dw_hdmi_bind(struct device *dev, struct device *master, { struct drm_device *drm = data; struct device_node *np = dev->of_node; + struct platform_device_info pdevinfo; struct device_node *ddc_node; + struct dw_hdmi_audio_data audio; struct dw_hdmi *hdmi; int ret; u32 val = 1; @@ -1608,13 +1673,16 @@ int dw_hdmi_bind(struct device *dev, struct device *master, if (!hdmi) return -ENOMEM; + hdmi->connector.interlace_allowed = 1; + hdmi->plat_data = plat_data; hdmi->dev = dev; hdmi->dev_type = plat_data->dev_type; hdmi->sample_rate = 48000; - hdmi->ratio = 100; hdmi->encoder = encoder; hdmi->disabled = true; + hdmi->rxsense = true; + hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); mutex_init(&hdmi->mutex); mutex_init(&hdmi->audio_mutex); @@ -1705,10 +1773,11 @@ int dw_hdmi_bind(struct device *dev, struct device *master, * Configure registers related to HDMI interrupt * generation before registering IRQ. */ - hdmi_writeb(hdmi, HDMI_PHY_HPD, HDMI_PHY_POL0); + hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); /* Clear Hotplug interrupts */ - hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, + HDMI_IH_PHY_STAT0); ret = dw_hdmi_fb_registered(hdmi); if (ret) @@ -1719,7 +1788,26 @@ int dw_hdmi_bind(struct device *dev, struct device *master, goto err_iahb; /* Unmute interrupts */ - hdmi_writeb(hdmi, ~HDMI_IH_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); + hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), + HDMI_IH_MUTE_PHY_STAT0); + + memset(&pdevinfo, 0, sizeof(pdevinfo)); + pdevinfo.parent = dev; + pdevinfo.id = PLATFORM_DEVID_AUTO; + + if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_CONFIG1_AHB) { + audio.phys = iores->start; + audio.base = hdmi->regs; + audio.irq = irq; + audio.hdmi = hdmi; + audio.eld = hdmi->connector.eld; + + pdevinfo.name = "dw-hdmi-ahb-audio"; + pdevinfo.data = &audio; + pdevinfo.size_data = sizeof(audio); + pdevinfo.dma_mask = DMA_BIT_MASK(32); + hdmi->audio = platform_device_register_full(&pdevinfo); + } dev_set_drvdata(dev, hdmi); @@ -1738,6 +1826,9 @@ void dw_hdmi_unbind(struct device *dev, struct device *master, void *data) { struct dw_hdmi *hdmi = dev_get_drvdata(dev); + if (hdmi->audio && !IS_ERR(hdmi->audio)) + platform_device_unregister(hdmi->audio); + /* Disable all interrupts */ hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); diff --git a/drivers/gpu/drm/bridge/dw_hdmi.h b/drivers/gpu/drm/bridge/dw_hdmi.h index ee7f7ed2ab12..fc9a560429d6 100644 --- a/drivers/gpu/drm/bridge/dw_hdmi.h +++ b/drivers/gpu/drm/bridge/dw_hdmi.h @@ -545,6 +545,9 @@ #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12 enum { +/* CONFIG1_ID field values */ + HDMI_CONFIG1_AHB = 0x01, + /* IH_FC_INT2 field values */ HDMI_IH_FC_INT2_OVERFLOW_MASK = 0x03, HDMI_IH_FC_INT2_LOW_PRIORITY_OVERFLOW = 0x02, diff --git a/drivers/gpu/drm/bridge/nxp-ptn3460.c b/drivers/gpu/drm/bridge/nxp-ptn3460.c index 1b1bf2384815..0ffa3a6a206a 100644 --- a/drivers/gpu/drm/bridge/nxp-ptn3460.c +++ b/drivers/gpu/drm/bridge/nxp-ptn3460.c @@ -400,7 +400,6 @@ static struct i2c_driver ptn3460_driver = { .remove = ptn3460_remove, .driver = { .name = "nxp,ptn3460", - .owner = THIS_MODULE, .of_match_table = ptn3460_match, }, }; diff --git a/drivers/gpu/drm/bridge/parade-ps8622.c b/drivers/gpu/drm/bridge/parade-ps8622.c index 1a6607beb29f..be881e9fef8f 100644 --- a/drivers/gpu/drm/bridge/parade-ps8622.c +++ b/drivers/gpu/drm/bridge/parade-ps8622.c @@ -668,7 +668,6 @@ static struct i2c_driver ps8622_driver = { .remove = ps8622_remove, .driver = { .name = "ps8622", - .owner = THIS_MODULE, .of_match_table = ps8622_devices, }, }; diff --git a/drivers/gpu/drm/drm_agpsupport.c b/drivers/gpu/drm/drm_agpsupport.c index 4b2b4aa5033b..a10ea6aec629 100644 --- a/drivers/gpu/drm/drm_agpsupport.c +++ b/drivers/gpu/drm/drm_agpsupport.c @@ -36,8 +36,6 @@ #include <linux/slab.h> #include "drm_legacy.h" -#if __OS_HAS_AGP - #include <asm/agp.h> /** @@ -502,5 +500,3 @@ drm_agp_bind_pages(struct drm_device *dev, return mem; } EXPORT_SYMBOL(drm_agp_bind_pages); - -#endif /* __OS_HAS_AGP */ diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 87a2a446d2b7..0c6f62168776 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1790,8 +1790,13 @@ int __drm_atomic_helper_set_config(struct drm_mode_set *set, primary_state->crtc_w = set->mode->hdisplay; primary_state->src_x = set->x << 16; primary_state->src_y = set->y << 16; - primary_state->src_h = set->mode->vdisplay << 16; - primary_state->src_w = set->mode->hdisplay << 16; + if (primary_state->rotation & (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))) { + primary_state->src_h = set->mode->hdisplay << 16; + primary_state->src_w = set->mode->vdisplay << 16; + } else { + primary_state->src_h = set->mode->vdisplay << 16; + primary_state->src_w = set->mode->hdisplay << 16; + } commit: ret = update_output_state(state, set); diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c index 569064a00693..f1a204d253cc 100644 --- a/drivers/gpu/drm/drm_bufs.c +++ b/drivers/gpu/drm/drm_bufs.c @@ -582,7 +582,7 @@ static void drm_cleanup_buf_error(struct drm_device * dev, } } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) /** * Add AGP buffers for DMA transfers. * @@ -756,7 +756,7 @@ int drm_legacy_addbufs_agp(struct drm_device *dev, return 0; } EXPORT_SYMBOL(drm_legacy_addbufs_agp); -#endif /* __OS_HAS_AGP */ +#endif /* CONFIG_AGP */ int drm_legacy_addbufs_pci(struct drm_device *dev, struct drm_buf_desc *request) @@ -1145,7 +1145,7 @@ int drm_legacy_addbufs(struct drm_device *dev, void *data, if (!drm_core_check_feature(dev, DRIVER_HAVE_DMA)) return -EINVAL; -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (request->flags & _DRM_AGP_BUFFER) ret = drm_legacy_addbufs_agp(dev, request); else diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c index e600a5fb2b60..720a153d1a46 100644 --- a/drivers/gpu/drm/drm_crtc.c +++ b/drivers/gpu/drm/drm_crtc.c @@ -306,8 +306,7 @@ static int drm_mode_object_get_reg(struct drm_device *dev, * reference counted modeset objects like framebuffers. * * Returns: - * New unique (relative to other objects in @dev) integer identifier for the - * object. + * Zero on success, error code on failure. */ int drm_mode_object_get(struct drm_device *dev, struct drm_mode_object *obj, uint32_t obj_type) @@ -423,7 +422,7 @@ int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb, out: mutex_unlock(&dev->mode_config.fb_lock); - return 0; + return ret; } EXPORT_SYMBOL(drm_framebuffer_init); @@ -677,7 +676,6 @@ int drm_crtc_init_with_planes(struct drm_device *dev, struct drm_crtc *crtc, crtc->dev = dev; crtc->funcs = funcs; - crtc->invert_dimensions = false; drm_modeset_lock_init(&crtc->mutex); ret = drm_mode_object_get(dev, &crtc->base, DRM_MODE_OBJECT_CRTC); @@ -1535,6 +1533,9 @@ int drm_mode_create_tv_properties(struct drm_device *dev, "select subconnector", drm_tv_select_enum_list, ARRAY_SIZE(drm_tv_select_enum_list)); + if (!tv_selector) + goto nomem; + dev->mode_config.tv_select_subconnector_property = tv_selector; tv_subconnector = @@ -1542,6 +1543,8 @@ int drm_mode_create_tv_properties(struct drm_device *dev, "subconnector", drm_tv_subconnector_enum_list, ARRAY_SIZE(drm_tv_subconnector_enum_list)); + if (!tv_subconnector) + goto nomem; dev->mode_config.tv_subconnector_property = tv_subconnector; /* @@ -1549,42 +1552,67 @@ int drm_mode_create_tv_properties(struct drm_device *dev, */ dev->mode_config.tv_left_margin_property = drm_property_create_range(dev, 0, "left margin", 0, 100); + if (!dev->mode_config.tv_left_margin_property) + goto nomem; dev->mode_config.tv_right_margin_property = drm_property_create_range(dev, 0, "right margin", 0, 100); + if (!dev->mode_config.tv_right_margin_property) + goto nomem; dev->mode_config.tv_top_margin_property = drm_property_create_range(dev, 0, "top margin", 0, 100); + if (!dev->mode_config.tv_top_margin_property) + goto nomem; dev->mode_config.tv_bottom_margin_property = drm_property_create_range(dev, 0, "bottom margin", 0, 100); + if (!dev->mode_config.tv_bottom_margin_property) + goto nomem; dev->mode_config.tv_mode_property = drm_property_create(dev, DRM_MODE_PROP_ENUM, "mode", num_modes); + if (!dev->mode_config.tv_mode_property) + goto nomem; + for (i = 0; i < num_modes; i++) drm_property_add_enum(dev->mode_config.tv_mode_property, i, i, modes[i]); dev->mode_config.tv_brightness_property = drm_property_create_range(dev, 0, "brightness", 0, 100); + if (!dev->mode_config.tv_brightness_property) + goto nomem; dev->mode_config.tv_contrast_property = drm_property_create_range(dev, 0, "contrast", 0, 100); + if (!dev->mode_config.tv_contrast_property) + goto nomem; dev->mode_config.tv_flicker_reduction_property = drm_property_create_range(dev, 0, "flicker reduction", 0, 100); + if (!dev->mode_config.tv_flicker_reduction_property) + goto nomem; dev->mode_config.tv_overscan_property = drm_property_create_range(dev, 0, "overscan", 0, 100); + if (!dev->mode_config.tv_overscan_property) + goto nomem; dev->mode_config.tv_saturation_property = drm_property_create_range(dev, 0, "saturation", 0, 100); + if (!dev->mode_config.tv_saturation_property) + goto nomem; dev->mode_config.tv_hue_property = drm_property_create_range(dev, 0, "hue", 0, 100); + if (!dev->mode_config.tv_hue_property) + goto nomem; return 0; +nomem: + return -ENOMEM; } EXPORT_SYMBOL(drm_mode_create_tv_properties); @@ -2286,6 +2314,32 @@ int drm_plane_check_pixel_format(const struct drm_plane *plane, u32 format) return -EINVAL; } +static int check_src_coords(uint32_t src_x, uint32_t src_y, + uint32_t src_w, uint32_t src_h, + const struct drm_framebuffer *fb) +{ + unsigned int fb_width, fb_height; + + fb_width = fb->width << 16; + fb_height = fb->height << 16; + + /* Make sure source coordinates are inside the fb. */ + if (src_w > fb_width || + src_x > fb_width - src_w || + src_h > fb_height || + src_y > fb_height - src_h) { + DRM_DEBUG_KMS("Invalid source coordinates " + "%u.%06ux%u.%06u+%u.%06u+%u.%06u\n", + src_w >> 16, ((src_w & 0xffff) * 15625) >> 10, + src_h >> 16, ((src_h & 0xffff) * 15625) >> 10, + src_x >> 16, ((src_x & 0xffff) * 15625) >> 10, + src_y >> 16, ((src_y & 0xffff) * 15625) >> 10); + return -ENOSPC; + } + + return 0; +} + /* * setplane_internal - setplane handler for internal callers * @@ -2305,7 +2359,6 @@ static int __setplane_internal(struct drm_plane *plane, uint32_t src_w, uint32_t src_h) { int ret = 0; - unsigned int fb_width, fb_height; /* No fb means shut it down */ if (!fb) { @@ -2342,27 +2395,13 @@ static int __setplane_internal(struct drm_plane *plane, crtc_y > INT_MAX - (int32_t) crtc_h) { DRM_DEBUG_KMS("Invalid CRTC coordinates %ux%u+%d+%d\n", crtc_w, crtc_h, crtc_x, crtc_y); - return -ERANGE; + ret = -ERANGE; + goto out; } - - fb_width = fb->width << 16; - fb_height = fb->height << 16; - - /* Make sure source coordinates are inside the fb. */ - if (src_w > fb_width || - src_x > fb_width - src_w || - src_h > fb_height || - src_y > fb_height - src_h) { - DRM_DEBUG_KMS("Invalid source coordinates " - "%u.%06ux%u.%06u+%u.%06u+%u.%06u\n", - src_w >> 16, ((src_w & 0xffff) * 15625) >> 10, - src_h >> 16, ((src_h & 0xffff) * 15625) >> 10, - src_x >> 16, ((src_x & 0xffff) * 15625) >> 10, - src_y >> 16, ((src_y & 0xffff) * 15625) >> 10); - ret = -ENOSPC; + ret = check_src_coords(src_x, src_y, src_w, src_h, fb); + if (ret) goto out; - } plane->old_fb = plane->fb; ret = plane->funcs->update_plane(plane, crtc, fb, @@ -2553,20 +2592,13 @@ int drm_crtc_check_viewport(const struct drm_crtc *crtc, drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); - if (crtc->invert_dimensions) + if (crtc->state && + crtc->primary->state->rotation & (BIT(DRM_ROTATE_90) | + BIT(DRM_ROTATE_270))) swap(hdisplay, vdisplay); - if (hdisplay > fb->width || - vdisplay > fb->height || - x > fb->width - hdisplay || - y > fb->height - vdisplay) { - DRM_DEBUG_KMS("Invalid fb size %ux%u for CRTC viewport %ux%u+%d+%d%s.\n", - fb->width, fb->height, hdisplay, vdisplay, x, y, - crtc->invert_dimensions ? " (inverted)" : ""); - return -ENOSPC; - } - - return 0; + return check_src_coords(x << 16, y << 16, + hdisplay << 16, vdisplay << 16, fb); } EXPORT_SYMBOL(drm_crtc_check_viewport); @@ -5181,7 +5213,14 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev, goto out; } - ret = drm_crtc_check_viewport(crtc, crtc->x, crtc->y, &crtc->mode, fb); + if (crtc->state) { + const struct drm_plane_state *state = crtc->primary->state; + + ret = check_src_coords(state->src_x, state->src_y, + state->src_w, state->src_h, fb); + } else { + ret = drm_crtc_check_viewport(crtc, crtc->x, crtc->y, &crtc->mode, fb); + } if (ret) goto out; @@ -5629,7 +5668,8 @@ unsigned int drm_rotation_simplify(unsigned int rotation, { if (rotation & ~supported_rotations) { rotation ^= BIT(DRM_REFLECT_X) | BIT(DRM_REFLECT_Y); - rotation = (rotation & ~0xf) | BIT((ffs(rotation & 0xf) + 1) % 4); + rotation = (rotation & DRM_REFLECT_MASK) | + BIT((ffs(rotation & DRM_ROTATE_MASK) + 1) % 4); } return rotation; diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index e23df5fd3836..2d46fc6230c2 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -53,8 +53,8 @@ static int drm_dp_send_dpcd_write(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, int offset, int size, u8 *bytes); -static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_branch *mstb); +static void drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_branch *mstb); static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_branch *mstb, struct drm_dp_mst_port *port); @@ -804,8 +804,6 @@ static void drm_dp_destroy_mst_branch_device(struct kref *kref) struct drm_dp_mst_port *port, *tmp; bool wake_tx = false; - cancel_work_sync(&mstb->mgr->work); - /* * destroy all ports - don't need lock * as there are no more references to the mst branch @@ -863,29 +861,33 @@ static void drm_dp_destroy_port(struct kref *kref) { struct drm_dp_mst_port *port = container_of(kref, struct drm_dp_mst_port, kref); struct drm_dp_mst_topology_mgr *mgr = port->mgr; + if (!port->input) { port->vcpi.num_slots = 0; kfree(port->cached_edid); - /* we can't destroy the connector here, as - we might be holding the mode_config.mutex - from an EDID retrieval */ + /* + * The only time we don't have a connector + * on an output port is if the connector init + * fails. + */ if (port->connector) { + /* we can't destroy the connector here, as + * we might be holding the mode_config.mutex + * from an EDID retrieval */ + mutex_lock(&mgr->destroy_connector_lock); list_add(&port->next, &mgr->destroy_connector_list); mutex_unlock(&mgr->destroy_connector_lock); schedule_work(&mgr->destroy_connector_work); return; } + /* no need to clean up vcpi + * as if we have no connector we never setup a vcpi */ drm_dp_port_teardown_pdt(port, port->pdt); - - if (!port->input && port->vcpi.vcpi > 0) - drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi); } kfree(port); - - (*mgr->cbs->hotplug)(mgr); } static void drm_dp_put_port(struct drm_dp_mst_port *port) @@ -1027,8 +1029,8 @@ static void drm_dp_check_port_guid(struct drm_dp_mst_branch *mstb, } } -static void build_mst_prop_path(struct drm_dp_mst_port *port, - struct drm_dp_mst_branch *mstb, +static void build_mst_prop_path(const struct drm_dp_mst_branch *mstb, + int pnum, char *proppath, size_t proppath_size) { @@ -1041,7 +1043,7 @@ static void build_mst_prop_path(struct drm_dp_mst_port *port, snprintf(temp, sizeof(temp), "-%d", port_num); strlcat(proppath, temp, proppath_size); } - snprintf(temp, sizeof(temp), "-%d", port->port_num); + snprintf(temp, sizeof(temp), "-%d", pnum); strlcat(proppath, temp, proppath_size); } @@ -1105,22 +1107,32 @@ static void drm_dp_add_port(struct drm_dp_mst_branch *mstb, drm_dp_port_teardown_pdt(port, old_pdt); ret = drm_dp_port_setup_pdt(port); - if (ret == true) { + if (ret == true) drm_dp_send_link_address(mstb->mgr, port->mstb); - port->mstb->link_address_sent = true; - } } if (created && !port->input) { char proppath[255]; - build_mst_prop_path(port, mstb, proppath, sizeof(proppath)); - port->connector = (*mstb->mgr->cbs->add_connector)(mstb->mgr, port, proppath); - if (port->port_num >= 8) { + build_mst_prop_path(mstb, port->port_num, proppath, sizeof(proppath)); + port->connector = (*mstb->mgr->cbs->add_connector)(mstb->mgr, port, proppath); + if (!port->connector) { + /* remove it from the port list */ + mutex_lock(&mstb->mgr->lock); + list_del(&port->next); + mutex_unlock(&mstb->mgr->lock); + /* drop port list reference */ + drm_dp_put_port(port); + goto out; + } + if (port->port_num >= DP_MST_LOGICAL_PORT_0) { port->cached_edid = drm_get_edid(port->connector, &port->aux.ddc); + drm_mode_connector_set_tile_property(port->connector); } + (*mstb->mgr->cbs->register_connector)(port->connector); } +out: /* put reference to this port */ drm_dp_put_port(port); } @@ -1182,17 +1194,18 @@ static struct drm_dp_mst_branch *drm_dp_get_mst_branch_device(struct drm_dp_mst_ list_for_each_entry(port, &mstb->ports, next) { if (port->port_num == port_num) { - if (!port->mstb) { + mstb = port->mstb; + if (!mstb) { DRM_ERROR("failed to lookup MSTB with lct %d, rad %02x\n", lct, rad[0]); - return NULL; + goto out; } - mstb = port->mstb; break; } } } kref_get(&mstb->kref); +out: mutex_unlock(&mgr->lock); return mstb; } @@ -1202,10 +1215,9 @@ static void drm_dp_check_and_send_link_address(struct drm_dp_mst_topology_mgr *m { struct drm_dp_mst_port *port; struct drm_dp_mst_branch *mstb_child; - if (!mstb->link_address_sent) { + if (!mstb->link_address_sent) drm_dp_send_link_address(mgr, mstb); - mstb->link_address_sent = true; - } + list_for_each_entry(port, &mstb->ports, next) { if (port->input) continue; @@ -1458,8 +1470,8 @@ static void drm_dp_queue_down_tx(struct drm_dp_mst_topology_mgr *mgr, mutex_unlock(&mgr->qlock); } -static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, - struct drm_dp_mst_branch *mstb) +static void drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_branch *mstb) { int len; struct drm_dp_sideband_msg_tx *txmsg; @@ -1467,11 +1479,12 @@ static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, txmsg = kzalloc(sizeof(*txmsg), GFP_KERNEL); if (!txmsg) - return -ENOMEM; + return; txmsg->dst = mstb; len = build_link_address(txmsg); + mstb->link_address_sent = true; drm_dp_queue_down_tx(mgr, txmsg); ret = drm_dp_mst_wait_tx_reply(mstb, txmsg); @@ -1499,11 +1512,12 @@ static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, } (*mgr->cbs->hotplug)(mgr); } - } else + } else { + mstb->link_address_sent = false; DRM_DEBUG_KMS("link address failed %d\n", ret); + } kfree(txmsg); - return 0; } static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, @@ -1978,6 +1992,8 @@ void drm_dp_mst_topology_mgr_suspend(struct drm_dp_mst_topology_mgr *mgr) drm_dp_dpcd_writeb(mgr->aux, DP_MSTM_CTRL, DP_MST_EN | DP_UPSTREAM_IS_SRC); mutex_unlock(&mgr->lock); + flush_work(&mgr->work); + flush_work(&mgr->destroy_connector_work); } EXPORT_SYMBOL(drm_dp_mst_topology_mgr_suspend); @@ -2263,10 +2279,10 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector, struct drm_dp_ if (port->cached_edid) edid = drm_edid_duplicate(port->cached_edid); - else + else { edid = drm_get_edid(connector, &port->aux.ddc); - - drm_mode_connector_set_tile_property(connector); + drm_mode_connector_set_tile_property(connector); + } drm_dp_put_port(port); return edid; } @@ -2671,7 +2687,7 @@ static void drm_dp_destroy_connector_work(struct work_struct *work) { struct drm_dp_mst_topology_mgr *mgr = container_of(work, struct drm_dp_mst_topology_mgr, destroy_connector_work); struct drm_dp_mst_port *port; - + bool send_hotplug = false; /* * Not a regular list traverse as we have to drop the destroy * connector lock before destroying the connector, to avoid AB->BA @@ -2694,7 +2710,10 @@ static void drm_dp_destroy_connector_work(struct work_struct *work) if (!port->input && port->vcpi.vcpi > 0) drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi); kfree(port); + send_hotplug = true; } + if (send_hotplug) + (*mgr->cbs->hotplug)(mgr); } /** @@ -2747,6 +2766,7 @@ EXPORT_SYMBOL(drm_dp_mst_topology_mgr_init); */ void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr) { + flush_work(&mgr->work); flush_work(&mgr->destroy_connector_work); mutex_lock(&mgr->payload_lock); kfree(mgr->payloads); diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c index 9ad823fcde87..9362609df38a 100644 --- a/drivers/gpu/drm/drm_drv.c +++ b/drivers/gpu/drm/drm_drv.c @@ -37,11 +37,9 @@ #include "drm_legacy.h" #include "drm_internal.h" -unsigned int drm_debug = 0; /* 1 to enable debug output */ +unsigned int drm_debug = 0; /* bitmask of DRM_UT_x */ EXPORT_SYMBOL(drm_debug); -bool drm_atomic = 0; - MODULE_AUTHOR(CORE_AUTHOR); MODULE_DESCRIPTION(CORE_DESC); MODULE_LICENSE("GPL and additional rights"); @@ -397,15 +395,51 @@ void drm_minor_release(struct drm_minor *minor) } /** + * DOC: driver instance overview + * + * A device instance for a drm driver is represented by struct &drm_device. This + * is allocated with drm_dev_alloc(), usually from bus-specific ->probe() + * callbacks implemented by the driver. The driver then needs to initialize all + * the various subsystems for the drm device like memory management, vblank + * handling, modesetting support and intial output configuration plus obviously + * initialize all the corresponding hardware bits. An important part of this is + * also calling drm_dev_set_unique() to set the userspace-visible unique name of + * this device instance. Finally when everything is up and running and ready for + * userspace the device instance can be published using drm_dev_register(). + * + * There is also deprecated support for initalizing device instances using + * bus-specific helpers and the ->load() callback. But due to + * backwards-compatibility needs the device instance have to be published too + * early, which requires unpretty global locking to make safe and is therefore + * only support for existing drivers not yet converted to the new scheme. + * + * When cleaning up a device instance everything needs to be done in reverse: + * First unpublish the device instance with drm_dev_unregister(). Then clean up + * any other resources allocated at device initialization and drop the driver's + * reference to &drm_device using drm_dev_unref(). + * + * Note that the lifetime rules for &drm_device instance has still a lot of + * historical baggage. Hence use the reference counting provided by + * drm_dev_ref() and drm_dev_unref() only carefully. + * + * Also note that embedding of &drm_device is currently not (yet) supported (but + * it would be easy to add). Drivers can store driver-private data in the + * dev_priv field of &drm_device. + */ + +/** * drm_put_dev - Unregister and release a DRM device * @dev: DRM device * * Called at module unload time or when a PCI device is unplugged. * - * Use of this function is discouraged. It will eventually go away completely. - * Please use drm_dev_unregister() and drm_dev_unref() explicitly instead. - * * Cleans up all DRM device, calling drm_lastclose(). + * + * Note: Use of this function is deprecated. It will eventually go away + * completely. Please use drm_dev_unregister() and drm_dev_unref() explicitly + * instead to make sure that the device isn't userspace accessible any more + * while teardown is in progress, ensuring that userspace can't access an + * inconsistent state. */ void drm_put_dev(struct drm_device *dev) { @@ -518,7 +552,9 @@ static void drm_fs_inode_free(struct inode *inode) * * Allocate and initialize a new DRM device. No device registration is done. * Call drm_dev_register() to advertice the device to user space and register it - * with other core subsystems. + * with other core subsystems. This should be done last in the device + * initialization sequence to make sure userspace can't access an inconsistent + * state. * * The initial ref-count of the object is 1. Use drm_dev_ref() and * drm_dev_unref() to take and drop further ref-counts. @@ -673,6 +709,12 @@ EXPORT_SYMBOL(drm_dev_unref); * * Never call this twice on any device! * + * NOTE: To ensure backward compatibility with existing drivers method this + * function calls the ->load() method after registering the device nodes, + * creating race conditions. Usage of the ->load() methods is therefore + * deprecated, drivers must perform all initialization before calling + * drm_dev_register(). + * * RETURNS: * 0 on success, negative error code on failure. */ @@ -720,6 +762,9 @@ EXPORT_SYMBOL(drm_dev_register); * Unregister the DRM device from the system. This does the reverse of * drm_dev_register() but does not deallocate the device. The caller must call * drm_dev_unref() to drop their final reference. + * + * This should be called first in the device teardown code to make sure + * userspace can't access the device instance any more. */ void drm_dev_unregister(struct drm_device *dev) { diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index d895556be4f0..d5d2c03fd136 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2418,6 +2418,8 @@ add_cvt_modes(struct drm_connector *connector, struct edid *edid) return closure.modes; } +static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); + static void do_detailed_mode(struct detailed_timing *timing, void *c) { @@ -2434,6 +2436,13 @@ do_detailed_mode(struct detailed_timing *timing, void *c) if (closure->preferred) newmode->type |= DRM_MODE_TYPE_PREFERRED; + /* + * Detailed modes are limited to 10kHz pixel clock resolution, + * so fix up anything that looks like CEA/HDMI mode, but the clock + * is just slightly off. + */ + fixup_detailed_cea_mode_clock(newmode); + drm_mode_probed_add(closure->connector, newmode); closure->modes++; closure->preferred = 0; @@ -2529,9 +2538,9 @@ cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) * and the 60Hz variant otherwise. */ if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) - clock = clock * 1001 / 1000; + clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); else - clock = DIV_ROUND_UP(clock * 1000, 1001); + clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); return clock; } @@ -3103,6 +3112,45 @@ add_cea_modes(struct drm_connector *connector, struct edid *edid) return modes; } +static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) +{ + const struct drm_display_mode *cea_mode; + int clock1, clock2, clock; + u8 mode_idx; + const char *type; + + mode_idx = drm_match_cea_mode(mode) - 1; + if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { + type = "CEA"; + cea_mode = &edid_cea_modes[mode_idx]; + clock1 = cea_mode->clock; + clock2 = cea_mode_alternate_clock(cea_mode); + } else { + mode_idx = drm_match_hdmi_mode(mode) - 1; + if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { + type = "HDMI"; + cea_mode = &edid_4k_modes[mode_idx]; + clock1 = cea_mode->clock; + clock2 = hdmi_mode_alternate_clock(cea_mode); + } else { + return; + } + } + + /* pick whichever is closest */ + if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) + clock = clock1; + else + clock = clock2; + + if (mode->clock == clock) + return; + + DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", + type, mode_idx + 1, mode->clock, clock); + mode->clock = clock; +} + static void parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) { diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index abe9793d548d..e673c13c7391 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -360,11 +360,7 @@ retry: goto fail; } - ret = drm_atomic_plane_set_property(plane, plane_state, - dev->mode_config.rotation_property, - BIT(DRM_ROTATE_0)); - if (ret != 0) - goto fail; + plane_state->rotation = BIT(DRM_ROTATE_0); /* disable non-primary: */ if (plane->type == DRM_PLANE_TYPE_PRIMARY) @@ -442,7 +438,11 @@ static int restore_fbdev_mode(struct drm_fb_helper *fb_helper) struct drm_crtc *crtc = mode_set->crtc; int ret; - if (crtc->funcs->cursor_set) { + if (crtc->funcs->cursor_set2) { + ret = crtc->funcs->cursor_set2(crtc, NULL, 0, 0, 0, 0, 0); + if (ret) + return ret; + } else if (crtc->funcs->cursor_set) { ret = crtc->funcs->cursor_set(crtc, NULL, 0, 0, 0); if (ret) return ret; @@ -1231,7 +1231,7 @@ int drm_fb_helper_set_par(struct fb_info *info) EXPORT_SYMBOL(drm_fb_helper_set_par); static int pan_display_atomic(struct fb_var_screeninfo *var, - struct fb_info *info) + struct fb_info *info) { struct drm_fb_helper *fb_helper = info->par; struct drm_device *dev = fb_helper->dev; @@ -1249,6 +1249,8 @@ retry: mode_set = &fb_helper->crtc_info[i].mode_set; + mode_set->crtc->primary->old_fb = mode_set->crtc->primary->fb; + mode_set->x = var->xoffset; mode_set->y = var->yoffset; @@ -1264,13 +1266,34 @@ retry: info->var.xoffset = var->xoffset; info->var.yoffset = var->yoffset; - return 0; fail: + for(i = 0; i < fb_helper->crtc_count; i++) { + struct drm_mode_set *mode_set; + struct drm_plane *plane; + + mode_set = &fb_helper->crtc_info[i].mode_set; + plane = mode_set->crtc->primary; + + if (ret == 0) { + struct drm_framebuffer *new_fb = plane->state->fb; + + if (new_fb) + drm_framebuffer_reference(new_fb); + plane->fb = new_fb; + plane->crtc = plane->state->crtc; + + if (plane->old_fb) + drm_framebuffer_unreference(plane->old_fb); + } + plane->old_fb = NULL; + } + if (ret == -EDEADLK) goto backoff; - drm_atomic_state_free(state); + if (ret != 0) + drm_atomic_state_free(state); return ret; diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index 3c2d4abd71c5..64353d40db53 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -763,7 +763,8 @@ EXPORT_SYMBOL(drm_gem_object_release); void drm_gem_object_free(struct kref *kref) { - struct drm_gem_object *obj = (struct drm_gem_object *) kref; + struct drm_gem_object *obj = + container_of(kref, struct drm_gem_object, refcount); struct drm_device *dev = obj->dev; WARN_ON(!mutex_is_locked(&dev->struct_mutex)); @@ -810,8 +811,6 @@ EXPORT_SYMBOL(drm_gem_vm_close); * drm_gem_mmap() prevents unprivileged users from mapping random objects. So * callers must verify access restrictions before calling this helper. * - * NOTE: This function has to be protected with dev->struct_mutex - * * Return 0 or success or -EINVAL if the object size is smaller than the VMA * size, or if no gem_vm_ops are provided. */ @@ -820,8 +819,6 @@ int drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, { struct drm_device *dev = obj->dev; - lockdep_assert_held(&dev->struct_mutex); - /* Check for valid size. */ if (obj_size < vma->vm_end - vma->vm_start) return -EINVAL; @@ -865,30 +862,46 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { struct drm_file *priv = filp->private_data; struct drm_device *dev = priv->minor->dev; - struct drm_gem_object *obj; + struct drm_gem_object *obj = NULL; struct drm_vma_offset_node *node; int ret; if (drm_device_is_unplugged(dev)) return -ENODEV; - mutex_lock(&dev->struct_mutex); + drm_vma_offset_lock_lookup(dev->vma_offset_manager); + node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager, + vma->vm_pgoff, + vma_pages(vma)); + if (likely(node)) { + obj = container_of(node, struct drm_gem_object, vma_node); + /* + * When the object is being freed, after it hits 0-refcnt it + * proceeds to tear down the object. In the process it will + * attempt to remove the VMA offset and so acquire this + * mgr->vm_lock. Therefore if we find an object with a 0-refcnt + * that matches our range, we know it is in the process of being + * destroyed and will be freed as soon as we release the lock - + * so we have to check for the 0-refcnted object and treat it as + * invalid. + */ + if (!kref_get_unless_zero(&obj->refcount)) + obj = NULL; + } + drm_vma_offset_unlock_lookup(dev->vma_offset_manager); - node = drm_vma_offset_exact_lookup(dev->vma_offset_manager, - vma->vm_pgoff, - vma_pages(vma)); - if (!node) { - mutex_unlock(&dev->struct_mutex); + if (!obj) return -EINVAL; - } else if (!drm_vma_node_is_allowed(node, filp)) { - mutex_unlock(&dev->struct_mutex); + + if (!drm_vma_node_is_allowed(node, filp)) { + drm_gem_object_unreference_unlocked(obj); return -EACCES; } - obj = container_of(node, struct drm_gem_object, vma_node); - ret = drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, vma); + ret = drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, + vma); - mutex_unlock(&dev->struct_mutex); + drm_gem_object_unreference_unlocked(obj); return ret; } diff --git a/drivers/gpu/drm/drm_gem_cma_helper.c b/drivers/gpu/drm/drm_gem_cma_helper.c index 86cc793cdf79..4fb4c45d039f 100644 --- a/drivers/gpu/drm/drm_gem_cma_helper.c +++ b/drivers/gpu/drm/drm_gem_cma_helper.c @@ -484,9 +484,7 @@ int drm_gem_cma_prime_mmap(struct drm_gem_object *obj, struct drm_device *dev = obj->dev; int ret; - mutex_lock(&dev->struct_mutex); ret = drm_gem_mmap_obj(obj, obj->size, vma); - mutex_unlock(&dev->struct_mutex); if (ret < 0) return ret; diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c index ddfa6014c2c2..57676f8d7ecf 100644 --- a/drivers/gpu/drm/drm_ioc32.c +++ b/drivers/gpu/drm/drm_ioc32.c @@ -720,7 +720,7 @@ static int compat_drm_dma(struct file *file, unsigned int cmd, return 0; } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) typedef struct drm_agp_mode32 { u32 mode; /**< AGP mode */ } drm_agp_mode32_t; @@ -882,7 +882,7 @@ static int compat_drm_agp_unbind(struct file *file, unsigned int cmd, return drm_ioctl(file, DRM_IOCTL_AGP_UNBIND, (unsigned long)request); } -#endif /* __OS_HAS_AGP */ +#endif /* CONFIG_AGP */ typedef struct drm_scatter_gather32 { u32 size; /**< In bytes -- will round to page boundary */ @@ -1090,7 +1090,7 @@ static drm_ioctl_compat_t *drm_compat_ioctls[] = { [DRM_IOCTL_NR(DRM_IOCTL_GET_SAREA_CTX32)] = compat_drm_getsareactx, [DRM_IOCTL_NR(DRM_IOCTL_RES_CTX32)] = compat_drm_resctx, [DRM_IOCTL_NR(DRM_IOCTL_DMA32)] = compat_drm_dma, -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) [DRM_IOCTL_NR(DRM_IOCTL_AGP_ENABLE32)] = compat_drm_agp_enable, [DRM_IOCTL_NR(DRM_IOCTL_AGP_INFO32)] = compat_drm_agp_info, [DRM_IOCTL_NR(DRM_IOCTL_AGP_ALLOC32)] = compat_drm_agp_alloc, diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c index d93e7378c077..8ce2a0c59116 100644 --- a/drivers/gpu/drm/drm_ioctl.c +++ b/drivers/gpu/drm/drm_ioctl.c @@ -40,7 +40,7 @@ static int drm_version(struct drm_device *dev, void *data, struct drm_file *file_priv); -/** +/* * Get the bus id. * * \param inode device inode. @@ -75,7 +75,7 @@ drm_unset_busid(struct drm_device *dev, master->unique_len = 0; } -/** +/* * Set the bus id. * * \param inode device inode. @@ -149,7 +149,7 @@ static int drm_set_busid(struct drm_device *dev, struct drm_file *file_priv) return 0; } -/** +/* * Get a mapping information. * * \param inode device inode. @@ -201,7 +201,7 @@ static int drm_getmap(struct drm_device *dev, void *data, return 0; } -/** +/* * Get client information. * * \param inode device inode. @@ -244,7 +244,7 @@ static int drm_getclient(struct drm_device *dev, void *data, } } -/** +/* * Get statistics information. * * \param inode device inode. @@ -265,7 +265,7 @@ static int drm_getstats(struct drm_device *dev, void *data, return 0; } -/** +/* * Get device/driver capabilities */ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv) @@ -318,7 +318,7 @@ static int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_ return 0; } -/** +/* * Set device/driver capabilities */ static int @@ -352,7 +352,7 @@ drm_setclientcap(struct drm_device *dev, void *data, struct drm_file *file_priv) return 0; } -/** +/* * Setversion ioctl. * * \param inode device inode. @@ -406,7 +406,18 @@ done: return retcode; } -/** No-op ioctl. */ +/** + * drm_noop - DRM no-op ioctl implemntation + * @dev: DRM device for the ioctl + * @data: data pointer for the ioctl + * @file_priv: DRM file for the ioctl call + * + * This no-op implementation for drm ioctls is useful for deprecated + * functionality where we can't return a failure code because existing userspace + * checks the result of the ioctl, but doesn't care about the action. + * + * Always returns successfully with 0. + */ int drm_noop(struct drm_device *dev, void *data, struct drm_file *file_priv) { @@ -416,6 +427,28 @@ int drm_noop(struct drm_device *dev, void *data, EXPORT_SYMBOL(drm_noop); /** + * drm_invalid_op - DRM invalid ioctl implemntation + * @dev: DRM device for the ioctl + * @data: data pointer for the ioctl + * @file_priv: DRM file for the ioctl call + * + * This no-op implementation for drm ioctls is useful for deprecated + * functionality where we really don't want to allow userspace to call the ioctl + * any more. This is the case for old ums interfaces for drivers that + * transitioned to kms gradually and so kept the old legacy tables around. This + * only applies to radeon and i915 kms drivers, other drivers shouldn't need to + * use this function. + * + * Always fails with a return value of -EINVAL. + */ +int drm_invalid_op(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + return -EINVAL; +} +EXPORT_SYMBOL(drm_invalid_op); + +/* * Copy and IOCTL return string to user space */ static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value) @@ -438,7 +471,7 @@ static int drm_copy_field(char __user *buf, size_t *buf_len, const char *value) return 0; } -/** +/* * Get version information * * \param inode device inode. @@ -470,7 +503,7 @@ static int drm_version(struct drm_device *dev, void *data, return err; } -/** +/* * drm_ioctl_permit - Check ioctl permissions against caller * * @flags: ioctl permission flags. @@ -518,7 +551,7 @@ EXPORT_SYMBOL(drm_ioctl_permit); .name = #ioctl \ } -/** Ioctl table */ +/* Ioctl table */ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_VERSION, drm_version, DRM_UNLOCKED|DRM_RENDER_ALLOW|DRM_CONTROL_ALLOW), @@ -571,7 +604,7 @@ static const struct drm_ioctl_desc drm_ioctls[] = { DRM_IOCTL_DEF(DRM_IOCTL_CONTROL, drm_control, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) DRM_IOCTL_DEF(DRM_IOCTL_AGP_ACQUIRE, drm_agp_acquire_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_AGP_RELEASE, drm_agp_release_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF(DRM_IOCTL_AGP_ENABLE, drm_agp_enable_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), @@ -635,16 +668,16 @@ static const struct drm_ioctl_desc drm_ioctls[] = { #define DRM_CORE_IOCTL_COUNT ARRAY_SIZE( drm_ioctls ) /** - * Called whenever a process performs an ioctl on /dev/drm. - * - * \param inode device inode. - * \param file_priv DRM file private. - * \param cmd command. - * \param arg user argument. - * \return zero on success or negative number on failure. + * drm_ioctl - ioctl callback implementation for DRM drivers + * @filp: file this ioctl is called on + * @cmd: ioctl cmd number + * @arg: user argument * * Looks up the ioctl function in the ::ioctls table, checking for root * previleges if so required, and dispatches to the respective function. + * + * Returns: + * Zero on success, negative error code on failure. */ long drm_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) @@ -658,13 +691,16 @@ long drm_ioctl(struct file *filp, char stack_kdata[128]; char *kdata = NULL; unsigned int usize, asize, drv_size; + bool is_driver_ioctl; dev = file_priv->minor->dev; if (drm_device_is_unplugged(dev)) return -ENODEV; - if (nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END) { + is_driver_ioctl = nr >= DRM_COMMAND_BASE && nr < DRM_COMMAND_END; + + if (is_driver_ioctl) { /* driver ioctl */ if (nr - DRM_COMMAND_BASE >= dev->driver->num_ioctls) goto err_i1; @@ -723,7 +759,10 @@ long drm_ioctl(struct file *filp, memset(kdata, 0, usize); } - if (ioctl->flags & DRM_UNLOCKED) + /* Enforce sane locking for kms driver ioctls. Core ioctls are + * too messy still. */ + if ((drm_core_check_feature(dev, DRIVER_MODESET) && is_driver_ioctl) || + (ioctl->flags & DRM_UNLOCKED)) retcode = func(dev, kdata, file_priv); else { mutex_lock(&drm_global_mutex); @@ -754,9 +793,15 @@ EXPORT_SYMBOL(drm_ioctl); /** * drm_ioctl_flags - Check for core ioctl and return ioctl permission flags + * @nr: ioctl number + * @flags: where to return the ioctl permission flags + * + * This ioctl is only used by the vmwgfx driver to augment the access checks + * done by the drm core and insofar a pretty decent layering violation. This + * shouldn't be used by any drivers. * - * @nr: Ioctl number. - * @flags: Where to return the ioctl permission flags + * Returns: + * True if the @nr corresponds to a DRM core ioctl numer, false otherwise. */ bool drm_ioctl_flags(unsigned int nr, unsigned int *flags) { diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c index ed2394e1720b..eba6337f5860 100644 --- a/drivers/gpu/drm/drm_irq.c +++ b/drivers/gpu/drm/drm_irq.c @@ -213,17 +213,17 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, diff = DIV_ROUND_CLOSEST_ULL(diff_ns, framedur_ns); if (diff == 0 && flags & DRM_CALLED_FROM_VBLIRQ) - DRM_DEBUG("crtc %u: Redundant vblirq ignored." - " diff_ns = %lld, framedur_ns = %d)\n", - pipe, (long long) diff_ns, framedur_ns); + DRM_DEBUG_VBL("crtc %u: Redundant vblirq ignored." + " diff_ns = %lld, framedur_ns = %d)\n", + pipe, (long long) diff_ns, framedur_ns); } else { /* some kind of default for drivers w/o accurate vbl timestamping */ diff = (flags & DRM_CALLED_FROM_VBLIRQ) != 0; } - DRM_DEBUG("updating vblank count on crtc %u:" - " current=%u, diff=%u, hw=%u hw_last=%u\n", - pipe, vblank->count, diff, cur_vblank, vblank->last); + DRM_DEBUG_VBL("updating vblank count on crtc %u:" + " current=%u, diff=%u, hw=%u hw_last=%u\n", + pipe, vblank->count, diff, cur_vblank, vblank->last); if (diff == 0) { WARN_ON_ONCE(cur_vblank != vblank->last); @@ -232,10 +232,11 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, /* * Only reinitialize corresponding vblank timestamp if high-precision query - * available and didn't fail. Otherwise reinitialize delayed at next vblank - * interrupt and assign 0 for now, to mark the vblanktimestamp as invalid. + * available and didn't fail, or we were called from the vblank interrupt. + * Otherwise reinitialize delayed at next vblank interrupt and assign 0 + * for now, to mark the vblanktimestamp as invalid. */ - if (!rc) + if (!rc && (flags & DRM_CALLED_FROM_VBLIRQ) == 0) t_vblank = (struct timeval) {0, 0}; store_vblank(dev, pipe, diff, &t_vblank, cur_vblank); @@ -799,11 +800,11 @@ int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, etime = ktime_sub_ns(etime, delta_ns); *vblank_time = ktime_to_timeval(etime); - DRM_DEBUG("crtc %u : v 0x%x p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n", - pipe, vbl_status, hpos, vpos, - (long)tv_etime.tv_sec, (long)tv_etime.tv_usec, - (long)vblank_time->tv_sec, (long)vblank_time->tv_usec, - duration_ns/1000, i); + DRM_DEBUG_VBL("crtc %u : v 0x%x p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n", + pipe, vbl_status, hpos, vpos, + (long)tv_etime.tv_sec, (long)tv_etime.tv_usec, + (long)vblank_time->tv_sec, (long)vblank_time->tv_usec, + duration_ns/1000, i); return ret; } @@ -876,7 +877,7 @@ drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe, * Returns: * The software vblank counter. */ -u32 drm_vblank_count(struct drm_device *dev, int pipe) +u32 drm_vblank_count(struct drm_device *dev, unsigned int pipe) { struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; @@ -1271,8 +1272,8 @@ void drm_vblank_off(struct drm_device *dev, unsigned int pipe) list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) { if (e->pipe != pipe) continue; - DRM_DEBUG("Sending premature vblank event on disable: \ - wanted %d, current %d\n", + DRM_DEBUG("Sending premature vblank event on disable: " + "wanted %d, current %d\n", e->event.sequence, seq); list_del(&e->base.link); drm_vblank_put(dev, pipe); @@ -1797,3 +1798,20 @@ bool drm_crtc_handle_vblank(struct drm_crtc *crtc) return drm_handle_vblank(crtc->dev, drm_crtc_index(crtc)); } EXPORT_SYMBOL(drm_crtc_handle_vblank); + +/** + * drm_vblank_no_hw_counter - "No hw counter" implementation of .get_vblank_counter() + * @dev: DRM device + * @pipe: CRTC for which to read the counter + * + * Drivers can plug this into the .get_vblank_counter() function if + * there is no useable hardware frame counter available. + * + * Returns: + * 0 + */ +u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) +{ + return 0; +} +EXPORT_SYMBOL(drm_vblank_no_hw_counter); diff --git a/drivers/gpu/drm/drm_memory.c b/drivers/gpu/drm/drm_memory.c index a521ef6ff807..87a8cb73366f 100644 --- a/drivers/gpu/drm/drm_memory.c +++ b/drivers/gpu/drm/drm_memory.c @@ -38,7 +38,7 @@ #include <drm/drmP.h> #include "drm_legacy.h" -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) #ifdef HAVE_PAGE_AGP # include <asm/agp.h> @@ -111,14 +111,14 @@ int drm_unbind_agp(struct agp_memory * handle) return agp_unbind_memory(handle); } -#else /* __OS_HAS_AGP */ +#else /* CONFIG_AGP */ static inline void *agp_remap(unsigned long offset, unsigned long size, struct drm_device * dev) { return NULL; } -#endif /* agp */ +#endif /* CONFIG_AGP */ void drm_legacy_ioremap(struct drm_local_map *map, struct drm_device *dev) { diff --git a/drivers/gpu/drm/drm_of.c b/drivers/gpu/drm/drm_of.c index be3884073ea4..493c05c9ce4f 100644 --- a/drivers/gpu/drm/drm_of.c +++ b/drivers/gpu/drm/drm_of.c @@ -1,3 +1,4 @@ +#include <linux/component.h> #include <linux/export.h> #include <linux/list.h> #include <linux/of_graph.h> @@ -61,3 +62,90 @@ uint32_t drm_of_find_possible_crtcs(struct drm_device *dev, return possible_crtcs; } EXPORT_SYMBOL(drm_of_find_possible_crtcs); + +/** + * drm_of_component_probe - Generic probe function for a component based master + * @dev: master device containing the OF node + * @compare_of: compare function used for matching components + * @master_ops: component master ops to be used + * + * Parse the platform device OF node and bind all the components associated + * with the master. Interface ports are added before the encoders in order to + * satisfy their .bind requirements + * See Documentation/devicetree/bindings/graph.txt for the bindings. + * + * Returns zero if successful, or one of the standard error codes if it fails. + */ +int drm_of_component_probe(struct device *dev, + int (*compare_of)(struct device *, void *), + const struct component_master_ops *m_ops) +{ + struct device_node *ep, *port, *remote; + struct component_match *match = NULL; + int i; + + if (!dev->of_node) + return -EINVAL; + + /* + * Bind the crtc's ports first, so that drm_of_find_possible_crtcs() + * called from encoder's .bind callbacks works as expected + */ + for (i = 0; ; i++) { + port = of_parse_phandle(dev->of_node, "ports", i); + if (!port) + break; + + if (!of_device_is_available(port->parent)) { + of_node_put(port); + continue; + } + + component_match_add(dev, &match, compare_of, port); + of_node_put(port); + } + + if (i == 0) { + dev_err(dev, "missing 'ports' property\n"); + return -ENODEV; + } + + if (!match) { + dev_err(dev, "no available port\n"); + return -ENODEV; + } + + /* + * For bound crtcs, bind the encoders attached to their remote endpoint + */ + for (i = 0; ; i++) { + port = of_parse_phandle(dev->of_node, "ports", i); + if (!port) + break; + + if (!of_device_is_available(port->parent)) { + of_node_put(port); + continue; + } + + for_each_child_of_node(port, ep) { + remote = of_graph_get_remote_port_parent(ep); + if (!remote || !of_device_is_available(remote)) { + of_node_put(remote); + continue; + } else if (!of_device_is_available(remote->parent)) { + dev_warn(dev, "parent device of %s is not available\n", + remote->full_name); + of_node_put(remote); + continue; + } + + component_match_add(dev, &match, compare_of, remote); + of_node_put(remote); + } + of_node_put(port); + } + + return component_master_add_with_match(dev, m_ops, match); +} +EXPORT_SYMBOL(drm_of_component_probe); diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c index 1b1bd42b0368..fcd2a86acd2c 100644 --- a/drivers/gpu/drm/drm_pci.c +++ b/drivers/gpu/drm/drm_pci.c @@ -266,6 +266,9 @@ void drm_pci_agp_destroy(struct drm_device *dev) * then register the character device and inter module information. * Try and register, if we fail to register, backout previous work. * + * NOTE: This function is deprecated, please use drm_dev_alloc() and + * drm_dev_register() instead and remove your ->load() callback. + * * Return: 0 on success or a negative error code on failure. */ int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent, @@ -326,6 +329,10 @@ EXPORT_SYMBOL(drm_get_pci_dev); * Initializes a drm_device structures, registering the stubs and initializing * the AGP device. * + * NOTE: This function is deprecated. Modern modesetting drm drivers should use + * pci_register_driver() directly, this function only provides shadow-binding + * support for old legacy drivers on top of that core pci function. + * * Return: 0 on success or a negative error code on failure. */ int drm_pci_init(struct drm_driver *driver, struct pci_driver *pdriver) @@ -435,6 +442,10 @@ EXPORT_SYMBOL(drm_pci_init); * * Unregisters one or more devices matched by a PCI driver from the DRM * subsystem. + * + * NOTE: This function is deprecated. Modern modesetting drm drivers should use + * pci_unregister_driver() directly, this function only provides shadow-binding + * support for old legacy drivers on top of that core pci function. */ void drm_pci_exit(struct drm_driver *driver, struct pci_driver *pdriver) { diff --git a/drivers/gpu/drm/drm_platform.c b/drivers/gpu/drm/drm_platform.c index 5314c9d5fef4..644169e1a029 100644 --- a/drivers/gpu/drm/drm_platform.c +++ b/drivers/gpu/drm/drm_platform.c @@ -95,6 +95,9 @@ EXPORT_SYMBOL(drm_platform_set_busid); * subsystem, initializing a drm_device structure and calling the driver's * .load() function. * + * NOTE: This function is deprecated, please use drm_dev_alloc() and + * drm_dev_register() instead and remove your ->load() callback. + * * Return: 0 on success or a negative error code on failure. */ int drm_platform_init(struct drm_driver *driver, struct platform_device *platform_device) diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c index d734780b31c0..a18164f2f6d2 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c @@ -94,7 +94,18 @@ static int drm_helper_probe_add_cmdline_mode(struct drm_connector *connector) } #define DRM_OUTPUT_POLL_PERIOD (10*HZ) -static void __drm_kms_helper_poll_enable(struct drm_device *dev) +/** + * drm_kms_helper_poll_enable_locked - re-enable output polling. + * @dev: drm_device + * + * This function re-enables the output polling work without + * locking the mode_config mutex. + * + * This is like drm_kms_helper_poll_enable() however it is to be + * called from a context where the mode_config mutex is locked + * already. + */ +void drm_kms_helper_poll_enable_locked(struct drm_device *dev) { bool poll = false; struct drm_connector *connector; @@ -113,6 +124,8 @@ static void __drm_kms_helper_poll_enable(struct drm_device *dev) if (poll) schedule_delayed_work(&dev->mode_config.output_poll_work, DRM_OUTPUT_POLL_PERIOD); } +EXPORT_SYMBOL(drm_kms_helper_poll_enable_locked); + static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connector *connector, uint32_t maxX, uint32_t maxY, bool merge_type_bits) @@ -174,7 +187,7 @@ static int drm_helper_probe_single_connector_modes_merge_bits(struct drm_connect /* Re-enable polling in case the global poll config changed. */ if (drm_kms_helper_poll != dev->mode_config.poll_running) - __drm_kms_helper_poll_enable(dev); + drm_kms_helper_poll_enable_locked(dev); dev->mode_config.poll_running = drm_kms_helper_poll; @@ -428,7 +441,7 @@ EXPORT_SYMBOL(drm_kms_helper_poll_disable); void drm_kms_helper_poll_enable(struct drm_device *dev) { mutex_lock(&dev->mode_config.mutex); - __drm_kms_helper_poll_enable(dev); + drm_kms_helper_poll_enable_locked(dev); mutex_unlock(&dev->mode_config.mutex); } EXPORT_SYMBOL(drm_kms_helper_poll_enable); diff --git a/drivers/gpu/drm/drm_rect.c b/drivers/gpu/drm/drm_rect.c index 631f5afd451c..531ac4cc9756 100644 --- a/drivers/gpu/drm/drm_rect.c +++ b/drivers/gpu/drm/drm_rect.c @@ -330,7 +330,7 @@ void drm_rect_rotate(struct drm_rect *r, } } - switch (rotation & 0xf) { + switch (rotation & DRM_ROTATE_MASK) { case BIT(DRM_ROTATE_0): break; case BIT(DRM_ROTATE_90): @@ -390,7 +390,7 @@ void drm_rect_rotate_inv(struct drm_rect *r, { struct drm_rect tmp; - switch (rotation & 0xf) { + switch (rotation & DRM_ROTATE_MASK) { case BIT(DRM_ROTATE_0): break; case BIT(DRM_ROTATE_90): diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c index f08873f6489c..615b7e667320 100644 --- a/drivers/gpu/drm/drm_sysfs.c +++ b/drivers/gpu/drm/drm_sysfs.c @@ -230,18 +230,12 @@ static ssize_t dpms_show(struct device *device, char *buf) { struct drm_connector *connector = to_drm_connector(device); - struct drm_device *dev = connector->dev; - uint64_t dpms_status; - int ret; + int dpms; - ret = drm_object_property_get_value(&connector->base, - dev->mode_config.dpms_property, - &dpms_status); - if (ret) - return 0; + dpms = READ_ONCE(connector->dpms); return snprintf(buf, PAGE_SIZE, "%s\n", - drm_get_dpms_name((int)dpms_status)); + drm_get_dpms_name(dpms)); } static ssize_t enabled_show(struct device *device, diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c index aab49ee4ed40..f90bd5fe35ba 100644 --- a/drivers/gpu/drm/drm_vm.c +++ b/drivers/gpu/drm/drm_vm.c @@ -95,7 +95,7 @@ static pgprot_t drm_dma_prot(uint32_t map_type, struct vm_area_struct *vma) * Find the right map and if it's AGP memory find the real physical page to * map, get the page, increment the use count and return it. */ -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) static int drm_do_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) { struct drm_file *priv = vma->vm_file->private_data; @@ -168,12 +168,12 @@ static int drm_do_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) vm_fault_error: return VM_FAULT_SIGBUS; /* Disallow mremap */ } -#else /* __OS_HAS_AGP */ +#else static int drm_do_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) { return VM_FAULT_SIGBUS; } -#endif /* __OS_HAS_AGP */ +#endif /** * \c nopage method for shared virtual memory. @@ -556,7 +556,7 @@ static int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma) * --BenH. */ if (!vma->vm_pgoff -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) && (!dev->agp || dev->agp->agp_info.device->vendor != PCI_VENDOR_ID_APPLE) #endif diff --git a/drivers/gpu/drm/drm_vma_manager.c b/drivers/gpu/drm/drm_vma_manager.c index 68c1f32fb086..2f2ecde8285b 100644 --- a/drivers/gpu/drm/drm_vma_manager.c +++ b/drivers/gpu/drm/drm_vma_manager.c @@ -112,7 +112,7 @@ void drm_vma_offset_manager_destroy(struct drm_vma_offset_manager *mgr) EXPORT_SYMBOL(drm_vma_offset_manager_destroy); /** - * drm_vma_offset_lookup() - Find node in offset space + * drm_vma_offset_lookup_locked() - Find node in offset space * @mgr: Manager object * @start: Start address for object (page-based) * @pages: Size of object (page-based) @@ -122,37 +122,21 @@ EXPORT_SYMBOL(drm_vma_offset_manager_destroy); * region and the given node will be returned, as long as the node spans the * whole requested area (given the size in number of pages as @pages). * - * RETURNS: - * Returns NULL if no suitable node can be found. Otherwise, the best match - * is returned. It's the caller's responsibility to make sure the node doesn't - * get destroyed before the caller can access it. - */ -struct drm_vma_offset_node *drm_vma_offset_lookup(struct drm_vma_offset_manager *mgr, - unsigned long start, - unsigned long pages) -{ - struct drm_vma_offset_node *node; - - read_lock(&mgr->vm_lock); - node = drm_vma_offset_lookup_locked(mgr, start, pages); - read_unlock(&mgr->vm_lock); - - return node; -} -EXPORT_SYMBOL(drm_vma_offset_lookup); - -/** - * drm_vma_offset_lookup_locked() - Find node in offset space - * @mgr: Manager object - * @start: Start address for object (page-based) - * @pages: Size of object (page-based) + * Note that before lookup the vma offset manager lookup lock must be acquired + * with drm_vma_offset_lock_lookup(). See there for an example. This can then be + * used to implement weakly referenced lookups using kref_get_unless_zero(). * - * Same as drm_vma_offset_lookup() but requires the caller to lock offset lookup - * manually. See drm_vma_offset_lock_lookup() for an example. + * Example: + * drm_vma_offset_lock_lookup(mgr); + * node = drm_vma_offset_lookup_locked(mgr); + * if (node) + * kref_get_unless_zero(container_of(node, sth, entr)); + * drm_vma_offset_unlock_lookup(mgr); * * RETURNS: * Returns NULL if no suitable node can be found. Otherwise, the best match - * is returned. + * is returned. It's the caller's responsibility to make sure the node doesn't + * get destroyed before the caller can access it. */ struct drm_vma_offset_node *drm_vma_offset_lookup_locked(struct drm_vma_offset_manager *mgr, unsigned long start, diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig index bd1a4156f647..96e86cf4455b 100644 --- a/drivers/gpu/drm/exynos/Kconfig +++ b/drivers/gpu/drm/exynos/Kconfig @@ -11,43 +11,59 @@ config DRM_EXYNOS Choose this option if you have a Samsung SoC EXYNOS chipset. If M is selected the module will be called exynosdrm. +if DRM_EXYNOS + config DRM_EXYNOS_IOMMU bool - depends on DRM_EXYNOS && EXYNOS_IOMMU && ARM_DMA_USE_IOMMU + depends on EXYNOS_IOMMU && ARM_DMA_USE_IOMMU default y +comment "CRTCs" + config DRM_EXYNOS_FIMD - bool "Exynos DRM FIMD" - depends on DRM_EXYNOS && !FB_S3C + bool "FIMD" + depends on !FB_S3C select FB_MODE_HELPERS select MFD_SYSCON help Choose this option if you want to use Exynos FIMD for DRM. config DRM_EXYNOS5433_DECON - bool "Exynos5433 DRM DECON" - depends on DRM_EXYNOS + bool "DECON on Exynos5433" help Choose this option if you want to use Exynos5433 DECON for DRM. config DRM_EXYNOS7_DECON - bool "Exynos7 DRM DECON" - depends on DRM_EXYNOS && !FB_S3C + bool "DECON on Exynos7" + depends on !FB_S3C select FB_MODE_HELPERS help Choose this option if you want to use Exynos DECON for DRM. +config DRM_EXYNOS_MIXER + bool "Mixer" + depends on !VIDEO_SAMSUNG_S5P_TV + help + Choose this option if you want to use Exynos Mixer for DRM. + +config DRM_EXYNOS_VIDI + bool "Virtual Display" + help + Choose this option if you want to use Exynos VIDI for DRM. + +comment "Encoders and Bridges" + config DRM_EXYNOS_DPI - bool "EXYNOS DRM parallel output support" - depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) + bool "Parallel output" + depends on DRM_EXYNOS_FIMD select DRM_PANEL default n help This enables support for Exynos parallel output. config DRM_EXYNOS_DSI - bool "EXYNOS DRM MIPI-DSI driver support" - depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS5433_DECON || DRM_EXYNOS7_DECON) + bool "MIPI-DSI host" + depends on DRM_EXYNOS_FIMD || DRM_EXYNOS5433_DECON || DRM_EXYNOS7_DECON select DRM_MIPI_DSI select DRM_PANEL default n @@ -55,58 +71,55 @@ config DRM_EXYNOS_DSI This enables support for Exynos MIPI-DSI device. config DRM_EXYNOS_DP - bool "EXYNOS DRM DP driver support" - depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON) + bool "Display Port" + depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON default DRM_EXYNOS select DRM_PANEL help This enables support for DP device. config DRM_EXYNOS_HDMI - bool "Exynos DRM HDMI" - depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_TV + bool "HDMI" + depends on !VIDEO_SAMSUNG_S5P_TV && (DRM_EXYNOS_MIXER || DRM_EXYNOS5433_DECON) help Choose this option if you want to use Exynos HDMI for DRM. -config DRM_EXYNOS_VIDI - bool "Exynos DRM Virtual Display" - depends on DRM_EXYNOS +config DRM_EXYNOS_MIC + bool "Mobile Image Compressor" + depends on DRM_EXYNOS5433_DECON help - Choose this option if you want to use Exynos VIDI for DRM. + Choose this option if you want to use Exynos MIC for DRM. + +comment "Sub-drivers" config DRM_EXYNOS_G2D - bool "Exynos DRM G2D" - depends on DRM_EXYNOS && !VIDEO_SAMSUNG_S5P_G2D + bool "G2D" + depends on !VIDEO_SAMSUNG_S5P_G2D select FRAME_VECTOR help Choose this option if you want to use Exynos G2D for DRM. config DRM_EXYNOS_IPP - bool "Exynos DRM IPP" - depends on DRM_EXYNOS + bool "Image Post Processor" help Choose this option if you want to use IPP feature for DRM. config DRM_EXYNOS_FIMC - bool "Exynos DRM FIMC" + bool "FIMC" depends on DRM_EXYNOS_IPP && MFD_SYSCON help Choose this option if you want to use Exynos FIMC for DRM. config DRM_EXYNOS_ROTATOR - bool "Exynos DRM Rotator" + bool "Rotator" depends on DRM_EXYNOS_IPP help Choose this option if you want to use Exynos Rotator for DRM. config DRM_EXYNOS_GSC - bool "Exynos DRM GSC" + bool "GScaler" depends on DRM_EXYNOS_IPP && ARCH_EXYNOS5 && !ARCH_MULTIPLATFORM help Choose this option if you want to use Exynos GSC for DRM. -config DRM_EXYNOS_MIC - bool "Exynos DRM MIC" - depends on (DRM_EXYNOS && DRM_EXYNOS5433_DECON) - help - Choose this option if you want to use Exynos MIC for DRM. +endif diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile index 02aecfed6354..6496532aaa91 100644 --- a/drivers/gpu/drm/exynos/Makefile +++ b/drivers/gpu/drm/exynos/Makefile @@ -14,7 +14,8 @@ exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON) += exynos7_drm_decon.o exynosdrm-$(CONFIG_DRM_EXYNOS_DPI) += exynos_drm_dpi.o exynosdrm-$(CONFIG_DRM_EXYNOS_DSI) += exynos_drm_dsi.o exynosdrm-$(CONFIG_DRM_EXYNOS_DP) += exynos_dp_core.o exynos_dp_reg.o -exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o exynos_mixer.o +exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER) += exynos_mixer.o +exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI) += exynos_hdmi.o exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o exynosdrm-$(CONFIG_DRM_EXYNOS_G2D) += exynos_drm_g2d.o exynosdrm-$(CONFIG_DRM_EXYNOS_IPP) += exynos_drm_ipp.o diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c index b3c730770b0f..fbe1b3174f75 100644 --- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c @@ -13,6 +13,7 @@ #include <linux/platform_device.h> #include <linux/clk.h> #include <linux/component.h> +#include <linux/of_device.h> #include <linux/of_gpio.h> #include <linux/pm_runtime.h> @@ -24,28 +25,11 @@ #include "exynos_drm_iommu.h" #define WINDOWS_NR 3 +#define CURSOR_WIN 2 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 -struct decon_context { - struct device *dev; - struct drm_device *drm_dev; - struct exynos_drm_crtc *crtc; - struct exynos_drm_plane planes[WINDOWS_NR]; - void __iomem *addr; - struct clk *clks[6]; - unsigned int default_win; - unsigned long irq_flags; - int pipe; - bool suspended; - -#define BIT_CLKS_ENABLED 0 -#define BIT_IRQS_ENABLED 1 - unsigned long enabled; - bool i80_if; - atomic_t win_updated; -}; - static const char * const decon_clks_name[] = { + "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", @@ -54,6 +38,32 @@ static const char * const decon_clks_name[] = { "sclk_decon_eclk", }; +enum decon_iftype { + IFTYPE_RGB, + IFTYPE_I80, + IFTYPE_HDMI +}; + +enum decon_flag_bits { + BIT_CLKS_ENABLED, + BIT_IRQS_ENABLED, + BIT_WIN_UPDATED, + BIT_SUSPENDED +}; + +struct decon_context { + struct device *dev; + struct drm_device *drm_dev; + struct exynos_drm_crtc *crtc; + struct exynos_drm_plane planes[WINDOWS_NR]; + void __iomem *addr; + struct clk *clks[ARRAY_SIZE(decon_clks_name)]; + int pipe; + unsigned long flags; + enum decon_iftype out_type; + int first_win; +}; + static const uint32_t decon_formats[] = { DRM_FORMAT_XRGB1555, DRM_FORMAT_RGB565, @@ -61,17 +71,24 @@ static const uint32_t decon_formats[] = { DRM_FORMAT_ARGB8888, }; +static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask, + u32 val) +{ + val = (val & mask) | (readl(ctx->addr + reg) & ~mask); + writel(val, ctx->addr + reg); +} + static int decon_enable_vblank(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; u32 val; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return -EPERM; - if (test_and_set_bit(0, &ctx->irq_flags)) { + if (test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) { val = VIDINTCON0_INTEN; - if (ctx->i80_if) + if (ctx->out_type == IFTYPE_I80) val |= VIDINTCON0_FRAMEDONE; else val |= VIDINTCON0_INTFRMEN; @@ -86,79 +103,85 @@ static void decon_disable_vblank(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; - if (test_and_clear_bit(0, &ctx->irq_flags)) + if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) writel(0, ctx->addr + DECON_VIDINTCON0); } static void decon_setup_trigger(struct decon_context *ctx) { - u32 val = TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | - TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN; + u32 val = (ctx->out_type != IFTYPE_HDMI) + ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | + TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN + : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | + TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB; writel(val, ctx->addr + DECON_TRIGCON); } static void decon_commit(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; - struct drm_display_mode *mode = &crtc->base.mode; + struct drm_display_mode *m = &crtc->base.mode; u32 val; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; + if (ctx->out_type == IFTYPE_HDMI) { + m->crtc_hsync_start = m->crtc_hdisplay + 10; + m->crtc_hsync_end = m->crtc_htotal - 92; + m->crtc_vsync_start = m->crtc_vdisplay + 1; + m->crtc_vsync_end = m->crtc_vsync_start + 1; + } + + decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0); + /* enable clock gate */ val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F; writel(val, ctx->addr + DECON_CMU); /* lcd on and use command if */ val = VIDOUT_LCD_ON; - if (ctx->i80_if) + if (ctx->out_type == IFTYPE_I80) val |= VIDOUT_COMMAND_IF; else val |= VIDOUT_RGB_IF; writel(val, ctx->addr + DECON_VIDOUTCON0); - val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | - VIDTCON2_HOZVAL(mode->hdisplay - 1); + val = VIDTCON2_LINEVAL(m->vdisplay - 1) | + VIDTCON2_HOZVAL(m->hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON2); - if (!ctx->i80_if) { + if (ctx->out_type != IFTYPE_I80) { val = VIDTCON00_VBPD_F( - mode->crtc_vtotal - mode->crtc_vsync_end) | + m->crtc_vtotal - m->crtc_vsync_end - 1) | VIDTCON00_VFPD_F( - mode->crtc_vsync_start - mode->crtc_vdisplay); + m->crtc_vsync_start - m->crtc_vdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON00); val = VIDTCON01_VSPW_F( - mode->crtc_vsync_end - mode->crtc_vsync_start); + m->crtc_vsync_end - m->crtc_vsync_start - 1); writel(val, ctx->addr + DECON_VIDTCON01); val = VIDTCON10_HBPD_F( - mode->crtc_htotal - mode->crtc_hsync_end) | + m->crtc_htotal - m->crtc_hsync_end - 1) | VIDTCON10_HFPD_F( - mode->crtc_hsync_start - mode->crtc_hdisplay); + m->crtc_hsync_start - m->crtc_hdisplay - 1); writel(val, ctx->addr + DECON_VIDTCON10); val = VIDTCON11_HSPW_F( - mode->crtc_hsync_end - mode->crtc_hsync_start); + m->crtc_hsync_end - m->crtc_hsync_start - 1); writel(val, ctx->addr + DECON_VIDTCON11); } decon_setup_trigger(ctx); /* enable output and display signal */ - val = VIDCON0_ENVID | VIDCON0_ENVID_F; - writel(val, ctx->addr + DECON_VIDCON0); + decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0); } -#define COORDINATE_X(x) (((x) & 0xfff) << 12) -#define COORDINATE_Y(x) ((x) & 0xfff) -#define OFFSIZE(x) (((x) & 0x3fff) << 14) -#define PAGEWIDTH(x) ((x) & 0x3fff) - static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, struct drm_framebuffer *fb) { @@ -214,16 +237,8 @@ static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win, static void decon_shadow_protect_win(struct decon_context *ctx, int win, bool protect) { - u32 val; - - val = readl(ctx->addr + DECON_SHADOWCON); - - if (protect) - val |= SHADOWCON_Wx_PROTECT(win); - else - val &= ~SHADOWCON_Wx_PROTECT(win); - - writel(val, ctx->addr + DECON_SHADOWCON); + decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win), + protect ? ~0 : 0); } static void decon_atomic_begin(struct exynos_drm_crtc *crtc, @@ -231,12 +246,16 @@ static void decon_atomic_begin(struct exynos_drm_crtc *crtc, { struct decon_context *ctx = crtc->ctx; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; decon_shadow_protect_win(ctx, plane->zpos, true); } +#define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s)) +#define COORDINATE_X(x) BIT_VAL((x), 23, 12) +#define COORDINATE_Y(x) BIT_VAL((x), 11, 0) + static void decon_update_plane(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane) { @@ -247,7 +266,7 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, unsigned int pitch = state->fb->pitches[0]; u32 val; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; val = COORDINATE_X(plane->crtc_x) | COORDINATE_Y(plane->crtc_y); @@ -270,21 +289,21 @@ static void decon_update_plane(struct exynos_drm_crtc *crtc, val = plane->dma_addr[0] + pitch * plane->crtc_h; writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); - val = OFFSIZE(pitch - plane->crtc_w * bpp) - | PAGEWIDTH(plane->crtc_w * bpp); + if (ctx->out_type != IFTYPE_HDMI) + val = BIT_VAL(pitch - plane->crtc_w * bpp, 27, 14) + | BIT_VAL(plane->crtc_w * bpp, 13, 0); + else + val = BIT_VAL(pitch - plane->crtc_w * bpp, 29, 15) + | BIT_VAL(plane->crtc_w * bpp, 14, 0); writel(val, ctx->addr + DECON_VIDW0xADD2(win)); decon_win_set_pixfmt(ctx, win, state->fb); /* window enable */ - val = readl(ctx->addr + DECON_WINCONx(win)); - val |= WINCONx_ENWIN_F; - writel(val, ctx->addr + DECON_WINCONx(win)); + decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0); /* standalone update */ - val = readl(ctx->addr + DECON_UPDATE); - val |= STANDALONE_UPDATE_F; - writel(val, ctx->addr + DECON_UPDATE); + decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } static void decon_disable_plane(struct exynos_drm_crtc *crtc, @@ -292,24 +311,19 @@ static void decon_disable_plane(struct exynos_drm_crtc *crtc, { struct decon_context *ctx = crtc->ctx; unsigned int win = plane->zpos; - u32 val; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; decon_shadow_protect_win(ctx, win, true); /* window disable */ - val = readl(ctx->addr + DECON_WINCONx(win)); - val &= ~WINCONx_ENWIN_F; - writel(val, ctx->addr + DECON_WINCONx(win)); + decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); decon_shadow_protect_win(ctx, win, false); /* standalone update */ - val = readl(ctx->addr + DECON_UPDATE); - val |= STANDALONE_UPDATE_F; - writel(val, ctx->addr + DECON_UPDATE); + decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } static void decon_atomic_flush(struct exynos_drm_crtc *crtc, @@ -317,13 +331,13 @@ static void decon_atomic_flush(struct exynos_drm_crtc *crtc, { struct decon_context *ctx = crtc->ctx; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; decon_shadow_protect_win(ctx, plane->zpos, false); - if (ctx->i80_if) - atomic_set(&ctx->win_updated, 1); + if (ctx->out_type == IFTYPE_I80) + set_bit(BIT_WIN_UPDATED, &ctx->flags); } static void decon_swreset(struct decon_context *ctx) @@ -347,6 +361,17 @@ static void decon_swreset(struct decon_context *ctx) } WARN(tries == 0, "failed to software reset DECON\n"); + + if (ctx->out_type != IFTYPE_HDMI) + return; + + writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); + decon_set_bits(ctx, DECON_CMU, + CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0); + writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); + writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, + ctx->addr + DECON_CRCCTRL); + decon_setup_trigger(ctx); } static void decon_enable(struct exynos_drm_crtc *crtc) @@ -355,11 +380,9 @@ static void decon_enable(struct exynos_drm_crtc *crtc) int ret; int i; - if (!ctx->suspended) + if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags)) return; - ctx->suspended = false; - pm_runtime_get_sync(ctx->dev); for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { @@ -368,10 +391,10 @@ static void decon_enable(struct exynos_drm_crtc *crtc) goto err; } - set_bit(BIT_CLKS_ENABLED, &ctx->enabled); + set_bit(BIT_CLKS_ENABLED, &ctx->flags); /* if vblank was enabled status, enable it again. */ - if (test_and_clear_bit(0, &ctx->irq_flags)) + if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags)) decon_enable_vblank(ctx->crtc); decon_commit(ctx->crtc); @@ -381,7 +404,7 @@ err: while (--i >= 0) clk_disable_unprepare(ctx->clks[i]); - ctx->suspended = true; + set_bit(BIT_SUSPENDED, &ctx->flags); } static void decon_disable(struct exynos_drm_crtc *crtc) @@ -389,7 +412,7 @@ static void decon_disable(struct exynos_drm_crtc *crtc) struct decon_context *ctx = crtc->ctx; int i; - if (ctx->suspended) + if (test_bit(BIT_SUSPENDED, &ctx->flags)) return; /* @@ -397,7 +420,7 @@ static void decon_disable(struct exynos_drm_crtc *crtc) * suspend that connector. Otherwise we might try to scan from * a destroyed buffer later. */ - for (i = 0; i < WINDOWS_NR; i++) + for (i = ctx->first_win; i < WINDOWS_NR; i++) decon_disable_plane(crtc, &ctx->planes[i]); decon_swreset(ctx); @@ -405,27 +428,22 @@ static void decon_disable(struct exynos_drm_crtc *crtc) for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) clk_disable_unprepare(ctx->clks[i]); - clear_bit(BIT_CLKS_ENABLED, &ctx->enabled); + clear_bit(BIT_CLKS_ENABLED, &ctx->flags); pm_runtime_put_sync(ctx->dev); - ctx->suspended = true; + set_bit(BIT_SUSPENDED, &ctx->flags); } void decon_te_irq_handler(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; - u32 val; - if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) + if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) return; - if (atomic_add_unless(&ctx->win_updated, -1, 0)) { - /* trigger */ - val = readl(ctx->addr + DECON_TRIGCON); - val |= TRIGCON_SWTRIGCMD; - writel(val, ctx->addr + DECON_TRIGCON); - } + if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags)) + decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0); drm_crtc_handle_vblank(&ctx->crtc->base); } @@ -434,7 +452,6 @@ static void decon_clear_channels(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; int win, i, ret; - u32 val; DRM_DEBUG_KMS("%s\n", __FILE__); @@ -445,25 +462,10 @@ static void decon_clear_channels(struct exynos_drm_crtc *crtc) } for (win = 0; win < WINDOWS_NR; win++) { - /* shadow update disable */ - val = readl(ctx->addr + DECON_SHADOWCON); - val |= SHADOWCON_Wx_PROTECT(win); - writel(val, ctx->addr + DECON_SHADOWCON); - - /* window disable */ - val = readl(ctx->addr + DECON_WINCONx(win)); - val &= ~WINCONx_ENWIN_F; - writel(val, ctx->addr + DECON_WINCONx(win)); - - /* shadow update enable */ - val = readl(ctx->addr + DECON_SHADOWCON); - val &= ~SHADOWCON_Wx_PROTECT(win); - writel(val, ctx->addr + DECON_SHADOWCON); - - /* standalone update */ - val = readl(ctx->addr + DECON_UPDATE); - val |= STANDALONE_UPDATE_F; - writel(val, ctx->addr + DECON_UPDATE); + decon_shadow_protect_win(ctx, win, true); + decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0); + decon_shadow_protect_win(ctx, win, false); + decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0); } /* TODO: wait for possible vsync */ msleep(50); @@ -479,7 +481,6 @@ static struct exynos_drm_crtc_ops decon_crtc_ops = { .commit = decon_commit, .enable_vblank = decon_enable_vblank, .disable_vblank = decon_disable_vblank, - .commit = decon_commit, .atomic_begin = decon_atomic_begin, .update_plane = decon_update_plane, .disable_plane = decon_disable_plane, @@ -493,26 +494,30 @@ static int decon_bind(struct device *dev, struct device *master, void *data) struct drm_device *drm_dev = data; struct exynos_drm_private *priv = drm_dev->dev_private; struct exynos_drm_plane *exynos_plane; + enum exynos_drm_output_type out_type; enum drm_plane_type type; - unsigned int zpos; + unsigned int win; int ret; ctx->drm_dev = drm_dev; ctx->pipe = priv->pipe++; - for (zpos = 0; zpos < WINDOWS_NR; zpos++) { - type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : - DRM_PLANE_TYPE_OVERLAY; - ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], + for (win = ctx->first_win; win < WINDOWS_NR; win++) { + int tmp = (win == ctx->first_win) ? 0 : win; + + type = exynos_plane_get_type(tmp, CURSOR_WIN); + ret = exynos_plane_init(drm_dev, &ctx->planes[win], 1 << ctx->pipe, type, decon_formats, - ARRAY_SIZE(decon_formats), zpos); + ARRAY_SIZE(decon_formats), win); if (ret) return ret; } - exynos_plane = &ctx->planes[ctx->default_win]; + exynos_plane = &ctx->planes[ctx->first_win]; + out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI + : EXYNOS_DISPLAY_TYPE_LCD; ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, - ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, + ctx->pipe, out_type, &decon_crtc_ops, ctx); if (IS_ERR(ctx->crtc)) { ret = PTR_ERR(ctx->crtc); @@ -546,38 +551,20 @@ static const struct component_ops decon_component_ops = { .unbind = decon_unbind, }; -static irqreturn_t decon_vsync_irq_handler(int irq, void *dev_id) -{ - struct decon_context *ctx = dev_id; - u32 val; - - if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) - goto out; - - val = readl(ctx->addr + DECON_VIDINTCON1); - if (val & VIDINTCON1_INTFRMPEND) { - drm_crtc_handle_vblank(&ctx->crtc->base); - - /* clear */ - writel(VIDINTCON1_INTFRMPEND, ctx->addr + DECON_VIDINTCON1); - } - -out: - return IRQ_HANDLED; -} - -static irqreturn_t decon_lcd_sys_irq_handler(int irq, void *dev_id) +static irqreturn_t decon_irq_handler(int irq, void *dev_id) { struct decon_context *ctx = dev_id; u32 val; int win; - if (!test_bit(BIT_CLKS_ENABLED, &ctx->enabled)) + if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags)) goto out; val = readl(ctx->addr + DECON_VIDINTCON1); - if (val & VIDINTCON1_INTFRMDONEPEND) { - for (win = 0 ; win < WINDOWS_NR ; win++) { + val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND; + + if (val) { + for (win = ctx->first_win; win < WINDOWS_NR ; win++) { struct exynos_drm_plane *plane = &ctx->planes[win]; if (!plane->pending_fb) @@ -587,16 +574,29 @@ static irqreturn_t decon_lcd_sys_irq_handler(int irq, void *dev_id) } /* clear */ - writel(VIDINTCON1_INTFRMDONEPEND, - ctx->addr + DECON_VIDINTCON1); + writel(val, ctx->addr + DECON_VIDINTCON1); } out: return IRQ_HANDLED; } +static const struct of_device_id exynos5433_decon_driver_dt_match[] = { + { + .compatible = "samsung,exynos5433-decon", + .data = (void *)IFTYPE_RGB + }, + { + .compatible = "samsung,exynos5433-decon-tv", + .data = (void *)IFTYPE_HDMI + }, + {}, +}; +MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); + static int exynos5433_decon_probe(struct platform_device *pdev) { + const struct of_device_id *of_id; struct device *dev = &pdev->dev; struct decon_context *ctx; struct resource *res; @@ -607,11 +607,16 @@ static int exynos5433_decon_probe(struct platform_device *pdev) if (!ctx) return -ENOMEM; - ctx->default_win = 0; - ctx->suspended = true; + __set_bit(BIT_SUSPENDED, &ctx->flags); ctx->dev = dev; - if (of_get_child_by_name(dev->of_node, "i80-if-timings")) - ctx->i80_if = true; + + of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev); + ctx->out_type = (enum decon_iftype)of_id->data; + + if (ctx->out_type == IFTYPE_HDMI) + ctx->first_win = 1; + else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) + ctx->out_type = IFTYPE_I80; for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) { struct clk *clk; @@ -636,15 +641,14 @@ static int exynos5433_decon_probe(struct platform_device *pdev) } res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, - ctx->i80_if ? "lcd_sys" : "vsync"); + (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync"); if (!res) { dev_err(dev, "cannot find IRQ resource\n"); return -ENXIO; } - ret = devm_request_irq(dev, res->start, ctx->i80_if ? - decon_lcd_sys_irq_handler : decon_vsync_irq_handler, 0, - "drm_decon", ctx); + ret = devm_request_irq(dev, res->start, decon_irq_handler, 0, + "drm_decon", ctx); if (ret < 0) { dev_err(dev, "lcd_sys irq request failed\n"); return ret; @@ -675,12 +679,6 @@ static int exynos5433_decon_remove(struct platform_device *pdev) return 0; } -static const struct of_device_id exynos5433_decon_driver_dt_match[] = { - { .compatible = "samsung,exynos5433-decon" }, - {}, -}; -MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match); - struct platform_driver exynos5433_decon_driver = { .probe = exynos5433_decon_probe, .remove = exynos5433_decon_remove, diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c index cbdb78ef3bac..ead2b16e237d 100644 --- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c +++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c @@ -37,10 +37,10 @@ * DECON stands for Display and Enhancement controller. */ -#define DECON_DEFAULT_FRAMERATE 60 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 #define WINDOWS_NR 2 +#define CURSOR_WIN 1 struct decon_context { struct device *dev; @@ -52,7 +52,6 @@ struct decon_context { struct clk *eclk; struct clk *vclk; void __iomem *regs; - unsigned int default_win; unsigned long irq_flags; bool i80_if; bool suspended; @@ -165,16 +164,6 @@ static u32 decon_calc_clkdiv(struct decon_context *ctx, return (clkdiv < 0x100) ? clkdiv : 0xff; } -static bool decon_mode_fixup(struct exynos_drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - if (adjusted_mode->vrefresh == 0) - adjusted_mode->vrefresh = DECON_DEFAULT_FRAMERATE; - - return true; -} - static void decon_commit(struct exynos_drm_crtc *crtc) { struct decon_context *ctx = crtc->ctx; @@ -637,7 +626,6 @@ static void decon_disable(struct exynos_drm_crtc *crtc) static const struct exynos_drm_crtc_ops decon_crtc_ops = { .enable = decon_enable, .disable = decon_disable, - .mode_fixup = decon_mode_fixup, .commit = decon_commit, .enable_vblank = decon_enable_vblank, .disable_vblank = decon_disable_vblank, @@ -702,8 +690,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) } for (zpos = 0; zpos < WINDOWS_NR; zpos++) { - type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : - DRM_PLANE_TYPE_OVERLAY; + type = exynos_plane_get_type(zpos, CURSOR_WIN); ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 1 << ctx->pipe, type, decon_formats, ARRAY_SIZE(decon_formats), zpos); @@ -711,7 +698,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data) return ret; } - exynos_plane = &ctx->planes[ctx->default_win]; + exynos_plane = &ctx->planes[DEFAULT_WIN]; ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx); diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c index d66ade0efac8..124fb9a56f02 100644 --- a/drivers/gpu/drm/exynos/exynos_dp_core.c +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c @@ -1383,28 +1383,6 @@ static int exynos_dp_remove(struct platform_device *pdev) return 0; } -#ifdef CONFIG_PM_SLEEP -static int exynos_dp_suspend(struct device *dev) -{ - struct exynos_dp_device *dp = dev_get_drvdata(dev); - - exynos_dp_disable(&dp->encoder); - return 0; -} - -static int exynos_dp_resume(struct device *dev) -{ - struct exynos_dp_device *dp = dev_get_drvdata(dev); - - exynos_dp_enable(&dp->encoder); - return 0; -} -#endif - -static const struct dev_pm_ops exynos_dp_pm_ops = { - SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume) -}; - static const struct of_device_id exynos_dp_match[] = { { .compatible = "samsung,exynos5-dp" }, {}, @@ -1417,7 +1395,6 @@ struct platform_driver dp_driver = { .driver = { .name = "exynos-dp", .owner = THIS_MODULE, - .pm = &exynos_dp_pm_ops, .of_match_table = exynos_dp_match, }, }; diff --git a/drivers/gpu/drm/exynos/exynos_drm_core.c b/drivers/gpu/drm/exynos/exynos_drm_core.c index c68a6a2a9b57..7f55ba6771c6 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_core.c +++ b/drivers/gpu/drm/exynos/exynos_drm_core.c @@ -28,7 +28,6 @@ int exynos_drm_subdrv_register(struct exynos_drm_subdrv *subdrv) return 0; } -EXPORT_SYMBOL_GPL(exynos_drm_subdrv_register); int exynos_drm_subdrv_unregister(struct exynos_drm_subdrv *subdrv) { @@ -39,7 +38,6 @@ int exynos_drm_subdrv_unregister(struct exynos_drm_subdrv *subdrv) return 0; } -EXPORT_SYMBOL_GPL(exynos_drm_subdrv_unregister); int exynos_drm_device_subdrv_probe(struct drm_device *dev) { @@ -69,7 +67,6 @@ int exynos_drm_device_subdrv_probe(struct drm_device *dev) return 0; } -EXPORT_SYMBOL_GPL(exynos_drm_device_subdrv_probe); int exynos_drm_device_subdrv_remove(struct drm_device *dev) { @@ -87,7 +84,6 @@ int exynos_drm_device_subdrv_remove(struct drm_device *dev) return 0; } -EXPORT_SYMBOL_GPL(exynos_drm_device_subdrv_remove); int exynos_drm_subdrv_open(struct drm_device *dev, struct drm_file *file) { @@ -111,7 +107,6 @@ err: } return ret; } -EXPORT_SYMBOL_GPL(exynos_drm_subdrv_open); void exynos_drm_subdrv_close(struct drm_device *dev, struct drm_file *file) { @@ -122,4 +117,3 @@ void exynos_drm_subdrv_close(struct drm_device *dev, struct drm_file *file) subdrv->close(dev, subdrv->dev, file); } } -EXPORT_SYMBOL_GPL(exynos_drm_subdrv_close); diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c index 0872aa2f450f..b3ba27fd9a6b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c @@ -41,27 +41,24 @@ static void exynos_drm_crtc_disable(struct drm_crtc *crtc) exynos_crtc->ops->disable(exynos_crtc); } -static bool -exynos_drm_crtc_mode_fixup(struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) +static void +exynos_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) { struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - if (exynos_crtc->ops->mode_fixup) - return exynos_crtc->ops->mode_fixup(exynos_crtc, mode, - adjusted_mode); - - return true; + if (exynos_crtc->ops->commit) + exynos_crtc->ops->commit(exynos_crtc); } -static void -exynos_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) +static int exynos_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) { struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - if (exynos_crtc->ops->commit) - exynos_crtc->ops->commit(exynos_crtc); + if (exynos_crtc->ops->atomic_check) + return exynos_crtc->ops->atomic_check(exynos_crtc, state); + + return 0; } static void exynos_crtc_atomic_begin(struct drm_crtc *crtc, @@ -99,8 +96,8 @@ static void exynos_crtc_atomic_flush(struct drm_crtc *crtc, static struct drm_crtc_helper_funcs exynos_crtc_helper_funcs = { .enable = exynos_drm_crtc_enable, .disable = exynos_drm_crtc_disable, - .mode_fixup = exynos_drm_crtc_mode_fixup, .mode_set_nofb = exynos_drm_crtc_mode_set_nofb, + .atomic_check = exynos_crtc_atomic_check, .atomic_begin = exynos_crtc_atomic_begin, .atomic_flush = exynos_crtc_atomic_flush, }; @@ -167,7 +164,7 @@ err_crtc: return ERR_PTR(ret); } -int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe) +int exynos_drm_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct exynos_drm_private *private = dev->dev_private; struct exynos_drm_crtc *exynos_crtc = @@ -179,7 +176,7 @@ int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe) return 0; } -void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe) +void exynos_drm_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct exynos_drm_private *private = dev->dev_private; struct exynos_drm_crtc *exynos_crtc = diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.h b/drivers/gpu/drm/exynos/exynos_drm_crtc.h index f87d4abda6f7..f9f365bd0257 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_crtc.h +++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.h @@ -23,8 +23,8 @@ struct exynos_drm_crtc *exynos_drm_crtc_create(struct drm_device *drm_dev, enum exynos_drm_output_type type, const struct exynos_drm_crtc_ops *ops, void *context); -int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int pipe); -void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int pipe); +int exynos_drm_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe); +void exynos_drm_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe); void exynos_drm_crtc_wait_pending_update(struct exynos_drm_crtc *exynos_crtc); void exynos_drm_crtc_finish_update(struct exynos_drm_crtc *exynos_crtc, struct exynos_drm_plane *exynos_plane); diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c index f0a5839bd226..2c6019d6a205 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.c +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c @@ -304,6 +304,7 @@ int exynos_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, return 0; } +#ifdef CONFIG_PM_SLEEP static int exynos_drm_suspend(struct drm_device *dev, pm_message_t state) { struct drm_connector *connector; @@ -340,6 +341,7 @@ static int exynos_drm_resume(struct drm_device *dev) return 0; } +#endif static int exynos_drm_open(struct drm_device *dev, struct drm_file *file) { @@ -403,25 +405,25 @@ static const struct vm_operations_struct exynos_drm_gem_vm_ops = { static const struct drm_ioctl_desc exynos_ioctls[] = { DRM_IOCTL_DEF_DRV(EXYNOS_GEM_CREATE, exynos_drm_gem_create_ioctl, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_GEM_GET, exynos_drm_gem_get_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_VIDI_CONNECTION, vidi_connection_ioctl, - DRM_UNLOCKED | DRM_AUTH), + DRM_AUTH), DRM_IOCTL_DEF_DRV(EXYNOS_G2D_GET_VER, exynos_g2d_get_ver_ioctl, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_G2D_SET_CMDLIST, exynos_g2d_set_cmdlist_ioctl, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_G2D_EXEC, exynos_g2d_exec_ioctl, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_IPP_GET_PROPERTY, exynos_drm_ipp_get_property, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_IPP_SET_PROPERTY, exynos_drm_ipp_set_property, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_IPP_QUEUE_BUF, exynos_drm_ipp_queue_buf, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(EXYNOS_IPP_CMD_CTRL, exynos_drm_ipp_cmd_ctrl, - DRM_UNLOCKED | DRM_AUTH | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), }; static const struct file_operations exynos_drm_driver_fops = { @@ -447,7 +449,7 @@ static struct drm_driver exynos_drm_driver = { .lastclose = exynos_drm_lastclose, .postclose = exynos_drm_postclose, .set_busid = drm_platform_set_busid, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = exynos_drm_crtc_enable_vblank, .disable_vblank = exynos_drm_crtc_disable_vblank, .gem_free_object = exynos_drm_gem_free_object, @@ -527,8 +529,10 @@ static struct platform_driver *const exynos_drm_kms_drivers[] = { #ifdef CONFIG_DRM_EXYNOS_DSI &dsi_driver, #endif -#ifdef CONFIG_DRM_EXYNOS_HDMI +#ifdef CONFIG_DRM_EXYNOS_MIXER &mixer_driver, +#endif +#ifdef CONFIG_DRM_EXYNOS_HDMI &hdmi_driver, #endif #ifdef CONFIG_DRM_EXYNOS_VIDI diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h index b7ba21dfb696..f1eda7fa4e3c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_drv.h +++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h @@ -22,6 +22,8 @@ #define MAX_PLANE 5 #define MAX_FB_BUFFER 4 +#define DEFAULT_WIN 0 + #define to_exynos_crtc(x) container_of(x, struct exynos_drm_crtc, base) #define to_exynos_plane(x) container_of(x, struct exynos_drm_plane, base) @@ -82,12 +84,12 @@ struct exynos_drm_plane { * * @enable: enable the device * @disable: disable the device - * @mode_fixup: fix mode data before applying it * @commit: set current hw specific display mode to hw. * @enable_vblank: specific driver callback for enabling vblank interrupt. * @disable_vblank: specific driver callback for disabling vblank interrupt. * @wait_for_vblank: wait for vblank interrupt to make sure that * hardware overlay is updated. + * @atomic_check: validate state * @atomic_begin: prepare a window to receive a update * @atomic_flush: mark the end of a window update * @update_plane: apply hardware specific overlay data to registers. @@ -103,13 +105,12 @@ struct exynos_drm_crtc; struct exynos_drm_crtc_ops { void (*enable)(struct exynos_drm_crtc *crtc); void (*disable)(struct exynos_drm_crtc *crtc); - bool (*mode_fixup)(struct exynos_drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode); void (*commit)(struct exynos_drm_crtc *crtc); int (*enable_vblank)(struct exynos_drm_crtc *crtc); void (*disable_vblank)(struct exynos_drm_crtc *crtc); void (*wait_for_vblank)(struct exynos_drm_crtc *crtc); + int (*atomic_check)(struct exynos_drm_crtc *crtc, + struct drm_crtc_state *state); void (*atomic_begin)(struct exynos_drm_crtc *crtc, struct exynos_drm_plane *plane); void (*update_plane)(struct exynos_drm_crtc *crtc, diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c index 084280859589..fcea28bdbc42 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c @@ -32,15 +32,15 @@ * exynos specific framebuffer structure. * * @fb: drm framebuffer obejct. - * @exynos_gem_obj: array of exynos specific gem object containing a gem object. + * @exynos_gem: array of exynos specific gem object containing a gem object. */ struct exynos_drm_fb { - struct drm_framebuffer fb; - struct exynos_drm_gem_obj *exynos_gem_obj[MAX_FB_BUFFER]; + struct drm_framebuffer fb; + struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; }; static int check_fb_gem_memory_type(struct drm_device *drm_dev, - struct exynos_drm_gem_obj *exynos_gem_obj) + struct exynos_drm_gem *exynos_gem) { unsigned int flags; @@ -51,7 +51,7 @@ static int check_fb_gem_memory_type(struct drm_device *drm_dev, if (is_drm_iommu_supported(drm_dev)) return 0; - flags = exynos_gem_obj->flags; + flags = exynos_gem->flags; /* * without iommu support, not support physically non-continuous memory @@ -75,13 +75,13 @@ static void exynos_drm_fb_destroy(struct drm_framebuffer *fb) drm_framebuffer_cleanup(fb); - for (i = 0; i < ARRAY_SIZE(exynos_fb->exynos_gem_obj); i++) { + for (i = 0; i < ARRAY_SIZE(exynos_fb->exynos_gem); i++) { struct drm_gem_object *obj; - if (exynos_fb->exynos_gem_obj[i] == NULL) + if (exynos_fb->exynos_gem[i] == NULL) continue; - obj = &exynos_fb->exynos_gem_obj[i]->base; + obj = &exynos_fb->exynos_gem[i]->base; drm_gem_object_unreference_unlocked(obj); } @@ -96,7 +96,7 @@ static int exynos_drm_fb_create_handle(struct drm_framebuffer *fb, struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); return drm_gem_handle_create(file_priv, - &exynos_fb->exynos_gem_obj[0]->base, handle); + &exynos_fb->exynos_gem[0]->base, handle); } static int exynos_drm_fb_dirty(struct drm_framebuffer *fb, @@ -118,7 +118,7 @@ static struct drm_framebuffer_funcs exynos_drm_fb_funcs = { struct drm_framebuffer * exynos_drm_framebuffer_init(struct drm_device *dev, struct drm_mode_fb_cmd2 *mode_cmd, - struct exynos_drm_gem_obj **gem_obj, + struct exynos_drm_gem **exynos_gem, int count) { struct exynos_drm_fb *exynos_fb; @@ -130,11 +130,11 @@ exynos_drm_framebuffer_init(struct drm_device *dev, return ERR_PTR(-ENOMEM); for (i = 0; i < count; i++) { - ret = check_fb_gem_memory_type(dev, gem_obj[i]); + ret = check_fb_gem_memory_type(dev, exynos_gem[i]); if (ret < 0) goto err; - exynos_fb->exynos_gem_obj[i] = gem_obj[i]; + exynos_fb->exynos_gem[i] = exynos_gem[i]; } drm_helper_mode_fill_fb_struct(&exynos_fb->fb, mode_cmd); @@ -156,7 +156,7 @@ static struct drm_framebuffer * exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd) { - struct exynos_drm_gem_obj *gem_objs[MAX_FB_BUFFER]; + struct exynos_drm_gem *exynos_gem[MAX_FB_BUFFER]; struct drm_gem_object *obj; struct drm_framebuffer *fb; int i; @@ -171,10 +171,10 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, goto err; } - gem_objs[i] = to_exynos_gem_obj(obj); + exynos_gem[i] = to_exynos_gem(obj); } - fb = exynos_drm_framebuffer_init(dev, mode_cmd, gem_objs, i); + fb = exynos_drm_framebuffer_init(dev, mode_cmd, exynos_gem, i); if (IS_ERR(fb)) { ret = PTR_ERR(fb); goto err; @@ -184,27 +184,26 @@ exynos_user_fb_create(struct drm_device *dev, struct drm_file *file_priv, err: while (i--) - drm_gem_object_unreference_unlocked(&gem_objs[i]->base); + drm_gem_object_unreference_unlocked(&exynos_gem[i]->base); return ERR_PTR(ret); } -struct exynos_drm_gem_obj *exynos_drm_fb_gem_obj(struct drm_framebuffer *fb, - int index) +struct exynos_drm_gem *exynos_drm_fb_gem(struct drm_framebuffer *fb, int index) { struct exynos_drm_fb *exynos_fb = to_exynos_fb(fb); - struct exynos_drm_gem_obj *obj; + struct exynos_drm_gem *exynos_gem; if (index >= MAX_FB_BUFFER) return NULL; - obj = exynos_fb->exynos_gem_obj[index]; - if (!obj) + exynos_gem = exynos_fb->exynos_gem[index]; + if (!exynos_gem) return NULL; - DRM_DEBUG_KMS("dma_addr = 0x%lx\n", (unsigned long)obj->dma_addr); + DRM_DEBUG_KMS("dma_addr: 0x%lx\n", (unsigned long)exynos_gem->dma_addr); - return obj; + return exynos_gem; } static void exynos_drm_output_poll_changed(struct drm_device *dev) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h index 85e4445b920e..726a2d44371f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fb.h +++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h @@ -19,12 +19,11 @@ struct drm_framebuffer * exynos_drm_framebuffer_init(struct drm_device *dev, struct drm_mode_fb_cmd2 *mode_cmd, - struct exynos_drm_gem_obj **gem_obj, + struct exynos_drm_gem **exynos_gem, int count); /* get gem object of a drm framebuffer */ -struct exynos_drm_gem_obj *exynos_drm_fb_gem_obj(struct drm_framebuffer *fb, - int index); +struct exynos_drm_gem *exynos_drm_fb_gem(struct drm_framebuffer *fb, int index); void exynos_drm_mode_config_init(struct drm_device *dev); diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c index a221f753ad9c..f6118baa8e3e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c @@ -30,8 +30,8 @@ drm_fb_helper) struct exynos_drm_fbdev { - struct drm_fb_helper drm_fb_helper; - struct exynos_drm_gem_obj *obj; + struct drm_fb_helper drm_fb_helper; + struct exynos_drm_gem *exynos_gem; }; static int exynos_drm_fb_mmap(struct fb_info *info, @@ -39,7 +39,7 @@ static int exynos_drm_fb_mmap(struct fb_info *info, { struct drm_fb_helper *helper = info->par; struct exynos_drm_fbdev *exynos_fbd = to_exynos_fbdev(helper); - struct exynos_drm_gem_obj *obj = exynos_fbd->obj; + struct exynos_drm_gem *exynos_gem = exynos_fbd->exynos_gem; unsigned long vm_size; int ret; @@ -47,11 +47,12 @@ static int exynos_drm_fb_mmap(struct fb_info *info, vm_size = vma->vm_end - vma->vm_start; - if (vm_size > obj->size) + if (vm_size > exynos_gem->size) return -EINVAL; - ret = dma_mmap_attrs(helper->dev->dev, vma, obj->pages, obj->dma_addr, - obj->size, &obj->dma_attrs); + ret = dma_mmap_attrs(helper->dev->dev, vma, exynos_gem->pages, + exynos_gem->dma_addr, exynos_gem->size, + &exynos_gem->dma_attrs); if (ret < 0) { DRM_ERROR("failed to mmap.\n"); return ret; @@ -75,7 +76,7 @@ static struct fb_ops exynos_drm_fb_ops = { static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes, - struct exynos_drm_gem_obj *obj) + struct exynos_drm_gem *exynos_gem) { struct fb_info *fbi; struct drm_framebuffer *fb = helper->fb; @@ -96,11 +97,11 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, drm_fb_helper_fill_fix(fbi, fb->pitches[0], fb->depth); drm_fb_helper_fill_var(fbi, helper, sizes->fb_width, sizes->fb_height); - nr_pages = obj->size >> PAGE_SHIFT; + nr_pages = exynos_gem->size >> PAGE_SHIFT; - obj->kvaddr = (void __iomem *) vmap(obj->pages, nr_pages, VM_MAP, - pgprot_writecombine(PAGE_KERNEL)); - if (!obj->kvaddr) { + exynos_gem->kvaddr = (void __iomem *) vmap(exynos_gem->pages, nr_pages, + VM_MAP, pgprot_writecombine(PAGE_KERNEL)); + if (!exynos_gem->kvaddr) { DRM_ERROR("failed to map pages to kernel space.\n"); drm_fb_helper_release_fbi(helper); return -EIO; @@ -109,7 +110,7 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, offset = fbi->var.xoffset * (fb->bits_per_pixel >> 3); offset += fbi->var.yoffset * fb->pitches[0]; - fbi->screen_base = obj->kvaddr + offset; + fbi->screen_base = exynos_gem->kvaddr + offset; fbi->screen_size = size; fbi->fix.smem_len = size; @@ -120,7 +121,7 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { struct exynos_drm_fbdev *exynos_fbdev = to_exynos_fbdev(helper); - struct exynos_drm_gem_obj *obj; + struct exynos_drm_gem *exynos_gem; struct drm_device *dev = helper->dev; struct drm_mode_fb_cmd2 mode_cmd = { 0 }; struct platform_device *pdev = dev->platformdev; @@ -141,32 +142,34 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, size = mode_cmd.pitches[0] * mode_cmd.height; - obj = exynos_drm_gem_create(dev, EXYNOS_BO_CONTIG, size); + exynos_gem = exynos_drm_gem_create(dev, EXYNOS_BO_CONTIG, size); /* * If physically contiguous memory allocation fails and if IOMMU is * supported then try to get buffer from non physically contiguous * memory area. */ - if (IS_ERR(obj) && is_drm_iommu_supported(dev)) { + if (IS_ERR(exynos_gem) && is_drm_iommu_supported(dev)) { dev_warn(&pdev->dev, "contiguous FB allocation failed, falling back to non-contiguous\n"); - obj = exynos_drm_gem_create(dev, EXYNOS_BO_NONCONTIG, size); + exynos_gem = exynos_drm_gem_create(dev, EXYNOS_BO_NONCONTIG, + size); } - if (IS_ERR(obj)) { - ret = PTR_ERR(obj); + if (IS_ERR(exynos_gem)) { + ret = PTR_ERR(exynos_gem); goto out; } - exynos_fbdev->obj = obj; + exynos_fbdev->exynos_gem = exynos_gem; - helper->fb = exynos_drm_framebuffer_init(dev, &mode_cmd, &obj, 1); + helper->fb = + exynos_drm_framebuffer_init(dev, &mode_cmd, &exynos_gem, 1); if (IS_ERR(helper->fb)) { DRM_ERROR("failed to create drm framebuffer.\n"); ret = PTR_ERR(helper->fb); goto err_destroy_gem; } - ret = exynos_drm_fbdev_update(helper, sizes, obj); + ret = exynos_drm_fbdev_update(helper, sizes, exynos_gem); if (ret < 0) goto err_destroy_framebuffer; @@ -176,7 +179,7 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, err_destroy_framebuffer: drm_framebuffer_cleanup(helper->fb); err_destroy_gem: - exynos_drm_gem_destroy(obj); + exynos_drm_gem_destroy(exynos_gem); /* * if failed, all resources allocated above would be released by @@ -269,11 +272,11 @@ static void exynos_drm_fbdev_destroy(struct drm_device *dev, struct drm_fb_helper *fb_helper) { struct exynos_drm_fbdev *exynos_fbd = to_exynos_fbdev(fb_helper); - struct exynos_drm_gem_obj *obj = exynos_fbd->obj; + struct exynos_drm_gem *exynos_gem = exynos_fbd->exynos_gem; struct drm_framebuffer *fb; - if (obj->kvaddr) - vunmap(obj->kvaddr); + if (exynos_gem->kvaddr) + vunmap(exynos_gem->kvaddr); /* release drm framebuffer and real buffer */ if (fb_helper->fb && fb_helper->fb->funcs) { diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c index 2a652359af64..c747824f3c98 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c @@ -466,7 +466,7 @@ static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt) EXYNOS_MSCTRL_C_INT_IN_2PLANE); break; default: - dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt); + dev_err(ippdrv->dev, "invalid source yuv order 0x%x.\n", fmt); return -EINVAL; } @@ -513,7 +513,7 @@ static int fimc_src_set_fmt(struct device *dev, u32 fmt) cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420; break; default: - dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt); + dev_err(ippdrv->dev, "invalid source format 0x%x.\n", fmt); return -EINVAL; } @@ -578,7 +578,7 @@ static int fimc_src_set_transf(struct device *dev, cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR; break; default: - dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); + dev_err(ippdrv->dev, "invalid degree value %d.\n", degree); return -EINVAL; } @@ -701,7 +701,7 @@ static int fimc_src_set_addr(struct device *dev, property->prop_id, buf_id, buf_type); if (buf_id > FIMC_MAX_SRC) { - dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); + dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id); return -ENOMEM; } @@ -812,7 +812,7 @@ static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt) cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE; break; default: - dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); + dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt); return -EINVAL; } @@ -865,7 +865,7 @@ static int fimc_dst_set_fmt(struct device *dev, u32 fmt) cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420; break; default: - dev_err(ippdrv->dev, "inavlid target format 0x%x.\n", + dev_err(ippdrv->dev, "invalid target format 0x%x.\n", fmt); return -EINVAL; } @@ -929,7 +929,7 @@ static int fimc_dst_set_transf(struct device *dev, cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR; break; default: - dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); + dev_err(ippdrv->dev, "invalid degree value %d.\n", degree); return -EINVAL; } @@ -1160,7 +1160,7 @@ static int fimc_dst_set_addr(struct device *dev, property->prop_id, buf_id, buf_type); if (buf_id > FIMC_MAX_DST) { - dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); + dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id); return -ENOMEM; } @@ -1206,23 +1206,6 @@ static struct exynos_drm_ipp_ops fimc_dst_ops = { .set_addr = fimc_dst_set_addr, }; -static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable) -{ - DRM_DEBUG_KMS("enable[%d]\n", enable); - - if (enable) { - clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); - clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]); - ctx->suspended = false; - } else { - clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); - clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]); - ctx->suspended = true; - } - - return 0; -} - static irqreturn_t fimc_irq_handler(int irq, void *dev_id) { struct fimc_context *ctx = dev_id; @@ -1780,6 +1763,24 @@ static int fimc_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM +static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable) +{ + DRM_DEBUG_KMS("enable[%d]\n", enable); + + if (enable) { + clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]); + clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]); + ctx->suspended = false; + } else { + clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]); + clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]); + ctx->suspended = true; + } + + return 0; +} + #ifdef CONFIG_PM_SLEEP static int fimc_suspend(struct device *dev) { @@ -1806,7 +1807,6 @@ static int fimc_resume(struct device *dev) } #endif -#ifdef CONFIG_PM static int fimc_runtime_suspend(struct device *dev) { struct fimc_context *ctx = get_fimc_context(dev); diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 750a9e6b9e8d..bd75c1531cac 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -41,7 +41,6 @@ * CPU Interface. */ -#define FIMD_DEFAULT_FRAMERATE 60 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128 /* position control register for hardware window 0, 2 ~ 4.*/ @@ -88,6 +87,7 @@ /* FIMD has totally five hardware windows. */ #define WINDOWS_NR 5 +#define CURSOR_WIN 4 struct fimd_driver_data { unsigned int timing_base; @@ -154,7 +154,6 @@ struct fimd_context { struct clk *lcd_clk; void __iomem *regs; struct regmap *sysreg; - unsigned int default_win; unsigned long irq_flags; u32 vidcon0; u32 vidcon1; @@ -377,16 +376,6 @@ static u32 fimd_calc_clkdiv(struct fimd_context *ctx, return (clkdiv < 0x100) ? clkdiv : 0xff; } -static bool fimd_mode_fixup(struct exynos_drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - if (adjusted_mode->vrefresh == 0) - adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE; - - return true; -} - static void fimd_commit(struct exynos_drm_crtc *crtc) { struct fimd_context *ctx = crtc->ctx; @@ -882,13 +871,12 @@ static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) return; val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; - writel(DP_MIE_CLK_DP_ENABLE, ctx->regs + DP_MIE_CLKCON); + writel(val, ctx->regs + DP_MIE_CLKCON); } static const struct exynos_drm_crtc_ops fimd_crtc_ops = { .enable = fimd_enable, .disable = fimd_disable, - .mode_fixup = fimd_mode_fixup, .commit = fimd_commit, .enable_vblank = fimd_enable_vblank, .disable_vblank = fimd_disable_vblank, @@ -961,8 +949,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) ctx->pipe = priv->pipe++; for (zpos = 0; zpos < WINDOWS_NR; zpos++) { - type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : - DRM_PLANE_TYPE_OVERLAY; + type = exynos_plane_get_type(zpos, CURSOR_WIN); ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 1 << ctx->pipe, type, fimd_formats, ARRAY_SIZE(fimd_formats), zpos); @@ -970,7 +957,7 @@ static int fimd_bind(struct device *dev, struct device *master, void *data) return ret; } - exynos_plane = &ctx->planes[ctx->default_win]; + exynos_plane = &ctx->planes[DEFAULT_WIN]; ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx); diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c index 3734c34aed16..c17efdb238a6 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c +++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c @@ -1059,7 +1059,6 @@ int exynos_g2d_get_ver_ioctl(struct drm_device *drm_dev, void *data, return 0; } -EXPORT_SYMBOL_GPL(exynos_g2d_get_ver_ioctl); int exynos_g2d_set_cmdlist_ioctl(struct drm_device *drm_dev, void *data, struct drm_file *file) @@ -1230,7 +1229,6 @@ err: g2d_put_cmdlist(g2d, node); return ret; } -EXPORT_SYMBOL_GPL(exynos_g2d_set_cmdlist_ioctl); int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data, struct drm_file *file) @@ -1293,7 +1291,6 @@ int exynos_g2d_exec_ioctl(struct drm_device *drm_dev, void *data, out: return 0; } -EXPORT_SYMBOL_GPL(exynos_g2d_exec_ioctl); static int g2d_subdrv_probe(struct drm_device *drm_dev, struct device *dev) { diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c index f12fbc36b120..252eb301470c 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c @@ -20,105 +20,108 @@ #include "exynos_drm_gem.h" #include "exynos_drm_iommu.h" -static int exynos_drm_alloc_buf(struct exynos_drm_gem_obj *obj) +static int exynos_drm_alloc_buf(struct exynos_drm_gem *exynos_gem) { - struct drm_device *dev = obj->base.dev; + struct drm_device *dev = exynos_gem->base.dev; enum dma_attr attr; unsigned int nr_pages; + struct sg_table sgt; + int ret = -ENOMEM; - if (obj->dma_addr) { + if (exynos_gem->dma_addr) { DRM_DEBUG_KMS("already allocated.\n"); return 0; } - init_dma_attrs(&obj->dma_attrs); + init_dma_attrs(&exynos_gem->dma_attrs); /* * if EXYNOS_BO_CONTIG, fully physically contiguous memory * region will be allocated else physically contiguous * as possible. */ - if (!(obj->flags & EXYNOS_BO_NONCONTIG)) - dma_set_attr(DMA_ATTR_FORCE_CONTIGUOUS, &obj->dma_attrs); + if (!(exynos_gem->flags & EXYNOS_BO_NONCONTIG)) + dma_set_attr(DMA_ATTR_FORCE_CONTIGUOUS, &exynos_gem->dma_attrs); /* * if EXYNOS_BO_WC or EXYNOS_BO_NONCACHABLE, writecombine mapping * else cachable mapping. */ - if (obj->flags & EXYNOS_BO_WC || !(obj->flags & EXYNOS_BO_CACHABLE)) + if (exynos_gem->flags & EXYNOS_BO_WC || + !(exynos_gem->flags & EXYNOS_BO_CACHABLE)) attr = DMA_ATTR_WRITE_COMBINE; else attr = DMA_ATTR_NON_CONSISTENT; - dma_set_attr(attr, &obj->dma_attrs); - dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &obj->dma_attrs); - - nr_pages = obj->size >> PAGE_SHIFT; - - if (!is_drm_iommu_supported(dev)) { - dma_addr_t start_addr; - unsigned int i = 0; - - obj->pages = drm_calloc_large(nr_pages, sizeof(struct page *)); - if (!obj->pages) { - DRM_ERROR("failed to allocate pages.\n"); - return -ENOMEM; - } - - obj->cookie = dma_alloc_attrs(dev->dev, - obj->size, - &obj->dma_addr, GFP_KERNEL, - &obj->dma_attrs); - if (!obj->cookie) { - DRM_ERROR("failed to allocate buffer.\n"); - drm_free_large(obj->pages); - return -ENOMEM; - } - - start_addr = obj->dma_addr; - while (i < nr_pages) { - obj->pages[i] = phys_to_page(start_addr); - start_addr += PAGE_SIZE; - i++; - } - } else { - obj->pages = dma_alloc_attrs(dev->dev, obj->size, - &obj->dma_addr, GFP_KERNEL, - &obj->dma_attrs); - if (!obj->pages) { - DRM_ERROR("failed to allocate buffer.\n"); - return -ENOMEM; - } + dma_set_attr(attr, &exynos_gem->dma_attrs); + dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &exynos_gem->dma_attrs); + + nr_pages = exynos_gem->size >> PAGE_SHIFT; + + exynos_gem->pages = drm_calloc_large(nr_pages, sizeof(struct page *)); + if (!exynos_gem->pages) { + DRM_ERROR("failed to allocate pages.\n"); + return -ENOMEM; + } + + exynos_gem->cookie = dma_alloc_attrs(dev->dev, exynos_gem->size, + &exynos_gem->dma_addr, GFP_KERNEL, + &exynos_gem->dma_attrs); + if (!exynos_gem->cookie) { + DRM_ERROR("failed to allocate buffer.\n"); + goto err_free; + } + + ret = dma_get_sgtable_attrs(dev->dev, &sgt, exynos_gem->cookie, + exynos_gem->dma_addr, exynos_gem->size, + &exynos_gem->dma_attrs); + if (ret < 0) { + DRM_ERROR("failed to get sgtable.\n"); + goto err_dma_free; + } + + if (drm_prime_sg_to_page_addr_arrays(&sgt, exynos_gem->pages, NULL, + nr_pages)) { + DRM_ERROR("invalid sgtable.\n"); + ret = -EINVAL; + goto err_sgt_free; } + sg_free_table(&sgt); + DRM_DEBUG_KMS("dma_addr(0x%lx), size(0x%lx)\n", - (unsigned long)obj->dma_addr, - obj->size); + (unsigned long)exynos_gem->dma_addr, exynos_gem->size); return 0; + +err_sgt_free: + sg_free_table(&sgt); +err_dma_free: + dma_free_attrs(dev->dev, exynos_gem->size, exynos_gem->cookie, + exynos_gem->dma_addr, &exynos_gem->dma_attrs); +err_free: + drm_free_large(exynos_gem->pages); + + return ret; } -static void exynos_drm_free_buf(struct exynos_drm_gem_obj *obj) +static void exynos_drm_free_buf(struct exynos_drm_gem *exynos_gem) { - struct drm_device *dev = obj->base.dev; + struct drm_device *dev = exynos_gem->base.dev; - if (!obj->dma_addr) { + if (!exynos_gem->dma_addr) { DRM_DEBUG_KMS("dma_addr is invalid.\n"); return; } DRM_DEBUG_KMS("dma_addr(0x%lx), size(0x%lx)\n", - (unsigned long)obj->dma_addr, obj->size); + (unsigned long)exynos_gem->dma_addr, exynos_gem->size); - if (!is_drm_iommu_supported(dev)) { - dma_free_attrs(dev->dev, obj->size, obj->cookie, - (dma_addr_t)obj->dma_addr, &obj->dma_attrs); - drm_free_large(obj->pages); - } else - dma_free_attrs(dev->dev, obj->size, obj->pages, - (dma_addr_t)obj->dma_addr, &obj->dma_attrs); + dma_free_attrs(dev->dev, exynos_gem->size, exynos_gem->cookie, + (dma_addr_t)exynos_gem->dma_addr, + &exynos_gem->dma_attrs); - obj->dma_addr = (dma_addr_t)NULL; + drm_free_large(exynos_gem->pages); } static int exynos_drm_gem_handle_create(struct drm_gem_object *obj, @@ -143,9 +146,9 @@ static int exynos_drm_gem_handle_create(struct drm_gem_object *obj, return 0; } -void exynos_drm_gem_destroy(struct exynos_drm_gem_obj *exynos_gem_obj) +void exynos_drm_gem_destroy(struct exynos_drm_gem *exynos_gem) { - struct drm_gem_object *obj = &exynos_gem_obj->base; + struct drm_gem_object *obj = &exynos_gem->base; DRM_DEBUG_KMS("handle count = %d\n", obj->handle_count); @@ -156,25 +159,21 @@ void exynos_drm_gem_destroy(struct exynos_drm_gem_obj *exynos_gem_obj) * once dmabuf's refcount becomes 0. */ if (obj->import_attach) - goto out; - - exynos_drm_free_buf(exynos_gem_obj); - -out: - drm_gem_free_mmap_offset(obj); + drm_prime_gem_destroy(obj, exynos_gem->sgt); + else + exynos_drm_free_buf(exynos_gem); /* release file pointer to gem object. */ drm_gem_object_release(obj); - kfree(exynos_gem_obj); - exynos_gem_obj = NULL; + kfree(exynos_gem); } unsigned long exynos_drm_gem_get_size(struct drm_device *dev, unsigned int gem_handle, struct drm_file *file_priv) { - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; struct drm_gem_object *obj; obj = drm_gem_object_lookup(dev, file_priv, gem_handle); @@ -183,45 +182,51 @@ unsigned long exynos_drm_gem_get_size(struct drm_device *dev, return 0; } - exynos_gem_obj = to_exynos_gem_obj(obj); + exynos_gem = to_exynos_gem(obj); drm_gem_object_unreference_unlocked(obj); - return exynos_gem_obj->size; + return exynos_gem->size; } - -struct exynos_drm_gem_obj *exynos_drm_gem_init(struct drm_device *dev, - unsigned long size) +static struct exynos_drm_gem *exynos_drm_gem_init(struct drm_device *dev, + unsigned long size) { - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; struct drm_gem_object *obj; int ret; - exynos_gem_obj = kzalloc(sizeof(*exynos_gem_obj), GFP_KERNEL); - if (!exynos_gem_obj) + exynos_gem = kzalloc(sizeof(*exynos_gem), GFP_KERNEL); + if (!exynos_gem) return ERR_PTR(-ENOMEM); - exynos_gem_obj->size = size; - obj = &exynos_gem_obj->base; + exynos_gem->size = size; + obj = &exynos_gem->base; ret = drm_gem_object_init(dev, obj, size); if (ret < 0) { DRM_ERROR("failed to initialize gem object\n"); - kfree(exynos_gem_obj); + kfree(exynos_gem); + return ERR_PTR(ret); + } + + ret = drm_gem_create_mmap_offset(obj); + if (ret < 0) { + drm_gem_object_release(obj); + kfree(exynos_gem); return ERR_PTR(ret); } DRM_DEBUG_KMS("created file object = 0x%x\n", (unsigned int)obj->filp); - return exynos_gem_obj; + return exynos_gem; } -struct exynos_drm_gem_obj *exynos_drm_gem_create(struct drm_device *dev, - unsigned int flags, - unsigned long size) +struct exynos_drm_gem *exynos_drm_gem_create(struct drm_device *dev, + unsigned int flags, + unsigned long size) { - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; int ret; if (flags & ~(EXYNOS_BO_MASK)) { @@ -236,38 +241,38 @@ struct exynos_drm_gem_obj *exynos_drm_gem_create(struct drm_device *dev, size = roundup(size, PAGE_SIZE); - exynos_gem_obj = exynos_drm_gem_init(dev, size); - if (IS_ERR(exynos_gem_obj)) - return exynos_gem_obj; + exynos_gem = exynos_drm_gem_init(dev, size); + if (IS_ERR(exynos_gem)) + return exynos_gem; /* set memory type and cache attribute from user side. */ - exynos_gem_obj->flags = flags; + exynos_gem->flags = flags; - ret = exynos_drm_alloc_buf(exynos_gem_obj); + ret = exynos_drm_alloc_buf(exynos_gem); if (ret < 0) { - drm_gem_object_release(&exynos_gem_obj->base); - kfree(exynos_gem_obj); + drm_gem_object_release(&exynos_gem->base); + kfree(exynos_gem); return ERR_PTR(ret); } - return exynos_gem_obj; + return exynos_gem; } int exynos_drm_gem_create_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { struct drm_exynos_gem_create *args = data; - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; int ret; - exynos_gem_obj = exynos_drm_gem_create(dev, args->flags, args->size); - if (IS_ERR(exynos_gem_obj)) - return PTR_ERR(exynos_gem_obj); + exynos_gem = exynos_drm_gem_create(dev, args->flags, args->size); + if (IS_ERR(exynos_gem)) + return PTR_ERR(exynos_gem); - ret = exynos_drm_gem_handle_create(&exynos_gem_obj->base, file_priv, - &args->handle); + ret = exynos_drm_gem_handle_create(&exynos_gem->base, file_priv, + &args->handle); if (ret) { - exynos_drm_gem_destroy(exynos_gem_obj); + exynos_drm_gem_destroy(exynos_gem); return ret; } @@ -278,7 +283,7 @@ dma_addr_t *exynos_drm_gem_get_dma_addr(struct drm_device *dev, unsigned int gem_handle, struct drm_file *filp) { - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; struct drm_gem_object *obj; obj = drm_gem_object_lookup(dev, filp, gem_handle); @@ -287,9 +292,9 @@ dma_addr_t *exynos_drm_gem_get_dma_addr(struct drm_device *dev, return ERR_PTR(-EINVAL); } - exynos_gem_obj = to_exynos_gem_obj(obj); + exynos_gem = to_exynos_gem(obj); - return &exynos_gem_obj->dma_addr; + return &exynos_gem->dma_addr; } void exynos_drm_gem_put_dma_addr(struct drm_device *dev, @@ -313,10 +318,10 @@ void exynos_drm_gem_put_dma_addr(struct drm_device *dev, drm_gem_object_unreference_unlocked(obj); } -int exynos_drm_gem_mmap_buffer(struct exynos_drm_gem_obj *exynos_gem_obj, +static int exynos_drm_gem_mmap_buffer(struct exynos_drm_gem *exynos_gem, struct vm_area_struct *vma) { - struct drm_device *drm_dev = exynos_gem_obj->base.dev; + struct drm_device *drm_dev = exynos_gem->base.dev; unsigned long vm_size; int ret; @@ -326,12 +331,12 @@ int exynos_drm_gem_mmap_buffer(struct exynos_drm_gem_obj *exynos_gem_obj, vm_size = vma->vm_end - vma->vm_start; /* check if user-requested size is valid. */ - if (vm_size > exynos_gem_obj->size) + if (vm_size > exynos_gem->size) return -EINVAL; - ret = dma_mmap_attrs(drm_dev->dev, vma, exynos_gem_obj->pages, - exynos_gem_obj->dma_addr, exynos_gem_obj->size, - &exynos_gem_obj->dma_attrs); + ret = dma_mmap_attrs(drm_dev->dev, vma, exynos_gem->pages, + exynos_gem->dma_addr, exynos_gem->size, + &exynos_gem->dma_attrs); if (ret < 0) { DRM_ERROR("failed to mmap.\n"); return ret; @@ -342,7 +347,8 @@ int exynos_drm_gem_mmap_buffer(struct exynos_drm_gem_obj *exynos_gem_obj, int exynos_drm_gem_get_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) -{ struct exynos_drm_gem_obj *exynos_gem_obj; +{ + struct exynos_drm_gem *exynos_gem; struct drm_exynos_gem_info *args = data; struct drm_gem_object *obj; @@ -355,10 +361,10 @@ int exynos_drm_gem_get_ioctl(struct drm_device *dev, void *data, return -EINVAL; } - exynos_gem_obj = to_exynos_gem_obj(obj); + exynos_gem = to_exynos_gem(obj); - args->flags = exynos_gem_obj->flags; - args->size = exynos_gem_obj->size; + args->flags = exynos_gem->flags; + args->size = exynos_gem->size; drm_gem_object_unreference(obj); mutex_unlock(&dev->struct_mutex); @@ -394,14 +400,15 @@ void exynos_gem_unmap_sgt_from_dma(struct drm_device *drm_dev, void exynos_drm_gem_free_object(struct drm_gem_object *obj) { - exynos_drm_gem_destroy(to_exynos_gem_obj(obj)); + exynos_drm_gem_destroy(to_exynos_gem(obj)); } int exynos_drm_gem_dumb_create(struct drm_file *file_priv, struct drm_device *dev, struct drm_mode_create_dumb *args) { - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; + unsigned int flags; int ret; /* @@ -413,25 +420,21 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv, args->pitch = args->width * ((args->bpp + 7) / 8); args->size = args->pitch * args->height; - if (is_drm_iommu_supported(dev)) { - exynos_gem_obj = exynos_drm_gem_create(dev, - EXYNOS_BO_NONCONTIG | EXYNOS_BO_WC, - args->size); - } else { - exynos_gem_obj = exynos_drm_gem_create(dev, - EXYNOS_BO_CONTIG | EXYNOS_BO_WC, - args->size); - } + if (is_drm_iommu_supported(dev)) + flags = EXYNOS_BO_NONCONTIG | EXYNOS_BO_WC; + else + flags = EXYNOS_BO_CONTIG | EXYNOS_BO_WC; - if (IS_ERR(exynos_gem_obj)) { + exynos_gem = exynos_drm_gem_create(dev, flags, args->size); + if (IS_ERR(exynos_gem)) { dev_warn(dev->dev, "FB allocation failed.\n"); - return PTR_ERR(exynos_gem_obj); + return PTR_ERR(exynos_gem); } - ret = exynos_drm_gem_handle_create(&exynos_gem_obj->base, file_priv, - &args->handle); + ret = exynos_drm_gem_handle_create(&exynos_gem->base, file_priv, + &args->handle); if (ret) { - exynos_drm_gem_destroy(exynos_gem_obj); + exynos_drm_gem_destroy(exynos_gem); return ret; } @@ -460,14 +463,9 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv, goto unlock; } - ret = drm_gem_create_mmap_offset(obj); - if (ret) - goto out; - *offset = drm_vma_node_offset_addr(&obj->vma_node); DRM_DEBUG_KMS("offset = 0x%lx\n", (unsigned long)*offset); -out: drm_gem_object_unreference(obj); unlock: mutex_unlock(&dev->struct_mutex); @@ -477,7 +475,7 @@ unlock: int exynos_drm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) { struct drm_gem_object *obj = vma->vm_private_data; - struct exynos_drm_gem_obj *exynos_gem_obj = to_exynos_gem_obj(obj); + struct exynos_drm_gem *exynos_gem = to_exynos_gem(obj); unsigned long pfn; pgoff_t page_offset; int ret; @@ -485,13 +483,13 @@ int exynos_drm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> PAGE_SHIFT; - if (page_offset >= (exynos_gem_obj->size >> PAGE_SHIFT)) { + if (page_offset >= (exynos_gem->size >> PAGE_SHIFT)) { DRM_ERROR("invalid page offset\n"); ret = -EINVAL; goto out; } - pfn = page_to_pfn(exynos_gem_obj->pages[page_offset]); + pfn = page_to_pfn(exynos_gem->pages[page_offset]); ret = vm_insert_mixed(vma, (unsigned long)vmf->virtual_address, pfn); out: @@ -509,7 +507,7 @@ out: int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; struct drm_gem_object *obj; int ret; @@ -521,21 +519,21 @@ int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) } obj = vma->vm_private_data; - exynos_gem_obj = to_exynos_gem_obj(obj); + exynos_gem = to_exynos_gem(obj); - DRM_DEBUG_KMS("flags = 0x%x\n", exynos_gem_obj->flags); + DRM_DEBUG_KMS("flags = 0x%x\n", exynos_gem->flags); /* non-cachable as default. */ - if (exynos_gem_obj->flags & EXYNOS_BO_CACHABLE) + if (exynos_gem->flags & EXYNOS_BO_CACHABLE) vma->vm_page_prot = vm_get_page_prot(vma->vm_flags); - else if (exynos_gem_obj->flags & EXYNOS_BO_WC) + else if (exynos_gem->flags & EXYNOS_BO_WC) vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); else vma->vm_page_prot = pgprot_noncached(vm_get_page_prot(vma->vm_flags)); - ret = exynos_drm_gem_mmap_buffer(exynos_gem_obj, vma); + ret = exynos_drm_gem_mmap_buffer(exynos_gem, vma); if (ret) goto err_close_vm; @@ -543,7 +541,6 @@ int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) err_close_vm: drm_gem_vm_close(vma); - drm_gem_free_mmap_offset(obj); return ret; } @@ -551,12 +548,12 @@ err_close_vm: /* low-level interface prime helpers */ struct sg_table *exynos_drm_gem_prime_get_sg_table(struct drm_gem_object *obj) { - struct exynos_drm_gem_obj *exynos_gem_obj = to_exynos_gem_obj(obj); + struct exynos_drm_gem *exynos_gem = to_exynos_gem(obj); int npages; - npages = exynos_gem_obj->size >> PAGE_SHIFT; + npages = exynos_gem->size >> PAGE_SHIFT; - return drm_prime_pages_to_sg(exynos_gem_obj->pages, npages); + return drm_prime_pages_to_sg(exynos_gem->pages, npages); } struct drm_gem_object * @@ -564,33 +561,35 @@ exynos_drm_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf_attachment *attach, struct sg_table *sgt) { - struct exynos_drm_gem_obj *exynos_gem_obj; + struct exynos_drm_gem *exynos_gem; int npages; int ret; - exynos_gem_obj = exynos_drm_gem_init(dev, attach->dmabuf->size); - if (IS_ERR(exynos_gem_obj)) { - ret = PTR_ERR(exynos_gem_obj); + exynos_gem = exynos_drm_gem_init(dev, attach->dmabuf->size); + if (IS_ERR(exynos_gem)) { + ret = PTR_ERR(exynos_gem); return ERR_PTR(ret); } - exynos_gem_obj->dma_addr = sg_dma_address(sgt->sgl); + exynos_gem->dma_addr = sg_dma_address(sgt->sgl); - npages = exynos_gem_obj->size >> PAGE_SHIFT; - exynos_gem_obj->pages = drm_malloc_ab(npages, sizeof(struct page *)); - if (!exynos_gem_obj->pages) { + npages = exynos_gem->size >> PAGE_SHIFT; + exynos_gem->pages = drm_malloc_ab(npages, sizeof(struct page *)); + if (!exynos_gem->pages) { ret = -ENOMEM; goto err; } - ret = drm_prime_sg_to_page_addr_arrays(sgt, exynos_gem_obj->pages, NULL, - npages); + ret = drm_prime_sg_to_page_addr_arrays(sgt, exynos_gem->pages, NULL, + npages); if (ret < 0) goto err_free_large; + exynos_gem->sgt = sgt; + if (sgt->nents == 1) { /* always physically continuous memory if sgt->nents is 1. */ - exynos_gem_obj->flags |= EXYNOS_BO_CONTIG; + exynos_gem->flags |= EXYNOS_BO_CONTIG; } else { /* * this case could be CONTIG or NONCONTIG type but for now @@ -598,16 +597,16 @@ exynos_drm_gem_prime_import_sg_table(struct drm_device *dev, * TODO. we have to find a way that exporter can notify * the type of its own buffer to importer. */ - exynos_gem_obj->flags |= EXYNOS_BO_NONCONTIG; + exynos_gem->flags |= EXYNOS_BO_NONCONTIG; } - return &exynos_gem_obj->base; + return &exynos_gem->base; err_free_large: - drm_free_large(exynos_gem_obj->pages); + drm_free_large(exynos_gem->pages); err: - drm_gem_object_release(&exynos_gem_obj->base); - kfree(exynos_gem_obj); + drm_gem_object_release(&exynos_gem->base); + kfree(exynos_gem); return ERR_PTR(ret); } diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h index cd62f8410d1e..37ab8b282db6 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gem.h +++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h @@ -14,8 +14,7 @@ #include <drm/drm_gem.h> -#define to_exynos_gem_obj(x) container_of(x,\ - struct exynos_drm_gem_obj, base) +#define to_exynos_gem(x) container_of(x, struct exynos_drm_gem, base) #define IS_NONCONTIG_BUFFER(f) (f & EXYNOS_BO_NONCONTIG) @@ -39,11 +38,12 @@ * - this address could be physical address without IOMMU and * device address with IOMMU. * @pages: Array of backing pages. + * @sgt: Imported sg_table. * * P.S. this object would be transferred to user as kms_bo.handle so * user can access the buffer through kms_bo.handle. */ -struct exynos_drm_gem_obj { +struct exynos_drm_gem { struct drm_gem_object base; unsigned int flags; unsigned long size; @@ -52,21 +52,18 @@ struct exynos_drm_gem_obj { dma_addr_t dma_addr; struct dma_attrs dma_attrs; struct page **pages; + struct sg_table *sgt; }; struct page **exynos_gem_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); /* destroy a buffer with gem object */ -void exynos_drm_gem_destroy(struct exynos_drm_gem_obj *exynos_gem_obj); - -/* create a private gem object and initialize it. */ -struct exynos_drm_gem_obj *exynos_drm_gem_init(struct drm_device *dev, - unsigned long size); +void exynos_drm_gem_destroy(struct exynos_drm_gem *exynos_gem); /* create a new buffer with gem object */ -struct exynos_drm_gem_obj *exynos_drm_gem_create(struct drm_device *dev, - unsigned int flags, - unsigned long size); +struct exynos_drm_gem *exynos_drm_gem_create(struct drm_device *dev, + unsigned int flags, + unsigned long size); /* * request gem object creation and buffer allocation as the size @@ -108,7 +105,7 @@ unsigned long exynos_drm_gem_get_size(struct drm_device *dev, struct drm_file *file_priv); /* free gem object. */ -void exynos_drm_gem_free_object(struct drm_gem_object *gem_obj); +void exynos_drm_gem_free_object(struct drm_gem_object *obj); /* create memory region for drm framebuffer. */ int exynos_drm_gem_dumb_create(struct drm_file *file_priv, diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c index 808a0a013780..11b87d2a7913 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c +++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c @@ -543,7 +543,7 @@ static int gsc_src_set_fmt(struct device *dev, u32 fmt) GSC_IN_YUV420_2P); break; default: - dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); + dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt); return -EINVAL; } @@ -595,7 +595,7 @@ static int gsc_src_set_transf(struct device *dev, cfg &= ~GSC_IN_ROT_YFLIP; break; default: - dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); + dev_err(ippdrv->dev, "invalid degree value %d.\n", degree); return -EINVAL; } @@ -721,7 +721,7 @@ static int gsc_src_set_addr(struct device *dev, property->prop_id, buf_id, buf_type); if (buf_id > GSC_MAX_SRC) { - dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); + dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id); return -EINVAL; } @@ -814,7 +814,7 @@ static int gsc_dst_set_fmt(struct device *dev, u32 fmt) GSC_OUT_YUV420_2P); break; default: - dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt); + dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt); return -EINVAL; } @@ -866,7 +866,7 @@ static int gsc_dst_set_transf(struct device *dev, cfg &= ~GSC_IN_ROT_YFLIP; break; default: - dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree); + dev_err(ippdrv->dev, "invalid degree value %d.\n", degree); return -EINVAL; } @@ -1176,7 +1176,7 @@ static int gsc_dst_set_addr(struct device *dev, property->prop_id, buf_id, buf_type); if (buf_id > GSC_MAX_DST) { - dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id); + dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id); return -EINVAL; } diff --git a/drivers/gpu/drm/exynos/exynos_drm_iommu.c b/drivers/gpu/drm/exynos/exynos_drm_iommu.c index 055e8ec2ef21..d73b9ad35b7a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_iommu.c +++ b/drivers/gpu/drm/exynos/exynos_drm_iommu.c @@ -139,6 +139,5 @@ void drm_iommu_detach_device(struct drm_device *drm_dev, if (!mapping || !mapping->domain) return; - iommu_detach_device(mapping->domain, subdrv_dev); - drm_release_iommu_mapping(drm_dev); + arm_iommu_detach_device(subdrv_dev); } diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c index 714822441467..179311760bb7 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.c +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c @@ -128,15 +128,14 @@ static int exynos_plane_atomic_check(struct drm_plane *plane, nr = drm_format_num_planes(state->fb->pixel_format); for (i = 0; i < nr; i++) { - struct exynos_drm_gem_obj *obj = - exynos_drm_fb_gem_obj(state->fb, i); - - if (!obj) { + struct exynos_drm_gem *exynos_gem = + exynos_drm_fb_gem(state->fb, i); + if (!exynos_gem) { DRM_DEBUG_KMS("gem object is null\n"); return -EFAULT; } - exynos_plane->dma_addr[i] = obj->dma_addr + + exynos_plane->dma_addr[i] = exynos_gem->dma_addr + state->fb->offsets[i]; DRM_DEBUG_KMS("buffer: %d, dma_addr = 0x%lx\n", @@ -208,6 +207,17 @@ static void exynos_plane_attach_zpos_property(struct drm_plane *plane, drm_object_attach_property(&plane->base, prop, zpos); } +enum drm_plane_type exynos_plane_get_type(unsigned int zpos, + unsigned int cursor_win) +{ + if (zpos == DEFAULT_WIN) + return DRM_PLANE_TYPE_PRIMARY; + else if (zpos == cursor_win) + return DRM_PLANE_TYPE_CURSOR; + else + return DRM_PLANE_TYPE_OVERLAY; +} + int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *exynos_plane, unsigned long possible_crtcs, enum drm_plane_type type, diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h b/drivers/gpu/drm/exynos/exynos_drm_plane.h index 476c9340b591..abb641e64c23 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_plane.h +++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h @@ -9,6 +9,8 @@ * */ +enum drm_plane_type exynos_plane_get_type(unsigned int zpos, + unsigned int cursor_win); int exynos_plane_init(struct drm_device *dev, struct exynos_drm_plane *exynos_plane, unsigned long possible_crtcs, enum drm_plane_type type, diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c index 425e70625388..2f5c118f4c8e 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c +++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c @@ -786,6 +786,7 @@ static int rotator_remove(struct platform_device *pdev) return 0; } +#ifdef CONFIG_PM static int rotator_clk_crtl(struct rot_context *rot, bool enable) { if (enable) { @@ -822,7 +823,6 @@ static int rotator_resume(struct device *dev) } #endif -#ifdef CONFIG_PM static int rotator_runtime_suspend(struct device *dev) { struct rot_context *rot = dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c index 75718e1bc3dd..669362c53f49 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c @@ -29,6 +29,7 @@ /* vidi has totally three virtual windows. */ #define WINDOWS_NR 3 +#define CURSOR_WIN 2 #define ctx_from_connector(c) container_of(c, struct vidi_context, \ connector) @@ -42,7 +43,6 @@ struct vidi_context { struct exynos_drm_plane planes[WINDOWS_NR]; struct edid *raw_edid; unsigned int clkdiv; - unsigned int default_win; unsigned long irq_flags; unsigned int connected; bool vblank_on; @@ -446,8 +446,7 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) vidi_ctx_initialize(ctx, drm_dev); for (zpos = 0; zpos < WINDOWS_NR; zpos++) { - type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY : - DRM_PLANE_TYPE_OVERLAY; + type = exynos_plane_get_type(zpos, CURSOR_WIN); ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 1 << ctx->pipe, type, formats, ARRAY_SIZE(formats), zpos); @@ -455,7 +454,7 @@ static int vidi_bind(struct device *dev, struct device *master, void *data) return ret; } - exynos_plane = &ctx->planes[ctx->default_win]; + exynos_plane = &ctx->planes[DEFAULT_WIN]; ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, ctx->pipe, EXYNOS_DISPLAY_TYPE_VIDI, &vidi_crtc_ops, ctx); @@ -507,7 +506,6 @@ static int vidi_probe(struct platform_device *pdev) if (!ctx) return -ENOMEM; - ctx->default_win = 0; ctx->pdev = pdev; INIT_WORK(&ctx->work, vidi_fake_vblank_handler); diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 932f7fa240f8..57b675563e94 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c @@ -30,11 +30,11 @@ #include <linux/delay.h> #include <linux/pm_runtime.h> #include <linux/clk.h> +#include <linux/gpio/consumer.h> #include <linux/regulator/consumer.h> #include <linux/io.h> #include <linux/of_address.h> #include <linux/of_device.h> -#include <linux/of_gpio.h> #include <linux/hdmi.h> #include <linux/component.h> #include <linux/mfd/syscon.h> @@ -44,11 +44,6 @@ #include "exynos_drm_drv.h" #include "exynos_drm_crtc.h" -#include "exynos_mixer.h" - -#include <linux/gpio.h> - -#define ctx_from_connector(c) container_of(c, struct hdmi_context, connector) #define HOTPLUG_DEBOUNCE_MS 1100 @@ -66,6 +61,33 @@ enum hdmi_type { HDMI_TYPE13, HDMI_TYPE14, + HDMI_TYPE_COUNT +}; + +#define HDMI_MAPPED_BASE 0xffff0000 + +enum hdmi_mapped_regs { + HDMI_PHY_STATUS = HDMI_MAPPED_BASE, + HDMI_PHY_RSTOUT, + HDMI_ACR_CON, + HDMI_ACR_MCTS0, + HDMI_ACR_CTS0, + HDMI_ACR_N0 +}; + +static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = { + { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 }, + { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT }, + { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON }, + { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 }, + { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 }, + { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 }, +}; + +static const char * const supply[] = { + "vdd", + "vdd_osc", + "vdd_pll", }; struct hdmi_driver_data { @@ -75,44 +97,32 @@ struct hdmi_driver_data { unsigned int is_apb_phy:1; }; -struct hdmi_resources { - struct clk *hdmi; - struct clk *sclk_hdmi; - struct clk *sclk_pixel; - struct clk *sclk_hdmiphy; - struct clk *mout_hdmi; - struct regulator_bulk_data *regul_bulk; - struct regulator *reg_hdmi_en; - int regul_count; -}; - struct hdmi_context { struct drm_encoder encoder; struct device *dev; struct drm_device *drm_dev; struct drm_connector connector; - bool hpd; bool powered; bool dvi_mode; - - void __iomem *regs; - int irq; struct delayed_work hotplug_work; - - struct i2c_adapter *ddc_adpt; - struct i2c_client *hdmiphy_port; - - /* current hdmiphy conf regs */ struct drm_display_mode current_mode; u8 cea_video_id; - - struct hdmi_resources res; const struct hdmi_driver_data *drv_data; - int hpd_gpio; + void __iomem *regs; void __iomem *regs_hdmiphy; - + struct i2c_client *hdmiphy_port; + struct i2c_adapter *ddc_adpt; + struct gpio_desc *hpd_gpio; + int irq; struct regmap *pmureg; + struct clk *hdmi; + struct clk *sclk_hdmi; + struct clk *sclk_pixel; + struct clk *sclk_hdmiphy; + struct clk *mout_hdmi; + struct regulator_bulk_data regul_bulk[ARRAY_SIZE(supply)]; + struct regulator *reg_hdmi_en; }; static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) @@ -120,6 +130,11 @@ static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e) return container_of(e, struct hdmi_context, encoder); } +static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c) +{ + return container_of(c, struct hdmi_context, connector); +} + struct hdmiphy_config { int pixel_clock; u8 conf[32]; @@ -133,7 +148,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40, 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, }, }, { @@ -142,7 +157,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64, 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87, 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00, + 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80, }, }, { @@ -151,7 +166,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B, 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9, 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00, + 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80, }, }, { @@ -160,7 +175,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40, 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba, 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0, - 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00, + 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80, }, }, { @@ -169,7 +184,7 @@ static const struct hdmiphy_config hdmiphy_v13_configs[] = { 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40, 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba, 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0, - 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00, + 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80, }, }, }; @@ -199,7 +214,7 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = { 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08, 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80, 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00, + 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80, }, }, { @@ -262,7 +277,7 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = { 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08, 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00, + 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80, }, }, { @@ -325,7 +340,7 @@ static const struct hdmiphy_config hdmiphy_v14_configs[] = { 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08, 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80, 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86, - 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00, + 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80, }, }, }; @@ -507,29 +522,31 @@ static struct hdmi_driver_data exynos4210_hdmi_driver_data = { .is_apb_phy = 0, }; -static struct hdmi_driver_data exynos5_hdmi_driver_data = { - .type = HDMI_TYPE14, - .phy_confs = hdmiphy_v13_configs, - .phy_conf_count = ARRAY_SIZE(hdmiphy_v13_configs), - .is_apb_phy = 0, -}; +static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id) +{ + if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE) + return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type]; + return reg_id; +} static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id) { - return readl(hdata->regs + reg_id); + return readl(hdata->regs + hdmi_map_reg(hdata, reg_id)); } static inline void hdmi_reg_writeb(struct hdmi_context *hdata, u32 reg_id, u8 value) { - writeb(value, hdata->regs + reg_id); + writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id)); } static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id, int bytes, u32 val) { + reg_id = hdmi_map_reg(hdata, reg_id); + while (--bytes >= 0) { - writeb(val & 0xff, hdata->regs + reg_id); + writel(val & 0xff, hdata->regs + reg_id); val >>= 8; reg_id += 4; } @@ -538,31 +555,14 @@ static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id, static inline void hdmi_reg_writemask(struct hdmi_context *hdata, u32 reg_id, u32 value, u32 mask) { - u32 old = readl(hdata->regs + reg_id); + u32 old; + + reg_id = hdmi_map_reg(hdata, reg_id); + old = readl(hdata->regs + reg_id); value = (value & mask) | (old & ~mask); writel(value, hdata->regs + reg_id); } -static int hdmiphy_reg_writeb(struct hdmi_context *hdata, - u32 reg_offset, u8 value) -{ - if (hdata->hdmiphy_port) { - u8 buffer[2]; - int ret; - - buffer[0] = reg_offset; - buffer[1] = value; - - ret = i2c_master_send(hdata->hdmiphy_port, buffer, 2); - if (ret == 2) - return 0; - return ret; - } else { - writeb(value, hdata->regs_hdmiphy + (reg_offset<<2)); - return 0; - } -} - static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, u32 reg_offset, const u8 *buf, u32 len) { @@ -579,7 +579,7 @@ static int hdmiphy_reg_write_buf(struct hdmi_context *hdata, } else { int i; for (i = 0; i < len; i++) - writeb(buf[i], hdata->regs_hdmiphy + + writel(buf[i], hdata->regs_hdmiphy + ((reg_offset + i)<<2)); return 0; } @@ -689,7 +689,7 @@ static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix) DUMPREG(HDMI_PHY_STATUS_0); DUMPREG(HDMI_PHY_STATUS_PLL); DUMPREG(HDMI_PHY_CON_0); - DUMPREG(HDMI_PHY_RSTOUT); + DUMPREG(HDMI_V14_PHY_RSTOUT); DUMPREG(HDMI_PHY_VPLL); DUMPREG(HDMI_PHY_CMU); DUMPREG(HDMI_CORE_RSTOUT); @@ -942,9 +942,9 @@ static void hdmi_reg_infoframe(struct hdmi_context *hdata, static enum drm_connector_status hdmi_detect(struct drm_connector *connector, bool force) { - struct hdmi_context *hdata = ctx_from_connector(connector); + struct hdmi_context *hdata = connector_to_hdmi(connector); - if (gpio_get_value(hdata->hpd_gpio)) + if (gpiod_get_value(hdata->hpd_gpio)) return connector_status_connected; return connector_status_disconnected; @@ -968,7 +968,7 @@ static struct drm_connector_funcs hdmi_connector_funcs = { static int hdmi_get_modes(struct drm_connector *connector) { - struct hdmi_context *hdata = ctx_from_connector(connector); + struct hdmi_context *hdata = connector_to_hdmi(connector); struct edid *edid; int ret; @@ -1008,7 +1008,7 @@ static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock) static int hdmi_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { - struct hdmi_context *hdata = ctx_from_connector(connector); + struct hdmi_context *hdata = connector_to_hdmi(connector); int ret; DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n", @@ -1016,10 +1016,6 @@ static int hdmi_mode_valid(struct drm_connector *connector, (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true : false, mode->clock * 1000); - ret = mixer_check_mode(mode); - if (ret) - return MODE_BAD; - ret = hdmi_find_phy_conf(hdata, mode->clock * 1000); if (ret < 0) return MODE_BAD; @@ -1029,7 +1025,7 @@ static int hdmi_mode_valid(struct drm_connector *connector, static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector) { - struct hdmi_context *hdata = ctx_from_connector(connector); + struct hdmi_context *hdata = connector_to_hdmi(connector); return &hdata->encoder; } @@ -1110,70 +1106,17 @@ static bool hdmi_mode_fixup(struct drm_encoder *encoder, return true; } -static void hdmi_set_acr(u32 freq, u8 *acr) +static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq) { u32 n, cts; - switch (freq) { - case 32000: - n = 4096; - cts = 27000; - break; - case 44100: - n = 6272; - cts = 30000; - break; - case 88200: - n = 12544; - cts = 30000; - break; - case 176400: - n = 25088; - cts = 30000; - break; - case 48000: - n = 6144; - cts = 27000; - break; - case 96000: - n = 12288; - cts = 27000; - break; - case 192000: - n = 24576; - cts = 27000; - break; - default: - n = 0; - cts = 0; - break; - } - - acr[1] = cts >> 16; - acr[2] = cts >> 8 & 0xff; - acr[3] = cts & 0xff; + cts = (freq % 9) ? 27000 : 30000; + n = 128 * freq / (27000000 / cts); - acr[4] = n >> 16; - acr[5] = n >> 8 & 0xff; - acr[6] = n & 0xff; -} - -static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr) -{ - hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]); - hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]); - hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]); - hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]); - hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]); - hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]); - hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]); - hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]); - hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]); - - if (hdata->drv_data->type == HDMI_TYPE13) - hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4); - else - hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); + hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n); + hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts); + hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts); + hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4); } static void hdmi_audio_init(struct hdmi_context *hdata) @@ -1181,7 +1124,6 @@ static void hdmi_audio_init(struct hdmi_context *hdata) u32 sample_rate, bits_per_sample; u32 data_num, bit_ch, sample_frq; u32 val; - u8 acr[7]; sample_rate = 44100; bits_per_sample = 16; @@ -1201,8 +1143,7 @@ static void hdmi_audio_init(struct hdmi_context *hdata) break; } - hdmi_set_acr(sample_rate, acr); - hdmi_reg_acr(hdata, acr); + hdmi_reg_acr(hdata, sample_rate); hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE @@ -1335,11 +1276,27 @@ static void hdmi_conf_init(struct hdmi_context *hdata) } } +static void hdmiphy_wait_for_pll(struct hdmi_context *hdata) +{ + int tries; + + for (tries = 0; tries < 10; ++tries) { + u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS); + + if (val & HDMI_PHY_STATUS_READY) { + DRM_DEBUG_KMS("PLL stabilized after %d tries\n", tries); + return; + } + usleep_range(10, 20); + } + + DRM_ERROR("PLL could not reach steady state\n"); +} + static void hdmi_v13_mode_apply(struct hdmi_context *hdata) { struct drm_display_mode *m = &hdata->current_mode; unsigned int val; - int tries; hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3, @@ -1425,32 +1382,11 @@ static void hdmi_v13_mode_apply(struct hdmi_context *hdata) hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2, 0x233); hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1); hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2, 0x233); - - /* waiting for HDMIPHY's PLL to get to steady state */ - for (tries = 100; tries; --tries) { - u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); - if (val & HDMI_PHY_STATUS_READY) - break; - usleep_range(1000, 2000); - } - /* steady state not achieved */ - if (tries == 0) { - DRM_ERROR("hdmiphy's pll could not reach steady state.\n"); - hdmi_regs_dump(hdata, "timing apply"); - } - - clk_disable_unprepare(hdata->res.sclk_hdmi); - clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy); - clk_prepare_enable(hdata->res.sclk_hdmi); - - /* enable HDMI and timing generator */ - hdmi_start(hdata, true); } static void hdmi_v14_mode_apply(struct hdmi_context *hdata) { struct drm_display_mode *m = &hdata->current_mode; - int tries; hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay); hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal); @@ -1562,26 +1498,6 @@ static void hdmi_v14_mode_apply(struct hdmi_context *hdata) hdmi_reg_writev(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, 2, 0x1); hdmi_reg_writev(hdata, HDMI_TG_FIELD_TOP_HDMI_L, 2, 0x1); hdmi_reg_writev(hdata, HDMI_TG_3D, 1, 0x0); - - /* waiting for HDMIPHY's PLL to get to steady state */ - for (tries = 100; tries; --tries) { - u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0); - if (val & HDMI_PHY_STATUS_READY) - break; - usleep_range(1000, 2000); - } - /* steady state not achieved */ - if (tries == 0) { - DRM_ERROR("hdmiphy's pll could not reach steady state.\n"); - hdmi_regs_dump(hdata, "timing apply"); - } - - clk_disable_unprepare(hdata->res.sclk_hdmi); - clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy); - clk_prepare_enable(hdata->res.sclk_hdmi); - - /* enable HDMI and timing generator */ - hdmi_start(hdata, true); } static void hdmi_mode_apply(struct hdmi_context *hdata) @@ -1590,74 +1506,26 @@ static void hdmi_mode_apply(struct hdmi_context *hdata) hdmi_v13_mode_apply(hdata); else hdmi_v14_mode_apply(hdata); -} -static void hdmiphy_conf_reset(struct hdmi_context *hdata) -{ - u32 reg; + hdmiphy_wait_for_pll(hdata); - clk_disable_unprepare(hdata->res.sclk_hdmi); - clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel); - clk_prepare_enable(hdata->res.sclk_hdmi); + clk_set_parent(hdata->mout_hdmi, hdata->sclk_hdmiphy); - /* operation mode */ - hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, - HDMI_PHY_ENABLE_MODE_SET); + /* enable HDMI and timing generator */ + hdmi_start(hdata, true); +} - if (hdata->drv_data->type == HDMI_TYPE13) - reg = HDMI_V13_PHY_RSTOUT; - else - reg = HDMI_PHY_RSTOUT; +static void hdmiphy_conf_reset(struct hdmi_context *hdata) +{ + clk_set_parent(hdata->mout_hdmi, hdata->sclk_pixel); /* reset hdmiphy */ - hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT); + hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT); usleep_range(10000, 12000); - hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT); + hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT); usleep_range(10000, 12000); } -static void hdmiphy_poweron(struct hdmi_context *hdata) -{ - if (hdata->drv_data->type != HDMI_TYPE14) - return; - - DRM_DEBUG_KMS("\n"); - - /* For PHY Mode Setting */ - hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, - HDMI_PHY_ENABLE_MODE_SET); - /* Phy Power On */ - hdmiphy_reg_writeb(hdata, HDMIPHY_POWER, - HDMI_PHY_POWER_ON); - /* For PHY Mode Setting */ - hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, - HDMI_PHY_DISABLE_MODE_SET); - /* PHY SW Reset */ - hdmiphy_conf_reset(hdata); -} - -static void hdmiphy_poweroff(struct hdmi_context *hdata) -{ - if (hdata->drv_data->type != HDMI_TYPE14) - return; - - DRM_DEBUG_KMS("\n"); - - /* PHY SW Reset */ - hdmiphy_conf_reset(hdata); - /* For PHY Mode Setting */ - hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, - HDMI_PHY_ENABLE_MODE_SET); - - /* PHY Power Off */ - hdmiphy_reg_writeb(hdata, HDMIPHY_POWER, - HDMI_PHY_POWER_OFF); - - /* For PHY Mode Setting */ - hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, - HDMI_PHY_DISABLE_MODE_SET); -} - static void hdmiphy_conf_apply(struct hdmi_context *hdata) { int ret; @@ -1678,14 +1546,6 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) } usleep_range(10000, 12000); - - ret = hdmiphy_reg_writeb(hdata, HDMIPHY_MODE_SET_DONE, - HDMI_PHY_DISABLE_MODE_SET); - if (ret) { - DRM_ERROR("failed to enable hdmiphy\n"); - return; - } - } static void hdmi_conf_apply(struct hdmi_context *hdata) @@ -1724,7 +1584,6 @@ static void hdmi_mode_set(struct drm_encoder *encoder, static void hdmi_enable(struct drm_encoder *encoder) { struct hdmi_context *hdata = encoder_to_hdmi(encoder); - struct hdmi_resources *res = &hdata->res; if (hdata->powered) return; @@ -1733,24 +1592,22 @@ static void hdmi_enable(struct drm_encoder *encoder) pm_runtime_get_sync(hdata->dev); - if (regulator_bulk_enable(res->regul_count, res->regul_bulk)) + if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk)) DRM_DEBUG_KMS("failed to enable regulator bulk\n"); /* set pmu hdmiphy control bit to enable hdmiphy */ regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, PMU_HDMI_PHY_ENABLE_BIT, 1); - clk_prepare_enable(res->hdmi); - clk_prepare_enable(res->sclk_hdmi); + clk_prepare_enable(hdata->hdmi); + clk_prepare_enable(hdata->sclk_hdmi); - hdmiphy_poweron(hdata); hdmi_conf_apply(hdata); } static void hdmi_disable(struct drm_encoder *encoder) { struct hdmi_context *hdata = encoder_to_hdmi(encoder); - struct hdmi_resources *res = &hdata->res; struct drm_crtc *crtc = encoder->crtc; const struct drm_crtc_helper_funcs *funcs = NULL; @@ -1774,18 +1631,16 @@ static void hdmi_disable(struct drm_encoder *encoder) /* HDMI System Disable */ hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN); - hdmiphy_poweroff(hdata); - cancel_delayed_work(&hdata->hotplug_work); - clk_disable_unprepare(res->sclk_hdmi); - clk_disable_unprepare(res->hdmi); + clk_disable_unprepare(hdata->sclk_hdmi); + clk_disable_unprepare(hdata->hdmi); /* reset pmu hdmiphy control bit to disable hdmiphy */ regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL, PMU_HDMI_PHY_ENABLE_BIT, 0); - regulator_bulk_disable(res->regul_count, res->regul_bulk); + regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk); pm_runtime_put_sync(hdata->dev); @@ -1826,80 +1681,76 @@ static irqreturn_t hdmi_irq_thread(int irq, void *arg) static int hdmi_resources_init(struct hdmi_context *hdata) { struct device *dev = hdata->dev; - struct hdmi_resources *res = &hdata->res; - static char *supply[] = { - "vdd", - "vdd_osc", - "vdd_pll", - }; int i, ret; DRM_DEBUG_KMS("HDMI resource init\n"); + hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN); + if (IS_ERR(hdata->hpd_gpio)) { + DRM_ERROR("cannot get hpd gpio property\n"); + return PTR_ERR(hdata->hpd_gpio); + } + + hdata->irq = gpiod_to_irq(hdata->hpd_gpio); + if (hdata->irq < 0) { + DRM_ERROR("failed to get GPIO irq\n"); + return hdata->irq; + } /* get clocks, power */ - res->hdmi = devm_clk_get(dev, "hdmi"); - if (IS_ERR(res->hdmi)) { + hdata->hdmi = devm_clk_get(dev, "hdmi"); + if (IS_ERR(hdata->hdmi)) { DRM_ERROR("failed to get clock 'hdmi'\n"); - ret = PTR_ERR(res->hdmi); + ret = PTR_ERR(hdata->hdmi); goto fail; } - res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); - if (IS_ERR(res->sclk_hdmi)) { + hdata->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi"); + if (IS_ERR(hdata->sclk_hdmi)) { DRM_ERROR("failed to get clock 'sclk_hdmi'\n"); - ret = PTR_ERR(res->sclk_hdmi); + ret = PTR_ERR(hdata->sclk_hdmi); goto fail; } - res->sclk_pixel = devm_clk_get(dev, "sclk_pixel"); - if (IS_ERR(res->sclk_pixel)) { + hdata->sclk_pixel = devm_clk_get(dev, "sclk_pixel"); + if (IS_ERR(hdata->sclk_pixel)) { DRM_ERROR("failed to get clock 'sclk_pixel'\n"); - ret = PTR_ERR(res->sclk_pixel); + ret = PTR_ERR(hdata->sclk_pixel); goto fail; } - res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy"); - if (IS_ERR(res->sclk_hdmiphy)) { + hdata->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy"); + if (IS_ERR(hdata->sclk_hdmiphy)) { DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n"); - ret = PTR_ERR(res->sclk_hdmiphy); + ret = PTR_ERR(hdata->sclk_hdmiphy); goto fail; } - res->mout_hdmi = devm_clk_get(dev, "mout_hdmi"); - if (IS_ERR(res->mout_hdmi)) { + hdata->mout_hdmi = devm_clk_get(dev, "mout_hdmi"); + if (IS_ERR(hdata->mout_hdmi)) { DRM_ERROR("failed to get clock 'mout_hdmi'\n"); - ret = PTR_ERR(res->mout_hdmi); + ret = PTR_ERR(hdata->mout_hdmi); goto fail; } - clk_set_parent(res->mout_hdmi, res->sclk_pixel); + clk_set_parent(hdata->mout_hdmi, hdata->sclk_pixel); - res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) * - sizeof(res->regul_bulk[0]), GFP_KERNEL); - if (!res->regul_bulk) { - ret = -ENOMEM; - goto fail; - } for (i = 0; i < ARRAY_SIZE(supply); ++i) { - res->regul_bulk[i].supply = supply[i]; - res->regul_bulk[i].consumer = NULL; + hdata->regul_bulk[i].supply = supply[i]; + hdata->regul_bulk[i].consumer = NULL; } - ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk); + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk); if (ret) { DRM_ERROR("failed to get regulators\n"); return ret; } - res->regul_count = ARRAY_SIZE(supply); - res->reg_hdmi_en = devm_regulator_get(dev, "hdmi-en"); - if (IS_ERR(res->reg_hdmi_en) && PTR_ERR(res->reg_hdmi_en) != -ENOENT) { - DRM_ERROR("failed to get hdmi-en regulator\n"); - return PTR_ERR(res->reg_hdmi_en); - } - if (!IS_ERR(res->reg_hdmi_en)) { - ret = regulator_enable(res->reg_hdmi_en); - if (ret) { - DRM_ERROR("failed to enable hdmi-en regulator\n"); - return ret; - } - } else - res->reg_hdmi_en = NULL; + hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en"); + + if (PTR_ERR(hdata->reg_hdmi_en) == -ENODEV) + return 0; + + if (IS_ERR(hdata->reg_hdmi_en)) + return PTR_ERR(hdata->reg_hdmi_en); + + ret = regulator_enable(hdata->reg_hdmi_en); + if (ret) + DRM_ERROR("failed to enable hdmi-en regulator\n"); return ret; fail: @@ -1909,9 +1760,6 @@ fail: static struct of_device_id hdmi_match_types[] = { { - .compatible = "samsung,exynos5-hdmi", - .data = &exynos5_hdmi_driver_data, - }, { .compatible = "samsung,exynos4210-hdmi", .data = &exynos4210_hdmi_driver_data, }, { @@ -2009,11 +1857,6 @@ static int hdmi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, hdata); hdata->dev = dev; - hdata->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpio", 0); - if (hdata->hpd_gpio < 0) { - DRM_ERROR("cannot get hpd gpio property\n"); - return hdata->hpd_gpio; - } ret = hdmi_resources_init(hdata); if (ret) { @@ -2028,12 +1871,6 @@ static int hdmi_probe(struct platform_device *pdev) return ret; } - ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD"); - if (ret) { - DRM_ERROR("failed to request HPD gpio\n"); - return ret; - } - ddc_node = hdmi_legacy_ddc_dt_binding(dev); if (ddc_node) goto out_get_ddc_adpt; @@ -2081,13 +1918,6 @@ out_get_phy_port: } } - hdata->irq = gpio_to_irq(hdata->hpd_gpio); - if (hdata->irq < 0) { - DRM_ERROR("failed to get GPIO irq\n"); - ret = hdata->irq; - goto err_hdmiphy; - } - INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func); ret = devm_request_threaded_irq(dev, hdata->irq, NULL, @@ -2133,15 +1963,17 @@ static int hdmi_remove(struct platform_device *pdev) cancel_delayed_work_sync(&hdata->hotplug_work); - if (hdata->res.reg_hdmi_en) - regulator_disable(hdata->res.reg_hdmi_en); + component_del(&pdev->dev, &hdmi_component_ops); + + pm_runtime_disable(&pdev->dev); + + if (!IS_ERR(hdata->reg_hdmi_en)) + regulator_disable(hdata->reg_hdmi_en); if (hdata->hdmiphy_port) put_device(&hdata->hdmiphy_port->dev); - put_device(&hdata->ddc_adpt->dev); - pm_runtime_disable(&pdev->dev); - component_del(&pdev->dev, &hdmi_component_ops); + put_device(&hdata->ddc_adpt->dev); return 0; } diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index 7f81cce966d4..d09f8f9a8939 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c @@ -39,11 +39,10 @@ #include "exynos_drm_crtc.h" #include "exynos_drm_plane.h" #include "exynos_drm_iommu.h" -#include "exynos_mixer.h" #define MIXER_WIN_NR 3 -#define MIXER_DEFAULT_WIN 0 #define VP_DEFAULT_WIN 2 +#define CURSOR_WIN 1 /* The pixelformats that are natively supported by the mixer. */ #define MXR_FORMAT_RGB565 4 @@ -600,7 +599,7 @@ static void mixer_graph_buffer(struct mixer_context *ctx, /* setup display size */ if (ctx->mxr_ver == MXR_VER_128_0_0_184 && - win == MIXER_DEFAULT_WIN) { + win == DEFAULT_WIN) { val = MXR_MXR_RES_HEIGHT(mode->vdisplay); val |= MXR_MXR_RES_WIDTH(mode->hdisplay); mixer_reg_write(res, MXR_RESOLUTION, val); @@ -652,7 +651,7 @@ static void vp_win_reset(struct mixer_context *ctx) /* waiting until VP_SRESET_PROCESSING is 0 */ if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING) break; - usleep_range(10000, 12000); + mdelay(10); } WARN(tries == 0, "failed to reset Video Processor\n"); } @@ -1096,8 +1095,10 @@ static void mixer_disable(struct exynos_drm_crtc *crtc) } /* Only valid for Mixer version 16.0.33.0 */ -int mixer_check_mode(struct drm_display_mode *mode) +static int mixer_atomic_check(struct exynos_drm_crtc *crtc, + struct drm_crtc_state *state) { + struct drm_display_mode *mode = &state->adjusted_mode; u32 w, h; w = mode->hdisplay; @@ -1123,6 +1124,7 @@ static const struct exynos_drm_crtc_ops mixer_crtc_ops = { .wait_for_vblank = mixer_wait_for_vblank, .update_plane = mixer_update_plane, .disable_plane = mixer_disable_plane, + .atomic_check = mixer_atomic_check, }; static struct mixer_drv_data exynos5420_mxr_drv_data = { @@ -1197,8 +1199,6 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) const uint32_t *formats; unsigned int fcount; - type = (zpos == MIXER_DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY : - DRM_PLANE_TYPE_OVERLAY; if (zpos < VP_DEFAULT_WIN) { formats = mixer_formats; fcount = ARRAY_SIZE(mixer_formats); @@ -1207,6 +1207,7 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) fcount = ARRAY_SIZE(vp_formats); } + type = exynos_plane_get_type(zpos, CURSOR_WIN); ret = exynos_plane_init(drm_dev, &ctx->planes[zpos], 1 << ctx->pipe, type, formats, fcount, zpos); @@ -1214,7 +1215,7 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data) return ret; } - exynos_plane = &ctx->planes[MIXER_DEFAULT_WIN]; + exynos_plane = &ctx->planes[DEFAULT_WIN]; ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base, ctx->pipe, EXYNOS_DISPLAY_TYPE_HDMI, &mixer_crtc_ops, ctx); diff --git a/drivers/gpu/drm/exynos/exynos_mixer.h b/drivers/gpu/drm/exynos/exynos_mixer.h deleted file mode 100644 index 3811e417f0e9..000000000000 --- a/drivers/gpu/drm/exynos/exynos_mixer.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _EXYNOS_MIXER_H_ -#define _EXYNOS_MIXER_H_ - -/* This function returns 0 if the given timing is valid for the mixer */ -int mixer_check_mode(struct drm_display_mode *mode); - -#endif diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h index 3f35ac6d8a47..8c891e59be21 100644 --- a/drivers/gpu/drm/exynos/regs-hdmi.h +++ b/drivers/gpu/drm/exynos/regs-hdmi.h @@ -72,7 +72,6 @@ #define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) #define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) #define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) -#define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180) #define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300) #define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) #define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0) @@ -171,7 +170,7 @@ #define HDMI_HPD_ST HDMI_CTRL_BASE(0x0044) #define HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050) #define HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070) -#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0074) +#define HDMI_V14_PHY_RSTOUT HDMI_CTRL_BASE(0x0074) #define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078) #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C) #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080) @@ -277,16 +276,26 @@ #define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318) #define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C) -#define HDMI_ACR_CON HDMI_CORE_BASE(0x0400) -#define HDMI_ACR_MCTS0 HDMI_CORE_BASE(0x0410) -#define HDMI_ACR_MCTS1 HDMI_CORE_BASE(0x0414) -#define HDMI_ACR_MCTS2 HDMI_CORE_BASE(0x0418) -#define HDMI_ACR_CTS0 HDMI_CORE_BASE(0x0420) -#define HDMI_ACR_CTS1 HDMI_CORE_BASE(0x0424) -#define HDMI_ACR_CTS2 HDMI_CORE_BASE(0x0428) -#define HDMI_ACR_N0 HDMI_CORE_BASE(0x0430) -#define HDMI_ACR_N1 HDMI_CORE_BASE(0x0434) -#define HDMI_ACR_N2 HDMI_CORE_BASE(0x0438) +#define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180) +#define HDMI_V13_ACR_MCTS0 HDMI_CORE_BASE(0x0184) +#define HDMI_V13_ACR_MCTS1 HDMI_CORE_BASE(0x0188) +#define HDMI_V13_ACR_MCTS2 HDMI_CORE_BASE(0x018C) +#define HDMI_V13_ACR_CTS0 HDMI_CORE_BASE(0x0190) +#define HDMI_V13_ACR_CTS1 HDMI_CORE_BASE(0x0194) +#define HDMI_V13_ACR_CTS2 HDMI_CORE_BASE(0x0198) +#define HDMI_V13_ACR_N0 HDMI_CORE_BASE(0x01A0) +#define HDMI_V13_ACR_N1 HDMI_CORE_BASE(0x01A4) +#define HDMI_V13_ACR_N2 HDMI_CORE_BASE(0x01A8) +#define HDMI_V14_ACR_CON HDMI_CORE_BASE(0x0400) +#define HDMI_V14_ACR_MCTS0 HDMI_CORE_BASE(0x0410) +#define HDMI_V14_ACR_MCTS1 HDMI_CORE_BASE(0x0414) +#define HDMI_V14_ACR_MCTS2 HDMI_CORE_BASE(0x0418) +#define HDMI_V14_ACR_CTS0 HDMI_CORE_BASE(0x0420) +#define HDMI_V14_ACR_CTS1 HDMI_CORE_BASE(0x0424) +#define HDMI_V14_ACR_CTS2 HDMI_CORE_BASE(0x0428) +#define HDMI_V14_ACR_N0 HDMI_CORE_BASE(0x0430) +#define HDMI_V14_ACR_N1 HDMI_CORE_BASE(0x0434) +#define HDMI_V14_ACR_N2 HDMI_CORE_BASE(0x0438) /* Packet related registers */ #define HDMI_ACP_CON HDMI_CORE_BASE(0x0500) diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c index 9a8e2da47158..1930234ba5f1 100644 --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c @@ -140,7 +140,7 @@ static irqreturn_t fsl_dcu_drm_irq(int irq, void *arg) return IRQ_HANDLED; } -static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, int crtc) +static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; unsigned int value; @@ -156,7 +156,8 @@ static int fsl_dcu_drm_enable_vblank(struct drm_device *dev, int crtc) return 0; } -static void fsl_dcu_drm_disable_vblank(struct drm_device *dev, int crtc) +static void fsl_dcu_drm_disable_vblank(struct drm_device *dev, + unsigned int pipe) { struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; unsigned int value; @@ -192,7 +193,7 @@ static struct drm_driver fsl_dcu_drm_driver = { .unload = fsl_dcu_unload, .preclose = fsl_dcu_drm_preclose, .irq_handler = fsl_dcu_drm_irq, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = fsl_dcu_drm_enable_vblank, .disable_vblank = fsl_dcu_drm_disable_vblank, .gem_free_object = drm_gem_cma_free_object, diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h index e38057b91865..e21726ecac32 100644 --- a/drivers/gpu/drm/gma500/psb_drv.h +++ b/drivers/gpu/drm/gma500/psb_drv.h @@ -687,15 +687,15 @@ extern void psb_irq_turn_off_dpst(struct drm_device *dev); extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands); extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence); extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence); -extern int psb_enable_vblank(struct drm_device *dev, int crtc); -extern void psb_disable_vblank(struct drm_device *dev, int crtc); +extern int psb_enable_vblank(struct drm_device *dev, unsigned int pipe); +extern void psb_disable_vblank(struct drm_device *dev, unsigned int pipe); void psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); void psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask); -extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc); +extern u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe); /* framebuffer.c */ extern int psbfb_probed(struct drm_device *dev); diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c index 624eb36511c5..78eb10902809 100644 --- a/drivers/gpu/drm/gma500/psb_irq.c +++ b/drivers/gpu/drm/gma500/psb_irq.c @@ -510,7 +510,7 @@ int psb_irq_disable_dpst(struct drm_device *dev) /* * It is used to enable VBLANK interrupt */ -int psb_enable_vblank(struct drm_device *dev, int pipe) +int psb_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_psb_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -549,7 +549,7 @@ int psb_enable_vblank(struct drm_device *dev, int pipe) /* * It is used to disable VBLANK interrupt */ -void psb_disable_vblank(struct drm_device *dev, int pipe) +void psb_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_psb_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -622,7 +622,7 @@ void mdfld_disable_te(struct drm_device *dev, int pipe) /* Called from drm generic code, passed a 'crtc', which * we use as a pipe index */ -u32 psb_get_vblank_counter(struct drm_device *dev, int pipe) +u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { uint32_t high_frame = PIPEAFRAMEHIGH; uint32_t low_frame = PIPEAFRAMEPIXEL; @@ -654,7 +654,7 @@ u32 psb_get_vblank_counter(struct drm_device *dev, int pipe) reg_val = REG_READ(pipeconf_reg); if (!(reg_val & PIPEACONF_ENABLE)) { - dev_err(dev->dev, "trying to get vblank count for disabled pipe %d\n", + dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n", pipe); goto psb_get_vblank_counter_exit; } diff --git a/drivers/gpu/drm/gma500/psb_irq.h b/drivers/gpu/drm/gma500/psb_irq.h index d0b45ffa1126..e6a81a8c9f35 100644 --- a/drivers/gpu/drm/gma500/psb_irq.h +++ b/drivers/gpu/drm/gma500/psb_irq.h @@ -38,9 +38,9 @@ int psb_irq_enable_dpst(struct drm_device *dev); int psb_irq_disable_dpst(struct drm_device *dev); void psb_irq_turn_on_dpst(struct drm_device *dev); void psb_irq_turn_off_dpst(struct drm_device *dev); -int psb_enable_vblank(struct drm_device *dev, int pipe); -void psb_disable_vblank(struct drm_device *dev, int pipe); -u32 psb_get_vblank_counter(struct drm_device *dev, int pipe); +int psb_enable_vblank(struct drm_device *dev, unsigned int pipe); +void psb_disable_vblank(struct drm_device *dev, unsigned int pipe); +u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe); int mdfld_enable_te(struct drm_device *dev, int pipe); void mdfld_disable_te(struct drm_device *dev, int pipe); diff --git a/drivers/gpu/drm/i2c/tda998x_drv.c b/drivers/gpu/drm/i2c/tda998x_drv.c index 424228be79ae..896b6aaf8c4d 100644 --- a/drivers/gpu/drm/i2c/tda998x_drv.c +++ b/drivers/gpu/drm/i2c/tda998x_drv.c @@ -23,7 +23,6 @@ #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> -#include <drm/drm_encoder_slave.h> #include <drm/drm_edid.h> #include <drm/drm_of.h> #include <drm/i2c/tda998x.h> @@ -34,9 +33,8 @@ struct tda998x_priv { struct i2c_client *cec; struct i2c_client *hdmi; struct mutex mutex; - struct delayed_work dwork; - uint16_t rev; - uint8_t current_page; + u16 rev; + u8 current_page; int dpms; bool is_hdmi_sink; u8 vip_cntrl_0; @@ -46,10 +44,21 @@ struct tda998x_priv { wait_queue_head_t wq_edid; volatile int wq_edid_wait; - struct drm_encoder *encoder; + + struct work_struct detect_work; + struct timer_list edid_delay_timer; + wait_queue_head_t edid_delay_waitq; + bool edid_delay_active; + + struct drm_encoder encoder; + struct drm_connector connector; }; -#define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) +#define conn_to_tda998x_priv(x) \ + container_of(x, struct tda998x_priv, connector) + +#define enc_to_tda998x_priv(x) \ + container_of(x, struct tda998x_priv, encoder) /* The TDA9988 series of devices use a paged register scheme.. to simplify * things we encode the page # in upper bits of the register #. To read/ @@ -326,6 +335,8 @@ struct tda998x_priv { # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ #define REG_CEC_RXSHPDINT 0xfd /* read */ +# define CEC_RXSHPDINT_RXSENS BIT(0) +# define CEC_RXSHPDINT_HPD BIT(1) #define REG_CEC_RXSHPDLEV 0xfe /* read */ # define CEC_RXSHPDLEV_RXSENS (1 << 0) # define CEC_RXSHPDLEV_HPD (1 << 1) @@ -345,10 +356,10 @@ struct tda998x_priv { #define TDA19988 0x0301 static void -cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val) +cec_write(struct tda998x_priv *priv, u16 addr, u8 val) { struct i2c_client *client = priv->cec; - uint8_t buf[] = {addr, val}; + u8 buf[] = {addr, val}; int ret; ret = i2c_master_send(client, buf, sizeof(buf)); @@ -356,11 +367,11 @@ cec_write(struct tda998x_priv *priv, uint16_t addr, uint8_t val) dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); } -static uint8_t -cec_read(struct tda998x_priv *priv, uint8_t addr) +static u8 +cec_read(struct tda998x_priv *priv, u8 addr) { struct i2c_client *client = priv->cec; - uint8_t val; + u8 val; int ret; ret = i2c_master_send(client, &addr, sizeof(addr)); @@ -379,11 +390,11 @@ fail: } static int -set_page(struct tda998x_priv *priv, uint16_t reg) +set_page(struct tda998x_priv *priv, u16 reg) { if (REG2PAGE(reg) != priv->current_page) { struct i2c_client *client = priv->hdmi; - uint8_t buf[] = { + u8 buf[] = { REG_CURPAGE, REG2PAGE(reg) }; int ret = i2c_master_send(client, buf, sizeof(buf)); @@ -399,10 +410,10 @@ set_page(struct tda998x_priv *priv, uint16_t reg) } static int -reg_read_range(struct tda998x_priv *priv, uint16_t reg, char *buf, int cnt) +reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) { struct i2c_client *client = priv->hdmi; - uint8_t addr = REG2ADDR(reg); + u8 addr = REG2ADDR(reg); int ret; mutex_lock(&priv->mutex); @@ -428,10 +439,10 @@ out: } static void -reg_write_range(struct tda998x_priv *priv, uint16_t reg, uint8_t *p, int cnt) +reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) { struct i2c_client *client = priv->hdmi; - uint8_t buf[cnt+1]; + u8 buf[cnt+1]; int ret; buf[0] = REG2ADDR(reg); @@ -450,9 +461,9 @@ out: } static int -reg_read(struct tda998x_priv *priv, uint16_t reg) +reg_read(struct tda998x_priv *priv, u16 reg) { - uint8_t val = 0; + u8 val = 0; int ret; ret = reg_read_range(priv, reg, &val, sizeof(val)); @@ -462,10 +473,10 @@ reg_read(struct tda998x_priv *priv, uint16_t reg) } static void -reg_write(struct tda998x_priv *priv, uint16_t reg, uint8_t val) +reg_write(struct tda998x_priv *priv, u16 reg, u8 val) { struct i2c_client *client = priv->hdmi; - uint8_t buf[] = {REG2ADDR(reg), val}; + u8 buf[] = {REG2ADDR(reg), val}; int ret; mutex_lock(&priv->mutex); @@ -481,10 +492,10 @@ out: } static void -reg_write16(struct tda998x_priv *priv, uint16_t reg, uint16_t val) +reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) { struct i2c_client *client = priv->hdmi; - uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; + u8 buf[] = {REG2ADDR(reg), val >> 8, val}; int ret; mutex_lock(&priv->mutex); @@ -500,7 +511,7 @@ out: } static void -reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val) +reg_set(struct tda998x_priv *priv, u16 reg, u8 val) { int old_val; @@ -510,7 +521,7 @@ reg_set(struct tda998x_priv *priv, uint16_t reg, uint8_t val) } static void -reg_clear(struct tda998x_priv *priv, uint16_t reg, uint8_t val) +reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) { int old_val; @@ -551,15 +562,50 @@ tda998x_reset(struct tda998x_priv *priv) reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); } -/* handle HDMI connect/disconnect */ -static void tda998x_hpd(struct work_struct *work) +/* + * The TDA998x has a problem when trying to read the EDID close to a + * HPD assertion: it needs a delay of 100ms to avoid timing out while + * trying to read EDID data. + * + * However, tda998x_encoder_get_modes() may be called at any moment + * after tda998x_connector_detect() indicates that we are connected, so + * we need to delay probing modes in tda998x_encoder_get_modes() after + * we have seen a HPD inactive->active transition. This code implements + * that delay. + */ +static void tda998x_edid_delay_done(unsigned long data) +{ + struct tda998x_priv *priv = (struct tda998x_priv *)data; + + priv->edid_delay_active = false; + wake_up(&priv->edid_delay_waitq); + schedule_work(&priv->detect_work); +} + +static void tda998x_edid_delay_start(struct tda998x_priv *priv) +{ + priv->edid_delay_active = true; + mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); +} + +static int tda998x_edid_delay_wait(struct tda998x_priv *priv) +{ + return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); +} + +/* + * We need to run the KMS hotplug event helper outside of our threaded + * interrupt routine as this can call back into our get_modes method, + * which will want to make use of interrupts. + */ +static void tda998x_detect_work(struct work_struct *work) { - struct delayed_work *dwork = to_delayed_work(work); struct tda998x_priv *priv = - container_of(dwork, struct tda998x_priv, dwork); + container_of(work, struct tda998x_priv, detect_work); + struct drm_device *dev = priv->encoder.dev; - if (priv->encoder && priv->encoder->dev) - drm_kms_helper_hotplug_event(priv->encoder->dev); + if (dev) + drm_kms_helper_hotplug_event(dev); } /* @@ -569,9 +615,8 @@ static irqreturn_t tda998x_irq_thread(int irq, void *data) { struct tda998x_priv *priv = data; u8 sta, cec, lvl, flag0, flag1, flag2; + bool handled = false; - if (!priv) - return IRQ_HANDLED; sta = cec_read(priv, REG_CEC_INTSTATUS); cec = cec_read(priv, REG_CEC_RXSHPDINT); lvl = cec_read(priv, REG_CEC_RXSHPDLEV); @@ -581,75 +626,76 @@ static irqreturn_t tda998x_irq_thread(int irq, void *data) DRM_DEBUG_DRIVER( "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", sta, cec, lvl, flag0, flag1, flag2); + + if (cec & CEC_RXSHPDINT_HPD) { + if (lvl & CEC_RXSHPDLEV_HPD) + tda998x_edid_delay_start(priv); + else + schedule_work(&priv->detect_work); + + handled = true; + } + if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { priv->wq_edid_wait = 0; wake_up(&priv->wq_edid); - } else if (cec != 0) { /* HPD change */ - schedule_delayed_work(&priv->dwork, HZ/10); + handled = true; } - return IRQ_HANDLED; -} -static uint8_t tda998x_cksum(uint8_t *buf, size_t bytes) -{ - int sum = 0; - - while (bytes--) - sum -= *buf++; - return sum; + return IRQ_RETVAL(handled); } -#define HB(x) (x) -#define PB(x) (HB(2) + 1 + (x)) - static void -tda998x_write_if(struct tda998x_priv *priv, uint8_t bit, uint16_t addr, - uint8_t *buf, size_t size) +tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr, + union hdmi_infoframe *frame) { + u8 buf[32]; + ssize_t len; + + len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); + if (len < 0) { + dev_err(&priv->hdmi->dev, + "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", + frame->any.type, len); + return; + } + reg_clear(priv, REG_DIP_IF_FLAGS, bit); - reg_write_range(priv, addr, buf, size); + reg_write_range(priv, addr, buf, len); reg_set(priv, REG_DIP_IF_FLAGS, bit); } static void tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p) { - u8 buf[PB(HDMI_AUDIO_INFOFRAME_SIZE) + 1]; + union hdmi_infoframe frame; + + hdmi_audio_infoframe_init(&frame.audio); - memset(buf, 0, sizeof(buf)); - buf[HB(0)] = HDMI_INFOFRAME_TYPE_AUDIO; - buf[HB(1)] = 0x01; - buf[HB(2)] = HDMI_AUDIO_INFOFRAME_SIZE; - buf[PB(1)] = p->audio_frame[1] & 0x07; /* CC */ - buf[PB(2)] = p->audio_frame[2] & 0x1c; /* SF */ - buf[PB(4)] = p->audio_frame[4]; - buf[PB(5)] = p->audio_frame[5] & 0xf8; /* DM_INH + LSV */ + frame.audio.channels = p->audio_frame[1] & 0x07; + frame.audio.channel_allocation = p->audio_frame[4]; + frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3; + frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7; - buf[PB(0)] = tda998x_cksum(buf, sizeof(buf)); + /* + * L-PCM and IEC61937 compressed audio shall always set sample + * frequency to "refer to stream". For others, see the HDMI + * specification. + */ + frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2; - tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, buf, - sizeof(buf)); + tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); } static void tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode) { - struct hdmi_avi_infoframe frame; - u8 buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; - ssize_t len; + union hdmi_infoframe frame; - drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); + drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode); + frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; - frame.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; - - len = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); - if (len < 0) { - dev_err(&priv->hdmi->dev, - "hdmi_avi_infoframe_pack() failed: %zd\n", len); - return; - } - - tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, buf, len); + tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); } static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) @@ -667,8 +713,8 @@ static void tda998x_configure_audio(struct tda998x_priv *priv, struct drm_display_mode *mode, struct tda998x_encoder_params *p) { - uint8_t buf[6], clksel_aip, clksel_fs, cts_n, adiv; - uint32_t n; + u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv; + u32 n; /* Enable audio ports */ reg_write(priv, REG_ENA_AP, p->audio_cfg); @@ -776,8 +822,10 @@ static void tda998x_encoder_set_config(struct tda998x_priv *priv, priv->params = *p; } -static void tda998x_encoder_dpms(struct tda998x_priv *priv, int mode) +static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) { + struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); + /* we only care about on or off: */ if (mode != DRM_MODE_DPMS_ON) mode = DRM_MODE_DPMS_OFF; @@ -827,8 +875,8 @@ tda998x_encoder_mode_fixup(struct drm_encoder *encoder, return true; } -static int tda998x_encoder_mode_valid(struct tda998x_priv *priv, - struct drm_display_mode *mode) +static int tda998x_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) { if (mode->clock > 150000) return MODE_CLOCK_HIGH; @@ -840,18 +888,19 @@ static int tda998x_encoder_mode_valid(struct tda998x_priv *priv, } static void -tda998x_encoder_mode_set(struct tda998x_priv *priv, +tda998x_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { - uint16_t ref_pix, ref_line, n_pix, n_line; - uint16_t hs_pix_s, hs_pix_e; - uint16_t vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; - uint16_t vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; - uint16_t vwin1_line_s, vwin1_line_e; - uint16_t vwin2_line_s, vwin2_line_e; - uint16_t de_pix_s, de_pix_e; - uint8_t reg, div, rep; + struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); + u16 ref_pix, ref_line, n_pix, n_line; + u16 hs_pix_s, hs_pix_e; + u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; + u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; + u16 vwin1_line_s, vwin1_line_e; + u16 vwin2_line_s, vwin2_line_e; + u16 de_pix_s, de_pix_e; + u8 reg, div, rep; /* * Internally TDA998x is using ITU-R BT.656 style sync but @@ -1031,9 +1080,10 @@ tda998x_encoder_mode_set(struct tda998x_priv *priv, } static enum drm_connector_status -tda998x_encoder_detect(struct tda998x_priv *priv) +tda998x_connector_detect(struct drm_connector *connector, bool force) { - uint8_t val = cec_read(priv, REG_CEC_RXSHPDLEV); + struct tda998x_priv *priv = conn_to_tda998x_priv(connector); + u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : connector_status_disconnected; @@ -1042,7 +1092,7 @@ tda998x_encoder_detect(struct tda998x_priv *priv) static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) { struct tda998x_priv *priv = data; - uint8_t offset, segptr; + u8 offset, segptr; int ret, i; offset = (blk & 1) ? 128 : 0; @@ -1095,13 +1145,20 @@ static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) return 0; } -static int -tda998x_encoder_get_modes(struct tda998x_priv *priv, - struct drm_connector *connector) +static int tda998x_connector_get_modes(struct drm_connector *connector) { + struct tda998x_priv *priv = conn_to_tda998x_priv(connector); struct edid *edid; int n; + /* + * If we get killed while waiting for the HPD timeout, return + * no modes found: we are not in a restartable path, so we + * can't handle signals gracefully. + */ + if (tda998x_edid_delay_wait(priv)) + return 0; + if (priv->rev == TDA19988) reg_clear(priv, REG_TX4, TX4_PD_RAM); @@ -1133,101 +1190,21 @@ static void tda998x_encoder_set_polling(struct tda998x_priv *priv, DRM_CONNECTOR_POLL_DISCONNECT; } -static int -tda998x_encoder_set_property(struct drm_encoder *encoder, - struct drm_connector *connector, - struct drm_property *property, - uint64_t val) -{ - DBG(""); - return 0; -} - static void tda998x_destroy(struct tda998x_priv *priv) { /* disable all IRQs and free the IRQ handler */ cec_write(priv, REG_CEC_RXSHPDINTENA, 0); reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); - if (priv->hdmi->irq) { - free_irq(priv->hdmi->irq, priv); - cancel_delayed_work_sync(&priv->dwork); - } - - i2c_unregister_device(priv->cec); -} - -/* Slave encoder support */ - -static void -tda998x_encoder_slave_set_config(struct drm_encoder *encoder, void *params) -{ - tda998x_encoder_set_config(to_tda998x_priv(encoder), params); -} -static void tda998x_encoder_slave_destroy(struct drm_encoder *encoder) -{ - struct tda998x_priv *priv = to_tda998x_priv(encoder); - - tda998x_destroy(priv); - drm_i2c_encoder_destroy(encoder); - kfree(priv); -} - -static void tda998x_encoder_slave_dpms(struct drm_encoder *encoder, int mode) -{ - tda998x_encoder_dpms(to_tda998x_priv(encoder), mode); -} - -static int tda998x_encoder_slave_mode_valid(struct drm_encoder *encoder, - struct drm_display_mode *mode) -{ - return tda998x_encoder_mode_valid(to_tda998x_priv(encoder), mode); -} + if (priv->hdmi->irq) + free_irq(priv->hdmi->irq, priv); -static void -tda998x_encoder_slave_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - tda998x_encoder_mode_set(to_tda998x_priv(encoder), mode, adjusted_mode); -} + del_timer_sync(&priv->edid_delay_timer); + cancel_work_sync(&priv->detect_work); -static enum drm_connector_status -tda998x_encoder_slave_detect(struct drm_encoder *encoder, - struct drm_connector *connector) -{ - return tda998x_encoder_detect(to_tda998x_priv(encoder)); -} - -static int tda998x_encoder_slave_get_modes(struct drm_encoder *encoder, - struct drm_connector *connector) -{ - return tda998x_encoder_get_modes(to_tda998x_priv(encoder), connector); -} - -static int -tda998x_encoder_slave_create_resources(struct drm_encoder *encoder, - struct drm_connector *connector) -{ - tda998x_encoder_set_polling(to_tda998x_priv(encoder), connector); - return 0; + i2c_unregister_device(priv->cec); } -static struct drm_encoder_slave_funcs tda998x_encoder_slave_funcs = { - .set_config = tda998x_encoder_slave_set_config, - .destroy = tda998x_encoder_slave_destroy, - .dpms = tda998x_encoder_slave_dpms, - .save = tda998x_encoder_save, - .restore = tda998x_encoder_restore, - .mode_fixup = tda998x_encoder_mode_fixup, - .mode_valid = tda998x_encoder_slave_mode_valid, - .mode_set = tda998x_encoder_slave_mode_set, - .detect = tda998x_encoder_slave_detect, - .get_modes = tda998x_encoder_slave_get_modes, - .create_resources = tda998x_encoder_slave_create_resources, - .set_property = tda998x_encoder_set_property, -}; - /* I2C driver functions */ static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) @@ -1252,6 +1229,10 @@ static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) priv->dpms = DRM_MODE_DPMS_OFF; mutex_init(&priv->mutex); /* protect the page access */ + init_waitqueue_head(&priv->edid_delay_waitq); + setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done, + (unsigned long)priv); + INIT_WORK(&priv->detect_work, tda998x_detect_work); /* wake up the device: */ cec_write(priv, REG_CEC_ENAMODS, @@ -1310,7 +1291,6 @@ static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv) /* init read EDID waitqueue and HDP work */ init_waitqueue_head(&priv->wq_edid); - INIT_DELAYED_WORK(&priv->dwork, tda998x_hpd); /* clear pending interrupts */ reg_read(priv, REG_INT_FLAGS_0); @@ -1359,84 +1339,31 @@ fail: return -ENXIO; } -static int tda998x_encoder_init(struct i2c_client *client, - struct drm_device *dev, - struct drm_encoder_slave *encoder_slave) -{ - struct tda998x_priv *priv; - int ret; - - priv = kzalloc(sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->encoder = &encoder_slave->base; - - ret = tda998x_create(client, priv); - if (ret) { - kfree(priv); - return ret; - } - - encoder_slave->slave_priv = priv; - encoder_slave->slave_funcs = &tda998x_encoder_slave_funcs; - - return 0; -} - -struct tda998x_priv2 { - struct tda998x_priv base; - struct drm_encoder encoder; - struct drm_connector connector; -}; - -#define conn_to_tda998x_priv2(x) \ - container_of(x, struct tda998x_priv2, connector); - -#define enc_to_tda998x_priv2(x) \ - container_of(x, struct tda998x_priv2, encoder); - -static void tda998x_encoder2_dpms(struct drm_encoder *encoder, int mode) -{ - struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder); - - tda998x_encoder_dpms(&priv->base, mode); -} - static void tda998x_encoder_prepare(struct drm_encoder *encoder) { - tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_OFF); + tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); } static void tda998x_encoder_commit(struct drm_encoder *encoder) { - tda998x_encoder2_dpms(encoder, DRM_MODE_DPMS_ON); -} - -static void tda998x_encoder2_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder); - - tda998x_encoder_mode_set(&priv->base, mode, adjusted_mode); + tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON); } static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = { - .dpms = tda998x_encoder2_dpms, + .dpms = tda998x_encoder_dpms, .save = tda998x_encoder_save, .restore = tda998x_encoder_restore, .mode_fixup = tda998x_encoder_mode_fixup, .prepare = tda998x_encoder_prepare, .commit = tda998x_encoder_commit, - .mode_set = tda998x_encoder2_mode_set, + .mode_set = tda998x_encoder_mode_set, }; static void tda998x_encoder_destroy(struct drm_encoder *encoder) { - struct tda998x_priv2 *priv = enc_to_tda998x_priv2(encoder); + struct tda998x_priv *priv = enc_to_tda998x_priv(encoder); - tda998x_destroy(&priv->base); + tda998x_destroy(priv); drm_encoder_cleanup(encoder); } @@ -1444,25 +1371,10 @@ static const struct drm_encoder_funcs tda998x_encoder_funcs = { .destroy = tda998x_encoder_destroy, }; -static int tda998x_connector_get_modes(struct drm_connector *connector) -{ - struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); - - return tda998x_encoder_get_modes(&priv->base, connector); -} - -static int tda998x_connector_mode_valid(struct drm_connector *connector, - struct drm_display_mode *mode) -{ - struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); - - return tda998x_encoder_mode_valid(&priv->base, mode); -} - static struct drm_encoder * tda998x_connector_best_encoder(struct drm_connector *connector) { - struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); + struct tda998x_priv *priv = conn_to_tda998x_priv(connector); return &priv->encoder; } @@ -1474,14 +1386,6 @@ const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { .best_encoder = tda998x_connector_best_encoder, }; -static enum drm_connector_status -tda998x_connector_detect(struct drm_connector *connector, bool force) -{ - struct tda998x_priv2 *priv = conn_to_tda998x_priv2(connector); - - return tda998x_encoder_detect(&priv->base); -} - static void tda998x_connector_destroy(struct drm_connector *connector) { drm_connector_unregister(connector); @@ -1500,8 +1404,8 @@ static int tda998x_bind(struct device *dev, struct device *master, void *data) struct tda998x_encoder_params *params = dev->platform_data; struct i2c_client *client = to_i2c_client(dev); struct drm_device *drm = data; - struct tda998x_priv2 *priv; - uint32_t crtcs = 0; + struct tda998x_priv *priv; + u32 crtcs = 0; int ret; priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); @@ -1519,18 +1423,17 @@ static int tda998x_bind(struct device *dev, struct device *master, void *data) crtcs = 1 << 0; } - priv->base.encoder = &priv->encoder; priv->connector.interlace_allowed = 1; priv->encoder.possible_crtcs = crtcs; - ret = tda998x_create(client, &priv->base); + ret = tda998x_create(client, priv); if (ret) return ret; if (!dev->of_node && params) - tda998x_encoder_set_config(&priv->base, params); + tda998x_encoder_set_config(priv, params); - tda998x_encoder_set_polling(&priv->base, &priv->connector); + tda998x_encoder_set_polling(priv, &priv->connector); drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs); ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs, @@ -1560,18 +1463,18 @@ err_sysfs: err_connector: drm_encoder_cleanup(&priv->encoder); err_encoder: - tda998x_destroy(&priv->base); + tda998x_destroy(priv); return ret; } static void tda998x_unbind(struct device *dev, struct device *master, void *data) { - struct tda998x_priv2 *priv = dev_get_drvdata(dev); + struct tda998x_priv *priv = dev_get_drvdata(dev); drm_connector_cleanup(&priv->connector); drm_encoder_cleanup(&priv->encoder); - tda998x_destroy(&priv->base); + tda998x_destroy(priv); } static const struct component_ops tda998x_ops = { @@ -1605,38 +1508,18 @@ static struct i2c_device_id tda998x_ids[] = { }; MODULE_DEVICE_TABLE(i2c, tda998x_ids); -static struct drm_i2c_encoder_driver tda998x_driver = { - .i2c_driver = { - .probe = tda998x_probe, - .remove = tda998x_remove, - .driver = { - .name = "tda998x", - .of_match_table = of_match_ptr(tda998x_dt_ids), - }, - .id_table = tda998x_ids, +static struct i2c_driver tda998x_driver = { + .probe = tda998x_probe, + .remove = tda998x_remove, + .driver = { + .name = "tda998x", + .of_match_table = of_match_ptr(tda998x_dt_ids), }, - .encoder_init = tda998x_encoder_init, + .id_table = tda998x_ids, }; -/* Module initialization */ - -static int __init -tda998x_init(void) -{ - DBG(""); - return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); -} - -static void __exit -tda998x_exit(void) -{ - DBG(""); - drm_i2c_encoder_unregister(&tda998x_driver); -} +module_i2c_driver(tda998x_driver); MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); MODULE_LICENSE("GPL"); - -module_init(tda998x_init); -module_exit(tda998x_exit); diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 1676388a62df..a3b22bdacd44 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -956,7 +956,6 @@ static int i915_gem_fence_regs_info(struct seq_file *m, void *data) if (ret) return ret; - seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start); seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs); for (i = 0; i < dev_priv->num_fence_regs; i++) { struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj; diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 499060a08d25..b4741d121a74 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -75,7 +75,7 @@ static int i915_getparam(struct drm_device *dev, void *data, value = 1; break; case I915_PARAM_NUM_FENCES_AVAIL: - value = dev_priv->num_fence_regs - dev_priv->fence_reg_start; + value = dev_priv->num_fence_regs; break; case I915_PARAM_HAS_OVERLAY: value = dev_priv->overlay ? 1 : 0; @@ -183,35 +183,6 @@ static int i915_getparam(struct drm_device *dev, void *data, return 0; } -static int i915_setparam(struct drm_device *dev, void *data, - struct drm_file *file_priv) -{ - struct drm_i915_private *dev_priv = dev->dev_private; - drm_i915_setparam_t *param = data; - - switch (param->param) { - case I915_SETPARAM_USE_MI_BATCHBUFFER_START: - case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY: - case I915_SETPARAM_ALLOW_BATCHBUFFER: - /* Reject all old ums/dri params. */ - return -ENODEV; - - case I915_SETPARAM_NUM_USED_FENCES: - if (param->value > dev_priv->num_fence_regs || - param->value < 0) - return -EINVAL; - /* Userspace can use first N regs */ - dev_priv->fence_reg_start = param->value; - break; - default: - DRM_DEBUG_DRIVER("unknown parameter %d\n", - param->param); - return -EINVAL; - } - - return 0; -} - static int i915_get_bridge_dev(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -435,10 +406,7 @@ static int i915_load_modeset_init(struct drm_device *dev) * working irqs for e.g. gmbus and dp aux transfers. */ intel_modeset_init(dev); - /* intel_guc_ucode_init() needs the mutex to allocate GEM objects */ - mutex_lock(&dev->struct_mutex); intel_guc_ucode_init(dev); - mutex_unlock(&dev->struct_mutex); ret = i915_gem_init(dev); if (ret) @@ -481,9 +449,7 @@ cleanup_gem: i915_gem_context_fini(dev); mutex_unlock(&dev->struct_mutex); cleanup_irq: - mutex_lock(&dev->struct_mutex); intel_guc_ucode_fini(dev); - mutex_unlock(&dev->struct_mutex); drm_irq_uninstall(dev); cleanup_gem_stolen: i915_gem_cleanup_stolen(dev); @@ -1222,8 +1188,8 @@ int i915_driver_unload(struct drm_device *dev) /* Flush any outstanding unpin_work. */ flush_workqueue(dev_priv->wq); - mutex_lock(&dev->struct_mutex); intel_guc_ucode_fini(dev); + mutex_lock(&dev->struct_mutex); i915_gem_cleanup_ringbuffer(dev); i915_gem_context_fini(dev); mutex_unlock(&dev->struct_mutex); @@ -1318,7 +1284,7 @@ const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), @@ -1328,41 +1294,41 @@ const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH), + DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0), + DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW), + DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW), + DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), }; int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index dd0429c612a4..8afda459a26e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1786,7 +1786,6 @@ struct drm_i915_private { struct mutex pps_mutex; struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ - int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ int num_fence_regs; /* 8 on pre-965, 16 otherwise */ unsigned int fsb_freq, mem_freq, is_ddr3; diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c index 1cbfd5b83135..40a10b25956c 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence.c +++ b/drivers/gpu/drm/i915/i915_gem_fence.c @@ -317,7 +317,7 @@ i915_find_fence_reg(struct drm_device *dev) /* First try to find a free reg */ avail = NULL; - for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { + for (i = 0; i < dev_priv->num_fence_regs; i++) { reg = &dev_priv->fence_regs[i]; if (!reg->obj) return reg; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 684a0d9909e7..0d228f909dcb 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -653,7 +653,7 @@ static void i915_enable_asle_pipestat(struct drm_device *dev) * of horizontal active on the first line of vertical active */ -static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) +static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { /* Gen2 doesn't have a hardware frame counter */ return 0; @@ -662,7 +662,7 @@ static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) /* Called from drm generic code, passed a 'crtc', which * we use as a pipe index */ -static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) +static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long high_frame; @@ -710,7 +710,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; } -static u32 g4x_get_vblank_counter(struct drm_device *dev, int pipe) +static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -770,7 +770,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) return (position + crtc->scanline_offset) % vtotal; } -static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, +static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, unsigned int flags, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode) @@ -907,27 +907,27 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) return position; } -static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, +static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, unsigned flags) { struct drm_crtc *crtc; - if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { - DRM_ERROR("Invalid crtc %d\n", pipe); + if (pipe >= INTEL_INFO(dev)->num_pipes) { + DRM_ERROR("Invalid crtc %u\n", pipe); return -EINVAL; } /* Get drm_crtc to timestamp: */ crtc = intel_get_crtc_for_pipe(dev, pipe); if (crtc == NULL) { - DRM_ERROR("Invalid crtc %d\n", pipe); + DRM_ERROR("Invalid crtc %u\n", pipe); return -EINVAL; } if (!crtc->hwmode.crtc_clock) { - DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); + DRM_DEBUG_KMS("crtc %u is disabled\n", pipe); return -EBUSY; } @@ -2619,7 +2619,7 @@ void i915_handle_error(struct drm_device *dev, bool wedged, /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */ -static int i915_enable_vblank(struct drm_device *dev, int pipe) +static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -2636,7 +2636,7 @@ static int i915_enable_vblank(struct drm_device *dev, int pipe) return 0; } -static int ironlake_enable_vblank(struct drm_device *dev, int pipe) +static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -2650,7 +2650,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, int pipe) return 0; } -static int valleyview_enable_vblank(struct drm_device *dev, int pipe) +static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -2663,7 +2663,7 @@ static int valleyview_enable_vblank(struct drm_device *dev, int pipe) return 0; } -static int gen8_enable_vblank(struct drm_device *dev, int pipe) +static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -2679,7 +2679,7 @@ static int gen8_enable_vblank(struct drm_device *dev, int pipe) /* Called from drm generic code, passed 'crtc' which * we use as a pipe index */ -static void i915_disable_vblank(struct drm_device *dev, int pipe) +static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -2691,7 +2691,7 @@ static void i915_disable_vblank(struct drm_device *dev, int pipe) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } -static void ironlake_disable_vblank(struct drm_device *dev, int pipe) +static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -2703,7 +2703,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, int pipe) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } -static void valleyview_disable_vblank(struct drm_device *dev, int pipe) +static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; @@ -2714,7 +2714,7 @@ static void valleyview_disable_vblank(struct drm_device *dev, int pipe) spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); } -static void gen8_disable_vblank(struct drm_device *dev, int pipe) +static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = dev->dev_private; unsigned long irqflags; diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 15372598b2c3..0639275fc471 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -458,11 +458,17 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); drm_mode_connector_set_path_property(connector, pathprop); + return connector; +} + +static void intel_dp_register_mst_connector(struct drm_connector *connector) +{ + struct intel_connector *intel_connector = to_intel_connector(connector); + struct drm_device *dev = connector->dev; drm_modeset_lock_all(dev); intel_connector_add_to_fbdev(intel_connector); drm_modeset_unlock_all(dev); drm_connector_register(&intel_connector->base); - return connector; } static void intel_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, @@ -508,6 +514,7 @@ static void intel_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) static struct drm_dp_mst_topology_cbs mst_cbs = { .add_connector = intel_dp_add_mst_connector, + .register_connector = intel_dp_register_mst_connector, .destroy_connector = intel_dp_destroy_mst_connector, .hotplug = intel_dp_mst_hotplug, }; diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index a17b6a56be83..3541f76c65a7 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -504,7 +504,9 @@ static void guc_fw_fetch(struct drm_device *dev, struct intel_guc_fw *guc_fw) guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found, guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted); + mutex_lock(&dev->struct_mutex); obj = i915_gem_object_create_from_data(dev, fw->data, fw->size); + mutex_unlock(&dev->struct_mutex); if (IS_ERR_OR_NULL(obj)) { err = obj ? PTR_ERR(obj) : -ENOMEM; goto fail; @@ -540,8 +542,6 @@ fail: * @dev: drm device * * Called early during driver load, but after GEM is initialised. - * The device struct_mutex must be held by the caller, as we're - * going to allocate a GEM object to hold the firmware image. * * The firmware will be transferred to the GuC's memory later, * when intel_guc_ucode_load() is called. @@ -598,9 +598,11 @@ void intel_guc_ucode_fini(struct drm_device *dev) direct_interrupts_to_host(dev_priv); i915_guc_submission_fini(dev); + mutex_lock(&dev->struct_mutex); if (guc_fw->guc_fw_obj) drm_gem_object_unreference(&guc_fw->guc_fw_obj->base); guc_fw->guc_fw_obj = NULL; + mutex_unlock(&dev->struct_mutex); guc_fw->guc_fw_fetch_status = GUC_FIRMWARE_NONE; } diff --git a/drivers/gpu/drm/i915/intel_hotplug.c b/drivers/gpu/drm/i915/intel_hotplug.c index 53c0173a39fe..b17785719598 100644 --- a/drivers/gpu/drm/i915/intel_hotplug.c +++ b/drivers/gpu/drm/i915/intel_hotplug.c @@ -180,7 +180,7 @@ static void intel_hpd_irq_storm_disable(struct drm_i915_private *dev_priv) /* Enable polling and queue hotplug re-enabling. */ if (hpd_disabled) { - drm_kms_helper_poll_enable(dev); + drm_kms_helper_poll_enable_locked(dev); mod_delayed_work(system_wq, &dev_priv->hotplug.reenable_work, msecs_to_jiffies(HPD_STORM_REENABLE_DELAY)); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 1bb1c9c8126e..efb704ba248b 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -511,16 +511,16 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring) status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); read_pointer = ring->next_context_status_buffer; - write_pointer = status_pointer & 0x07; + write_pointer = status_pointer & GEN8_CSB_PTR_MASK; if (read_pointer > write_pointer) - write_pointer += 6; + write_pointer += GEN8_CSB_ENTRIES; spin_lock(&ring->execlist_lock); while (read_pointer < write_pointer) { read_pointer++; - status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % 6)); - status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % 6)); + status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, read_pointer % GEN8_CSB_ENTRIES)); + status_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, read_pointer % GEN8_CSB_ENTRIES)); if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) continue; @@ -552,10 +552,12 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring) spin_unlock(&ring->execlist_lock); WARN(submit_contexts > 2, "More than two context complete events?\n"); - ring->next_context_status_buffer = write_pointer % 6; + ring->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES; I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), - _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8)); + _MASKED_FIELD(GEN8_CSB_PTR_MASK << 8, + ((u32)ring->next_context_status_buffer & + GEN8_CSB_PTR_MASK) << 8)); } static int execlists_context_queue(struct drm_i915_gem_request *request) @@ -1462,6 +1464,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; + u8 next_context_status_buffer_hw; lrc_setup_hardware_status_page(ring, ring->default_context->engine[ring->id].state); @@ -1479,7 +1482,29 @@ static int gen8_init_common_ring(struct intel_engine_cs *ring) _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); POSTING_READ(RING_MODE_GEN7(ring)); - ring->next_context_status_buffer = 0; + + /* + * Instead of resetting the Context Status Buffer (CSB) read pointer to + * zero, we need to read the write pointer from hardware and use its + * value because "this register is power context save restored". + * Effectively, these states have been observed: + * + * | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) | + * BDW | CSB regs not reset | CSB regs reset | + * CHT | CSB regs not reset | CSB regs not reset | + */ + next_context_status_buffer_hw = (I915_READ(RING_CONTEXT_STATUS_PTR(ring)) + & GEN8_CSB_PTR_MASK); + + /* + * When the CSB registers are reset (also after power-up / gpu reset), + * CSB write pointer is set to all 1's, which is not valid, use '5' in + * this special case, so the first element read is CSB[0]. + */ + if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK) + next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1); + + ring->next_context_status_buffer = next_context_status_buffer_hw; DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 8a08a2780321..4e60d54ba66d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -25,6 +25,8 @@ #define _INTEL_LRC_H_ #define GEN8_LR_CONTEXT_ALIGN 4096 +#define GEN8_CSB_ENTRIES 6 +#define GEN8_CSB_PTR_MASK 0x07 /* Execlists regs */ #define RING_ELSP(ring) ((ring)->mmio_base+0x230) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 1aedf2762dff..d89c1d0aa1b7 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -246,7 +246,8 @@ static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, } if (power_well->data == SKL_DISP_PW_1) { - intel_prepare_ddi(dev); + if (!dev_priv->power_domains.initializing) + intel_prepare_ddi(dev); gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); } } diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c index 644edf65dbe0..98605ea2ad9d 100644 --- a/drivers/gpu/drm/imx/dw_hdmi-imx.c +++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c @@ -48,11 +48,17 @@ static const struct dw_hdmi_mpll_config imx_mpll_cfg[] = { { 0x40a2, 0x000a }, }, }, { - ~0UL, { + 216000000, { { 0x00a0, 0x000a }, { 0x2001, 0x000f }, { 0x4002, 0x000f }, }, + }, { + ~0UL, { + { 0x0000, 0x0000 }, + { 0x0000, 0x0000 }, + { 0x0000, 0x0000 }, + }, } }; @@ -82,7 +88,7 @@ static const struct dw_hdmi_curr_ctrl imx_cur_ctr[] = { */ static const struct dw_hdmi_phy_config imx_phy_config[] = { /*pixelclk symbol term vlev */ - { 148500000, 0x800d, 0x0005, 0x01ad}, + { 216000000, 0x800d, 0x0005, 0x01ad}, { ~0UL, 0x0000, 0x0000, 0x0000} }; @@ -148,7 +154,8 @@ static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con, { if (mode->clock < 13500) return MODE_CLOCK_LOW; - if (mode->clock > 266000) + /* FIXME: Hardware is capable of 266MHz, but setup data is missing. */ + if (mode->clock > 216000) return MODE_CLOCK_HIGH; return MODE_OK; @@ -159,7 +166,8 @@ static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con, { if (mode->clock < 13500) return MODE_CLOCK_LOW; - if (mode->clock > 270000) + /* FIXME: Hardware is capable of 270MHz, but setup data is missing. */ + if (mode->clock > 216000) return MODE_CLOCK_HIGH; return MODE_OK; diff --git a/drivers/gpu/drm/imx/imx-drm-core.c b/drivers/gpu/drm/imx/imx-drm-core.c index 74f505b0dd02..64f16ea779ef 100644 --- a/drivers/gpu/drm/imx/imx-drm-core.c +++ b/drivers/gpu/drm/imx/imx-drm-core.c @@ -145,10 +145,10 @@ void imx_drm_handle_vblank(struct imx_drm_crtc *imx_drm_crtc) } EXPORT_SYMBOL_GPL(imx_drm_handle_vblank); -static int imx_drm_enable_vblank(struct drm_device *drm, int crtc) +static int imx_drm_enable_vblank(struct drm_device *drm, unsigned int pipe) { struct imx_drm_device *imxdrm = drm->dev_private; - struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc]; + struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[pipe]; int ret; if (!imx_drm_crtc) @@ -163,10 +163,10 @@ static int imx_drm_enable_vblank(struct drm_device *drm, int crtc) return ret; } -static void imx_drm_disable_vblank(struct drm_device *drm, int crtc) +static void imx_drm_disable_vblank(struct drm_device *drm, unsigned int pipe) { struct imx_drm_device *imxdrm = drm->dev_private; - struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[crtc]; + struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[pipe]; if (!imx_drm_crtc) return; @@ -487,7 +487,7 @@ static struct drm_driver imx_drm_driver = { .gem_prime_vmap = drm_gem_cma_prime_vmap, .gem_prime_vunmap = drm_gem_cma_prime_vunmap, .gem_prime_mmap = drm_gem_cma_prime_mmap, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = imx_drm_enable_vblank, .disable_vblank = imx_drm_disable_vblank, .ioctls = imx_drm_ioctls, @@ -531,59 +531,12 @@ static const struct component_master_ops imx_drm_ops = { static int imx_drm_platform_probe(struct platform_device *pdev) { - struct device_node *ep, *port, *remote; - struct component_match *match = NULL; - int ret; - int i; - - /* - * Bind the IPU display interface ports first, so that - * imx_drm_encoder_parse_of called from encoder .bind callbacks - * works as expected. - */ - for (i = 0; ; i++) { - port = of_parse_phandle(pdev->dev.of_node, "ports", i); - if (!port) - break; - - component_match_add(&pdev->dev, &match, compare_of, port); - } + int ret = drm_of_component_probe(&pdev->dev, compare_of, &imx_drm_ops); - if (i == 0) { - dev_err(&pdev->dev, "missing 'ports' property\n"); - return -ENODEV; - } + if (!ret) + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); - /* Then bind all encoders */ - for (i = 0; ; i++) { - port = of_parse_phandle(pdev->dev.of_node, "ports", i); - if (!port) - break; - - for_each_child_of_node(port, ep) { - remote = of_graph_get_remote_port_parent(ep); - if (!remote || !of_device_is_available(remote)) { - of_node_put(remote); - continue; - } else if (!of_device_is_available(remote->parent)) { - dev_warn(&pdev->dev, "parent device of %s is not available\n", - remote->full_name); - of_node_put(remote); - continue; - } - - component_match_add(&pdev->dev, &match, compare_of, - remote); - of_node_put(remote); - } - of_node_put(port); - } - - ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); - if (ret) - return ret; - - return component_master_add_with_match(&pdev->dev, &imx_drm_ops, match); + return ret; } static int imx_drm_platform_remove(struct platform_device *pdev) diff --git a/drivers/gpu/drm/imx/ipuv3-plane.c b/drivers/gpu/drm/imx/ipuv3-plane.c index 878a643d72e4..575f4c84388f 100644 --- a/drivers/gpu/drm/imx/ipuv3-plane.c +++ b/drivers/gpu/drm/imx/ipuv3-plane.c @@ -23,12 +23,21 @@ #define to_ipu_plane(x) container_of(x, struct ipu_plane, base) static const uint32_t ipu_plane_formats[] = { + DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ABGR1555, DRM_FORMAT_XBGR1555, + DRM_FORMAT_RGBA5551, + DRM_FORMAT_BGRA5551, + DRM_FORMAT_ARGB4444, DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_XBGR8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_RGBX8888, + DRM_FORMAT_BGRA8888, + DRM_FORMAT_BGRA8888, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU, DRM_FORMAT_YUV420, @@ -175,8 +184,15 @@ int ipu_plane_mode_set(struct ipu_plane *ipu_plane, struct drm_crtc *crtc, ipu_dp_set_window_pos(ipu_plane->dp, crtc_x, crtc_y); /* Enable local alpha on partial plane */ switch (fb->pixel_format) { + case DRM_FORMAT_ARGB1555: + case DRM_FORMAT_ABGR1555: + case DRM_FORMAT_RGBA5551: + case DRM_FORMAT_BGRA5551: + case DRM_FORMAT_ARGB4444: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_BGRA8888: ipu_dp_set_global_alpha(ipu_plane->dp, false, 0, false); break; default: diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c index 8cfa9cb74c86..1f2f9ca25901 100644 --- a/drivers/gpu/drm/mga/mga_dma.c +++ b/drivers/gpu/drm/mga/mga_dma.c @@ -416,7 +416,7 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags) return 0; } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) /** * Bootstrap the driver for AGP DMA. * @@ -947,7 +947,7 @@ static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup) drm_legacy_ioremapfree(dev->agp_buffer_map, dev); if (dev_priv->used_new_dma_init) { -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->agp_handle != 0) { struct drm_agp_binding unbind_req; struct drm_agp_buffer free_req; diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h index b4a2014917e5..bb312339e0b0 100644 --- a/drivers/gpu/drm/mga/mga_drv.h +++ b/drivers/gpu/drm/mga/mga_drv.h @@ -183,9 +183,9 @@ extern int mga_warp_install_microcode(drm_mga_private_t *dev_priv); extern int mga_warp_init(drm_mga_private_t *dev_priv); /* mga_irq.c */ -extern int mga_enable_vblank(struct drm_device *dev, int crtc); -extern void mga_disable_vblank(struct drm_device *dev, int crtc); -extern u32 mga_get_vblank_counter(struct drm_device *dev, int crtc); +extern int mga_enable_vblank(struct drm_device *dev, unsigned int pipe); +extern void mga_disable_vblank(struct drm_device *dev, unsigned int pipe); +extern u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe); extern int mga_driver_fence_wait(struct drm_device *dev, unsigned int *sequence); extern int mga_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence); extern irqreturn_t mga_driver_irq_handler(int irq, void *arg); diff --git a/drivers/gpu/drm/mga/mga_irq.c b/drivers/gpu/drm/mga/mga_irq.c index 1b071b8ff9dc..693ba708cfed 100644 --- a/drivers/gpu/drm/mga/mga_irq.c +++ b/drivers/gpu/drm/mga/mga_irq.c @@ -35,12 +35,12 @@ #include <drm/mga_drm.h> #include "mga_drv.h" -u32 mga_get_vblank_counter(struct drm_device *dev, int crtc) +u32 mga_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { const drm_mga_private_t *const dev_priv = (drm_mga_private_t *) dev->dev_private; - if (crtc != 0) + if (pipe != 0) return 0; return atomic_read(&dev_priv->vbl_received); @@ -88,13 +88,13 @@ irqreturn_t mga_driver_irq_handler(int irq, void *arg) return IRQ_NONE; } -int mga_enable_vblank(struct drm_device *dev, int crtc) +int mga_enable_vblank(struct drm_device *dev, unsigned int pipe) { drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private; - if (crtc != 0) { - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); + if (pipe != 0) { + DRM_ERROR("tried to enable vblank on non-existent crtc %u\n", + pipe); return 0; } @@ -103,11 +103,11 @@ int mga_enable_vblank(struct drm_device *dev, int crtc) } -void mga_disable_vblank(struct drm_device *dev, int crtc) +void mga_disable_vblank(struct drm_device *dev, unsigned int pipe) { - if (crtc != 0) { - DRM_ERROR("tried to disable vblank on non-existent crtc %d\n", - crtc); + if (pipe != 0) { + DRM_ERROR("tried to disable vblank on non-existent crtc %u\n", + pipe); } /* Do *NOT* disable the vertical refresh interrupt. MGA doesn't have diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 8e6c7c638e24..84d3ec98e6b9 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -14,20 +14,6 @@ config DRM_MSM help DRM/KMS driver for MSM/snapdragon. -config DRM_MSM_FBDEV - bool "Enable legacy fbdev support for MSM modesetting driver" - depends on DRM_MSM - select DRM_KMS_FB_HELPER - select FB_SYS_FILLRECT - select FB_SYS_COPYAREA - select FB_SYS_IMAGEBLIT - select FB_SYS_FOPS - default y - help - Choose this option if you have a need for the legacy fbdev - support. Note that this support also provide the linux console - support on top of the MSM modesetting driver. - config DRM_MSM_REGISTER_LOGGING bool "MSM DRM register logging" depends on DRM_MSM diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 0a543eb5e5d7..1c90290be716 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -50,7 +50,7 @@ msm-y := \ msm_rd.o \ msm_ringbuffer.o -msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o +msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index 0261f0d31612..9e2aceb4ffe6 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2015 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h index 48d133711487..97dc1c6ec107 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2015 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) @@ -280,6 +281,8 @@ enum a3xx_rb_blend_opcode { enum a3xx_intp_mode { SMOOTH = 0, FLAT = 1, + ZERO = 2, + ONE = 3, }; enum a3xx_repl_mode { @@ -680,9 +683,16 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 +#define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 +#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000 +#define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26 +static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) +{ + return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; +} #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff @@ -773,7 +783,7 @@ static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) { - return ((((int32_t)(val * 16384.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; + return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; } #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d @@ -894,6 +904,9 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 +#define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001 +#define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002 +#define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 @@ -907,6 +920,8 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000 +#define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000 +#define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 @@ -914,6 +929,8 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compar { return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; } +#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000 +#define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h index ac55066db3b0..99de8271dba8 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2015 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) @@ -162,10 +163,13 @@ enum a4xx_tex_fmt { TFMT4_8_UNORM = 4, TFMT4_8_8_UNORM = 14, TFMT4_8_8_8_8_UNORM = 28, + TFMT4_8_SNORM = 5, TFMT4_8_8_SNORM = 15, TFMT4_8_8_8_8_SNORM = 29, + TFMT4_8_UINT = 6, TFMT4_8_8_UINT = 16, TFMT4_8_8_8_8_UINT = 30, + TFMT4_8_SINT = 7, TFMT4_8_8_SINT = 17, TFMT4_8_8_8_8_SINT = 31, TFMT4_16_UINT = 21, @@ -246,7 +250,8 @@ enum a4xx_tex_clamp { A4XX_TEX_REPEAT = 0, A4XX_TEX_CLAMP_TO_EDGE = 1, A4XX_TEX_MIRROR_REPEAT = 2, - A4XX_TEX_CLAMP_NONE = 3, + A4XX_TEX_CLAMP_TO_BORDER = 3, + A4XX_TEX_MIRROR_CLAMP = 4, }; enum a4xx_tex_aniso { diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h index 399a9e528139..c304468cf2bd 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2015 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) @@ -85,6 +86,10 @@ enum adreno_rb_blend_factor { FACTOR_CONSTANT_ALPHA = 14, FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, FACTOR_SRC_ALPHA_SATURATE = 16, + FACTOR_SRC1_COLOR = 20, + FACTOR_ONE_MINUS_SRC1_COLOR = 21, + FACTOR_SRC1_ALPHA = 22, + FACTOR_ONE_MINUS_SRC1_ALPHA = 23, }; enum adreno_rb_surface_endian { diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index 41904fed1350..a22fef569499 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h @@ -8,13 +8,14 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55) - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67120 bytes, from 2015-08-14 23:22:03) -- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63785 bytes, from 2015-08-14 18:27:06) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 67771 bytes, from 2015-09-14 20:46:55) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63970 bytes, from 2015-09-14 20:50:12) +- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00) Copyright (C) 2013-2015 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 1d2e32f0817b..b2b5f3dd1b4c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) @@ -567,114 +567,234 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000 -static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; } +static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } -static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; } +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } -static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; } +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } -static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; } +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } -static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; } +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } -static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; } +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*i0; } -static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; } +static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*i0; } -#define REG_DSI_8960_PHY_LNCK_CFG_0 0x00000400 +#define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100 -#define REG_DSI_8960_PHY_LNCK_CFG_1 0x00000404 +#define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104 -#define REG_DSI_8960_PHY_LNCK_CFG_2 0x00000408 +#define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108 -#define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH 0x0000040c +#define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c -#define REG_DSI_8960_PHY_LNCK_TEST_STR0 0x00000414 +#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114 -#define REG_DSI_8960_PHY_LNCK_TEST_STR1 0x00000418 +#define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118 -#define REG_DSI_8960_PHY_TIMING_CTRL_0 0x00000440 +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140 +#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144 +#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148 +#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150 +#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154 +#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158 +#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c +#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160 +#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164 +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007 +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK; +} +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070 +#define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT 4 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168 +#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007 +#define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK; +} + +#define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c +#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff +#define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0 +static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) +{ + return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK; +} + +#define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170 + +#define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174 + +#define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178 + +#define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c + +#define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180 + +#define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184 + +#define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198 + +#define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c -#define REG_DSI_8960_PHY_TIMING_CTRL_1 0x00000444 +#define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0 -#define REG_DSI_8960_PHY_TIMING_CTRL_2 0x00000448 +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000 -#define REG_DSI_8960_PHY_TIMING_CTRL_3 0x0000044c +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004 -#define REG_DSI_8960_PHY_TIMING_CTRL_4 0x00000450 +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008 -#define REG_DSI_8960_PHY_TIMING_CTRL_5 0x00000454 +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c -#define REG_DSI_8960_PHY_TIMING_CTRL_6 0x00000458 +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010 -#define REG_DSI_8960_PHY_TIMING_CTRL_7 0x0000045c +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014 -#define REG_DSI_8960_PHY_TIMING_CTRL_8 0x00000460 +#define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018 -#define REG_DSI_8960_PHY_TIMING_CTRL_9 0x00000464 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028 -#define REG_DSI_8960_PHY_TIMING_CTRL_10 0x00000468 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c -#define REG_DSI_8960_PHY_TIMING_CTRL_11 0x0000046c +#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030 -#define REG_DSI_8960_PHY_CTRL_0 0x00000470 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034 -#define REG_DSI_8960_PHY_CTRL_1 0x00000474 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038 -#define REG_DSI_8960_PHY_CTRL_2 0x00000478 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c -#define REG_DSI_8960_PHY_CTRL_3 0x0000047c +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040 -#define REG_DSI_8960_PHY_STRENGTH_0 0x00000480 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044 -#define REG_DSI_8960_PHY_STRENGTH_1 0x00000484 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048 -#define REG_DSI_8960_PHY_STRENGTH_2 0x00000488 +#define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050 +#define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010 -#define REG_DSI_8960_PHY_BIST_CTRL_0 0x0000048c +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000 +#define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001 -#define REG_DSI_8960_PHY_BIST_CTRL_1 0x00000490 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004 -#define REG_DSI_8960_PHY_BIST_CTRL_2 0x00000494 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008 -#define REG_DSI_8960_PHY_BIST_CTRL_3 0x00000498 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c -#define REG_DSI_8960_PHY_BIST_CTRL_4 0x0000049c +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010 -#define REG_DSI_8960_PHY_LDO_CTRL 0x000004b0 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014 -#define REG_DSI_8960_PHY_REGULATOR_CTRL_0 0x00000500 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018 -#define REG_DSI_8960_PHY_REGULATOR_CTRL_1 0x00000504 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c -#define REG_DSI_8960_PHY_REGULATOR_CTRL_2 0x00000508 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020 -#define REG_DSI_8960_PHY_REGULATOR_CTRL_3 0x0000050c +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024 -#define REG_DSI_8960_PHY_REGULATOR_CTRL_4 0x00000510 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028 -#define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG 0x00000518 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c -#define REG_DSI_8960_PHY_CAL_HW_TRIGGER 0x00000528 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030 -#define REG_DSI_8960_PHY_CAL_SW_CFG_0 0x0000052c +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034 -#define REG_DSI_8960_PHY_CAL_SW_CFG_1 0x00000530 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038 -#define REG_DSI_8960_PHY_CAL_SW_CFG_2 0x00000534 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c -#define REG_DSI_8960_PHY_CAL_HW_CFG_0 0x00000538 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040 -#define REG_DSI_8960_PHY_CAL_HW_CFG_1 0x0000053c +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044 -#define REG_DSI_8960_PHY_CAL_HW_CFG_2 0x00000540 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048 -#define REG_DSI_8960_PHY_CAL_HW_CFG_3 0x00000544 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c -#define REG_DSI_8960_PHY_CAL_HW_CFG_4 0x00000548 +#define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050 -#define REG_DSI_8960_PHY_CAL_STATUS 0x00000550 -#define DSI_8960_PHY_CAL_STATUS_CAL_BUSY 0x00000010 +#define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080 +#define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 8d82973fe9db..4c49868efcda 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -278,7 +278,7 @@ static int dsi_regulator_init(struct msm_dsi_host *msm_host) } for (i = 0; i < num; i++) { - if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) { + if (regulator_can_change_voltage(s[i].consumer)) { ret = regulator_set_voltage(s[i].consumer, regs[i].min_voltage, regs[i].max_voltage); if (ret < 0) { diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h index 5de505e627be..80ec65e47468 100644 --- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h +++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index 401ff58d6893..f1f955f571fa 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -178,7 +178,7 @@ static int dsi_phy_regulator_init(struct msm_dsi_phy *phy) } for (i = 0; i < num; i++) { - if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) { + if (regulator_can_change_voltage(s[i].consumer)) { ret = regulator_set_voltage(s[i].consumer, regs[i].min_voltage, regs[i].max_voltage); if (ret < 0) { diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index f1a7c7b46420..edf74110ced7 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -99,16 +99,14 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id, dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0); + dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1); dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97); } - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa); - dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf); + dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_4, 0); dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0); dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1); dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb); diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h index 06cbddfc914f..7d7662e69e11 100644 --- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h +++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) @@ -45,7 +45,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#define REG_SFPB_CFG 0x00000058 +enum sfpb_ahb_arb_master_port_en { + SFPB_MASTER_PORT_ENABLE = 3, + SFPB_MASTER_PORT_DISABLE = 0, +}; + +#define REG_SFPB_GPREG 0x00000058 +#define SFPB_GPREG_MASTER_PORT_EN__MASK 0x00001800 +#define SFPB_GPREG_MASTER_PORT_EN__SHIFT 11 +static inline uint32_t SFPB_GPREG_MASTER_PORT_EN(enum sfpb_ahb_arb_master_port_en val) +{ + return ((val) << SFPB_GPREG_MASTER_PORT_EN__SHIFT) & SFPB_GPREG_MASTER_PORT_EN__MASK; +} #endif /* SFPB_XML */ diff --git a/drivers/gpu/drm/msm/edp/edp.xml.h b/drivers/gpu/drm/msm/edp/edp.xml.h index bef1d65fe28c..90bf5ed46746 100644 --- a/drivers/gpu/drm/msm/edp/edp.xml.h +++ b/drivers/gpu/drm/msm/edp/edp.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 101b324cdeef..1f4a95eeb348 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -328,6 +328,9 @@ fail: .item ## _names = item ##_names_ ## entry, \ .item ## _cnt = ARRAY_SIZE(item ## _names_ ## entry) +static const char *pwr_reg_names_none[] = {}; +static const char *hpd_reg_names_none[] = {}; + static struct hdmi_platform_config hdmi_tx_8660_config = { .phy_init = hdmi_phy_8x60_init, }; @@ -367,18 +370,26 @@ static struct hdmi_platform_config hdmi_tx_8084_config = { .hpd_freq = hpd_clk_freq_8x74, }; -static const char *hpd_reg_names_8x94[] = {}; - static struct hdmi_platform_config hdmi_tx_8994_config = { .phy_init = NULL, /* nothing to do for this HDMI PHY 20nm */ HDMI_CFG(pwr_reg, 8x74), - HDMI_CFG(hpd_reg, 8x94), + HDMI_CFG(hpd_reg, none), + HDMI_CFG(pwr_clk, 8x74), + HDMI_CFG(hpd_clk, 8x74), + .hpd_freq = hpd_clk_freq_8x74, +}; + +static struct hdmi_platform_config hdmi_tx_8996_config = { + .phy_init = NULL, + HDMI_CFG(pwr_reg, none), + HDMI_CFG(hpd_reg, none), HDMI_CFG(pwr_clk, 8x74), HDMI_CFG(hpd_clk, 8x74), .hpd_freq = hpd_clk_freq_8x74, }; static const struct of_device_id dt_match[] = { + { .compatible = "qcom,hdmi-tx-8996", .data = &hdmi_tx_8996_config }, { .compatible = "qcom,hdmi-tx-8994", .data = &hdmi_tx_8994_config }, { .compatible = "qcom,hdmi-tx-8084", .data = &hdmi_tx_8084_config }, { .compatible = "qcom,hdmi-tx-8974", .data = &hdmi_tx_8974_config }, diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h index 0b1b5586ff35..10c45700aefe 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h index 2aa23b98f8aa..dbd9cc4daf2e 100644 --- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h +++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h index 74b86734fef5..d5d94575fa1b 100644 --- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h index 3469f50d5590..c37da9c61e29 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) @@ -895,6 +895,7 @@ static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val) #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000 #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000 +#define MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE 0x80000000 static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000003c + __offset_PIPE(i0); } @@ -932,6 +933,83 @@ static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val) return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK; } +static inline uint32_t __offset_SW_PIX_EXT(enum mdp_component_type idx) +{ + switch (idx) { + case COMP_0: return 0x00000100; + case COMP_1_2: return 0x00000110; + case COMP_3: return 0x00000120; + default: return INVALID_IDX(idx); + } +} +static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } + +static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } +#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK 0x000000ff +#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT 0 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(uint32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT__MASK; +} +#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK 0x0000ff00 +#define MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT 8 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(int32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF__MASK; +} +#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK 0x00ff0000 +#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT 16 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(uint32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT__MASK; +} +#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK 0xff000000 +#define MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT 24 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(int32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF__MASK; +} + +static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } +#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK 0x000000ff +#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT 0 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(uint32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT__MASK; +} +#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK 0x0000ff00 +#define MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT 8 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(int32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF__MASK; +} +#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK 0x00ff0000 +#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT 16 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(uint32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT__MASK; +} +#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK 0xff000000 +#define MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT 24 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(int32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__SHIFT) & MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF__MASK; +} + +static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } +#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK 0x0000ffff +#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT 0 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(uint32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT__MASK; +} +#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK 0xffff0000 +#define MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT 16 +static inline uint32_t MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(uint32_t val) +{ + return ((val) << MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__SHIFT) & MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM__MASK; +} + static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00000204 + __offset_PIPE(i0); } #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001 #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002 diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c index a1e26f23c7cc..bb1225aa2f75 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c @@ -27,6 +27,8 @@ const struct mdp5_cfg_hw msm8x74v1_config = { .mdp = { .count = 1, .base = { 0x00100 }, + .caps = MDP_CAP_SMP | + 0, }, .smp = { .mmb_count = 22, @@ -96,6 +98,8 @@ const struct mdp5_cfg_hw msm8x74v2_config = { .mdp = { .count = 1, .base = { 0x00100 }, + .caps = MDP_CAP_SMP | + 0, }, .smp = { .mmb_count = 22, @@ -165,6 +169,8 @@ const struct mdp5_cfg_hw apq8084_config = { .mdp = { .count = 1, .base = { 0x00100 }, + .caps = MDP_CAP_SMP | + 0, }, .smp = { .mmb_count = 44, @@ -242,6 +248,8 @@ const struct mdp5_cfg_hw msm8x16_config = { .mdp = { .count = 1, .base = { 0x01000 }, + .caps = MDP_CAP_SMP | + 0, }, .smp = { .mmb_count = 8, @@ -301,6 +309,8 @@ const struct mdp5_cfg_hw msm8x94_config = { .mdp = { .count = 1, .base = { 0x01000 }, + .caps = MDP_CAP_SMP | + 0, }, .smp = { .mmb_count = 44, @@ -370,7 +380,89 @@ const struct mdp5_cfg_hw msm8x94_config = { [3] = INTF_HDMI, }, }, - .max_clk = 320000000, + .max_clk = 400000000, +}; + +const struct mdp5_cfg_hw msm8x96_config = { + .name = "msm8x96", + .mdp = { + .count = 1, + .base = { 0x01000 }, + .caps = MDP_CAP_DSC | + MDP_CAP_CDM | + 0, + }, + .ctl = { + .count = 5, + .base = { 0x02000, 0x02200, 0x02400, 0x02600, 0x02800 }, + .flush_hw_mask = 0xf4ffffff, + }, + .pipe_vig = { + .count = 4, + .base = { 0x05000, 0x07000, 0x09000, 0x0b000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + MDP_PIPE_CAP_CSC | + MDP_PIPE_CAP_DECIMATION | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_rgb = { + .count = 4, + .base = { 0x15000, 0x17000, 0x19000, 0x1b000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + MDP_PIPE_CAP_DECIMATION | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .pipe_dma = { + .count = 2, + .base = { 0x25000, 0x27000 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SW_PIX_EXT | + 0, + }, + .lm = { + .count = 6, + .base = { 0x45000, 0x46000, 0x47000, 0x48000, 0x49000, 0x4a000 }, + .nb_stages = 8, + .max_width = 2560, + .max_height = 0xFFFF, + }, + .dspp = { + .count = 2, + .base = { 0x55000, 0x57000 }, + }, + .ad = { + .count = 3, + .base = { 0x79000, 0x79800, 0x7a000 }, + }, + .pp = { + .count = 4, + .base = { 0x71000, 0x71800, 0x72000, 0x72800 }, + }, + .cdm = { + .count = 1, + .base = { 0x7a200 }, + }, + .dsc = { + .count = 2, + .base = { 0x81000, 0x81400 }, + }, + .intf = { + .base = { 0x6b000, 0x6b800, 0x6c000, 0x6c800, 0x6d000 }, + .connect = { + [0] = INTF_DISABLED, + [1] = INTF_DSI, + [2] = INTF_DSI, + [3] = INTF_HDMI, + }, + }, + .max_clk = 412500000, }; static const struct mdp5_cfg_handler cfg_handlers[] = { @@ -379,6 +471,7 @@ static const struct mdp5_cfg_handler cfg_handlers[] = { { .revision = 3, .config = { .hw = &apq8084_config } }, { .revision = 6, .config = { .hw = &msm8x16_config } }, { .revision = 9, .config = { .hw = &msm8x94_config } }, + { .revision = 7, .config = { .hw = &msm8x96_config } }, }; static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev); diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h index efb918d9f68b..050e1618c836 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h @@ -61,7 +61,12 @@ struct mdp5_smp_block { int mmb_size; /* MMB: size in bytes */ uint32_t clients[MAX_CLIENTS]; /* SMP port allocation /pipe */ mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */ - int reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */ + uint8_t reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */ +}; + +struct mdp5_mdp_block { + MDP5_SUB_BLOCK_DEFINITION; + uint32_t caps; /* MDP capabilities: MDP_CAP_xxx bits */ }; #define MDP5_INTF_NUM_MAX 5 @@ -74,7 +79,7 @@ struct mdp5_intf_block { struct mdp5_cfg_hw { char *name; - struct mdp5_sub_block mdp; + struct mdp5_mdp_block mdp; struct mdp5_smp_block smp; struct mdp5_ctl_block ctl; struct mdp5_pipe_block pipe_vig; @@ -84,6 +89,8 @@ struct mdp5_cfg_hw { struct mdp5_sub_block dspp; struct mdp5_sub_block ad; struct mdp5_sub_block pp; + struct mdp5_sub_block dsc; + struct mdp5_sub_block cdm; struct mdp5_intf_block intf; uint32_t max_clk; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index 047cb0433ccb..b532faa8026d 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -452,15 +452,19 @@ static void read_hw_revision(struct mdp5_kms *mdp5_kms, } static int get_clk(struct platform_device *pdev, struct clk **clkp, - const char *name) + const char *name, bool mandatory) { struct device *dev = &pdev->dev; struct clk *clk = devm_clk_get(dev, name); - if (IS_ERR(clk)) { + if (IS_ERR(clk) && mandatory) { dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); return PTR_ERR(clk); } - *clkp = clk; + if (IS_ERR(clk)) + DBG("skipping %s", name); + else + *clkp = clk; + return 0; } @@ -514,25 +518,26 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) goto fail; } - ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk"); + /* mandatory clocks: */ + ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk", true); if (ret) goto fail; - ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk"); + ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk", true); if (ret) goto fail; - ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src"); + ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src", true); if (ret) goto fail; - ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk"); + ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk", true); if (ret) goto fail; - ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk"); - if (ret) - DBG("failed to get (optional) lut_clk clock"); - ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk"); + ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk", true); if (ret) goto fail; + /* optional clocks: */ + get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk", false); + /* we need to set a default rate before enabling. Set a safe * rate first, then figure out hw revision, and then set a * more optimal rate: @@ -549,15 +554,23 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) } config = mdp5_cfg_get_config(mdp5_kms->cfg); + mdp5_kms->caps = config->hw->mdp.caps; /* TODO: compute core clock rate at runtime */ clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk); - mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); - if (IS_ERR(mdp5_kms->smp)) { - ret = PTR_ERR(mdp5_kms->smp); - mdp5_kms->smp = NULL; - goto fail; + /* + * Some chipsets have a Shared Memory Pool (SMP), while others + * have dedicated latency buffering per source pipe instead; + * this section initializes the SMP: + */ + if (mdp5_kms->caps & MDP_CAP_SMP) { + mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp); + if (IS_ERR(mdp5_kms->smp)) { + ret = PTR_ERR(mdp5_kms->smp); + mdp5_kms->smp = NULL; + goto fail; + } } mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg); @@ -586,6 +599,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) if (IS_ERR(mmu)) { ret = PTR_ERR(mmu); dev_err(dev->dev, "failed to init iommu: %d\n", ret); + iommu_domain_free(config->platform.iommu); goto fail; } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index 0bb62423586e..84f65d415598 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -32,6 +32,8 @@ struct mdp5_kms { struct drm_device *dev; struct mdp5_cfg_handler *cfg; + uint32_t caps; /* MDP capabilities (MDP_CAP_XXX bits) */ + /* mapper-id used to request GEM buffer mapped for scanout: */ int id; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c index a0f5ff0ce8dc..81cd49045ffc 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c @@ -500,7 +500,7 @@ static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase) static int calc_scalex_steps(struct drm_plane *plane, uint32_t pixel_format, uint32_t src, uint32_t dest, - uint32_t phasex_steps[2]) + uint32_t phasex_steps[COMP_MAX]) { struct mdp5_kms *mdp5_kms = get_kms(plane); struct device *dev = mdp5_kms->dev->dev; @@ -516,15 +516,16 @@ static int calc_scalex_steps(struct drm_plane *plane, hsub = drm_format_horz_chroma_subsampling(pixel_format); - phasex_steps[0] = phasex_step; - phasex_steps[1] = phasex_step / hsub; + phasex_steps[COMP_0] = phasex_step; + phasex_steps[COMP_3] = phasex_step; + phasex_steps[COMP_1_2] = phasex_step / hsub; return 0; } static int calc_scaley_steps(struct drm_plane *plane, uint32_t pixel_format, uint32_t src, uint32_t dest, - uint32_t phasey_steps[2]) + uint32_t phasey_steps[COMP_MAX]) { struct mdp5_kms *mdp5_kms = get_kms(plane); struct device *dev = mdp5_kms->dev->dev; @@ -540,46 +541,127 @@ static int calc_scaley_steps(struct drm_plane *plane, vsub = drm_format_vert_chroma_subsampling(pixel_format); - phasey_steps[0] = phasey_step; - phasey_steps[1] = phasey_step / vsub; + phasey_steps[COMP_0] = phasey_step; + phasey_steps[COMP_3] = phasey_step; + phasey_steps[COMP_1_2] = phasey_step / vsub; return 0; } -static uint32_t get_scale_config(enum mdp_chroma_samp_type chroma_sample, - uint32_t src, uint32_t dest, bool hor) +static uint32_t get_scale_config(const struct mdp_format *format, + uint32_t src, uint32_t dst, bool horz) { - uint32_t y_filter = (src <= dest) ? SCALE_FILTER_CA : SCALE_FILTER_PCMN; - uint32_t y_a_filter = (src <= dest) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; - uint32_t uv_filter = ((src / 2) <= dest) ? /* 2x upsample */ - SCALE_FILTER_BIL : SCALE_FILTER_PCMN; - uint32_t value = 0; - - if (chroma_sample == CHROMA_420 || chroma_sample == CHROMA_H2V1) { - if (hor) - value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | - MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_filter) | - MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter) | - MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter); - else - value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | - MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_filter) | - MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter) | - MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter); - } else if (src != dest) { - if (hor) - value = MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | - MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(y_a_filter) | - MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(y_a_filter); - else - value = MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | - MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(y_a_filter) | - MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(y_a_filter); + bool scaling = format->is_yuv ? true : (src != dst); + uint32_t sub, pix_fmt = format->base.pixel_format; + uint32_t ya_filter, uv_filter; + bool yuv = format->is_yuv; + + if (!scaling) + return 0; + + if (yuv) { + sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) : + drm_format_vert_chroma_subsampling(pix_fmt); + uv_filter = ((src / sub) <= dst) ? + SCALE_FILTER_BIL : SCALE_FILTER_PCMN; } + ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN; - return value; + if (horz) + return MDP5_PIPE_SCALE_CONFIG_SCALEX_EN | + MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) | + MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) | + COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter)); + else + return MDP5_PIPE_SCALE_CONFIG_SCALEY_EN | + MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) | + MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) | + COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter)); } +static void calc_pixel_ext(const struct mdp_format *format, + uint32_t src, uint32_t dst, uint32_t phase_step[2], + int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], + bool horz) +{ + bool scaling = format->is_yuv ? true : (src != dst); + int i; + + /* + * Note: + * We assume here that: + * 1. PCMN filter is used for downscale + * 2. bilinear filter is used for upscale + * 3. we are in a single pipe configuration + */ + + for (i = 0; i < COMP_MAX; i++) { + pix_ext_edge1[i] = 0; + pix_ext_edge2[i] = scaling ? 1 : 0; + } +} + +static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe, + const struct mdp_format *format, + uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX], + uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX]) +{ + uint32_t pix_fmt = format->base.pixel_format; + uint32_t lr, tb, req; + int i; + + for (i = 0; i < COMP_MAX; i++) { + uint32_t roi_w = src_w; + uint32_t roi_h = src_h; + + if (format->is_yuv && i == COMP_1_2) { + roi_w /= drm_format_horz_chroma_subsampling(pix_fmt); + roi_h /= drm_format_vert_chroma_subsampling(pix_fmt); + } + + lr = (pe_left[i] >= 0) ? + MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) : + MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]); + + lr |= (pe_right[i] >= 0) ? + MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) : + MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]); + + tb = (pe_top[i] >= 0) ? + MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) : + MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]); + + tb |= (pe_bottom[i] >= 0) ? + MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) : + MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]); + + req = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w + + pe_left[i] + pe_right[i]); + + req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h + + pe_top[i] + pe_bottom[i]); + + mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr); + mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb); + mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req); + + DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i, + FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), + FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), + FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), + FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), + FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); + + DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i, + FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), + FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), + FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), + FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), + FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); + } +} + + static int mdp5_plane_mode_set(struct drm_plane *plane, struct drm_crtc *crtc, struct drm_framebuffer *fb, int crtc_x, int crtc_y, @@ -593,8 +675,10 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, enum mdp5_pipe pipe = mdp5_plane->pipe; const struct mdp_format *format; uint32_t nplanes, config = 0; - /* below array -> index 0: comp 0/3 ; index 1: comp 1/2 */ - uint32_t phasex_step[2] = {0,}, phasey_step[2] = {0,}; + uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,}; + bool pe = mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT; + int pe_left[COMP_MAX], pe_right[COMP_MAX]; + int pe_top[COMP_MAX], pe_bottom[COMP_MAX]; uint32_t hdecm = 0, vdecm = 0; uint32_t pix_format; bool vflip, hflip; @@ -621,10 +705,12 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h); /* Request some memory from the SMP: */ - ret = mdp5_smp_request(mdp5_kms->smp, - mdp5_plane->pipe, format, src_w, false); - if (ret) - return ret; + if (mdp5_kms->smp) { + ret = mdp5_smp_request(mdp5_kms->smp, + mdp5_plane->pipe, format, src_w, false); + if (ret) + return ret; + } /* * Currently we update the hw for allocations/requests immediately, @@ -632,7 +718,8 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, * would move into atomic->check_plane_state(), while updating the * hw would remain here: */ - mdp5_smp_configure(mdp5_kms->smp, pipe); + if (mdp5_kms->smp) + mdp5_smp_configure(mdp5_kms->smp, pipe); ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step); if (ret) @@ -642,11 +729,18 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, if (ret) return ret; + if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) { + calc_pixel_ext(format, src_w, crtc_w, phasex_step, + pe_left, pe_right, true); + calc_pixel_ext(format, src_h, crtc_h, phasey_step, + pe_top, pe_bottom, false); + } + /* TODO calc hdecm, vdecm */ /* SCALE is used to both scale and up-sample chroma components */ - config |= get_scale_config(format->chroma_sample, src_w, crtc_w, true); - config |= get_scale_config(format->chroma_sample, src_h, crtc_h, false); + config |= get_scale_config(format, src_w, crtc_w, true); + config |= get_scale_config(format, src_h, crtc_h, false); DBG("scale config = %x", config); hflip = !!(pstate->rotation & BIT(DRM_REFLECT_X)); @@ -695,20 +789,26 @@ static int mdp5_plane_mode_set(struct drm_plane *plane, mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe), (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) | (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) | + COND(pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) | MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS)); /* not using secure mode: */ mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0); + if (mdp5_plane->caps & MDP_PIPE_CAP_SW_PIX_EXT) + mdp5_write_pixel_ext(mdp5_kms, pipe, format, + src_w, pe_left, pe_right, + src_h, pe_top, pe_bottom); + if (mdp5_plane->caps & MDP_PIPE_CAP_SCALE) { mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe), - phasex_step[0]); + phasex_step[COMP_0]); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe), - phasey_step[0]); + phasey_step[COMP_0]); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe), - phasex_step[1]); + phasex_step[COMP_1_2]); mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe), - phasey_step[1]); + phasey_step[COMP_1_2]); mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe), MDP5_PIPE_DECIMATION_VERT(vdecm) | MDP5_PIPE_DECIMATION_HORZ(hdecm)); @@ -738,7 +838,8 @@ void mdp5_plane_complete_flip(struct drm_plane *plane) DBG("%s: complete flip", mdp5_plane->name); - mdp5_smp_commit(mdp5_kms->smp, pipe); + if (mdp5_kms->smp) + mdp5_smp_commit(mdp5_kms->smp, pipe); to_mdp5_plane_state(plane->state)->pending = false; } @@ -764,7 +865,7 @@ void mdp5_plane_complete_commit(struct drm_plane *plane, struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane); enum mdp5_pipe pipe = mdp5_plane->pipe; - if (!plane_enabled(plane->state)) { + if (!plane_enabled(plane->state) && mdp5_kms->smp) { DBG("%s: free SMP", mdp5_plane->name); mdp5_smp_release(mdp5_kms->smp, pipe); } diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c index 563cca972dcb..6f425c25d9fe 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_smp.c @@ -90,7 +90,7 @@ struct mdp5_smp { struct drm_device *dev; - const struct mdp5_smp_block *cfg; + uint8_t reserved[MAX_CLIENTS]; /* fixed MMBs allocation per client */ int blk_cnt; int blk_size; @@ -141,10 +141,10 @@ static int smp_request_block(struct mdp5_smp *smp, struct mdp5_kms *mdp5_kms = get_kms(smp); struct mdp5_client_smp_state *ps = &smp->client_state[cid]; int i, ret, avail, cur_nblks, cnt = smp->blk_cnt; - int reserved; + uint8_t reserved; unsigned long flags; - reserved = smp->cfg->reserved[cid]; + reserved = smp->reserved[cid]; spin_lock_irqsave(&smp->state_lock, flags); @@ -405,12 +405,12 @@ struct mdp5_smp *mdp5_smp_init(struct drm_device *dev, const struct mdp5_smp_blo } smp->dev = dev; - smp->cfg = cfg; smp->blk_cnt = cfg->mmb_count; smp->blk_size = cfg->mmb_size; /* statically tied MMBs cannot be re-allocated: */ bitmap_copy(smp->state, cfg->reserved_state, smp->blk_cnt); + memcpy(smp->reserved, cfg->reserved, sizeof(smp->reserved)); spin_lock_init(&smp->state_lock); return smp; diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h index 4f792c4e40f4..0aec1ac1f6d0 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h +++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h @@ -11,10 +11,10 @@ The rules-ng-ng source files this header was generated from are: - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2576 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36021 bytes, from 2015-07-09 22:10:24) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 26057 bytes, from 2015-08-14 21:47:57) -- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2015-05-20 20:03:07) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37194 bytes, from 2015-09-18 12:07:28) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52) +- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02) - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07) - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29154 bytes, from 2015-08-10 21:25:43) @@ -78,6 +78,13 @@ enum mdp_alpha_type { BG_PIXEL = 3, }; +enum mdp_component_type { + COMP_0 = 0, + COMP_1_2 = 1, + COMP_3 = 2, + COMP_MAX = 3, +}; + enum mdp_bpc { BPC1 = 0, BPC5 = 1, diff --git a/drivers/gpu/drm/msm/mdp/mdp_kms.h b/drivers/gpu/drm/msm/mdp/mdp_kms.h index 46a94e7d50e2..303130320748 100644 --- a/drivers/gpu/drm/msm/mdp/mdp_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp_kms.h @@ -100,12 +100,18 @@ struct mdp_format { uint32_t mdp_get_formats(uint32_t *formats, uint32_t max_formats, bool rgb_only); const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format); +/* MDP capabilities */ +#define MDP_CAP_SMP BIT(0) /* Shared Memory Pool */ +#define MDP_CAP_DSC BIT(1) /* VESA Display Stream Compression */ +#define MDP_CAP_CDM BIT(2) /* Chroma Down Module (HDMI 2.0 YUV) */ + /* MDP pipe capabilities */ #define MDP_PIPE_CAP_HFLIP BIT(0) #define MDP_PIPE_CAP_VFLIP BIT(1) #define MDP_PIPE_CAP_SCALE BIT(2) #define MDP_PIPE_CAP_CSC BIT(3) #define MDP_PIPE_CAP_DECIMATION BIT(4) +#define MDP_PIPE_CAP_SW_PIX_EXT BIT(5) static inline bool pipe_supports_yuv(uint32_t pipe_caps) { diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 0339c5d82d37..b88ce514eb8e 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -21,11 +21,9 @@ static void msm_fb_output_poll_changed(struct drm_device *dev) { -#ifdef CONFIG_DRM_MSM_FBDEV struct msm_drm_private *priv = dev->dev_private; if (priv->fbdev) drm_fb_helper_hotplug_event(priv->fbdev); -#endif } static const struct drm_mode_config_funcs mode_config_funcs = { @@ -56,7 +54,7 @@ module_param(reglog, bool, 0600); #define reglog 0 #endif -#ifdef CONFIG_DRM_MSM_FBDEV +#ifdef CONFIG_DRM_FBDEV_EMULATION static bool fbdev = true; MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); module_param(fbdev, bool, 0600); @@ -423,7 +421,7 @@ static int msm_load(struct drm_device *dev, unsigned long flags) drm_mode_config_reset(dev); -#ifdef CONFIG_DRM_MSM_FBDEV +#ifdef CONFIG_DRM_FBDEV_EMULATION if (fbdev) priv->fbdev = msm_fbdev_init(dev); #endif @@ -491,11 +489,9 @@ static void msm_preclose(struct drm_device *dev, struct drm_file *file) static void msm_lastclose(struct drm_device *dev) { -#ifdef CONFIG_DRM_MSM_FBDEV struct msm_drm_private *priv = dev->dev_private; if (priv->fbdev) drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev); -#endif } static irqreturn_t msm_irq(int irq, void *arg) @@ -531,24 +527,24 @@ static void msm_irq_uninstall(struct drm_device *dev) kms->funcs->irq_uninstall(kms); } -static int msm_enable_vblank(struct drm_device *dev, int crtc_id) +static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; if (!kms) return -ENXIO; - DBG("dev=%p, crtc=%d", dev, crtc_id); - return vblank_ctrl_queue_work(priv, crtc_id, true); + DBG("dev=%p, crtc=%u", dev, pipe); + return vblank_ctrl_queue_work(priv, pipe, true); } -static void msm_disable_vblank(struct drm_device *dev, int crtc_id) +static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct msm_drm_private *priv = dev->dev_private; struct msm_kms *kms = priv->kms; if (!kms) return; - DBG("dev=%p, crtc=%d", dev, crtc_id); - vblank_ctrl_queue_work(priv, crtc_id, false); + DBG("dev=%p, crtc=%u", dev, pipe); + vblank_ctrl_queue_work(priv, pipe, false); } /* @@ -932,13 +928,13 @@ static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, } static const struct drm_ioctl_desc msm_ioctls[] = { - DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW), }; static const struct vm_operations_struct vm_ops = { @@ -978,7 +974,7 @@ static struct drm_driver msm_driver = { .irq_preinstall = msm_irq_preinstall, .irq_postinstall = msm_irq_postinstall, .irq_uninstall = msm_irq_uninstall, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = msm_enable_vblank, .disable_vblank = msm_disable_vblank, .gem_free_object = msm_gem_free_object, diff --git a/drivers/gpu/drm/msm/msm_fbdev.c b/drivers/gpu/drm/msm/msm_fbdev.c index f97a1964ef39..3f6ec077b51d 100644 --- a/drivers/gpu/drm/msm/msm_fbdev.c +++ b/drivers/gpu/drm/msm/msm_fbdev.c @@ -68,12 +68,7 @@ static int msm_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) if (drm_device_is_unplugged(dev)) return -ENODEV; - mutex_lock(&dev->struct_mutex); - ret = drm_gem_mmap_obj(drm_obj, drm_obj->size, vma); - - mutex_unlock(&dev->struct_mutex); - if (ret) { pr_err("%s:drm_gem_mmap_obj fail\n", __func__); return ret; diff --git a/drivers/gpu/drm/msm/msm_gem_prime.c b/drivers/gpu/drm/msm/msm_gem_prime.c index 831461bc98a5..121975b07cd4 100644 --- a/drivers/gpu/drm/msm/msm_gem_prime.c +++ b/drivers/gpu/drm/msm/msm_gem_prime.c @@ -45,9 +45,7 @@ int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { int ret; - mutex_lock(&obj->dev->struct_mutex); ret = drm_gem_mmap_obj(obj, obj->size, vma); - mutex_unlock(&obj->dev->struct_mutex); if (ret < 0) return ret; diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c index 8f70d9248ac5..6b02ada6579a 100644 --- a/drivers/gpu/drm/msm/msm_gpu.c +++ b/drivers/gpu/drm/msm/msm_gpu.c @@ -651,6 +651,14 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, if (iommu) { dev_info(drm->dev, "%s: using IOMMU\n", name); gpu->mmu = msm_iommu_new(&pdev->dev, iommu); + if (IS_ERR(gpu->mmu)) { + ret = PTR_ERR(gpu->mmu); + dev_err(drm->dev, "failed to init iommu: %d\n", ret); + gpu->mmu = NULL; + iommu_domain_free(iommu); + goto fail; + } + } else { dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); } diff --git a/drivers/gpu/drm/nouveau/include/nvif/os.h b/drivers/gpu/drm/nouveau/include/nvif/os.h index 3accc99d8e0b..9fcab67c8557 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/os.h +++ b/drivers/gpu/drm/nouveau/include/nvif/os.h @@ -27,6 +27,7 @@ #include <linux/agp_backend.h> #include <linux/reset.h> #include <linux/iommu.h> +#include <linux/of_device.h> #include <asm/unaligned.h> diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h index 5aa2480da25f..16641cec18a2 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h @@ -4,6 +4,7 @@ #include <core/mm.h> struct nvkm_device_tegra { + const struct nvkm_device_tegra_func *func; struct nvkm_device device; struct platform_device *pdev; int irq; @@ -28,7 +29,17 @@ struct nvkm_device_tegra { int gpu_speedo; }; -int nvkm_device_tegra_new(struct platform_device *, +struct nvkm_device_tegra_func { + /* + * If an IOMMU is used, indicates which address bit will trigger a + * IOMMU translation when set (when this bit is not set, IOMMU is + * bypassed). A value of 0 means an IOMMU is never used. + */ + u8 iommu_bit; +}; + +int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *, + struct platform_device *, const char *cfg, const char *dbg, bool detect, bool mmio, u64 subdev_mask, struct nvkm_device **); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h index 33be260ddd38..a47d46dda704 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -15,6 +15,7 @@ enum dcb_gpio_func_name { DCB_GPIO_VID5 = 0x74, DCB_GPIO_VID6 = 0x75, DCB_GPIO_VID7 = 0x76, + DCB_GPIO_VID_PWM = 0x81, }; #define DCB_GPIO_LOG_DIR 0x02 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h index d606875c125a..3a643df6de04 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/pmu.h @@ -4,8 +4,6 @@ struct nvbios_pmuT { }; u32 nvbios_pmuTe(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); -u32 nvbios_pmuTp(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_pmuT *); struct nvbios_pmuE { u8 type; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h index 3a9abd38aca8..dca6c060a24f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/ramcfg.h @@ -39,6 +39,7 @@ struct nvbios_ramcfg { unsigned ramcfg_timing; unsigned ramcfg_DLLoff; unsigned ramcfg_RON; + unsigned ramcfg_FBVDDQ; union { struct { unsigned ramcfg_00_03_01:1; @@ -78,7 +79,6 @@ struct nvbios_ramcfg { unsigned ramcfg_11_01_04:1; unsigned ramcfg_11_01_08:1; unsigned ramcfg_11_01_10:1; - unsigned ramcfg_11_01_20:1; unsigned ramcfg_11_01_40:1; unsigned ramcfg_11_01_80:1; unsigned ramcfg_11_02_03:2; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h index eb2de4b85bbd..b0df610cec2b 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/volt.h @@ -1,11 +1,24 @@ #ifndef __NVBIOS_VOLT_H__ #define __NVBIOS_VOLT_H__ + +enum nvbios_volt_type { + NVBIOS_VOLT_GPIO = 0, + NVBIOS_VOLT_PWM, +}; + struct nvbios_volt { - u8 vidmask; + enum nvbios_volt_type type; u32 min; u32 max; u32 base; + + /* GPIO mode */ + u8 vidmask; s16 step; + + /* PWM mode */ + u32 pwm_freq; + u32 pwm_range; }; u16 nvbios_volt_table(struct nvkm_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h index 6a04d9c07944..33a057c334f2 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h @@ -14,6 +14,7 @@ int nvkm_hwsq_fini(struct nvkm_hwsq **, bool exec); void nvkm_hwsq_wr32(struct nvkm_hwsq *, u32 addr, u32 data); void nvkm_hwsq_setf(struct nvkm_hwsq *, u8 flag, int data); void nvkm_hwsq_wait(struct nvkm_hwsq *, u8 flag, u8 data); +void nvkm_hwsq_wait_vblank(struct nvkm_hwsq *); void nvkm_hwsq_nsec(struct nvkm_hwsq *, u32 nsec); int nv04_bus_new(struct nvkm_device *, int, struct nvkm_bus **); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h index 9d512cd5a0a7..c4dcd2680fe1 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ibus.h @@ -3,6 +3,7 @@ #include <core/subdev.h> int gf100_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); +int gf117_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); int gk104_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); int gk20a_ibus_new(struct nvkm_device *, int, struct nvkm_subdev **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h index c773b5e958b4..3d4dbbf9aab3 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h @@ -30,7 +30,11 @@ void nvkm_ltc_tags_clear(struct nvkm_ltc *, u32 first, u32 count); int nvkm_ltc_zbc_color_get(struct nvkm_ltc *, int index, const u32[4]); int nvkm_ltc_zbc_depth_get(struct nvkm_ltc *, int index, const u32); +void nvkm_ltc_invalidate(struct nvkm_ltc *); +void nvkm_ltc_flush(struct nvkm_ltc *); + int gf100_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gk104_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); +int gk20a_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); int gm107_ltc_new(struct nvkm_device *, int, struct nvkm_ltc **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h index 5b3c054f3b55..fee0a97c44c5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h @@ -24,11 +24,14 @@ struct nvkm_pci { u32 nvkm_pci_rd32(struct nvkm_pci *, u16 addr); void nvkm_pci_wr08(struct nvkm_pci *, u16 addr, u8 data); void nvkm_pci_wr32(struct nvkm_pci *, u16 addr, u32 data); +u32 nvkm_pci_mask(struct nvkm_pci *, u16 addr, u32 mask, u32 value); void nvkm_pci_rom_shadow(struct nvkm_pci *, bool shadow); int nv04_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int nv40_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **); -int nv50_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **); +int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **); int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **); #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h index 62ed0880b0e1..82d3e28918fd 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/timer.h @@ -59,6 +59,16 @@ void nvkm_timer_alarm_cancel(struct nvkm_timer *, struct nvkm_alarm *); #define nvkm_usec(d,u,cond...) nvkm_nsec((d), (u) * 1000, ##cond) #define nvkm_msec(d,m,cond...) nvkm_usec((d), (m) * 1000, ##cond) +#define nvkm_wait_nsec(d,n,addr,mask,data) \ + nvkm_nsec(d, n, \ + if ((nvkm_rd32(d, (addr)) & (mask)) == (data)) \ + break; \ + ) +#define nvkm_wait_usec(d,u,addr,mask,data) \ + nvkm_wait_nsec((d), (u) * 1000, (addr), (mask), (data)) +#define nvkm_wait_msec(d,m,addr,mask,data) \ + nvkm_wait_usec((d), (m) * 1000, (addr), (mask), (data)) + int nv04_timer_new(struct nvkm_device *, int, struct nvkm_timer **); int nv40_timer_new(struct nvkm_device *, int, struct nvkm_timer **); int nv41_timer_new(struct nvkm_device *, int, struct nvkm_timer **); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h index 5c8a3f1196de..b458d046dba7 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h @@ -18,5 +18,6 @@ int nvkm_volt_get(struct nvkm_volt *); int nvkm_volt_set_id(struct nvkm_volt *, u8 id, int condition); int nv40_volt_new(struct nvkm_device *, int, struct nvkm_volt **); +int gk104_volt_new(struct nvkm_device *, int, struct nvkm_volt **); int gk20a_volt_new(struct nvkm_device *, int, struct nvkm_volt **); #endif diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c index d336c2247d6a..7f50cf5f929e 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.c +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c @@ -25,6 +25,7 @@ #include <nvif/driver.h> #include <nvif/ioctl.h> #include <nvif/class.h> +#include <nvif/unpack.h> #include "nouveau_drm.h" #include "nouveau_dma.h" @@ -32,11 +33,10 @@ #include "nouveau_chan.h" #include "nouveau_abi16.h" -struct nouveau_abi16 * -nouveau_abi16_get(struct drm_file *file_priv, struct drm_device *dev) +static struct nouveau_abi16 * +nouveau_abi16(struct drm_file *file_priv) { struct nouveau_cli *cli = nouveau_cli(file_priv); - mutex_lock(&cli->mutex); if (!cli->abi16) { struct nouveau_abi16 *abi16; cli->abi16 = abi16 = kzalloc(sizeof(*abi16), GFP_KERNEL); @@ -51,8 +51,7 @@ nouveau_abi16_get(struct drm_file *file_priv, struct drm_device *dev) * device (ie. the one that belongs to the fd it * opened) */ - if (nvif_device_init(&cli->base.object, - NOUVEAU_ABI16_DEVICE, NV_DEVICE, + if (nvif_device_init(&cli->base.object, 0, NV_DEVICE, &args, sizeof(args), &abi16->device) == 0) return cli->abi16; @@ -60,12 +59,21 @@ nouveau_abi16_get(struct drm_file *file_priv, struct drm_device *dev) kfree(cli->abi16); cli->abi16 = NULL; } - - mutex_unlock(&cli->mutex); } return cli->abi16; } +struct nouveau_abi16 * +nouveau_abi16_get(struct drm_file *file_priv) +{ + struct nouveau_cli *cli = nouveau_cli(file_priv); + mutex_lock(&cli->mutex); + if (nouveau_abi16(file_priv)) + return cli->abi16; + mutex_unlock(&cli->mutex); + return NULL; +} + int nouveau_abi16_put(struct nouveau_abi16 *abi16, int ret) { @@ -133,7 +141,6 @@ nouveau_abi16_chan_fini(struct nouveau_abi16 *abi16, /* destroy channel object, all children will be killed too */ if (chan->chan) { - abi16->handles &= ~(1ULL << (chan->chan->user.handle & 0xffff)); nouveau_channel_idle(chan->chan); nouveau_channel_del(&chan->chan); } @@ -238,7 +245,7 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) struct drm_nouveau_channel_alloc *init = data; struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); + struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv); struct nouveau_abi16_chan *chan; struct nvif_device *device; int ret; @@ -268,26 +275,21 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS) return nouveau_abi16_put(abi16, -EINVAL); /* allocate "abi16 channel" data and make up a handle for it */ - init->channel = __ffs64(~abi16->handles); - if (~abi16->handles == 0) - return nouveau_abi16_put(abi16, -ENOSPC); - chan = kzalloc(sizeof(*chan), GFP_KERNEL); if (!chan) return nouveau_abi16_put(abi16, -ENOMEM); INIT_LIST_HEAD(&chan->notifiers); list_add(&chan->head, &abi16->channels); - abi16->handles |= (1ULL << init->channel); /* create channel object and initialise dma and fence management */ - ret = nouveau_channel_new(drm, device, - NOUVEAU_ABI16_CHAN(init->channel), - init->fb_ctxdma_handle, + ret = nouveau_channel_new(drm, device, init->fb_ctxdma_handle, init->tt_ctxdma_handle, &chan->chan); if (ret) goto done; + init->channel = chan->chan->chid; + if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) init->pushbuf_domains = NOUVEAU_GEM_DOMAIN_VRAM | NOUVEAU_GEM_DOMAIN_GART; @@ -338,7 +340,7 @@ nouveau_abi16_chan(struct nouveau_abi16 *abi16, int channel) struct nouveau_abi16_chan *chan; list_for_each_entry(chan, &abi16->channels, head) { - if (chan->chan->user.handle == NOUVEAU_ABI16_CHAN(channel)) + if (chan->chan->chid == channel) return chan; } @@ -346,10 +348,48 @@ nouveau_abi16_chan(struct nouveau_abi16 *abi16, int channel) } int +nouveau_abi16_usif(struct drm_file *file_priv, void *data, u32 size) +{ + union { + struct nvif_ioctl_v0 v0; + } *args = data; + struct nouveau_abi16_chan *chan; + struct nouveau_abi16 *abi16; + int ret; + + if (nvif_unpack(args->v0, 0, 0, true)) { + switch (args->v0.type) { + case NVIF_IOCTL_V0_NEW: + case NVIF_IOCTL_V0_MTHD: + case NVIF_IOCTL_V0_SCLASS: + break; + default: + return -EACCES; + } + } else + return ret; + + if (!(abi16 = nouveau_abi16(file_priv))) + return -ENOMEM; + + if (args->v0.token != ~0ULL) { + if (!(chan = nouveau_abi16_chan(abi16, args->v0.token))) + return -EINVAL; + args->v0.object = nvif_handle(&chan->chan->user); + args->v0.owner = NVIF_IOCTL_V0_OWNER_ANY; + return 0; + } + + args->v0.object = nvif_handle(&abi16->device.object); + args->v0.owner = NVIF_IOCTL_V0_OWNER_ANY; + return 0; +} + +int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS) { struct drm_nouveau_channel_free *req = data; - struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); + struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv); struct nouveau_abi16_chan *chan; if (unlikely(!abi16)) @@ -366,7 +406,7 @@ int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS) { struct drm_nouveau_grobj_alloc *init = data; - struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); + struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv); struct nouveau_abi16_chan *chan; struct nouveau_abi16_ntfy *ntfy; struct nvif_client *client; @@ -459,7 +499,7 @@ nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS) { struct drm_nouveau_notifierobj_alloc *info = data; struct nouveau_drm *drm = nouveau_drm(dev); - struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); + struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv); struct nouveau_abi16_chan *chan; struct nouveau_abi16_ntfy *ntfy; struct nvif_device *device = &abi16->device; @@ -531,7 +571,7 @@ int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS) { struct drm_nouveau_gpuobj_free *fini = data; - struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); + struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv); struct nouveau_abi16_chan *chan; struct nouveau_abi16_ntfy *ntfy; int ret = -ENOENT; diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.h b/drivers/gpu/drm/nouveau/nouveau_abi16.h index 6584557afa40..841cc556fad8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_abi16.h +++ b/drivers/gpu/drm/nouveau/nouveau_abi16.h @@ -33,11 +33,11 @@ struct nouveau_abi16 { u64 handles; }; -struct nouveau_drm; -struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *, struct drm_device *); +struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *); int nouveau_abi16_put(struct nouveau_abi16 *, int); void nouveau_abi16_fini(struct nouveau_abi16 *); s32 nouveau_abi16_swclass(struct nouveau_drm *); +int nouveau_abi16_usif(struct drm_file *, void *data, u32 size); #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c index df2d9818aba3..8b8332e46f24 100644 --- a/drivers/gpu/drm/nouveau/nouveau_acpi.c +++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c @@ -206,7 +206,7 @@ static int nouveau_dsm_get_client_id(struct pci_dev *pdev) return VGA_SWITCHEROO_DIS; } -static struct vga_switcheroo_handler nouveau_dsm_handler = { +static const struct vga_switcheroo_handler nouveau_dsm_handler = { .switchto = nouveau_dsm_switchto, .power_state = nouveau_dsm_power_state, .get_client_id = nouveau_dsm_get_client_id, diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c index 15057b39491c..78f520d05de9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bo.c +++ b/drivers/gpu/drm/nouveau/nouveau_bo.c @@ -574,7 +574,7 @@ static struct ttm_tt * nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, uint32_t page_flags, struct page *dummy_read) { -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) struct nouveau_drm *drm = nouveau_bdev(bdev); if (drm->agp.bridge) { @@ -1366,7 +1366,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) /* System memory */ return 0; case TTM_PL_TT: -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (drm->agp.bridge) { mem->bus.offset = mem->start << PAGE_SHIFT; mem->bus.base = drm->agp.base; @@ -1496,7 +1496,7 @@ nouveau_ttm_tt_populate(struct ttm_tt *ttm) ttm->caching_state == tt_uncached) return ttm_dma_populate(ttm_dma, dev->dev); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (drm->agp.bridge) { return ttm_agp_tt_populate(ttm); } @@ -1563,7 +1563,7 @@ nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) return; } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (drm->agp.bridge) { ttm_agp_tt_unpopulate(ttm); return; diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.c b/drivers/gpu/drm/nouveau/nouveau_chan.c index ff5e59db49db..1860f389f21f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.c +++ b/drivers/gpu/drm/nouveau/nouveau_chan.c @@ -55,10 +55,8 @@ nouveau_channel_idle(struct nouveau_channel *chan) } if (ret) { - NV_PRINTK(err, cli, "failed to idle channel " - "0x%08x [%s]\n", - chan->user.handle, - nvxx_client(&cli->base)->name); + NV_PRINTK(err, cli, "failed to idle channel %d [%s]\n", + chan->chid, nvxx_client(&cli->base)->name); return ret; } } @@ -89,7 +87,7 @@ nouveau_channel_del(struct nouveau_channel **pchan) static int nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, - u32 handle, u32 size, struct nouveau_channel **pchan) + u32 size, struct nouveau_channel **pchan) { struct nouveau_cli *cli = (void *)device->object.client; struct nvkm_mmu *mmu = nvxx_mmu(device); @@ -174,8 +172,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, } } - ret = nvif_object_init(&device->object, NVDRM_PUSH | - (handle & 0xffff), NV_DMA_FROM_MEMORY, + ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, &args, sizeof(args), &chan->push.ctxdma); if (ret) { nouveau_channel_del(pchan); @@ -187,7 +184,7 @@ nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device, static int nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, - u32 handle, u32 engine, struct nouveau_channel **pchan) + u32 engine, struct nouveau_channel **pchan) { static const u16 oclasses[] = { MAXWELL_CHANNEL_GPFIFO_A, KEPLER_CHANNEL_GPFIFO_A, @@ -206,7 +203,7 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, int ret; /* allocate dma push buffer */ - ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan); + ret = nouveau_channel_prep(drm, device, 0x12000, &chan); *pchan = chan; if (ret) return ret; @@ -236,7 +233,7 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, size = sizeof(args.nv50); } - ret = nvif_object_init(&device->object, handle, *oclass++, + ret = nvif_object_init(&device->object, 0, *oclass++, &args, size, &chan->user); if (ret == 0) { if (chan->user.oclass >= KEPLER_CHANNEL_GPFIFO_A) @@ -256,7 +253,7 @@ nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device, static int nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, - u32 handle, struct nouveau_channel **pchan) + struct nouveau_channel **pchan) { static const u16 oclasses[] = { NV40_CHANNEL_DMA, NV17_CHANNEL_DMA, @@ -269,7 +266,7 @@ nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, int ret; /* allocate dma push buffer */ - ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan); + ret = nouveau_channel_prep(drm, device, 0x10000, &chan); *pchan = chan; if (ret) return ret; @@ -280,7 +277,7 @@ nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device, args.offset = chan->push.vma.offset; do { - ret = nvif_object_init(&device->object, handle, *oclass++, + ret = nvif_object_init(&device->object, 0, *oclass++, &args, sizeof(args), &chan->user); if (ret == 0) { chan->chid = args.chid; @@ -401,8 +398,7 @@ nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) int nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, - u32 handle, u32 arg0, u32 arg1, - struct nouveau_channel **pchan) + u32 arg0, u32 arg1, struct nouveau_channel **pchan) { struct nouveau_cli *cli = (void *)device->object.client; bool super; @@ -412,10 +408,10 @@ nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device, super = cli->base.super; cli->base.super = true; - ret = nouveau_channel_ind(drm, device, handle, arg0, pchan); + ret = nouveau_channel_ind(drm, device, arg0, pchan); if (ret) { NV_PRINTK(dbg, cli, "ib channel create, %d\n", ret); - ret = nouveau_channel_dma(drm, device, handle, pchan); + ret = nouveau_channel_dma(drm, device, pchan); if (ret) { NV_PRINTK(dbg, cli, "dma channel create, %d\n", ret); goto done; diff --git a/drivers/gpu/drm/nouveau/nouveau_chan.h b/drivers/gpu/drm/nouveau/nouveau_chan.h index 2ed32414cb69..48062c94f36d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_chan.h +++ b/drivers/gpu/drm/nouveau/nouveau_chan.h @@ -42,8 +42,7 @@ struct nouveau_channel { int nouveau_channel_new(struct nouveau_drm *, struct nvif_device *, - u32 handle, u32 arg0, u32 arg1, - struct nouveau_channel **); + u32 arg0, u32 arg1, struct nouveau_channel **); void nouveau_channel_del(struct nouveau_channel **); int nouveau_channel_idle(struct nouveau_channel *); diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index a82c3cbe3127..db6bc6760545 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -51,12 +51,12 @@ nouveau_display_vblank_handler(struct nvif_notify *notify) } int -nouveau_display_vblank_enable(struct drm_device *dev, int head) +nouveau_display_vblank_enable(struct drm_device *dev, unsigned int pipe) { struct drm_crtc *crtc; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); - if (nv_crtc->index == head) { + if (nv_crtc->index == pipe) { nvif_notify_get(&nv_crtc->vblank); return 0; } @@ -65,12 +65,12 @@ nouveau_display_vblank_enable(struct drm_device *dev, int head) } void -nouveau_display_vblank_disable(struct drm_device *dev, int head) +nouveau_display_vblank_disable(struct drm_device *dev, unsigned int pipe) { struct drm_crtc *crtc; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); - if (nv_crtc->index == head) { + if (nv_crtc->index == pipe) { nvif_notify_put(&nv_crtc->vblank); return; } @@ -132,14 +132,15 @@ nouveau_display_scanoutpos_head(struct drm_crtc *crtc, int *vpos, int *hpos, } int -nouveau_display_scanoutpos(struct drm_device *dev, int head, unsigned int flags, - int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, +nouveau_display_scanoutpos(struct drm_device *dev, unsigned int pipe, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode) { struct drm_crtc *crtc; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - if (nouveau_crtc(crtc)->index == head) { + if (nouveau_crtc(crtc)->index == pipe) { return nouveau_display_scanoutpos_head(crtc, vpos, hpos, stime, etime); } @@ -149,15 +150,15 @@ nouveau_display_scanoutpos(struct drm_device *dev, int head, unsigned int flags, } int -nouveau_display_vblstamp(struct drm_device *dev, int head, int *max_error, - struct timeval *time, unsigned flags) +nouveau_display_vblstamp(struct drm_device *dev, unsigned int pipe, + int *max_error, struct timeval *time, unsigned flags) { struct drm_crtc *crtc; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - if (nouveau_crtc(crtc)->index == head) { + if (nouveau_crtc(crtc)->index == pipe) { return drm_calc_vbltimestamp_from_scanoutpos(dev, - head, max_error, time, flags, + pipe, max_error, time, flags, &crtc->hwmode); } } @@ -471,9 +472,13 @@ nouveau_display_create(struct drm_device *dev) if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) { dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; - } else { + } else + if (drm->device.info.family < NV_DEVICE_INFO_V0_FERMI) { dev->mode_config.max_width = 8192; dev->mode_config.max_height = 8192; + } else { + dev->mode_config.max_width = 16384; + dev->mode_config.max_height = 16384; } dev->mode_config.preferred_depth = 24; @@ -504,9 +509,8 @@ nouveau_display_create(struct drm_device *dev) int i; for (i = 0, ret = -ENODEV; ret && i < ARRAY_SIZE(oclass); i++) { - ret = nvif_object_init(&drm->device.object, - NVDRM_DISPLAY, oclass[i], - NULL, 0, &disp->disp); + ret = nvif_object_init(&drm->device.object, 0, + oclass[i], NULL, 0, &disp->disp); } if (ret == 0) { diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 4182d21538c5..856abe0f070d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -65,12 +65,12 @@ int nouveau_display_init(struct drm_device *dev); void nouveau_display_fini(struct drm_device *dev); int nouveau_display_suspend(struct drm_device *dev, bool runtime); void nouveau_display_resume(struct drm_device *dev, bool runtime); -int nouveau_display_vblank_enable(struct drm_device *, int); -void nouveau_display_vblank_disable(struct drm_device *, int); -int nouveau_display_scanoutpos(struct drm_device *, int, unsigned int, - int *, int *, ktime_t *, ktime_t *, - const struct drm_display_mode *); -int nouveau_display_vblstamp(struct drm_device *, int, int *, +int nouveau_display_vblank_enable(struct drm_device *, unsigned int); +void nouveau_display_vblank_disable(struct drm_device *, unsigned int); +int nouveau_display_scanoutpos(struct drm_device *, unsigned int, + unsigned int, int *, int *, ktime_t *, + ktime_t *, const struct drm_display_mode *); +int nouveau_display_vblstamp(struct drm_device *, unsigned int, int *, struct timeval *, unsigned); int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index ccefb645fd55..1d3ee5179ab8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -208,7 +208,7 @@ nouveau_accel_init(struct nouveau_drm *drm) } if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) { - ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, + ret = nouveau_channel_new(drm, &drm->device, KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0| KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1, 0, &drm->cechan); @@ -221,7 +221,7 @@ nouveau_accel_init(struct nouveau_drm *drm) if (device->info.chipset >= 0xa3 && device->info.chipset != 0xaa && device->info.chipset != 0xac) { - ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1, + ret = nouveau_channel_new(drm, &drm->device, NvDmaFB, NvDmaTT, &drm->cechan); if (ret) NV_ERROR(drm, "failed to create ce channel, %d\n", ret); @@ -233,8 +233,7 @@ nouveau_accel_init(struct nouveau_drm *drm) arg1 = NvDmaTT; } - ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN, arg0, arg1, - &drm->channel); + ret = nouveau_channel_new(drm, &drm->device, arg0, arg1, &drm->channel); if (ret) { NV_ERROR(drm, "failed to create kernel channel, %d\n", ret); nouveau_accel_fini(drm); @@ -403,8 +402,7 @@ nouveau_drm_load(struct drm_device *dev, unsigned long flags) nouveau_get_hdmi_dev(drm); - ret = nvif_device_init(&drm->client.base.object, - NVDRM_DEVICE, NV_DEVICE, + ret = nvif_device_init(&drm->client.base.object, 0, NV_DEVICE, &(struct nv_device_v0) { .device = ~0, }, sizeof(struct nv_device_v0), @@ -862,18 +860,18 @@ nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv) static const struct drm_ioctl_desc nouveau_ioctls[] = { - DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_AUTH|DRM_RENDER_ALLOW), }; long @@ -934,7 +932,7 @@ driver_stub = { .debugfs_cleanup = nouveau_debugfs_takedown, #endif - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = nouveau_display_vblank_enable, .disable_vblank = nouveau_display_vblank_disable, .get_scanout_position = nouveau_display_scanoutpos, @@ -1030,13 +1028,14 @@ nouveau_drm_pci_driver = { }; struct drm_device * -nouveau_platform_device_create(struct platform_device *pdev, +nouveau_platform_device_create(const struct nvkm_device_tegra_func *func, + struct platform_device *pdev, struct nvkm_device **pdevice) { struct drm_device *drm; int err; - err = nvkm_device_tegra_new(pdev, nouveau_config, nouveau_debug, + err = nvkm_device_tegra_new(func, pdev, nouveau_config, nouveau_debug, true, true, ~0ULL, pdevice); if (err) goto err_free; diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.h b/drivers/gpu/drm/nouveau/nouveau_drm.h index 3c902c24a8dd..3050042e6c6d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.h +++ b/drivers/gpu/drm/nouveau/nouveau_drm.h @@ -10,7 +10,7 @@ #define DRIVER_MAJOR 1 #define DRIVER_MINOR 3 -#define DRIVER_PATCHLEVEL 0 +#define DRIVER_PATCHLEVEL 1 /* * 1.1.1: @@ -33,6 +33,8 @@ * 1.3.0: * - NVIF ABI modified, safe because only (current) users are test * programs that get directly linked with NVKM. + * 1.3.1: + * - implemented limited ABI16/NVIF interop */ #include <nvif/client.h> @@ -74,11 +76,6 @@ enum nouveau_drm_notify_route { }; enum nouveau_drm_handle { - NVDRM_CLIENT = 0xffffffff, - NVDRM_DEVICE = 0xdddddddd, - NVDRM_CONTROL = 0xdddddddc, - NVDRM_DISPLAY = 0xd1500000, - NVDRM_PUSH = 0xbbbb0000, /* |= client chid */ NVDRM_CHAN = 0xcccc0000, /* |= client chid */ NVDRM_NVSW = 0x55550000, }; @@ -183,8 +180,11 @@ nouveau_drm(struct drm_device *dev) int nouveau_pmops_suspend(struct device *); int nouveau_pmops_resume(struct device *); +#include <nvkm/core/tegra.h> + struct drm_device * -nouveau_platform_device_create(struct platform_device *, struct nvkm_device **); +nouveau_platform_device_create(const struct nvkm_device_tegra_func *, + struct platform_device *, struct nvkm_device **); void nouveau_drm_device_remove(struct drm_device *dev); #define NV_PRINTK(l,c,f,a...) do { \ diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 2791701685dc..59f27e774acb 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -178,8 +178,30 @@ nouveau_fbcon_sync(struct fb_info *info) return 0; } +static int +nouveau_fbcon_open(struct fb_info *info, int user) +{ + struct nouveau_fbdev *fbcon = info->par; + struct nouveau_drm *drm = nouveau_drm(fbcon->dev); + int ret = pm_runtime_get_sync(drm->dev->dev); + if (ret < 0 && ret != -EACCES) + return ret; + return 0; +} + +static int +nouveau_fbcon_release(struct fb_info *info, int user) +{ + struct nouveau_fbdev *fbcon = info->par; + struct nouveau_drm *drm = nouveau_drm(fbcon->dev); + pm_runtime_put(drm->dev->dev); + return 0; +} + static struct fb_ops nouveau_fbcon_ops = { .owner = THIS_MODULE, + .fb_open = nouveau_fbcon_open, + .fb_release = nouveau_fbcon_release, .fb_check_var = drm_fb_helper_check_var, .fb_set_par = drm_fb_helper_set_par, .fb_fillrect = nouveau_fbcon_fillrect, @@ -195,6 +217,8 @@ static struct fb_ops nouveau_fbcon_ops = { static struct fb_ops nouveau_fbcon_sw_ops = { .owner = THIS_MODULE, + .fb_open = nouveau_fbcon_open, + .fb_release = nouveau_fbcon_release, .fb_check_var = drm_fb_helper_check_var, .fb_set_par = drm_fb_helper_set_par, .fb_fillrect = drm_fb_helper_cfb_fillrect, diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c index 2c9981512d27..a0865c49ec83 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.c +++ b/drivers/gpu/drm/nouveau/nouveau_gem.c @@ -84,8 +84,10 @@ nouveau_gem_object_open(struct drm_gem_object *gem, struct drm_file *file_priv) } ret = pm_runtime_get_sync(dev); - if (ret < 0 && ret != -EACCES) + if (ret < 0 && ret != -EACCES) { + kfree(vma); goto out; + } ret = nouveau_bo_vma_add(nvbo, cli->vm, vma); if (ret) @@ -227,11 +229,12 @@ nouveau_gem_info(struct drm_file *file_priv, struct drm_gem_object *gem, struct nouveau_bo *nvbo = nouveau_gem_object(gem); struct nvkm_vma *vma; - if (nvbo->bo.mem.mem_type == TTM_PL_TT) + if (is_power_of_2(nvbo->valid_domains)) + rep->domain = nvbo->valid_domains; + else if (nvbo->bo.mem.mem_type == TTM_PL_TT) rep->domain = NOUVEAU_GEM_DOMAIN_GART; else rep->domain = NOUVEAU_GEM_DOMAIN_VRAM; - rep->offset = nvbo->bo.offset; if (cli->vm) { vma = nouveau_bo_vma_find(nvbo, cli->vm); @@ -665,7 +668,7 @@ int nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, struct drm_file *file_priv) { - struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv, dev); + struct nouveau_abi16 *abi16 = nouveau_abi16_get(file_priv); struct nouveau_cli *cli = nouveau_cli(file_priv); struct nouveau_abi16_chan *temp; struct nouveau_drm *drm = nouveau_drm(dev); @@ -681,7 +684,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, return -ENOMEM; list_for_each_entry(temp, &abi16->channels, head) { - if (temp->chan->user.handle == (NVDRM_CHAN | req->channel)) { + if (temp->chan->chid == req->channel) { chan = temp->chan; break; } diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c index 3eb665453165..60e32c4e4e49 100644 --- a/drivers/gpu/drm/nouveau/nouveau_platform.c +++ b/drivers/gpu/drm/nouveau/nouveau_platform.c @@ -23,11 +23,14 @@ static int nouveau_platform_probe(struct platform_device *pdev) { + const struct nvkm_device_tegra_func *func; struct nvkm_device *device; struct drm_device *drm; int ret; - drm = nouveau_platform_device_create(pdev, &device); + func = of_device_get_match_data(&pdev->dev); + + drm = nouveau_platform_device_create(func, pdev, &device); if (IS_ERR(drm)) return PTR_ERR(drm); @@ -48,9 +51,19 @@ static int nouveau_platform_remove(struct platform_device *pdev) } #if IS_ENABLED(CONFIG_OF) +static const struct nvkm_device_tegra_func gk20a_platform_data = { + .iommu_bit = 34, +}; + static const struct of_device_id nouveau_platform_match[] = { - { .compatible = "nvidia,gk20a" }, - { .compatible = "nvidia,gm20b" }, + { + .compatible = "nvidia,gk20a", + .data = &gk20a_platform_data, + }, + { + .compatible = "nvidia,gm20b", + .data = &gk20a_platform_data, + }, { } }; diff --git a/drivers/gpu/drm/nouveau/nouveau_sysfs.c b/drivers/gpu/drm/nouveau/nouveau_sysfs.c index d12a5faee047..5dac3546c1b8 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sysfs.c +++ b/drivers/gpu/drm/nouveau/nouveau_sysfs.c @@ -188,9 +188,8 @@ nouveau_sysfs_init(struct drm_device *dev) if (!sysfs) return -ENOMEM; - ret = nvif_object_init(&device->object, NVDRM_CONTROL, - NVIF_IOCTL_NEW_V0_CONTROL, NULL, 0, - &sysfs->ctrl); + ret = nvif_object_init(&device->object, 0, NVIF_IOCTL_NEW_V0_CONTROL, + NULL, 0, &sysfs->ctrl); if (ret == 0) device_create_file(nvxx_device(device)->dev, &dev_attr_pstate); diff --git a/drivers/gpu/drm/nouveau/nouveau_ttm.c b/drivers/gpu/drm/nouveau/nouveau_ttm.c index 3f0fb55cb473..3f713c1b5dc1 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ttm.c +++ b/drivers/gpu/drm/nouveau/nouveau_ttm.c @@ -29,6 +29,9 @@ #include "nouveau_gem.h" #include "drm_legacy.h" + +#include <core/tegra.h> + static int nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize) { @@ -338,7 +341,7 @@ nouveau_ttm_init(struct nouveau_drm *drm) struct nvkm_device *device = nvxx_device(&drm->device); struct nvkm_pci *pci = device->pci; struct drm_device *dev = drm->dev; - u32 bits; + u8 bits; int ret; if (pci && pci->agp.bridge) { @@ -351,20 +354,28 @@ nouveau_ttm_init(struct nouveau_drm *drm) bits = nvxx_mmu(&drm->device)->dma_bits; if (nvxx_device(&drm->device)->func->pci) { if (drm->agp.bridge || - !pci_dma_supported(dev->pdev, DMA_BIT_MASK(bits))) + !dma_supported(dev->dev, DMA_BIT_MASK(bits))) bits = 32; + } else if (device->func->tegra) { + struct nvkm_device_tegra *tegra = device->func->tegra(device); - ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(bits)); - if (ret) - return ret; + /* + * If the platform can use a IOMMU, then the addressable DMA + * space is constrained by the IOMMU bit + */ + if (tegra->func->iommu_bit) + bits = min(bits, tegra->func->iommu_bit); - ret = pci_set_consistent_dma_mask(dev->pdev, - DMA_BIT_MASK(bits)); - if (ret) - pci_set_consistent_dma_mask(dev->pdev, - DMA_BIT_MASK(32)); } + ret = dma_set_mask(dev->dev, DMA_BIT_MASK(bits)); + if (ret) + return ret; + + ret = dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(bits)); + if (ret) + dma_set_coherent_mask(dev->dev, DMA_BIT_MASK(32)); + ret = nouveau_ttm_global_init(drm); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nouveau_usif.c b/drivers/gpu/drm/nouveau/nouveau_usif.c index cb1182d7e80e..89dc4ce63490 100644 --- a/drivers/gpu/drm/nouveau/nouveau_usif.c +++ b/drivers/gpu/drm/nouveau/nouveau_usif.c @@ -24,6 +24,7 @@ #include "nouveau_drm.h" #include "nouveau_usif.h" +#include "nouveau_abi16.h" #include <nvif/notify.h> #include <nvif/unpack.h> @@ -316,11 +317,21 @@ usif_ioctl(struct drm_file *filp, void __user *user, u32 argc) } else goto done; + /* USIF slightly abuses some return-only ioctl members in order + * to provide interoperability with the older ABI16 objects + */ mutex_lock(&cli->mutex); + if (argv->v0.route) { + if (ret = -EINVAL, argv->v0.route == 0xff) + ret = nouveau_abi16_usif(filp, argv, argc); + if (ret) { + mutex_unlock(&cli->mutex); + goto done; + } + } + switch (argv->v0.type) { case NVIF_IOCTL_V0_NEW: - /* ... except if we're creating children */ - argv->v0.owner = NVIF_IOCTL_V0_OWNER_ANY; ret = usif_object_new(filp, data, size, argv, argc); break; case NVIF_IOCTL_V0_NTFY_NEW: diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index 4ae87aed4505..c053c50b346a 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c @@ -68,7 +68,6 @@ nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, const s32 *oclass, u8 head, void *data, u32 size, struct nv50_chan *chan) { - const u32 handle = (oclass[0] << 16) | head; struct nvif_sclass *sclass; int ret, i, n; @@ -81,7 +80,7 @@ nv50_chan_create(struct nvif_device *device, struct nvif_object *disp, while (oclass[0]) { for (i = 0; i < n; i++) { if (sclass[i].oclass == oclass[0]) { - ret = nvif_object_init(disp, handle, oclass[0], + ret = nvif_object_init(disp, 0, oclass[0], data, size, &chan->user); if (ret == 0) nvif_object_map(&chan->user); @@ -231,8 +230,8 @@ nv50_dmac_create(struct nvif_device *device, struct nvif_object *disp, if (!dmac->ptr) return -ENOMEM; - ret = nvif_object_init(&device->object, 0xd0000000, - NV_DMA_FROM_MEMORY, &(struct nv_dma_v0) { + ret = nvif_object_init(&device->object, 0, NV_DMA_FROM_MEMORY, + &(struct nv_dma_v0) { .target = NV_DMA_V0_TARGET_PCI_US, .access = NV_DMA_V0_ACCESS_RD, .start = dmac->handle + 0x0000, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index 94a906b8cb88..bbc9824af6e0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -637,7 +637,7 @@ nv46_chipset = { .imem = nv40_instmem_new, .mc = nv44_mc_new, .mmu = nv44_mmu_new, - .pci = nv4c_pci_new, + .pci = nv46_pci_new, .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -822,7 +822,7 @@ nv50_chipset = { .mc = nv50_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv50_pci_new, + .pci = nv46_pci_new, .therm = nv50_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -929,7 +929,7 @@ nv84_chipset = { .mc = nv50_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv50_pci_new, + .pci = g84_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -961,7 +961,7 @@ nv86_chipset = { .mc = nv50_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv50_pci_new, + .pci = g84_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -993,7 +993,7 @@ nv92_chipset = { .mc = nv50_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv50_pci_new, + .pci = g84_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1025,7 +1025,7 @@ nv94_chipset = { .mc = nv50_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1057,7 +1057,7 @@ nv96_chipset = { .mc = nv50_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1089,7 +1089,7 @@ nv98_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1121,7 +1121,7 @@ nva0_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1153,7 +1153,7 @@ nva3_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1187,7 +1187,7 @@ nva5_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1220,7 +1220,7 @@ nva8_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1253,7 +1253,7 @@ nvaa_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1285,7 +1285,7 @@ nvac_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, @@ -1317,7 +1317,7 @@ nvaf_chipset = { .mc = g98_mc_new, .mmu = nv50_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gt215_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1388,7 +1388,7 @@ nvc1_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1423,7 +1423,7 @@ nvc3_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1566,7 +1566,7 @@ nvcf_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gf100_pmu_new, .therm = gt215_therm_new, .timer = nv41_timer_new, @@ -1595,13 +1595,13 @@ nvd7_chipset = { .fuse = gf100_fuse_new, .gpio = gf119_gpio_new, .i2c = gf117_i2c_new, - .ibus = gf100_ibus_new, + .ibus = gf117_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .therm = gf119_therm_new, .timer = nv41_timer_new, .ce[0] = gf100_ce_new, @@ -1628,13 +1628,13 @@ nvd9_chipset = { .fuse = gf100_fuse_new, .gpio = gf119_gpio_new, .i2c = gf119_i2c_new, - .ibus = gf100_ibus_new, + .ibus = gf117_ibus_new, .imem = nv50_instmem_new, .ltc = gf100_ltc_new, .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gf119_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, @@ -1669,11 +1669,11 @@ nve4_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, @@ -1706,11 +1706,11 @@ nve6_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, @@ -1743,11 +1743,11 @@ nve7_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, - .pmu = gf119_pmu_new, + .pci = g94_pci_new, + .pmu = gk104_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, @@ -1804,11 +1804,11 @@ nvf0_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, @@ -1840,11 +1840,11 @@ nvf1_chipset = { .mc = gf100_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gk110_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, @@ -1876,11 +1876,11 @@ nv106_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, @@ -1912,11 +1912,11 @@ nv108_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gk208_pmu_new, .therm = gf119_therm_new, .timer = nv41_timer_new, - .volt = nv40_volt_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, @@ -1948,10 +1948,11 @@ nv117_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gm107_pmu_new, .therm = gm107_therm_new, .timer = gk20a_timer_new, + .volt = gk104_volt_new, .ce[0] = gk104_ce_new, .ce[2] = gk104_ce_new, .disp = gm107_disp_new, @@ -1978,9 +1979,10 @@ nv124_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gm107_pmu_new, .timer = gk20a_timer_new, + .volt = gk104_volt_new, .ce[0] = gm204_ce_new, .ce[1] = gm204_ce_new, .ce[2] = gm204_ce_new, @@ -2008,9 +2010,10 @@ nv126_chipset = { .mc = gk20a_mc_new, .mmu = gf100_mmu_new, .mxm = nv50_mxm_new, - .pci = nv40_pci_new, + .pci = g94_pci_new, .pmu = gm107_pmu_new, .timer = gk20a_timer_new, + .volt = gk104_volt_new, .ce[0] = gm204_ce_new, .ce[1] = gm204_ce_new, .ce[2] = gm204_ce_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c index e8eb14e438f4..e3c783d0e2ab 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/pci.c @@ -259,6 +259,12 @@ nvkm_device_pci_10de_0df4[] = { }; static const struct nvkm_device_pci_vendor +nvkm_device_pci_10de_0fcd[] = { + { 0x17aa, 0x3801, NULL, { .War00C800_0 = true } }, /* Lenovo Y510P */ + {} +}; + +static const struct nvkm_device_pci_vendor nvkm_device_pci_10de_0fd2[] = { { 0x1028, 0x0595, "GeForce GT 640M LE" }, { 0x1028, 0x05b2, "GeForce GT 640M LE" }, @@ -678,6 +684,7 @@ nvkm_device_pci_10de_1189[] = { static const struct nvkm_device_pci_vendor nvkm_device_pci_10de_1199[] = { { 0x1458, 0xd001, "GeForce GTX 760" }, + { 0x1462, 0x1106, "GeForce GTX 780M", { .War00C800_0 = true } }, /* Medion Erazer X7827 */ {} }; @@ -1349,7 +1356,7 @@ nvkm_device_pci_10de[] = { { 0x0fc6, "GeForce GTX 650" }, { 0x0fc8, "GeForce GT 740" }, { 0x0fc9, "GeForce GT 730" }, - { 0x0fcd, "GeForce GT 755M" }, + { 0x0fcd, "GeForce GT 755M", nvkm_device_pci_10de_0fcd }, { 0x0fce, "GeForce GT 640M LE" }, { 0x0fd1, "GeForce GT 650M" }, { 0x0fd2, "GeForce GT 640M", nvkm_device_pci_10de_0fd2 }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c index da57c8a60608..7f8a42721eb2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.c @@ -85,6 +85,9 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) unsigned long pgsize_bitmap; int ret; + if (!tdev->func->iommu_bit) + return; + mutex_init(&tdev->iommu.mutex); if (iommu_present(&platform_bus_type)) { @@ -114,7 +117,8 @@ nvkm_device_tegra_probe_iommu(struct nvkm_device_tegra *tdev) goto free_domain; ret = nvkm_mm_init(&tdev->iommu.mm, 0, - (1ULL << 40) >> tdev->iommu.pgshift, 1); + (1ULL << tdev->func->iommu_bit) >> + tdev->iommu.pgshift, 1); if (ret) goto detach_device; } @@ -237,7 +241,8 @@ nvkm_device_tegra_func = { }; int -nvkm_device_tegra_new(struct platform_device *pdev, +nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, + struct platform_device *pdev, const char *cfg, const char *dbg, bool detect, bool mmio, u64 subdev_mask, struct nvkm_device **pdevice) @@ -248,6 +253,7 @@ nvkm_device_tegra_new(struct platform_device *pdev, if (!(tdev = kzalloc(sizeof(*tdev), GFP_KERNEL))) return -ENOMEM; *pdevice = &tdev->device; + tdev->func = func; tdev->pdev = pdev; tdev->irq = -1; @@ -285,7 +291,8 @@ nvkm_device_tegra_new(struct platform_device *pdev, } #else int -nvkm_device_tegra_new(struct platform_device *pdev, +nvkm_device_tegra_new(const struct nvkm_device_tegra_func *func, + struct platform_device *pdev, const char *cfg, const char *dbg, bool detect, bool mmio, u64 subdev_mask, struct nvkm_device **pdevice) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c index 62d3fb66d0ec..2be846374d39 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/rootnv04.c @@ -109,7 +109,7 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) return -EINVAL; } -static struct nvkm_object_func +static const struct nvkm_object_func nv04_disp_root = { .mthd = nv04_disp_mthd, .ntfy = nvkm_disp_ntfy, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c index f1358a564e3e..dda7a7d224c9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c @@ -882,6 +882,7 @@ static const struct nvkm_enum gf100_mp_warp_error[] = { { 0x0d, "GPR_OUT_OF_BOUNDS" }, { 0x0e, "MEM_OUT_OF_BOUNDS" }, { 0x0f, "UNALIGNED_MEM_ACCESS" }, + { 0x10, "INVALID_ADDR_SPACE" }, { 0x11, "INVALID_PARAM" }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c index d13187409d68..d081ee41fc14 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c @@ -98,6 +98,7 @@ gf110_gr = { { -1, -1, FERMI_B, &gf100_fermi }, { -1, -1, FERMI_C, &gf100_fermi }, { -1, -1, FERMI_COMPUTE_A }, + { -1, -1, FERMI_COMPUTE_B }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c index 28483d8bf3d2..d8e8af4d3b30 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c @@ -135,6 +135,7 @@ gf117_gr = { { -1, -1, FERMI_B, &gf100_fermi }, { -1, -1, FERMI_C, &gf100_fermi }, { -1, -1, FERMI_COMPUTE_A }, + { -1, -1, FERMI_COMPUTE_B }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c index 9811a72e0313..01faf9a73774 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c @@ -189,6 +189,7 @@ gf119_gr = { { -1, -1, FERMI_B, &gf100_fermi }, { -1, -1, FERMI_C, &gf100_fermi }, { -1, -1, FERMI_COMPUTE_A }, + { -1, -1, FERMI_COMPUTE_B }, {} } }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c index 0db9be202c42..2721592d3031 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/pm/base.c @@ -633,7 +633,7 @@ nvkm_perfmon_dtor(struct nvkm_object *object) return perfmon; } -static struct nvkm_object_func +static const struct nvkm_object_func nvkm_perfmon = { .dtor = nvkm_perfmon_dtor, .mthd = nvkm_perfmon_mthd, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index 65af31441e9c..a7d69ce7abc1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -267,6 +267,12 @@ init_i2c(struct nvbios_init *init, int index) index = NVKM_I2C_BUS_PRI; if (init->outp && init->outp->i2c_upper_default) index = NVKM_I2C_BUS_SEC; + } else + if (index == 0x80) { + index = NVKM_I2C_BUS_PRI; + } else + if (index == 0x81) { + index = NVKM_I2C_BUS_SEC; } bus = nvkm_i2c_bus_find(i2c, index); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c index 441ec451b788..c268e5afe852 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.c @@ -62,19 +62,6 @@ nvbios_pmuTe(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len) } u32 -nvbios_pmuTp(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, - struct nvbios_pmuT *info) -{ - u32 data = nvbios_pmuTe(bios, ver, hdr, cnt, len); - memset(info, 0x00, sizeof(*info)); - switch (!!data * *ver) { - default: - break; - } - return data; -} - -u32 nvbios_pmuEe(struct nvkm_bios *bios, int idx, u8 *ver, u8 *hdr) { u8 cnt, len; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h index e0ec2a6b7b79..212800ecdce9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/priv.h @@ -8,7 +8,10 @@ struct nvbios_source { void *(*init)(struct nvkm_bios *, const char *); void (*fini)(void *); u32 (*read)(void *, u32 offset, u32 length, struct nvkm_bios *); + u32 (*size)(void *); bool rw; + bool ignore_checksum; + bool no_pcir; }; int nvbios_extend(struct nvkm_bios *, u32 length); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c index f0e1fc74a52e..d0ae7454764e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.c @@ -171,6 +171,7 @@ nvbios_rammapSp_from_perf(struct nvkm_bios *bios, u32 data, u8 size, int idx, p->ramcfg_DLLoff = (nvbios_rd08(bios, data + 0x03) & 0x04) >> 2; p->ramcfg_00_03_08 = (nvbios_rd08(bios, data + 0x03) & 0x08) >> 3; p->ramcfg_RON = (nvbios_rd08(bios, data + 0x03) & 0x10) >> 3; + p->ramcfg_FBVDDQ = (nvbios_rd08(bios, data + 0x03) & 0x80) >> 7; p->ramcfg_00_04_02 = (nvbios_rd08(bios, data + 0x04) & 0x02) >> 1; p->ramcfg_00_04_04 = (nvbios_rd08(bios, data + 0x04) & 0x04) >> 2; p->ramcfg_00_04_20 = (nvbios_rd08(bios, data + 0x04) & 0x20) >> 5; @@ -205,6 +206,7 @@ nvbios_rammapSp(struct nvkm_bios *bios, u32 data, p->ramcfg_DLLoff = (nvbios_rd08(bios, data + 0x02) & 0x40) >> 6; p->ramcfg_10_03_0f = (nvbios_rd08(bios, data + 0x03) & 0x0f) >> 0; p->ramcfg_10_04_01 = (nvbios_rd08(bios, data + 0x04) & 0x01) >> 0; + p->ramcfg_FBVDDQ = (nvbios_rd08(bios, data + 0x04) & 0x08) >> 3; p->ramcfg_10_05 = (nvbios_rd08(bios, data + 0x05) & 0xff) >> 0; p->ramcfg_10_06 = (nvbios_rd08(bios, data + 0x06) & 0xff) >> 0; p->ramcfg_10_07 = (nvbios_rd08(bios, data + 0x07) & 0xff) >> 0; @@ -219,7 +221,7 @@ nvbios_rammapSp(struct nvkm_bios *bios, u32 data, p->ramcfg_11_01_04 = (nvbios_rd08(bios, data + 0x01) & 0x04) >> 2; p->ramcfg_11_01_08 = (nvbios_rd08(bios, data + 0x01) & 0x08) >> 3; p->ramcfg_11_01_10 = (nvbios_rd08(bios, data + 0x01) & 0x10) >> 4; - p->ramcfg_11_01_20 = (nvbios_rd08(bios, data + 0x01) & 0x20) >> 5; + p->ramcfg_DLLoff = (nvbios_rd08(bios, data + 0x01) & 0x20) >> 5; p->ramcfg_11_01_40 = (nvbios_rd08(bios, data + 0x01) & 0x40) >> 6; p->ramcfg_11_01_80 = (nvbios_rd08(bios, data + 0x01) & 0x80) >> 7; p->ramcfg_11_02_03 = (nvbios_rd08(bios, data + 0x02) & 0x03) >> 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c index 792f017525f6..b2557e87afdd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.c @@ -45,7 +45,7 @@ shadow_fetch(struct nvkm_bios *bios, struct shadow *mthd, u32 upto) u32 read = mthd->func->read(data, start, limit - start, bios); bios->size = start + read; } - return bios->size >= limit; + return bios->size >= upto; } static int @@ -55,14 +55,22 @@ shadow_image(struct nvkm_bios *bios, int idx, u32 offset, struct shadow *mthd) struct nvbios_image image; int score = 1; - if (!shadow_fetch(bios, mthd, offset + 0x1000)) { - nvkm_debug(subdev, "%08x: header fetch failed\n", offset); - return 0; - } + if (mthd->func->no_pcir) { + image.base = 0; + image.type = 0; + image.size = mthd->func->size(mthd->data); + image.last = 1; + } else { + if (!shadow_fetch(bios, mthd, offset + 0x1000)) { + nvkm_debug(subdev, "%08x: header fetch failed\n", + offset); + return 0; + } - if (!nvbios_image(bios, idx, &image)) { - nvkm_debug(subdev, "image %d invalid\n", idx); - return 0; + if (!nvbios_image(bios, idx, &image)) { + nvkm_debug(subdev, "image %d invalid\n", idx); + return 0; + } } nvkm_debug(subdev, "%08x: type %02x, %d bytes\n", image.base, image.type, image.size); @@ -74,7 +82,8 @@ shadow_image(struct nvkm_bios *bios, int idx, u32 offset, struct shadow *mthd) switch (image.type) { case 0x00: - if (nvbios_checksum(&bios->data[image.base], image.size)) { + if (!mthd->func->ignore_checksum && + nvbios_checksum(&bios->data[image.base], image.size)) { nvkm_debug(subdev, "%08x: checksum failed\n", image.base); if (mthd->func->rw) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c index bd60d7dd09f5..4bf486b57101 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.c @@ -21,6 +21,7 @@ * */ #include "priv.h" + #include <core/pci.h> #if defined(__powerpc__) @@ -33,17 +34,26 @@ static u32 of_read(void *data, u32 offset, u32 length, struct nvkm_bios *bios) { struct priv *priv = data; - if (offset + length <= priv->size) { + if (offset < priv->size) { + length = min_t(u32, length, priv->size - offset); memcpy_fromio(bios->data + offset, priv->data + offset, length); return length; } return 0; } +static u32 +of_size(void *data) +{ + struct priv *priv = data; + return priv->size; +} + static void * of_init(struct nvkm_bios *bios, const char *name) { - struct pci_dev *pdev = bios->subdev.device->func->pci(bios->subdev.device)->pdev; + struct nvkm_device *device = bios->subdev.device; + struct pci_dev *pdev = device->func->pci(device)->pdev; struct device_node *dn; struct priv *priv; if (!(dn = pci_device_to_OF_node(pdev))) @@ -62,7 +72,10 @@ nvbios_of = { .init = of_init, .fini = (void(*)(void *))kfree, .read = of_read, + .size = of_size, .rw = false, + .ignore_checksum = true, + .no_pcir = true, }; #else const struct nvbios_source diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c index 615804c3887b..6e0a33648be9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -73,15 +73,19 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, memset(info, 0x00, sizeof(*info)); switch (!!volt * *ver) { case 0x12: + info->type = NVBIOS_VOLT_GPIO; info->vidmask = nvbios_rd08(bios, volt + 0x04); break; case 0x20: + info->type = NVBIOS_VOLT_GPIO; info->vidmask = nvbios_rd08(bios, volt + 0x05); break; case 0x30: + info->type = NVBIOS_VOLT_GPIO; info->vidmask = nvbios_rd08(bios, volt + 0x04); break; case 0x40: + info->type = NVBIOS_VOLT_GPIO; info->base = nvbios_rd32(bios, volt + 0x04); info->step = nvbios_rd16(bios, volt + 0x08); info->vidmask = nvbios_rd08(bios, volt + 0x0b); @@ -90,11 +94,20 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->max = info->base; break; case 0x50: - info->vidmask = nvbios_rd08(bios, volt + 0x06); info->min = nvbios_rd32(bios, volt + 0x0a); info->max = nvbios_rd32(bios, volt + 0x0e); info->base = nvbios_rd32(bios, volt + 0x12) & 0x00ffffff; - info->step = nvbios_rd16(bios, volt + 0x16); + + /* offset 4 seems to be a flag byte */ + if (nvbios_rd32(bios, volt + 0x4) & 1) { + info->type = NVBIOS_VOLT_PWM; + info->pwm_freq = nvbios_rd32(bios, volt + 0x5) / 1000; + info->pwm_range = nvbios_rd32(bios, volt + 0x16); + } else { + info->type = NVBIOS_VOLT_GPIO; + info->vidmask = nvbios_rd08(bios, volt + 0x06); + info->step = nvbios_rd16(bios, volt + 0x16); + } break; } return volt; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c index 79f1cf513b36..2a5668938f2f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c @@ -132,6 +132,38 @@ nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data) } void +nvkm_hwsq_wait_vblank(struct nvkm_hwsq *hwsq) +{ + struct nvkm_subdev *subdev = hwsq->subdev; + struct nvkm_device *device = subdev->device; + u32 heads, x, y, px = 0; + int i, head_sync; + + heads = nvkm_rd32(device, 0x610050); + for (i = 0; i < 2; i++) { + /* Heuristic: sync to head with biggest resolution */ + if (heads & (2 << (i << 3))) { + x = nvkm_rd32(device, 0x610b40 + (0x540 * i)); + y = (x & 0xffff0000) >> 16; + x &= 0x0000ffff; + if ((x * y) > px) { + px = (x * y); + head_sync = i; + } + } + } + + if (px == 0) { + nvkm_debug(subdev, "WAIT VBLANK !NO ACTIVE HEAD\n"); + return; + } + + nvkm_debug(subdev, "WAIT VBLANK HEAD%d\n", head_sync); + nvkm_hwsq_wait(hwsq, head_sync ? 0x3 : 0x1, 0x0); + nvkm_hwsq_wait(hwsq, head_sync ? 0x3 : 0x1, 0x1); +} + +void nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec) { u8 shift = 0, usec = nsec / 1000; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h index 8117ec5a1468..54ec3b131dfd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h @@ -134,6 +134,12 @@ hwsq_wait(struct hwsq *ram, u8 flag, u8 data) } static inline void +hwsq_wait_vblank(struct hwsq *ram) +{ + nvkm_hwsq_wait_vblank(ram->hwsq); +} + +static inline void hwsq_nsec(struct hwsq *ram, u32 nsec) { nvkm_hwsq_nsec(ram->hwsq, nsec); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c index 347da9ee20f5..f97e3ec196bb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c @@ -44,5 +44,5 @@ int g84_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk) { return nv50_clk_new_(&g84_clk, device, index, - (device->chipset == 0xa0), pclk); + (device->chipset >= 0x94), pclk); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c index 79b523aa52aa..60ece0a8a2e1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.c @@ -63,7 +63,7 @@ ramgddr3_wr_lo[] = { { 5, 2 }, { 7, 4 }, { 8, 5 }, { 9, 6 }, { 10, 7 }, { 11, 0 }, { 13 , 1 }, /* the below are mentioned in some, but not all, gddr3 docs */ - { 4, 1 }, { 6, 3 }, { 12, 1 }, + { 4, 0 }, { 6, 3 }, { 12, 1 }, { -1 } }; @@ -87,15 +87,17 @@ nvkm_gddr3_calc(struct nvkm_ram *ram) WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; /* XXX: Get these values from the VBIOS instead */ DLL = !(ram->mr[1] & 0x1); - ODT = (ram->mr[1] & 0x004) >> 2 | - (ram->mr[1] & 0x040) >> 5 | - (ram->mr[1] & 0x200) >> 7; RON = !(ram->mr[1] & 0x300) >> 8; break; default: return -ENOSYS; } + if (ram->next->bios.timing_ver == 0x20 || + ram->next->bios.ramcfg_timing == 0xff) { + ODT = (ram->mr[1] & 0xc) >> 2; + } + hi = ram->mr[2] & 0x1; CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL); WR = ramxlat(ramgddr3_wr_lo, WR); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c index 24f83b09e6a1..2cc074d3901a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.c @@ -38,11 +38,12 @@ nvkm_gddr5_calc(struct nvkm_ram *ram, bool nuts) int WL, CL, WR, at[2], dt, ds; int rq = ram->freq < 1000000; /* XXX */ + xd = !ram->next->bios.ramcfg_DLLoff; + switch (ram->next->bios.ramcfg_ver) { case 0x11: pd = ram->next->bios.ramcfg_11_01_80; lf = ram->next->bios.ramcfg_11_01_40; - xd = !ram->next->bios.ramcfg_11_01_20; vh = ram->next->bios.ramcfg_11_02_10; vr = ram->next->bios.ramcfg_11_02_04; vo = ram->next->bios.ramcfg_11_06; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c index 989355622aac..9df45030ff9f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c @@ -673,6 +673,25 @@ gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq) * DDR3 ******************************************************************************/ +static void +nvkm_sddr3_dll_reset(struct gk104_ramfuc *fuc) +{ + ram_nuke(fuc, mr[0]); + ram_mask(fuc, mr[0], 0x100, 0x100); + ram_mask(fuc, mr[0], 0x100, 0x000); +} + +static void +nvkm_sddr3_dll_disable(struct gk104_ramfuc *fuc) +{ + u32 mr1_old = ram_rd32(fuc, mr[1]); + + if (!(mr1_old & 0x1)) { + ram_mask(fuc, mr[1], 0x1, 0x1); + ram_nsec(fuc, 1000); + } +} + static int gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) { @@ -702,6 +721,10 @@ gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000); ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */ + + if (next->bios.ramcfg_DLLoff) + nvkm_sddr3_dll_disable(fuc); + ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */ ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */ ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000); @@ -879,17 +902,20 @@ gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq) ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */ ram_nsec(fuc, 1000); - ram_nuke(fuc, mr[0]); - ram_mask(fuc, mr[0], 0x100, 0x100); - ram_mask(fuc, mr[0], 0x100, 0x000); + if (!next->bios.ramcfg_DLLoff) { + ram_mask(fuc, mr[1], 0x1, 0x0); + nvkm_sddr3_dll_reset(fuc); + } - ram_mask(fuc, mr[2], 0xfff, ram->base.mr[2]); + ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]); + ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]); ram_wr32(fuc, mr[0], ram->base.mr[0]); ram_nsec(fuc, 1000); - ram_nuke(fuc, mr[0]); - ram_mask(fuc, mr[0], 0x100, 0x100); - ram_mask(fuc, mr[0], 0x100, 0x000); + if (!next->bios.ramcfg_DLLoff) { + nvkm_sddr3_dll_reset(fuc); + ram_nsec(fuc, 1000); + } if (vc == 0 && ram_have(fuc, gpio2E)) { u32 temp = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]); @@ -945,6 +971,67 @@ gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data) } static int +gk104_calc_pll_output(int fN, int M, int N, int P, int clk) +{ + return ((clk * N) + (((u16)(fN + 4096) * clk) >> 13)) / (M * P); +} + +static int +gk104_pll_calc_hiclk(int target_khz, int crystal, + int *N1, int *fN1, int *M1, int *P1, + int *N2, int *M2, int *P2) +{ + int best_clk = 0, best_err = target_khz, p_ref, n_ref; + bool upper = false; + + *M1 = 1; + /* M has to be 1, otherwise it gets unstable */ + *M2 = 1; + /* can be 1 or 2, sticking with 1 for simplicity */ + *P2 = 1; + + for (p_ref = 0x7; p_ref >= 0x5; --p_ref) { + for (n_ref = 0x25; n_ref <= 0x2b; ++n_ref) { + int cur_N, cur_clk, cur_err; + + cur_clk = gk104_calc_pll_output(0, 1, n_ref, p_ref, crystal); + cur_N = target_khz / cur_clk; + cur_err = target_khz + - gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk); + + /* we found a better combination */ + if (cur_err < best_err) { + best_err = cur_err; + best_clk = cur_clk; + *N2 = cur_N; + *N1 = n_ref; + *P1 = p_ref; + upper = false; + } + + cur_N += 1; + cur_err = gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk) + - target_khz; + if (cur_err < best_err) { + best_err = cur_err; + best_clk = cur_clk; + *N2 = cur_N; + *N1 = n_ref; + *P1 = p_ref; + upper = true; + } + } + } + + /* adjust fN to get closer to the target clock */ + *fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal); + if (upper) + *fN1 = (u16)(1 - *fN1); + + return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal); +} + +static int gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next) { struct gk104_ramfuc *fuc = &ram->fuc; @@ -968,31 +1055,24 @@ gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next) * kepler boards, no idea how/why they're chosen. */ refclk = next->freq; - if (ram->mode == 2) - refclk = fuc->mempll.refclk; - - /* calculate refpll coefficients */ - ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1, - &ram->fN1, &ram->M1, &ram->P1); - fuc->mempll.refclk = ret; - if (ret <= 0) { - nvkm_error(subdev, "unable to calc refpll\n"); - return -EINVAL; - } - - /* calculate mempll coefficients, if we're using it */ if (ram->mode == 2) { - /* post-divider doesn't work... the reg takes the values but - * appears to completely ignore it. there *is* a bit at - * bit 28 that appears to divide the clock by 2 if set. - */ - fuc->mempll.min_p = 1; - fuc->mempll.max_p = 2; - - ret = gt215_pll_calc(subdev, &fuc->mempll, next->freq, - &ram->N2, NULL, &ram->M2, &ram->P2); + ret = gk104_pll_calc_hiclk(next->freq, subdev->device->crystal, + &ram->N1, &ram->fN1, &ram->M1, &ram->P1, + &ram->N2, &ram->M2, &ram->P2); + fuc->mempll.refclk = ret; + if (ret <= 0) { + nvkm_error(subdev, "unable to calc plls\n"); + return -EINVAL; + } + nvkm_debug(subdev, "sucessfully calced PLLs for clock %i kHz" + " (refclock: %i kHz)\n", next->freq, ret); + } else { + /* calculate refpll coefficients */ + ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1, + &ram->fN1, &ram->M1, &ram->P1); + fuc->mempll.refclk = ret; if (ret <= 0) { - nvkm_error(subdev, "unable to calc mempll\n"); + nvkm_error(subdev, "unable to calc refpll\n"); return -EINVAL; } } @@ -1600,6 +1680,7 @@ gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) break; case NVKM_RAM_TYPE_DDR3: ram->fuc.r_mr[0] = ramfuc_reg(0x10f300); + ram->fuc.r_mr[1] = ramfuc_reg(0x10f304); ram->fuc.r_mr[2] = ramfuc_reg(0x10f320); break; default: diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c index 5c08ae8023fa..d15ea886df27 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c @@ -34,9 +34,6 @@ #include <subdev/clk/gt215.h> #include <subdev/gpio.h> -/* XXX: Remove when memx gains GPIO support */ -extern int nv50_gpio_location(int line, u32 *reg, u32 *shift); - struct gt215_ramfuc { struct ramfuc base; struct ramfuc_reg r_0x001610; @@ -75,7 +72,7 @@ struct gt215_ramfuc { struct ramfuc_reg r_0x111400; struct ramfuc_reg r_0x611200; struct ramfuc_reg r_mr[4]; - struct ramfuc_reg r_gpioFBVREF; + struct ramfuc_reg r_gpio[4]; }; struct gt215_ltrain { @@ -466,24 +463,27 @@ gt215_ram_lock_pll(struct gt215_ramfuc *fuc, struct gt215_clk_info *mclk) } static void -gt215_ram_fbvref(struct gt215_ramfuc *fuc, u32 val) +gt215_ram_gpio(struct gt215_ramfuc *fuc, u8 tag, u32 val) { struct nvkm_gpio *gpio = fuc->base.fb->subdev.device->gpio; struct dcb_gpio_func func; u32 reg, sh, gpio_val; int ret; - if (nvkm_gpio_get(gpio, 0, 0x2e, DCB_GPIO_UNUSED) != val) { - ret = nvkm_gpio_find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func); + if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) { + ret = nvkm_gpio_find(gpio, 0, tag, DCB_GPIO_UNUSED, &func); if (ret) return; - nv50_gpio_location(func.line, ®, &sh); - gpio_val = ram_rd32(fuc, gpioFBVREF); + reg = func.line >> 3; + sh = (func.line & 0x7) << 2; + gpio_val = ram_rd32(fuc, gpio[reg]); if (gpio_val & (8 << sh)) val = !val; + if (!(func.log[1] & 1)) + val = !val; - ram_mask(fuc, gpioFBVREF, (0x3 << sh), ((val | 0x2) << sh)); + ram_mask(fuc, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); ram_nsec(fuc, 20000); } } @@ -498,6 +498,7 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq) struct nvkm_device *device = subdev->device; struct nvkm_bios *bios = device->bios; struct gt215_clk_info mclk; + struct nvkm_gpio *gpio = device->gpio; struct nvkm_ram_data *next; u8 ver, hdr, cnt, len, strap; u32 data; @@ -642,8 +643,8 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq) break; } - if (fuc->r_gpioFBVREF.addr && next->bios.timing_10_ODT) - gt215_ram_fbvref(fuc, 0); + if (next->bios.timing_10_ODT) + gt215_ram_gpio(fuc, 0x2e, 1); /* Brace RAM for impact */ ram_wr32(fuc, 0x1002d4, 0x00000001); @@ -656,6 +657,23 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq) if (device->chipset == 0xa3 && freq <= 500000) ram_mask(fuc, 0x100700, 0x00000006, 0x00000006); + /* Alter FBVDD/Q, apparently must be done with PLL disabled, thus + * set it to bypass */ + if (nvkm_gpio_get(gpio, 0, 0x18, DCB_GPIO_UNUSED) == + next->bios.ramcfg_FBVDDQ) { + data = ram_rd32(fuc, 0x004000) & 0x9; + + if (data == 0x1) + ram_mask(fuc, 0x004000, 0x8, 0x8); + if (data & 0x1) + ram_mask(fuc, 0x004000, 0x1, 0x0); + + gt215_ram_gpio(fuc, 0x18, !next->bios.ramcfg_FBVDDQ); + + if (data & 0x1) + ram_mask(fuc, 0x004000, 0x1, 0x1); + } + /* Fiddle with clocks */ /* There's 4 scenario's * pll->pll: first switch to a 324MHz clock, set up new PLL, switch @@ -753,39 +771,43 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq) unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100; r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000; - if (next->bios.ramcfg_10_02_04) { - switch (ram->base.type) { - case NVKM_RAM_TYPE_DDR3: - if (device->chipset != 0xa8) - r111100 |= 0x00000004; - /* no break */ - case NVKM_RAM_TYPE_DDR2: - r111100 |= 0x08000000; - break; - default: - break; - } - } else { - switch (ram->base.type) { - case NVKM_RAM_TYPE_DDR2: - r111100 |= 0x1a800000; + /* NVA8 seems to skip various bits related to ramcfg_10_02_04 */ + if (device->chipset == 0xa8) { + r111100 |= 0x08000000; + if (!next->bios.ramcfg_10_02_04) unk714 |= 0x00000010; - break; - case NVKM_RAM_TYPE_DDR3: - if (device->chipset == 0xa8) { - r111100 |= 0x08000000; - } else { - r111100 &= ~0x00000004; + } else { + if (next->bios.ramcfg_10_02_04) { + switch (ram->base.type) { + case NVKM_RAM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR3: + r111100 &= ~0x00000020; + if (next->bios.ramcfg_10_02_10) + r111100 |= 0x08000004; + else + r111100 |= 0x00000024; + break; + default: + break; + } + } else { + switch (ram->base.type) { + case NVKM_RAM_TYPE_DDR2: + case NVKM_RAM_TYPE_DDR3: + r111100 &= ~0x00000024; r111100 |= 0x12800000; + + if (next->bios.ramcfg_10_02_10) + r111100 |= 0x08000000; + unk714 |= 0x00000010; + break; + case NVKM_RAM_TYPE_GDDR3: + r111100 |= 0x30000000; + unk714 |= 0x00000020; + break; + default: + break; } - unk714 |= 0x00000010; - break; - case NVKM_RAM_TYPE_GDDR3: - r111100 |= 0x30000000; - unk714 |= 0x00000020; - break; - default: - break; } } @@ -809,8 +831,8 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq) ram_mask(fuc, 0x100718, 0xffffffff, unk718); ram_mask(fuc, 0x111100, 0xffffffff, r111100); - if (fuc->r_gpioFBVREF.addr && !next->bios.timing_10_ODT) - gt215_ram_fbvref(fuc, 1); + if (!next->bios.timing_10_ODT) + gt215_ram_gpio(fuc, 0x2e, 0); /* Reset DLL */ if (!next->bios.ramcfg_DLLoff) @@ -919,10 +941,7 @@ gt215_ram_func = { int gt215_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) { - struct nvkm_gpio *gpio = fb->subdev.device->gpio; - struct dcb_gpio_func func; struct gt215_ram *ram; - u32 reg, shift; int ret, i; if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL))) @@ -981,12 +1000,10 @@ gt215_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) ram->fuc.r_mr[2] = ramfuc_reg(0x1002e0); ram->fuc.r_mr[3] = ramfuc_reg(0x1002e4); } - - ret = nvkm_gpio_find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func); - if (ret == 0) { - nv50_gpio_location(func.line, ®, &shift); - ram->fuc.r_gpioFBVREF = ramfuc_reg(reg); - } + ram->fuc.r_gpio[0] = ramfuc_reg(0x00e104); + ram->fuc.r_gpio[1] = ramfuc_reg(0x00e108); + ram->fuc.r_gpio[2] = ramfuc_reg(0x00e120); + ram->fuc.r_gpio[3] = ramfuc_reg(0x00e124); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 9197e0ef5cdb..87bde8ff2d6b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -33,6 +33,7 @@ #include <subdev/bios/rammap.h> #include <subdev/bios/timing.h> #include <subdev/clk/pll.h> +#include <subdev/gpio.h> struct nv50_ramseq { struct hwsq base; @@ -59,6 +60,7 @@ struct nv50_ramseq { struct hwsq_reg r_0x611200; struct hwsq_reg r_timing[9]; struct hwsq_reg r_mr[4]; + struct hwsq_reg r_gpio[4]; }; struct nv50_ram { @@ -144,6 +146,38 @@ nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) nvkm_debug(subdev, " 240: %08x\n", timing[8]); return 0; } + +static int +nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) +{ + unsigned int i; + struct nvbios_ramcfg *cfg = &ram->base.target.bios; + struct nvkm_subdev *subdev = &ram->base.fb->subdev; + struct nvkm_device *device = subdev->device; + + for (i = 0; i <= 8; i++) + timing[i] = nvkm_rd32(device, 0x100220 + (i * 4)); + + /* Derive the bare minimum for the MR calculation to succeed */ + cfg->timing_ver = 0x10; + T(CL) = (timing[3] & 0xff) + 1; + + switch (ram->base.type) { + case NVKM_RAM_TYPE_DDR2: + T(CWL) = T(CL) - 1; + break; + case NVKM_RAM_TYPE_GDDR3: + T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1; + break; + default: + return -ENOSYS; + break; + } + + T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); + + return 0; +} #undef T static void @@ -154,6 +188,33 @@ nvkm_sddr2_dll_reset(struct nv50_ramseq *hwsq) ram_nsec(hwsq, 24000); } +static void +nv50_ram_gpio(struct nv50_ramseq *hwsq, u8 tag, u32 val) +{ + struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio; + struct dcb_gpio_func func; + u32 reg, sh, gpio_val; + int ret; + + if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) { + ret = nvkm_gpio_find(gpio, 0, tag, DCB_GPIO_UNUSED, &func); + if (ret) + return; + + reg = func.line >> 3; + sh = (func.line & 0x7) << 2; + gpio_val = ram_rd32(hwsq, gpio[reg]); + + if (gpio_val & (8 << sh)) + val = !val; + if (!(func.log[1] & 1)) + val = !val; + + ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); + ram_nsec(hwsq, 20000); + } +} + static int nv50_ram_calc(struct nvkm_ram *base, u32 freq) { @@ -213,10 +274,11 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) strap, data, ver, hdr); return -EINVAL; } + nv50_ram_timing_calc(ram, timing); + } else { + nv50_ram_timing_read(ram, timing); } - nv50_ram_timing_calc(ram, timing); - ret = ram_init(hwsq, subdev); if (ret) return ret; @@ -235,14 +297,18 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) break; } - if (ret) + if (ret) { + nvkm_error(subdev, "Could not calculate MR\n"); return ret; + } + + if (subdev->device->chipset <= 0x96 && !next->bios.ramcfg_00_03_02) + ram_mask(hwsq, 0x100710, 0x00000200, 0x00000000); /* Always disable this bit during reclock */ ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000); - ram_wait(hwsq, 0x01, 0x00); /* wait for !vblank */ - ram_wait(hwsq, 0x01, 0x01); /* wait for vblank */ + ram_wait_vblank(hwsq); ram_wr32(hwsq, 0x611200, 0x00003300); ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */ ram_nsec(hwsq, 8000); @@ -250,6 +316,9 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ ram_nsec(hwsq, 2000); + if (next->bios.timing_10_ODT) + nv50_ram_gpio(hwsq, 0x2e, 1); + ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */ ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ @@ -286,8 +355,12 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) next->bios.rammap_00_16_40 << 14); ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); ram_mask(hwsq, 0x004008, 0x91ff0000, r004008); - if (subdev->device->chipset >= 0x96) + + /* XXX: GDDR3 only? */ + if (subdev->device->chipset >= 0x92) ram_wr32(hwsq, 0x100da0, r100da0); + + nv50_ram_gpio(hwsq, 0x18, !next->bios.ramcfg_FBVDDQ); ram_nsec(hwsq, 64000); /*XXX*/ ram_nsec(hwsq, 32000); /*XXX*/ @@ -329,19 +402,33 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12); /* XXX: A lot of this could be "chipset"/"ram type" specific stuff */ - unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000101; + unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000100; unk714 = ram_rd32(hwsq, 0x100714) & ~0xf0000020; unk718 = ram_rd32(hwsq, 0x100718) & ~0x00000100; unk71c = ram_rd32(hwsq, 0x10071c) & ~0x00000100; + if (subdev->device->chipset <= 0x96) { + unk710 &= ~0x0000006e; + unk714 &= ~0x00000100; + + if (!next->bios.ramcfg_00_03_08) + unk710 |= 0x00000060; + if (!next->bios.ramcfg_FBVDDQ) + unk714 |= 0x00000100; + if ( next->bios.ramcfg_00_04_04) + unk710 |= 0x0000000e; + } else { + unk710 &= ~0x00000001; + + if (!next->bios.ramcfg_00_03_08) + unk710 |= 0x00000001; + } if ( next->bios.ramcfg_00_03_01) unk71c |= 0x00000100; if ( next->bios.ramcfg_00_03_02) unk710 |= 0x00000100; - if (!next->bios.ramcfg_00_03_08) { - unk710 |= 0x1; - unk714 |= 0x20; - } + if (!next->bios.ramcfg_00_03_08) + unk714 |= 0x00000020; if ( next->bios.ramcfg_00_04_04) unk714 |= 0x70000000; if ( next->bios.ramcfg_00_04_20) @@ -352,6 +439,8 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) ram_mask(hwsq, 0x100718, 0xffffffff, unk718); ram_mask(hwsq, 0x100710, 0xffffffff, unk710); + /* XXX: G94 does not even test these regs in trace. Harmless we do it, + * but why is it omitted? */ if (next->bios.rammap_00_16_20) { ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 | next->bios.ramcfg_00_06 << 8 | @@ -364,6 +453,9 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) } ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]); + if (!next->bios.timing_10_ODT) + nv50_ram_gpio(hwsq, 0x2e, 0); + /* Reset DLL */ if (!next->bios.ramcfg_DLLoff) nvkm_sddr2_dll_reset(hwsq); @@ -379,6 +471,8 @@ nv50_ram_calc(struct nvkm_ram *base, u32 freq) ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000); if (next->bios.ramcfg_00_03_02) ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000); + if (subdev->device->chipset <= 0x96 && next->bios.ramcfg_00_03_02) + ram_mask(hwsq, 0x100710, 0x00000200, 0x00000200); return 0; } @@ -634,5 +728,10 @@ nv50_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram) ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); } + ram->hwsq.r_gpio[0] = hwsq_reg(0x00e104); + ram->hwsq.r_gpio[1] = hwsq_reg(0x00e108); + ram->hwsq.r_gpio[2] = hwsq_reg(0x00e120); + ram->hwsq.r_gpio[3] = hwsq_reg(0x00e124); + return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h index 0f1f97ccd5f6..8df7306d5729 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramseq.h @@ -11,5 +11,6 @@ #define ram_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) #define ram_setf(s,f,d) hwsq_setf(&(s)->base, (f), (d)) #define ram_wait(s,f,d) hwsq_wait(&(s)->base, (f), (d)) +#define ram_wait_vblank(s) hwsq_wait_vblank(&(s)->base) #define ram_nsec(s,n) hwsq_nsec(&(s)->base, (n)) #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c index 86bf67456b14..b9f1ffdfc602 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.c @@ -76,6 +76,12 @@ nvkm_sddr2_calc(struct nvkm_ram *ram) return -ENOSYS; } + if (ram->next->bios.timing_ver == 0x20 || + ram->next->bios.ramcfg_timing == 0xff) { + ODT = (ram->mr[1] & 0x004) >> 2 | + (ram->mr[1] & 0x040) >> 5; + } + CL = ramxlat(ramddr2_cl, CL); WR = ramxlat(ramddr2_wr, WR); if (CL < 0 || WR < 0) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c index b4edc97dc8c5..26900333b1d6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.c @@ -70,6 +70,8 @@ nvkm_sddr3_calc(struct nvkm_ram *ram) { int CWL, CL, WR, DLL = 0, ODT = 0; + DLL = !ram->next->bios.ramcfg_DLLoff; + switch (ram->next->bios.timing_ver) { case 0x10: if (ram->next->bios.timing_hdr < 0x17) { @@ -79,7 +81,6 @@ nvkm_sddr3_calc(struct nvkm_ram *ram) CWL = ram->next->bios.timing_10_CWL; CL = ram->next->bios.timing_10_CL; WR = ram->next->bios.timing_10_WR; - DLL = !ram->next->bios.ramcfg_DLLoff; ODT = ram->next->bios.timing_10_ODT; break; case 0x20: @@ -87,7 +88,6 @@ nvkm_sddr3_calc(struct nvkm_ram *ram) CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0; WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16; /* XXX: Get these values from the VBIOS instead */ - DLL = !(ram->mr[1] & 0x1); ODT = (ram->mr[1] & 0x004) >> 2 | (ram->mr[1] & 0x040) >> 5 | (ram->mr[1] & 0x200) >> 7; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c index 8996649209ab..73923fd5f7f2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.c @@ -54,7 +54,7 @@ nv50_gpio_reset(struct nvkm_gpio *gpio, u8 match) } } -int +static int nv50_gpio_location(int line, u32 *reg, u32 *shift) { const u32 nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild index a0b12d27284a..de888fa62b3e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/Kbuild @@ -1,3 +1,4 @@ nvkm-y += nvkm/subdev/ibus/gf100.o +nvkm-y += nvkm/subdev/ibus/gf117.o nvkm-y += nvkm/subdev/ibus/gk104.o nvkm-y += nvkm/subdev/ibus/gk20a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c index 37a0496f7ed1..72d6330d243d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf100.c @@ -21,7 +21,7 @@ * * Authors: Ben Skeggs */ -#include <subdev/ibus.h> +#include "priv.h" static void gf100_ibus_intr_hub(struct nvkm_subdev *ibus, int i) @@ -56,7 +56,7 @@ gf100_ibus_intr_gpc(struct nvkm_subdev *ibus, int i) nvkm_mask(device, 0x128128 + (i * 0x0400), 0x00000200, 0x00000000); } -static void +void gf100_ibus_intr(struct nvkm_subdev *ibus) { struct nvkm_device *device = ibus->device; @@ -92,8 +92,21 @@ gf100_ibus_intr(struct nvkm_subdev *ibus) } } +static int +gf100_ibus_init(struct nvkm_subdev *ibus) +{ + struct nvkm_device *device = ibus->device; + nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); + nvkm_wr32(device, 0x12232c, 0x00100064); + nvkm_wr32(device, 0x122330, 0x00100064); + nvkm_wr32(device, 0x122334, 0x00100064); + nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); + return 0; +} + static const struct nvkm_subdev_func gf100_ibus = { + .init = gf100_ibus_init, .intr = gf100_ibus_intr, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf117.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf117.c new file mode 100644 index 000000000000..f69f263c5906 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/gf117.c @@ -0,0 +1,51 @@ +/* + * Copyright 2015 Samuel Pitosiet + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Samuel Pitoiset + */ +#include "priv.h" + +static int +gf117_ibus_init(struct nvkm_subdev *ibus) +{ + struct nvkm_device *device = ibus->device; + nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); + nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); + nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); + return 0; +} + +static const struct nvkm_subdev_func +gf117_ibus = { + .init = gf117_ibus_init, + .intr = gf100_ibus_intr, +}; + +int +gf117_ibus_new(struct nvkm_device *device, int index, + struct nvkm_subdev **pibus) +{ + struct nvkm_subdev *ibus; + if (!(ibus = *pibus = kzalloc(sizeof(*ibus), GFP_KERNEL))) + return -ENOMEM; + nvkm_subdev_ctor(&gf117_ibus, device, index, 0, ibus); + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h new file mode 100644 index 000000000000..48e1b6365ce6 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/priv.h @@ -0,0 +1,7 @@ +#ifndef __NVKM_IBUS_PRIV_H__ +#define __NVKM_IBUS_PRIV_H__ + +#include <subdev/ibus.h> + +void gf100_ibus_intr(struct nvkm_subdev *); +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c index cd7feb1b25f6..fc419bb8eab7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c @@ -23,35 +23,42 @@ /* * GK20A does not have dedicated video memory, and to accurately represent this * fact Nouveau will not create a RAM device for it. Therefore its instmem - * implementation must be done directly on top of system memory, while providing - * coherent read and write operations. + * implementation must be done directly on top of system memory, while + * preserving coherency for read and write operations. * * Instmem can be allocated through two means: - * 1) If an IOMMU mapping has been probed, the IOMMU API is used to make memory + * 1) If an IOMMU unit has been probed, the IOMMU API is used to make memory * pages contiguous to the GPU. This is the preferred way. - * 2) If no IOMMU mapping is probed, the DMA API is used to allocate physically + * 2) If no IOMMU unit is probed, the DMA API is used to allocate physically * contiguous memory. * - * In both cases CPU read and writes are performed using PRAMIN (i.e. using the - * GPU path) to ensure these operations are coherent for the GPU. This allows us - * to use more "relaxed" allocation parameters when using the DMA API, since we - * never need a kernel mapping. + * In both cases CPU read and writes are performed by creating a write-combined + * mapping. The GPU L2 cache must thus be flushed/invalidated when required. To + * be conservative we do this every time we acquire or release an instobj, but + * ideally L2 management should be handled at a higher level. + * + * To improve performance, CPU mappings are not removed upon instobj release. + * Instead they are placed into a LRU list to be recycled when the mapped space + * goes beyond a certain threshold. At the moment this limit is 1MB. */ -#define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base) #include "priv.h" #include <core/memory.h> #include <core/mm.h> #include <core/tegra.h> #include <subdev/fb.h> - -#define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory) +#include <subdev/ltc.h> struct gk20a_instobj { struct nvkm_memory memory; - struct gk20a_instmem *imem; struct nvkm_mem mem; + struct gk20a_instmem *imem; + + /* CPU mapping */ + u32 *vaddr; + struct list_head vaddr_node; }; +#define gk20a_instobj(p) container_of((p), struct gk20a_instobj, memory) /* * Used for objects allocated using the DMA API @@ -59,10 +66,12 @@ struct gk20a_instobj { struct gk20a_instobj_dma { struct gk20a_instobj base; - void *cpuaddr; + u32 *cpuaddr; dma_addr_t handle; struct nvkm_mm_node r; }; +#define gk20a_instobj_dma(p) \ + container_of(gk20a_instobj(p), struct gk20a_instobj_dma, base) /* * Used for objects flattened using the IOMMU API @@ -70,25 +79,38 @@ struct gk20a_instobj_dma { struct gk20a_instobj_iommu { struct gk20a_instobj base; - /* array of base.mem->size pages */ + /* will point to the higher half of pages */ + dma_addr_t *dma_addrs; + /* array of base.mem->size pages (+ dma_addr_ts) */ struct page *pages[]; }; +#define gk20a_instobj_iommu(p) \ + container_of(gk20a_instobj(p), struct gk20a_instobj_iommu, base) struct gk20a_instmem { struct nvkm_instmem base; - unsigned long lock_flags; + + /* protects vaddr_* and gk20a_instobj::vaddr* */ spinlock_t lock; - u64 addr; + + /* CPU mappings LRU */ + unsigned int vaddr_use; + unsigned int vaddr_max; + struct list_head vaddr_lru; /* Only used if IOMMU if present */ struct mutex *mm_mutex; struct nvkm_mm *mm; struct iommu_domain *domain; unsigned long iommu_pgshift; + u16 iommu_bit; /* Only used by DMA API */ struct dma_attrs attrs; + + void __iomem * (*cpu_map)(struct nvkm_memory *); }; +#define gk20a_instmem(p) container_of((p), struct gk20a_instmem, base) static enum nvkm_memory_target gk20a_instobj_target(struct nvkm_memory *memory) @@ -100,7 +122,6 @@ static u64 gk20a_instobj_addr(struct nvkm_memory *memory) { return gk20a_instobj(memory)->mem.offset; - } static u64 @@ -110,107 +131,217 @@ gk20a_instobj_size(struct nvkm_memory *memory) } static void __iomem * +gk20a_instobj_cpu_map_dma(struct nvkm_memory *memory) +{ + struct gk20a_instobj_dma *node = gk20a_instobj_dma(memory); + struct device *dev = node->base.imem->base.subdev.device->dev; + int npages = nvkm_memory_size(memory) >> 12; + struct page *pages[npages]; + int i; + + /* phys_to_page does not exist on all platforms... */ + pages[0] = pfn_to_page(dma_to_phys(dev, node->handle) >> PAGE_SHIFT); + for (i = 1; i < npages; i++) + pages[i] = pages[0] + i; + + return vmap(pages, npages, VM_MAP, pgprot_writecombine(PAGE_KERNEL)); +} + +static void __iomem * +gk20a_instobj_cpu_map_iommu(struct nvkm_memory *memory) +{ + struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); + int npages = nvkm_memory_size(memory) >> 12; + + return vmap(node->pages, npages, VM_MAP, + pgprot_writecombine(PAGE_KERNEL)); +} + +/* + * Must be called while holding gk20a_instmem_lock + */ +static void +gk20a_instmem_vaddr_gc(struct gk20a_instmem *imem, const u64 size) +{ + while (imem->vaddr_use + size > imem->vaddr_max) { + struct gk20a_instobj *obj; + + /* no candidate that can be unmapped, abort... */ + if (list_empty(&imem->vaddr_lru)) + break; + + obj = list_first_entry(&imem->vaddr_lru, struct gk20a_instobj, + vaddr_node); + list_del(&obj->vaddr_node); + vunmap(obj->vaddr); + obj->vaddr = NULL; + imem->vaddr_use -= nvkm_memory_size(&obj->memory); + nvkm_debug(&imem->base.subdev, "(GC) vaddr used: %x/%x\n", + imem->vaddr_use, imem->vaddr_max); + + } +} + +static void __iomem * gk20a_instobj_acquire(struct nvkm_memory *memory) { - struct gk20a_instmem *imem = gk20a_instobj(memory)->imem; + struct gk20a_instobj *node = gk20a_instobj(memory); + struct gk20a_instmem *imem = node->imem; + struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; + const u64 size = nvkm_memory_size(memory); unsigned long flags; + + nvkm_ltc_flush(ltc); + spin_lock_irqsave(&imem->lock, flags); - imem->lock_flags = flags; - return NULL; + + if (node->vaddr) { + /* remove us from the LRU list since we cannot be unmapped */ + list_del(&node->vaddr_node); + + goto out; + } + + /* try to free some address space if we reached the limit */ + gk20a_instmem_vaddr_gc(imem, size); + + node->vaddr = imem->cpu_map(memory); + + if (!node->vaddr) { + nvkm_error(&imem->base.subdev, "cannot map instobj - " + "this is not going to end well...\n"); + goto out; + } + + imem->vaddr_use += size; + nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", + imem->vaddr_use, imem->vaddr_max); + +out: + spin_unlock_irqrestore(&imem->lock, flags); + + return node->vaddr; } static void gk20a_instobj_release(struct nvkm_memory *memory) { - struct gk20a_instmem *imem = gk20a_instobj(memory)->imem; - spin_unlock_irqrestore(&imem->lock, imem->lock_flags); -} + struct gk20a_instobj *node = gk20a_instobj(memory); + struct gk20a_instmem *imem = node->imem; + struct nvkm_ltc *ltc = imem->base.subdev.device->ltc; + unsigned long flags; -/* - * Use PRAMIN to read/write data and avoid coherency issues. - * PRAMIN uses the GPU path and ensures data will always be coherent. - * - * A dynamic mapping based solution would be desirable in the future, but - * the issue remains of how to maintain coherency efficiently. On ARM it is - * not easy (if possible at all?) to create uncached temporary mappings. - */ + spin_lock_irqsave(&imem->lock, flags); + + /* add ourselves to the LRU list so our CPU mapping can be freed */ + list_add_tail(&node->vaddr_node, &imem->vaddr_lru); + + spin_unlock_irqrestore(&imem->lock, flags); + + wmb(); + nvkm_ltc_invalidate(ltc); +} static u32 gk20a_instobj_rd32(struct nvkm_memory *memory, u64 offset) { struct gk20a_instobj *node = gk20a_instobj(memory); - struct gk20a_instmem *imem = node->imem; - struct nvkm_device *device = imem->base.subdev.device; - u64 base = (node->mem.offset + offset) & 0xffffff00000ULL; - u64 addr = (node->mem.offset + offset) & 0x000000fffffULL; - u32 data; - - if (unlikely(imem->addr != base)) { - nvkm_wr32(device, 0x001700, base >> 16); - imem->addr = base; - } - data = nvkm_rd32(device, 0x700000 + addr); - return data; + + return node->vaddr[offset / 4]; } static void gk20a_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data) { struct gk20a_instobj *node = gk20a_instobj(memory); - struct gk20a_instmem *imem = node->imem; - struct nvkm_device *device = imem->base.subdev.device; - u64 base = (node->mem.offset + offset) & 0xffffff00000ULL; - u64 addr = (node->mem.offset + offset) & 0x000000fffffULL; - if (unlikely(imem->addr != base)) { - nvkm_wr32(device, 0x001700, base >> 16); - imem->addr = base; - } - nvkm_wr32(device, 0x700000 + addr, data); + node->vaddr[offset / 4] = data; } static void gk20a_instobj_map(struct nvkm_memory *memory, struct nvkm_vma *vma, u64 offset) { struct gk20a_instobj *node = gk20a_instobj(memory); + nvkm_vm_map_at(vma, offset, &node->mem); } +/* + * Clear the CPU mapping of an instobj if it exists + */ static void -gk20a_instobj_dtor_dma(struct gk20a_instobj *_node) +gk20a_instobj_dtor(struct gk20a_instobj *node) +{ + struct gk20a_instmem *imem = node->imem; + struct gk20a_instobj *obj; + unsigned long flags; + + spin_lock_irqsave(&imem->lock, flags); + + if (!node->vaddr) + goto out; + + list_for_each_entry(obj, &imem->vaddr_lru, vaddr_node) { + if (obj == node) { + list_del(&obj->vaddr_node); + break; + } + } + vunmap(node->vaddr); + node->vaddr = NULL; + imem->vaddr_use -= nvkm_memory_size(&node->memory); + nvkm_debug(&imem->base.subdev, "vaddr used: %x/%x\n", + imem->vaddr_use, imem->vaddr_max); + +out: + spin_unlock_irqrestore(&imem->lock, flags); +} + +static void * +gk20a_instobj_dtor_dma(struct nvkm_memory *memory) { - struct gk20a_instobj_dma *node = (void *)_node; - struct gk20a_instmem *imem = _node->imem; + struct gk20a_instobj_dma *node = gk20a_instobj_dma(memory); + struct gk20a_instmem *imem = node->base.imem; struct device *dev = imem->base.subdev.device->dev; + gk20a_instobj_dtor(&node->base); + if (unlikely(!node->cpuaddr)) - return; + goto out; - dma_free_attrs(dev, _node->mem.size << PAGE_SHIFT, node->cpuaddr, + dma_free_attrs(dev, node->base.mem.size << PAGE_SHIFT, node->cpuaddr, node->handle, &imem->attrs); + +out: + return node; } -static void -gk20a_instobj_dtor_iommu(struct gk20a_instobj *_node) +static void * +gk20a_instobj_dtor_iommu(struct nvkm_memory *memory) { - struct gk20a_instobj_iommu *node = (void *)_node; - struct gk20a_instmem *imem = _node->imem; + struct gk20a_instobj_iommu *node = gk20a_instobj_iommu(memory); + struct gk20a_instmem *imem = node->base.imem; + struct device *dev = imem->base.subdev.device->dev; struct nvkm_mm_node *r; int i; - if (unlikely(list_empty(&_node->mem.regions))) - return; + gk20a_instobj_dtor(&node->base); - r = list_first_entry(&_node->mem.regions, struct nvkm_mm_node, + if (unlikely(list_empty(&node->base.mem.regions))) + goto out; + + r = list_first_entry(&node->base.mem.regions, struct nvkm_mm_node, rl_entry); - /* clear bit 34 to unmap pages */ - r->offset &= ~BIT(34 - imem->iommu_pgshift); + /* clear IOMMU bit to unmap pages */ + r->offset &= ~BIT(imem->iommu_bit - imem->iommu_pgshift); /* Unmap pages from GPU address space and free them */ - for (i = 0; i < _node->mem.size; i++) { + for (i = 0; i < node->base.mem.size; i++) { iommu_unmap(imem->domain, (r->offset + i) << imem->iommu_pgshift, PAGE_SIZE); + dma_unmap_page(dev, node->dma_addrs[i], PAGE_SIZE, + DMA_BIDIRECTIONAL); __free_page(node->pages[i]); } @@ -218,25 +349,27 @@ gk20a_instobj_dtor_iommu(struct gk20a_instobj *_node) mutex_lock(imem->mm_mutex); nvkm_mm_free(imem->mm, &r); mutex_unlock(imem->mm_mutex); -} - -static void * -gk20a_instobj_dtor(struct nvkm_memory *memory) -{ - struct gk20a_instobj *node = gk20a_instobj(memory); - struct gk20a_instmem *imem = node->imem; - - if (imem->domain) - gk20a_instobj_dtor_iommu(node); - else - gk20a_instobj_dtor_dma(node); +out: return node; } static const struct nvkm_memory_func -gk20a_instobj_func = { - .dtor = gk20a_instobj_dtor, +gk20a_instobj_func_dma = { + .dtor = gk20a_instobj_dtor_dma, + .target = gk20a_instobj_target, + .addr = gk20a_instobj_addr, + .size = gk20a_instobj_size, + .acquire = gk20a_instobj_acquire, + .release = gk20a_instobj_release, + .rd32 = gk20a_instobj_rd32, + .wr32 = gk20a_instobj_wr32, + .map = gk20a_instobj_map, +}; + +static const struct nvkm_memory_func +gk20a_instobj_func_iommu = { + .dtor = gk20a_instobj_dtor_iommu, .target = gk20a_instobj_target, .addr = gk20a_instobj_addr, .size = gk20a_instobj_size, @@ -259,6 +392,8 @@ gk20a_instobj_ctor_dma(struct gk20a_instmem *imem, u32 npages, u32 align, return -ENOMEM; *_node = &node->base; + nvkm_memory_ctor(&gk20a_instobj_func_dma, &node->base.memory); + node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT, &node->handle, GFP_KERNEL, &imem->attrs); @@ -292,24 +427,40 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align, { struct gk20a_instobj_iommu *node; struct nvkm_subdev *subdev = &imem->base.subdev; + struct device *dev = subdev->device->dev; struct nvkm_mm_node *r; int ret; int i; - if (!(node = kzalloc(sizeof(*node) + - sizeof( node->pages[0]) * npages, GFP_KERNEL))) + /* + * despite their variable size, instmem allocations are small enough + * (< 1 page) to be handled by kzalloc + */ + if (!(node = kzalloc(sizeof(*node) + ((sizeof(node->pages[0]) + + sizeof(*node->dma_addrs)) * npages), GFP_KERNEL))) return -ENOMEM; *_node = &node->base; + node->dma_addrs = (void *)(node->pages + npages); + + nvkm_memory_ctor(&gk20a_instobj_func_iommu, &node->base.memory); /* Allocate backing memory */ for (i = 0; i < npages; i++) { struct page *p = alloc_page(GFP_KERNEL); + dma_addr_t dma_adr; if (p == NULL) { ret = -ENOMEM; goto free_pages; } node->pages[i] = p; + dma_adr = dma_map_page(dev, p, 0, PAGE_SIZE, DMA_BIDIRECTIONAL); + if (dma_mapping_error(dev, dma_adr)) { + nvkm_error(subdev, "DMA mapping error!\n"); + ret = -ENOMEM; + goto free_pages; + } + node->dma_addrs[i] = dma_adr; } mutex_lock(imem->mm_mutex); @@ -318,16 +469,15 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align, align >> imem->iommu_pgshift, &r); mutex_unlock(imem->mm_mutex); if (ret) { - nvkm_error(subdev, "virtual space is full!\n"); + nvkm_error(subdev, "IOMMU space is full!\n"); goto free_pages; } /* Map into GPU address space */ for (i = 0; i < npages; i++) { - struct page *p = node->pages[i]; u32 offset = (r->offset + i) << imem->iommu_pgshift; - ret = iommu_map(imem->domain, offset, page_to_phys(p), + ret = iommu_map(imem->domain, offset, node->dma_addrs[i], PAGE_SIZE, IOMMU_READ | IOMMU_WRITE); if (ret < 0) { nvkm_error(subdev, "IOMMU mapping failure: %d\n", ret); @@ -340,8 +490,8 @@ gk20a_instobj_ctor_iommu(struct gk20a_instmem *imem, u32 npages, u32 align, } } - /* Bit 34 tells that an address is to be resolved through the IOMMU */ - r->offset |= BIT(34 - imem->iommu_pgshift); + /* IOMMU bit tells that an address is to be resolved through the IOMMU */ + r->offset |= BIT(imem->iommu_bit - imem->iommu_pgshift); node->base.mem.offset = ((u64)r->offset) << imem->iommu_pgshift; @@ -356,8 +506,13 @@ release_area: mutex_unlock(imem->mm_mutex); free_pages: - for (i = 0; i < npages && node->pages[i] != NULL; i++) + for (i = 0; i < npages && node->pages[i] != NULL; i++) { + dma_addr_t dma_addr = node->dma_addrs[i]; + if (dma_addr) + dma_unmap_page(dev, dma_addr, PAGE_SIZE, + DMA_BIDIRECTIONAL); __free_page(node->pages[i]); + } return ret; } @@ -367,8 +522,8 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, struct nvkm_memory **pmemory) { struct gk20a_instmem *imem = gk20a_instmem(base); - struct gk20a_instobj *node = NULL; struct nvkm_subdev *subdev = &imem->base.subdev; + struct gk20a_instobj *node = NULL; int ret; nvkm_debug(subdev, "%s (%s): size: %x align: %x\n", __func__, @@ -388,7 +543,6 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, if (ret) return ret; - nvkm_memory_ctor(&gk20a_instobj_func, &node->memory); node->imem = imem; /* present memory for being mapped using small pages */ @@ -402,15 +556,25 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero, return 0; } -static void -gk20a_instmem_fini(struct nvkm_instmem *base) +static void * +gk20a_instmem_dtor(struct nvkm_instmem *base) { - gk20a_instmem(base)->addr = ~0ULL; + struct gk20a_instmem *imem = gk20a_instmem(base); + + /* perform some sanity checks... */ + if (!list_empty(&imem->vaddr_lru)) + nvkm_warn(&base->subdev, "instobj LRU not empty!\n"); + + if (imem->vaddr_use != 0) + nvkm_warn(&base->subdev, "instobj vmap area not empty! " + "0x%x bytes still mapped\n", imem->vaddr_use); + + return imem; } static const struct nvkm_instmem_func gk20a_instmem = { - .fini = gk20a_instmem_fini, + .dtor = gk20a_instmem_dtor, .memory_new = gk20a_instobj_new, .persistent = true, .zero = false, @@ -429,23 +593,28 @@ gk20a_instmem_new(struct nvkm_device *device, int index, spin_lock_init(&imem->lock); *pimem = &imem->base; + /* do not allow more than 1MB of CPU-mapped instmem */ + imem->vaddr_use = 0; + imem->vaddr_max = 0x100000; + INIT_LIST_HEAD(&imem->vaddr_lru); + if (tdev->iommu.domain) { - imem->domain = tdev->iommu.domain; + imem->mm_mutex = &tdev->iommu.mutex; imem->mm = &tdev->iommu.mm; + imem->domain = tdev->iommu.domain; imem->iommu_pgshift = tdev->iommu.pgshift; - imem->mm_mutex = &tdev->iommu.mutex; + imem->cpu_map = gk20a_instobj_cpu_map_iommu; + imem->iommu_bit = tdev->func->iommu_bit; nvkm_info(&imem->base.subdev, "using IOMMU\n"); } else { init_dma_attrs(&imem->attrs); - /* - * We will access instmem through PRAMIN and thus do not need a - * consistent CPU pointer or kernel mapping - */ + /* We will access the memory through our own mapping */ dma_set_attr(DMA_ATTR_NON_CONSISTENT, &imem->attrs); dma_set_attr(DMA_ATTR_WEAK_ORDERING, &imem->attrs); dma_set_attr(DMA_ATTR_WRITE_COMBINE, &imem->attrs); dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &imem->attrs); + imem->cpu_map = gk20a_instobj_cpu_map_dma; nvkm_info(&imem->base.subdev, "using DMA API\n"); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c index 930d25b6e63c..85b1464c0194 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c @@ -67,6 +67,20 @@ nvkm_ltc_zbc_depth_get(struct nvkm_ltc *ltc, int index, const u32 depth) return index; } +void +nvkm_ltc_invalidate(struct nvkm_ltc *ltc) +{ + if (ltc->func->invalidate) + ltc->func->invalidate(ltc); +} + +void +nvkm_ltc_flush(struct nvkm_ltc *ltc) +{ + if (ltc->func->flush) + ltc->func->flush(ltc); +} + static void nvkm_ltc_intr(struct nvkm_subdev *subdev) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c index 45ac765b753e..fb0de83da13c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c @@ -122,6 +122,36 @@ gf100_ltc_intr(struct nvkm_ltc *ltc) } } +void +gf100_ltc_invalidate(struct nvkm_ltc *ltc) +{ + struct nvkm_device *device = ltc->subdev.device; + s64 taken; + + nvkm_wr32(device, 0x70004, 0x00000001); + taken = nvkm_wait_msec(device, 2, 0x70004, 0x00000003, 0x00000000); + if (taken < 0) + nvkm_warn(<c->subdev, "LTC invalidate timeout\n"); + + if (taken > 0) + nvkm_debug(<c->subdev, "LTC invalidate took %lld ns\n", taken); +} + +void +gf100_ltc_flush(struct nvkm_ltc *ltc) +{ + struct nvkm_device *device = ltc->subdev.device; + s64 taken; + + nvkm_wr32(device, 0x70010, 0x00000001); + taken = nvkm_wait_msec(device, 2, 0x70010, 0x00000003, 0x00000000); + if (taken < 0) + nvkm_warn(<c->subdev, "LTC flush timeout\n"); + + if (taken > 0) + nvkm_debug(<c->subdev, "LTC flush took %lld ns\n", taken); +} + /* TODO: Figure out tag memory details and drop the over-cautious allocation. */ int @@ -215,6 +245,8 @@ gf100_ltc = { .zbc = 16, .zbc_clear_color = gf100_ltc_zbc_clear_color, .zbc_clear_depth = gf100_ltc_zbc_clear_depth, + .invalidate = gf100_ltc_invalidate, + .flush = gf100_ltc_flush, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c index 839e6b4c597b..b4f6e0034d58 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c @@ -45,6 +45,8 @@ gk104_ltc = { .zbc = 16, .zbc_clear_color = gf100_ltc_zbc_clear_color, .zbc_clear_depth = gf100_ltc_zbc_clear_depth, + .invalidate = gf100_ltc_invalidate, + .flush = gf100_ltc_flush, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c index 389331bb63ba..3043bbfd7384 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c @@ -138,6 +138,8 @@ gm107_ltc = { .zbc = 16, .zbc_clear_color = gm107_ltc_zbc_clear_color, .zbc_clear_depth = gm107_ltc_zbc_clear_depth, + .invalidate = gf100_ltc_invalidate, + .flush = gf100_ltc_flush, }; int diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h index 4e05037cc99f..4e3755b82769 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h @@ -17,6 +17,9 @@ struct nvkm_ltc_func { int zbc; void (*zbc_clear_color)(struct nvkm_ltc *, int, const u32[4]); void (*zbc_clear_depth)(struct nvkm_ltc *, int, const u32); + + void (*invalidate)(struct nvkm_ltc *); + void (*flush)(struct nvkm_ltc *); }; int gf100_ltc_oneinit(struct nvkm_ltc *); @@ -26,4 +29,6 @@ void gf100_ltc_cbc_clear(struct nvkm_ltc *, u32, u32); void gf100_ltc_cbc_wait(struct nvkm_ltc *); void gf100_ltc_zbc_clear_color(struct nvkm_ltc *, int, const u32[4]); void gf100_ltc_zbc_clear_depth(struct nvkm_ltc *, int, const u32); +void gf100_ltc_invalidate(struct nvkm_ltc *); +void gf100_ltc_flush(struct nvkm_ltc *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild index 99672c3d0bad..4476ef75acd6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild @@ -2,6 +2,8 @@ nvkm-y += nvkm/subdev/pci/agp.o nvkm-y += nvkm/subdev/pci/base.o nvkm-y += nvkm/subdev/pci/nv04.o nvkm-y += nvkm/subdev/pci/nv40.o +nvkm-y += nvkm/subdev/pci/nv46.o nvkm-y += nvkm/subdev/pci/nv4c.o -nvkm-y += nvkm/subdev/pci/nv50.o +nvkm-y += nvkm/subdev/pci/g84.o +nvkm-y += nvkm/subdev/pci/g94.o nvkm-y += nvkm/subdev/pci/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c index 814cb51cc873..385a90f91ed6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.c @@ -35,6 +35,8 @@ static const struct nvkm_device_agp_quirk nvkm_device_agp_quirks[] = { /* VIA Apollo PRO133x / GeForce FX 5600 Ultra - fdo#20341 */ { PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_NVIDIA, 0x0311, 2 }, + /* SiS 761 does not support AGP cards, use PCI mode */ + { PCI_VENDOR_ID_SI, 0x0761, PCI_ANY_ID, PCI_ANY_ID, 0 }, {}, }; @@ -137,8 +139,10 @@ nvkm_agp_ctor(struct nvkm_pci *pci) while (quirk->hostbridge_vendor) { if (info.device->vendor == quirk->hostbridge_vendor && info.device->device == quirk->hostbridge_device && - pci->pdev->vendor == quirk->chip_vendor && - pci->pdev->device == quirk->chip_device) { + (quirk->chip_vendor == (u16)PCI_ANY_ID || + pci->pdev->vendor == quirk->chip_vendor) && + (quirk->chip_device == (u16)PCI_ANY_ID || + pci->pdev->device == quirk->chip_device)) { nvkm_info(subdev, "forcing default agp mode to %dX, " "use NvAGP=<mode> to override\n", quirk->mode); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c index d1c148e51922..d671dcfaff3c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.c @@ -46,6 +46,14 @@ nvkm_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data) pci->func->wr32(pci, addr, data); } +u32 +nvkm_pci_mask(struct nvkm_pci *pci, u16 addr, u32 mask, u32 value) +{ + u32 data = pci->func->rd32(pci, addr); + pci->func->wr32(pci, addr, (data & ~mask) | value); + return data; +} + void nvkm_pci_rom_shadow(struct nvkm_pci *pci, bool shadow) { @@ -111,6 +119,9 @@ nvkm_pci_init(struct nvkm_subdev *subdev) return ret; } + if (pci->func->init) + pci->func->init(pci); + ret = request_irq(pdev->irq, nvkm_pci_intr, IRQF_SHARED, "nvkm", pci); if (ret) return ret; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c new file mode 100644 index 000000000000..3faa6bfb895b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.c @@ -0,0 +1,64 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +#include <core/pci.h> + +void +g84_pci_init(struct nvkm_pci *pci) +{ + /* The following only concerns PCIe cards. */ + if (!pci_is_pcie(pci->pdev)) + return; + + /* Tag field is 8-bit long, regardless of EXT_TAG. + * However, if EXT_TAG is disabled, only the lower 5 bits of the tag + * field should be used, limiting the number of request to 32. + * + * Apparently, 0x041c stores some limit on the number of requests + * possible, so if EXT_TAG is disabled, limit that requests number to + * 32 + * + * Fixes fdo#86537 + */ + if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020) + nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100); + else + nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000); +} + +static const struct nvkm_pci_func +g84_pci_func = { + .init = g84_pci_init, + .rd32 = nv40_pci_rd32, + .wr08 = nv40_pci_wr08, + .wr32 = nv40_pci_wr32, + .msi_rearm = nv46_pci_msi_rearm, +}; + +int +g84_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +{ + return nvkm_pci_new_(&g84_pci_func, device, index, ppci); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c new file mode 100644 index 000000000000..cd311ee311cc --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c @@ -0,0 +1,39 @@ +/* + * Copyright 2015 Red Hat Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Ben Skeggs <bskeggs@redhat.com> + */ +#include "priv.h" + +static const struct nvkm_pci_func +g94_pci_func = { + .init = g84_pci_init, + .rd32 = nv40_pci_rd32, + .wr08 = nv40_pci_wr08, + .wr32 = nv40_pci_wr32, + .msi_rearm = nv40_pci_msi_rearm, +}; + +int +g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +{ + return nvkm_pci_new_(&g94_pci_func, device, index, ppci); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c index 86f8226532d3..25e1ae70867f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.c @@ -31,6 +31,7 @@ gf100_pci_msi_rearm(struct nvkm_pci *pci) static const struct nvkm_pci_func gf100_pci_func = { + .init = g84_pci_init, .rd32 = nv40_pci_rd32, .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c index 090a187f165f..6eb417765802 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.c @@ -44,7 +44,7 @@ nv40_pci_wr32(struct nvkm_pci *pci, u16 addr, u32 data) nvkm_wr32(device, 0x088000 + addr, data); } -static void +void nv40_pci_msi_rearm(struct nvkm_pci *pci) { nvkm_pci_wr08(pci, 0x0068, 0xff); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c index 3e167d4a381f..fc617e4c0ab6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.c @@ -25,11 +25,11 @@ #include <core/pci.h> -/* MSI re-arm through the PRI appears to be broken on the original G80, +/* MSI re-arm through the PRI appears to be broken on NV46/NV50/G84/G86/G92, * so we access it via alternate PCI config space mechanisms. */ -static void -nv50_pci_msi_rearm(struct nvkm_pci *pci) +void +nv46_pci_msi_rearm(struct nvkm_pci *pci) { struct nvkm_device *device = pci->subdev.device; struct pci_dev *pdev = device->func->pci(device)->pdev; @@ -37,15 +37,15 @@ nv50_pci_msi_rearm(struct nvkm_pci *pci) } static const struct nvkm_pci_func -nv50_pci_func = { +nv46_pci_func = { .rd32 = nv40_pci_rd32, .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, - .msi_rearm = nv50_pci_msi_rearm, + .msi_rearm = nv46_pci_msi_rearm, }; int -nv50_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) +nv46_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci) { - return nvkm_pci_new_(&nv50_pci_func, device, index, ppci); + return nvkm_pci_new_(&nv46_pci_func, device, index, ppci); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h index d22c2c117106..cf46d38d0b0a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pci/priv.h @@ -7,6 +7,7 @@ int nvkm_pci_new_(const struct nvkm_pci_func *, struct nvkm_device *, int index, struct nvkm_pci **); struct nvkm_pci_func { + void (*init)(struct nvkm_pci *); u32 (*rd32)(struct nvkm_pci *, u16 addr); void (*wr08)(struct nvkm_pci *, u16 addr, u8 data); void (*wr32)(struct nvkm_pci *, u16 addr, u32 data); @@ -16,4 +17,9 @@ struct nvkm_pci_func { u32 nv40_pci_rd32(struct nvkm_pci *, u16); void nv40_pci_wr08(struct nvkm_pci *, u16, u8); void nv40_pci_wr32(struct nvkm_pci *, u16, u32); +void nv40_pci_msi_rearm(struct nvkm_pci *); + +void nv46_pci_msi_rearm(struct nvkm_pci *); + +void g84_pci_init(struct nvkm_pci *pci); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index 27a79c0c3888..d95eb8659d1b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -28,7 +28,7 @@ void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) { - if (pmu->func->pgob) + if (pmu && pmu->func->pgob) pmu->func->pgob(pmu, enable); } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c index e33f5c03b9ac..d942fa7b9f18 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.c @@ -27,6 +27,7 @@ #include "fuc/gf119.fuc4.h" #include <core/option.h> +#include <subdev/fuse.h> #include <subdev/timer.h> static void @@ -57,6 +58,9 @@ gk104_pmu_pgob(struct nvkm_pmu *pmu, bool enable) { struct nvkm_device *device = pmu->subdev.device; + if (!(nvkm_fuse_read(device->fuse, 0x31c) & 0x00000001)) + return; + nvkm_mask(device, 0x000200, 0x00001000, 0x00000000); nvkm_rd32(device, 0x000200); nvkm_mask(device, 0x000200, 0x08000000, 0x08000000); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild index 6b46ff4213a3..b035c6e28be8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/Kbuild @@ -1,4 +1,5 @@ nvkm-y += nvkm/subdev/volt/base.o nvkm-y += nvkm/subdev/volt/gpio.o nvkm-y += nvkm/subdev/volt/nv40.o +nvkm-y += nvkm/subdev/volt/gk104.o nvkm-y += nvkm/subdev/volt/gk20a.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c index 4752dbd33923..50b5649ad1a4 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.c @@ -30,7 +30,12 @@ int nvkm_volt_get(struct nvkm_volt *volt) { - int ret = volt->func->vid_get(volt), i; + int ret, i; + + if (volt->func->volt_get) + return volt->func->volt_get(volt); + + ret = volt->func->vid_get(volt); if (ret >= 0) { for (i = 0; i < volt->vid_nr; i++) { if (volt->vid[i].vid == ret) @@ -46,6 +51,10 @@ nvkm_volt_set(struct nvkm_volt *volt, u32 uv) { struct nvkm_subdev *subdev = &volt->subdev; int i, ret = -EINVAL; + + if (volt->func->volt_set) + return volt->func->volt_set(volt, uv); + for (i = 0; i < volt->vid_nr; i++) { if (volt->vid[i].uv == uv) { ret = volt->func->vid_set(volt, volt->vid[i].vid); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c new file mode 100644 index 000000000000..b61509e26ec9 --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.c @@ -0,0 +1,119 @@ +/* + * Copyright 2015 Martin Peres + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Martin Peres + */ +#include "priv.h" + +#include <subdev/volt.h> +#include <subdev/gpio.h> +#include <subdev/bios.h> +#include <subdev/bios/volt.h> + +#define gk104_volt(p) container_of((p), struct gk104_volt, base) +struct gk104_volt { + struct nvkm_volt base; + struct nvbios_volt bios; +}; + +int +gk104_volt_get(struct nvkm_volt *base) +{ + struct nvbios_volt *bios = &gk104_volt(base)->bios; + struct nvkm_device *device = base->subdev.device; + u32 div, duty; + + div = nvkm_rd32(device, 0x20340); + duty = nvkm_rd32(device, 0x20344); + + return bios->base + bios->pwm_range * duty / div; +} + +int +gk104_volt_set(struct nvkm_volt *base, u32 uv) +{ + struct nvbios_volt *bios = &gk104_volt(base)->bios; + struct nvkm_device *device = base->subdev.device; + u32 div, duty; + + /* the blob uses this crystal frequency, let's use it too. */ + div = 27648000 / bios->pwm_freq; + duty = (uv - bios->base) * div / bios->pwm_range; + + nvkm_wr32(device, 0x20340, div); + nvkm_wr32(device, 0x20344, 0x8000000 | duty); + + return 0; +} + +static const struct nvkm_volt_func +gk104_volt_pwm = { + .volt_get = gk104_volt_get, + .volt_set = gk104_volt_set, +}, gk104_volt_gpio = { + .vid_get = nvkm_voltgpio_get, + .vid_set = nvkm_voltgpio_set, +}; + +int +gk104_volt_new(struct nvkm_device *device, int index, struct nvkm_volt **pvolt) +{ + const struct nvkm_volt_func *volt_func = &gk104_volt_gpio; + struct dcb_gpio_func gpio; + struct nvbios_volt bios; + struct gk104_volt *volt; + u8 ver, hdr, cnt, len; + const char *mode; + + if (!nvbios_volt_parse(device->bios, &ver, &hdr, &cnt, &len, &bios)) + return 0; + + if (!nvkm_gpio_find(device->gpio, 0, DCB_GPIO_VID_PWM, 0xff, &gpio) && + bios.type == NVBIOS_VOLT_PWM) { + volt_func = &gk104_volt_pwm; + } + + if (!(volt = kzalloc(sizeof(*volt), GFP_KERNEL))) + return -ENOMEM; + nvkm_volt_ctor(volt_func, device, index, &volt->base); + *pvolt = &volt->base; + volt->bios = bios; + + /* now that we have a subdev, we can show an error if we found through + * the voltage table that we were supposed to use the PWN mode but we + * did not find the right GPIO for it. + */ + if (bios.type == NVBIOS_VOLT_PWM && volt_func != &gk104_volt_pwm) { + nvkm_error(&volt->base.subdev, + "Type mismatch between the voltage table type and " + "the GPIO table. Fallback to GPIO mode.\n"); + } + + if (volt_func == &gk104_volt_gpio) { + nvkm_voltgpio_init(&volt->base); + mode = "GPIO"; + } else + mode = "PWM"; + + nvkm_debug(&volt->base.subdev, "Using %s mode\n", mode); + + return 0; +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h index 394f37c723af..d5140d991161 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/volt/priv.h @@ -9,6 +9,8 @@ int nvkm_volt_new_(const struct nvkm_volt_func *, struct nvkm_device *, int index, struct nvkm_volt **); struct nvkm_volt_func { + int (*volt_get)(struct nvkm_volt *); + int (*volt_set)(struct nvkm_volt *, u32 uv); int (*vid_get)(struct nvkm_volt *); int (*vid_set)(struct nvkm_volt *, u8 vid); int (*set_id)(struct nvkm_volt *, u8 id, int condition); @@ -17,4 +19,8 @@ struct nvkm_volt_func { int nvkm_voltgpio_init(struct nvkm_volt *); int nvkm_voltgpio_get(struct nvkm_volt *); int nvkm_voltgpio_set(struct nvkm_volt *, u8); + +int nvkm_voltpwm_init(struct nvkm_volt *volt); +int nvkm_voltpwm_get(struct nvkm_volt *volt); +int nvkm_voltpwm_set(struct nvkm_volt *volt, u32 uv); #endif diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c index 9a4ba4f03567..ad09590e8a46 100644 --- a/drivers/gpu/drm/omapdrm/omap_crtc.c +++ b/drivers/gpu/drm/omapdrm/omap_crtc.c @@ -412,9 +412,6 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, dispc_mgr_go(omap_crtc->channel); omap_irq_register(crtc->dev, &omap_crtc->vblank_irq); } - - crtc->invert_dimensions = !!(crtc->primary->state->rotation & - (BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270))); } static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c index d685e23449ce..5c6609cbb6a2 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.c +++ b/drivers/gpu/drm/omapdrm/omap_drv.c @@ -626,12 +626,12 @@ static int ioctl_gem_info(struct drm_device *dev, void *data, } static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = { - DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_UNLOCKED|DRM_AUTH), - DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH), - DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH), - DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH), - DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH), + DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_AUTH), + DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_AUTH), + DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_AUTH), + DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_AUTH), + DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_AUTH), }; /* @@ -839,7 +839,7 @@ static struct drm_driver omap_drm_driver = { .preclose = dev_preclose, .postclose = dev_postclose, .set_busid = drm_platform_set_busid, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = omap_irq_enable_vblank, .disable_vblank = omap_irq_disable_vblank, #ifdef CONFIG_DEBUG_FS diff --git a/drivers/gpu/drm/omapdrm/omap_drv.h b/drivers/gpu/drm/omapdrm/omap_drv.h index 12081e61d45a..5c367aad8a6e 100644 --- a/drivers/gpu/drm/omapdrm/omap_drv.h +++ b/drivers/gpu/drm/omapdrm/omap_drv.h @@ -129,8 +129,8 @@ void omap_gem_describe_objects(struct list_head *list, struct seq_file *m); int omap_gem_resume(struct device *dev); #endif -int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id); -void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id); +int omap_irq_enable_vblank(struct drm_device *dev, unsigned int pipe); +void omap_irq_disable_vblank(struct drm_device *dev, unsigned int pipe); void __omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); void __omap_irq_unregister(struct drm_device *dev, struct omap_drm_irq *irq); void omap_irq_register(struct drm_device *dev, struct omap_drm_irq *irq); diff --git a/drivers/gpu/drm/omapdrm/omap_fb.c b/drivers/gpu/drm/omapdrm/omap_fb.c index 51b1219af87f..636a1f921569 100644 --- a/drivers/gpu/drm/omapdrm/omap_fb.c +++ b/drivers/gpu/drm/omapdrm/omap_fb.c @@ -171,7 +171,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, uint32_t w = win->src_w; uint32_t h = win->src_h; - switch (win->rotation & 0xf) { + switch (win->rotation & DRM_ROTATE_MASK) { default: dev_err(fb->dev->dev, "invalid rotation: %02x", (uint32_t)win->rotation); @@ -209,7 +209,7 @@ void omap_framebuffer_update_scanout(struct drm_framebuffer *fb, info->rotation_type = OMAP_DSS_ROT_TILER; info->screen_width = omap_gem_tiled_stride(plane->bo, orient); } else { - switch (win->rotation & 0xf) { + switch (win->rotation & DRM_ROTATE_MASK) { case 0: case BIT(DRM_ROTATE_0): /* OK */ diff --git a/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c b/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c index 0cc71c9d08d5..27c297672076 100644 --- a/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c +++ b/drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c @@ -140,15 +140,12 @@ static int omap_gem_dmabuf_mmap(struct dma_buf *buffer, struct vm_area_struct *vma) { struct drm_gem_object *obj = buffer->priv; - struct drm_device *dev = obj->dev; int ret = 0; if (WARN_ON(!obj->filp)) return -EINVAL; - mutex_lock(&dev->struct_mutex); ret = drm_gem_mmap_obj(obj, omap_gem_mmap_size(obj), vma); - mutex_unlock(&dev->struct_mutex); if (ret < 0) return ret; diff --git a/drivers/gpu/drm/omapdrm/omap_irq.c b/drivers/gpu/drm/omapdrm/omap_irq.c index 249c0330d6ce..60e1e8016708 100644 --- a/drivers/gpu/drm/omapdrm/omap_irq.c +++ b/drivers/gpu/drm/omapdrm/omap_irq.c @@ -134,7 +134,7 @@ int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, /** * enable_vblank - enable vblank interrupt events * @dev: DRM device - * @crtc: which irq to enable + * @pipe: which irq to enable * * Enable vblank interrupts for @crtc. If the device doesn't have * a hardware vblank counter, this routine should be a no-op, since @@ -144,13 +144,13 @@ int omap_irq_wait(struct drm_device *dev, struct omap_irq_wait *wait, * Zero on success, appropriate errno if the given @crtc's vblank * interrupt cannot be enabled. */ -int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id) +int omap_irq_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct omap_drm_private *priv = dev->dev_private; - struct drm_crtc *crtc = priv->crtcs[crtc_id]; + struct drm_crtc *crtc = priv->crtcs[pipe]; unsigned long flags; - DBG("dev=%p, crtc=%d", dev, crtc_id); + DBG("dev=%p, crtc=%u", dev, pipe); spin_lock_irqsave(&list_lock, flags); priv->vblank_mask |= pipe2vbl(crtc); @@ -163,19 +163,19 @@ int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id) /** * disable_vblank - disable vblank interrupt events * @dev: DRM device - * @crtc: which irq to enable + * @pipe: which irq to enable * * Disable vblank interrupts for @crtc. If the device doesn't have * a hardware vblank counter, this routine should be a no-op, since * interrupts will have to stay on to keep the count accurate. */ -void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id) +void omap_irq_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct omap_drm_private *priv = dev->dev_private; - struct drm_crtc *crtc = priv->crtcs[crtc_id]; + struct drm_crtc *crtc = priv->crtcs[pipe]; unsigned long flags; - DBG("dev=%p, crtc=%d", dev, crtc_id); + DBG("dev=%p, crtc=%u", dev, pipe); spin_lock_irqsave(&list_lock, flags); priv->vblank_mask &= ~pipe2vbl(crtc); diff --git a/drivers/gpu/drm/omapdrm/omap_plane.c b/drivers/gpu/drm/omapdrm/omap_plane.c index 09e363bb55f2..3054bda72688 100644 --- a/drivers/gpu/drm/omapdrm/omap_plane.c +++ b/drivers/gpu/drm/omapdrm/omap_plane.c @@ -108,7 +108,7 @@ static void omap_plane_atomic_update(struct drm_plane *plane, win.src_x = state->src_x >> 16; win.src_y = state->src_y >> 16; - switch (state->rotation & 0xf) { + switch (state->rotation & DRM_ROTATE_MASK) { case BIT(DRM_ROTATE_90): case BIT(DRM_ROTATE_270): win.src_w = state->src_h >> 16; diff --git a/drivers/gpu/drm/qxl/qxl_display.c b/drivers/gpu/drm/qxl/qxl_display.c index dd845f82cc24..183aea1abebc 100644 --- a/drivers/gpu/drm/qxl/qxl_display.c +++ b/drivers/gpu/drm/qxl/qxl_display.c @@ -244,6 +244,10 @@ static int qxl_crtc_page_flip(struct drm_crtc *crtc, ret = qxl_bo_reserve(bo, false); if (ret) return ret; + ret = qxl_bo_pin(bo, bo->type, NULL); + qxl_bo_unreserve(bo); + if (ret) + return ret; qxl_draw_dirty_fb(qdev, qfb_src, bo, 0, 0, &norect, one_clip_rect, inc); @@ -257,7 +261,11 @@ static int qxl_crtc_page_flip(struct drm_crtc *crtc, } drm_vblank_put(dev, qcrtc->index); - qxl_bo_unreserve(bo); + ret = qxl_bo_reserve(bo, false); + if (!ret) { + qxl_bo_unpin(bo); + qxl_bo_unreserve(bo); + } return 0; } @@ -618,7 +626,7 @@ static int qxl_crtc_mode_set(struct drm_crtc *crtc, adjusted_mode->hdisplay, adjusted_mode->vdisplay); - if (qcrtc->index == 0) + if (bo->is_primary == false) recreate_primary = true; if (bo->surf.stride * bo->surf.height > qdev->vram_size) { diff --git a/drivers/gpu/drm/qxl/qxl_drv.c b/drivers/gpu/drm/qxl/qxl_drv.c index 83f6f0b5e9ef..7307b07fe06b 100644 --- a/drivers/gpu/drm/qxl/qxl_drv.c +++ b/drivers/gpu/drm/qxl/qxl_drv.c @@ -196,17 +196,18 @@ static int qxl_pm_restore(struct device *dev) return qxl_drm_resume(drm_dev, false); } -static u32 qxl_noop_get_vblank_counter(struct drm_device *dev, int crtc) +static u32 qxl_noop_get_vblank_counter(struct drm_device *dev, + unsigned int pipe) { return 0; } -static int qxl_noop_enable_vblank(struct drm_device *dev, int crtc) +static int qxl_noop_enable_vblank(struct drm_device *dev, unsigned int pipe) { return 0; } -static void qxl_noop_disable_vblank(struct drm_device *dev, int crtc) +static void qxl_noop_disable_vblank(struct drm_device *dev, unsigned int pipe) { } diff --git a/drivers/gpu/drm/qxl/qxl_fb.c b/drivers/gpu/drm/qxl/qxl_fb.c index 41c422fee31a..c4a552637c93 100644 --- a/drivers/gpu/drm/qxl/qxl_fb.c +++ b/drivers/gpu/drm/qxl/qxl_fb.c @@ -144,14 +144,17 @@ static void qxl_dirty_update(struct qxl_fbdev *qfbdev, spin_lock_irqsave(&qfbdev->dirty.lock, flags); - if (qfbdev->dirty.y1 < y) - y = qfbdev->dirty.y1; - if (qfbdev->dirty.y2 > y2) - y2 = qfbdev->dirty.y2; - if (qfbdev->dirty.x1 < x) - x = qfbdev->dirty.x1; - if (qfbdev->dirty.x2 > x2) - x2 = qfbdev->dirty.x2; + if ((qfbdev->dirty.y2 - qfbdev->dirty.y1) && + (qfbdev->dirty.x2 - qfbdev->dirty.x1)) { + if (qfbdev->dirty.y1 < y) + y = qfbdev->dirty.y1; + if (qfbdev->dirty.y2 > y2) + y2 = qfbdev->dirty.y2; + if (qfbdev->dirty.x1 < x) + x = qfbdev->dirty.x1; + if (qfbdev->dirty.x2 > x2) + x2 = qfbdev->dirty.x2; + } qfbdev->dirty.x1 = x; qfbdev->dirty.x2 = x2; diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c index bda5c5f80c24..2ae8577497ca 100644 --- a/drivers/gpu/drm/qxl/qxl_ioctl.c +++ b/drivers/gpu/drm/qxl/qxl_ioctl.c @@ -422,21 +422,21 @@ static int qxl_alloc_surf_ioctl(struct drm_device *dev, void *data, } const struct drm_ioctl_desc qxl_ioctls[] = { - DRM_IOCTL_DEF_DRV(QXL_ALLOC, qxl_alloc_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(QXL_ALLOC, qxl_alloc_ioctl, DRM_AUTH), - DRM_IOCTL_DEF_DRV(QXL_MAP, qxl_map_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(QXL_MAP, qxl_map_ioctl, DRM_AUTH), DRM_IOCTL_DEF_DRV(QXL_EXECBUFFER, qxl_execbuffer_ioctl, - DRM_AUTH|DRM_UNLOCKED), + DRM_AUTH), DRM_IOCTL_DEF_DRV(QXL_UPDATE_AREA, qxl_update_area_ioctl, - DRM_AUTH|DRM_UNLOCKED), + DRM_AUTH), DRM_IOCTL_DEF_DRV(QXL_GETPARAM, qxl_getparam_ioctl, - DRM_AUTH|DRM_UNLOCKED), + DRM_AUTH), DRM_IOCTL_DEF_DRV(QXL_CLIENTCAP, qxl_clientcap_ioctl, - DRM_AUTH|DRM_UNLOCKED), + DRM_AUTH), DRM_IOCTL_DEF_DRV(QXL_ALLOC_SURF, qxl_alloc_surf_ioctl, - DRM_AUTH|DRM_UNLOCKED), + DRM_AUTH), }; int qxl_max_ioctls = ARRAY_SIZE(qxl_ioctls); diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c index b66ec331c17c..4efa8e261baf 100644 --- a/drivers/gpu/drm/qxl/qxl_release.c +++ b/drivers/gpu/drm/qxl/qxl_release.c @@ -307,7 +307,7 @@ int qxl_alloc_surface_release_reserved(struct qxl_device *qdev, idr_ret = qxl_release_alloc(qdev, QXL_RELEASE_SURFACE_CMD, release); if (idr_ret < 0) return idr_ret; - bo = qxl_bo_ref(to_qxl_bo(entry->tv.bo)); + bo = to_qxl_bo(entry->tv.bo); (*release)->release_offset = create_rel->release_offset + 64; @@ -316,8 +316,6 @@ int qxl_alloc_surface_release_reserved(struct qxl_device *qdev, info = qxl_release_map(qdev, *release); info->id = idr_ret; qxl_release_unmap(qdev, *release, info); - - qxl_bo_unref(&bo); return 0; } diff --git a/drivers/gpu/drm/r128/r128_cce.c b/drivers/gpu/drm/r128/r128_cce.c index 2c45ac9c1dc3..14fd83b5f497 100644 --- a/drivers/gpu/drm/r128/r128_cce.c +++ b/drivers/gpu/drm/r128/r128_cce.c @@ -311,7 +311,7 @@ static void r128_cce_init_ring_buffer(struct drm_device *dev, /* The manual (p. 2) says this address is in "VM space". This * means it's an offset from the start of AGP space. */ -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (!dev_priv->is_pci) ring_start = dev_priv->cce_ring->offset - dev->agp->base; else @@ -505,7 +505,7 @@ static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init) (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (!dev_priv->is_pci) { drm_legacy_ioremap_wc(dev_priv->cce_ring, dev); drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev); @@ -529,7 +529,7 @@ static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init) (void *)(unsigned long)dev->agp_buffer_map->offset; } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (!dev_priv->is_pci) dev_priv->cce_buffers_offset = dev->agp->base; else @@ -552,7 +552,7 @@ static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init) dev_priv->sarea_priv->last_dispatch = 0; R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->is_pci) { #endif dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); @@ -568,7 +568,7 @@ static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init) return -ENOMEM; } R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) } #endif @@ -600,7 +600,7 @@ int r128_do_cleanup_cce(struct drm_device *dev) if (dev->dev_private) { drm_r128_private_t *dev_priv = dev->dev_private; -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (!dev_priv->is_pci) { if (dev_priv->cce_ring != NULL) drm_legacy_ioremapfree(dev_priv->cce_ring, dev); diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h index 723e5d6f10a4..09143b840482 100644 --- a/drivers/gpu/drm/r128/r128_drv.h +++ b/drivers/gpu/drm/r128/r128_drv.h @@ -154,9 +154,9 @@ extern int r128_wait_ring(drm_r128_private_t *dev_priv, int n); extern int r128_do_cce_idle(drm_r128_private_t *dev_priv); extern int r128_do_cleanup_cce(struct drm_device *dev); -extern int r128_enable_vblank(struct drm_device *dev, int crtc); -extern void r128_disable_vblank(struct drm_device *dev, int crtc); -extern u32 r128_get_vblank_counter(struct drm_device *dev, int crtc); +extern int r128_enable_vblank(struct drm_device *dev, unsigned int pipe); +extern void r128_disable_vblank(struct drm_device *dev, unsigned int pipe); +extern u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe); extern irqreturn_t r128_driver_irq_handler(int irq, void *arg); extern void r128_driver_irq_preinstall(struct drm_device *dev); extern int r128_driver_irq_postinstall(struct drm_device *dev); diff --git a/drivers/gpu/drm/r128/r128_irq.c b/drivers/gpu/drm/r128/r128_irq.c index c2ae496babb7..9730f4918944 100644 --- a/drivers/gpu/drm/r128/r128_irq.c +++ b/drivers/gpu/drm/r128/r128_irq.c @@ -34,11 +34,11 @@ #include <drm/r128_drm.h> #include "r128_drv.h" -u32 r128_get_vblank_counter(struct drm_device *dev, int crtc) +u32 r128_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { const drm_r128_private_t *dev_priv = dev->dev_private; - if (crtc != 0) + if (pipe != 0) return 0; return atomic_read(&dev_priv->vbl_received); @@ -62,12 +62,12 @@ irqreturn_t r128_driver_irq_handler(int irq, void *arg) return IRQ_NONE; } -int r128_enable_vblank(struct drm_device *dev, int crtc) +int r128_enable_vblank(struct drm_device *dev, unsigned int pipe) { drm_r128_private_t *dev_priv = dev->dev_private; - if (crtc != 0) { - DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); + if (pipe != 0) { + DRM_ERROR("%s: bad crtc %u\n", __func__, pipe); return -EINVAL; } @@ -75,10 +75,10 @@ int r128_enable_vblank(struct drm_device *dev, int crtc) return 0; } -void r128_disable_vblank(struct drm_device *dev, int crtc) +void r128_disable_vblank(struct drm_device *dev, unsigned int pipe) { - if (crtc != 0) - DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); + if (pipe != 0) + DRM_ERROR("%s: bad crtc %u\n", __func__, pipe); /* * FIXME: implement proper interrupt disable by using the vblank diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c index c3872598b85a..65adb9c72377 100644 --- a/drivers/gpu/drm/radeon/atombios_encoders.c +++ b/drivers/gpu/drm/radeon/atombios_encoders.c @@ -1624,8 +1624,9 @@ radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode) } else atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { - args.ucAction = ATOM_LCD_BLON; - atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); + struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; + + atombios_set_backlight_level(radeon_encoder, dig->backlight_level); } break; case DRM_MODE_DPMS_STANDBY: @@ -1706,8 +1707,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0); } if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) - atombios_dig_transmitter_setup(encoder, - ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0); + atombios_set_backlight_level(radeon_encoder, dig->backlight_level); if (ext_encoder) atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE); break; diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c index 98d009e154bf..9fec4d09f383 100644 --- a/drivers/gpu/drm/radeon/cayman_blit_shaders.c +++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c @@ -32,7 +32,7 @@ * evergreen cards need to use the 3D engine to blit data which requires * quite a bit of hw state setup. Rather than pull the whole 3D driver * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The regsiter state and shaders + * statically generated state tables. The register state and shaders * were hand generated to support blitting functionality. See the 3D * driver or documentation for descriptions of the registers and * shader instructions. diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 0acde1949c18..7f33767d7ed6 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -1404,44 +1404,20 @@ void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) * @crtc_id: crtc to cleanup pageflip on * @crtc_base: new address of the crtc (GPU MC address) * - * Does the actual pageflip (evergreen+). - * During vblank we take the crtc lock and wait for the update_pending - * bit to go high, when it does, we release the lock, and allow the - * double buffered update to take place. - * Returns the current update pending status. + * Triggers the actual pageflip by updating the primary + * surface base address (evergreen+). */ void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) { struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; - u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); - int i; - - /* Lock the graphics update lock */ - tmp |= EVERGREEN_GRPH_UPDATE_LOCK; - WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); /* update the scanout addresses */ - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, - upper_32_bits(crtc_base)); - WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, - (u32)crtc_base); - WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, upper_32_bits(crtc_base)); WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, (u32)crtc_base); - - /* Wait for update_pending to go high. */ - for (i = 0; i < rdev->usec_timeout; i++) { - if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) - break; - udelay(1); - } - DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); - - /* Unlock the lock, so double-buffering can take place inside vblank */ - tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; - WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); + /* post the write */ + RREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset); } /** diff --git a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c index d43383470cdf..1a96ddb3e5ed 100644 --- a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c +++ b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c @@ -32,7 +32,7 @@ * evergreen cards need to use the 3D engine to blit data which requires * quite a bit of hw state setup. Rather than pull the whole 3D driver * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The regsiter state and shaders + * statically generated state tables. The register state and shaders * were hand generated to support blitting functionality. See the 3D * driver or documentation for descriptions of the registers and * shader instructions. diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c index c9e0fbbf76a3..46f87d4aaf31 100644 --- a/drivers/gpu/drm/radeon/evergreen_cs.c +++ b/drivers/gpu/drm/radeon/evergreen_cs.c @@ -34,6 +34,8 @@ #define MAX(a,b) (((a)>(b))?(a):(b)) #define MIN(a,b) (((a)<(b))?(a):(b)) +#define REG_SAFE_BM_SIZE ARRAY_SIZE(evergreen_reg_safe_bm) + int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, struct radeon_bo_list **cs_reloc); struct evergreen_cs_track { @@ -84,6 +86,7 @@ struct evergreen_cs_track { u32 htile_surface; struct radeon_bo *htile_bo; unsigned long indirect_draw_buffer_size; + const unsigned *reg_safe_bm; }; static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) @@ -444,7 +447,7 @@ static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned i * command stream. */ if (!surf.mode) { - volatile u32 *ib = p->ib.ptr; + uint32_t *ib = p->ib.ptr; unsigned long tmp, nby, bsize, size, min = 0; /* find the height the ddx wants */ @@ -1083,41 +1086,18 @@ static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p, } /** - * evergreen_cs_check_reg() - check if register is authorized or not + * evergreen_cs_handle_reg() - process registers that need special handling. * @parser: parser structure holding parsing context * @reg: register we are testing * @idx: index into the cs buffer - * - * This function will test against evergreen_reg_safe_bm and return 0 - * if register is safe. If register is not flag as safe this function - * will test it against a list of register needind special handling. */ -static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +static int evergreen_cs_handle_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) { struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track; struct radeon_bo_list *reloc; - u32 last_reg; - u32 m, i, tmp, *ib; + u32 tmp, *ib; int r; - if (p->rdev->family >= CHIP_CAYMAN) - last_reg = ARRAY_SIZE(cayman_reg_safe_bm); - else - last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); - - i = (reg >> 7); - if (i >= last_reg) { - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); - return -EINVAL; - } - m = 1 << ((reg >> 2) & 31); - if (p->rdev->family >= CHIP_CAYMAN) { - if (!(cayman_reg_safe_bm[i] & m)) - return 0; - } else { - if (!(evergreen_reg_safe_bm[i] & m)) - return 0; - } ib = p->ib.ptr; switch (reg) { /* force following reg to 0 in an attempt to disable out buffer @@ -1764,29 +1744,27 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) return 0; } -static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +/** + * evergreen_is_safe_reg() - check if register is authorized or not + * @parser: parser structure holding parsing context + * @reg: register we are testing + * + * This function will test against reg_safe_bm and return true + * if register is safe or false otherwise. + */ +static inline bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg) { - u32 last_reg, m, i; - - if (p->rdev->family >= CHIP_CAYMAN) - last_reg = ARRAY_SIZE(cayman_reg_safe_bm); - else - last_reg = ARRAY_SIZE(evergreen_reg_safe_bm); + struct evergreen_cs_track *track = p->track; + u32 m, i; i = (reg >> 7); - if (i >= last_reg) { - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); + if (unlikely(i >= REG_SAFE_BM_SIZE)) { return false; } m = 1 << ((reg >> 2) & 31); - if (p->rdev->family >= CHIP_CAYMAN) { - if (!(cayman_reg_safe_bm[i] & m)) - return true; - } else { - if (!(evergreen_reg_safe_bm[i] & m)) - return true; - } - dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); + if (!(track->reg_safe_bm[i] & m)) + return true; + return false; } @@ -1795,7 +1773,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, { struct radeon_bo_list *reloc; struct evergreen_cs_track *track; - volatile u32 *ib; + uint32_t *ib; unsigned idx; unsigned i; unsigned start_reg, end_reg, reg; @@ -2321,9 +2299,10 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n"); return -EINVAL; } - for (i = 0; i < pkt->count; i++) { - reg = start_reg + (4 * i); - r = evergreen_cs_check_reg(p, reg, idx+1+i); + for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { + if (evergreen_is_safe_reg(p, reg)) + continue; + r = evergreen_cs_handle_reg(p, reg, idx); if (r) return r; } @@ -2337,9 +2316,10 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n"); return -EINVAL; } - for (i = 0; i < pkt->count; i++) { - reg = start_reg + (4 * i); - r = evergreen_cs_check_reg(p, reg, idx+1+i); + for (reg = start_reg, idx++; reg <= end_reg; reg += 4, idx++) { + if (evergreen_is_safe_reg(p, reg)) + continue; + r = evergreen_cs_handle_reg(p, reg, idx); if (r) return r; } @@ -2594,8 +2574,11 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } else { /* SRC is a reg. */ reg = radeon_get_ib_value(p, idx+1) << 2; - if (!evergreen_is_safe_reg(p, reg, idx+1)) + if (!evergreen_is_safe_reg(p, reg)) { + dev_warn(p->dev, "forbidden register 0x%08x at %d\n", + reg, idx + 1); return -EINVAL; + } } if (idx_value & 0x2) { u64 offset; @@ -2618,8 +2601,11 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, } else { /* DST is a reg. */ reg = radeon_get_ib_value(p, idx+3) << 2; - if (!evergreen_is_safe_reg(p, reg, idx+3)) + if (!evergreen_is_safe_reg(p, reg)) { + dev_warn(p->dev, "forbidden register 0x%08x at %d\n", + reg, idx + 3); return -EINVAL; + } } break; case PACKET3_NOP: @@ -2644,11 +2630,15 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) if (track == NULL) return -ENOMEM; evergreen_cs_track_init(track); - if (p->rdev->family >= CHIP_CAYMAN) + if (p->rdev->family >= CHIP_CAYMAN) { tmp = p->rdev->config.cayman.tile_config; - else + track->reg_safe_bm = cayman_reg_safe_bm; + } else { tmp = p->rdev->config.evergreen.tile_config; - + track->reg_safe_bm = evergreen_reg_safe_bm; + } + BUILD_BUG_ON(ARRAY_SIZE(cayman_reg_safe_bm) != REG_SAFE_BM_SIZE); + BUILD_BUG_ON(ARRAY_SIZE(evergreen_reg_safe_bm) != REG_SAFE_BM_SIZE); switch (tmp & 0xf) { case 0: track->npipes = 1; @@ -2757,7 +2747,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p) struct radeon_cs_chunk *ib_chunk = p->chunk_ib; struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc; u32 header, cmd, count, sub_cmd; - volatile u32 *ib = p->ib.ptr; + uint32_t *ib = p->ib.ptr; u32 idx; u64 src_offset, dst_offset, dst2_offset; int r; diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c index 34c8b2340f33..443cbe59b274 100644 --- a/drivers/gpu/drm/radeon/r600_blit_shaders.c +++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c @@ -32,7 +32,7 @@ * R6xx+ cards need to use the 3D engine to blit data which requires * quite a bit of hw state setup. Rather than pull the whole 3D driver * (which normally generates the 3D state) into the DRM, we opt to use - * statically generated state tables. The regsiter state and shaders + * statically generated state tables. The register state and shaders * were hand generated to support blitting functionality. See the 3D * driver or documentation for descriptions of the registers and * shader instructions. diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c index 98f9adaccc3d..e231eeafef23 100644 --- a/drivers/gpu/drm/radeon/r600_cp.c +++ b/drivers/gpu/drm/radeon/r600_cp.c @@ -1837,7 +1837,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, SET_RING_HEAD(dev_priv, 0); dev_priv->ring.tail = 0; -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { rptr_addr = dev_priv->ring_rptr->offset - dev->agp->base + @@ -1863,7 +1863,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, dev_priv->ring.size_l2qw); #endif -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { /* XXX */ radeon_write_agp_base(dev_priv, dev->agp->base); @@ -1946,7 +1946,7 @@ int r600_do_cleanup_cp(struct drm_device *dev) if (dev->irq_enabled) drm_irq_uninstall(dev); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { if (dev_priv->cp_ring != NULL) { drm_legacy_ioremapfree(dev_priv->cp_ring, dev); @@ -2089,7 +2089,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, } } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) /* XXX */ if (dev_priv->flags & RADEON_IS_AGP) { drm_legacy_ioremap_wc(dev_priv->cp_ring, dev); @@ -2148,7 +2148,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, * location in the card and on the bus, though we have to * align it down. */ -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) /* XXX */ if (dev_priv->flags & RADEON_IS_AGP) { base = dev->agp->base; @@ -2175,7 +2175,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, base, dev_priv->gart_vm_start); } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) /* XXX */ if (dev_priv->flags & RADEON_IS_AGP) dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset @@ -2212,7 +2212,7 @@ int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { /* XXX turn off pcie gart */ } else diff --git a/drivers/gpu/drm/radeon/radeon_acpi.c b/drivers/gpu/drm/radeon/radeon_acpi.c index 77e9d07c55b6..59acd0e5c2c6 100644 --- a/drivers/gpu/drm/radeon/radeon_acpi.c +++ b/drivers/gpu/drm/radeon/radeon_acpi.c @@ -25,7 +25,6 @@ #include <linux/acpi.h> #include <linux/slab.h> #include <linux/power_supply.h> -#include <linux/vga_switcheroo.h> #include <acpi/video.h> #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> diff --git a/drivers/gpu/drm/radeon/radeon_agp.c b/drivers/gpu/drm/radeon/radeon_agp.c index a9297b2c3524..fe994aac3b04 100644 --- a/drivers/gpu/drm/radeon/radeon_agp.c +++ b/drivers/gpu/drm/radeon/radeon_agp.c @@ -28,7 +28,7 @@ #include "radeon.h" #include <drm/radeon_drm.h> -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) struct radeon_agpmode_quirk { u32 hostbridge_vendor; @@ -123,7 +123,7 @@ static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = { int radeon_agp_init(struct radeon_device *rdev) { -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list; struct drm_agp_mode mode; struct drm_agp_info info; @@ -257,7 +257,7 @@ int radeon_agp_init(struct radeon_device *rdev) void radeon_agp_resume(struct radeon_device *rdev) { -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) int r; if (rdev->flags & RADEON_IS_AGP) { r = radeon_agp_init(rdev); @@ -269,7 +269,7 @@ void radeon_agp_resume(struct radeon_device *rdev) void radeon_agp_fini(struct radeon_device *rdev) { -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (rdev->ddev->agp && rdev->ddev->agp->acquired) { drm_agp_release(rdev->ddev); } diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index f2421bc3e901..1d4d4520a0ac 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -31,7 +31,6 @@ #include <drm/drm_crtc_helper.h> #include <drm/radeon_drm.h> #include <linux/vgaarb.h> -#include <linux/vga_switcheroo.h> #include "radeon_reg.h" #include "radeon.h" #include "radeon_asic.h" diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c index 8bc7d0bbd3c8..c4b4f298a283 100644 --- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c +++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c @@ -499,7 +499,7 @@ static int radeon_atpx_get_client_id(struct pci_dev *pdev) return VGA_SWITCHEROO_DIS; } -static struct vga_switcheroo_handler radeon_atpx_handler = { +static const struct vga_switcheroo_handler radeon_atpx_handler = { .switchto = radeon_atpx_switchto, .power_state = radeon_atpx_power_state, .init = radeon_atpx_init, @@ -535,7 +535,7 @@ static bool radeon_atpx_detect(void) if (has_atpx && vga_count == 2) { acpi_get_name(radeon_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer); - printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n", + printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n", acpi_method_name); radeon_atpx_priv.atpx_detected = true; return true; diff --git a/drivers/gpu/drm/radeon/radeon_bios.c b/drivers/gpu/drm/radeon/radeon_bios.c index d27e4ccb848c..21b6732425c5 100644 --- a/drivers/gpu/drm/radeon/radeon_bios.c +++ b/drivers/gpu/drm/radeon/radeon_bios.c @@ -30,7 +30,6 @@ #include "radeon.h" #include "atom.h" -#include <linux/vga_switcheroo.h> #include <linux/slab.h> #include <linux/acpi.h> /* diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index ea134a7d51a5..500287eff55d 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c @@ -762,7 +762,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, ((dev_priv->gart_vm_start - 1) & 0xffff0000) | (dev_priv->fb_location >> 16)); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { radeon_write_agp_base(dev_priv, dev->agp->base); @@ -791,7 +791,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev, SET_RING_HEAD(dev_priv, cur_read_ptr); dev_priv->ring.tail = cur_read_ptr; -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, dev_priv->ring_rptr->offset @@ -1335,7 +1335,7 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, } } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { drm_legacy_ioremap_wc(dev_priv->cp_ring, dev); drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev); @@ -1394,7 +1394,7 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, * location in the card and on the bus, though we have to * align it down. */ -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { base = dev->agp->base; /* Check if valid */ @@ -1424,7 +1424,7 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, RADEON_READ(RADEON_CONFIG_APER_SIZE); } -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset - dev->agp->base @@ -1455,7 +1455,7 @@ static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { /* Turn off PCI GART */ radeon_set_pcigart(dev_priv, 0); @@ -1566,7 +1566,7 @@ static int radeon_do_cleanup_cp(struct drm_device * dev) if (dev->irq_enabled) drm_irq_uninstall(dev); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { if (dev_priv->cp_ring != NULL) { drm_legacy_ioremapfree(dev_priv->cp_ring, dev); @@ -1625,7 +1625,7 @@ static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_pri DRM_DEBUG("Starting radeon_do_resume_cp()\n"); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (dev_priv->flags & RADEON_IS_AGP) { /* Turn off PCI GART */ radeon_set_pcigart(dev_priv, 0); diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index f3f562f6d848..c566993a2ec3 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c @@ -1197,7 +1197,7 @@ static void radeon_check_arguments(struct radeon_device *rdev) * radeon_switcheroo_set_state - set switcheroo state * * @pdev: pci dev pointer - * @state: vga switcheroo state + * @state: vga_switcheroo state * * Callback for the switcheroo driver. Suspends or resumes the * the asics before or after it is powered up using ACPI methods. diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 0503af748d99..a8d9927ed9eb 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -1634,18 +1634,8 @@ int radeon_modeset_init(struct radeon_device *rdev) radeon_fbdev_init(rdev); drm_kms_helper_poll_init(rdev->ddev); - if (rdev->pm.dpm_enabled) { - /* do dpm late init */ - ret = radeon_pm_late_init(rdev); - if (ret) { - rdev->pm.dpm_enabled = false; - DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); - } - /* set the dpm state for PX since there won't be - * a modeset to call this. - */ - radeon_pm_compute_clocks(rdev); - } + /* do pm late init */ + ret = radeon_pm_late_init(rdev); return 0; } @@ -1799,8 +1789,9 @@ bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc, * unknown small number of scanlines wrt. real scanout position. * */ -int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags, - int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, +int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode) { u32 stat_crtc = 0, vbl = 0, position = 0; @@ -1816,42 +1807,42 @@ int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl *stime = ktime_get(); if (ASIC_IS_DCE4(rdev)) { - if (crtc == 0) { + if (pipe == 0) { vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET); position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + EVERGREEN_CRTC0_REGISTER_OFFSET); ret |= DRM_SCANOUTPOS_VALID; } - if (crtc == 1) { + if (pipe == 1) { vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET); position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + EVERGREEN_CRTC1_REGISTER_OFFSET); ret |= DRM_SCANOUTPOS_VALID; } - if (crtc == 2) { + if (pipe == 2) { vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET); position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + EVERGREEN_CRTC2_REGISTER_OFFSET); ret |= DRM_SCANOUTPOS_VALID; } - if (crtc == 3) { + if (pipe == 3) { vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET); position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + EVERGREEN_CRTC3_REGISTER_OFFSET); ret |= DRM_SCANOUTPOS_VALID; } - if (crtc == 4) { + if (pipe == 4) { vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET); position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + EVERGREEN_CRTC4_REGISTER_OFFSET); ret |= DRM_SCANOUTPOS_VALID; } - if (crtc == 5) { + if (pipe == 5) { vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET); position = RREG32(EVERGREEN_CRTC_STATUS_POSITION + @@ -1859,19 +1850,19 @@ int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl ret |= DRM_SCANOUTPOS_VALID; } } else if (ASIC_IS_AVIVO(rdev)) { - if (crtc == 0) { + if (pipe == 0) { vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END); position = RREG32(AVIVO_D1CRTC_STATUS_POSITION); ret |= DRM_SCANOUTPOS_VALID; } - if (crtc == 1) { + if (pipe == 1) { vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END); position = RREG32(AVIVO_D2CRTC_STATUS_POSITION); ret |= DRM_SCANOUTPOS_VALID; } } else { /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */ - if (crtc == 0) { + if (pipe == 0) { /* Assume vbl_end == 0, get vbl_start from * upper 16 bits. */ @@ -1885,7 +1876,7 @@ int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl ret |= DRM_SCANOUTPOS_VALID; } - if (crtc == 1) { + if (pipe == 1) { vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) & RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT; position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL; diff --git a/drivers/gpu/drm/radeon/radeon_dp_mst.c b/drivers/gpu/drm/radeon/radeon_dp_mst.c index 5e09c061847f..6cddae44fa6e 100644 --- a/drivers/gpu/drm/radeon/radeon_dp_mst.c +++ b/drivers/gpu/drm/radeon/radeon_dp_mst.c @@ -265,7 +265,6 @@ static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topol { struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr); struct drm_device *dev = master->base.dev; - struct radeon_device *rdev = dev->dev_private; struct radeon_connector *radeon_connector; struct drm_connector *connector; @@ -286,12 +285,19 @@ static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topol drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); drm_mode_connector_set_path_property(connector, pathprop); + return connector; +} + +static void radeon_dp_register_mst_connector(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct radeon_device *rdev = dev->dev_private; + drm_modeset_lock_all(dev); radeon_fb_add_connector(rdev, connector); drm_modeset_unlock_all(dev); drm_connector_register(connector); - return connector; } static void radeon_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, @@ -324,6 +330,7 @@ static void radeon_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) struct drm_dp_mst_topology_cbs mst_cbs = { .add_connector = radeon_dp_add_mst_connector, + .register_connector = radeon_dp_register_mst_connector, .destroy_connector = radeon_dp_destroy_mst_connector, .hotplug = radeon_dp_mst_hotplug, }; diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c index e30c1d73b4ca..5b6a6f5b3619 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.c +++ b/drivers/gpu/drm/radeon/radeon_drv.c @@ -105,10 +105,10 @@ void radeon_driver_preclose_kms(struct drm_device *dev, struct drm_file *file_priv); int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon); -u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc); -int radeon_enable_vblank_kms(struct drm_device *dev, int crtc); -void radeon_disable_vblank_kms(struct drm_device *dev, int crtc); -int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, +u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); +int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); +void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); +int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, unsigned flags); @@ -124,9 +124,8 @@ void radeon_gem_object_close(struct drm_gem_object *obj, struct dma_buf *radeon_gem_prime_export(struct drm_device *dev, struct drm_gem_object *gobj, int flags); -extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, - unsigned int flags, - int *vpos, int *hpos, +extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc, + unsigned int flags, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); extern bool radeon_is_px(struct drm_device *dev); diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index 46bd3938282c..0caafc7a6e17 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h @@ -404,9 +404,9 @@ extern int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file * extern int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv); extern void radeon_do_release(struct drm_device * dev); -extern u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc); -extern int radeon_enable_vblank(struct drm_device *dev, int crtc); -extern void radeon_disable_vblank(struct drm_device *dev, int crtc); +extern u32 radeon_get_vblank_counter(struct drm_device *dev, unsigned int pipe); +extern int radeon_enable_vblank(struct drm_device *dev, unsigned int pipe); +extern void radeon_disable_vblank(struct drm_device *dev, unsigned int pipe); extern irqreturn_t radeon_driver_irq_handler(int irq, void *arg); extern void radeon_driver_irq_preinstall(struct drm_device * dev); extern int radeon_driver_irq_postinstall(struct drm_device *dev); diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c index 7214858ffcea..26da2f4d7b4f 100644 --- a/drivers/gpu/drm/radeon/radeon_fb.c +++ b/drivers/gpu/drm/radeon/radeon_fb.c @@ -48,40 +48,10 @@ struct radeon_fbdev { struct radeon_device *rdev; }; -/** - * radeon_fb_helper_set_par - Hide cursor on CRTCs used by fbdev. - * - * @info: fbdev info - * - * This function hides the cursor on all CRTCs used by fbdev. - */ -static int radeon_fb_helper_set_par(struct fb_info *info) -{ - int ret; - - ret = drm_fb_helper_set_par(info); - - /* XXX: with universal plane support fbdev will automatically disable - * all non-primary planes (including the cursor) - */ - if (ret == 0) { - struct drm_fb_helper *fb_helper = info->par; - int i; - - for (i = 0; i < fb_helper->crtc_count; i++) { - struct drm_crtc *crtc = fb_helper->crtc_info[i].mode_set.crtc; - - radeon_crtc_cursor_set2(crtc, NULL, 0, 0, 0, 0, 0); - } - } - - return ret; -} - static struct fb_ops radeonfb_ops = { .owner = THIS_MODULE, .fb_check_var = drm_fb_helper_check_var, - .fb_set_par = radeon_fb_helper_set_par, + .fb_set_par = drm_fb_helper_set_par, .fb_fillrect = drm_fb_helper_cfb_fillrect, .fb_copyarea = drm_fb_helper_cfb_copyarea, .fb_imageblit = drm_fb_helper_cfb_imageblit, @@ -427,3 +397,19 @@ void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector { drm_fb_helper_remove_one_connector(&rdev->mode_info.rfbdev->helper, connector); } + +void radeon_fbdev_restore_mode(struct radeon_device *rdev) +{ + struct radeon_fbdev *rfbdev = rdev->mode_info.rfbdev; + struct drm_fb_helper *fb_helper; + int ret; + + if (!rfbdev) + return; + + fb_helper = &rfbdev->helper; + + ret = drm_fb_helper_restore_fbdev_mode_unlocked(fb_helper); + if (ret) + DRM_DEBUG("failed to restore crtc mode\n"); +} diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c index 244b19bab2e7..688afb62f7c4 100644 --- a/drivers/gpu/drm/radeon/radeon_irq.c +++ b/drivers/gpu/drm/radeon/radeon_irq.c @@ -62,12 +62,12 @@ static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state) RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg); } -int radeon_enable_vblank(struct drm_device *dev, int crtc) +int radeon_enable_vblank(struct drm_device *dev, unsigned int pipe) { drm_radeon_private_t *dev_priv = dev->dev_private; if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { - switch (crtc) { + switch (pipe) { case 0: r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1); break; @@ -75,12 +75,12 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc) r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1); break; default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); + DRM_ERROR("tried to enable vblank on non-existent crtc %u\n", + pipe); return -EINVAL; } } else { - switch (crtc) { + switch (pipe) { case 0: radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1); break; @@ -88,8 +88,8 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc) radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1); break; default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); + DRM_ERROR("tried to enable vblank on non-existent crtc %u\n", + pipe); return -EINVAL; } } @@ -97,12 +97,12 @@ int radeon_enable_vblank(struct drm_device *dev, int crtc) return 0; } -void radeon_disable_vblank(struct drm_device *dev, int crtc) +void radeon_disable_vblank(struct drm_device *dev, unsigned int pipe) { drm_radeon_private_t *dev_priv = dev->dev_private; if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { - switch (crtc) { + switch (pipe) { case 0: r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0); break; @@ -110,12 +110,12 @@ void radeon_disable_vblank(struct drm_device *dev, int crtc) r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0); break; default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); + DRM_ERROR("tried to enable vblank on non-existent crtc %u\n", + pipe); break; } } else { - switch (crtc) { + switch (pipe) { case 0: radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0); break; @@ -123,8 +123,8 @@ void radeon_disable_vblank(struct drm_device *dev, int crtc) radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0); break; default: - DRM_ERROR("tried to enable vblank on non-existent crtc %d\n", - crtc); + DRM_ERROR("tried to enable vblank on non-existent crtc %u\n", + pipe); break; } } @@ -255,7 +255,7 @@ static int radeon_wait_irq(struct drm_device * dev, int swi_nr) return ret; } -u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc) +u32 radeon_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { drm_radeon_private_t *dev_priv = dev->dev_private; @@ -264,18 +264,18 @@ u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc) return -EINVAL; } - if (crtc < 0 || crtc > 1) { - DRM_ERROR("Invalid crtc %d\n", crtc); + if (pipe > 1) { + DRM_ERROR("Invalid crtc %u\n", pipe); return -EINVAL; } if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) { - if (crtc == 0) + if (pipe == 0) return RADEON_READ(R500_D1CRTC_FRAME_COUNT); else return RADEON_READ(R500_D2CRTC_FRAME_COUNT); } else { - if (crtc == 0) + if (pipe == 0) return RADEON_READ(RADEON_CRTC_CRNT_FRAME); else return RADEON_READ(RADEON_CRTC2_CRNT_FRAME); diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c index fd9da282b29c..0ec6fcca16d3 100644 --- a/drivers/gpu/drm/radeon/radeon_kms.c +++ b/drivers/gpu/drm/radeon/radeon_kms.c @@ -181,7 +181,9 @@ static void radeon_set_filp_rights(struct drm_device *dev, struct drm_file *applier, uint32_t *value) { - mutex_lock(&dev->struct_mutex); + struct radeon_device *rdev = dev->dev_private; + + mutex_lock(&rdev->gem.mutex); if (*value == 1) { /* wants rights */ if (!*owner) @@ -192,7 +194,7 @@ static void radeon_set_filp_rights(struct drm_device *dev, *owner = NULL; } *value = *owner == applier ? 1 : 0; - mutex_unlock(&dev->struct_mutex); + mutex_unlock(&rdev->gem.mutex); } /* @@ -598,14 +600,17 @@ static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file * Outdated mess for old drm with Xorg being in charge (void function now). */ /** - * radeon_driver_firstopen_kms - drm callback for last close + * radeon_driver_lastclose_kms - drm callback for last close * * @dev: drm dev pointer * - * Switch vga switcheroo state after last close (all asics). + * Switch vga_switcheroo state after last close (all asics). */ void radeon_driver_lastclose_kms(struct drm_device *dev) { + struct radeon_device *rdev = dev->dev_private; + + radeon_fbdev_restore_mode(rdev); vga_switcheroo_process_delayed_switch(); } @@ -724,10 +729,14 @@ void radeon_driver_preclose_kms(struct drm_device *dev, struct drm_file *file_priv) { struct radeon_device *rdev = dev->dev_private; + + mutex_lock(&rdev->gem.mutex); if (rdev->hyperz_filp == file_priv) rdev->hyperz_filp = NULL; if (rdev->cmask_filp == file_priv) rdev->cmask_filp = NULL; + mutex_unlock(&rdev->gem.mutex); + radeon_uvd_free_handles(rdev, file_priv); radeon_vce_free_handles(rdev, file_priv); } @@ -844,89 +853,49 @@ int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, &drmcrtc->hwmode); } -#define KMS_INVALID_IOCTL(name) \ -static int name(struct drm_device *dev, void *data, struct drm_file \ - *file_priv) \ -{ \ - DRM_ERROR("invalid ioctl with kms %s\n", __func__); \ - return -EINVAL; \ -} - -/* - * All these ioctls are invalid in kms world. - */ -KMS_INVALID_IOCTL(radeon_cp_init_kms) -KMS_INVALID_IOCTL(radeon_cp_start_kms) -KMS_INVALID_IOCTL(radeon_cp_stop_kms) -KMS_INVALID_IOCTL(radeon_cp_reset_kms) -KMS_INVALID_IOCTL(radeon_cp_idle_kms) -KMS_INVALID_IOCTL(radeon_cp_resume_kms) -KMS_INVALID_IOCTL(radeon_engine_reset_kms) -KMS_INVALID_IOCTL(radeon_fullscreen_kms) -KMS_INVALID_IOCTL(radeon_cp_swap_kms) -KMS_INVALID_IOCTL(radeon_cp_clear_kms) -KMS_INVALID_IOCTL(radeon_cp_vertex_kms) -KMS_INVALID_IOCTL(radeon_cp_indices_kms) -KMS_INVALID_IOCTL(radeon_cp_texture_kms) -KMS_INVALID_IOCTL(radeon_cp_stipple_kms) -KMS_INVALID_IOCTL(radeon_cp_indirect_kms) -KMS_INVALID_IOCTL(radeon_cp_vertex2_kms) -KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms) -KMS_INVALID_IOCTL(radeon_cp_getparam_kms) -KMS_INVALID_IOCTL(radeon_cp_flip_kms) -KMS_INVALID_IOCTL(radeon_mem_alloc_kms) -KMS_INVALID_IOCTL(radeon_mem_free_kms) -KMS_INVALID_IOCTL(radeon_mem_init_heap_kms) -KMS_INVALID_IOCTL(radeon_irq_emit_kms) -KMS_INVALID_IOCTL(radeon_irq_wait_kms) -KMS_INVALID_IOCTL(radeon_cp_setparam_kms) -KMS_INVALID_IOCTL(radeon_surface_alloc_kms) -KMS_INVALID_IOCTL(radeon_surface_free_kms) - - const struct drm_ioctl_desc radeon_ioctls_kms[] = { - DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), - DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH), - DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(RADEON_CP_START, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_RESET, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_SWAP, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_CLEAR, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_VERTEX, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_INDICES, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_FLIP, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_ALLOC, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_FREE, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, drm_invalid_op, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), + DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, drm_invalid_op, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, drm_invalid_op, DRM_AUTH), /* KMS */ - DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH), + DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(RADEON_GEM_USERPTR, radeon_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), }; int radeon_max_kms_ioctl = ARRAY_SIZE(radeon_ioctls_kms); diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h index 2317d04f8a09..830e171c3a9e 100644 --- a/drivers/gpu/drm/radeon/radeon_mode.h +++ b/drivers/gpu/drm/radeon/radeon_mode.h @@ -874,9 +874,8 @@ extern int radeon_crtc_cursor_move(struct drm_crtc *crtc, int x, int y); extern void radeon_cursor_reset(struct drm_crtc *crtc); -extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, - unsigned int flags, - int *vpos, int *hpos, +extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, + unsigned int flags, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); @@ -981,6 +980,7 @@ int radeon_fbdev_init(struct radeon_device *rdev); void radeon_fbdev_fini(struct radeon_device *rdev); void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state); bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj); +void radeon_fbdev_restore_mode(struct radeon_device *rdev); void radeon_fb_output_poll_changed(struct radeon_device *rdev); diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c index 10f4c12e439e..bcdc508127f1 100644 --- a/drivers/gpu/drm/radeon/radeon_pm.c +++ b/drivers/gpu/drm/radeon/radeon_pm.c @@ -1326,14 +1326,6 @@ static int radeon_pm_init_old(struct radeon_device *rdev) INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); if (rdev->pm.num_power_states > 1) { - /* where's the best place to put these? */ - ret = device_create_file(rdev->dev, &dev_attr_power_profile); - if (ret) - DRM_ERROR("failed to create device file for power profile\n"); - ret = device_create_file(rdev->dev, &dev_attr_power_method); - if (ret) - DRM_ERROR("failed to create device file for power method\n"); - if (radeon_debugfs_pm_init(rdev)) { DRM_ERROR("Failed to register debugfs file for PM!\n"); } @@ -1391,20 +1383,6 @@ static int radeon_pm_init_dpm(struct radeon_device *rdev) goto dpm_failed; rdev->pm.dpm_enabled = true; - ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); - if (ret) - DRM_ERROR("failed to create device file for dpm state\n"); - ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); - if (ret) - DRM_ERROR("failed to create device file for dpm state\n"); - /* XXX: these are noops for dpm but are here for backwards compat */ - ret = device_create_file(rdev->dev, &dev_attr_power_profile); - if (ret) - DRM_ERROR("failed to create device file for power profile\n"); - ret = device_create_file(rdev->dev, &dev_attr_power_method); - if (ret) - DRM_ERROR("failed to create device file for power method\n"); - if (radeon_debugfs_pm_init(rdev)) { DRM_ERROR("Failed to register debugfs file for dpm!\n"); } @@ -1545,9 +1523,44 @@ int radeon_pm_late_init(struct radeon_device *rdev) int ret = 0; if (rdev->pm.pm_method == PM_METHOD_DPM) { - mutex_lock(&rdev->pm.mutex); - ret = radeon_dpm_late_enable(rdev); - mutex_unlock(&rdev->pm.mutex); + if (rdev->pm.dpm_enabled) { + ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); + if (ret) + DRM_ERROR("failed to create device file for dpm state\n"); + ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); + if (ret) + DRM_ERROR("failed to create device file for dpm state\n"); + /* XXX: these are noops for dpm but are here for backwards compat */ + ret = device_create_file(rdev->dev, &dev_attr_power_profile); + if (ret) + DRM_ERROR("failed to create device file for power profile\n"); + ret = device_create_file(rdev->dev, &dev_attr_power_method); + if (ret) + DRM_ERROR("failed to create device file for power method\n"); + + mutex_lock(&rdev->pm.mutex); + ret = radeon_dpm_late_enable(rdev); + mutex_unlock(&rdev->pm.mutex); + if (ret) { + rdev->pm.dpm_enabled = false; + DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); + } else { + /* set the dpm state for PX since there won't be + * a modeset to call this. + */ + radeon_pm_compute_clocks(rdev); + } + } + } else { + if (rdev->pm.num_power_states > 1) { + /* where's the best place to put these? */ + ret = device_create_file(rdev->dev, &dev_attr_power_profile); + if (ret) + DRM_ERROR("failed to create device file for power profile\n"); + ret = device_create_file(rdev->dev, &dev_attr_power_method); + if (ret) + DRM_ERROR("failed to create device file for power method\n"); + } } return ret; } diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index 06ac59fe332a..e34307459e50 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -144,7 +144,7 @@ static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, man->available_caching = TTM_PL_MASK_CACHING; man->default_caching = TTM_PL_FLAG_CACHED; man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (rdev->flags & RADEON_IS_AGP) { if (!rdev->ddev->agp) { DRM_ERROR("AGP is not enabled for memory type %u\n", @@ -461,7 +461,7 @@ static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_ /* system memory */ return 0; case TTM_PL_TT: -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (rdev->flags & RADEON_IS_AGP) { /* RADEON_IS_AGP is set only if AGP is active */ mem->bus.offset = mem->start << PAGE_SHIFT; @@ -680,7 +680,7 @@ static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, struct radeon_ttm_tt *gtt; rdev = radeon_get_rdev(bdev); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (rdev->flags & RADEON_IS_AGP) { return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, size, page_flags, dummy_read_page); @@ -736,7 +736,7 @@ static int radeon_ttm_tt_populate(struct ttm_tt *ttm) } rdev = radeon_get_rdev(ttm->bdev); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (rdev->flags & RADEON_IS_AGP) { return ttm_agp_tt_populate(ttm); } @@ -787,7 +787,7 @@ static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) return; rdev = radeon_get_rdev(ttm->bdev); -#if __OS_HAS_AGP +#if IS_ENABLED(CONFIG_AGP) if (rdev->flags & RADEON_IS_AGP) { ttm_agp_tt_unpopulate(ttm); return; diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index e9115d3f67b0..e72bf46042e0 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -2928,6 +2928,7 @@ static struct si_dpm_quirk si_dpm_quirk_list[] = { { PCI_VENDOR_ID_ATI, 0x6811, 0x174b, 0xe271, 0, 120000 }, { PCI_VENDOR_ID_ATI, 0x6810, 0x174b, 0xe271, 85000, 90000 }, { PCI_VENDOR_ID_ATI, 0x6811, 0x1762, 0x2015, 0, 120000 }, + { PCI_VENDOR_ID_ATI, 0x6811, 0x1043, 0x2015, 0, 120000 }, { 0, 0, 0, 0 }, }; diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig index 11485a4a16ae..d4e0a39568f6 100644 --- a/drivers/gpu/drm/rcar-du/Kconfig +++ b/drivers/gpu/drm/rcar-du/Kconfig @@ -1,6 +1,6 @@ config DRM_RCAR_DU tristate "DRM Support for R-Car Display Unit" - depends on DRM && ARM && HAVE_DMA_ATTRS + depends on DRM && ARM && HAVE_DMA_ATTRS && OF depends on ARCH_SHMOBILE || COMPILE_TEST select DRM_KMS_HELPER select DRM_KMS_CMA_HELPER diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c index 780ca11512ba..40422f6b645e 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c @@ -84,16 +84,17 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = { .num_lvds = 2, }; +/* M2-W (r8a7791) and M2-N (r8a7793) are identical */ static const struct rcar_du_device_info rcar_du_r8a7791_info = { .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK | RCAR_DU_FEATURE_EXT_CTRL_REGS, .num_crtcs = 2, .routes = { - /* R8A7791 has one RGB output, one LVDS output and one + /* R8A779[13] has one RGB output, one LVDS output and one * (currently unsupported) TCON output. */ [RCAR_DU_OUTPUT_DPAD0] = { - .possible_crtcs = BIT(1), + .possible_crtcs = BIT(1) | BIT(0), .encoder_type = DRM_MODE_ENCODER_NONE, .port = 0, }, @@ -106,19 +107,34 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = { .num_lvds = 1, }; -static const struct platform_device_id rcar_du_id_table[] = { - { "rcar-du-r8a7779", (kernel_ulong_t)&rcar_du_r8a7779_info }, - { "rcar-du-r8a7790", (kernel_ulong_t)&rcar_du_r8a7790_info }, - { "rcar-du-r8a7791", (kernel_ulong_t)&rcar_du_r8a7791_info }, - { } +static const struct rcar_du_device_info rcar_du_r8a7794_info = { + .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK + | RCAR_DU_FEATURE_EXT_CTRL_REGS, + .num_crtcs = 2, + .routes = { + /* R8A7794 has two RGB outputs and one (currently unsupported) + * TCON output. + */ + [RCAR_DU_OUTPUT_DPAD0] = { + .possible_crtcs = BIT(0), + .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 0, + }, + [RCAR_DU_OUTPUT_DPAD1] = { + .possible_crtcs = BIT(1), + .encoder_type = DRM_MODE_ENCODER_NONE, + .port = 1, + }, + }, + .num_lvds = 0, }; -MODULE_DEVICE_TABLE(platform, rcar_du_id_table); - static const struct of_device_id rcar_du_of_table[] = { { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info }, { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info }, { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info }, + { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info }, + { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info }, { } }; @@ -167,8 +183,7 @@ static int rcar_du_load(struct drm_device *dev, unsigned long flags) init_waitqueue_head(&rcdu->commit.wait); rcdu->dev = &pdev->dev; - rcdu->info = np ? of_match_device(rcar_du_of_table, rcdu->dev)->data - : (void *)platform_get_device_id(pdev)->driver_data; + rcdu->info = of_match_device(rcar_du_of_table, rcdu->dev)->data; rcdu->ddev = dev; dev->dev_private = rcdu; @@ -221,20 +236,20 @@ static void rcar_du_lastclose(struct drm_device *dev) drm_fbdev_cma_restore_mode(rcdu->fbdev); } -static int rcar_du_enable_vblank(struct drm_device *dev, int crtc) +static int rcar_du_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct rcar_du_device *rcdu = dev->dev_private; - rcar_du_crtc_enable_vblank(&rcdu->crtcs[crtc], true); + rcar_du_crtc_enable_vblank(&rcdu->crtcs[pipe], true); return 0; } -static void rcar_du_disable_vblank(struct drm_device *dev, int crtc) +static void rcar_du_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct rcar_du_device *rcdu = dev->dev_private; - rcar_du_crtc_enable_vblank(&rcdu->crtcs[crtc], false); + rcar_du_crtc_enable_vblank(&rcdu->crtcs[pipe], false); } static const struct file_operations rcar_du_fops = { @@ -259,7 +274,7 @@ static struct drm_driver rcar_du_driver = { .preclose = rcar_du_preclose, .lastclose = rcar_du_lastclose, .set_busid = drm_platform_set_busid, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = rcar_du_enable_vblank, .disable_vblank = rcar_du_disable_vblank, .gem_free_object = drm_gem_cma_free_object, @@ -340,7 +355,6 @@ static struct platform_driver rcar_du_platform_driver = { .pm = &rcar_du_pm_ops, .of_match_table = rcar_du_of_table, }, - .id_table = rcar_du_id_table, }; module_platform_driver(rcar_du_platform_driver); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 7fd39a7d91c8..8e2ffe025153 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -49,9 +49,10 @@ static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp) u32 defr8 = DEFR8_CODE | DEFR8_DEFE8; /* The DEFR8 register for the first group also controls RGB output - * routing to DPAD0 + * routing to DPAD0 for DU instances that support it. */ - if (rgrp->index == 0) + if (rgrp->dev->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs > 1 && + rgrp->index == 0) defr8 |= DEFR8_DRGBS_DU(rgrp->dev->dpad0_source); rcar_du_group_write(rgrp, DEFR8, defr8); diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c b/drivers/gpu/drm/rcar-du/rcar_du_plane.c index c66986414bb4..ffa583712cd9 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c @@ -273,29 +273,6 @@ static const struct drm_plane_helper_funcs rcar_du_plane_helper_funcs = { .atomic_update = rcar_du_plane_atomic_update, }; -static void rcar_du_plane_reset(struct drm_plane *plane) -{ - struct rcar_du_plane_state *state; - - if (plane->state && plane->state->fb) - drm_framebuffer_unreference(plane->state->fb); - - kfree(plane->state); - plane->state = NULL; - - state = kzalloc(sizeof(*state), GFP_KERNEL); - if (state == NULL) - return; - - state->hwindex = -1; - state->alpha = 255; - state->colorkey = RCAR_DU_COLORKEY_NONE; - state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1; - - plane->state = &state->state; - plane->state->plane = plane; -} - static struct drm_plane_state * rcar_du_plane_atomic_duplicate_state(struct drm_plane *plane) { @@ -322,6 +299,28 @@ static void rcar_du_plane_atomic_destroy_state(struct drm_plane *plane, kfree(to_rcar_plane_state(state)); } +static void rcar_du_plane_reset(struct drm_plane *plane) +{ + struct rcar_du_plane_state *state; + + if (plane->state) { + rcar_du_plane_atomic_destroy_state(plane, plane->state); + plane->state = NULL; + } + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (state == NULL) + return; + + state->hwindex = -1; + state->alpha = 255; + state->colorkey = RCAR_DU_COLORKEY_NONE; + state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1; + + plane->state = &state->state; + plane->state->plane = plane; +} + static int rcar_du_plane_atomic_set_property(struct drm_plane *plane, struct drm_plane_state *state, struct drm_property *property, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c index 9a0c2911272a..d26e0cc7dc4b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c @@ -19,6 +19,7 @@ #include <drm/drmP.h> #include <drm/drm_crtc_helper.h> #include <drm/drm_fb_helper.h> +#include <drm/drm_of.h> #include <linux/dma-mapping.h> #include <linux/pm_runtime.h> #include <linux/module.h> @@ -103,7 +104,8 @@ static struct drm_crtc *rockchip_crtc_from_pipe(struct drm_device *drm, return NULL; } -static int rockchip_drm_crtc_enable_vblank(struct drm_device *dev, int pipe) +static int rockchip_drm_crtc_enable_vblank(struct drm_device *dev, + unsigned int pipe) { struct rockchip_drm_private *priv = dev->dev_private; struct drm_crtc *crtc = rockchip_crtc_from_pipe(dev, pipe); @@ -115,7 +117,8 @@ static int rockchip_drm_crtc_enable_vblank(struct drm_device *dev, int pipe) return 0; } -static void rockchip_drm_crtc_disable_vblank(struct drm_device *dev, int pipe) +static void rockchip_drm_crtc_disable_vblank(struct drm_device *dev, + unsigned int pipe) { struct rockchip_drm_private *priv = dev->dev_private; struct drm_crtc *crtc = rockchip_crtc_from_pipe(dev, pipe); @@ -277,7 +280,7 @@ static struct drm_driver rockchip_drm_driver = { .load = rockchip_drm_load, .unload = rockchip_drm_unload, .lastclose = rockchip_drm_lastclose, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = rockchip_drm_crtc_enable_vblank, .disable_vblank = rockchip_drm_crtc_disable_vblank, .gem_vm_ops = &rockchip_drm_vm_ops, @@ -416,29 +419,6 @@ static int compare_of(struct device *dev, void *data) return dev->of_node == np; } -static void rockchip_add_endpoints(struct device *dev, - struct component_match **match, - struct device_node *port) -{ - struct device_node *ep, *remote; - - for_each_child_of_node(port, ep) { - remote = of_graph_get_remote_port_parent(ep); - if (!remote || !of_device_is_available(remote)) { - of_node_put(remote); - continue; - } else if (!of_device_is_available(remote->parent)) { - dev_warn(dev, "parent device of %s is not available\n", - remote->full_name); - of_node_put(remote); - continue; - } - - component_match_add(dev, match, compare_of, remote); - of_node_put(remote); - } -} - static int rockchip_drm_bind(struct device *dev) { struct drm_device *drm; @@ -481,61 +461,14 @@ static const struct component_master_ops rockchip_drm_ops = { static int rockchip_drm_platform_probe(struct platform_device *pdev) { - struct device *dev = &pdev->dev; - struct component_match *match = NULL; - struct device_node *np = dev->of_node; - struct device_node *port; - int i; - - if (!np) - return -ENODEV; - /* - * Bind the crtc ports first, so that - * drm_of_find_possible_crtcs called from encoder .bind callbacks - * works as expected. - */ - for (i = 0;; i++) { - port = of_parse_phandle(np, "ports", i); - if (!port) - break; - - if (!of_device_is_available(port->parent)) { - of_node_put(port); - continue; - } - - component_match_add(dev, &match, compare_of, port->parent); - of_node_put(port); - } + int ret = drm_of_component_probe(&pdev->dev, compare_of, + &rockchip_drm_ops); - if (i == 0) { - dev_err(dev, "missing 'ports' property\n"); + /* keep compatibility with old code that was returning -ENODEV */ + if (ret == -EINVAL) return -ENODEV; - } - if (!match) { - dev_err(dev, "No available vop found for display-subsystem.\n"); - return -ENODEV; - } - /* - * For each bound crtc, bind the encoders attached to its - * remote endpoint. - */ - for (i = 0;; i++) { - port = of_parse_phandle(np, "ports", i); - if (!port) - break; - - if (!of_device_is_available(port->parent)) { - of_node_put(port); - continue; - } - - rockchip_add_endpoints(dev, &match, port); - of_node_put(port); - } - - return component_master_add_with_match(dev, &rockchip_drm_ops, match); + return ret; } static int rockchip_drm_platform_remove(struct platform_device *pdev) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c index a6d9104f7f15..8caea0a33dd8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_gem.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_gem.c @@ -79,12 +79,9 @@ static int rockchip_drm_gem_object_mmap(struct drm_gem_object *obj, int rockchip_gem_mmap_buf(struct drm_gem_object *obj, struct vm_area_struct *vma) { - struct drm_device *drm = obj->dev; int ret; - mutex_lock(&drm->struct_mutex); ret = drm_gem_mmap_obj(obj, obj->size, vma); - mutex_unlock(&drm->struct_mutex); if (ret) return ret; diff --git a/drivers/gpu/drm/shmobile/shmob_drm_drv.c b/drivers/gpu/drm/shmobile/shmob_drm_drv.c index 666321de7b99..04e66e3751b4 100644 --- a/drivers/gpu/drm/shmobile/shmob_drm_drv.c +++ b/drivers/gpu/drm/shmobile/shmob_drm_drv.c @@ -231,7 +231,7 @@ static irqreturn_t shmob_drm_irq(int irq, void *arg) return IRQ_HANDLED; } -static int shmob_drm_enable_vblank(struct drm_device *dev, int crtc) +static int shmob_drm_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct shmob_drm_device *sdev = dev->dev_private; @@ -240,7 +240,7 @@ static int shmob_drm_enable_vblank(struct drm_device *dev, int crtc) return 0; } -static void shmob_drm_disable_vblank(struct drm_device *dev, int crtc) +static void shmob_drm_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct shmob_drm_device *sdev = dev->dev_private; @@ -269,7 +269,7 @@ static struct drm_driver shmob_drm_driver = { .preclose = shmob_drm_preclose, .set_busid = drm_platform_set_busid, .irq_handler = shmob_drm_irq, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = shmob_drm_enable_vblank, .disable_vblank = shmob_drm_disable_vblank, .gem_free_object = drm_gem_cma_free_object, diff --git a/drivers/gpu/drm/sis/sis_drv.h b/drivers/gpu/drm/sis/sis_drv.h index 16f972b2a76a..328f8a750976 100644 --- a/drivers/gpu/drm/sis/sis_drv.h +++ b/drivers/gpu/drm/sis/sis_drv.h @@ -67,6 +67,10 @@ typedef struct drm_sis_private { struct idr object_idr; } drm_sis_private_t; +struct sis_file_private { + struct list_head obj_list; +}; + extern int sis_idle(struct drm_device *dev); extern void sis_reclaim_buffers_locked(struct drm_device *dev, struct drm_file *file_priv); diff --git a/drivers/gpu/drm/sti/sti_crtc.c b/drivers/gpu/drm/sti/sti_crtc.c index 018ffc970e96..493c4a3006ad 100644 --- a/drivers/gpu/drm/sti/sti_crtc.c +++ b/drivers/gpu/drm/sti/sti_crtc.c @@ -299,7 +299,7 @@ int sti_crtc_vblank_cb(struct notifier_block *nb, return 0; } -int sti_crtc_enable_vblank(struct drm_device *dev, int crtc) +int sti_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct sti_private *dev_priv = dev->dev_private; struct sti_compositor *compo = dev_priv->compo; @@ -307,9 +307,9 @@ int sti_crtc_enable_vblank(struct drm_device *dev, int crtc) DRM_DEBUG_DRIVER("\n"); - if (sti_vtg_register_client(crtc == STI_MIXER_MAIN ? + if (sti_vtg_register_client(pipe == STI_MIXER_MAIN ? compo->vtg_main : compo->vtg_aux, - vtg_vblank_nb, crtc)) { + vtg_vblank_nb, pipe)) { DRM_ERROR("Cannot register VTG notifier\n"); return -EINVAL; } @@ -318,7 +318,7 @@ int sti_crtc_enable_vblank(struct drm_device *dev, int crtc) } EXPORT_SYMBOL(sti_crtc_enable_vblank); -void sti_crtc_disable_vblank(struct drm_device *drm_dev, int crtc) +void sti_crtc_disable_vblank(struct drm_device *drm_dev, unsigned int pipe) { struct sti_private *priv = drm_dev->dev_private; struct sti_compositor *compo = priv->compo; @@ -326,14 +326,14 @@ void sti_crtc_disable_vblank(struct drm_device *drm_dev, int crtc) DRM_DEBUG_DRIVER("\n"); - if (sti_vtg_unregister_client(crtc == STI_MIXER_MAIN ? + if (sti_vtg_unregister_client(pipe == STI_MIXER_MAIN ? compo->vtg_main : compo->vtg_aux, vtg_vblank_nb)) DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n"); /* free the resources of the pending requests */ - if (compo->mixer[crtc]->pending_event) { - drm_vblank_put(drm_dev, crtc); - compo->mixer[crtc]->pending_event = NULL; + if (compo->mixer[pipe]->pending_event) { + drm_vblank_put(drm_dev, pipe); + compo->mixer[pipe]->pending_event = NULL; } } EXPORT_SYMBOL(sti_crtc_disable_vblank); diff --git a/drivers/gpu/drm/sti/sti_crtc.h b/drivers/gpu/drm/sti/sti_crtc.h index 51963e6ddbe7..3f2d89a3634d 100644 --- a/drivers/gpu/drm/sti/sti_crtc.h +++ b/drivers/gpu/drm/sti/sti_crtc.h @@ -13,8 +13,8 @@ struct sti_mixer; int sti_crtc_init(struct drm_device *drm_dev, struct sti_mixer *mixer, struct drm_plane *primary, struct drm_plane *cursor); -int sti_crtc_enable_vblank(struct drm_device *dev, int crtc); -void sti_crtc_disable_vblank(struct drm_device *dev, int crtc); +int sti_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe); +void sti_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe); int sti_crtc_vblank_cb(struct notifier_block *nb, unsigned long event, void *data); bool sti_crtc_is_main(struct drm_crtc *drm_crtc); diff --git a/drivers/gpu/drm/sti/sti_drv.c b/drivers/gpu/drm/sti/sti_drv.c index 9f85988a43ce..f8469967a0bf 100644 --- a/drivers/gpu/drm/sti/sti_drv.c +++ b/drivers/gpu/drm/sti/sti_drv.c @@ -201,7 +201,7 @@ static struct drm_driver sti_driver = { .dumb_destroy = drm_gem_dumb_destroy, .fops = &sti_driver_fops, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = sti_crtc_enable_vblank, .disable_vblank = sti_crtc_disable_vblank, diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index b4af4ab9ce6b..e9f24a85a103 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1694,6 +1694,7 @@ static int tegra_dc_debugfs_exit(struct tegra_dc *dc) static int tegra_dc_init(struct host1x_client *client) { struct drm_device *drm = dev_get_drvdata(client->parent); + unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; struct tegra_dc *dc = host1x_client_to_dc(client); struct tegra_drm *tegra = drm->dev_private; struct drm_plane *primary = NULL; @@ -1701,6 +1702,10 @@ static int tegra_dc_init(struct host1x_client *client) u32 value; int err; + dc->syncpt = host1x_syncpt_request(dc->dev, flags); + if (!dc->syncpt) + dev_warn(dc->dev, "failed to allocate syncpoint\n"); + if (tegra->domain) { err = iommu_attach_device(tegra->domain, dc->dev); if (err < 0) { @@ -1847,6 +1852,8 @@ static int tegra_dc_exit(struct host1x_client *client) dc->domain = NULL; } + host1x_syncpt_free(dc->syncpt); + return 0; } @@ -1959,7 +1966,6 @@ static int tegra_dc_parse_dt(struct tegra_dc *dc) static int tegra_dc_probe(struct platform_device *pdev) { - unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; const struct of_device_id *id; struct resource *regs; struct tegra_dc *dc; @@ -2034,10 +2040,6 @@ static int tegra_dc_probe(struct platform_device *pdev) return -ENXIO; } - dc->syncpt = host1x_syncpt_request(&pdev->dev, flags); - if (!dc->syncpt) - dev_warn(&pdev->dev, "failed to allocate syncpoint\n"); - INIT_LIST_HEAD(&dc->client.list); dc->client.ops = &dc_client_ops; dc->client.dev = &pdev->dev; @@ -2065,8 +2067,6 @@ static int tegra_dc_remove(struct platform_device *pdev) struct tegra_dc *dc = platform_get_drvdata(pdev); int err; - host1x_syncpt_free(dc->syncpt); - err = host1x_client_unregister(&dc->client); if (err < 0) { dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 2486bc24bff6..159ef515cab1 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -778,20 +778,20 @@ static int tegra_gem_get_flags(struct drm_device *drm, void *data, static const struct drm_ioctl_desc tegra_drm_ioctls[] = { #ifdef CONFIG_DRM_TEGRA_STAGING - DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, DRM_UNLOCKED), - DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), + DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), + DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), + DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), + DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), + DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), #endif }; @@ -822,7 +822,8 @@ static struct drm_crtc *tegra_crtc_from_pipe(struct drm_device *drm, return NULL; } -static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, int pipe) +static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, + unsigned int pipe) { struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); struct tegra_dc *dc = to_tegra_dc(crtc); @@ -833,7 +834,7 @@ static u32 tegra_drm_get_vblank_counter(struct drm_device *drm, int pipe) return tegra_dc_get_vblank_counter(dc); } -static int tegra_drm_enable_vblank(struct drm_device *drm, int pipe) +static int tegra_drm_enable_vblank(struct drm_device *drm, unsigned int pipe) { struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); struct tegra_dc *dc = to_tegra_dc(crtc); @@ -846,7 +847,7 @@ static int tegra_drm_enable_vblank(struct drm_device *drm, int pipe) return 0; } -static void tegra_drm_disable_vblank(struct drm_device *drm, int pipe) +static void tegra_drm_disable_vblank(struct drm_device *drm, unsigned int pipe) { struct drm_crtc *crtc = tegra_crtc_from_pipe(drm, pipe); struct tegra_dc *dc = to_tegra_dc(crtc); diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c index 07c844b746b4..1004075fd088 100644 --- a/drivers/gpu/drm/tegra/fb.c +++ b/drivers/gpu/drm/tegra/fb.c @@ -341,7 +341,6 @@ fini: static void tegra_fbdev_exit(struct tegra_fbdev *fbdev) { - drm_fb_helper_unregister_fbi(&fbdev->base); drm_fb_helper_release_fbi(&fbdev->base); diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c index 0f283a3b932c..876cad58b1f9 100644 --- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c +++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c @@ -425,13 +425,13 @@ static void enable_vblank(struct drm_device *dev, bool enable) tilcdc_clear(dev, reg, mask); } -static int tilcdc_enable_vblank(struct drm_device *dev, int crtc) +static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe) { enable_vblank(dev, true); return 0; } -static void tilcdc_disable_vblank(struct drm_device *dev, int crtc) +static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe) { enable_vblank(dev, false); } @@ -563,7 +563,7 @@ static struct drm_driver tilcdc_driver = { .irq_preinstall = tilcdc_irq_preinstall, .irq_postinstall = tilcdc_irq_postinstall, .irq_uninstall = tilcdc_irq_uninstall, - .get_vblank_counter = drm_vblank_count, + .get_vblank_counter = drm_vblank_no_hw_counter, .enable_vblank = tilcdc_enable_vblank, .disable_vblank = tilcdc_disable_vblank, .gem_free_object = drm_gem_cma_free_object, diff --git a/drivers/gpu/drm/vc4/Kconfig b/drivers/gpu/drm/vc4/Kconfig new file mode 100644 index 000000000000..e502802d74b6 --- /dev/null +++ b/drivers/gpu/drm/vc4/Kconfig @@ -0,0 +1,13 @@ +config DRM_VC4 + tristate "Broadcom VC4 Graphics" + depends on ARCH_BCM2835 || COMPILE_TEST + depends on DRM + select DRM_KMS_HELPER + select DRM_KMS_CMA_HELPER + help + Choose this option if you have a system that has a Broadcom + VC4 GPU, such as the Raspberry Pi or other BCM2708/BCM2835. + + This driver requires that "avoid_warnings=2" be present in + the config.txt for the firmware, to keep it from smashing + our display setup. diff --git a/drivers/gpu/drm/vc4/Makefile b/drivers/gpu/drm/vc4/Makefile new file mode 100644 index 000000000000..32b4f9cd8f52 --- /dev/null +++ b/drivers/gpu/drm/vc4/Makefile @@ -0,0 +1,17 @@ +ccflags-y := -Iinclude/drm + +# Please keep these build lists sorted! + +# core driver code +vc4-y := \ + vc4_bo.o \ + vc4_crtc.o \ + vc4_drv.o \ + vc4_kms.o \ + vc4_hdmi.o \ + vc4_hvs.o \ + vc4_plane.o + +vc4-$(CONFIG_DEBUG_FS) += vc4_debugfs.o + +obj-$(CONFIG_DRM_VC4) += vc4.o diff --git a/drivers/gpu/drm/vc4/vc4_bo.c b/drivers/gpu/drm/vc4/vc4_bo.c new file mode 100644 index 000000000000..ab9f5108ae1a --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_bo.c @@ -0,0 +1,52 @@ +/* + * Copyright © 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* DOC: VC4 GEM BO management support. + * + * The VC4 GPU architecture (both scanout and rendering) has direct + * access to system memory with no MMU in between. To support it, we + * use the GEM CMA helper functions to allocate contiguous ranges of + * physical memory for our BOs. + */ + +#include "vc4_drv.h" + +struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size) +{ + struct drm_gem_cma_object *cma_obj; + + cma_obj = drm_gem_cma_create(dev, size); + if (IS_ERR(cma_obj)) + return NULL; + else + return to_vc4_bo(&cma_obj->base); +} + +int vc4_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args) +{ + int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); + struct vc4_bo *bo = NULL; + int ret; + + if (args->pitch < min_pitch) + args->pitch = min_pitch; + + if (args->size < args->pitch * args->height) + args->size = args->pitch * args->height; + + bo = vc4_bo_create(dev, roundup(args->size, PAGE_SIZE)); + if (!bo) + return -ENOMEM; + + ret = drm_gem_handle_create(file_priv, &bo->base.base, &args->handle); + drm_gem_object_unreference_unlocked(&bo->base.base); + + return ret; +} diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c new file mode 100644 index 000000000000..7a9f4768591e --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -0,0 +1,672 @@ +/* + * Copyright (C) 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/** + * DOC: VC4 CRTC module + * + * In VC4, the Pixel Valve is what most closely corresponds to the + * DRM's concept of a CRTC. The PV generates video timings from the + * output's clock plus its configuration. It pulls scaled pixels from + * the HVS at that timing, and feeds it to the encoder. + * + * However, the DRM CRTC also collects the configuration of all the + * DRM planes attached to it. As a result, this file also manages + * setup of the VC4 HVS's display elements on the CRTC. + * + * The 2835 has 3 different pixel valves. pv0 in the audio power + * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the + * image domain can feed either HDMI or the SDTV controller. The + * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for + * SDTV, etc.) according to which output type is chosen in the mux. + * + * For power management, the pixel valve's registers are all clocked + * by the AXI clock, while the timings and FIFOs make use of the + * output-specific clock. Since the encoders also directly consume + * the CPRMAN clocks, and know what timings they need, they are the + * ones that set the clock. + */ + +#include "drm_atomic.h" +#include "drm_atomic_helper.h" +#include "drm_crtc_helper.h" +#include "linux/clk.h" +#include "linux/component.h" +#include "linux/of_device.h" +#include "vc4_drv.h" +#include "vc4_regs.h" + +struct vc4_crtc { + struct drm_crtc base; + const struct vc4_crtc_data *data; + void __iomem *regs; + + /* Which HVS channel we're using for our CRTC. */ + int channel; + + /* Pointer to the actual hardware display list memory for the + * crtc. + */ + u32 __iomem *dlist; + + u32 dlist_size; /* in dwords */ + + struct drm_pending_vblank_event *event; +}; + +static inline struct vc4_crtc * +to_vc4_crtc(struct drm_crtc *crtc) +{ + return (struct vc4_crtc *)crtc; +} + +struct vc4_crtc_data { + /* Which channel of the HVS this pixelvalve sources from. */ + int hvs_channel; + + enum vc4_encoder_type encoder0_type; + enum vc4_encoder_type encoder1_type; +}; + +#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) +#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) + +#define CRTC_REG(reg) { reg, #reg } +static const struct { + u32 reg; + const char *name; +} crtc_regs[] = { + CRTC_REG(PV_CONTROL), + CRTC_REG(PV_V_CONTROL), + CRTC_REG(PV_VSYNCD), + CRTC_REG(PV_HORZA), + CRTC_REG(PV_HORZB), + CRTC_REG(PV_VERTA), + CRTC_REG(PV_VERTB), + CRTC_REG(PV_VERTA_EVEN), + CRTC_REG(PV_VERTB_EVEN), + CRTC_REG(PV_INTEN), + CRTC_REG(PV_INTSTAT), + CRTC_REG(PV_STAT), + CRTC_REG(PV_HACT_ACT), +}; + +static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { + DRM_INFO("0x%04x (%s): 0x%08x\n", + crtc_regs[i].reg, crtc_regs[i].name, + CRTC_READ(crtc_regs[i].reg)); + } +} + +#ifdef CONFIG_DEBUG_FS +int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + int crtc_index = (uintptr_t)node->info_ent->data; + struct drm_crtc *crtc; + struct vc4_crtc *vc4_crtc; + int i; + + i = 0; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + if (i == crtc_index) + break; + i++; + } + if (!crtc) + return 0; + vc4_crtc = to_vc4_crtc(crtc); + + for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { + seq_printf(m, "%s (0x%04x): 0x%08x\n", + crtc_regs[i].name, crtc_regs[i].reg, + CRTC_READ(crtc_regs[i].reg)); + } + + return 0; +} +#endif + +static void vc4_crtc_destroy(struct drm_crtc *crtc) +{ + drm_crtc_cleanup(crtc); +} + +static u32 vc4_get_fifo_full_level(u32 format) +{ + static const u32 fifo_len_bytes = 64; + static const u32 hvs_latency_pix = 6; + + switch (format) { + case PV_CONTROL_FORMAT_DSIV_16: + case PV_CONTROL_FORMAT_DSIC_16: + return fifo_len_bytes - 2 * hvs_latency_pix; + case PV_CONTROL_FORMAT_DSIV_18: + return fifo_len_bytes - 14; + case PV_CONTROL_FORMAT_24: + case PV_CONTROL_FORMAT_DSIV_24: + default: + return fifo_len_bytes - 3 * hvs_latency_pix; + } +} + +/* + * Returns the clock select bit for the connector attached to the + * CRTC. + */ +static int vc4_get_clock_select(struct drm_crtc *crtc) +{ + struct drm_connector *connector; + + drm_for_each_connector(connector, crtc->dev) { + if (connector && connector->state->crtc == crtc) { + struct drm_encoder *encoder = connector->encoder; + struct vc4_encoder *vc4_encoder = + to_vc4_encoder(encoder); + + return vc4_encoder->clock_select; + } + } + + return -1; +} + +static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) +{ + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_crtc_state *state = crtc->state; + struct drm_display_mode *mode = &state->adjusted_mode; + bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; + u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0)); + u32 format = PV_CONTROL_FORMAT_24; + bool debug_dump_regs = false; + int clock_select = vc4_get_clock_select(crtc); + + if (debug_dump_regs) { + DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); + vc4_crtc_dump_regs(vc4_crtc); + } + + /* Reset the PV fifo. */ + CRTC_WRITE(PV_CONTROL, 0); + CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); + CRTC_WRITE(PV_CONTROL, 0); + + CRTC_WRITE(PV_HORZA, + VC4_SET_FIELD(mode->htotal - mode->hsync_end, + PV_HORZA_HBP) | + VC4_SET_FIELD(mode->hsync_end - mode->hsync_start, + PV_HORZA_HSYNC)); + CRTC_WRITE(PV_HORZB, + VC4_SET_FIELD(mode->hsync_start - mode->hdisplay, + PV_HORZB_HFP) | + VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE)); + + if (interlace) { + CRTC_WRITE(PV_VERTA_EVEN, + VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1, + PV_VERTA_VBP) | + VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, + PV_VERTA_VSYNC)); + CRTC_WRITE(PV_VERTB_EVEN, + VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, + PV_VERTB_VFP) | + VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE)); + } + + CRTC_WRITE(PV_HACT_ACT, mode->hdisplay); + + CRTC_WRITE(PV_V_CONTROL, + PV_VCONTROL_CONTINUOUS | + (interlace ? PV_VCONTROL_INTERLACE : 0)); + + CRTC_WRITE(PV_CONTROL, + VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | + VC4_SET_FIELD(vc4_get_fifo_full_level(format), + PV_CONTROL_FIFO_LEVEL) | + PV_CONTROL_CLR_AT_START | + PV_CONTROL_TRIGGER_UNDERFLOW | + PV_CONTROL_WAIT_HSTART | + VC4_SET_FIELD(clock_select, PV_CONTROL_CLK_SELECT) | + PV_CONTROL_FIFO_CLR | + PV_CONTROL_EN); + + if (debug_dump_regs) { + DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc)); + vc4_crtc_dump_regs(vc4_crtc); + } +} + +static void require_hvs_enabled(struct drm_device *dev) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + + WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != + SCALER_DISPCTRL_ENABLE); +} + +static void vc4_crtc_disable(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + u32 chan = vc4_crtc->channel; + int ret; + require_hvs_enabled(dev); + + CRTC_WRITE(PV_V_CONTROL, + CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); + ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); + WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); + + if (HVS_READ(SCALER_DISPCTRLX(chan)) & + SCALER_DISPCTRLX_ENABLE) { + HVS_WRITE(SCALER_DISPCTRLX(chan), + SCALER_DISPCTRLX_RESET); + + /* While the docs say that reset is self-clearing, it + * seems it doesn't actually. + */ + HVS_WRITE(SCALER_DISPCTRLX(chan), 0); + } + + /* Once we leave, the scaler should be disabled and its fifo empty. */ + + WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); + + WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), + SCALER_DISPSTATX_MODE) != + SCALER_DISPSTATX_MODE_DISABLED); + + WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & + (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != + SCALER_DISPSTATX_EMPTY); +} + +static void vc4_crtc_enable(struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_crtc_state *state = crtc->state; + struct drm_display_mode *mode = &state->adjusted_mode; + + require_hvs_enabled(dev); + + /* Turn on the scaler, which will wait for vstart to start + * compositing. + */ + HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), + VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) | + VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) | + SCALER_DISPCTRLX_ENABLE); + + /* Turn on the pixel valve, which will emit the vstart signal. */ + CRTC_WRITE(PV_V_CONTROL, + CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); +} + +static int vc4_crtc_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct drm_device *dev = crtc->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct drm_plane *plane; + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + u32 dlist_count = 0; + + /* The pixelvalve can only feed one encoder (and encoders are + * 1:1 with connectors.) + */ + if (drm_atomic_connectors_for_crtc(state->state, crtc) > 1) + return -EINVAL; + + drm_atomic_crtc_state_for_each_plane(plane, state) { + struct drm_plane_state *plane_state = + state->state->plane_states[drm_plane_index(plane)]; + + /* plane might not have changed, in which case take + * current state: + */ + if (!plane_state) + plane_state = plane->state; + + dlist_count += vc4_plane_dlist_size(plane_state); + } + + dlist_count++; /* Account for SCALER_CTL0_END. */ + + if (!vc4_crtc->dlist || dlist_count > vc4_crtc->dlist_size) { + vc4_crtc->dlist = ((u32 __iomem *)vc4->hvs->dlist + + HVS_BOOTLOADER_DLIST_END); + vc4_crtc->dlist_size = ((SCALER_DLIST_SIZE >> 2) - + HVS_BOOTLOADER_DLIST_END); + + if (dlist_count > vc4_crtc->dlist_size) { + DRM_DEBUG_KMS("dlist too large for CRTC (%d > %d).\n", + dlist_count, vc4_crtc->dlist_size); + return -EINVAL; + } + } + + return 0; +} + +static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, + struct drm_crtc_state *old_state) +{ + struct drm_device *dev = crtc->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_plane *plane; + bool debug_dump_regs = false; + u32 __iomem *dlist_next = vc4_crtc->dlist; + + if (debug_dump_regs) { + DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); + vc4_hvs_dump_state(dev); + } + + /* Copy all the active planes' dlist contents to the hardware dlist. + * + * XXX: If the new display list was large enough that it + * overlapped a currently-read display list, we need to do + * something like disable scanout before putting in the new + * list. For now, we're safe because we only have the two + * planes. + */ + drm_atomic_crtc_for_each_plane(plane, crtc) { + dlist_next += vc4_plane_write_dlist(plane, dlist_next); + } + + if (dlist_next == vc4_crtc->dlist) { + /* If no planes were enabled, use the SCALER_CTL0_END + * at the start of the display list memory (in the + * bootloader section). We'll rewrite that + * SCALER_CTL0_END, just in case, though. + */ + writel(SCALER_CTL0_END, vc4->hvs->dlist); + HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 0); + } else { + writel(SCALER_CTL0_END, dlist_next); + dlist_next++; + + HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), + (u32 *)vc4_crtc->dlist - (u32 *)vc4->hvs->dlist); + + /* Make the next display list start after ours. */ + vc4_crtc->dlist_size -= (dlist_next - vc4_crtc->dlist); + vc4_crtc->dlist = dlist_next; + } + + if (debug_dump_regs) { + DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); + vc4_hvs_dump_state(dev); + } + + if (crtc->state->event) { + unsigned long flags; + + crtc->state->event->pipe = drm_crtc_index(crtc); + + WARN_ON(drm_crtc_vblank_get(crtc) != 0); + + spin_lock_irqsave(&dev->event_lock, flags); + vc4_crtc->event = crtc->state->event; + spin_unlock_irqrestore(&dev->event_lock, flags); + crtc->state->event = NULL; + } +} + +int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; + + CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); + + return 0; +} + +void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + struct vc4_crtc *vc4_crtc = vc4->crtc[crtc_id]; + + CRTC_WRITE(PV_INTEN, 0); +} + +static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) +{ + struct drm_crtc *crtc = &vc4_crtc->base; + struct drm_device *dev = crtc->dev; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + if (vc4_crtc->event) { + drm_crtc_send_vblank_event(crtc, vc4_crtc->event); + vc4_crtc->event = NULL; + } + spin_unlock_irqrestore(&dev->event_lock, flags); +} + +static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) +{ + struct vc4_crtc *vc4_crtc = data; + u32 stat = CRTC_READ(PV_INTSTAT); + irqreturn_t ret = IRQ_NONE; + + if (stat & PV_INT_VFP_START) { + CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); + drm_crtc_handle_vblank(&vc4_crtc->base); + vc4_crtc_handle_page_flip(vc4_crtc); + ret = IRQ_HANDLED; + } + + return ret; +} + +static const struct drm_crtc_funcs vc4_crtc_funcs = { + .set_config = drm_atomic_helper_set_config, + .destroy = vc4_crtc_destroy, + .page_flip = drm_atomic_helper_page_flip, + .set_property = NULL, + .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ + .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ + .reset = drm_atomic_helper_crtc_reset, + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +}; + +static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { + .mode_set_nofb = vc4_crtc_mode_set_nofb, + .disable = vc4_crtc_disable, + .enable = vc4_crtc_enable, + .atomic_check = vc4_crtc_atomic_check, + .atomic_flush = vc4_crtc_atomic_flush, +}; + +/* Frees the page flip event when the DRM device is closed with the + * event still outstanding. + */ +void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) +{ + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_device *dev = crtc->dev; + unsigned long flags; + + spin_lock_irqsave(&dev->event_lock, flags); + + if (vc4_crtc->event && vc4_crtc->event->base.file_priv == file) { + vc4_crtc->event->base.destroy(&vc4_crtc->event->base); + drm_crtc_vblank_put(crtc); + vc4_crtc->event = NULL; + } + + spin_unlock_irqrestore(&dev->event_lock, flags); +} + +static const struct vc4_crtc_data pv0_data = { + .hvs_channel = 0, + .encoder0_type = VC4_ENCODER_TYPE_DSI0, + .encoder1_type = VC4_ENCODER_TYPE_DPI, +}; + +static const struct vc4_crtc_data pv1_data = { + .hvs_channel = 2, + .encoder0_type = VC4_ENCODER_TYPE_DSI1, + .encoder1_type = VC4_ENCODER_TYPE_SMI, +}; + +static const struct vc4_crtc_data pv2_data = { + .hvs_channel = 1, + .encoder0_type = VC4_ENCODER_TYPE_VEC, + .encoder1_type = VC4_ENCODER_TYPE_HDMI, +}; + +static const struct of_device_id vc4_crtc_dt_match[] = { + { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data }, + { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data }, + { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data }, + {} +}; + +static void vc4_set_crtc_possible_masks(struct drm_device *drm, + struct drm_crtc *crtc) +{ + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_encoder *encoder; + + drm_for_each_encoder(encoder, drm) { + struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); + + if (vc4_encoder->type == vc4_crtc->data->encoder0_type) { + vc4_encoder->clock_select = 0; + encoder->possible_crtcs |= drm_crtc_mask(crtc); + } else if (vc4_encoder->type == vc4_crtc->data->encoder1_type) { + vc4_encoder->clock_select = 1; + encoder->possible_crtcs |= drm_crtc_mask(crtc); + } + } +} + +static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = to_vc4_dev(drm); + struct vc4_crtc *vc4_crtc; + struct drm_crtc *crtc; + struct drm_plane *primary_plane, *cursor_plane; + const struct of_device_id *match; + int ret; + + vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); + if (!vc4_crtc) + return -ENOMEM; + crtc = &vc4_crtc->base; + + match = of_match_device(vc4_crtc_dt_match, dev); + if (!match) + return -ENODEV; + vc4_crtc->data = match->data; + + vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); + if (IS_ERR(vc4_crtc->regs)) + return PTR_ERR(vc4_crtc->regs); + + /* For now, we create just the primary and the legacy cursor + * planes. We should be able to stack more planes on easily, + * but to do that we would need to compute the bandwidth + * requirement of the plane configuration, and reject ones + * that will take too much. + */ + primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); + if (!primary_plane) { + dev_err(dev, "failed to construct primary plane\n"); + ret = PTR_ERR(primary_plane); + goto err; + } + + cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); + if (!cursor_plane) { + dev_err(dev, "failed to construct cursor plane\n"); + ret = PTR_ERR(cursor_plane); + goto err_primary; + } + + drm_crtc_init_with_planes(drm, crtc, primary_plane, cursor_plane, + &vc4_crtc_funcs); + drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); + primary_plane->crtc = crtc; + cursor_plane->crtc = crtc; + vc4->crtc[drm_crtc_index(crtc)] = vc4_crtc; + vc4_crtc->channel = vc4_crtc->data->hvs_channel; + + CRTC_WRITE(PV_INTEN, 0); + CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); + ret = devm_request_irq(dev, platform_get_irq(pdev, 0), + vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc); + if (ret) + goto err_cursor; + + vc4_set_crtc_possible_masks(drm, crtc); + + platform_set_drvdata(pdev, vc4_crtc); + + return 0; + +err_cursor: + cursor_plane->funcs->destroy(cursor_plane); +err_primary: + primary_plane->funcs->destroy(primary_plane); +err: + return ret; +} + +static void vc4_crtc_unbind(struct device *dev, struct device *master, + void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); + + vc4_crtc_destroy(&vc4_crtc->base); + + CRTC_WRITE(PV_INTEN, 0); + + platform_set_drvdata(pdev, NULL); +} + +static const struct component_ops vc4_crtc_ops = { + .bind = vc4_crtc_bind, + .unbind = vc4_crtc_unbind, +}; + +static int vc4_crtc_dev_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &vc4_crtc_ops); +} + +static int vc4_crtc_dev_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &vc4_crtc_ops); + return 0; +} + +struct platform_driver vc4_crtc_driver = { + .probe = vc4_crtc_dev_probe, + .remove = vc4_crtc_dev_remove, + .driver = { + .name = "vc4_crtc", + .of_match_table = vc4_crtc_dt_match, + }, +}; diff --git a/drivers/gpu/drm/vc4/vc4_debugfs.c b/drivers/gpu/drm/vc4/vc4_debugfs.c new file mode 100644 index 000000000000..4297b0a5b74e --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_debugfs.c @@ -0,0 +1,39 @@ +/* + * Copyright © 2014 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/seq_file.h> +#include <linux/circ_buf.h> +#include <linux/ctype.h> +#include <linux/debugfs.h> +#include <drm/drmP.h> + +#include "vc4_drv.h" +#include "vc4_regs.h" + +static const struct drm_info_list vc4_debugfs_list[] = { + {"hdmi_regs", vc4_hdmi_debugfs_regs, 0}, + {"hvs_regs", vc4_hvs_debugfs_regs, 0}, + {"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0}, + {"crtc1_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)1}, + {"crtc2_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)2}, +}; + +#define VC4_DEBUGFS_ENTRIES ARRAY_SIZE(vc4_debugfs_list) + +int +vc4_debugfs_init(struct drm_minor *minor) +{ + return drm_debugfs_create_files(vc4_debugfs_list, VC4_DEBUGFS_ENTRIES, + minor->debugfs_root, minor); +} + +void +vc4_debugfs_cleanup(struct drm_minor *minor) +{ + drm_debugfs_remove_files(vc4_debugfs_list, VC4_DEBUGFS_ENTRIES, minor); +} diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c new file mode 100644 index 000000000000..6e730605edcc --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_drv.c @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2014-2015 Broadcom + * Copyright (C) 2013 Red Hat + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/clk.h> +#include <linux/component.h> +#include <linux/device.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include "drm_fb_cma_helper.h" + +#include "vc4_drv.h" +#include "vc4_regs.h" + +#define DRIVER_NAME "vc4" +#define DRIVER_DESC "Broadcom VC4 graphics" +#define DRIVER_DATE "20140616" +#define DRIVER_MAJOR 0 +#define DRIVER_MINOR 0 +#define DRIVER_PATCHLEVEL 0 + +/* Helper function for mapping the regs on a platform device. */ +void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index) +{ + struct resource *res; + void __iomem *map; + + res = platform_get_resource(dev, IORESOURCE_MEM, index); + map = devm_ioremap_resource(&dev->dev, res); + if (IS_ERR(map)) { + DRM_ERROR("Failed to map registers: %ld\n", PTR_ERR(map)); + return map; + } + + return map; +} + +static void vc4_drm_preclose(struct drm_device *dev, struct drm_file *file) +{ + struct drm_crtc *crtc; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) + vc4_cancel_page_flip(crtc, file); +} + +static void vc4_lastclose(struct drm_device *dev) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + + if (vc4->fbdev) + drm_fbdev_cma_restore_mode(vc4->fbdev); +} + +static const struct file_operations vc4_drm_fops = { + .owner = THIS_MODULE, + .open = drm_open, + .release = drm_release, + .unlocked_ioctl = drm_ioctl, + .mmap = drm_gem_cma_mmap, + .poll = drm_poll, + .read = drm_read, +#ifdef CONFIG_COMPAT + .compat_ioctl = drm_compat_ioctl, +#endif + .llseek = noop_llseek, +}; + +static const struct drm_ioctl_desc vc4_drm_ioctls[] = { +}; + +static struct drm_driver vc4_drm_driver = { + .driver_features = (DRIVER_MODESET | + DRIVER_ATOMIC | + DRIVER_GEM | + DRIVER_PRIME), + .lastclose = vc4_lastclose, + .preclose = vc4_drm_preclose, + + .enable_vblank = vc4_enable_vblank, + .disable_vblank = vc4_disable_vblank, + .get_vblank_counter = drm_vblank_count, + +#if defined(CONFIG_DEBUG_FS) + .debugfs_init = vc4_debugfs_init, + .debugfs_cleanup = vc4_debugfs_cleanup, +#endif + + .gem_free_object = drm_gem_cma_free_object, + .gem_vm_ops = &drm_gem_cma_vm_ops, + + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_export = drm_gem_prime_export, + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table, + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table, + .gem_prime_vmap = drm_gem_cma_prime_vmap, + .gem_prime_vunmap = drm_gem_cma_prime_vunmap, + .gem_prime_mmap = drm_gem_cma_prime_mmap, + + .dumb_create = vc4_dumb_create, + .dumb_map_offset = drm_gem_cma_dumb_map_offset, + .dumb_destroy = drm_gem_dumb_destroy, + + .ioctls = vc4_drm_ioctls, + .num_ioctls = ARRAY_SIZE(vc4_drm_ioctls), + .fops = &vc4_drm_fops, + + .name = DRIVER_NAME, + .desc = DRIVER_DESC, + .date = DRIVER_DATE, + .major = DRIVER_MAJOR, + .minor = DRIVER_MINOR, + .patchlevel = DRIVER_PATCHLEVEL, +}; + +static int compare_dev(struct device *dev, void *data) +{ + return dev == data; +} + +static void vc4_match_add_drivers(struct device *dev, + struct component_match **match, + struct platform_driver *const *drivers, + int count) +{ + int i; + + for (i = 0; i < count; i++) { + struct device_driver *drv = &drivers[i]->driver; + struct device *p = NULL, *d; + + while ((d = bus_find_device(&platform_bus_type, p, drv, + (void *)platform_bus_type.match))) { + put_device(p); + component_match_add(dev, match, compare_dev, d); + p = d; + } + put_device(p); + } +} + +static int vc4_drm_bind(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm; + struct drm_connector *connector; + struct vc4_dev *vc4; + int ret = 0; + + dev->coherent_dma_mask = DMA_BIT_MASK(32); + + vc4 = devm_kzalloc(dev, sizeof(*vc4), GFP_KERNEL); + if (!vc4) + return -ENOMEM; + + drm = drm_dev_alloc(&vc4_drm_driver, dev); + if (!drm) + return -ENOMEM; + platform_set_drvdata(pdev, drm); + vc4->dev = drm; + drm->dev_private = vc4; + + drm_dev_set_unique(drm, dev_name(dev)); + + drm_mode_config_init(drm); + if (ret) + goto unref; + + ret = component_bind_all(dev, drm); + if (ret) + goto unref; + + ret = drm_dev_register(drm, 0); + if (ret < 0) + goto unbind_all; + + /* Connector registration has to occur after DRM device + * registration, because it creates sysfs entries based on the + * DRM device. + */ + list_for_each_entry(connector, &drm->mode_config.connector_list, head) { + ret = drm_connector_register(connector); + if (ret) + goto unregister; + } + + vc4_kms_load(drm); + + return 0; + +unregister: + drm_dev_unregister(drm); +unbind_all: + component_unbind_all(dev, drm); +unref: + drm_dev_unref(drm); + return ret; +} + +static void vc4_drm_unbind(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = platform_get_drvdata(pdev); + struct vc4_dev *vc4 = to_vc4_dev(drm); + + if (vc4->fbdev) + drm_fbdev_cma_fini(vc4->fbdev); + + drm_mode_config_cleanup(drm); + + drm_put_dev(drm); +} + +static const struct component_master_ops vc4_drm_ops = { + .bind = vc4_drm_bind, + .unbind = vc4_drm_unbind, +}; + +static struct platform_driver *const component_drivers[] = { + &vc4_hdmi_driver, + &vc4_crtc_driver, + &vc4_hvs_driver, +}; + +static int vc4_platform_drm_probe(struct platform_device *pdev) +{ + struct component_match *match = NULL; + struct device *dev = &pdev->dev; + + vc4_match_add_drivers(dev, &match, + component_drivers, ARRAY_SIZE(component_drivers)); + + return component_master_add_with_match(dev, &vc4_drm_ops, match); +} + +static int vc4_platform_drm_remove(struct platform_device *pdev) +{ + component_master_del(&pdev->dev, &vc4_drm_ops); + + return 0; +} + +static const struct of_device_id vc4_of_match[] = { + { .compatible = "brcm,bcm2835-vc4", }, + {}, +}; +MODULE_DEVICE_TABLE(of, vc4_of_match); + +static struct platform_driver vc4_platform_driver = { + .probe = vc4_platform_drm_probe, + .remove = vc4_platform_drm_remove, + .driver = { + .name = "vc4-drm", + .owner = THIS_MODULE, + .of_match_table = vc4_of_match, + }, +}; + +static int __init vc4_drm_register(void) +{ + int i, ret; + + for (i = 0; i < ARRAY_SIZE(component_drivers); i++) { + ret = platform_driver_register(component_drivers[i]); + if (ret) { + while (--i >= 0) + platform_driver_unregister(component_drivers[i]); + return ret; + } + } + return platform_driver_register(&vc4_platform_driver); +} + +static void __exit vc4_drm_unregister(void) +{ + int i; + + for (i = ARRAY_SIZE(component_drivers) - 1; i >= 0; i--) + platform_driver_unregister(component_drivers[i]); + + platform_driver_unregister(&vc4_platform_driver); +} + +module_init(vc4_drm_register); +module_exit(vc4_drm_unregister); + +MODULE_ALIAS("platform:vc4-drm"); +MODULE_DESCRIPTION("Broadcom VC4 DRM Driver"); +MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h new file mode 100644 index 000000000000..fd8319fa682e --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "drmP.h" +#include "drm_gem_cma_helper.h" + +struct vc4_dev { + struct drm_device *dev; + + struct vc4_hdmi *hdmi; + struct vc4_hvs *hvs; + struct vc4_crtc *crtc[3]; + + struct drm_fbdev_cma *fbdev; +}; + +static inline struct vc4_dev * +to_vc4_dev(struct drm_device *dev) +{ + return (struct vc4_dev *)dev->dev_private; +} + +struct vc4_bo { + struct drm_gem_cma_object base; +}; + +static inline struct vc4_bo * +to_vc4_bo(struct drm_gem_object *bo) +{ + return (struct vc4_bo *)bo; +} + +struct vc4_hvs { + struct platform_device *pdev; + void __iomem *regs; + void __iomem *dlist; +}; + +struct vc4_plane { + struct drm_plane base; +}; + +static inline struct vc4_plane * +to_vc4_plane(struct drm_plane *plane) +{ + return (struct vc4_plane *)plane; +} + +enum vc4_encoder_type { + VC4_ENCODER_TYPE_HDMI, + VC4_ENCODER_TYPE_VEC, + VC4_ENCODER_TYPE_DSI0, + VC4_ENCODER_TYPE_DSI1, + VC4_ENCODER_TYPE_SMI, + VC4_ENCODER_TYPE_DPI, +}; + +struct vc4_encoder { + struct drm_encoder base; + enum vc4_encoder_type type; + u32 clock_select; +}; + +static inline struct vc4_encoder * +to_vc4_encoder(struct drm_encoder *encoder) +{ + return container_of(encoder, struct vc4_encoder, base); +} + +#define HVS_READ(offset) readl(vc4->hvs->regs + offset) +#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) + +/** + * _wait_for - magic (register) wait macro + * + * Does the right thing for modeset paths when run under kdgb or similar atomic + * contexts. Note that it's important that we check the condition again after + * having timed out, since the timeout could be due to preemption or similar and + * we've never had a chance to check the condition before the timeout. + */ +#define _wait_for(COND, MS, W) ({ \ + unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ + int ret__ = 0; \ + while (!(COND)) { \ + if (time_after(jiffies, timeout__)) { \ + if (!(COND)) \ + ret__ = -ETIMEDOUT; \ + break; \ + } \ + if (W && drm_can_sleep()) { \ + msleep(W); \ + } else { \ + cpu_relax(); \ + } \ + } \ + ret__; \ +}) + +#define wait_for(COND, MS) _wait_for(COND, MS, 1) + +/* vc4_bo.c */ +void vc4_free_object(struct drm_gem_object *gem_obj); +struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size); +int vc4_dumb_create(struct drm_file *file_priv, + struct drm_device *dev, + struct drm_mode_create_dumb *args); +struct dma_buf *vc4_prime_export(struct drm_device *dev, + struct drm_gem_object *obj, int flags); + +/* vc4_crtc.c */ +extern struct platform_driver vc4_crtc_driver; +int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id); +void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id); +void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); +int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); + +/* vc4_debugfs.c */ +int vc4_debugfs_init(struct drm_minor *minor); +void vc4_debugfs_cleanup(struct drm_minor *minor); + +/* vc4_drv.c */ +void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); + +/* vc4_hdmi.c */ +extern struct platform_driver vc4_hdmi_driver; +int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); + +/* vc4_hvs.c */ +extern struct platform_driver vc4_hvs_driver; +void vc4_hvs_dump_state(struct drm_device *dev); +int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); + +/* vc4_kms.c */ +int vc4_kms_load(struct drm_device *dev); + +/* vc4_plane.c */ +struct drm_plane *vc4_plane_init(struct drm_device *dev, + enum drm_plane_type type); +u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); +u32 vc4_plane_dlist_size(struct drm_plane_state *state); diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c new file mode 100644 index 000000000000..da9a36d6e1d1 --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -0,0 +1,590 @@ +/* + * Copyright (C) 2015 Broadcom + * Copyright (c) 2014 The Linux Foundation. All rights reserved. + * Copyright (C) 2013 Red Hat + * Author: Rob Clark <robdclark@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/** + * DOC: VC4 Falcon HDMI module + * + * The HDMI core has a state machine and a PHY. Most of the unit + * operates off of the HSM clock from CPRMAN. It also internally uses + * the PLLH_PIX clock for the PHY. + */ + +#include "drm_atomic_helper.h" +#include "drm_crtc_helper.h" +#include "drm_edid.h" +#include "linux/clk.h" +#include "linux/component.h" +#include "linux/i2c.h" +#include "linux/of_gpio.h" +#include "linux/of_platform.h" +#include "vc4_drv.h" +#include "vc4_regs.h" + +/* General HDMI hardware state. */ +struct vc4_hdmi { + struct platform_device *pdev; + + struct drm_encoder *encoder; + struct drm_connector *connector; + + struct i2c_adapter *ddc; + void __iomem *hdmicore_regs; + void __iomem *hd_regs; + int hpd_gpio; + + struct clk *pixel_clock; + struct clk *hsm_clock; +}; + +#define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) +#define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) +#define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) +#define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) + +/* VC4 HDMI encoder KMS struct */ +struct vc4_hdmi_encoder { + struct vc4_encoder base; + bool hdmi_monitor; +}; + +static inline struct vc4_hdmi_encoder * +to_vc4_hdmi_encoder(struct drm_encoder *encoder) +{ + return container_of(encoder, struct vc4_hdmi_encoder, base.base); +} + +/* VC4 HDMI connector KMS struct */ +struct vc4_hdmi_connector { + struct drm_connector base; + + /* Since the connector is attached to just the one encoder, + * this is the reference to it so we can do the best_encoder() + * hook. + */ + struct drm_encoder *encoder; +}; + +static inline struct vc4_hdmi_connector * +to_vc4_hdmi_connector(struct drm_connector *connector) +{ + return container_of(connector, struct vc4_hdmi_connector, base); +} + +#define HDMI_REG(reg) { reg, #reg } +static const struct { + u32 reg; + const char *name; +} hdmi_regs[] = { + HDMI_REG(VC4_HDMI_CORE_REV), + HDMI_REG(VC4_HDMI_SW_RESET_CONTROL), + HDMI_REG(VC4_HDMI_HOTPLUG_INT), + HDMI_REG(VC4_HDMI_HOTPLUG), + HDMI_REG(VC4_HDMI_HORZA), + HDMI_REG(VC4_HDMI_HORZB), + HDMI_REG(VC4_HDMI_FIFO_CTL), + HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL), + HDMI_REG(VC4_HDMI_VERTA0), + HDMI_REG(VC4_HDMI_VERTA1), + HDMI_REG(VC4_HDMI_VERTB0), + HDMI_REG(VC4_HDMI_VERTB1), + HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL), +}; + +static const struct { + u32 reg; + const char *name; +} hd_regs[] = { + HDMI_REG(VC4_HD_M_CTL), + HDMI_REG(VC4_HD_MAI_CTL), + HDMI_REG(VC4_HD_VID_CTL), + HDMI_REG(VC4_HD_CSC_CTL), + HDMI_REG(VC4_HD_FRAME_COUNT), +}; + +#ifdef CONFIG_DEBUG_FS +int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { + seq_printf(m, "%s (0x%04x): 0x%08x\n", + hdmi_regs[i].name, hdmi_regs[i].reg, + HDMI_READ(hdmi_regs[i].reg)); + } + + for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { + seq_printf(m, "%s (0x%04x): 0x%08x\n", + hd_regs[i].name, hd_regs[i].reg, + HD_READ(hd_regs[i].reg)); + } + + return 0; +} +#endif /* CONFIG_DEBUG_FS */ + +static void vc4_hdmi_dump_regs(struct drm_device *dev) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { + DRM_INFO("0x%04x (%s): 0x%08x\n", + hdmi_regs[i].reg, hdmi_regs[i].name, + HDMI_READ(hdmi_regs[i].reg)); + } + for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { + DRM_INFO("0x%04x (%s): 0x%08x\n", + hd_regs[i].reg, hd_regs[i].name, + HD_READ(hd_regs[i].reg)); + } +} + +static enum drm_connector_status +vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) +{ + struct drm_device *dev = connector->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + + if (vc4->hdmi->hpd_gpio) { + if (gpio_get_value(vc4->hdmi->hpd_gpio)) + return connector_status_connected; + else + return connector_status_disconnected; + } + + if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) + return connector_status_connected; + else + return connector_status_disconnected; +} + +static void vc4_hdmi_connector_destroy(struct drm_connector *connector) +{ + drm_connector_unregister(connector); + drm_connector_cleanup(connector); +} + +static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) +{ + struct vc4_hdmi_connector *vc4_connector = + to_vc4_hdmi_connector(connector); + struct drm_encoder *encoder = vc4_connector->encoder; + struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); + struct drm_device *dev = connector->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + int ret = 0; + struct edid *edid; + + edid = drm_get_edid(connector, vc4->hdmi->ddc); + if (!edid) + return -ENODEV; + + vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); + drm_mode_connector_update_edid_property(connector, edid); + ret = drm_add_edid_modes(connector, edid); + + return ret; +} + +static struct drm_encoder * +vc4_hdmi_connector_best_encoder(struct drm_connector *connector) +{ + struct vc4_hdmi_connector *hdmi_connector = + to_vc4_hdmi_connector(connector); + return hdmi_connector->encoder; +} + +static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { + .dpms = drm_atomic_helper_connector_dpms, + .detect = vc4_hdmi_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = vc4_hdmi_connector_destroy, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { + .get_modes = vc4_hdmi_connector_get_modes, + .best_encoder = vc4_hdmi_connector_best_encoder, +}; + +static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, + struct drm_encoder *encoder) +{ + struct drm_connector *connector = NULL; + struct vc4_hdmi_connector *hdmi_connector; + int ret = 0; + + hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), + GFP_KERNEL); + if (!hdmi_connector) { + ret = -ENOMEM; + goto fail; + } + connector = &hdmi_connector->base; + + hdmi_connector->encoder = encoder; + + drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); + + connector->polled = (DRM_CONNECTOR_POLL_CONNECT | + DRM_CONNECTOR_POLL_DISCONNECT); + + connector->interlace_allowed = 0; + connector->doublescan_allowed = 0; + + drm_mode_connector_attach_encoder(connector, encoder); + + return connector; + + fail: + if (connector) + vc4_hdmi_connector_destroy(connector); + + return ERR_PTR(ret); +} + +static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); +} + +static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { + .destroy = vc4_hdmi_encoder_destroy, +}; + +static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, + struct drm_display_mode *unadjusted_mode, + struct drm_display_mode *mode) +{ + struct drm_device *dev = encoder->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + bool debug_dump_regs = false; + bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; + bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; + u32 vactive = (mode->vdisplay >> + ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0)); + u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, + VC4_HDMI_VERTA_VSP) | + VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, + VC4_HDMI_VERTA_VFP) | + VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL)); + u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | + VC4_SET_FIELD(mode->vtotal - mode->vsync_end, + VC4_HDMI_VERTB_VBP)); + + if (debug_dump_regs) { + DRM_INFO("HDMI regs before:\n"); + vc4_hdmi_dump_regs(dev); + } + + HD_WRITE(VC4_HD_VID_CTL, 0); + + clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000); + + HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, + HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | + VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | + VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); + + HDMI_WRITE(VC4_HDMI_HORZA, + (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | + (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | + VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP)); + + HDMI_WRITE(VC4_HDMI_HORZB, + VC4_SET_FIELD(mode->htotal - mode->hsync_end, + VC4_HDMI_HORZB_HBP) | + VC4_SET_FIELD(mode->hsync_end - mode->hsync_start, + VC4_HDMI_HORZB_HSP) | + VC4_SET_FIELD(mode->hsync_start - mode->hdisplay, + VC4_HDMI_HORZB_HFP)); + + HDMI_WRITE(VC4_HDMI_VERTA0, verta); + HDMI_WRITE(VC4_HDMI_VERTA1, verta); + + HDMI_WRITE(VC4_HDMI_VERTB0, vertb); + HDMI_WRITE(VC4_HDMI_VERTB1, vertb); + + HD_WRITE(VC4_HD_VID_CTL, + (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | + (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); + + /* The RGB order applies even when CSC is disabled. */ + HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, + VC4_HD_CSC_CTL_ORDER)); + + HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); + + if (debug_dump_regs) { + DRM_INFO("HDMI regs after:\n"); + vc4_hdmi_dump_regs(dev); + } +} + +static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) +{ + struct drm_device *dev = encoder->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + + HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); + HD_WRITE(VC4_HD_VID_CTL, + HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); +} + +static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) +{ + struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); + struct drm_device *dev = encoder->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + int ret; + + HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); + + HD_WRITE(VC4_HD_VID_CTL, + HD_READ(VC4_HD_VID_CTL) | + VC4_HD_VID_CTL_ENABLE | + VC4_HD_VID_CTL_UNDERFLOW_ENABLE | + VC4_HD_VID_CTL_FRAME_COUNTER_RESET); + + if (vc4_encoder->hdmi_monitor) { + HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, + HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | + VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); + + ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1); + WARN_ONCE(ret, "Timeout waiting for " + "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); + } else { + HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, + HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & + ~(VC4_HDMI_RAM_PACKET_ENABLE)); + HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, + HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); + + ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1); + WARN_ONCE(ret, "Timeout waiting for " + "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); + } + + if (vc4_encoder->hdmi_monitor) { + u32 drift; + + WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & + VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); + HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, + HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | + VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); + + /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set + * up the infoframe. + */ + + drift = HDMI_READ(VC4_HDMI_FIFO_CTL); + drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; + + HDMI_WRITE(VC4_HDMI_FIFO_CTL, + drift & ~VC4_HDMI_FIFO_CTL_RECENTER); + HDMI_WRITE(VC4_HDMI_FIFO_CTL, + drift | VC4_HDMI_FIFO_CTL_RECENTER); + udelay(1000); + HDMI_WRITE(VC4_HDMI_FIFO_CTL, + drift & ~VC4_HDMI_FIFO_CTL_RECENTER); + HDMI_WRITE(VC4_HDMI_FIFO_CTL, + drift | VC4_HDMI_FIFO_CTL_RECENTER); + + ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & + VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); + WARN_ONCE(ret, "Timeout waiting for " + "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); + } +} + +static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { + .mode_set = vc4_hdmi_encoder_mode_set, + .disable = vc4_hdmi_encoder_disable, + .enable = vc4_hdmi_encoder_enable, +}; + +static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = drm->dev_private; + struct vc4_hdmi *hdmi; + struct vc4_hdmi_encoder *vc4_hdmi_encoder; + struct device_node *ddc_node; + u32 value; + int ret; + + hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); + if (!hdmi) + return -ENOMEM; + + vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), + GFP_KERNEL); + if (!vc4_hdmi_encoder) + return -ENOMEM; + vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; + hdmi->encoder = &vc4_hdmi_encoder->base.base; + + hdmi->pdev = pdev; + hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); + if (IS_ERR(hdmi->hdmicore_regs)) + return PTR_ERR(hdmi->hdmicore_regs); + + hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); + if (IS_ERR(hdmi->hd_regs)) + return PTR_ERR(hdmi->hd_regs); + + ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); + if (!ddc_node) { + DRM_ERROR("Failed to find ddc node in device tree\n"); + return -ENODEV; + } + + hdmi->pixel_clock = devm_clk_get(dev, "pixel"); + if (IS_ERR(hdmi->pixel_clock)) { + DRM_ERROR("Failed to get pixel clock\n"); + return PTR_ERR(hdmi->pixel_clock); + } + hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); + if (IS_ERR(hdmi->hsm_clock)) { + DRM_ERROR("Failed to get HDMI state machine clock\n"); + return PTR_ERR(hdmi->hsm_clock); + } + + hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); + if (!hdmi->ddc) { + DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); + return -EPROBE_DEFER; + } + + /* Enable the clocks at startup. We can't quite recover from + * turning off the pixel clock during disable/enables yet, so + * it's always running. + */ + ret = clk_prepare_enable(hdmi->pixel_clock); + if (ret) { + DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); + goto err_put_i2c; + } + + ret = clk_prepare_enable(hdmi->hsm_clock); + if (ret) { + DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", + ret); + goto err_unprepare_pix; + } + + /* Only use the GPIO HPD pin if present in the DT, otherwise + * we'll use the HDMI core's register. + */ + if (of_find_property(dev->of_node, "hpd-gpios", &value)) { + hdmi->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0); + if (hdmi->hpd_gpio < 0) { + ret = hdmi->hpd_gpio; + goto err_unprepare_hsm; + } + } + + vc4->hdmi = hdmi; + + /* HDMI core must be enabled. */ + WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0); + + drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, + DRM_MODE_ENCODER_TMDS); + drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); + + hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); + if (IS_ERR(hdmi->connector)) { + ret = PTR_ERR(hdmi->connector); + goto err_destroy_encoder; + } + + return 0; + +err_destroy_encoder: + vc4_hdmi_encoder_destroy(hdmi->encoder); +err_unprepare_hsm: + clk_disable_unprepare(hdmi->hsm_clock); +err_unprepare_pix: + clk_disable_unprepare(hdmi->pixel_clock); +err_put_i2c: + put_device(&vc4->hdmi->ddc->dev); + + return ret; +} + +static void vc4_hdmi_unbind(struct device *dev, struct device *master, + void *data) +{ + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = drm->dev_private; + struct vc4_hdmi *hdmi = vc4->hdmi; + + vc4_hdmi_connector_destroy(hdmi->connector); + vc4_hdmi_encoder_destroy(hdmi->encoder); + + clk_disable_unprepare(hdmi->pixel_clock); + clk_disable_unprepare(hdmi->hsm_clock); + put_device(&hdmi->ddc->dev); + + vc4->hdmi = NULL; +} + +static const struct component_ops vc4_hdmi_ops = { + .bind = vc4_hdmi_bind, + .unbind = vc4_hdmi_unbind, +}; + +static int vc4_hdmi_dev_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &vc4_hdmi_ops); +} + +static int vc4_hdmi_dev_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &vc4_hdmi_ops); + return 0; +} + +static const struct of_device_id vc4_hdmi_dt_match[] = { + { .compatible = "brcm,bcm2835-hdmi" }, + {} +}; + +struct platform_driver vc4_hdmi_driver = { + .probe = vc4_hdmi_dev_probe, + .remove = vc4_hdmi_dev_remove, + .driver = { + .name = "vc4_hdmi", + .of_match_table = vc4_hdmi_dt_match, + }, +}; diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c new file mode 100644 index 000000000000..ab1673f672a4 --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/** + * DOC: VC4 HVS module. + * + * The HVS is the piece of hardware that does translation, scaling, + * colorspace conversion, and compositing of pixels stored in + * framebuffers into a FIFO of pixels going out to the Pixel Valve + * (CRTC). It operates at the system clock rate (the system audio + * clock gate, specifically), which is much higher than the pixel + * clock rate. + * + * There is a single global HVS, with multiple output FIFOs that can + * be consumed by the PVs. This file just manages the resources for + * the HVS, while the vc4_crtc.c code actually drives HVS setup for + * each CRTC. + */ + +#include "linux/component.h" +#include "vc4_drv.h" +#include "vc4_regs.h" + +#define HVS_REG(reg) { reg, #reg } +static const struct { + u32 reg; + const char *name; +} hvs_regs[] = { + HVS_REG(SCALER_DISPCTRL), + HVS_REG(SCALER_DISPSTAT), + HVS_REG(SCALER_DISPID), + HVS_REG(SCALER_DISPECTRL), + HVS_REG(SCALER_DISPPROF), + HVS_REG(SCALER_DISPDITHER), + HVS_REG(SCALER_DISPEOLN), + HVS_REG(SCALER_DISPLIST0), + HVS_REG(SCALER_DISPLIST1), + HVS_REG(SCALER_DISPLIST2), + HVS_REG(SCALER_DISPLSTAT), + HVS_REG(SCALER_DISPLACT0), + HVS_REG(SCALER_DISPLACT1), + HVS_REG(SCALER_DISPLACT2), + HVS_REG(SCALER_DISPCTRL0), + HVS_REG(SCALER_DISPBKGND0), + HVS_REG(SCALER_DISPSTAT0), + HVS_REG(SCALER_DISPBASE0), + HVS_REG(SCALER_DISPCTRL1), + HVS_REG(SCALER_DISPBKGND1), + HVS_REG(SCALER_DISPSTAT1), + HVS_REG(SCALER_DISPBASE1), + HVS_REG(SCALER_DISPCTRL2), + HVS_REG(SCALER_DISPBKGND2), + HVS_REG(SCALER_DISPSTAT2), + HVS_REG(SCALER_DISPBASE2), + HVS_REG(SCALER_DISPALPHA2), +}; + +void vc4_hvs_dump_state(struct drm_device *dev) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(hvs_regs); i++) { + DRM_INFO("0x%04x (%s): 0x%08x\n", + hvs_regs[i].reg, hvs_regs[i].name, + HVS_READ(hvs_regs[i].reg)); + } + + DRM_INFO("HVS ctx:\n"); + for (i = 0; i < 64; i += 4) { + DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", + i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", + ((uint32_t *)vc4->hvs->dlist)[i + 0], + ((uint32_t *)vc4->hvs->dlist)[i + 1], + ((uint32_t *)vc4->hvs->dlist)[i + 2], + ((uint32_t *)vc4->hvs->dlist)[i + 3]); + } +} + +#ifdef CONFIG_DEBUG_FS +int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused) +{ + struct drm_info_node *node = (struct drm_info_node *)m->private; + struct drm_device *dev = node->minor->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(hvs_regs); i++) { + seq_printf(m, "%s (0x%04x): 0x%08x\n", + hvs_regs[i].name, hvs_regs[i].reg, + HVS_READ(hvs_regs[i].reg)); + } + + return 0; +} +#endif + +static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) +{ + struct platform_device *pdev = to_platform_device(dev); + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = drm->dev_private; + struct vc4_hvs *hvs = NULL; + + hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL); + if (!hvs) + return -ENOMEM; + + hvs->pdev = pdev; + + hvs->regs = vc4_ioremap_regs(pdev, 0); + if (IS_ERR(hvs->regs)) + return PTR_ERR(hvs->regs); + + hvs->dlist = hvs->regs + SCALER_DLIST_START; + + vc4->hvs = hvs; + return 0; +} + +static void vc4_hvs_unbind(struct device *dev, struct device *master, + void *data) +{ + struct drm_device *drm = dev_get_drvdata(master); + struct vc4_dev *vc4 = drm->dev_private; + + vc4->hvs = NULL; +} + +static const struct component_ops vc4_hvs_ops = { + .bind = vc4_hvs_bind, + .unbind = vc4_hvs_unbind, +}; + +static int vc4_hvs_dev_probe(struct platform_device *pdev) +{ + return component_add(&pdev->dev, &vc4_hvs_ops); +} + +static int vc4_hvs_dev_remove(struct platform_device *pdev) +{ + component_del(&pdev->dev, &vc4_hvs_ops); + return 0; +} + +static const struct of_device_id vc4_hvs_dt_match[] = { + { .compatible = "brcm,bcm2835-hvs" }, + {} +}; + +struct platform_driver vc4_hvs_driver = { + .probe = vc4_hvs_dev_probe, + .remove = vc4_hvs_dev_remove, + .driver = { + .name = "vc4_hvs", + .of_match_table = vc4_hvs_dt_match, + }, +}; diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c new file mode 100644 index 000000000000..2e5597d10cc6 --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/** + * DOC: VC4 KMS + * + * This is the general code for implementing KMS mode setting that + * doesn't clearly associate with any of the other objects (plane, + * crtc, HDMI encoder). + */ + +#include "drm_crtc.h" +#include "drm_atomic_helper.h" +#include "drm_crtc_helper.h" +#include "drm_plane_helper.h" +#include "drm_fb_cma_helper.h" +#include "vc4_drv.h" + +static void vc4_output_poll_changed(struct drm_device *dev) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + + if (vc4->fbdev) + drm_fbdev_cma_hotplug_event(vc4->fbdev); +} + +static const struct drm_mode_config_funcs vc4_mode_funcs = { + .output_poll_changed = vc4_output_poll_changed, + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, + .fb_create = drm_fb_cma_create, +}; + +int vc4_kms_load(struct drm_device *dev) +{ + struct vc4_dev *vc4 = to_vc4_dev(dev); + int ret; + + ret = drm_vblank_init(dev, dev->mode_config.num_crtc); + if (ret < 0) { + dev_err(dev->dev, "failed to initialize vblank\n"); + return ret; + } + + dev->mode_config.max_width = 2048; + dev->mode_config.max_height = 2048; + dev->mode_config.funcs = &vc4_mode_funcs; + dev->mode_config.preferred_depth = 24; + dev->vblank_disable_allowed = true; + + drm_mode_config_reset(dev); + + vc4->fbdev = drm_fbdev_cma_init(dev, 32, + dev->mode_config.num_crtc, + dev->mode_config.num_connector); + if (IS_ERR(vc4->fbdev)) + vc4->fbdev = NULL; + + drm_kms_helper_poll_init(dev); + + return 0; +} diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c new file mode 100644 index 000000000000..cdd8b10c0147 --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -0,0 +1,320 @@ +/* + * Copyright (C) 2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/** + * DOC: VC4 plane module + * + * Each DRM plane is a layer of pixels being scanned out by the HVS. + * + * At atomic modeset check time, we compute the HVS display element + * state that would be necessary for displaying the plane (giving us a + * chance to figure out if a plane configuration is invalid), then at + * atomic flush time the CRTC will ask us to write our element state + * into the region of the HVS that it has allocated for us. + */ + +#include "vc4_drv.h" +#include "vc4_regs.h" +#include "drm_atomic_helper.h" +#include "drm_fb_cma_helper.h" +#include "drm_plane_helper.h" + +struct vc4_plane_state { + struct drm_plane_state base; + u32 *dlist; + u32 dlist_size; /* Number of dwords in allocated for the display list */ + u32 dlist_count; /* Number of used dwords in the display list. */ +}; + +static inline struct vc4_plane_state * +to_vc4_plane_state(struct drm_plane_state *state) +{ + return (struct vc4_plane_state *)state; +} + +static const struct hvs_format { + u32 drm; /* DRM_FORMAT_* */ + u32 hvs; /* HVS_FORMAT_* */ + u32 pixel_order; + bool has_alpha; +} hvs_formats[] = { + { + .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, + .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = false, + }, + { + .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, + .pixel_order = HVS_PIXEL_ORDER_ABGR, .has_alpha = true, + }, +}; + +static const struct hvs_format *vc4_get_hvs_format(u32 drm_format) +{ + unsigned i; + + for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { + if (hvs_formats[i].drm == drm_format) + return &hvs_formats[i]; + } + + return NULL; +} + +static bool plane_enabled(struct drm_plane_state *state) +{ + return state->fb && state->crtc; +} + +struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) +{ + struct vc4_plane_state *vc4_state; + + if (WARN_ON(!plane->state)) + return NULL; + + vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL); + if (!vc4_state) + return NULL; + + __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base); + + if (vc4_state->dlist) { + vc4_state->dlist = kmemdup(vc4_state->dlist, + vc4_state->dlist_count * 4, + GFP_KERNEL); + if (!vc4_state->dlist) { + kfree(vc4_state); + return NULL; + } + vc4_state->dlist_size = vc4_state->dlist_count; + } + + return &vc4_state->base; +} + +void vc4_plane_destroy_state(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); + + kfree(vc4_state->dlist); + __drm_atomic_helper_plane_destroy_state(plane, &vc4_state->base); + kfree(state); +} + +/* Called during init to allocate the plane's atomic state. */ +void vc4_plane_reset(struct drm_plane *plane) +{ + struct vc4_plane_state *vc4_state; + + WARN_ON(plane->state); + + vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); + if (!vc4_state) + return; + + plane->state = &vc4_state->base; + vc4_state->base.plane = plane; +} + +static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val) +{ + if (vc4_state->dlist_count == vc4_state->dlist_size) { + u32 new_size = max(4u, vc4_state->dlist_count * 2); + u32 *new_dlist = kmalloc(new_size * 4, GFP_KERNEL); + + if (!new_dlist) + return; + memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4); + + kfree(vc4_state->dlist); + vc4_state->dlist = new_dlist; + vc4_state->dlist_size = new_size; + } + + vc4_state->dlist[vc4_state->dlist_count++] = val; +} + +/* Writes out a full display list for an active plane to the plane's + * private dlist state. + */ +static int vc4_plane_mode_set(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); + struct drm_framebuffer *fb = state->fb; + struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); + u32 ctl0_offset = vc4_state->dlist_count; + const struct hvs_format *format = vc4_get_hvs_format(fb->pixel_format); + uint32_t offset = fb->offsets[0]; + int crtc_x = state->crtc_x; + int crtc_y = state->crtc_y; + int crtc_w = state->crtc_w; + int crtc_h = state->crtc_h; + + if (crtc_x < 0) { + offset += drm_format_plane_cpp(fb->pixel_format, 0) * -crtc_x; + crtc_w += crtc_x; + crtc_x = 0; + } + + if (crtc_y < 0) { + offset += fb->pitches[0] * -crtc_y; + crtc_h += crtc_y; + crtc_y = 0; + } + + vc4_dlist_write(vc4_state, + SCALER_CTL0_VALID | + (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | + (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | + SCALER_CTL0_UNITY); + + /* Position Word 0: Image Positions and Alpha Value */ + vc4_dlist_write(vc4_state, + VC4_SET_FIELD(0xff, SCALER_POS0_FIXED_ALPHA) | + VC4_SET_FIELD(crtc_x, SCALER_POS0_START_X) | + VC4_SET_FIELD(crtc_y, SCALER_POS0_START_Y)); + + /* Position Word 1: Scaled Image Dimensions. + * Skipped due to SCALER_CTL0_UNITY scaling. + */ + + /* Position Word 2: Source Image Size, Alpha Mode */ + vc4_dlist_write(vc4_state, + VC4_SET_FIELD(format->has_alpha ? + SCALER_POS2_ALPHA_MODE_PIPELINE : + SCALER_POS2_ALPHA_MODE_FIXED, + SCALER_POS2_ALPHA_MODE) | + VC4_SET_FIELD(crtc_w, SCALER_POS2_WIDTH) | + VC4_SET_FIELD(crtc_h, SCALER_POS2_HEIGHT)); + + /* Position Word 3: Context. Written by the HVS. */ + vc4_dlist_write(vc4_state, 0xc0c0c0c0); + + /* Pointer Word 0: RGB / Y Pointer */ + vc4_dlist_write(vc4_state, bo->paddr + offset); + + /* Pointer Context Word 0: Written by the HVS */ + vc4_dlist_write(vc4_state, 0xc0c0c0c0); + + /* Pitch word 0: Pointer 0 Pitch */ + vc4_dlist_write(vc4_state, + VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH)); + + vc4_state->dlist[ctl0_offset] |= + VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE); + + return 0; +} + +/* If a modeset involves changing the setup of a plane, the atomic + * infrastructure will call this to validate a proposed plane setup. + * However, if a plane isn't getting updated, this (and the + * corresponding vc4_plane_atomic_update) won't get called. Thus, we + * compute the dlist here and have all active plane dlists get updated + * in the CRTC's flush. + */ +static int vc4_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); + + vc4_state->dlist_count = 0; + + if (plane_enabled(state)) + return vc4_plane_mode_set(plane, state); + else + return 0; +} + +static void vc4_plane_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + /* No contents here. Since we don't know where in the CRTC's + * dlist we should be stored, our dlist is uploaded to the + * hardware with vc4_plane_write_dlist() at CRTC atomic_flush + * time. + */ +} + +u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist) +{ + struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); + int i; + + /* Can't memcpy_toio() because it needs to be 32-bit writes. */ + for (i = 0; i < vc4_state->dlist_count; i++) + writel(vc4_state->dlist[i], &dlist[i]); + + return vc4_state->dlist_count; +} + +u32 vc4_plane_dlist_size(struct drm_plane_state *state) +{ + struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); + + return vc4_state->dlist_count; +} + +static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = { + .prepare_fb = NULL, + .cleanup_fb = NULL, + .atomic_check = vc4_plane_atomic_check, + .atomic_update = vc4_plane_atomic_update, +}; + +static void vc4_plane_destroy(struct drm_plane *plane) +{ + drm_plane_helper_disable(plane); + drm_plane_cleanup(plane); +} + +static const struct drm_plane_funcs vc4_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = vc4_plane_destroy, + .set_property = NULL, + .reset = vc4_plane_reset, + .atomic_duplicate_state = vc4_plane_duplicate_state, + .atomic_destroy_state = vc4_plane_destroy_state, +}; + +struct drm_plane *vc4_plane_init(struct drm_device *dev, + enum drm_plane_type type) +{ + struct drm_plane *plane = NULL; + struct vc4_plane *vc4_plane; + u32 formats[ARRAY_SIZE(hvs_formats)]; + int ret = 0; + unsigned i; + + vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane), + GFP_KERNEL); + if (!vc4_plane) { + ret = -ENOMEM; + goto fail; + } + + for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) + formats[i] = hvs_formats[i].drm; + plane = &vc4_plane->base; + ret = drm_universal_plane_init(dev, plane, 0xff, + &vc4_plane_funcs, + formats, ARRAY_SIZE(formats), + type); + + drm_plane_helper_add(plane, &vc4_plane_helper_funcs); + + return plane; +fail: + if (plane) + vc4_plane_destroy(plane); + + return ERR_PTR(ret); +} diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h new file mode 100644 index 000000000000..9e4e904c668e --- /dev/null +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -0,0 +1,570 @@ +/* + * Copyright © 2014-2015 Broadcom + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef VC4_REGS_H +#define VC4_REGS_H + +#include <linux/bitops.h> + +#define VC4_MASK(high, low) ((u32)GENMASK(high, low)) +/* Using the GNU statement expression extension */ +#define VC4_SET_FIELD(value, field) \ + ({ \ + uint32_t fieldval = (value) << field##_SHIFT; \ + WARN_ON((fieldval & ~field##_MASK) != 0); \ + fieldval & field##_MASK; \ + }) + +#define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \ + field##_SHIFT) + +#define V3D_IDENT0 0x00000 +# define V3D_EXPECTED_IDENT0 \ + ((2 << 24) | \ + ('V' << 0) | \ + ('3' << 8) | \ + ('D' << 16)) + +#define V3D_IDENT1 0x00004 +/* Multiples of 1kb */ +# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) +# define V3D_IDENT1_VPM_SIZE_SHIFT 28 +# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) +# define V3D_IDENT1_NSEM_SHIFT 16 +# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) +# define V3D_IDENT1_TUPS_SHIFT 12 +# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) +# define V3D_IDENT1_QUPS_SHIFT 8 +# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) +# define V3D_IDENT1_NSLC_SHIFT 4 +# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) +# define V3D_IDENT1_REV_SHIFT 0 + +#define V3D_IDENT2 0x00008 +#define V3D_SCRATCH 0x00010 +#define V3D_L2CACTL 0x00020 +# define V3D_L2CACTL_L2CCLR BIT(2) +# define V3D_L2CACTL_L2CDIS BIT(1) +# define V3D_L2CACTL_L2CENA BIT(0) + +#define V3D_SLCACTL 0x00024 +# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) +# define V3D_SLCACTL_T1CC_SHIFT 24 +# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) +# define V3D_SLCACTL_T0CC_SHIFT 16 +# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) +# define V3D_SLCACTL_UCC_SHIFT 8 +# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) +# define V3D_SLCACTL_ICC_SHIFT 0 + +#define V3D_INTCTL 0x00030 +#define V3D_INTENA 0x00034 +#define V3D_INTDIS 0x00038 +# define V3D_INT_SPILLUSE BIT(3) +# define V3D_INT_OUTOMEM BIT(2) +# define V3D_INT_FLDONE BIT(1) +# define V3D_INT_FRDONE BIT(0) + +#define V3D_CT0CS 0x00100 +#define V3D_CT1CS 0x00104 +#define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) +# define V3D_CTRSTA BIT(15) +# define V3D_CTSEMA BIT(12) +# define V3D_CTRTSD BIT(8) +# define V3D_CTRUN BIT(5) +# define V3D_CTSUBS BIT(4) +# define V3D_CTERR BIT(3) +# define V3D_CTMODE BIT(0) + +#define V3D_CT0EA 0x00108 +#define V3D_CT1EA 0x0010c +#define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) +#define V3D_CT0CA 0x00110 +#define V3D_CT1CA 0x00114 +#define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) +#define V3D_CT00RA0 0x00118 +#define V3D_CT01RA0 0x0011c +#define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) +#define V3D_CT0LC 0x00120 +#define V3D_CT1LC 0x00124 +#define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) +#define V3D_CT0PC 0x00128 +#define V3D_CT1PC 0x0012c +#define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) + +#define V3D_PCS 0x00130 +# define V3D_BMOOM BIT(8) +# define V3D_RMBUSY BIT(3) +# define V3D_RMACTIVE BIT(2) +# define V3D_BMBUSY BIT(1) +# define V3D_BMACTIVE BIT(0) + +#define V3D_BFC 0x00134 +#define V3D_RFC 0x00138 +#define V3D_BPCA 0x00300 +#define V3D_BPCS 0x00304 +#define V3D_BPOA 0x00308 +#define V3D_BPOS 0x0030c +#define V3D_BXCF 0x00310 +#define V3D_SQRSV0 0x00410 +#define V3D_SQRSV1 0x00414 +#define V3D_SQCNTL 0x00418 +#define V3D_SRQPC 0x00430 +#define V3D_SRQUA 0x00434 +#define V3D_SRQUL 0x00438 +#define V3D_SRQCS 0x0043c +#define V3D_VPACNTL 0x00500 +#define V3D_VPMBASE 0x00504 +#define V3D_PCTRC 0x00670 +#define V3D_PCTRE 0x00674 +#define V3D_PCTR0 0x00680 +#define V3D_PCTRS0 0x00684 +#define V3D_PCTR1 0x00688 +#define V3D_PCTRS1 0x0068c +#define V3D_PCTR2 0x00690 +#define V3D_PCTRS2 0x00694 +#define V3D_PCTR3 0x00698 +#define V3D_PCTRS3 0x0069c +#define V3D_PCTR4 0x006a0 +#define V3D_PCTRS4 0x006a4 +#define V3D_PCTR5 0x006a8 +#define V3D_PCTRS5 0x006ac +#define V3D_PCTR6 0x006b0 +#define V3D_PCTRS6 0x006b4 +#define V3D_PCTR7 0x006b8 +#define V3D_PCTRS7 0x006bc +#define V3D_PCTR8 0x006c0 +#define V3D_PCTRS8 0x006c4 +#define V3D_PCTR9 0x006c8 +#define V3D_PCTRS9 0x006cc +#define V3D_PCTR10 0x006d0 +#define V3D_PCTRS10 0x006d4 +#define V3D_PCTR11 0x006d8 +#define V3D_PCTRS11 0x006dc +#define V3D_PCTR12 0x006e0 +#define V3D_PCTRS12 0x006e4 +#define V3D_PCTR13 0x006e8 +#define V3D_PCTRS13 0x006ec +#define V3D_PCTR14 0x006f0 +#define V3D_PCTRS14 0x006f4 +#define V3D_PCTR15 0x006f8 +#define V3D_PCTRS15 0x006fc +#define V3D_BGE 0x00f00 +#define V3D_FDBGO 0x00f04 +#define V3D_FDBGB 0x00f08 +#define V3D_FDBGR 0x00f0c +#define V3D_FDBGS 0x00f10 +#define V3D_ERRSTAT 0x00f20 + +#define PV_CONTROL 0x00 +# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) +# define PV_CONTROL_FORMAT_SHIFT 21 +# define PV_CONTROL_FORMAT_24 0 +# define PV_CONTROL_FORMAT_DSIV_16 1 +# define PV_CONTROL_FORMAT_DSIC_16 2 +# define PV_CONTROL_FORMAT_DSIV_18 3 +# define PV_CONTROL_FORMAT_DSIV_24 4 + +# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) +# define PV_CONTROL_FIFO_LEVEL_SHIFT 15 +# define PV_CONTROL_CLR_AT_START BIT(14) +# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) +# define PV_CONTROL_WAIT_HSTART BIT(12) +# define PV_CONTROL_CLK_SELECT_DSI_VEC 0 +# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 +# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) +# define PV_CONTROL_CLK_SELECT_SHIFT 2 +# define PV_CONTROL_FIFO_CLR BIT(1) +# define PV_CONTROL_EN BIT(0) + +#define PV_V_CONTROL 0x04 +# define PV_VCONTROL_INTERLACE BIT(4) +# define PV_VCONTROL_CONTINUOUS BIT(1) +# define PV_VCONTROL_VIDEN BIT(0) + +#define PV_VSYNCD 0x08 + +#define PV_HORZA 0x0c +# define PV_HORZA_HBP_MASK VC4_MASK(31, 16) +# define PV_HORZA_HBP_SHIFT 16 +# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) +# define PV_HORZA_HSYNC_SHIFT 0 + +#define PV_HORZB 0x10 +# define PV_HORZB_HFP_MASK VC4_MASK(31, 16) +# define PV_HORZB_HFP_SHIFT 16 +# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) +# define PV_HORZB_HACTIVE_SHIFT 0 + +#define PV_VERTA 0x14 +# define PV_VERTA_VBP_MASK VC4_MASK(31, 16) +# define PV_VERTA_VBP_SHIFT 16 +# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) +# define PV_VERTA_VSYNC_SHIFT 0 + +#define PV_VERTB 0x18 +# define PV_VERTB_VFP_MASK VC4_MASK(31, 16) +# define PV_VERTB_VFP_SHIFT 16 +# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) +# define PV_VERTB_VACTIVE_SHIFT 0 + +#define PV_VERTA_EVEN 0x1c +#define PV_VERTB_EVEN 0x20 + +#define PV_INTEN 0x24 +#define PV_INTSTAT 0x28 +# define PV_INT_VID_IDLE BIT(9) +# define PV_INT_VFP_END BIT(8) +# define PV_INT_VFP_START BIT(7) +# define PV_INT_VACT_START BIT(6) +# define PV_INT_VBP_START BIT(5) +# define PV_INT_VSYNC_START BIT(4) +# define PV_INT_HFP_START BIT(3) +# define PV_INT_HACT_START BIT(2) +# define PV_INT_HBP_START BIT(1) +# define PV_INT_HSYNC_START BIT(0) + +#define PV_STAT 0x2c + +#define PV_HACT_ACT 0x30 + +#define SCALER_DISPCTRL 0x00000000 +/* Global register for clock gating the HVS */ +# define SCALER_DISPCTRL_ENABLE BIT(31) +# define SCALER_DISPCTRL_DSP2EISLUR BIT(15) +# define SCALER_DISPCTRL_DSP1EISLUR BIT(14) +/* Enables Display 0 short line and underrun contribution to + * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are + * always enabled. + */ +# define SCALER_DISPCTRL_DSP0EISLUR BIT(13) +# define SCALER_DISPCTRL_DSP2EIEOLN BIT(12) +# define SCALER_DISPCTRL_DSP2EIEOF BIT(11) +# define SCALER_DISPCTRL_DSP1EIEOLN BIT(10) +# define SCALER_DISPCTRL_DSP1EIEOF BIT(9) +/* Enables Display 0 end-of-line-N contribution to + * SCALER_DISPSTAT_IRQDISP0 + */ +# define SCALER_DISPCTRL_DSP0EIEOLN BIT(8) +/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ +# define SCALER_DISPCTRL_DSP0EIEOF BIT(7) + +# define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) +# define SCALER_DISPCTRL_SLVWREIRQ BIT(5) +# define SCALER_DISPCTRL_DMAEIRQ BIT(4) +# define SCALER_DISPCTRL_DISP2EIRQ BIT(3) +# define SCALER_DISPCTRL_DISP1EIRQ BIT(2) +/* Enables interrupt generation on the enabled EOF/EOLN/EISLUR + * bits and short frames.. + */ +# define SCALER_DISPCTRL_DISP0EIRQ BIT(1) +/* Enables interrupt generation on scaler profiler interrupt. */ +# define SCALER_DISPCTRL_SCLEIRQ BIT(0) + +#define SCALER_DISPSTAT 0x00000004 +# define SCALER_DISPSTAT_COBLOW2 BIT(29) +# define SCALER_DISPSTAT_EOLN2 BIT(28) +# define SCALER_DISPSTAT_ESFRAME2 BIT(27) +# define SCALER_DISPSTAT_ESLINE2 BIT(26) +# define SCALER_DISPSTAT_EUFLOW2 BIT(25) +# define SCALER_DISPSTAT_EOF2 BIT(24) + +# define SCALER_DISPSTAT_COBLOW1 BIT(21) +# define SCALER_DISPSTAT_EOLN1 BIT(20) +# define SCALER_DISPSTAT_ESFRAME1 BIT(19) +# define SCALER_DISPSTAT_ESLINE1 BIT(18) +# define SCALER_DISPSTAT_EUFLOW1 BIT(17) +# define SCALER_DISPSTAT_EOF1 BIT(16) + +# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) +# define SCALER_DISPSTAT_RESP_SHIFT 14 +# define SCALER_DISPSTAT_RESP_OKAY 0 +# define SCALER_DISPSTAT_RESP_EXOKAY 1 +# define SCALER_DISPSTAT_RESP_SLVERR 2 +# define SCALER_DISPSTAT_RESP_DECERR 3 + +# define SCALER_DISPSTAT_COBLOW0 BIT(13) +/* Set when the DISPEOLN line is done compositing. */ +# define SCALER_DISPSTAT_EOLN0 BIT(12) +/* Set when VSTART is seen but there are still pixels in the current + * output line. + */ +# define SCALER_DISPSTAT_ESFRAME0 BIT(11) +/* Set when HSTART is seen but there are still pixels in the current + * output line. + */ +# define SCALER_DISPSTAT_ESLINE0 BIT(10) +/* Set when the the downstream tries to read from the display FIFO + * while it's empty. + */ +# define SCALER_DISPSTAT_EUFLOW0 BIT(9) +/* Set when the display mode changes from RUN to EOF */ +# define SCALER_DISPSTAT_EOF0 BIT(8) + +/* Set on AXI invalid DMA ID error. */ +# define SCALER_DISPSTAT_DMA_ERROR BIT(7) +/* Set on AXI slave read decode error */ +# define SCALER_DISPSTAT_IRQSLVRD BIT(6) +/* Set on AXI slave write decode error */ +# define SCALER_DISPSTAT_IRQSLVWR BIT(5) +/* Set when SCALER_DISPSTAT_DMA_ERROR is set, or + * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. + */ +# define SCALER_DISPSTAT_IRQDMA BIT(4) +# define SCALER_DISPSTAT_IRQDISP2 BIT(3) +# define SCALER_DISPSTAT_IRQDISP1 BIT(2) +/* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their + * corresponding interrupt bit is enabled in DISPCTRL. + */ +# define SCALER_DISPSTAT_IRQDISP0 BIT(1) +/* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ +# define SCALER_DISPSTAT_IRQSCL BIT(0) + +#define SCALER_DISPID 0x00000008 +#define SCALER_DISPECTRL 0x0000000c +#define SCALER_DISPPROF 0x00000010 +#define SCALER_DISPDITHER 0x00000014 +#define SCALER_DISPEOLN 0x00000018 +#define SCALER_DISPLIST0 0x00000020 +#define SCALER_DISPLIST1 0x00000024 +#define SCALER_DISPLIST2 0x00000028 +#define SCALER_DISPLSTAT 0x0000002c +#define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ + (x) * (SCALER_DISPLIST1 - \ + SCALER_DISPLIST0)) + +#define SCALER_DISPLACT0 0x00000030 +#define SCALER_DISPLACT1 0x00000034 +#define SCALER_DISPLACT2 0x00000038 +#define SCALER_DISPCTRL0 0x00000040 +# define SCALER_DISPCTRLX_ENABLE BIT(31) +# define SCALER_DISPCTRLX_RESET BIT(30) +# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) +# define SCALER_DISPCTRLX_WIDTH_SHIFT 12 +# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) +# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 + +#define SCALER_DISPBKGND0 0x00000044 +#define SCALER_DISPSTAT0 0x00000048 +#define SCALER_DISPBASE0 0x0000004c +# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) +# define SCALER_DISPSTATX_MODE_SHIFT 30 +# define SCALER_DISPSTATX_MODE_DISABLED 0 +# define SCALER_DISPSTATX_MODE_INIT 1 +# define SCALER_DISPSTATX_MODE_RUN 2 +# define SCALER_DISPSTATX_MODE_EOF 3 +# define SCALER_DISPSTATX_FULL BIT(29) +# define SCALER_DISPSTATX_EMPTY BIT(28) +#define SCALER_DISPCTRL1 0x00000050 +#define SCALER_DISPBKGND1 0x00000054 +#define SCALER_DISPSTAT1 0x00000058 +#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ + (x) * (SCALER_DISPSTAT1 - \ + SCALER_DISPSTAT0)) +#define SCALER_DISPBASE1 0x0000005c +#define SCALER_DISPCTRL2 0x00000060 +#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ + (x) * (SCALER_DISPCTRL1 - \ + SCALER_DISPCTRL0)) +#define SCALER_DISPBKGND2 0x00000064 +#define SCALER_DISPSTAT2 0x00000068 +#define SCALER_DISPBASE2 0x0000006c +#define SCALER_DISPALPHA2 0x00000070 +#define SCALER_GAMADDR 0x00000078 +#define SCALER_GAMDATA 0x000000e0 +#define SCALER_DLIST_START 0x00002000 +#define SCALER_DLIST_SIZE 0x00004000 + +#define VC4_HDMI_CORE_REV 0x000 + +#define VC4_HDMI_SW_RESET_CONTROL 0x004 +# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) +# define VC4_HDMI_SW_RESET_HDMI BIT(0) + +#define VC4_HDMI_HOTPLUG_INT 0x008 + +#define VC4_HDMI_HOTPLUG 0x00c +# define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) + +#define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 +# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) + +#define VC4_HDMI_HORZA 0x0c4 +# define VC4_HDMI_HORZA_VPOS BIT(14) +# define VC4_HDMI_HORZA_HPOS BIT(13) +/* Horizontal active pixels (hdisplay). */ +# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) +# define VC4_HDMI_HORZA_HAP_SHIFT 0 + +#define VC4_HDMI_HORZB 0x0c8 +/* Horizontal pack porch (htotal - hsync_end). */ +# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) +# define VC4_HDMI_HORZB_HBP_SHIFT 20 +/* Horizontal sync pulse (hsync_end - hsync_start). */ +# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) +# define VC4_HDMI_HORZB_HSP_SHIFT 10 +/* Horizontal front porch (hsync_start - hdisplay). */ +# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) +# define VC4_HDMI_HORZB_HFP_SHIFT 0 + +#define VC4_HDMI_FIFO_CTL 0x05c +# define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) +# define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) +# define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) +# define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) +# define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) +# define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) +# define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) +# define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) +# define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) +# define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) +# define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff + +#define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 +# define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) +# define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) +# define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) +# define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) +# define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) + +#define VC4_HDMI_VERTA0 0x0cc +#define VC4_HDMI_VERTA1 0x0d4 +/* Vertical sync pulse (vsync_end - vsync_start). */ +# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) +# define VC4_HDMI_VERTA_VSP_SHIFT 20 +/* Vertical front porch (vsync_start - vdisplay). */ +# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) +# define VC4_HDMI_VERTA_VFP_SHIFT 13 +/* Vertical active lines (vdisplay). */ +# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) +# define VC4_HDMI_VERTA_VAL_SHIFT 0 + +#define VC4_HDMI_VERTB0 0x0d0 +#define VC4_HDMI_VERTB1 0x0d8 +/* Vertical sync pulse offset (for interlaced) */ +# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) +# define VC4_HDMI_VERTB_VSPO_SHIFT 9 +/* Vertical pack porch (vtotal - vsync_end). */ +# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) +# define VC4_HDMI_VERTB_VBP_SHIFT 0 + +#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 + +#define VC4_HD_M_CTL 0x00c +# define VC4_HD_M_SW_RST BIT(2) +# define VC4_HD_M_ENABLE BIT(0) + +#define VC4_HD_MAI_CTL 0x014 + +#define VC4_HD_VID_CTL 0x038 +# define VC4_HD_VID_CTL_ENABLE BIT(31) +# define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) +# define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) +# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) +# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) + +#define VC4_HD_CSC_CTL 0x040 +# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) +# define VC4_HD_CSC_CTL_ORDER_SHIFT 5 +# define VC4_HD_CSC_CTL_ORDER_RGB 0 +# define VC4_HD_CSC_CTL_ORDER_BGR 1 +# define VC4_HD_CSC_CTL_ORDER_BRG 2 +# define VC4_HD_CSC_CTL_ORDER_GRB 3 +# define VC4_HD_CSC_CTL_ORDER_GBR 4 +# define VC4_HD_CSC_CTL_ORDER_RBG 5 +# define VC4_HD_CSC_CTL_PADMSB BIT(4) +# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) +# define VC4_HD_CSC_CTL_MODE_SHIFT 2 +# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 +# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 +# define VC4_HD_CSC_CTL_MODE_CUSTOM 2 +# define VC4_HD_CSC_CTL_RGB2YCC BIT(1) +# define VC4_HD_CSC_CTL_ENABLE BIT(0) + +#define VC4_HD_FRAME_COUNT 0x068 + +/* HVS display list information. */ +#define HVS_BOOTLOADER_DLIST_END 32 + +enum hvs_pixel_format { + /* 8bpp */ + HVS_PIXEL_FORMAT_RGB332 = 0, + /* 16bpp */ + HVS_PIXEL_FORMAT_RGBA4444 = 1, + HVS_PIXEL_FORMAT_RGB555 = 2, + HVS_PIXEL_FORMAT_RGBA5551 = 3, + HVS_PIXEL_FORMAT_RGB565 = 4, + /* 24bpp */ + HVS_PIXEL_FORMAT_RGB888 = 5, + HVS_PIXEL_FORMAT_RGBA6666 = 6, + /* 32bpp */ + HVS_PIXEL_FORMAT_RGBA8888 = 7 +}; + +/* Note: the LSB is the rightmost character shown. Only valid for + * HVS_PIXEL_FORMAT_RGB8888, not RGB888. + */ +#define HVS_PIXEL_ORDER_RGBA 0 +#define HVS_PIXEL_ORDER_BGRA 1 +#define HVS_PIXEL_ORDER_ARGB 2 +#define HVS_PIXEL_ORDER_ABGR 3 + +#define HVS_PIXEL_ORDER_XBRG 0 +#define HVS_PIXEL_ORDER_XRBG 1 +#define HVS_PIXEL_ORDER_XRGB 2 +#define HVS_PIXEL_ORDER_XBGR 3 + +#define HVS_PIXEL_ORDER_XYCBCR 0 +#define HVS_PIXEL_ORDER_XYCRCB 1 +#define HVS_PIXEL_ORDER_YXCBCR 2 +#define HVS_PIXEL_ORDER_YXCRCB 3 + +#define SCALER_CTL0_END BIT(31) +#define SCALER_CTL0_VALID BIT(30) + +#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) +#define SCALER_CTL0_SIZE_SHIFT 24 + +#define SCALER_CTL0_HFLIP BIT(16) +#define SCALER_CTL0_VFLIP BIT(15) + +#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) +#define SCALER_CTL0_ORDER_SHIFT 13 + +/* Set to indicate no scaling. */ +#define SCALER_CTL0_UNITY BIT(4) + +#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) +#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 + +#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) +#define SCALER_POS0_FIXED_ALPHA_SHIFT 24 + +#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) +#define SCALER_POS0_START_Y_SHIFT 12 + +#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) +#define SCALER_POS0_START_X_SHIFT 0 + +#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) +#define SCALER_POS2_ALPHA_MODE_SHIFT 30 +#define SCALER_POS2_ALPHA_MODE_PIPELINE 0 +#define SCALER_POS2_ALPHA_MODE_FIXED 1 +#define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 +#define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 + +#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) +#define SCALER_POS2_HEIGHT_SHIFT 16 + +#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) +#define SCALER_POS2_WIDTH_SHIFT 0 + +#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) +#define SCALER_SRC_PITCH_SHIFT 0 + +#endif /* VC4_REGS_H */ diff --git a/drivers/gpu/drm/vgem/vgem_drv.c b/drivers/gpu/drm/vgem/vgem_drv.c index 860062ef8814..c503a840fd88 100644 --- a/drivers/gpu/drm/vgem/vgem_drv.c +++ b/drivers/gpu/drm/vgem/vgem_drv.c @@ -235,66 +235,13 @@ unlock: return ret; } -int vgem_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) -{ - struct drm_file *priv = filp->private_data; - struct drm_device *dev = priv->minor->dev; - struct drm_vma_offset_node *node; - struct drm_gem_object *obj; - struct drm_vgem_gem_object *vgem_obj; - int ret = 0; - - mutex_lock(&dev->struct_mutex); - - node = drm_vma_offset_exact_lookup(dev->vma_offset_manager, - vma->vm_pgoff, - vma_pages(vma)); - if (!node) { - ret = -EINVAL; - goto out_unlock; - } else if (!drm_vma_node_is_allowed(node, filp)) { - ret = -EACCES; - goto out_unlock; - } - - obj = container_of(node, struct drm_gem_object, vma_node); - - vgem_obj = to_vgem_bo(obj); - - if (obj->dma_buf && vgem_obj->use_dma_buf) { - ret = dma_buf_mmap(obj->dma_buf, vma, 0); - goto out_unlock; - } - - if (!obj->dev->driver->gem_vm_ops) { - ret = -EINVAL; - goto out_unlock; - } - - vma->vm_flags |= VM_IO | VM_MIXEDMAP | VM_DONTEXPAND | VM_DONTDUMP; - vma->vm_ops = obj->dev->driver->gem_vm_ops; - vma->vm_private_data = vgem_obj; - vma->vm_page_prot = - pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); - - mutex_unlock(&dev->struct_mutex); - drm_gem_vm_open(vma); - return ret; - -out_unlock: - mutex_unlock(&dev->struct_mutex); - - return ret; -} - - static struct drm_ioctl_desc vgem_ioctls[] = { }; static const struct file_operations vgem_driver_fops = { .owner = THIS_MODULE, .open = drm_open, - .mmap = vgem_drm_gem_mmap, + .mmap = drm_gem_mmap, .poll = drm_poll, .read = drm_read, .unlocked_ioctl = drm_ioctl, diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h index ef8c500b4a00..286a785fab4f 100644 --- a/drivers/gpu/drm/via/via_drv.h +++ b/drivers/gpu/drm/via/via_drv.h @@ -102,6 +102,10 @@ typedef struct drm_via_private { uint32_t dma_diff; } drm_via_private_t; +struct via_file_private { + struct list_head obj_list; +}; + enum via_family { VIA_OTHER = 0, /* Baseline */ VIA_PRO_GROUP_A, /* Another video engine and DMA commands */ @@ -136,9 +140,9 @@ extern int via_init_context(struct drm_device *dev, int context); extern int via_final_context(struct drm_device *dev, int context); extern int via_do_cleanup_map(struct drm_device *dev); -extern u32 via_get_vblank_counter(struct drm_device *dev, int crtc); -extern int via_enable_vblank(struct drm_device *dev, int crtc); -extern void via_disable_vblank(struct drm_device *dev, int crtc); +extern u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe); +extern int via_enable_vblank(struct drm_device *dev, unsigned int pipe); +extern void via_disable_vblank(struct drm_device *dev, unsigned int pipe); extern irqreturn_t via_driver_irq_handler(int irq, void *arg); extern void via_driver_irq_preinstall(struct drm_device *dev); diff --git a/drivers/gpu/drm/via/via_irq.c b/drivers/gpu/drm/via/via_irq.c index 1319433816d3..ea8172c747a2 100644 --- a/drivers/gpu/drm/via/via_irq.c +++ b/drivers/gpu/drm/via/via_irq.c @@ -95,10 +95,11 @@ static unsigned time_diff(struct timeval *now, struct timeval *then) 1000000 - (then->tv_usec - now->tv_usec); } -u32 via_get_vblank_counter(struct drm_device *dev, int crtc) +u32 via_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { drm_via_private_t *dev_priv = dev->dev_private; - if (crtc != 0) + + if (pipe != 0) return 0; return atomic_read(&dev_priv->vbl_received); @@ -170,13 +171,13 @@ static __inline__ void viadrv_acknowledge_irqs(drm_via_private_t *dev_priv) } } -int via_enable_vblank(struct drm_device *dev, int crtc) +int via_enable_vblank(struct drm_device *dev, unsigned int pipe) { drm_via_private_t *dev_priv = dev->dev_private; u32 status; - if (crtc != 0) { - DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); + if (pipe != 0) { + DRM_ERROR("%s: bad crtc %u\n", __func__, pipe); return -EINVAL; } @@ -189,7 +190,7 @@ int via_enable_vblank(struct drm_device *dev, int crtc) return 0; } -void via_disable_vblank(struct drm_device *dev, int crtc) +void via_disable_vblank(struct drm_device *dev, unsigned int pipe) { drm_via_private_t *dev_priv = dev->dev_private; u32 status; @@ -200,8 +201,8 @@ void via_disable_vblank(struct drm_device *dev, int crtc) VIA_WRITE8(0x83d4, 0x11); VIA_WRITE8(0x83d5, VIA_READ8(0x83d5) & ~0x30); - if (crtc != 0) - DRM_ERROR("%s: bad crtc %d\n", __func__, crtc); + if (pipe != 0) + DRM_ERROR("%s: bad crtc %u\n", __func__, pipe); } static int diff --git a/drivers/gpu/drm/virtio/Makefile b/drivers/gpu/drm/virtio/Makefile index 2ee1602d77d4..3fb8eac1084f 100644 --- a/drivers/gpu/drm/virtio/Makefile +++ b/drivers/gpu/drm/virtio/Makefile @@ -6,6 +6,7 @@ ccflags-y := -Iinclude/drm virtio-gpu-y := virtgpu_drv.o virtgpu_kms.o virtgpu_drm_bus.o virtgpu_gem.o \ virtgpu_fb.o virtgpu_display.o virtgpu_vq.o virtgpu_ttm.o \ - virtgpu_fence.o virtgpu_object.o virtgpu_debugfs.o virtgpu_plane.o + virtgpu_fence.o virtgpu_object.o virtgpu_debugfs.o virtgpu_plane.o \ + virtgpu_ioctl.o virtgpu_prime.o obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio-gpu.o diff --git a/drivers/gpu/drm/virtio/virtgpu_display.c b/drivers/gpu/drm/virtio/virtgpu_display.c index 4e160efc9402..f545913a56c7 100644 --- a/drivers/gpu/drm/virtio/virtgpu_display.c +++ b/drivers/gpu/drm/virtio/virtgpu_display.c @@ -90,6 +90,14 @@ static int virtio_gpu_crtc_cursor_set(struct drm_crtc *crtc, cpu_to_le32(64), cpu_to_le32(64), 0, 0, &fence); + ret = virtio_gpu_object_reserve(qobj, false); + if (!ret) { + reservation_object_add_excl_fence(qobj->tbo.resv, + &fence->f); + fence_put(&fence->f); + virtio_gpu_object_unreserve(qobj); + virtio_gpu_object_wait(qobj, false); + } output->cursor.hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR); output->cursor.resource_id = cpu_to_le32(qobj->hw_res_handle); @@ -117,6 +125,51 @@ static int virtio_gpu_crtc_cursor_move(struct drm_crtc *crtc, return 0; } +static int virtio_gpu_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t flags) +{ + struct virtio_gpu_device *vgdev = crtc->dev->dev_private; + struct virtio_gpu_output *output = + container_of(crtc, struct virtio_gpu_output, crtc); + struct drm_plane *plane = crtc->primary; + struct virtio_gpu_framebuffer *vgfb; + struct virtio_gpu_object *bo; + unsigned long irqflags; + uint32_t handle; + + plane->fb = fb; + vgfb = to_virtio_gpu_framebuffer(plane->fb); + bo = gem_to_virtio_gpu_obj(vgfb->obj); + handle = bo->hw_res_handle; + + DRM_DEBUG("handle 0x%x%s, crtc %dx%d\n", handle, + bo->dumb ? ", dumb" : "", + crtc->mode.hdisplay, crtc->mode.vdisplay); + if (bo->dumb) { + virtio_gpu_cmd_transfer_to_host_2d + (vgdev, handle, 0, + cpu_to_le32(crtc->mode.hdisplay), + cpu_to_le32(crtc->mode.vdisplay), + 0, 0, NULL); + } + virtio_gpu_cmd_set_scanout(vgdev, output->index, handle, + crtc->mode.hdisplay, + crtc->mode.vdisplay, 0, 0); + virtio_gpu_cmd_resource_flush(vgdev, handle, 0, 0, + crtc->mode.hdisplay, + crtc->mode.vdisplay); + + if (event) { + spin_lock_irqsave(&crtc->dev->event_lock, irqflags); + drm_send_vblank_event(crtc->dev, -1, event); + spin_unlock_irqrestore(&crtc->dev->event_lock, irqflags); + } + + return 0; +} + static const struct drm_crtc_funcs virtio_gpu_crtc_funcs = { .cursor_set2 = virtio_gpu_crtc_cursor_set, .cursor_move = virtio_gpu_crtc_cursor_move, @@ -124,9 +177,7 @@ static const struct drm_crtc_funcs virtio_gpu_crtc_funcs = { .set_config = drm_atomic_helper_set_config, .destroy = drm_crtc_cleanup, -#if 0 /* not (yet) working without vblank support according to docs */ - .page_flip = drm_atomic_helper_page_flip, -#endif + .page_flip = virtio_gpu_page_flip, .reset = drm_atomic_helper_crtc_reset, .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.c b/drivers/gpu/drm/virtio/virtgpu_drv.c index 7d9610aaeff9..b40ed6061f05 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.c +++ b/drivers/gpu/drm/virtio/virtgpu_drv.c @@ -73,6 +73,14 @@ static struct virtio_device_id id_table[] = { }; static unsigned int features[] = { +#ifdef __LITTLE_ENDIAN + /* + * Gallium command stream send by virgl is native endian. + * Because of that we only support little endian guests on + * little endian hosts. + */ + VIRTIO_GPU_F_VIRGL, +#endif }; static struct virtio_driver virtio_gpu_driver = { .feature_table = features, @@ -110,10 +118,12 @@ static const struct file_operations virtio_gpu_driver_fops = { static struct drm_driver driver = { - .driver_features = DRIVER_MODESET | DRIVER_GEM, + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | DRIVER_RENDER, .set_busid = drm_virtio_set_busid, .load = virtio_gpu_driver_load, .unload = virtio_gpu_driver_unload, + .open = virtio_gpu_driver_open, + .postclose = virtio_gpu_driver_postclose, .dumb_create = virtio_gpu_mode_dumb_create, .dumb_map_offset = virtio_gpu_mode_dumb_mmap, @@ -123,10 +133,26 @@ static struct drm_driver driver = { .debugfs_init = virtio_gpu_debugfs_init, .debugfs_cleanup = virtio_gpu_debugfs_takedown, #endif + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, + .gem_prime_export = drm_gem_prime_export, + .gem_prime_import = drm_gem_prime_import, + .gem_prime_pin = virtgpu_gem_prime_pin, + .gem_prime_unpin = virtgpu_gem_prime_unpin, + .gem_prime_get_sg_table = virtgpu_gem_prime_get_sg_table, + .gem_prime_import_sg_table = virtgpu_gem_prime_import_sg_table, + .gem_prime_vmap = virtgpu_gem_prime_vmap, + .gem_prime_vunmap = virtgpu_gem_prime_vunmap, + .gem_prime_mmap = virtgpu_gem_prime_mmap, .gem_free_object = virtio_gpu_gem_free_object, + .gem_open_object = virtio_gpu_gem_object_open, + .gem_close_object = virtio_gpu_gem_object_close, .fops = &virtio_gpu_driver_fops, + .ioctls = virtio_gpu_ioctls, + .num_ioctls = DRM_VIRTIO_NUM_IOCTLS, + .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, diff --git a/drivers/gpu/drm/virtio/virtgpu_drv.h b/drivers/gpu/drm/virtio/virtgpu_drv.h index 6d4db2dba90b..79f0abe69b64 100644 --- a/drivers/gpu/drm/virtio/virtgpu_drv.h +++ b/drivers/gpu/drm/virtio/virtgpu_drv.h @@ -146,6 +146,21 @@ struct virtio_gpu_queue { struct work_struct dequeue_work; }; +struct virtio_gpu_drv_capset { + uint32_t id; + uint32_t max_version; + uint32_t max_size; +}; + +struct virtio_gpu_drv_cap_cache { + struct list_head head; + void *caps_cache; + uint32_t id; + uint32_t version; + uint32_t size; + atomic_t is_valid; +}; + struct virtio_gpu_device { struct device *dev; struct drm_device *ddev; @@ -179,7 +194,13 @@ struct virtio_gpu_device { struct idr ctx_id_idr; spinlock_t ctx_id_idr_lock; + bool has_virgl_3d; + struct work_struct config_changed_work; + + struct virtio_gpu_drv_capset *capsets; + uint32_t num_capsets; + struct list_head cap_cache; }; struct virtio_gpu_fpriv { @@ -193,6 +214,8 @@ extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS]; /* virtio_kms.c */ int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags); int virtio_gpu_driver_unload(struct drm_device *dev); +int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file); +void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file); /* virtio_gem.c */ void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj); @@ -203,6 +226,10 @@ int virtio_gpu_gem_create(struct drm_file *file, uint64_t size, struct drm_gem_object **obj_p, uint32_t *handle_p); +int virtio_gpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file); +void virtio_gpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file); struct virtio_gpu_object *virtio_gpu_alloc_object(struct drm_device *dev, size_t size, bool kernel, bool pinned); @@ -260,10 +287,43 @@ void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev, int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev); void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev, uint32_t resource_id); +int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx); +int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev, + int idx, int version, + struct virtio_gpu_drv_cap_cache **cache_p); +void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id, + uint32_t nlen, const char *name); +void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev, + uint32_t id); +void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev, + uint32_t ctx_id, + uint32_t resource_id); +void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev, + uint32_t ctx_id, + uint32_t resource_id); +void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev, + void *data, uint32_t data_size, + uint32_t ctx_id, struct virtio_gpu_fence **fence); +void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev, + uint32_t resource_id, uint32_t ctx_id, + uint64_t offset, uint32_t level, + struct virtio_gpu_box *box, + struct virtio_gpu_fence **fence); +void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev, + uint32_t resource_id, uint32_t ctx_id, + uint64_t offset, uint32_t level, + struct virtio_gpu_box *box, + struct virtio_gpu_fence **fence); +void +virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev, + struct virtio_gpu_resource_create_3d *rc_3d, + struct virtio_gpu_fence **fence); void virtio_gpu_ctrl_ack(struct virtqueue *vq); void virtio_gpu_cursor_ack(struct virtqueue *vq); +void virtio_gpu_fence_ack(struct virtqueue *vq); void virtio_gpu_dequeue_ctrl_func(struct work_struct *work); void virtio_gpu_dequeue_cursor_func(struct work_struct *work); +void virtio_gpu_dequeue_fence_func(struct work_struct *work); /* virtio_gpu_display.c */ int virtio_gpu_framebuffer_init(struct drm_device *dev, @@ -299,6 +359,18 @@ int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev, void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo); int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait); +/* virtgpu_prime.c */ +int virtgpu_gem_prime_pin(struct drm_gem_object *obj); +void virtgpu_gem_prime_unpin(struct drm_gem_object *obj); +struct sg_table *virtgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); +struct drm_gem_object *virtgpu_gem_prime_import_sg_table( + struct drm_device *dev, struct dma_buf_attachment *attach, + struct sg_table *sgt); +void *virtgpu_gem_prime_vmap(struct drm_gem_object *obj); +void virtgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); +int virtgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma); + static inline struct virtio_gpu_object* virtio_gpu_object_ref(struct virtio_gpu_object *bo) { diff --git a/drivers/gpu/drm/virtio/virtgpu_fence.c b/drivers/gpu/drm/virtio/virtgpu_fence.c index 1da632631dac..793ad9f631fd 100644 --- a/drivers/gpu/drm/virtio/virtgpu_fence.c +++ b/drivers/gpu/drm/virtio/virtgpu_fence.c @@ -81,7 +81,7 @@ int virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev, struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv; unsigned long irq_flags; - *fence = kmalloc(sizeof(struct virtio_gpu_fence), GFP_KERNEL); + *fence = kmalloc(sizeof(struct virtio_gpu_fence), GFP_ATOMIC); if ((*fence) == NULL) return -ENOMEM; diff --git a/drivers/gpu/drm/virtio/virtgpu_gem.c b/drivers/gpu/drm/virtio/virtgpu_gem.c index cfa0d27150bd..1feb7cee3f0d 100644 --- a/drivers/gpu/drm/virtio/virtgpu_gem.c +++ b/drivers/gpu/drm/virtio/virtgpu_gem.c @@ -138,3 +138,44 @@ int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv, drm_gem_object_unreference_unlocked(gobj); return 0; } + +int virtio_gpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file) +{ + struct virtio_gpu_device *vgdev = obj->dev->dev_private; + struct virtio_gpu_fpriv *vfpriv = file->driver_priv; + struct virtio_gpu_object *qobj = gem_to_virtio_gpu_obj(obj); + int r; + + if (!vgdev->has_virgl_3d) + return 0; + + r = virtio_gpu_object_reserve(qobj, false); + if (r) + return r; + + virtio_gpu_cmd_context_attach_resource(vgdev, vfpriv->ctx_id, + qobj->hw_res_handle); + virtio_gpu_object_unreserve(qobj); + return 0; +} + +void virtio_gpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file) +{ + struct virtio_gpu_device *vgdev = obj->dev->dev_private; + struct virtio_gpu_fpriv *vfpriv = file->driver_priv; + struct virtio_gpu_object *qobj = gem_to_virtio_gpu_obj(obj); + int r; + + if (!vgdev->has_virgl_3d) + return; + + r = virtio_gpu_object_reserve(qobj, false); + if (r) + return; + + virtio_gpu_cmd_context_detach_resource(vgdev, vfpriv->ctx_id, + qobj->hw_res_handle); + virtio_gpu_object_unreserve(qobj); +} diff --git a/drivers/gpu/drm/virtio/virtgpu_ioctl.c b/drivers/gpu/drm/virtio/virtgpu_ioctl.c new file mode 100644 index 000000000000..b4de18e65db8 --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_ioctl.c @@ -0,0 +1,573 @@ +/* + * Copyright (C) 2015 Red Hat, Inc. + * All Rights Reserved. + * + * Authors: + * Dave Airlie + * Alon Levy + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <drm/drmP.h> +#include "virtgpu_drv.h" +#include <drm/virtgpu_drm.h> +#include "ttm/ttm_execbuf_util.h" + +static void convert_to_hw_box(struct virtio_gpu_box *dst, + const struct drm_virtgpu_3d_box *src) +{ + dst->x = cpu_to_le32(src->x); + dst->y = cpu_to_le32(src->y); + dst->z = cpu_to_le32(src->z); + dst->w = cpu_to_le32(src->w); + dst->h = cpu_to_le32(src->h); + dst->d = cpu_to_le32(src->d); +} + +static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct drm_virtgpu_map *virtio_gpu_map = data; + + return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev, + virtio_gpu_map->handle, + &virtio_gpu_map->offset); +} + +static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, + struct list_head *head) +{ + struct ttm_validate_buffer *buf; + struct ttm_buffer_object *bo; + struct virtio_gpu_object *qobj; + int ret; + + ret = ttm_eu_reserve_buffers(ticket, head, true, NULL); + if (ret != 0) + return ret; + + list_for_each_entry(buf, head, head) { + bo = buf->bo; + qobj = container_of(bo, struct virtio_gpu_object, tbo); + ret = ttm_bo_validate(bo, &qobj->placement, false, false); + if (ret) { + ttm_eu_backoff_reservation(ticket, head); + return ret; + } + } + return 0; +} + +static void virtio_gpu_unref_list(struct list_head *head) +{ + struct ttm_validate_buffer *buf; + struct ttm_buffer_object *bo; + struct virtio_gpu_object *qobj; + list_for_each_entry(buf, head, head) { + bo = buf->bo; + qobj = container_of(bo, struct virtio_gpu_object, tbo); + + drm_gem_object_unreference_unlocked(&qobj->gem_base); + } +} + +static int virtio_gpu_execbuffer(struct drm_device *dev, + struct drm_virtgpu_execbuffer *exbuf, + struct drm_file *drm_file) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv; + struct drm_gem_object *gobj; + struct virtio_gpu_fence *fence; + struct virtio_gpu_object *qobj; + int ret; + uint32_t *bo_handles = NULL; + void __user *user_bo_handles = NULL; + struct list_head validate_list; + struct ttm_validate_buffer *buflist = NULL; + int i; + struct ww_acquire_ctx ticket; + void *buf; + + if (vgdev->has_virgl_3d == false) + return -ENOSYS; + + INIT_LIST_HEAD(&validate_list); + if (exbuf->num_bo_handles) { + + bo_handles = drm_malloc_ab(exbuf->num_bo_handles, + sizeof(uint32_t)); + buflist = drm_calloc_large(exbuf->num_bo_handles, + sizeof(struct ttm_validate_buffer)); + if (!bo_handles || !buflist) { + drm_free_large(bo_handles); + drm_free_large(buflist); + return -ENOMEM; + } + + user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles; + if (copy_from_user(bo_handles, user_bo_handles, + exbuf->num_bo_handles * sizeof(uint32_t))) { + ret = -EFAULT; + drm_free_large(bo_handles); + drm_free_large(buflist); + return ret; + } + + for (i = 0; i < exbuf->num_bo_handles; i++) { + gobj = drm_gem_object_lookup(dev, + drm_file, bo_handles[i]); + if (!gobj) { + drm_free_large(bo_handles); + drm_free_large(buflist); + return -ENOENT; + } + + qobj = gem_to_virtio_gpu_obj(gobj); + buflist[i].bo = &qobj->tbo; + + list_add(&buflist[i].head, &validate_list); + } + drm_free_large(bo_handles); + } + + ret = virtio_gpu_object_list_validate(&ticket, &validate_list); + if (ret) + goto out_free; + + buf = kmalloc(exbuf->size, GFP_KERNEL); + if (!buf) { + ret = -ENOMEM; + goto out_unresv; + } + if (copy_from_user(buf, (void __user *)(uintptr_t)exbuf->command, + exbuf->size)) { + kfree(buf); + ret = -EFAULT; + goto out_unresv; + } + virtio_gpu_cmd_submit(vgdev, buf, exbuf->size, + vfpriv->ctx_id, &fence); + + ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f); + + /* fence the command bo */ + virtio_gpu_unref_list(&validate_list); + drm_free_large(buflist); + fence_put(&fence->f); + return 0; + +out_unresv: + ttm_eu_backoff_reservation(&ticket, &validate_list); +out_free: + virtio_gpu_unref_list(&validate_list); + drm_free_large(buflist); + return ret; +} + +/* + * Usage of execbuffer: + * Relocations need to take into account the full VIRTIO_GPUDrawable size. + * However, the command as passed from user space must *not* contain the initial + * VIRTIO_GPUReleaseInfo struct (first XXX bytes) + */ +static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_virtgpu_execbuffer *execbuffer = data; + return virtio_gpu_execbuffer(dev, execbuffer, file_priv); +} + + +static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct drm_virtgpu_getparam *param = data; + int value; + + switch (param->param) { + case VIRTGPU_PARAM_3D_FEATURES: + value = vgdev->has_virgl_3d == true ? 1 : 0; + break; + default: + return -EINVAL; + } + if (copy_to_user((void __user *)(unsigned long)param->value, + &value, sizeof(int))) { + return -EFAULT; + } + return 0; +} + +static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct drm_virtgpu_resource_create *rc = data; + int ret; + uint32_t res_id; + struct virtio_gpu_object *qobj; + struct drm_gem_object *obj; + uint32_t handle = 0; + uint32_t size; + struct list_head validate_list; + struct ttm_validate_buffer mainbuf; + struct virtio_gpu_fence *fence = NULL; + struct ww_acquire_ctx ticket; + struct virtio_gpu_resource_create_3d rc_3d; + + if (vgdev->has_virgl_3d == false) { + if (rc->depth > 1) + return -EINVAL; + if (rc->nr_samples > 1) + return -EINVAL; + if (rc->last_level > 1) + return -EINVAL; + if (rc->target != 2) + return -EINVAL; + if (rc->array_size > 1) + return -EINVAL; + } + + INIT_LIST_HEAD(&validate_list); + memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer)); + + virtio_gpu_resource_id_get(vgdev, &res_id); + + size = rc->size; + + /* allocate a single page size object */ + if (size == 0) + size = PAGE_SIZE; + + qobj = virtio_gpu_alloc_object(dev, size, false, false); + if (IS_ERR(qobj)) { + ret = PTR_ERR(qobj); + goto fail_id; + } + obj = &qobj->gem_base; + + if (!vgdev->has_virgl_3d) { + virtio_gpu_cmd_create_resource(vgdev, res_id, rc->format, + rc->width, rc->height); + + ret = virtio_gpu_object_attach(vgdev, qobj, res_id, NULL); + } else { + /* use a gem reference since unref list undoes them */ + drm_gem_object_reference(&qobj->gem_base); + mainbuf.bo = &qobj->tbo; + list_add(&mainbuf.head, &validate_list); + + ret = virtio_gpu_object_list_validate(&ticket, &validate_list); + if (ret) { + DRM_DEBUG("failed to validate\n"); + goto fail_unref; + } + + rc_3d.resource_id = cpu_to_le32(res_id); + rc_3d.target = cpu_to_le32(rc->target); + rc_3d.format = cpu_to_le32(rc->format); + rc_3d.bind = cpu_to_le32(rc->bind); + rc_3d.width = cpu_to_le32(rc->width); + rc_3d.height = cpu_to_le32(rc->height); + rc_3d.depth = cpu_to_le32(rc->depth); + rc_3d.array_size = cpu_to_le32(rc->array_size); + rc_3d.last_level = cpu_to_le32(rc->last_level); + rc_3d.nr_samples = cpu_to_le32(rc->nr_samples); + rc_3d.flags = cpu_to_le32(rc->flags); + + virtio_gpu_cmd_resource_create_3d(vgdev, &rc_3d, NULL); + ret = virtio_gpu_object_attach(vgdev, qobj, res_id, &fence); + if (ret) { + ttm_eu_backoff_reservation(&ticket, &validate_list); + goto fail_unref; + } + ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f); + } + + qobj->hw_res_handle = res_id; + + ret = drm_gem_handle_create(file_priv, obj, &handle); + if (ret) { + + drm_gem_object_release(obj); + if (vgdev->has_virgl_3d) { + virtio_gpu_unref_list(&validate_list); + fence_put(&fence->f); + } + return ret; + } + drm_gem_object_unreference_unlocked(obj); + + rc->res_handle = res_id; /* similiar to a VM address */ + rc->bo_handle = handle; + + if (vgdev->has_virgl_3d) { + virtio_gpu_unref_list(&validate_list); + fence_put(&fence->f); + } + return 0; +fail_unref: + if (vgdev->has_virgl_3d) { + virtio_gpu_unref_list(&validate_list); + fence_put(&fence->f); + } +//fail_obj: +// drm_gem_object_handle_unreference_unlocked(obj); +fail_id: + virtio_gpu_resource_id_put(vgdev, res_id); + return ret; +} + +static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_virtgpu_resource_info *ri = data; + struct drm_gem_object *gobj = NULL; + struct virtio_gpu_object *qobj = NULL; + + gobj = drm_gem_object_lookup(dev, file_priv, ri->bo_handle); + if (gobj == NULL) + return -ENOENT; + + qobj = gem_to_virtio_gpu_obj(gobj); + + ri->size = qobj->gem_base.size; + ri->res_handle = qobj->hw_res_handle; + drm_gem_object_unreference_unlocked(gobj); + return 0; +} + +static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, + void *data, + struct drm_file *file) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_fpriv *vfpriv = file->driver_priv; + struct drm_virtgpu_3d_transfer_from_host *args = data; + struct drm_gem_object *gobj = NULL; + struct virtio_gpu_object *qobj = NULL; + struct virtio_gpu_fence *fence; + int ret; + u32 offset = args->offset; + struct virtio_gpu_box box; + + if (vgdev->has_virgl_3d == false) + return -ENOSYS; + + gobj = drm_gem_object_lookup(dev, file, args->bo_handle); + if (gobj == NULL) + return -ENOENT; + + qobj = gem_to_virtio_gpu_obj(gobj); + + ret = virtio_gpu_object_reserve(qobj, false); + if (ret) + goto out; + + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, + true, false); + if (unlikely(ret)) + goto out_unres; + + convert_to_hw_box(&box, &args->box); + virtio_gpu_cmd_transfer_from_host_3d + (vgdev, qobj->hw_res_handle, + vfpriv->ctx_id, offset, args->level, + &box, &fence); + reservation_object_add_excl_fence(qobj->tbo.resv, + &fence->f); + + fence_put(&fence->f); +out_unres: + virtio_gpu_object_unreserve(qobj); +out: + drm_gem_object_unreference_unlocked(gobj); + return ret; +} + +static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_fpriv *vfpriv = file->driver_priv; + struct drm_virtgpu_3d_transfer_to_host *args = data; + struct drm_gem_object *gobj = NULL; + struct virtio_gpu_object *qobj = NULL; + struct virtio_gpu_fence *fence; + struct virtio_gpu_box box; + int ret; + u32 offset = args->offset; + + gobj = drm_gem_object_lookup(dev, file, args->bo_handle); + if (gobj == NULL) + return -ENOENT; + + qobj = gem_to_virtio_gpu_obj(gobj); + + ret = virtio_gpu_object_reserve(qobj, false); + if (ret) + goto out; + + ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, + true, false); + if (unlikely(ret)) + goto out_unres; + + convert_to_hw_box(&box, &args->box); + if (!vgdev->has_virgl_3d) { + virtio_gpu_cmd_transfer_to_host_2d + (vgdev, qobj->hw_res_handle, offset, + box.w, box.h, box.x, box.y, NULL); + } else { + virtio_gpu_cmd_transfer_to_host_3d + (vgdev, qobj->hw_res_handle, + vfpriv ? vfpriv->ctx_id : 0, offset, + args->level, &box, &fence); + reservation_object_add_excl_fence(qobj->tbo.resv, + &fence->f); + fence_put(&fence->f); + } + +out_unres: + virtio_gpu_object_unreserve(qobj); +out: + drm_gem_object_unreference_unlocked(gobj); + return ret; +} + +static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_virtgpu_3d_wait *args = data; + struct drm_gem_object *gobj = NULL; + struct virtio_gpu_object *qobj = NULL; + int ret; + bool nowait = false; + + gobj = drm_gem_object_lookup(dev, file, args->handle); + if (gobj == NULL) + return -ENOENT; + + qobj = gem_to_virtio_gpu_obj(gobj); + + if (args->flags & VIRTGPU_WAIT_NOWAIT) + nowait = true; + ret = virtio_gpu_object_wait(qobj, nowait); + + drm_gem_object_unreference_unlocked(gobj); + return ret; +} + +static int virtio_gpu_get_caps_ioctl(struct drm_device *dev, + void *data, struct drm_file *file) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct drm_virtgpu_get_caps *args = data; + int size; + int i; + int found_valid = -1; + int ret; + struct virtio_gpu_drv_cap_cache *cache_ent; + void *ptr; + if (vgdev->num_capsets == 0) + return -ENOSYS; + + spin_lock(&vgdev->display_info_lock); + for (i = 0; i < vgdev->num_capsets; i++) { + if (vgdev->capsets[i].id == args->cap_set_id) { + if (vgdev->capsets[i].max_version >= args->cap_set_ver) { + found_valid = i; + break; + } + } + } + + if (found_valid == -1) { + spin_unlock(&vgdev->display_info_lock); + return -EINVAL; + } + + size = vgdev->capsets[found_valid].max_size; + if (args->size > size) { + spin_unlock(&vgdev->display_info_lock); + return -EINVAL; + } + + list_for_each_entry(cache_ent, &vgdev->cap_cache, head) { + if (cache_ent->id == args->cap_set_id && + cache_ent->version == args->cap_set_ver) { + ptr = cache_ent->caps_cache; + spin_unlock(&vgdev->display_info_lock); + goto copy_exit; + } + } + spin_unlock(&vgdev->display_info_lock); + + /* not in cache - need to talk to hw */ + virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver, + &cache_ent); + + ret = wait_event_timeout(vgdev->resp_wq, + atomic_read(&cache_ent->is_valid), 5 * HZ); + + ptr = cache_ent->caps_cache; + +copy_exit: + if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size)) + return -EFAULT; + + return 0; +} + +struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = { + DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + + DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + + DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + + DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE, + virtio_gpu_resource_create_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + + DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + + /* make transfer async to the main ring? - no sure, can we + thread these in the underlying GL */ + DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST, + virtio_gpu_transfer_from_host_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST, + virtio_gpu_transfer_to_host_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + + DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), + + DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl, + DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), +}; diff --git a/drivers/gpu/drm/virtio/virtgpu_kms.c b/drivers/gpu/drm/virtio/virtgpu_kms.c index 782766c00d70..06496a128162 100644 --- a/drivers/gpu/drm/virtio/virtgpu_kms.c +++ b/drivers/gpu/drm/virtio/virtgpu_kms.c @@ -52,6 +52,41 @@ static void virtio_gpu_config_changed_work_func(struct work_struct *work) events_clear, &events_clear); } +static void virtio_gpu_ctx_id_get(struct virtio_gpu_device *vgdev, + uint32_t *resid) +{ + int handle; + + idr_preload(GFP_KERNEL); + spin_lock(&vgdev->ctx_id_idr_lock); + handle = idr_alloc(&vgdev->ctx_id_idr, NULL, 1, 0, 0); + spin_unlock(&vgdev->ctx_id_idr_lock); + idr_preload_end(); + *resid = handle; +} + +static void virtio_gpu_ctx_id_put(struct virtio_gpu_device *vgdev, uint32_t id) +{ + spin_lock(&vgdev->ctx_id_idr_lock); + idr_remove(&vgdev->ctx_id_idr, id); + spin_unlock(&vgdev->ctx_id_idr_lock); +} + +static void virtio_gpu_context_create(struct virtio_gpu_device *vgdev, + uint32_t nlen, const char *name, + uint32_t *ctx_id) +{ + virtio_gpu_ctx_id_get(vgdev, ctx_id); + virtio_gpu_cmd_context_create(vgdev, *ctx_id, nlen, name); +} + +static void virtio_gpu_context_destroy(struct virtio_gpu_device *vgdev, + uint32_t ctx_id) +{ + virtio_gpu_cmd_context_destroy(vgdev, ctx_id); + virtio_gpu_ctx_id_put(vgdev, ctx_id); +} + static void virtio_gpu_init_vq(struct virtio_gpu_queue *vgvq, void (*work_func)(struct work_struct *work)) { @@ -60,6 +95,36 @@ static void virtio_gpu_init_vq(struct virtio_gpu_queue *vgvq, INIT_WORK(&vgvq->dequeue_work, work_func); } +static void virtio_gpu_get_capsets(struct virtio_gpu_device *vgdev, + int num_capsets) +{ + int i, ret; + + vgdev->capsets = kcalloc(num_capsets, + sizeof(struct virtio_gpu_drv_capset), + GFP_KERNEL); + if (!vgdev->capsets) { + DRM_ERROR("failed to allocate cap sets\n"); + return; + } + for (i = 0; i < num_capsets; i++) { + virtio_gpu_cmd_get_capset_info(vgdev, i); + ret = wait_event_timeout(vgdev->resp_wq, + vgdev->capsets[i].id > 0, 5 * HZ); + if (ret == 0) { + DRM_ERROR("timed out waiting for cap set %d\n", i); + kfree(vgdev->capsets); + vgdev->capsets = NULL; + return; + } + DRM_INFO("cap set %d: id %d, max-version %d, max-size %d\n", + i, vgdev->capsets[i].id, + vgdev->capsets[i].max_version, + vgdev->capsets[i].max_size); + } + vgdev->num_capsets = num_capsets; +} + int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags) { static vq_callback_t *callbacks[] = { @@ -70,7 +135,7 @@ int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags) struct virtio_gpu_device *vgdev; /* this will expand later */ struct virtqueue *vqs[2]; - u32 num_scanouts; + u32 num_scanouts, num_capsets; int ret; if (!virtio_has_feature(dev->virtdev, VIRTIO_F_VERSION_1)) @@ -96,9 +161,15 @@ int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags) spin_lock_init(&vgdev->fence_drv.lock); INIT_LIST_HEAD(&vgdev->fence_drv.fences); + INIT_LIST_HEAD(&vgdev->cap_cache); INIT_WORK(&vgdev->config_changed_work, virtio_gpu_config_changed_work_func); + if (virtio_has_feature(vgdev->vdev, VIRTIO_GPU_F_VIRGL)) + vgdev->has_virgl_3d = true; + DRM_INFO("virgl 3d acceleration %s\n", + vgdev->has_virgl_3d ? "enabled" : "not available"); + ret = vgdev->vdev->config->find_vqs(vgdev->vdev, 2, vqs, callbacks, names); if (ret) { @@ -129,6 +200,11 @@ int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags) ret = -EINVAL; goto err_scanouts; } + DRM_INFO("number of scanouts: %d\n", num_scanouts); + + virtio_cread(vgdev->vdev, struct virtio_gpu_config, + num_capsets, &num_capsets); + DRM_INFO("number of cap sets: %d\n", num_capsets); ret = virtio_gpu_modeset_init(vgdev); if (ret) @@ -137,6 +213,8 @@ int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags) virtio_device_ready(vgdev->vdev); vgdev->vqs_ready = true; + if (num_capsets) + virtio_gpu_get_capsets(vgdev, num_capsets); virtio_gpu_cmd_get_display_info(vgdev); wait_event_timeout(vgdev->resp_wq, !vgdev->display_info_pending, 5 * HZ); @@ -157,6 +235,16 @@ err_vqs: return ret; } +static void virtio_gpu_cleanup_cap_cache(struct virtio_gpu_device *vgdev) +{ + struct virtio_gpu_drv_cap_cache *cache_ent, *tmp; + + list_for_each_entry_safe(cache_ent, tmp, &vgdev->cap_cache, head) { + kfree(cache_ent->caps_cache); + kfree(cache_ent); + } +} + int virtio_gpu_driver_unload(struct drm_device *dev) { struct virtio_gpu_device *vgdev = dev->dev_private; @@ -170,6 +258,49 @@ int virtio_gpu_driver_unload(struct drm_device *dev) virtio_gpu_modeset_fini(vgdev); virtio_gpu_ttm_fini(vgdev); virtio_gpu_free_vbufs(vgdev); + virtio_gpu_cleanup_cap_cache(vgdev); + kfree(vgdev->capsets); kfree(vgdev); return 0; } + +int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_fpriv *vfpriv; + uint32_t id; + char dbgname[64], tmpname[TASK_COMM_LEN]; + + /* can't create contexts without 3d renderer */ + if (!vgdev->has_virgl_3d) + return 0; + + get_task_comm(tmpname, current); + snprintf(dbgname, sizeof(dbgname), "%s", tmpname); + dbgname[63] = 0; + /* allocate a virt GPU context for this opener */ + vfpriv = kzalloc(sizeof(*vfpriv), GFP_KERNEL); + if (!vfpriv) + return -ENOMEM; + + virtio_gpu_context_create(vgdev, strlen(dbgname), dbgname, &id); + + vfpriv->ctx_id = id; + file->driver_priv = vfpriv; + return 0; +} + +void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file) +{ + struct virtio_gpu_device *vgdev = dev->dev_private; + struct virtio_gpu_fpriv *vfpriv; + + if (!vgdev->has_virgl_3d) + return; + + vfpriv = file->driver_priv; + + virtio_gpu_context_destroy(vgdev, vfpriv->ctx_id); + kfree(vfpriv); + file->driver_priv = NULL; +} diff --git a/drivers/gpu/drm/virtio/virtgpu_object.c b/drivers/gpu/drm/virtio/virtgpu_object.c index 2c624c784c1d..f300eba95bb1 100644 --- a/drivers/gpu/drm/virtio/virtgpu_object.c +++ b/drivers/gpu/drm/virtio/virtgpu_object.c @@ -82,24 +82,19 @@ int virtio_gpu_object_create(struct virtio_gpu_device *vgdev, size = roundup(size, PAGE_SIZE); ret = drm_gem_object_init(vgdev->ddev, &bo->gem_base, size); if (ret != 0) - goto err_gem_init; + return ret; bo->dumb = false; virtio_gpu_init_ttm_placement(bo, pinned); ret = ttm_bo_init(&vgdev->mman.bdev, &bo->tbo, size, type, &bo->placement, 0, !kernel, NULL, acc_size, NULL, NULL, &virtio_gpu_ttm_bo_destroy); + /* ttm_bo_init failure will call the destroy */ if (ret != 0) - goto err_ttm_init; + return ret; *bo_ptr = bo; return 0; - -err_ttm_init: - drm_gem_object_release(&bo->gem_base); -err_gem_init: - kfree(bo); - return ret; } int virtio_gpu_object_kmap(struct virtio_gpu_object *bo, void **ptr) diff --git a/drivers/gpu/drm/virtio/virtgpu_prime.c b/drivers/gpu/drm/virtio/virtgpu_prime.c new file mode 100644 index 000000000000..385e0eb9826a --- /dev/null +++ b/drivers/gpu/drm/virtio/virtgpu_prime.c @@ -0,0 +1,71 @@ +/* + * Copyright 2014 Canonical + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Andreas Pokorny + */ + +#include "virtgpu_drv.h" + +/* Empty Implementations as there should not be any other driver for a virtual + * device that might share buffers with virtgpu */ + +int virtgpu_gem_prime_pin(struct drm_gem_object *obj) +{ + WARN_ONCE(1, "not implemented"); + return -ENODEV; +} + +void virtgpu_gem_prime_unpin(struct drm_gem_object *obj) +{ + WARN_ONCE(1, "not implemented"); +} + + +struct sg_table *virtgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) +{ + WARN_ONCE(1, "not implemented"); + return ERR_PTR(-ENODEV); +} + +struct drm_gem_object *virtgpu_gem_prime_import_sg_table( + struct drm_device *dev, struct dma_buf_attachment *attach, + struct sg_table *table) +{ + WARN_ONCE(1, "not implemented"); + return ERR_PTR(-ENODEV); +} + +void *virtgpu_gem_prime_vmap(struct drm_gem_object *obj) +{ + WARN_ONCE(1, "not implemented"); + return ERR_PTR(-ENODEV); +} + +void virtgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr) +{ + WARN_ONCE(1, "not implemented"); +} + +int virtgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *area) +{ + return -ENODEV; +} diff --git a/drivers/gpu/drm/virtio/virtgpu_ttm.c b/drivers/gpu/drm/virtio/virtgpu_ttm.c index b092d7b9a292..9fd924cd2b7f 100644 --- a/drivers/gpu/drm/virtio/virtgpu_ttm.c +++ b/drivers/gpu/drm/virtio/virtgpu_ttm.c @@ -32,6 +32,7 @@ #include <ttm/ttm_module.h> #include <drm/drmP.h> #include <drm/drm.h> +#include <drm/virtgpu_drm.h> #include "virtgpu_drv.h" #include <linux/delay.h> diff --git a/drivers/gpu/drm/virtio/virtgpu_vq.c b/drivers/gpu/drm/virtio/virtgpu_vq.c index 1698669f4185..5a0f8a745b9d 100644 --- a/drivers/gpu/drm/virtio/virtgpu_vq.c +++ b/drivers/gpu/drm/virtio/virtgpu_vq.c @@ -293,8 +293,8 @@ void virtio_gpu_dequeue_cursor_func(struct work_struct *work) wake_up(&vgdev->cursorq.ack_queue); } -static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev, - struct virtio_gpu_vbuffer *vbuf) +static int virtio_gpu_queue_ctrl_buffer_locked(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) { struct virtqueue *vq = vgdev->ctrlq.vq; struct scatterlist *sgs[3], vcmd, vout, vresp; @@ -320,7 +320,6 @@ static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev, incnt++; } - spin_lock(&vgdev->ctrlq.qlock); retry: ret = virtqueue_add_sgs(vq, sgs, outcnt, incnt, vbuf, GFP_ATOMIC); if (ret == -ENOSPC) { @@ -331,13 +330,55 @@ retry: } else { virtqueue_kick(vq); } - spin_unlock(&vgdev->ctrlq.qlock); if (!ret) ret = vq->num_free; return ret; } +static int virtio_gpu_queue_ctrl_buffer(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) +{ + int rc; + + spin_lock(&vgdev->ctrlq.qlock); + rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf); + spin_unlock(&vgdev->ctrlq.qlock); + return rc; +} + +static int virtio_gpu_queue_fenced_ctrl_buffer(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf, + struct virtio_gpu_ctrl_hdr *hdr, + struct virtio_gpu_fence **fence) +{ + struct virtqueue *vq = vgdev->ctrlq.vq; + int rc; + +again: + spin_lock(&vgdev->ctrlq.qlock); + + /* + * Make sure we have enouth space in the virtqueue. If not + * wait here until we have. + * + * Without that virtio_gpu_queue_ctrl_buffer_nolock might have + * to wait for free space, which can result in fence ids being + * submitted out-of-order. + */ + if (vq->num_free < 3) { + spin_unlock(&vgdev->ctrlq.qlock); + wait_event(vgdev->ctrlq.ack_queue, vq->num_free >= 3); + goto again; + } + + if (fence) + virtio_gpu_fence_emit(vgdev, hdr, fence); + rc = virtio_gpu_queue_ctrl_buffer_locked(vgdev, vbuf); + spin_unlock(&vgdev->ctrlq.qlock); + return rc; +} + static int virtio_gpu_queue_cursor(struct virtio_gpu_device *vgdev, struct virtio_gpu_vbuffer *vbuf) { @@ -490,9 +531,7 @@ void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev, cmd_p->r.x = x; cmd_p->r.y = y; - if (fence) - virtio_gpu_fence_emit(vgdev, &cmd_p->hdr, fence); - virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); } static void @@ -515,9 +554,7 @@ virtio_gpu_cmd_resource_attach_backing(struct virtio_gpu_device *vgdev, vbuf->data_buf = ents; vbuf->data_size = sizeof(*ents) * nents; - if (fence) - virtio_gpu_fence_emit(vgdev, &cmd_p->hdr, fence); - virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); } static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev, @@ -549,6 +586,47 @@ static void virtio_gpu_cmd_get_display_info_cb(struct virtio_gpu_device *vgdev, drm_kms_helper_hotplug_event(vgdev->ddev); } +static void virtio_gpu_cmd_get_capset_info_cb(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) +{ + struct virtio_gpu_get_capset_info *cmd = + (struct virtio_gpu_get_capset_info *)vbuf->buf; + struct virtio_gpu_resp_capset_info *resp = + (struct virtio_gpu_resp_capset_info *)vbuf->resp_buf; + int i = le32_to_cpu(cmd->capset_index); + + spin_lock(&vgdev->display_info_lock); + vgdev->capsets[i].id = le32_to_cpu(resp->capset_id); + vgdev->capsets[i].max_version = le32_to_cpu(resp->capset_max_version); + vgdev->capsets[i].max_size = le32_to_cpu(resp->capset_max_size); + spin_unlock(&vgdev->display_info_lock); + wake_up(&vgdev->resp_wq); +} + +static void virtio_gpu_cmd_capset_cb(struct virtio_gpu_device *vgdev, + struct virtio_gpu_vbuffer *vbuf) +{ + struct virtio_gpu_get_capset *cmd = + (struct virtio_gpu_get_capset *)vbuf->buf; + struct virtio_gpu_resp_capset *resp = + (struct virtio_gpu_resp_capset *)vbuf->resp_buf; + struct virtio_gpu_drv_cap_cache *cache_ent; + + spin_lock(&vgdev->display_info_lock); + list_for_each_entry(cache_ent, &vgdev->cap_cache, head) { + if (cache_ent->version == le32_to_cpu(cmd->capset_version) && + cache_ent->id == le32_to_cpu(cmd->capset_id)) { + memcpy(cache_ent->caps_cache, resp->capset_data, + cache_ent->size); + atomic_set(&cache_ent->is_valid, 1); + break; + } + } + spin_unlock(&vgdev->display_info_lock); + wake_up(&vgdev->resp_wq); +} + + int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev) { struct virtio_gpu_ctrl_hdr *cmd_p; @@ -572,6 +650,230 @@ int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev) return 0; } +int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx) +{ + struct virtio_gpu_get_capset_info *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + void *resp_buf; + + resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset_info), + GFP_KERNEL); + if (!resp_buf) + return -ENOMEM; + + cmd_p = virtio_gpu_alloc_cmd_resp + (vgdev, &virtio_gpu_cmd_get_capset_info_cb, &vbuf, + sizeof(*cmd_p), sizeof(struct virtio_gpu_resp_capset_info), + resp_buf); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET_INFO); + cmd_p->capset_index = cpu_to_le32(idx); + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); + return 0; +} + +int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev, + int idx, int version, + struct virtio_gpu_drv_cap_cache **cache_p) +{ + struct virtio_gpu_get_capset *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + int max_size = vgdev->capsets[idx].max_size; + struct virtio_gpu_drv_cap_cache *cache_ent; + void *resp_buf; + + if (idx > vgdev->num_capsets) + return -EINVAL; + + if (version > vgdev->capsets[idx].max_version) + return -EINVAL; + + cache_ent = kzalloc(sizeof(*cache_ent), GFP_KERNEL); + if (!cache_ent) + return -ENOMEM; + + cache_ent->caps_cache = kmalloc(max_size, GFP_KERNEL); + if (!cache_ent->caps_cache) { + kfree(cache_ent); + return -ENOMEM; + } + + resp_buf = kzalloc(sizeof(struct virtio_gpu_resp_capset) + max_size, + GFP_KERNEL); + if (!resp_buf) { + kfree(cache_ent->caps_cache); + kfree(cache_ent); + return -ENOMEM; + } + + cache_ent->version = version; + cache_ent->id = vgdev->capsets[idx].id; + atomic_set(&cache_ent->is_valid, 0); + cache_ent->size = max_size; + spin_lock(&vgdev->display_info_lock); + list_add_tail(&cache_ent->head, &vgdev->cap_cache); + spin_unlock(&vgdev->display_info_lock); + + cmd_p = virtio_gpu_alloc_cmd_resp + (vgdev, &virtio_gpu_cmd_capset_cb, &vbuf, sizeof(*cmd_p), + sizeof(struct virtio_gpu_resp_capset) + max_size, + resp_buf); + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_GET_CAPSET); + cmd_p->capset_id = cpu_to_le32(vgdev->capsets[idx].id); + cmd_p->capset_version = cpu_to_le32(version); + *cache_p = cache_ent; + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); + + return 0; +} + +void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id, + uint32_t nlen, const char *name) +{ + struct virtio_gpu_ctx_create *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_CREATE); + cmd_p->hdr.ctx_id = cpu_to_le32(id); + cmd_p->nlen = cpu_to_le32(nlen); + strncpy(cmd_p->debug_name, name, sizeof(cmd_p->debug_name)-1); + cmd_p->debug_name[sizeof(cmd_p->debug_name)-1] = 0; + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev, + uint32_t id) +{ + struct virtio_gpu_ctx_destroy *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DESTROY); + cmd_p->hdr.ctx_id = cpu_to_le32(id); + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev, + uint32_t ctx_id, + uint32_t resource_id) +{ + struct virtio_gpu_ctx_resource *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE); + cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id); + cmd_p->resource_id = cpu_to_le32(resource_id); + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); + +} + +void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev, + uint32_t ctx_id, + uint32_t resource_id) +{ + struct virtio_gpu_ctx_resource *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE); + cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id); + cmd_p->resource_id = cpu_to_le32(resource_id); + virtio_gpu_queue_ctrl_buffer(vgdev, vbuf); +} + +void +virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev, + struct virtio_gpu_resource_create_3d *rc_3d, + struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_resource_create_3d *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + *cmd_p = *rc_3d; + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_RESOURCE_CREATE_3D); + cmd_p->hdr.flags = 0; + + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); +} + +void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev, + uint32_t resource_id, uint32_t ctx_id, + uint64_t offset, uint32_t level, + struct virtio_gpu_box *box, + struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_transfer_host_3d *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D); + cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id); + cmd_p->resource_id = cpu_to_le32(resource_id); + cmd_p->box = *box; + cmd_p->offset = cpu_to_le64(offset); + cmd_p->level = cpu_to_le32(level); + + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); +} + +void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev, + uint32_t resource_id, uint32_t ctx_id, + uint64_t offset, uint32_t level, + struct virtio_gpu_box *box, + struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_transfer_host_3d *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D); + cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id); + cmd_p->resource_id = cpu_to_le32(resource_id); + cmd_p->box = *box; + cmd_p->offset = cpu_to_le64(offset); + cmd_p->level = cpu_to_le32(level); + + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); +} + +void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev, + void *data, uint32_t data_size, + uint32_t ctx_id, struct virtio_gpu_fence **fence) +{ + struct virtio_gpu_cmd_submit *cmd_p; + struct virtio_gpu_vbuffer *vbuf; + + cmd_p = virtio_gpu_alloc_cmd(vgdev, &vbuf, sizeof(*cmd_p)); + memset(cmd_p, 0, sizeof(*cmd_p)); + + vbuf->data_buf = data; + vbuf->data_size = data_size; + + cmd_p->hdr.type = cpu_to_le32(VIRTIO_GPU_CMD_SUBMIT_3D); + cmd_p->hdr.ctx_id = cpu_to_le32(ctx_id); + cmd_p->size = cpu_to_le32(data_size); + + virtio_gpu_queue_fenced_ctrl_buffer(vgdev, vbuf, &cmd_p->hdr, fence); +} + int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev, struct virtio_gpu_object *obj, uint32_t resource_id, diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c index 5ae8f921da2a..8a76821177a6 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf.c @@ -681,6 +681,14 @@ static bool vmw_cmdbuf_try_alloc(struct vmw_cmdbuf_man *man, 0, 0, DRM_MM_SEARCH_DEFAULT, DRM_MM_CREATE_DEFAULT); + if (ret) { + (void) vmw_cmdbuf_man_process(man); + ret = drm_mm_insert_node_generic(&man->mm, info->node, + info->page_size, 0, 0, + DRM_MM_SEARCH_DEFAULT, + DRM_MM_CREATE_DEFAULT); + } + spin_unlock_bh(&man->lock); info->done = !ret; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index 2c7a25c71af2..a09cf8529b9f 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c @@ -146,73 +146,73 @@ static const struct drm_ioctl_desc vmw_ioctls[] = { VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, vmw_kms_cursor_bypass_ioctl, - DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), + DRM_MASTER | DRM_CONTROL_ALLOW), VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, - DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), + DRM_MASTER | DRM_CONTROL_ALLOW), VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, - DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), + DRM_MASTER | DRM_CONTROL_ALLOW), VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, - DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), + DRM_MASTER | DRM_CONTROL_ALLOW), VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), - VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | DRM_UNLOCKED | + DRM_AUTH | DRM_RENDER_ALLOW), + VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, vmw_fence_obj_signaled_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), /* these allow direct access to the framebuffers mark as master only */ VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, - DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), + DRM_MASTER | DRM_AUTH), VMW_IOCTL_DEF(VMW_PRESENT_READBACK, vmw_present_readback_ioctl, - DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), + DRM_MASTER | DRM_AUTH), VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl, - DRM_MASTER | DRM_UNLOCKED), + DRM_MASTER), VMW_IOCTL_DEF(VMW_CREATE_SHADER, vmw_shader_define_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_UNREF_SHADER, vmw_shader_destroy_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, vmw_gb_surface_define_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, vmw_gb_surface_reference_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_SYNCCPU, vmw_user_dmabuf_synccpu_ioctl, - DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_RENDER_ALLOW), VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, vmw_extended_context_define_ioctl, - DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), + DRM_AUTH | DRM_RENDER_ALLOW), }; static struct pci_device_id vmw_pci_id_list[] = { @@ -643,7 +643,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) init_waitqueue_head(&dev_priv->fence_queue); init_waitqueue_head(&dev_priv->fifo_queue); dev_priv->fence_queue_waiters = 0; - atomic_set(&dev_priv->fifo_queue_waiters, 0); + dev_priv->fifo_queue_waiters = 0; dev_priv->used_memory_size = 0; @@ -752,8 +752,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); dev_priv->active_master = &dev_priv->fbdev_master; - dev_priv->mmio_virt = ioremap_cache(dev_priv->mmio_start, - dev_priv->mmio_size); + dev_priv->mmio_virt = memremap(dev_priv->mmio_start, + dev_priv->mmio_size, MEMREMAP_WB); if (unlikely(dev_priv->mmio_virt == NULL)) { ret = -ENOMEM; @@ -907,7 +907,7 @@ out_no_irq: out_no_device: ttm_object_device_release(&dev_priv->tdev); out_err4: - iounmap(dev_priv->mmio_virt); + memunmap(dev_priv->mmio_virt); out_err3: vmw_ttm_global_release(dev_priv); out_err0: @@ -958,7 +958,7 @@ static int vmw_driver_unload(struct drm_device *dev) pci_release_regions(dev->pdev); ttm_object_device_release(&dev_priv->tdev); - iounmap(dev_priv->mmio_virt); + memunmap(dev_priv->mmio_virt); if (dev_priv->ctx.staged_bindings) vmw_binding_state_free(dev_priv->ctx.staged_bindings); vmw_ttm_global_release(dev_priv); @@ -1062,14 +1062,6 @@ static struct vmw_master *vmw_master_check(struct drm_device *dev, mutex_unlock(&dev->master_mutex); /* - * Taking the drm_global_mutex after the TTM lock might deadlock - */ - if (!(flags & DRM_UNLOCKED)) { - DRM_ERROR("Refusing locked ioctl access.\n"); - return ERR_PTR(-EDEADLK); - } - - /* * Take the TTM lock. Possibly sleep waiting for the authenticating * master to become master again, or for a SIGTERM if the * authenticating master exits. diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h index f19fd39b43e1..a8ae9dfb83b7 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h @@ -375,7 +375,7 @@ struct vmw_private { uint32_t stdu_max_height; uint32_t initial_width; uint32_t initial_height; - u32 __iomem *mmio_virt; + u32 *mmio_virt; uint32_t capabilities; uint32_t max_gmr_ids; uint32_t max_gmr_pages; @@ -440,13 +440,12 @@ struct vmw_private { spinlock_t waiter_lock; int fence_queue_waiters; /* Protected by waiter_lock */ int goal_queue_waiters; /* Protected by waiter_lock */ - int cmdbuf_waiters; /* Protected by irq_lock */ - int error_waiters; /* Protected by irq_lock */ - atomic_t fifo_queue_waiters; + int cmdbuf_waiters; /* Protected by waiter_lock */ + int error_waiters; /* Protected by waiter_lock */ + int fifo_queue_waiters; /* Protected by waiter_lock */ uint32_t last_read_seqno; - spinlock_t irq_lock; struct vmw_fence_manager *fman; - uint32_t irq_mask; + uint32_t irq_mask; /* Updates protected by waiter_lock */ /* * Device state @@ -914,9 +913,9 @@ void vmw_kms_idle_workqueues(struct vmw_master *vmaster); bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv, uint32_t pitch, uint32_t height); -u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc); -int vmw_enable_vblank(struct drm_device *dev, int crtc); -void vmw_disable_vblank(struct drm_device *dev, int crtc); +u32 vmw_get_vblank_counter(struct drm_device *dev, unsigned int pipe); +int vmw_enable_vblank(struct drm_device *dev, unsigned int pipe); +void vmw_disable_vblank(struct drm_device *dev, unsigned int pipe); int vmw_kms_present(struct vmw_private *dev_priv, struct drm_file *file_priv, struct vmw_framebuffer *vfb, @@ -1206,4 +1205,30 @@ static inline void vmw_fifo_resource_dec(struct vmw_private *dev_priv) { atomic_dec(&dev_priv->num_fifo_resources); } + +/** + * vmw_mmio_read - Perform a MMIO read from volatile memory + * + * @addr: The address to read from + * + * This function is intended to be equivalent to ioread32() on + * memremap'd memory, but without byteswapping. + */ +static inline u32 vmw_mmio_read(u32 *addr) +{ + return READ_ONCE(*addr); +} + +/** + * vmw_mmio_write - Perform a MMIO write to volatile memory + * + * @addr: The address to write to + * + * This function is intended to be equivalent to iowrite32 on + * memremap'd memory, but without byteswapping. + */ +static inline void vmw_mmio_write(u32 value, u32 *addr) +{ + WRITE_ONCE(*addr, value); +} #endif diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c index 567ddede51d1..8e689b439890 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c @@ -142,8 +142,8 @@ static bool vmw_fence_enable_signaling(struct fence *f) struct vmw_fence_manager *fman = fman_from_fence(fence); struct vmw_private *dev_priv = fman->dev_priv; - u32 __iomem *fifo_mem = dev_priv->mmio_virt; - u32 seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); + u32 *fifo_mem = dev_priv->mmio_virt; + u32 seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); if (seqno - fence->base.seqno < VMW_FENCE_WRAP) return false; @@ -386,14 +386,14 @@ static bool vmw_fence_goal_new_locked(struct vmw_fence_manager *fman, u32 passed_seqno) { u32 goal_seqno; - u32 __iomem *fifo_mem; + u32 *fifo_mem; struct vmw_fence_obj *fence; if (likely(!fman->seqno_valid)) return false; fifo_mem = fman->dev_priv->mmio_virt; - goal_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE_GOAL); + goal_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE_GOAL); if (likely(passed_seqno - goal_seqno >= VMW_FENCE_WRAP)) return false; @@ -401,8 +401,8 @@ static bool vmw_fence_goal_new_locked(struct vmw_fence_manager *fman, list_for_each_entry(fence, &fman->fence_list, head) { if (!list_empty(&fence->seq_passed_actions)) { fman->seqno_valid = true; - iowrite32(fence->base.seqno, - fifo_mem + SVGA_FIFO_FENCE_GOAL); + vmw_mmio_write(fence->base.seqno, + fifo_mem + SVGA_FIFO_FENCE_GOAL); break; } } @@ -430,18 +430,18 @@ static bool vmw_fence_goal_check_locked(struct vmw_fence_obj *fence) { struct vmw_fence_manager *fman = fman_from_fence(fence); u32 goal_seqno; - u32 __iomem *fifo_mem; + u32 *fifo_mem; if (fence_is_signaled_locked(&fence->base)) return false; fifo_mem = fman->dev_priv->mmio_virt; - goal_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE_GOAL); + goal_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE_GOAL); if (likely(fman->seqno_valid && goal_seqno - fence->base.seqno < VMW_FENCE_WRAP)) return false; - iowrite32(fence->base.seqno, fifo_mem + SVGA_FIFO_FENCE_GOAL); + vmw_mmio_write(fence->base.seqno, fifo_mem + SVGA_FIFO_FENCE_GOAL); fman->seqno_valid = true; return true; @@ -453,9 +453,9 @@ static void __vmw_fences_update(struct vmw_fence_manager *fman) struct list_head action_list; bool needs_rerun; uint32_t seqno, new_seqno; - u32 __iomem *fifo_mem = fman->dev_priv->mmio_virt; + u32 *fifo_mem = fman->dev_priv->mmio_virt; - seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); + seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); rerun: list_for_each_entry_safe(fence, next_fence, &fman->fence_list, head) { if (seqno - fence->base.seqno < VMW_FENCE_WRAP) { @@ -477,7 +477,7 @@ rerun: needs_rerun = vmw_fence_goal_new_locked(fman, seqno); if (unlikely(needs_rerun)) { - new_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); + new_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); if (new_seqno != seqno) { seqno = new_seqno; goto rerun; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c index 80c40c31d4f8..a8baf5f5e765 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c @@ -36,7 +36,7 @@ struct vmw_temp_set_context { bool vmw_fifo_have_3d(struct vmw_private *dev_priv) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; + u32 *fifo_mem = dev_priv->mmio_virt; uint32_t fifo_min, hwversion; const struct vmw_fifo_state *fifo = &dev_priv->fifo; @@ -60,15 +60,15 @@ bool vmw_fifo_have_3d(struct vmw_private *dev_priv) if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) return false; - fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN); + fifo_min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int)) return false; - hwversion = ioread32(fifo_mem + - ((fifo->capabilities & - SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? - SVGA_FIFO_3D_HWVERSION_REVISED : - SVGA_FIFO_3D_HWVERSION)); + hwversion = vmw_mmio_read(fifo_mem + + ((fifo->capabilities & + SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? + SVGA_FIFO_3D_HWVERSION_REVISED : + SVGA_FIFO_3D_HWVERSION)); if (hwversion == 0) return false; @@ -85,13 +85,13 @@ bool vmw_fifo_have_3d(struct vmw_private *dev_priv) bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; + u32 *fifo_mem = dev_priv->mmio_virt; uint32_t caps; if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)) return false; - caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); + caps = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES); if (caps & SVGA_FIFO_CAP_PITCHLOCK) return true; @@ -100,7 +100,7 @@ bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv) int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; + u32 *fifo_mem = dev_priv->mmio_virt; uint32_t max; uint32_t min; @@ -137,19 +137,19 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) if (min < PAGE_SIZE) min = PAGE_SIZE; - iowrite32(min, fifo_mem + SVGA_FIFO_MIN); - iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); + vmw_mmio_write(min, fifo_mem + SVGA_FIFO_MIN); + vmw_mmio_write(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX); wmb(); - iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD); - iowrite32(min, fifo_mem + SVGA_FIFO_STOP); - iowrite32(0, fifo_mem + SVGA_FIFO_BUSY); + vmw_mmio_write(min, fifo_mem + SVGA_FIFO_NEXT_CMD); + vmw_mmio_write(min, fifo_mem + SVGA_FIFO_STOP); + vmw_mmio_write(0, fifo_mem + SVGA_FIFO_BUSY); mb(); vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); - max = ioread32(fifo_mem + SVGA_FIFO_MAX); - min = ioread32(fifo_mem + SVGA_FIFO_MIN); - fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES); + max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); + min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); + fifo->capabilities = vmw_mmio_read(fifo_mem + SVGA_FIFO_CAPABILITIES); DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n", (unsigned int) max, @@ -157,7 +157,7 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) (unsigned int) fifo->capabilities); atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); - iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); + vmw_mmio_write(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE); vmw_marker_queue_init(&fifo->marker_queue); return 0; @@ -165,31 +165,23 @@ int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; - static DEFINE_SPINLOCK(ping_lock); - unsigned long irq_flags; + u32 *fifo_mem = dev_priv->mmio_virt; - /* - * The ping_lock is needed because we don't have an atomic - * test-and-set of the SVGA_FIFO_BUSY register. - */ - spin_lock_irqsave(&ping_lock, irq_flags); - if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) { - iowrite32(1, fifo_mem + SVGA_FIFO_BUSY); + preempt_disable(); + if (cmpxchg(fifo_mem + SVGA_FIFO_BUSY, 0, 1) == 0) vmw_write(dev_priv, SVGA_REG_SYNC, reason); - } - spin_unlock_irqrestore(&ping_lock, irq_flags); + preempt_enable(); } void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; + u32 *fifo_mem = dev_priv->mmio_virt; vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0) ; - dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); + dev_priv->last_read_seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, dev_priv->config_done_state); @@ -213,11 +205,11 @@ void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo) static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; - uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); - uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); - uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); - uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); + u32 *fifo_mem = dev_priv->mmio_virt; + uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); + uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); + uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); + uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP); return ((max - next_cmd) + (stop - min) <= bytes); } @@ -260,7 +252,6 @@ static int vmw_fifo_wait(struct vmw_private *dev_priv, unsigned long timeout) { long ret = 1L; - unsigned long irq_flags; if (likely(!vmw_fifo_is_full(dev_priv, bytes))) return 0; @@ -270,16 +261,8 @@ static int vmw_fifo_wait(struct vmw_private *dev_priv, return vmw_fifo_wait_noirq(dev_priv, bytes, interruptible, timeout); - spin_lock(&dev_priv->waiter_lock); - if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) { - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - outl(SVGA_IRQFLAG_FIFO_PROGRESS, - dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); - dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS; - vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); - } - spin_unlock(&dev_priv->waiter_lock); + vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS, + &dev_priv->fifo_queue_waiters); if (interruptible) ret = wait_event_interruptible_timeout @@ -295,14 +278,8 @@ static int vmw_fifo_wait(struct vmw_private *dev_priv, else if (likely(ret > 0)) ret = 0; - spin_lock(&dev_priv->waiter_lock); - if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) { - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS; - vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); - } - spin_unlock(&dev_priv->waiter_lock); + vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FIFO_PROGRESS, + &dev_priv->fifo_queue_waiters); return ret; } @@ -321,7 +298,7 @@ static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes) { struct vmw_fifo_state *fifo_state = &dev_priv->fifo; - u32 __iomem *fifo_mem = dev_priv->mmio_virt; + u32 *fifo_mem = dev_priv->mmio_virt; uint32_t max; uint32_t min; uint32_t next_cmd; @@ -329,9 +306,9 @@ static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, int ret; mutex_lock(&fifo_state->fifo_mutex); - max = ioread32(fifo_mem + SVGA_FIFO_MAX); - min = ioread32(fifo_mem + SVGA_FIFO_MIN); - next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); + max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); + min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); + next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); if (unlikely(bytes >= (max - min))) goto out_err; @@ -342,7 +319,7 @@ static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, fifo_state->reserved_size = bytes; while (1) { - uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP); + uint32_t stop = vmw_mmio_read(fifo_mem + SVGA_FIFO_STOP); bool need_bounce = false; bool reserve_in_place = false; @@ -376,8 +353,8 @@ static void *vmw_local_fifo_reserve(struct vmw_private *dev_priv, fifo_state->using_bounce_buffer = false; if (reserveable) - iowrite32(bytes, fifo_mem + - SVGA_FIFO_RESERVED); + vmw_mmio_write(bytes, fifo_mem + + SVGA_FIFO_RESERVED); return (void __force *) (fifo_mem + (next_cmd >> 2)); } else { @@ -427,7 +404,7 @@ void *vmw_fifo_reserve_dx(struct vmw_private *dev_priv, uint32_t bytes, } static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, - u32 __iomem *fifo_mem, + u32 *fifo_mem, uint32_t next_cmd, uint32_t max, uint32_t min, uint32_t bytes) { @@ -439,17 +416,16 @@ static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state, if (bytes < chunk_size) chunk_size = bytes; - iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED); + vmw_mmio_write(bytes, fifo_mem + SVGA_FIFO_RESERVED); mb(); - memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size); + memcpy(fifo_mem + (next_cmd >> 2), buffer, chunk_size); rest = bytes - chunk_size; if (rest) - memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), - rest); + memcpy(fifo_mem + (min >> 2), buffer + (chunk_size >> 2), rest); } static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, - u32 __iomem *fifo_mem, + u32 *fifo_mem, uint32_t next_cmd, uint32_t max, uint32_t min, uint32_t bytes) { @@ -457,12 +433,12 @@ static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, fifo_state->dynamic_buffer : fifo_state->static_buffer; while (bytes > 0) { - iowrite32(*buffer++, fifo_mem + (next_cmd >> 2)); + vmw_mmio_write(*buffer++, fifo_mem + (next_cmd >> 2)); next_cmd += sizeof(uint32_t); if (unlikely(next_cmd == max)) next_cmd = min; mb(); - iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); + vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); mb(); bytes -= sizeof(uint32_t); } @@ -471,10 +447,10 @@ static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state, static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) { struct vmw_fifo_state *fifo_state = &dev_priv->fifo; - u32 __iomem *fifo_mem = dev_priv->mmio_virt; - uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD); - uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX); - uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN); + u32 *fifo_mem = dev_priv->mmio_virt; + uint32_t next_cmd = vmw_mmio_read(fifo_mem + SVGA_FIFO_NEXT_CMD); + uint32_t max = vmw_mmio_read(fifo_mem + SVGA_FIFO_MAX); + uint32_t min = vmw_mmio_read(fifo_mem + SVGA_FIFO_MIN); bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE; if (fifo_state->dx) @@ -507,11 +483,11 @@ static void vmw_local_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes) if (next_cmd >= max) next_cmd -= max - min; mb(); - iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); + vmw_mmio_write(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD); } if (reserveable) - iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED); + vmw_mmio_write(0, fifo_mem + SVGA_FIFO_RESERVED); mb(); up_write(&fifo_state->rwsem); vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c index 0a970afed93b..b8c6a03c8c54 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c @@ -64,7 +64,7 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data, break; case DRM_VMW_PARAM_FIFO_HW_VERSION: { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; + u32 *fifo_mem = dev_priv->mmio_virt; const struct vmw_fifo_state *fifo = &dev_priv->fifo; if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) { @@ -73,11 +73,11 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data, } param->value = - ioread32(fifo_mem + - ((fifo->capabilities & - SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? - SVGA_FIFO_3D_HWVERSION_REVISED : - SVGA_FIFO_3D_HWVERSION)); + vmw_mmio_read(fifo_mem + + ((fifo->capabilities & + SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ? + SVGA_FIFO_3D_HWVERSION_REVISED : + SVGA_FIFO_3D_HWVERSION)); break; } case DRM_VMW_PARAM_MAX_SURF_MEMORY: @@ -122,6 +122,22 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data, return 0; } +static u32 vmw_mask_multisample(unsigned int cap, u32 fmt_value) +{ + /* If the header is updated, update the format test as well! */ + BUILD_BUG_ON(SVGA3D_DEVCAP_DXFMT_BC5_UNORM + 1 != SVGA3D_DEVCAP_MAX); + + if (cap >= SVGA3D_DEVCAP_DXFMT_X8R8G8B8 && + cap <= SVGA3D_DEVCAP_DXFMT_BC5_UNORM) + fmt_value &= ~(SVGADX_DXFMT_MULTISAMPLE_2 | + SVGADX_DXFMT_MULTISAMPLE_4 | + SVGADX_DXFMT_MULTISAMPLE_8); + else if (cap == SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES) + return 0; + + return fmt_value; +} + static int vmw_fill_compat_cap(struct vmw_private *dev_priv, void *bounce, size_t size) { @@ -147,7 +163,8 @@ static int vmw_fill_compat_cap(struct vmw_private *dev_priv, void *bounce, for (i = 0; i < max_size; ++i) { vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); compat_cap->pairs[i][0] = i; - compat_cap->pairs[i][1] = vmw_read(dev_priv, SVGA_REG_DEV_CAP); + compat_cap->pairs[i][1] = vmw_mask_multisample + (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); } spin_unlock(&dev_priv->cap_lock); @@ -162,7 +179,7 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data, (struct drm_vmw_get_3d_cap_arg *) data; struct vmw_private *dev_priv = vmw_priv(dev); uint32_t size; - u32 __iomem *fifo_mem; + u32 *fifo_mem; void __user *buffer = (void __user *)((unsigned long)(arg->buffer)); void *bounce; int ret; @@ -202,7 +219,8 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data, spin_lock(&dev_priv->cap_lock); for (i = 0; i < num; ++i) { vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); - *bounce32++ = vmw_read(dev_priv, SVGA_REG_DEV_CAP); + *bounce32++ = vmw_mask_multisample + (i, vmw_read(dev_priv, SVGA_REG_DEV_CAP)); } spin_unlock(&dev_priv->cap_lock); } else if (gb_objects) { @@ -211,7 +229,7 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data, goto out_err; } else { fifo_mem = dev_priv->mmio_virt; - memcpy_fromio(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size); + memcpy(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size); } ret = copy_to_user(buffer, bounce, size); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c index 9498a5e33c12..0c7e1723292c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_irq.c @@ -36,15 +36,13 @@ irqreturn_t vmw_irq_handler(int irq, void *arg) struct vmw_private *dev_priv = vmw_priv(dev); uint32_t status, masked_status; - spin_lock(&dev_priv->irq_lock); status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); - masked_status = status & dev_priv->irq_mask; - spin_unlock(&dev_priv->irq_lock); + masked_status = status & READ_ONCE(dev_priv->irq_mask); if (likely(status)) outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); - if (!masked_status) + if (!status) return IRQ_NONE; if (masked_status & (SVGA_IRQFLAG_ANY_FENCE | @@ -72,8 +70,8 @@ static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) void vmw_update_seqno(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo_state) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; - uint32_t seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE); + u32 *fifo_mem = dev_priv->mmio_virt; + uint32_t seqno = vmw_mmio_read(fifo_mem + SVGA_FIFO_FENCE); if (dev_priv->last_read_seqno != seqno) { dev_priv->last_read_seqno = seqno; @@ -178,8 +176,9 @@ int vmw_fallback_wait(struct vmw_private *dev_priv, } finish_wait(&dev_priv->fence_queue, &__wait); if (ret == 0 && fifo_idle) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; - iowrite32(signal_seq, fifo_mem + SVGA_FIFO_FENCE); + u32 *fifo_mem = dev_priv->mmio_virt; + + vmw_mmio_write(signal_seq, fifo_mem + SVGA_FIFO_FENCE); } wake_up_all(&dev_priv->fence_queue); out_err: @@ -189,65 +188,51 @@ out_err: return ret; } -void vmw_seqno_waiter_add(struct vmw_private *dev_priv) +void vmw_generic_waiter_add(struct vmw_private *dev_priv, + u32 flag, int *waiter_count) { - spin_lock(&dev_priv->waiter_lock); - if (dev_priv->fence_queue_waiters++ == 0) { - unsigned long irq_flags; - - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - outl(SVGA_IRQFLAG_ANY_FENCE, - dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); - dev_priv->irq_mask |= SVGA_IRQFLAG_ANY_FENCE; + spin_lock_bh(&dev_priv->waiter_lock); + if ((*waiter_count)++ == 0) { + outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); + dev_priv->irq_mask |= flag; vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); } - spin_unlock(&dev_priv->waiter_lock); + spin_unlock_bh(&dev_priv->waiter_lock); } -void vmw_seqno_waiter_remove(struct vmw_private *dev_priv) +void vmw_generic_waiter_remove(struct vmw_private *dev_priv, + u32 flag, int *waiter_count) { - spin_lock(&dev_priv->waiter_lock); - if (--dev_priv->fence_queue_waiters == 0) { - unsigned long irq_flags; - - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - dev_priv->irq_mask &= ~SVGA_IRQFLAG_ANY_FENCE; + spin_lock_bh(&dev_priv->waiter_lock); + if (--(*waiter_count) == 0) { + dev_priv->irq_mask &= ~flag; vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); } - spin_unlock(&dev_priv->waiter_lock); + spin_unlock_bh(&dev_priv->waiter_lock); } +void vmw_seqno_waiter_add(struct vmw_private *dev_priv) +{ + vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE, + &dev_priv->fence_queue_waiters); +} + +void vmw_seqno_waiter_remove(struct vmw_private *dev_priv) +{ + vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE, + &dev_priv->fence_queue_waiters); +} void vmw_goal_waiter_add(struct vmw_private *dev_priv) { - spin_lock(&dev_priv->waiter_lock); - if (dev_priv->goal_queue_waiters++ == 0) { - unsigned long irq_flags; - - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - outl(SVGA_IRQFLAG_FENCE_GOAL, - dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); - dev_priv->irq_mask |= SVGA_IRQFLAG_FENCE_GOAL; - vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); - } - spin_unlock(&dev_priv->waiter_lock); + vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, + &dev_priv->goal_queue_waiters); } void vmw_goal_waiter_remove(struct vmw_private *dev_priv) { - spin_lock(&dev_priv->waiter_lock); - if (--dev_priv->goal_queue_waiters == 0) { - unsigned long irq_flags; - - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - dev_priv->irq_mask &= ~SVGA_IRQFLAG_FENCE_GOAL; - vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); - } - spin_unlock(&dev_priv->waiter_lock); + vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, + &dev_priv->goal_queue_waiters); } int vmw_wait_seqno(struct vmw_private *dev_priv, @@ -304,7 +289,6 @@ void vmw_irq_preinstall(struct drm_device *dev) if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) return; - spin_lock_init(&dev_priv->irq_lock); status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); } @@ -327,30 +311,3 @@ void vmw_irq_uninstall(struct drm_device *dev) status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); } - -void vmw_generic_waiter_add(struct vmw_private *dev_priv, - u32 flag, int *waiter_count) -{ - unsigned long irq_flags; - - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - if ((*waiter_count)++ == 0) { - outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT); - dev_priv->irq_mask |= flag; - vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - } - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); -} - -void vmw_generic_waiter_remove(struct vmw_private *dev_priv, - u32 flag, int *waiter_count) -{ - unsigned long irq_flags; - - spin_lock_irqsave(&dev_priv->irq_lock, irq_flags); - if (--(*waiter_count) == 0) { - dev_priv->irq_mask &= ~flag; - vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); - } - spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags); -} diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c index 15a6c01cd016..9fcd7f82995c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c @@ -78,7 +78,7 @@ int vmw_cursor_update_image(struct vmw_private *dev_priv, cmd->cursor.hotspotX = hotspotX; cmd->cursor.hotspotY = hotspotY; - vmw_fifo_commit(dev_priv, cmd_size); + vmw_fifo_commit_flush(dev_priv, cmd_size); return 0; } @@ -123,14 +123,14 @@ err_unreserve: void vmw_cursor_update_position(struct vmw_private *dev_priv, bool show, int x, int y) { - u32 __iomem *fifo_mem = dev_priv->mmio_virt; + u32 *fifo_mem = dev_priv->mmio_virt; uint32_t count; - iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON); - iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X); - iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y); - count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT); - iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT); + vmw_mmio_write(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON); + vmw_mmio_write(x, fifo_mem + SVGA_FIFO_CURSOR_X); + vmw_mmio_write(y, fifo_mem + SVGA_FIFO_CURSOR_Y); + count = vmw_mmio_read(fifo_mem + SVGA_FIFO_CURSOR_COUNT); + vmw_mmio_write(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT); } int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, @@ -1155,7 +1155,8 @@ int vmw_kms_write_svga(struct vmw_private *vmw_priv, if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK) vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch); else if (vmw_fifo_have_pitchlock(vmw_priv)) - iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK); + vmw_mmio_write(pitch, vmw_priv->mmio_virt + + SVGA_FIFO_PITCHLOCK); vmw_write(vmw_priv, SVGA_REG_WIDTH, width); vmw_write(vmw_priv, SVGA_REG_HEIGHT, height); vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp); @@ -1181,8 +1182,8 @@ int vmw_kms_save_vga(struct vmw_private *vmw_priv) vmw_priv->vga_pitchlock = vmw_read(vmw_priv, SVGA_REG_PITCHLOCK); else if (vmw_fifo_have_pitchlock(vmw_priv)) - vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt + - SVGA_FIFO_PITCHLOCK); + vmw_priv->vga_pitchlock = vmw_mmio_read(vmw_priv->mmio_virt + + SVGA_FIFO_PITCHLOCK); if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)) return 0; @@ -1230,8 +1231,8 @@ int vmw_kms_restore_vga(struct vmw_private *vmw_priv) vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, vmw_priv->vga_pitchlock); else if (vmw_fifo_have_pitchlock(vmw_priv)) - iowrite32(vmw_priv->vga_pitchlock, - vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK); + vmw_mmio_write(vmw_priv->vga_pitchlock, + vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK); if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)) return 0; @@ -1263,7 +1264,7 @@ bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv, /** * Function called by DRM code called with vbl_lock held. */ -u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc) +u32 vmw_get_vblank_counter(struct drm_device *dev, unsigned int pipe) { return 0; } @@ -1271,7 +1272,7 @@ u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc) /** * Function called by DRM code called with vbl_lock held. */ -int vmw_enable_vblank(struct drm_device *dev, int crtc) +int vmw_enable_vblank(struct drm_device *dev, unsigned int pipe) { return -ENOSYS; } @@ -1279,7 +1280,7 @@ int vmw_enable_vblank(struct drm_device *dev, int crtc) /** * Function called by DRM code called with vbl_lock held. */ -void vmw_disable_vblank(struct drm_device *dev, int crtc) +void vmw_disable_vblank(struct drm_device *dev, unsigned int pipe) { } diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c index c22e2df1b336..b1fc1c02792d 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c @@ -717,6 +717,8 @@ static int vmw_stdu_crtc_page_flip(struct drm_crtc *crtc, &event->event.tv_usec, true); vmw_fence_obj_unreference(&fence); + } else { + vmw_fifo_flush(dev_priv, false); } return ret; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c index 64b50409fa07..a279863784c8 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_surface.c @@ -1290,6 +1290,8 @@ int vmw_gb_surface_define_ioctl(struct drm_device *dev, void *data, uint32_t size; uint32_t backup_handle; + if (req->multisample_count != 0) + return -EINVAL; if (unlikely(vmw_user_surface_size == 0)) vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) + |