diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/dt-bindings/clock/aspeed-clock.h | 2 | ||||
-rw-r--r-- | include/dt-bindings/clock/ast2600-clock.h | 13 | ||||
-rw-r--r-- | include/linux/aspeed-mctp.h | 149 | ||||
-rw-r--r-- | include/linux/i2c-mux.h | 5 | ||||
-rw-r--r-- | include/linux/i2c.h | 27 | ||||
-rw-r--r-- | include/linux/i3c/ccc.h | 12 | ||||
-rw-r--r-- | include/linux/i3c/device.h | 14 | ||||
-rw-r--r-- | include/linux/i3c/master.h | 24 | ||||
-rw-r--r-- | include/linux/i3c/target.h | 23 | ||||
-rw-r--r-- | include/linux/jtag.h | 47 | ||||
-rw-r--r-- | include/linux/mfd/intel-peci-client.h | 163 | ||||
-rw-r--r-- | include/linux/peci.h | 151 | ||||
-rw-r--r-- | include/uapi/linux/aspeed-espi-ioc.h | 198 | ||||
-rw-r--r-- | include/uapi/linux/aspeed-lpc-mbox.h | 11 | ||||
-rw-r--r-- | include/uapi/linux/aspeed-lpc-sio.h | 46 | ||||
-rw-r--r-- | include/uapi/linux/aspeed-mctp.h | 128 | ||||
-rw-r--r-- | include/uapi/linux/i2c.h | 1 | ||||
-rw-r--r-- | include/uapi/linux/i3c/i3cdev.h | 38 | ||||
-rw-r--r-- | include/uapi/linux/jtag.h | 369 | ||||
-rw-r--r-- | include/uapi/linux/jtag_drv.h | 73 | ||||
-rw-r--r-- | include/uapi/linux/peci-ioctl.h | 703 |
21 files changed, 2197 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 9ff4f6e4558c..41d531dd0b48 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -41,6 +41,8 @@ #define ASPEED_CLK_24M 35 #define ASPEED_CLK_MAC1RCLK 36 #define ASPEED_CLK_MAC2RCLK 37 +#define ASPEED_CLK_UART_HS 38 +#define ASPEED_CLK_MAX 39 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 62b9520a00fd..165bec96ebe7 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -87,15 +87,28 @@ #define ASPEED_CLK_MAC2RCLK 68 #define ASPEED_CLK_MAC3RCLK 69 #define ASPEED_CLK_MAC4RCLK 70 +#define ASPEED_CLK_UART5 71 +#define ASPEED_CLK_I3C 72 +#define ASPEED_CLK_MAX 73 /* Only list resets here that are not part of a gate */ +#define ASPEED_RESET_ESPI 57 #define ASPEED_RESET_ADC 55 #define ASPEED_RESET_JTAG_MASTER2 54 +#define ASPEED_RESET_I3C7 47 +#define ASPEED_RESET_I3C6 46 +#define ASPEED_RESET_I3C5 45 +#define ASPEED_RESET_I3C4 44 +#define ASPEED_RESET_I3C3 43 +#define ASPEED_RESET_I3C2 42 +#define ASPEED_RESET_I3C1 41 +#define ASPEED_RESET_I3C0 40 #define ASPEED_RESET_I3C_DMA 39 #define ASPEED_RESET_PWM 37 #define ASPEED_RESET_PECI 36 #define ASPEED_RESET_MII 35 #define ASPEED_RESET_I2C 34 +#define ASPEED_RESET_LPC 32 #define ASPEED_RESET_H2X 31 #define ASPEED_RESET_GP_MCU 30 #define ASPEED_RESET_DP_MCU 29 diff --git a/include/linux/aspeed-mctp.h b/include/linux/aspeed-mctp.h new file mode 100644 index 000000000000..d286060a79ee --- /dev/null +++ b/include/linux/aspeed-mctp.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2020 Intel Corporation */ + +#ifndef __LINUX_ASPEED_MCTP_H +#define __LINUX_ASPEED_MCTP_H + +#include <linux/types.h> + +struct mctp_client; +struct aspeed_mctp; + +struct pcie_transport_hdr { + u8 fmt_type; + u8 mbz; + u8 mbz_attr_len_hi; + u8 len_lo; + u16 requester; + u8 tag; + u8 code; + u16 target; + u16 vendor; +} __packed; + +struct mctp_protocol_hdr { + u8 ver; + u8 dest; + u8 src; + u8 flags_seq_tag; +} __packed; + +#define PCIE_VDM_HDR_SIZE 16 +#define MCTP_BTU_SIZE 64 +#define PCIE_VDM_DATA_SIZE_DW (MCTP_BTU_SIZE / 4) +#define PCIE_VDM_HDR_SIZE_DW (PCIE_VDM_HDR_SIZE / 4) + +#define PCIE_MCTP_MIN_PACKET_SIZE (PCIE_VDM_HDR_SIZE + 4) + +struct mctp_pcie_packet_data { + u32 hdr[PCIE_VDM_HDR_SIZE_DW]; + u32 payload[PCIE_VDM_DATA_SIZE_DW]; +}; + +struct mctp_pcie_packet { + struct mctp_pcie_packet_data data; + u32 size; +}; + +/** + * aspeed_mctp_add_type_handler() - register for the given MCTP message type + * @client: pointer to the existing mctp_client context + * @mctp_type: message type code according to DMTF DSP0239 spec. + * @pci_vendor_id: vendor ID (non-zero if msg_type is Vendor Defined PCI, + * otherwise it should be set to 0) + * @vdm_type: vendor defined message type (it should be set to 0 for non-Vendor + * Defined PCI message type) + * @vdm_mask: vendor defined message mask (it should be set to 0 for non-Vendor + * Defined PCI message type) + * + * Return: + * * 0 - success, + * * -EINVAL - arguments passed are incorrect, + * * -ENOMEM - cannot alloc a new handler, + * * -EBUSY - given message has already registered handler. + */ + +int aspeed_mctp_add_type_handler(struct mctp_client *client, u8 mctp_type, + u16 pci_vendor_id, u16 vdm_type, u16 vdm_mask); + +/** + * aspeed_mctp_create_client() - create mctp_client context + * @priv pointer to aspeed-mctp context + * + * Returns struct mctp_client or NULL. + */ +struct mctp_client *aspeed_mctp_create_client(struct aspeed_mctp *priv); + +/** + * aspeed_mctp_delete_client()- delete mctp_client context + * @client: pointer to existing mctp_client context + */ +void aspeed_mctp_delete_client(struct mctp_client *client); + +/** + * aspeed_mctp_send_packet() - send mctp_packet + * @client: pointer to existing mctp_client context + * @tx_packet: the allocated packet that needs to be send via aspeed-mctp + * + * After the function returns success, the packet is no longer owned by the + * caller, and as such, the caller should not attempt to free it. + * + * Return: + * * 0 - success, + * * -ENOSPC - failed to send packet due to lack of available space. + */ +int aspeed_mctp_send_packet(struct mctp_client *client, + struct mctp_pcie_packet *tx_packet); + +/** + * aspeed_mctp_receive_packet() - receive mctp_packet + * @client: pointer to existing mctp_client context + * @timeout: timeout, in jiffies + * + * The function will sleep for up to @timeout if no packet is ready to read. + * + * After the function returns valid packet, the caller takes its ownership and + * is responsible for freeing it. + * + * Returns struct mctp_pcie_packet from or ERR_PTR in case of error or the + * @timeout elapsed. + */ +struct mctp_pcie_packet *aspeed_mctp_receive_packet(struct mctp_client *client, + unsigned long timeout); + +/** + * aspeed_mctp_flush_rx_queue() - remove all mctp_packets from rx queue + * @client: pointer to existing mctp_client context + */ +void aspeed_mctp_flush_rx_queue(struct mctp_client *client); + +/** + * aspeed_mctp_get_eid_bdf() - return PCIe address for requested endpoint ID + * @client: pointer to existing mctp_client context + * @eid: requested eid + * @bdf: pointer to store BDF value + * + * Return: + * * 0 - success, + * * -ENOENT - there is no record for requested endpoint id. + */ +int aspeed_mctp_get_eid_bdf(struct mctp_client *client, u8 eid, u16 *bdf); + +/** + * aspeed_mctp_get_eid() - return EID for requested BDF and domainId. + * @client: pointer to existing mctp_client context + * @bdf: requested BDF value + * @domain_id: requested domainId + * @eid: pointer to store EID value + * + * Return: + * * 0 - success, + * * -ENOENT - there is no record for requested bdf/domainId. + */ +int aspeed_mctp_get_eid(struct mctp_client *client, u16 bdf, + u8 domain_id, u8 *eid); + +void *aspeed_mctp_packet_alloc(gfp_t flags); +void aspeed_mctp_packet_free(void *packet); + +#endif /* __LINUX_ASPEED_MCTP_H */ diff --git a/include/linux/i2c-mux.h b/include/linux/i2c-mux.h index 98ef73b7c8fd..3d2586062ccc 100644 --- a/include/linux/i2c-mux.h +++ b/include/linux/i2c-mux.h @@ -14,6 +14,7 @@ #ifdef __KERNEL__ #include <linux/bitops.h> +#include <linux/workqueue.h> struct i2c_mux_core { struct i2c_adapter *parent; @@ -27,6 +28,10 @@ struct i2c_mux_core { int (*select)(struct i2c_mux_core *, u32 chan_id); int (*deselect)(struct i2c_mux_core *, u32 chan_id); + struct mutex hold_lock; /* mutex for channel holding */ + u32 holder_chan_id; + struct delayed_work unhold_work; + int num_adapters; int max_adapters; struct i2c_adapter *adapter[]; diff --git a/include/linux/i2c.h b/include/linux/i2c.h index 2ce3efbe9198..fa0af97af147 100644 --- a/include/linux/i2c.h +++ b/include/linux/i2c.h @@ -20,6 +20,7 @@ #include <linux/irqdomain.h> /* for Host Notify IRQ */ #include <linux/of.h> /* for struct device_node */ #include <linux/swab.h> /* for swab16 */ +#include <linux/workqueue.h> #include <uapi/linux/i2c.h> extern struct bus_type i2c_bus_type; @@ -373,6 +374,7 @@ enum i2c_slave_event { I2C_SLAVE_WRITE_REQUESTED, I2C_SLAVE_READ_PROCESSED, I2C_SLAVE_WRITE_RECEIVED, + I2C_SLAVE_GCALL_REQUESTED, I2C_SLAVE_STOP, }; @@ -738,6 +740,13 @@ struct i2c_adapter { struct irq_domain *host_notify_domain; struct regulator *bus_regulator; + + /* + * These will be used by root adpaters only. For muxes, each mux core + * has these individually. + */ + struct mutex hold_lock; /* mutex for bus holding */ + struct delayed_work unhold_work; }; #define to_i2c_adapter(d) container_of(d, struct i2c_adapter, dev) @@ -1040,4 +1049,22 @@ static inline struct i2c_adapter *i2c_acpi_find_adapter_by_handle(acpi_handle ha } #endif /* CONFIG_ACPI */ +enum i2c_hold_msg_type { + I2C_HOLD_MSG_NONE, + I2C_HOLD_MSG_SET, + I2C_HOLD_MSG_RESET +}; + +static inline enum i2c_hold_msg_type i2c_check_hold_msg(u16 flags, u16 len, u16 *buf) +{ + if (flags & I2C_M_HOLD && len == sizeof(u16)) { + if (*buf) + return I2C_HOLD_MSG_SET; + + return I2C_HOLD_MSG_RESET; + } + + return I2C_HOLD_MSG_NONE; +} + #endif /* _LINUX_I2C_H */ diff --git a/include/linux/i3c/ccc.h b/include/linux/i3c/ccc.h index 73b0982cc519..a7a19ebe6b6d 100644 --- a/include/linux/i3c/ccc.h +++ b/include/linux/i3c/ccc.h @@ -32,6 +32,9 @@ #define I3C_CCC_DEFSLVS I3C_CCC_ID(0x8, true) #define I3C_CCC_ENTTM I3C_CCC_ID(0xb, true) #define I3C_CCC_ENTHDR(x) I3C_CCC_ID(0x20 + (x), true) +#define I3C_CCC_SETAASA I3C_CCC_ID(0x29, true) +#define I3C_CCC_SETHID I3C_CCC_ID(0x61, true) +#define I3C_CCC_DEVCTRL I3C_CCC_ID(0x62, true) /* Unicast-only commands */ #define I3C_CCC_SETDASA I3C_CCC_ID(0x7, false) @@ -243,6 +246,15 @@ struct i3c_ccc_setbrgtgt { struct i3c_ccc_bridged_slave_desc bslaves[0]; } __packed; + +/** + * struct i3c_ccc_sethid - payload passed to SETHID CCC + * + * @hid: 3-bit HID + */ +struct i3c_ccc_sethid { + u8 hid; +}; /** * enum i3c_sdr_max_data_rate - max data rate values for private SDR transfers */ diff --git a/include/linux/i3c/device.h b/include/linux/i3c/device.h index 8242e13e7b0b..e036a30f8c7e 100644 --- a/include/linux/i3c/device.h +++ b/include/linux/i3c/device.h @@ -71,9 +71,11 @@ struct i3c_priv_xfer { /** * enum i3c_dcr - I3C DCR values * @I3C_DCR_GENERIC_DEVICE: generic I3C device + * @I3C_DCR_HUB: I3C HUB device */ enum i3c_dcr { I3C_DCR_GENERIC_DEVICE = 0, + I3C_DCR_HUB = 0xC2, }; #define I3C_PID_MANUF_ID(pid) (((pid) & GENMASK_ULL(47, 33)) >> 33) @@ -128,6 +130,7 @@ struct i3c_device_info { u32 max_read_turnaround; u16 max_read_len; u16 max_write_len; + __be16 status; }; /* @@ -178,6 +181,7 @@ struct i3c_driver { int (*probe)(struct i3c_device *dev); void (*remove)(struct i3c_device *dev); const struct i3c_device_id *id_table; + bool target; }; static inline struct i3c_driver *drv_to_i3cdrv(struct device_driver *drv) @@ -293,6 +297,8 @@ int i3c_device_do_priv_xfers(struct i3c_device *dev, struct i3c_priv_xfer *xfers, int nxfers); +int i3c_device_generate_ibi(struct i3c_device *dev, const u8 *data, int len); + void i3c_device_get_info(struct i3c_device *dev, struct i3c_device_info *info); struct i3c_ibi_payload { @@ -332,4 +338,12 @@ void i3c_device_free_ibi(struct i3c_device *dev); int i3c_device_enable_ibi(struct i3c_device *dev); int i3c_device_disable_ibi(struct i3c_device *dev); +int i3c_device_getstatus_ccc(struct i3c_device *dev, struct i3c_device_info *info); + +struct i3c_target_read_setup { + void (*handler)(struct i3c_device *dev, const u8 *data, size_t len); +}; + +int i3c_target_read_register(struct i3c_device *dev, const struct i3c_target_read_setup *setup); + #endif /* I3C_DEV_H */ diff --git a/include/linux/i3c/master.h b/include/linux/i3c/master.h index 9cb39d901cd5..5d35a6d1c992 100644 --- a/include/linux/i3c/master.h +++ b/include/linux/i3c/master.h @@ -22,6 +22,7 @@ #define I3C_BROADCAST_ADDR 0x7e #define I3C_MAX_ADDR GENMASK(6, 0) +struct i3c_target_ops; struct i3c_master_controller; struct i3c_bus; struct i2c_device; @@ -185,10 +186,20 @@ struct i3c_dev_boardinfo { }; /** + * struct i3c_target_info - target information attached to a specific device + * @read handler: handler specified at i3c_target_read_register() call time. + */ + +struct i3c_target_info { + void (*read_handler)(struct i3c_device *dev, const u8 *data, size_t len); +}; + +/** * struct i3c_dev_desc - I3C device descriptor * @common: common part of the I3C device descriptor * @info: I3C device information. Will be automatically filled when you create * your device with i3c_master_add_i3c_dev_locked() + * @target_info: I3C target information. * @ibi_lock: lock used to protect the &struct_i3c_device->ibi * @ibi: IBI info attached to a device. Should be NULL until * i3c_device_request_ibi() is called @@ -207,6 +218,7 @@ struct i3c_dev_boardinfo { struct i3c_dev_desc { struct i3c_i2c_dev_desc common; struct i3c_device_info info; + struct i3c_target_info target_info; struct mutex ibi_lock; struct i3c_device_ibi_info *ibi; struct i3c_device *dev; @@ -463,6 +475,8 @@ struct i3c_master_controller_ops { * registered to the I2C subsystem to be as transparent as possible to * existing I2C drivers * @ops: master operations. See &struct i3c_master_controller_ops + * @target_ops: target operations. See &struct i3c_target_ops + * @target: true if the underlying I3C device acts as a target on I3C bus * @secondary: true if the master is a secondary master * @init_done: true when the bus initialization is done * @boardinfo.i3c: list of I3C boardinfo objects @@ -485,8 +499,11 @@ struct i3c_master_controller { struct i3c_dev_desc *this; struct i2c_adapter i2c; const struct i3c_master_controller_ops *ops; + const struct i3c_target_ops *target_ops; + unsigned int target : 1; unsigned int secondary : 1; unsigned int init_done : 1; + unsigned int jdec_spd : 1; struct { struct list_head i3c; struct list_head i2c; @@ -544,6 +561,13 @@ int i3c_master_register(struct i3c_master_controller *master, bool secondary); int i3c_master_unregister(struct i3c_master_controller *master); +int i3c_register(struct i3c_master_controller *master, + struct device *parent, + const struct i3c_master_controller_ops *master_ops, + const struct i3c_target_ops *target_ops, + bool secondary); +int i3c_unregister(struct i3c_master_controller *master); + /** * i3c_dev_get_master_data() - get master private data attached to an I3C * device descriptor diff --git a/include/linux/i3c/target.h b/include/linux/i3c/target.h new file mode 100644 index 000000000000..9e71124b5325 --- /dev/null +++ b/include/linux/i3c/target.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2022, Intel Corporation */ + +#ifndef I3C_TARGET_H +#define I3C_TARGET_H + +#include <linux/device.h> +#include <linux/i3c/device.h> + +struct i3c_master_controller; + +struct i3c_target_ops { + int (*bus_init)(struct i3c_master_controller *master); + void (*bus_cleanup)(struct i3c_master_controller *master); + int (*priv_xfers)(struct i3c_dev_desc *dev, struct i3c_priv_xfer *xfers, int nxfers); + int (*generate_ibi)(struct i3c_dev_desc *dev, const u8 *data, int len); +}; + +int i3c_target_register(struct i3c_master_controller *master, struct device *parent, + const struct i3c_target_ops *ops); +int i3c_target_unregister(struct i3c_master_controller *master); + +#endif diff --git a/include/linux/jtag.h b/include/linux/jtag.h new file mode 100644 index 000000000000..fab12dc4fc5e --- /dev/null +++ b/include/linux/jtag.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Mellanox Technologies. All rights reserved. */ +/* Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com> */ +/* Copyright (c) 2019 Intel Corporation */ + +#ifndef __LINUX_JTAG_H +#define __LINUX_JTAG_H + +#include <linux/types.h> +#include <uapi/linux/jtag.h> + +#define JTAG_MAX_XFER_DATA_LEN 65535 + +struct jtag; +/** + * struct jtag_ops - callbacks for JTAG control functions: + * + * @freq_get: get frequency function. Filled by dev driver + * @freq_set: set frequency function. Filled by dev driver + * @status_get: get JTAG TAPC state function. Mandatory, Filled by dev driver + * @status_set: set JTAG TAPC state function. Mandatory, Filled by dev driver + * @xfer: send JTAG xfer function. Mandatory func. Filled by dev driver + * @mode_set: set specific work mode for JTAG. Filled by dev driver + * @bitbang: set low level bitbang operations. Filled by dev driver + * @enable: enables JTAG interface in master mode. Filled by dev driver + * @disable: disables JTAG interface master mode. Filled by dev driver + */ +struct jtag_ops { + int (*freq_get)(struct jtag *jtag, u32 *freq); + int (*freq_set)(struct jtag *jtag, u32 freq); + int (*status_get)(struct jtag *jtag, u32 *state); + int (*status_set)(struct jtag *jtag, struct jtag_tap_state *endst); + int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data); + int (*mode_set)(struct jtag *jtag, struct jtag_mode *jtag_mode); + int (*bitbang)(struct jtag *jtag, struct bitbang_packet *bitbang, + struct tck_bitbang *bitbang_data); + int (*enable)(struct jtag *jtag); + int (*disable)(struct jtag *jtag); +}; + +void *jtag_priv(struct jtag *jtag); +int devm_jtag_register(struct device *dev, struct jtag *jtag); +struct jtag *jtag_alloc(struct device *host, size_t priv_size, + const struct jtag_ops *ops); +void jtag_free(struct jtag *jtag); + +#endif /* __LINUX_JTAG_H */ diff --git a/include/linux/mfd/intel-peci-client.h b/include/linux/mfd/intel-peci-client.h new file mode 100644 index 000000000000..84b5882bcf31 --- /dev/null +++ b/include/linux/mfd/intel-peci-client.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2020 Intel Corporation */ + +#ifndef __LINUX_MFD_INTEL_PECI_CLIENT_H +#define __LINUX_MFD_INTEL_PECI_CLIENT_H + +#include <linux/peci.h> + +#if IS_ENABLED(CONFIG_X86) +#include <asm/intel-family.h> +#else +/* + * Architectures other than x86 cannot include the header file so define these + * at here. These are needed for detecting type of client x86 CPUs behind a PECI + * connection. + */ +#define INTEL_FAM6_HASWELL_X 0x3F +#define INTEL_FAM6_BROADWELL_X 0x4F +#define INTEL_FAM6_SKYLAKE_X 0x55 +#define INTEL_FAM6_SKYLAKE_XD 0x56 +#define INTEL_FAM6_ICELAKE_X 0x6A +#define INTEL_FAM6_ICELAKE_XD 0x6C +#endif + +#define INTEL_FAM6 6 /* P6 (Pentium Pro and later) */ + +#define CORE_MASK_BITS_ON_HSX 18 +#define CHAN_RANK_MAX_ON_HSX 8 /* Max number of channel ranks on Haswell */ +#define DIMM_IDX_MAX_ON_HSX 3 /* Max DIMM index per channel on Haswell */ + +#define CORE_MASK_BITS_ON_BDX 24 +#define CHAN_RANK_MAX_ON_BDX 4 /* Max number of channel ranks on Broadwell */ +#define DIMM_IDX_MAX_ON_BDX 3 /* Max DIMM index per channel on Broadwell */ + +#define CORE_MASK_BITS_ON_SKX 28 +#define CHAN_RANK_MAX_ON_SKX 6 /* Max number of channel ranks on Skylake */ +#define DIMM_IDX_MAX_ON_SKX 2 /* Max DIMM index per channel on Skylake */ + +#define CORE_MASK_BITS_ON_SKXD 28 +#define CHAN_RANK_MAX_ON_SKXD 2 /* Max number of channel ranks on Skylake D */ +#define DIMM_IDX_MAX_ON_SKXD 2 /* Max DIMM index per channel on Skylake D */ + +#define CORE_MASK_BITS_ON_ICX 64 +#define CHAN_RANK_MAX_ON_ICX 8 /* Max number of channel ranks on Icelake */ +#define DIMM_IDX_MAX_ON_ICX 2 /* Max DIMM index per channel on Icelake */ + +#define CORE_MASK_BITS_ON_ICXD 64 +#define CHAN_RANK_MAX_ON_ICXD 4 /* Max number of channel ranks on Icelake D */ +#define DIMM_IDX_MAX_ON_ICXD 2 /* Max DIMM index per channel on Icelake D */ + +#define CORE_MASK_BITS_MAX CORE_MASK_BITS_ON_ICX +#define CHAN_RANK_MAX CHAN_RANK_MAX_ON_HSX +#define DIMM_IDX_MAX DIMM_IDX_MAX_ON_HSX +#define DIMM_NUMS_MAX (CHAN_RANK_MAX * DIMM_IDX_MAX) + +/** + * struct cpu_gen_info - CPU generation specific information + * @family: CPU family ID + * @model: CPU model + * @core_mask_bits: number of resolved core bits + * @chan_rank_max: max number of channel ranks + * @dimm_idx_max: max number of DIMM indices + * + * CPU generation specific information to identify maximum number of cores and + * DIMM slots. + */ +struct cpu_gen_info { + u16 family; + u8 model; + uint core_mask_bits; + uint chan_rank_max; + uint dimm_idx_max; +}; + +/** + * struct peci_client_manager - PECI client manager information + * @client; pointer to the PECI client + * @name: PECI client manager name + * @gen_info: CPU generation info of the detected CPU + * + * PECI client manager information for managing PECI sideband functions on a CPU + * client. + */ +struct peci_client_manager { + struct peci_client *client; + char name[PECI_NAME_SIZE]; + const struct cpu_gen_info *gen_info; +}; + +/** + * peci_client_read_package_config - read from the Package Configuration Space + * @priv: driver private data structure + * @index: encoding index for the requested service + * @param: parameter to specify the exact data being requested + * @data: data buffer to store the result + * Context: can sleep + * + * A generic PECI command that provides read access to the + * "Package Configuration Space" that is maintained by the PCU, including + * various power and thermal management functions. Typical PCS read services + * supported by the processor may include access to temperature data, energy + * status, run time information, DIMM temperatures and so on. + * + * Return: zero on success, else a negative error code. + */ +static inline int +peci_client_read_package_config(struct peci_client_manager *priv, + u8 index, u16 param, u8 *data) +{ + struct peci_rd_pkg_cfg_msg msg; + int ret; + + msg.addr = priv->client->addr; + msg.index = index; + msg.param = param; + msg.rx_len = 4; + msg.domain_id = 0; + + ret = peci_command(priv->client->adapter, PECI_CMD_RD_PKG_CFG, sizeof(msg), &msg); + if (msg.cc != PECI_DEV_CC_SUCCESS) + ret = -EAGAIN; + if (ret) + return ret; + + memcpy(data, msg.pkg_config, 4); + + return 0; +} + +/** + * peci_client_write_package_config - write to the Package Configuration Space + * @priv: driver private data structure + * @index: encoding index for the requested service + * @param: parameter to specify the exact data being requested + * @data: data to write + * Context: can sleep + * + * Return: zero on success, else a negative error code. + */ +static inline int +peci_client_write_package_config(struct peci_client_manager *priv, + u8 index, u16 param, u32 data) +{ + struct peci_wr_pkg_cfg_msg msg; + int ret; + + msg.addr = priv->client->addr; + msg.index = index; + msg.param = param; + msg.tx_len = 4u; + msg.value = data; + msg.domain_id = 0; + + ret = peci_command(priv->client->adapter, PECI_CMD_WR_PKG_CFG, sizeof(msg), &msg); + if (!ret) { + if (msg.cc != PECI_DEV_CC_SUCCESS) + ret = -EAGAIN; + } + + return ret; +} + +#endif /* __LINUX_MFD_INTEL_PECI_CLIENT_H */ diff --git a/include/linux/peci.h b/include/linux/peci.h new file mode 100644 index 000000000000..5a707bbeb66d --- /dev/null +++ b/include/linux/peci.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2019 Intel Corporation */ + +#ifndef __LINUX_PECI_H +#define __LINUX_PECI_H + +#include <linux/device.h> +#include <linux/mutex.h> +#include <linux/peci-ioctl.h> + +#define PECI_NAME_SIZE 32 + +struct peci_board_info { + char type[PECI_NAME_SIZE]; + u8 addr; /* CPU client address */ + struct device_node *of_node; +}; + +/** + * struct peci_adapter - represent a PECI adapter + * @owner: owner module of the PECI adpater + * @bus_lock: mutex for exclusion of multiple callers + * @dev: device interface to this driver + * @nr: the bus number to map + * @name: name of the adapter + * @userspace_clients_lock: mutex for exclusion of clients handling + * @userspace_clients: list of registered clients + * @xfer: low-level transfer function pointer of the adapter + * @cmd_mask: mask for supportable PECI commands + * @use_dma: flag for indicating that adapter uses DMA + * + * Each PECI adapter can communicate with one or more PECI client children. + * These make a small bus, sharing a single wired PECI connection. + */ +struct peci_adapter { + struct module *owner; + struct mutex bus_lock; /* mutex for bus locking */ + struct device dev; + int nr; + char name[PECI_NAME_SIZE]; + struct mutex userspace_clients_lock; /* clients list mutex */ + struct list_head userspace_clients; + int (*xfer)(struct peci_adapter *adapter, + struct peci_xfer_msg *msg); + u32 cmd_mask; + bool use_dma; + u8 peci_revision; +}; + +static inline struct peci_adapter *to_peci_adapter(void *d) +{ + return container_of(d, struct peci_adapter, dev); +} + +static inline void *peci_get_adapdata(const struct peci_adapter *adapter) +{ + return dev_get_drvdata(&adapter->dev); +} + +static inline void peci_set_adapdata(struct peci_adapter *adapter, void *data) +{ + dev_set_drvdata(&adapter->dev, data); +} + +/** + * struct peci_client - represent a PECI client device + * @dev: driver model device node for the client + * @adapter: manages the bus segment hosting this PECI device + * @addr: address used on the PECI bus connected to the parent adapter + * @name: indicates the type of the device + * @detected: detected PECI clients list + * + * A peci_client identifies a single device (i.e. CPU) connected to a peci bus. + * The behaviour exposed to Linux is defined by the driver managing the device. + */ +struct peci_client { + struct device dev; + struct peci_adapter *adapter; + u8 addr; + char name[PECI_NAME_SIZE]; + struct list_head detected; +}; + +static inline struct peci_client *to_peci_client(void *d) +{ + return container_of(d, struct peci_client, dev); +} + +struct peci_device_id { + char name[PECI_NAME_SIZE]; + ulong driver_data; /* Data private to the driver */ +}; + +/** + * struct peci_driver - represent a PECI device driver + * @probe: callback for device binding + * @remove: callback for device unbinding + * @shutdown: callback for device shutdown + * @driver: device driver model driver + * @id_table: list of PECI devices supported by this driver + * + * The driver.owner field should be set to the module owner of this driver. + * The driver.name field should be set to the name of this driver. + */ +struct peci_driver { + int (*probe)(struct peci_client *client); + int (*remove)(struct peci_client *client); + void (*shutdown)(struct peci_client *client); + struct device_driver driver; + const struct peci_device_id *id_table; +}; + +static inline struct peci_driver *to_peci_driver(void *d) +{ + return container_of(d, struct peci_driver, driver); +} + +/** + * module_peci_driver - Helper macro for registering a modular PECI driver + * @__peci_driver: peci_driver struct + * + * Helper macro for PECI drivers which do not do anything special in module + * init/exit. This eliminates a lot of boilerplate. Each module may only + * use this macro once, and calling it replaces module_init() and module_exit() + */ +#define module_peci_driver(__peci_driver) \ + module_driver(__peci_driver, peci_add_driver, peci_del_driver) + +/* use a define to avoid include chaining to get THIS_MODULE */ +#define peci_add_driver(driver) peci_register_driver(THIS_MODULE, driver) + +extern struct bus_type peci_bus_type; +extern struct device_type peci_adapter_type; +extern struct device_type peci_client_type; + +int peci_register_driver(struct module *owner, struct peci_driver *drv); +void peci_del_driver(struct peci_driver *driver); +struct peci_client *peci_verify_client(struct device *dev); +struct peci_adapter *peci_alloc_adapter(struct device *dev, uint size); +struct peci_adapter *peci_get_adapter(int nr); +void peci_put_adapter(struct peci_adapter *adapter); +int peci_add_adapter(struct peci_adapter *adapter); +void peci_del_adapter(struct peci_adapter *adapter); +struct peci_adapter *peci_verify_adapter(struct device *dev); +int peci_for_each_dev(void *data, int (*fn)(struct device *, void *)); +struct peci_xfer_msg *peci_get_xfer_msg(u8 tx_len, u8 rx_len); +void peci_put_xfer_msg(struct peci_xfer_msg *msg); +int peci_command(struct peci_adapter *adpater, enum peci_cmd cmd, uint msg_len, void *vmsg); +int peci_get_cpu_id(struct peci_adapter *adapter, u8 addr, u32 *cpu_id); + +#endif /* __LINUX_PECI_H */ diff --git a/include/uapi/linux/aspeed-espi-ioc.h b/include/uapi/linux/aspeed-espi-ioc.h new file mode 100644 index 000000000000..8e198158f6da --- /dev/null +++ b/include/uapi/linux/aspeed-espi-ioc.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 Aspeed Technology Inc. + */ +#ifndef _ASPEED_ESPI_IOC_H +#define _ASPEED_ESPI_IOC_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +/* + * eSPI cycle type encoding + * + * Section 5.1 Cycle Types and Packet Format, + * Intel eSPI Interface Base Specification, Rev 1.0, Jan. 2016. + */ +#define ESPI_PERIF_MEMRD32 0x00 +#define ESPI_PERIF_MEMRD64 0x02 +#define ESPI_PERIF_MEMWR32 0x01 +#define ESPI_PERIF_MEMWR64 0x03 +#define ESPI_PERIF_MSG 0x10 +#define ESPI_PERIF_MSG_D 0x11 +#define ESPI_PERIF_SUC_CMPLT 0x06 +#define ESPI_PERIF_SUC_CMPLT_D_MIDDLE 0x09 +#define ESPI_PERIF_SUC_CMPLT_D_FIRST 0x0b +#define ESPI_PERIF_SUC_CMPLT_D_LAST 0x0d +#define ESPI_PERIF_SUC_CMPLT_D_ONLY 0x0f +#define ESPI_PERIF_UNSUC_CMPLT 0x0c +#define ESPI_OOB_MSG 0x21 +#define ESPI_FLASH_READ 0x00 +#define ESPI_FLASH_WRITE 0x01 +#define ESPI_FLASH_ERASE 0x02 +#define ESPI_FLASH_SUC_CMPLT 0x06 +#define ESPI_FLASH_SUC_CMPLT_D_MIDDLE 0x09 +#define ESPI_FLASH_SUC_CMPLT_D_FIRST 0x0b +#define ESPI_FLASH_SUC_CMPLT_D_LAST 0x0d +#define ESPI_FLASH_SUC_CMPLT_D_ONLY 0x0f +#define ESPI_FLASH_UNSUC_CMPLT 0x0c + +/* + * eSPI packet format structure + * + * Section 5.1 Cycle Types and Packet Format, + * Intel eSPI Interface Base Specification, Rev 1.0, Jan. 2016. + */ +struct espi_comm_hdr { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; +} __packed; + +struct espi_perif_mem32 { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; + u32 addr_be; + u8 data[]; +} __packed; + +struct espi_perif_mem64 { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; + u32 addr_be; + u8 data[]; +} __packed; + +struct espi_perif_msg { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; + u8 msg_code; + u8 msg_byte[4]; + u8 data[]; +} __packed; + +struct espi_perif_cmplt { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; + u8 data[]; +} __packed; + +struct espi_oob_msg { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; + u8 data[]; +} __packed; + +struct espi_flash_rwe { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; + u32 addr_be; + u8 data[]; +} __packed; + +struct espi_flash_cmplt { + u8 cyc; + u8 len_h : 4; + u8 tag : 4; + u8 len_l; + u8 data[]; +} __packed; + +struct aspeed_espi_ioc { + u32 pkt_len; + u8 *pkt; +}; + +#define ESPI_LEN_HIGH(len) (((len) >> 0x08) & 0x0F) +#define ESPI_LEN_LOW(len) ((len) & 0xFF) +#define ESPI_LEN(len_h, len_l) ((((len_h) << 0x08) & 0x0F00) | ((len_l) & 0xFF)) + +/* + * We choose the longest header and the max payload size based on the Intel + * specification to define the maximum eSPI packet length. + */ +#define ASPEED_ESPI_PLD_LEN_MIN BIT(6) +#define ASPEED_ESPI_PLD_LEN_MAX BIT(12) +#define ASPEED_ESPI_PKT_LEN_MAX (sizeof(struct espi_perif_msg) + ASPEED_ESPI_PLD_LEN_MAX) + +#define __ASPEED_ESPI_IOCTL_MAGIC 0xb8 + +/* + * The IOCTL-based interface works in the eSPI packet in/out paradigm. + * + * Only the virtual wire IOCTL is a special case which does not send + * or receive an eSPI packet. However, to keep a more consisten use from + * userspace, we make all of the four channel drivers serve through the + * IOCTL interface. + * + * For the eSPI packet format, refer to + * Section 5.1 Cycle Types and Packet Format, + * Intel eSPI Interface Base Specification, Rev 1.0, Jan. 2016. + * + * For the example user apps using these IOCTL, refer to + * https://github.com/AspeedTech-BMC/aspeed_app/tree/master/espi_test + */ + +/* + * Peripheral Channel (CH0) + * - ASPEED_ESPI_PERIF_PC_GET_RX + * Receive an eSPI Posted/Completion packet + * - ASPEED_ESPI_PERIF_PC_PUT_TX + * Transmit an eSPI Posted/Completion packet + * - ASPEED_ESPI_PERIF_NP_PUT_TX + * Transmit an eSPI Non-Posted packet + */ +#define ASPEED_ESPI_PERIF_PC_GET_RX _IOR(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x00, struct aspeed_espi_ioc) +#define ASPEED_ESPI_PERIF_PC_PUT_TX _IOW(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x01, struct aspeed_espi_ioc) +#define ASPEED_ESPI_PERIF_NP_PUT_TX _IOW(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x02, struct aspeed_espi_ioc) +/* + * Virtual Wire Channel (CH1) + * - ASPEED_ESPI_VW_GET_GPIO_VAL + * Read the input value of GPIO over the VW channel + * - ASPEED_ESPI_VW_PUT_GPIO_VAL + * Write the output value of GPIO over the VW channel + */ +#define ASPEED_ESPI_VW_GET_GPIO_VAL _IOR(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x10, u8) +#define ASPEED_ESPI_VW_PUT_GPIO_VAL _IOW(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x11, u8) +/* + * Out-of-band Channel (CH2) + * - ASPEED_ESPI_OOB_GET_RX + * Receive an eSPI OOB packet + * - ASPEED_ESPI_OOB_PUT_TX + * Transmit an eSPI OOB packet + */ +#define ASPEED_ESPI_OOB_GET_RX _IOR(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x20, struct aspeed_espi_ioc) +#define ASPEED_ESPI_OOB_PUT_TX _IOW(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x21, struct aspeed_espi_ioc) +/* + * Flash Channel (CH3) + * - ASPEED_ESPI_FLASH_GET_RX + * Receive an eSPI flash packet + * - ASPEED_ESPI_FLASH_PUT_TX + * Transmit an eSPI flash packet + */ +#define ASPEED_ESPI_FLASH_GET_RX _IOR(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x30, struct aspeed_espi_ioc) +#define ASPEED_ESPI_FLASH_PUT_TX _IOW(__ASPEED_ESPI_IOCTL_MAGIC, \ + 0x31, struct aspeed_espi_ioc) + +#endif diff --git a/include/uapi/linux/aspeed-lpc-mbox.h b/include/uapi/linux/aspeed-lpc-mbox.h new file mode 100644 index 000000000000..dbb8a7f24222 --- /dev/null +++ b/include/uapi/linux/aspeed-lpc-mbox.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later WITH Linux-syscall-note */ +/* Copyright (c) 2021 Intel Corporation */ + +struct aspeed_mbox_ioctl_data { + unsigned int data; +}; + +#define ASPEED_MBOX_IOCTL_BASE 0xA3 + +#define ASPEED_MBOX_SIZE \ + _IOR(ASPEED_MBOX_IOCTL_BASE, 0, struct aspeed_mbox_ioctl_data) diff --git a/include/uapi/linux/aspeed-lpc-sio.h b/include/uapi/linux/aspeed-lpc-sio.h new file mode 100644 index 000000000000..0a4ae34a8ed1 --- /dev/null +++ b/include/uapi/linux/aspeed-lpc-sio.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2012-2020 ASPEED Technology Inc. + * Copyright (c) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + */ + +#ifndef _UAPI_LINUX_ASPEED_LPC_SIO_H +#define _UAPI_LINUX_ASPEED_LPC_SIO_H + +#include <linux/ioctl.h> + +enum ACPI_SLP_STATE { + ACPI_STATE_S12 = 1, + ACPI_STATE_S3I, + ACPI_STATE_S45 +}; + +/* SWC & ACPI for SuperIO IOCTL */ +enum SIO_CMD { + SIO_GET_ACPI_STATE = 0, + SIO_GET_PWRGD_STATUS, + SIO_GET_ONCTL_STATUS, + SIO_SET_ONCTL_GPIO, + SIO_GET_PWRBTN_OVERRIDE, + SIO_GET_PFAIL_STATUS, /* Start from AC Loss */ + SIO_SET_BMC_SCI_EVENT, + SIO_SET_BMC_SMI_EVENT, + + SIO_MAX_CMD +}; + +struct sio_ioctl_data { + unsigned short sio_cmd; + unsigned short param; + unsigned int data; +}; + +#define SIO_IOC_BASE 'P' +#define SIO_IOC_COMMAND _IOWR(SIO_IOC_BASE, 1, struct sio_ioctl_data) + +#endif /* _UAPI_LINUX_ASPEED_LPC_SIO_H */ diff --git a/include/uapi/linux/aspeed-mctp.h b/include/uapi/linux/aspeed-mctp.h new file mode 100644 index 000000000000..678ec3d9f1cc --- /dev/null +++ b/include/uapi/linux/aspeed-mctp.h @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2020 Intel Corporation */ + +#ifndef _UAPI_LINUX_ASPEED_MCTP_H +#define _UAPI_LINUX_ASPEED_MCTP_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +/* + * aspeed-mctp is a simple device driver exposing a read/write interface: + * +----------------------+ + * | PCIe VDM Header | 16 bytes (Big Endian) + * +----------------------+ + * | MCTP Message Payload | 64/128/256/512 bytes (Big Endian) + * +----------------------+ + * + * MCTP packet description can be found in DMTF DSP0238, + * MCTP PCIe VDM Transport Specification. + */ + +#define ASPEED_MCTP_PCIE_VDM_HDR_SIZE 16 + +/* + * uevents generated by aspeed-mctp driver + */ +#define ASPEED_MCTP_READY "PCIE_READY" + +/* + * maximum possible number of struct eid_info elements stored in list + */ +#define ASPEED_MCTP_EID_INFO_MAX 256 + +/* + * MCTP operations + * @ASPEED_MCTP_IOCTL_FILTER_EID: enable/disable filter incoming packets based + * on Endpoint ID (BROKEN) + * @ASPEED_MCTP_IOCTL_GET_BDF: read PCI bus/device/function of MCTP Controller + * @ASPEED_MCTP_IOCTL_GET_MEDIUM_ID: read MCTP physical medium identifier + * related to PCIe revision + * @ASPEED_MCTP_IOCTL_GET_MTU: read max transmission unit (in bytes) + * @ASPEED_MCTP_IOCTL_REGISTER_DEFAULT_HANDLER Register client as default + * handler that receives all MCTP messages that were not dispatched to other + * clients + * @ASPEED_MCTP_IOCTL_REGISTER_TYPE_HANDLER Register client to receive all + * messages of specified MCTP type or PCI vendor defined type + * @ASPEED_MCTP_IOCTL_UNREGISTER_TYPE_HANDLER Unregister client as handler + * for specified MCTP type or PCI vendor defined message type + * @ASPEED_MCTP_GET_EID_INFO: read list of existing endpoint mappings + * returns count which is less of the two requested count and existing count + * @ASPEED_MCTP_SET_EID_INFO: write list of endpoint mappings + * overwrites already existing endpoint mappings + */ + +struct aspeed_mctp_filter_eid { + __u8 eid; + bool enable; +}; + +struct aspeed_mctp_get_bdf { + __u16 bdf; +}; + +struct aspeed_mctp_get_medium_id { + __u8 medium_id; +}; + +struct aspeed_mctp_get_mtu { + __u8 mtu; +}; + +struct aspeed_mctp_type_handler_ioctl { + __u8 mctp_type; /* MCTP message type as per DSP239*/ + /* Below params must be 0 if mctp_type is not Vendor Defined PCI */ + __u16 pci_vendor_id; /* PCI Vendor ID */ + __u16 vendor_type; /* Vendor specific type */ + __u16 vendor_type_mask; /* Mask applied to vendor type */ +}; + +struct aspeed_mctp_eid_info { + __u8 eid; + __u16 bdf; +}; + +struct aspeed_mctp_eid_ext_info { + __u8 eid; + __u16 bdf; + __u8 domain_id; +}; + +struct aspeed_mctp_get_eid_info { + __u64 ptr; + __u16 count; + __u8 start_eid; +}; + +struct aspeed_mctp_set_eid_info { + __u64 ptr; + __u16 count; +}; + +#define ASPEED_MCTP_IOCTL_BASE 0x4d + +#define ASPEED_MCTP_IOCTL_FILTER_EID \ + _IOW(ASPEED_MCTP_IOCTL_BASE, 0, struct aspeed_mctp_filter_eid) +#define ASPEED_MCTP_IOCTL_GET_BDF \ + _IOR(ASPEED_MCTP_IOCTL_BASE, 1, struct aspeed_mctp_get_bdf) +#define ASPEED_MCTP_IOCTL_GET_MEDIUM_ID \ + _IOR(ASPEED_MCTP_IOCTL_BASE, 2, struct aspeed_mctp_get_medium_id) +#define ASPEED_MCTP_IOCTL_GET_MTU \ + _IOR(ASPEED_MCTP_IOCTL_BASE, 3, struct aspeed_mctp_get_mtu) +#define ASPEED_MCTP_IOCTL_REGISTER_DEFAULT_HANDLER \ + _IO(ASPEED_MCTP_IOCTL_BASE, 4) +#define ASPEED_MCTP_IOCTL_REGISTER_TYPE_HANDLER \ + _IOW(ASPEED_MCTP_IOCTL_BASE, 6, struct aspeed_mctp_type_handler_ioctl) +#define ASPEED_MCTP_IOCTL_UNREGISTER_TYPE_HANDLER \ + _IOW(ASPEED_MCTP_IOCTL_BASE, 7, struct aspeed_mctp_type_handler_ioctl) +#define ASPEED_MCTP_IOCTL_GET_EID_INFO \ + _IOWR(ASPEED_MCTP_IOCTL_BASE, 8, struct aspeed_mctp_get_eid_info) +#define ASPEED_MCTP_IOCTL_SET_EID_INFO \ + _IOW(ASPEED_MCTP_IOCTL_BASE, 9, struct aspeed_mctp_set_eid_info) +#define ASPEED_MCTP_IOCTL_GET_EID_EXT_INFO \ + _IOW(ASPEED_MCTP_IOCTL_BASE, 10, struct aspeed_mctp_get_eid_info) +#define ASPEED_MCTP_IOCTL_SET_EID_EXT_INFO \ + _IOW(ASPEED_MCTP_IOCTL_BASE, 11, struct aspeed_mctp_set_eid_info) + + +#endif /* _UAPI_LINUX_ASPEED_MCTP_H */ diff --git a/include/uapi/linux/i2c.h b/include/uapi/linux/i2c.h index 92326ebde350..83e0f406fedc 100644 --- a/include/uapi/linux/i2c.h +++ b/include/uapi/linux/i2c.h @@ -75,6 +75,7 @@ struct i2c_msg { __u16 flags; #define I2C_M_RD 0x0001 /* guaranteed to be 0x0001! */ #define I2C_M_TEN 0x0010 /* use only if I2C_FUNC_10BIT_ADDR */ +#define I2C_M_HOLD 0x0100 /* for holding a mux path */ #define I2C_M_DMA_SAFE 0x0200 /* use only in kernel space */ #define I2C_M_RECV_LEN 0x0400 /* use only if I2C_FUNC_SMBUS_READ_BLOCK_DATA */ #define I2C_M_NO_RD_ACK 0x0800 /* use only if I2C_FUNC_PROTOCOL_MANGLING */ diff --git a/include/uapi/linux/i3c/i3cdev.h b/include/uapi/linux/i3c/i3cdev.h new file mode 100644 index 000000000000..0897313f5516 --- /dev/null +++ b/include/uapi/linux/i3c/i3cdev.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* + * Copyright (c) 2019 Synopsys, Inc. and/or its affiliates. + * + * Author: Vitor Soares <vitor.soares@synopsys.com> + */ + +#ifndef _UAPI_I3C_DEV_H_ +#define _UAPI_I3C_DEV_H_ + +#include <linux/types.h> +#include <linux/ioctl.h> + +/* IOCTL commands */ +#define I3C_DEV_IOC_MAGIC 0x07 + +/** + * struct i3c_ioc_priv_xfer - I3C SDR ioctl private transfer + * @data: Holds pointer to userspace buffer with transmit data. + * @len: Length of data buffer buffers, in bytes. + * @rnw: encodes the transfer direction. true for a read, false for a write + */ +struct i3c_ioc_priv_xfer { + __u64 data; + __u16 len; + __u8 rnw; + __u8 pad[5]; +}; + + +#define I3C_PRIV_XFER_SIZE(N) \ + ((((sizeof(struct i3c_ioc_priv_xfer)) * (N)) < (1 << _IOC_SIZEBITS)) \ + ? ((sizeof(struct i3c_ioc_priv_xfer)) * (N)) : 0) + +#define I3C_IOC_PRIV_XFER(N) \ + _IOC(_IOC_READ|_IOC_WRITE, I3C_DEV_IOC_MAGIC, 30, I3C_PRIV_XFER_SIZE(N)) + +#endif diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h new file mode 100644 index 000000000000..b500266cfd61 --- /dev/null +++ b/include/uapi/linux/jtag.h @@ -0,0 +1,369 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Mellanox Technologies. All rights reserved. */ +/* Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com> */ +/* Copyright (c) 2019 Intel Corporation */ + +#ifndef __UAPI_LINUX_JTAG_H +#define __UAPI_LINUX_JTAG_H + +#include <linux/types.h> +#include <linux/ioctl.h> + +/* + * JTAG_XFER_MODE: JTAG transfer mode. Used to set JTAG controller transfer mode + * This is bitmask for feature param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_XFER_MODE 0 +/* + * JTAG_CONTROL_MODE: JTAG controller mode. Used to set JTAG controller mode + * This is bitmask for feature param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_CONTROL_MODE 1 +/* + * JTAG_MASTER_OUTPUT_DISABLE: JTAG master mode output disable, it is used to + * enable other devices to own the JTAG bus. + * This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_MASTER_OUTPUT_DISABLE 0 +/* + * JTAG_MASTER_MODE: JTAG master mode. Used to set JTAG controller master mode + * This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_MASTER_MODE 1 +/* + * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived or bitbang + * mode. This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_XFER_HW_MODE 1 +/* + * JTAG_XFER_SW_MODE: JTAG software mode. Used to set SW drived or bitbang + * mode. This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_XFER_SW_MODE 0 + +/** + * enum jtag_tapstate: + * + * @JTAG_STATE_TLRESET: JTAG state machine Test Logic Reset state + * @JTAG_STATE_IDLE: JTAG state machine IDLE state + * @JTAG_STATE_SELECTDR: JTAG state machine SELECT_DR state + * @JTAG_STATE_CAPTUREDR: JTAG state machine CAPTURE_DR state + * @JTAG_STATE_SHIFTDR: JTAG state machine SHIFT_DR state + * @JTAG_STATE_EXIT1DR: JTAG state machine EXIT-1 DR state + * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state + * @JTAG_STATE_EXIT2DR: JTAG state machine EXIT-2 DR state + * @JTAG_STATE_UPDATEDR: JTAG state machine UPDATE DR state + * @JTAG_STATE_SELECTIR: JTAG state machine SELECT_IR state + * @JTAG_STATE_CAPTUREIR: JTAG state machine CAPTURE_IR state + * @JTAG_STATE_SHIFTIR: JTAG state machine SHIFT_IR state + * @JTAG_STATE_EXIT1IR: JTAG state machine EXIT-1 IR state + * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state + * @JTAG_STATE_EXIT2IR: JTAG state machine EXIT-2 IR state + * @JTAG_STATE_UPDATEIR: JTAG state machine UPDATE IR state + * @JTAG_STATE_CURRENT: JTAG current state, saved by driver + */ +enum jtag_tapstate { + JTAG_STATE_TLRESET, + JTAG_STATE_IDLE, + JTAG_STATE_SELECTDR, + JTAG_STATE_CAPTUREDR, + JTAG_STATE_SHIFTDR, + JTAG_STATE_EXIT1DR, + JTAG_STATE_PAUSEDR, + JTAG_STATE_EXIT2DR, + JTAG_STATE_UPDATEDR, + JTAG_STATE_SELECTIR, + JTAG_STATE_CAPTUREIR, + JTAG_STATE_SHIFTIR, + JTAG_STATE_EXIT1IR, + JTAG_STATE_PAUSEIR, + JTAG_STATE_EXIT2IR, + JTAG_STATE_UPDATEIR, + JTAG_STATE_CURRENT +}; + +/** + * enum jtag_reset: + * + * @JTAG_NO_RESET: JTAG run TAP from current state + * @JTAG_FORCE_RESET: JTAG force TAP to reset state + */ +enum jtag_reset { + JTAG_NO_RESET = 0, + JTAG_FORCE_RESET = 1, +}; + +/** + * enum jtag_xfer_type: + * + * @JTAG_SIR_XFER: SIR transfer + * @JTAG_SDR_XFER: SDR transfer + */ +enum jtag_xfer_type { + JTAG_SIR_XFER = 0, + JTAG_SDR_XFER = 1, +}; + +/** + * enum jtag_xfer_direction: + * + * @JTAG_READ_XFER: read transfer + * @JTAG_WRITE_XFER: write transfer + * @JTAG_READ_WRITE_XFER: read & write transfer + */ +enum jtag_xfer_direction { + JTAG_READ_XFER = 1, + JTAG_WRITE_XFER = 2, + JTAG_READ_WRITE_XFER = 3, +}; + +/** + * struct jtag_tap_state - forces JTAG state machine to go into a TAPC + * state + * + * @reset: 0 - run IDLE/PAUSE from current state + * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE + * @end: completion flag + * @tck: clock counter + * + * Structure provide interface to JTAG device for JTAG set state execution. + */ +struct jtag_tap_state { + __u8 reset; + __u8 from; + __u8 endstate; + __u8 tck; +}; + +/** + * union pad_config - Padding Configuration: + * + * @type: transfer type + * @pre_pad_number: Number of prepadding bits bit[11:0] + * @post_pad_number: Number of prepadding bits bit[23:12] + * @pad_data : Bit value to be used by pre and post padding bit[24] + * @int_value: unsigned int packed padding configuration value bit[32:0] + * + * Structure provide pre and post padding configuration in a single __u32 + */ +union pad_config { + struct { + __u32 pre_pad_number : 12; + __u32 post_pad_number : 12; + __u32 pad_data : 1; + __u32 rsvd : 7; + }; + __u32 int_value; +}; + +/** + * struct jtag_xfer - jtag xfer: + * + * @type: transfer type + * @direction: xfer direction + * @from: xfer current state + * @endstate: xfer end state + * @padding: xfer padding + * @length: xfer bits length + * @tdio : xfer data array + * + * Structure provide interface to JTAG device for JTAG SDR/SIR xfer execution. + */ +struct jtag_xfer { + __u8 type; + __u8 direction; + __u8 from; + __u8 endstate; + __u32 padding; + __u32 length; + __u64 tdio; +}; + +/** + * struct bitbang_packet - jtag bitbang array packet: + * + * @data: JTAG Bitbang struct array pointer(input/output) + * @length: array size (input) + * + * Structure provide interface to JTAG device for JTAG bitbang bundle execution + */ +struct bitbang_packet { + struct tck_bitbang *data; + __u32 length; +} __attribute__((__packed__)); + +/** + * struct jtag_bitbang - jtag bitbang: + * + * @tms: JTAG TMS + * @tdi: JTAG TDI (input) + * @tdo: JTAG TDO (output) + * + * Structure provide interface to JTAG device for JTAG bitbang execution. + */ +struct tck_bitbang { + __u8 tms; + __u8 tdi; + __u8 tdo; +} __attribute__((__packed__)); + +/** + * struct jtag_mode - jtag mode: + * + * @feature: 0 - JTAG feature setting selector for JTAG controller HW/SW + * 1 - JTAG feature setting selector for controller bus master + * mode output (enable / disable). + * @mode: (0 - SW / 1 - HW) for JTAG_XFER_MODE feature(0) + * (0 - output disable / 1 - output enable) for JTAG_CONTROL_MODE + * feature(1) + * + * Structure provide configuration modes to JTAG device. + */ +struct jtag_mode { + __u32 feature; + __u32 mode; +}; + +/* ioctl interface */ +#define __JTAG_IOCTL_MAGIC 0xb2 + +#define JTAG_SIOCSTATE _IOW(__JTAG_IOCTL_MAGIC, 0, struct jtag_tap_state) +#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned int) +#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int) +#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct jtag_xfer) +#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum jtag_tapstate) +#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned int) +#define JTAG_IOCBITBANG _IOW(__JTAG_IOCTL_MAGIC, 6, unsigned int) + +/** + * struct tms_cycle - This structure represents a tms cycle state. + * + * @tmsbits: is the bitwise representation of the needed tms transitions to + * move from one state to another. + * @count: number of jumps needed to move to the needed state. + * + */ +struct tms_cycle { + unsigned char tmsbits; + unsigned char count; +}; + +/* + * This is the complete set TMS cycles for going from any TAP state to any + * other TAP state, following a "shortest path" rule. + */ +static const struct tms_cycle _tms_cycle_lookup[][16] = { +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* TLR */{{0x00, 0}, {0x00, 1}, {0x02, 2}, {0x02, 3}, {0x02, 4}, {0x0a, 4}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x0a, 5}, {0x2a, 6}, {0x1a, 5}, {0x06, 3}, {0x06, 4}, {0x06, 5}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x16, 5}, {0x16, 6}, {0x56, 7}, {0x36, 6} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* RTI */{{0x07, 3}, {0x00, 0}, {0x01, 1}, {0x01, 2}, {0x01, 3}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x05, 4}, {0x15, 5}, {0x0d, 4}, {0x03, 2}, {0x03, 3}, {0x03, 4}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x0b, 4}, {0x0b, 5}, {0x2b, 6}, {0x1b, 5} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SelDR*/{{0x03, 2}, {0x03, 3}, {0x00, 0}, {0x00, 1}, {0x00, 2}, {0x02, 2}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x02, 3}, {0x0a, 4}, {0x06, 3}, {0x01, 1}, {0x01, 2}, {0x01, 3}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x05, 3}, {0x05, 4}, {0x15, 5}, {0x0d, 4} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* CapDR*/{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x00, 0}, {0x00, 1}, {0x01, 1}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x01, 2}, {0x05, 3}, {0x03, 2}, {0x0f, 4}, {0x0f, 5}, {0x0f, 6}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x2f, 6}, {0x2f, 7}, {0xaf, 8}, {0x6f, 7} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SDR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x00, 0}, {0x01, 1}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x01, 2}, {0x05, 3}, {0x03, 2}, {0x0f, 4}, {0x0f, 5}, {0x0f, 6}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x2f, 6}, {0x2f, 7}, {0xaf, 8}, {0x6f, 7} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex1DR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x02, 3}, {0x00, 0}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x00, 1}, {0x02, 2}, {0x01, 1}, {0x07, 3}, {0x07, 4}, {0x07, 5}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x17, 5}, {0x17, 6}, {0x57, 7}, {0x37, 6} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* PDR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x01, 2}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x00, 0}, {0x01, 1}, {0x03, 2}, {0x0f, 4}, {0x0f, 5}, {0x0f, 6}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x2f, 6}, {0x2f, 7}, {0xaf, 8}, {0x6f, 7} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex2DR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x00, 1}, {0x02, 2}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x02, 3}, {0x00, 0}, {0x01, 1}, {0x07, 3}, {0x07, 4}, {0x07, 5}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x17, 5}, {0x17, 6}, {0x57, 7}, {0x37, 6} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* UpdDR*/{{0x07, 3}, {0x00, 1}, {0x01, 1}, {0x01, 2}, {0x01, 3}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x05, 4}, {0x15, 5}, {0x00, 0}, {0x03, 2}, {0x03, 3}, {0x03, 4}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x0b, 4}, {0x0b, 5}, {0x2b, 6}, {0x1b, 5} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SelIR*/{{0x01, 1}, {0x01, 2}, {0x05, 3}, {0x05, 4}, {0x05, 5}, {0x15, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x15, 6}, {0x55, 7}, {0x35, 6}, {0x00, 0}, {0x00, 1}, {0x00, 2}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x02, 2}, {0x02, 3}, {0x0a, 4}, {0x06, 3} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* CapIR*/{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x07, 5}, {0x17, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x17, 6}, {0x57, 7}, {0x37, 6}, {0x0f, 4}, {0x00, 0}, {0x00, 1}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x01, 1}, {0x01, 2}, {0x05, 3}, {0x03, 2} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SIR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x07, 5}, {0x17, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x17, 6}, {0x57, 7}, {0x37, 6}, {0x0f, 4}, {0x0f, 5}, {0x00, 0}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x01, 1}, {0x01, 2}, {0x05, 3}, {0x03, 2} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex1IR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x03, 4}, {0x0b, 4}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x0b, 5}, {0x2b, 6}, {0x1b, 5}, {0x07, 3}, {0x07, 4}, {0x02, 3}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x00, 0}, {0x00, 1}, {0x02, 2}, {0x01, 1} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* PIR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x07, 5}, {0x17, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x17, 6}, {0x57, 7}, {0x37, 6}, {0x0f, 4}, {0x0f, 5}, {0x01, 2}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x05, 3}, {0x00, 0}, {0x01, 1}, {0x03, 2} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex2IR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x03, 4}, {0x0b, 4}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x0b, 5}, {0x2b, 6}, {0x1b, 5}, {0x07, 3}, {0x07, 4}, {0x00, 1}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x02, 2}, {0x02, 3}, {0x00, 0}, {0x01, 1} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* UpdIR*/{{0x07, 3}, {0x00, 1}, {0x01, 1}, {0x01, 2}, {0x01, 3}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x05, 4}, {0x15, 5}, {0x0d, 4}, {0x03, 2}, {0x03, 3}, {0x03, 4}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x0b, 4}, {0x0b, 5}, {0x2b, 6}, {0x00, 0} }, +}; + +#endif /* __UAPI_LINUX_JTAG_H */ diff --git a/include/uapi/linux/jtag_drv.h b/include/uapi/linux/jtag_drv.h new file mode 100644 index 000000000000..4df638f8fa43 --- /dev/null +++ b/include/uapi/linux/jtag_drv.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (C) 2012-2017 ASPEED Technology Inc. */ +/* Copyright (c) 2018 Intel Corporation */ + +#ifndef __JTAG_DRV_H__ +#define __JTAG_DRV_H__ + +enum xfer_mode { + HW_MODE = 0, + SW_MODE +} xfer_mode; + +struct tck_bitbang { + __u8 tms; + __u8 tdi; + __u8 tdo; +} __attribute__((__packed__)); + +struct scan_xfer { + __u8 mode; + __u32 tap_state; + __u32 length; + __u8 *tdi; + __u32 tdi_bytes; + __u8 *tdo; + __u32 tdo_bytes; + __u32 end_tap_state; +} __attribute__((__packed__)); + +struct set_tck_param { + __u8 mode; + __u32 tck; +} __attribute__((__packed__)); + +struct get_tck_param { + __u8 mode; + __u32 tck; +} __attribute__((__packed__)); + +struct tap_state_param { + __u8 mode; + __u32 from_state; + __u32 to_state; +} __attribute__((__packed__)); + +enum jtag_states { + jtag_tlr, + jtag_rti, + jtag_sel_dr, + jtag_cap_dr, + jtag_shf_dr, + jtag_ex1_dr, + jtag_pau_dr, + jtag_ex2_dr, + jtag_upd_dr, + jtag_sel_ir, + jtag_cap_ir, + jtag_shf_ir, + jtag_ex1_ir, + jtag_pau_ir, + jtag_ex2_ir, + jtag_upd_ir +} jtag_states; + +#define JTAGIOC_BASE 'T' + +#define AST_JTAG_SET_TCK _IOW(JTAGIOC_BASE, 3, struct set_tck_param) +#define AST_JTAG_GET_TCK _IOR(JTAGIOC_BASE, 4, struct get_tck_param) +#define AST_JTAG_BITBANG _IOWR(JTAGIOC_BASE, 5, struct tck_bitbang) +#define AST_JTAG_SET_TAPSTATE _IOW(JTAGIOC_BASE, 6, struct tap_state_param) +#define AST_JTAG_READWRITESCAN _IOWR(JTAGIOC_BASE, 7, struct scan_xfer) + +#endif diff --git a/include/uapi/linux/peci-ioctl.h b/include/uapi/linux/peci-ioctl.h new file mode 100644 index 000000000000..181559c0655d --- /dev/null +++ b/include/uapi/linux/peci-ioctl.h @@ -0,0 +1,703 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* Copyright (c) 2018-2020 Intel Corporation */ + +#ifndef __PECI_IOCTL_H +#define __PECI_IOCTL_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +/* The PECI client's default address of 0x30 */ +#define PECI_BASE_ADDR 0x30 + +/* Max number of CPU clients */ +#define PECI_OFFSET_MAX 8 + +/* Max number of domains per CPU */ +#define DOMAIN_OFFSET_MAX 16 + +/* PECI read/write data buffer size max */ +#define PECI_BUFFER_SIZE 255 + +/* Device Specific Completion Code (CC) Definition */ +#define PECI_DEV_CC_SUCCESS 0x40 +#define PECI_DEV_CC_NEED_RETRY 0x80 +#define PECI_DEV_CC_OUT_OF_RESOURCE 0x81 +#define PECI_DEV_CC_UNAVAIL_RESOURCE 0x82 +#define PECI_DEV_CC_INVALID_REQ 0x90 +#define PECI_DEV_CC_MCA_ERROR 0x91 +#define PECI_DEV_CC_CATASTROPHIC_MCA_ERROR 0x93 +#define PECI_DEV_CC_FATAL_MCA_DETECTED 0x94 +#define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB 0x98 +#define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_IERR 0x9B +#define PECI_DEV_CC_PARITY_ERROR_ON_GPSB_OR_PMSB_MCA 0x9C + +/* Completion Code mask to check retry needs */ +#define PECI_DEV_CC_RETRY_CHECK_MASK 0xf0 + +#define PECI_DEV_RETRY_TIMEOUT msecs_to_jiffies(700) +#define PECI_DEV_RETRY_INTERVAL_MIN_USEC 100 +#define PECI_DEV_RETRY_INTERVAL_MAX_USEC (128 * 1000) +#define PECI_DEV_RETRY_BIT 0x01 + +/** + * enum peci_cmd - PECI client commands + * @PECI_CMD_XFER: raw PECI transfer + * @PECI_CMD_PING: ping, a required message for all PECI devices + * @PECI_CMD_GET_DIB: get DIB (Device Info Byte) + * @PECI_CMD_GET_TEMP: get maximum die temperature + * @PECI_CMD_RD_PKG_CFG: read access to the PCS (Package Configuration Space) + * @PECI_CMD_WR_PKG_CFG: write access to the PCS (Package Configuration Space) + * @PECI_CMD_RD_IA_MSR: read access to MSRs (Model Specific Registers) + * @PECI_CMD_WR_IA_MSR: write access to MSRs (Model Specific Registers) + * @PECI_CMD_RD_IA_MSREX: read access to MSRs (Model Specific Registers) + * @PECI_CMD_RD_PCI_CFG: sideband read access to the PCI configuration space + * maintained in downstream devices external to the processor + * @PECI_CMD_WR_PCI_CFG: sideband write access to the PCI configuration space + * maintained in downstream devices external to the processor + * @PECI_CMD_RD_PCI_CFG_LOCAL: sideband read access to the PCI configuration + * space that resides within the processor + * @PECI_CMD_WR_PCI_CFG_LOCAL: sideband write access to the PCI configuration + * space that resides within the processor + * + * Available commands depend on client's PECI revision. + */ +enum peci_cmd { + PECI_CMD_XFER = 0, + PECI_CMD_PING, + PECI_CMD_GET_DIB, + PECI_CMD_GET_TEMP, + PECI_CMD_RD_PKG_CFG, + PECI_CMD_WR_PKG_CFG, + PECI_CMD_RD_IA_MSR, + PECI_CMD_WR_IA_MSR, + PECI_CMD_RD_IA_MSREX, + PECI_CMD_RD_PCI_CFG, + PECI_CMD_WR_PCI_CFG, + PECI_CMD_RD_PCI_CFG_LOCAL, + PECI_CMD_WR_PCI_CFG_LOCAL, + PECI_CMD_RD_END_PT_CFG, + PECI_CMD_WR_END_PT_CFG, + PECI_CMD_CRASHDUMP_DISC, + PECI_CMD_CRASHDUMP_GET_FRAME, + PECI_CMD_MAX +}; + +/** + * struct peci_xfer_msg - raw PECI transfer command + * @addr; address of the client + * @tx_len: number of data to be written in bytes + * @rx_len: number of data to be read in bytes + * @tx_buf: data to be written, or NULL + * @rx_buf: data to be read, or NULL + * + * raw PECI transfer + */ +struct peci_xfer_msg { + __u8 addr; + __u8 tx_len; + __u8 rx_len; + __u8 padding; + __u8 *tx_buf; + __u8 *rx_buf; +} __attribute__((__packed__)); + +/** + * struct peci_ping_msg - ping command + * @addr: address of the client + * + * Ping() is a required message for all PECI devices. This message is used to + * enumerate devices or determine if a device has been removed, been + * powered-off, etc. + */ +struct peci_ping_msg { + __u8 addr; + __u8 padding[3]; +} __attribute__((__packed__)); + +/** + * struct peci_get_dib_msg - GetDIB command + * @addr: address of the client + * @dib: DIB data to be read + * + * The processor PECI client implementation of GetDIB() includes an 8-byte + * response and provides information regarding client revision number and the + * number of supported domains. All processor PECI clients support the GetDIB() + * command. + */ +struct peci_get_dib_msg { +#define PECI_GET_DIB_WR_LEN 1 +#define PECI_GET_DIB_RD_LEN 8 +#define PECI_GET_DIB_CMD 0xf7 + + __u8 addr; + __u8 padding[3]; + __u64 dib; +} __attribute__((__packed__)); + +/** + * struct peci_get_temp_msg - GetTemp command + * @addr: address of the client + * @temp_raw: raw temperature data to be read + * + * The GetTemp() command is used to retrieve the maximum die temperature from a + * target PECI address. The temperature is used by the external thermal + * management system to regulate the temperature on the die. The data is + * returned as a negative value representing the number of degrees centigrade + * below the maximum processor junction temperature. + */ +struct peci_get_temp_msg { +#define PECI_GET_TEMP_WR_LEN 1 +#define PECI_GET_TEMP_RD_LEN 2 +#define PECI_GET_TEMP_CMD 0x01 + + __u8 addr; + __u8 padding; + __s16 temp_raw; +} __attribute__((__packed__)); + +/** + * struct peci_rd_pkg_cfg_msg - RdPkgConfig command + * @addr: address of the client + * @index: encoding index for the requested service + * @param: specific data being requested + * @rx_len: number of data to be read in bytes + * @cc: completion code + * @pkg_config: package config data to be read + * @domain_id: domain ID of the client + * + * The RdPkgConfig() command provides read access to the Package Configuration + * Space (PCS) within the processor, including various power and thermal + * management functions. Typical PCS read services supported by the processor + * may include access to temperature data, energy status, run time information, + * DIMM temperatures and so on. + */ +struct peci_rd_pkg_cfg_msg { +#define PECI_RDPKGCFG_WRITE_LEN 5 +#define PECI_RDPKGCFG_READ_LEN_BASE 1 +#define PECI_RDPKGCFG_CMD 0xa1 + + __u8 addr; + __u8 index; +#define PECI_MBX_INDEX_CPU_ID 0 /* Package Identifier Read */ +#define PECI_MBX_INDEX_VR_DEBUG 1 /* VR Debug */ +#define PECI_MBX_INDEX_PKG_TEMP_READ 2 /* Package Temperature Read */ +#define PECI_MBX_INDEX_ENERGY_COUNTER 3 /* Energy counter */ +#define PECI_MBX_INDEX_ENERGY_STATUS 4 /* DDR Energy Status */ +#define PECI_MBX_INDEX_WAKE_MODE_BIT 5 /* "Wake on PECI" Mode bit */ +#define PECI_MBX_INDEX_EPI 6 /* Efficient Performance Indication */ +#define PECI_MBX_INDEX_PKG_RAPL_PERF 8 /* Pkg RAPL Performance Status Read */ +#define PECI_MBX_INDEX_MODULE_TEMP 9 /* Module Temperature Read */ +#define PECI_MBX_INDEX_DTS_MARGIN 10 /* DTS thermal margin */ +#define PECI_MBX_INDEX_SKT_PWR_THRTL_DUR 11 /* Socket Power Throttled Duration */ +#define PECI_MBX_INDEX_CFG_TDP_CONTROL 12 /* TDP Config Control */ +#define PECI_MBX_INDEX_CFG_TDP_LEVELS 13 /* TDP Config Levels */ +#define PECI_MBX_INDEX_DDR_DIMM_TEMP 14 /* DDR DIMM Temperature */ +#define PECI_MBX_INDEX_CFG_ICCMAX 15 /* Configurable ICCMAX */ +#define PECI_MBX_INDEX_TEMP_TARGET 16 /* Temperature Target Read */ +#define PECI_MBX_INDEX_CURR_CFG_LIMIT 17 /* Current Config Limit */ +#define PECI_MBX_INDEX_DIMM_TEMP_READ 20 /* Package Thermal Status Read */ +#define PECI_MBX_INDEX_DRAM_IMC_TMP_READ 22 /* DRAM IMC Temperature Read */ +#define PECI_MBX_INDEX_DDR_CH_THERM_STAT 23 /* DDR Channel Thermal Status */ +#define PECI_MBX_INDEX_PKG_POWER_LIMIT1 26 /* Package Power Limit1 */ +#define PECI_MBX_INDEX_PKG_POWER_LIMIT2 27 /* Package Power Limit2 */ +#define PECI_MBX_INDEX_TDP 28 /* Thermal design power minimum */ +#define PECI_MBX_INDEX_TDP_HIGH 29 /* Thermal design power maximum */ +#define PECI_MBX_INDEX_TDP_UNITS 30 /* Units for power/energy registers */ +#define PECI_MBX_INDEX_RUN_TIME 31 /* Accumulated Run Time */ +#define PECI_MBX_INDEX_CONSTRAINED_TIME 32 /* Thermally Constrained Time Read */ +#define PECI_MBX_INDEX_TURBO_RATIO 33 /* Turbo Activation Ratio */ +#define PECI_MBX_INDEX_DDR_RAPL_PL1 34 /* DDR RAPL PL1 */ +#define PECI_MBX_INDEX_DDR_PWR_INFO_HIGH 35 /* DRAM Power Info Read (high) */ +#define PECI_MBX_INDEX_DDR_PWR_INFO_LOW 36 /* DRAM Power Info Read (low) */ +#define PECI_MBX_INDEX_DDR_RAPL_PL2 37 /* DDR RAPL PL2 */ +#define PECI_MBX_INDEX_DDR_RAPL_STATUS 38 /* DDR RAPL Performance Status */ +#define PECI_MBX_INDEX_DDR_HOT_ABSOLUTE 43 /* DDR Hottest Dimm Absolute Temp */ +#define PECI_MBX_INDEX_DDR_HOT_RELATIVE 44 /* DDR Hottest Dimm Relative Temp */ +#define PECI_MBX_INDEX_DDR_THROTTLE_TIME 45 /* DDR Throttle Time */ +#define PECI_MBX_INDEX_DDR_THERM_STATUS 46 /* DDR Thermal Status */ +#define PECI_MBX_INDEX_TIME_AVG_TEMP 47 /* Package time-averaged temperature */ +#define PECI_MBX_INDEX_TURBO_RATIO_LIMIT 49 /* Turbo Ratio Limit Read */ +#define PECI_MBX_INDEX_HWP_AUTO_OOB 53 /* HWP Autonomous Out-of-band */ +#define PECI_MBX_INDEX_DDR_WARM_BUDGET 55 /* DDR Warm Power Budget */ +#define PECI_MBX_INDEX_DDR_HOT_BUDGET 56 /* DDR Hot Power Budget */ +#define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM3 57 /* Package/Psys Power Limit3 */ +#define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM1 58 /* Package/Psys Power Limit1 */ +#define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM2 59 /* Package/Psys Power Limit2 */ +#define PECI_MBX_INDEX_PKG_PSYS_PWR_LIM4 60 /* Package/Psys Power Limit4 */ +#define PECI_MBX_INDEX_PERF_LIMIT_REASON 65 /* Performance Limit Reasons */ + + __u16 param; +/* When index is PECI_MBX_INDEX_CPU_ID */ +#define PECI_PKG_ID_CPU_ID 0x0000 /* CPUID Info */ +#define PECI_PKG_POWER_SKU_UNIT 0x0000 /* Time, Energy, Power units */ +#define PECI_PKG_ID_PLATFORM_ID 0x0001 /* Platform ID */ +#define PECI_PKG_ID_UNCORE_ID 0x0002 /* Uncore Device ID */ +#define PECI_PKG_ID_MAX_THREAD_ID 0x0003 /* Max Thread ID */ +#define PECI_PKG_ID_MICROCODE_REV 0x0004 /* CPU Microcode Update Revision */ +#define PECI_PKG_ID_MACHINE_CHECK_STATUS 0x0005 /* Machine Check Status */ +#define PECI_PKG_ID_CPU_PACKAGE 0x00ff /* CPU package ID*/ +#define PECI_PKG_ID_DIMM 0x00ff /* DIMM ID*/ +#define PECI_PKG_ID_PLATFORM 0x00fe /* Entire platform ID */ + + __u8 rx_len; + __u8 cc; + __u8 padding[2]; + __u8 pkg_config[4]; + __u8 domain_id; + __u8 padding1[3]; +} __attribute__((__packed__)); + +/** + * struct peci_wr_pkg_cfg_msg - WrPkgConfig command + * @addr: address of the client + * @index: encoding index for the requested service + * @param: specific data being requested + * @tx_len: number of data to be written in bytes + * @cc: completion code + * @value: package config data to be written + * @domain_id: domain ID of the client + * + * The WrPkgConfig() command provides write access to the Package Configuration + * Space (PCS) within the processor, including various power and thermal + * management functions. Typical PCS write services supported by the processor + * may include power limiting, thermal averaging constant programming and so + * on. + */ +struct peci_wr_pkg_cfg_msg { +#define PECI_WRPKGCFG_WRITE_LEN_BASE 6 +#define PECI_WRPKGCFG_READ_LEN 1 +#define PECI_WRPKGCFG_CMD 0xa5 + + __u8 addr; + __u8 index; +#define PECI_MBX_INDEX_DIMM_AMBIENT 19 +#define PECI_MBX_INDEX_DIMM_TEMP 24 + + __u16 param; + __u8 tx_len; + __u8 cc; + __u8 padding[2]; + __u32 value; + __u8 domain_id; + __u8 padding1[3]; +} __attribute__((__packed__)); + +/** + * struct peci_rd_ia_msr_msg - RdIAMSR command + * @addr: address of the client + * @thread_id: ID of the specific logical processor + * @address: address of MSR to read from + * @cc: completion code + * @value: data to be read + * @domain_id: domain ID of the client + * + * The RdIAMSR() PECI command provides read access to Model Specific Registers + * (MSRs) defined in the processor's Intel Architecture (IA). + */ +struct peci_rd_ia_msr_msg { +#define PECI_RDIAMSR_WRITE_LEN 5 +#define PECI_RDIAMSR_READ_LEN 9 +#define PECI_RDIAMSR_CMD 0xb1 + + __u8 addr; + __u8 thread_id; + __u16 address; + __u8 cc; + __u8 padding[3]; + __u64 value; + __u8 domain_id; + __u8 padding1[3]; +} __attribute__((__packed__)); + +/** + * struct peci_wr_ia_msr_msg - WrIAMSR command + * @addr: address of the client + * @thread_id: ID of the specific logical processor + * @address: address of MSR to write to + * @tx_len: number of data to be written in bytes + * @cc: completion code + * @value: data to be written + * @domain_id: domain ID of the client + * + * The WrIAMSR() PECI command provides write access to Model Specific Registers + * (MSRs) defined in the processor's Intel Architecture (IA). + */ +struct peci_wr_ia_msr_msg { +#define PECI_WRIAMSR_CMD 0xb5 + + __u8 addr; + __u8 thread_id; + __u16 address; + __u8 tx_len; + __u8 cc; + __u8 padding[2]; + __u64 value; + __u8 domain_id; + __u8 padding1[3]; +} __attribute__((__packed__)); + +/** + * struct peci_rd_ia_msrex_msg - RdIAMSREX command + * @addr: address of the client + * @thread_id: ID of the specific logical processor + * @address: address of MSR to read from + * @cc: completion code + * @value: data to be read + * @domain_id: domain ID of the client + * + * The RdIAMSREX() PECI command provides read access to Model Specific + * Registers (MSRs) defined in the processor's Intel Architecture (IA). + * The differences between RdIAMSREX() and RdIAMSR() are that: + * (1)RdIAMSR() can only read MC registers, RdIAMSREX() can read all MSRs + * (2)thread_id of RdIAMSR() is u8, thread_id of RdIAMSREX() is u16 + */ +struct peci_rd_ia_msrex_msg { +#define PECI_RDIAMSREX_WRITE_LEN 6 +#define PECI_RDIAMSREX_READ_LEN 9 +#define PECI_RDIAMSREX_CMD 0xd1 + + __u8 addr; + __u8 padding0; + __u16 thread_id; + __u16 address; + __u8 cc; + __u8 padding1; + __u64 value; + __u8 domain_id; + __u8 padding2[3]; +} __attribute__((__packed__)); + +/** + * struct peci_rd_pci_cfg_msg - RdPCIConfig command + * @addr: address of the client + * @bus: PCI bus number + * @device: PCI device number + * @function: specific function to read from + * @reg: specific register to read from + * @cc: completion code + * @pci_config: config data to be read + * @domain_id: domain ID of the client + * + * The RdPCIConfig() command provides sideband read access to the PCI + * configuration space maintained in downstream devices external to the + * processor. + */ +struct peci_rd_pci_cfg_msg { +#define PECI_RDPCICFG_WRITE_LEN 6 +#define PECI_RDPCICFG_READ_LEN 5 +#define PECI_RDPCICFG_READ_LEN_MAX 24 +#define PECI_RDPCICFG_CMD 0x61 + + __u8 addr; + __u8 bus; +#define PECI_PCI_BUS0_CPU0 0x00 +#define PECI_PCI_BUS0_CPU1 0x80 +#define PECI_PCI_CPUBUSNO_BUS 0x00 +#define PECI_PCI_CPUBUSNO_DEV 0x08 +#define PECI_PCI_CPUBUSNO_FUNC 0x02 +#define PECI_PCI_CPUBUSNO 0xcc +#define PECI_PCI_CPUBUSNO_1 0xd0 +#define PECI_PCI_CPUBUSNO_VALID 0xd4 + + __u8 device; + __u8 function; + __u16 reg; + __u8 cc; + __u8 padding[1]; + __u8 pci_config[4]; + __u8 domain_id; + __u8 padding1[3]; +} __attribute__((__packed__)); + +/** + * struct peci_wr_pci_cfg_msg - WrPCIConfig command + * @addr: address of the client + * @bus: PCI bus number + * @device: PCI device number + * @function: specific function to write to + * @reg: specific register to write to + * @tx_len: number of data to be written in bytes + * @cc: completion code + * @pci_config: config data to be written + * @domain_id: domain ID of the client + * + * The RdPCIConfig() command provides sideband write access to the PCI + * configuration space maintained in downstream devices external to the + * processor. + */ +struct peci_wr_pci_cfg_msg { +#define PECI_WRPCICFG_CMD 0x65 + + __u8 addr; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + __u8 tx_len; + __u8 cc; + __u8 pci_config[4]; + __u8 domain_id; + __u8 padding[3]; +} __attribute__((__packed__)); + +/** + * struct peci_rd_pci_cfg_local_msg - RdPCIConfigLocal command + * @addr: address of the client + * @bus: PCI bus number + * @device: PCI device number + * @function: specific function to read from + * @reg: specific register to read from + * @rx_len: number of data to be read in bytes + * @cc: completion code + * @pci_config: config data to be read + * @domain_id: domain ID of the client + * + * The RdPCIConfigLocal() command provides sideband read access to the PCI + * configuration space that resides within the processor. This includes all + * processor IIO and uncore registers within the PCI configuration space. + */ +struct peci_rd_pci_cfg_local_msg { +#define PECI_RDPCICFGLOCAL_WRITE_LEN 5 +#define PECI_RDPCICFGLOCAL_READ_LEN_BASE 1 +#define PECI_RDPCICFGLOCAL_CMD 0xe1 + + __u8 addr; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + __u8 rx_len; + __u8 cc; + __u8 pci_config[4]; + __u8 domain_id; + __u8 padding[3]; +} __attribute__((__packed__)); + +/** + * struct peci_wr_pci_cfg_local_msg - WrPCIConfigLocal command + * @addr: address of the client + * @bus: PCI bus number + * @device: PCI device number + * @function: specific function to read from + * @reg: specific register to read from + * @tx_len: number of data to be written in bytes + * @cc: completion code + * @value: config data to be written + * @domain_id: domain ID of the client + * + * The WrPCIConfigLocal() command provides sideband write access to the PCI + * configuration space that resides within the processor. PECI originators can + * access this space even before BIOS enumeration of the system buses. + */ +struct peci_wr_pci_cfg_local_msg { +#define PECI_WRPCICFGLOCAL_WRITE_LEN_BASE 6 +#define PECI_WRPCICFGLOCAL_READ_LEN 1 +#define PECI_WRPCICFGLOCAL_CMD 0xe5 + + __u8 addr; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + __u8 tx_len; + __u8 cc; + __u32 value; + __u8 domain_id; + __u8 padding[3]; +} __attribute__((__packed__)); + +struct peci_rd_end_pt_cfg_msg { +#define PECI_RDENDPTCFG_PCI_WRITE_LEN 12 +#define PECI_RDENDPTCFG_MMIO_D_WRITE_LEN 14 +#define PECI_RDENDPTCFG_MMIO_Q_WRITE_LEN 18 +#define PECI_RDENDPTCFG_READ_LEN_BASE 1 +#define PECI_RDENDPTCFG_CMD 0xc1 + + __u8 addr; + __u8 msg_type; +#define PECI_ENDPTCFG_TYPE_LOCAL_PCI 0x03 +#define PECI_ENDPTCFG_TYPE_PCI 0x04 +#define PECI_ENDPTCFG_TYPE_MMIO 0x05 + + union { + struct { + __u8 seg; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + } pci_cfg; + struct { + __u8 seg; + __u8 bus; + __u8 device; + __u8 function; + __u8 bar; + __u8 addr_type; +#define PECI_ENDPTCFG_ADDR_TYPE_PCI 0x04 +#define PECI_ENDPTCFG_ADDR_TYPE_MMIO_D 0x05 +#define PECI_ENDPTCFG_ADDR_TYPE_MMIO_Q 0x06 + + __u64 offset; + } mmio; + } params; + __u8 rx_len; + __u8 cc; + __u8 padding[2]; + __u8 data[8]; + __u8 domain_id; + __u8 padding1[3]; +} __attribute__((__packed__)); + +struct peci_wr_end_pt_cfg_msg { +#define PECI_WRENDPTCFG_PCI_WRITE_LEN_BASE 13 +#define PECI_WRENDPTCFG_MMIO_D_WRITE_LEN_BASE 15 +#define PECI_WRENDPTCFG_MMIO_Q_WRITE_LEN_BASE 19 +#define PECI_WRENDPTCFG_READ_LEN 1 +#define PECI_WRENDPTCFG_CMD 0xc5 + + __u8 addr; + __u8 msg_type; + /* See msg_type in struct peci_rd_end_pt_cfg_msg */ + + union { + struct { + __u8 seg; + __u8 bus; + __u8 device; + __u8 function; + __u16 reg; + } pci_cfg; + struct { + __u8 seg; + __u8 bus; + __u8 device; + __u8 function; + __u8 bar; + __u8 addr_type; + /* See addr_type in struct peci_rd_end_pt_cfg_msg */ + + __u64 offset; + } mmio; + } params; + __u8 tx_len; + __u8 cc; + __u8 padding[2]; + __u64 value; + __u8 domain_id; + __u8 padding1[3]; +} __attribute__((__packed__)); + +/* Crashdump Agent */ +#define PECI_CRASHDUMP_CORE 0x00 +#define PECI_CRASHDUMP_TOR 0x01 + +/* Crashdump Agent Param */ +#define PECI_CRASHDUMP_PAYLOAD_SIZE 0x00 + +/* Crashdump Agent Data Param */ +#define PECI_CRASHDUMP_AGENT_ID 0x00 +#define PECI_CRASHDUMP_AGENT_PARAM 0x01 + +struct peci_crashdump_disc_msg { + __u8 addr; + __u8 subopcode; +#define PECI_CRASHDUMP_ENABLED 0x00 +#define PECI_CRASHDUMP_NUM_AGENTS 0x01 +#define PECI_CRASHDUMP_AGENT_DATA 0x02 + + __u8 cc; + __u8 param0; + __u16 param1; + __u8 param2; + __u8 rx_len; + __u8 data[8]; + __u8 domain_id; + __u8 padding[3]; +} __attribute__((__packed__)); + +struct peci_crashdump_get_frame_msg { +#define PECI_CRASHDUMP_DISC_WRITE_LEN 9 +#define PECI_CRASHDUMP_DISC_READ_LEN_BASE 1 +#define PECI_CRASHDUMP_DISC_VERSION 0 +#define PECI_CRASHDUMP_DISC_OPCODE 1 +#define PECI_CRASHDUMP_GET_FRAME_WRITE_LEN 10 +#define PECI_CRASHDUMP_GET_FRAME_READ_LEN_BASE 1 +#define PECI_CRASHDUMP_GET_FRAME_VERSION 0 +#define PECI_CRASHDUMP_GET_FRAME_OPCODE 3 +#define PECI_CRASHDUMP_CMD 0x71 + + __u8 addr; + __u8 padding0; + __u16 param0; + __u16 param1; + __u16 param2; + __u8 rx_len; + __u8 cc; + __u8 padding1[2]; + __u8 data[16]; + __u8 domain_id; + __u8 padding2[3]; +} __attribute__((__packed__)); + +#define PECI_IOC_BASE 0xb8 + +#define PECI_IOC_XFER \ + _IOWR(PECI_IOC_BASE, PECI_CMD_XFER, struct peci_xfer_msg) + +#define PECI_IOC_PING \ + _IOWR(PECI_IOC_BASE, PECI_CMD_PING, struct peci_ping_msg) + +#define PECI_IOC_GET_DIB \ + _IOWR(PECI_IOC_BASE, PECI_CMD_GET_DIB, struct peci_get_dib_msg) + +#define PECI_IOC_GET_TEMP \ + _IOWR(PECI_IOC_BASE, PECI_CMD_GET_TEMP, struct peci_get_temp_msg) + +#define PECI_IOC_RD_PKG_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PKG_CFG, struct peci_rd_pkg_cfg_msg) + +#define PECI_IOC_WR_PKG_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PKG_CFG, struct peci_wr_pkg_cfg_msg) + +#define PECI_IOC_RD_IA_MSR \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSR, struct peci_rd_ia_msr_msg) + +#define PECI_IOC_WR_IA_MSR \ + _IOWR(PECI_IOC_BASE, PECI_CMD_WR_IA_MSR, struct peci_wr_ia_msr_msg) + +#define PECI_IOC_RD_IA_MSREX \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_IA_MSREX, struct peci_rd_ia_msrex_msg) + +#define PECI_IOC_RD_PCI_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG, struct peci_rd_pci_cfg_msg) + +#define PECI_IOC_WR_PCI_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG, struct peci_wr_pci_cfg_msg) + +#define PECI_IOC_RD_PCI_CFG_LOCAL \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_PCI_CFG_LOCAL, \ + struct peci_rd_pci_cfg_local_msg) + +#define PECI_IOC_WR_PCI_CFG_LOCAL \ + _IOWR(PECI_IOC_BASE, PECI_CMD_WR_PCI_CFG_LOCAL, \ + struct peci_wr_pci_cfg_local_msg) + +#define PECI_IOC_RD_END_PT_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_RD_END_PT_CFG, \ + struct peci_rd_end_pt_cfg_msg) + +#define PECI_IOC_WR_END_PT_CFG \ + _IOWR(PECI_IOC_BASE, PECI_CMD_WR_END_PT_CFG, \ + struct peci_wr_end_pt_cfg_msg) + +#define PECI_IOC_CRASHDUMP_DISC \ + _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_DISC, \ + struct peci_crashdump_disc_msg) + +#define PECI_IOC_CRASHDUMP_GET_FRAME \ + _IOWR(PECI_IOC_BASE, PECI_CMD_CRASHDUMP_GET_FRAME, \ + struct peci_crashdump_get_frame_msg) + +#endif /* __PECI_IOCTL_H */ |