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2018-05-30ARM: dts: aspeed: Fix hwrng register addressdev-4.13Joel Stanley2-4/+4
The register address should be the full address of the rng, not the offset from the start of the SCU. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-30hwmon: occ: Properly initialize sysfs attributesBenjamin Herrenschmidt1-1/+3
Otherwise, lockdep will complain OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-30hwmon: occ: Avoid displaying an error when host is downBenjamin Herrenschmidt1-1/+4
Instead display a much less scary informational message as this can happen in normal circumstances. OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-30hwmon: occ: Display info about the OCC code level and sensors foundBenjamin Herrenschmidt1-1/+11
OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/scom: Fixup endian annotationsBenjamin Herrenschmidt1-5/+4
Use the proper annotated type __be32 and fixup the accessor used for get_scom() OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/scom: Whitespace fixesBenjamin Herrenschmidt1-4/+4
No functional changes OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/scom: Add mutex around FSI2PIB accessesBenjamin Herrenschmidt1-7/+18
Otherwise, multiple clients can open the driver and attempt to access the PIB at the same time, thus clobbering each other in the process. OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi: scom: Remove PIB reset during probeEddie James1-8/+0
The PIB reset causes problems for the running P9 chip. The reset shouldn't be performed by this driver. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25hwmon/occ: Silence probe error message when host is shutdownBenjamin Herrenschmidt1-1/+7
OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/occ: Don't set driver data lateBenjamin Herrenschmidt1-2/+2
Until now, the OCC driver was setting the driver data after registering the character device and the hwmon device. This might have been intentional, as doing so makes the initial probe of the OCC by the hwmon device fail while the data is NULL (provided you are lucky and the hwmon driver doesn't get bound asynchronously). That failure used to be necessary, otherwise the driver would try to access the SBE fifo at a time when it's not ready, causing all sort of problems. The new SBE fifo driver is much more robust and will return an appropriate error code, so that (fragile) tweak is no longer necessary. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/fsi-occ: Simple conversion to new sbefifo driverBenjamin Herrenschmidt3-114/+99
Replace open/close/write/read API with the simple submit() API and the helper to parse status. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/sbefifo: Add driver for the SBE FIFOBenjamin Herrenschmidt3-1/+1041
This driver provides an in-kernel and a user API for accessing the command FIFO of the SBE (Self Boot Engine) of the POWER9 processor, via the FSI bus. It provides an in-kernel interface to submit command and receive responses, along with a helper to locate and analyse the response status block. It's a simple synchronous submit() type API. The user interface uses the write/read interface that an earlier version of this driver already provided, however it has some specific limitations in order to keep the driver simple and avoid using up a lot of kernel memory: - The user should perform a single write() with the command and a single read() to get the response (with a buffer big enough to hold the entire response). - On a write() the command is simply "stored" into a kernel buffer, it is submitted as one operation on the subsequent read(). This allows to have the code write directly from the FIFO into the user buffer and avoid hogging the SBE between the write() and read() syscall as it's critical that the SBE be freed asap to respond to the host. An extra write() will simply replace the previously written command. - A write of a single 4 bytes containing the value 0x52534554 in big endian will trigger a reset request. No read is necessary, the write() call will return when the reset has been acknowledged or times out. - The command is limited to 4K bytes. OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi: Remove old sbefifo driverBenjamin Herrenschmidt4-1104/+3
And remporarily disable build of fsi-occ OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/master-gpio: Replace bit_bit lock with IRQ disable/enableJeremy Kerr1-25/+23
We currently use a spinlock (bit_lock) around operations that clock bits out of the FSI bus, and a mutex to protect against simultaneous access to the master. This means that bit_lock isn't needed for mutual exlusion, only to prevent timing issues when clocking bits out. To reflect this, this change converts bit_lock to just the local_irq_save/restore operation. OpenBMC-Staging-Count: 1 Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/fsi-master-gpio: More error handling cleanupBenjamin Herrenschmidt1-21/+5
Remove calls to the empty and useless fsi_master_gpio_error() function, and report CRC errors as "FSI_ERR_NO_SLAVE" when reading an all 1's response. OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/fsi-master-gpio: Implement CRC error recoveryBenjamin Herrenschmidt2-18/+99
The FSI protocol defines two modes of recovery from CRC errors, this implements both: - If the device returns an ECRC (it detected a CRC error in the command), then we simply issue the command again. - If the master detects a CRC error in the response, we send an E_POLL command which requests a resend of the response without actually re-executing the command (which could otherwise have unwanted side effects such as dequeuing a FIFO twice). OpenBMC-Staging-Count: 1 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/gpio: Use relative-addressing commandsJeremy Kerr1-11/+91
FSI CFAMs support shorter commands that use a relative (or same) address as the last. This change introduces a last_addr to the master state, and uses it for subsequent reads/writes, and performs relative addressing when a subsequent read/write is in range. OpenBMC-Staging-Count: 1 Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-25fsi/gpio: Include command build in locked sectionJeremy Kerr1-7/+18
For implementing relative addressing mode, we'll need to build a command that is coherent with CFAM state. To do that, include the build_command_* functions in the locked section of read/write/term. OpenBMC-Staging-Count: 1 Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18ipmi: NPCM7xx KCS BMC: enable interrupt to the hostAvi Fishman1-4/+16
Original kcs_bmc_npcm7xx.c was missing enabling to send interrupt to the host on writes to output buffer. This patch fixes it by setting the bits that enables the generation of IRQn events by hardware control based on the status of the OBF flag. OpenBMC-Staging-Count: 1 Signed-off-by: Avi Fishman <AviFishman70@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18ipmi: kcs_bmc: coding-style fixesHaiyue Wang4-36/+43
OpenBMC-Staging-Count: 1 Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> [This is is not the same commit as upstream, as the changes to use new type '__poll_t' from linux-4.16-rc1 are not included. This was done because the feature is not a small self contained backport. There is no impact on functionality for dev-4.13] Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18ipmi: add an NPCM7xx KCS BMC driverHaiyue Wang4-0/+259
This driver exposes the Keyboard Controller Style (KCS) interface on Novoton NPCM7xx SoCs as a character device. Such SOCs are commonly used as a BaseBoard Management Controller (BMC) on a server board, and KCS interface is commonly used to perform the in-band IPMI communication between the server and its BMC. OpenBMC-Staging-Count: 1 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18ipmi: add an Aspeed KCS IPMI BMC driverHaiyue Wang4-0/+357
The KCS (Keyboard Controller Style) interface is used to perform in-band IPMI communication between a server host and its BMC (BaseBoard Management Controllers). This driver exposes the KCS interface on ASpeed SOCs (AST2400 and AST2500) as a character device. Such SOCs are commonly used as BMCs and this driver implements the BMC side of the KCS interface. OpenBMC-Staging-Count: 1 Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18ipmi: add a KCS IPMI BMC driverHaiyue Wang5-0/+588
Provides a device driver for the KCS (Keyboard Controller Style) IPMI interface which meets the requirement of the BMC (Baseboard Management Controllers) side for handling the IPMI request from host system software. Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com> [Removed the selectability of IPMI_KCS_BMC, as it doesn't do much good to have it by itself.] Signed-off-by: Corey Minyard <cminyard@mvista.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18clk: npcm7xx: fix return value check in npcm7xx_clk_init()Wei Yongjun1-1/+1
In case of error, the function ioremap() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. OpenBMC-Staging-Count: 1 Fixes: fcfd14369856 ("clk: npcm7xx: add clock controller") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18pinctrl: npcm: add NPCM7xx pin control driverTomer Maimon5-0/+2149
Add Nuvoton BMC NPCM7xx pin controller driver. The NPCM7XX Pin Controller multi-function routed through the multiplexing block, Each pin supports GPIO functionality (GPIOx) and multiple functions that directly connect the pin to different hardware blocks. OpenBMC-Staging-Count: 1 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [Joel: - changed depend to select for MFD_SYSCON to fix kconfig warn - Fixed unintialised variable warning in npcm_set_drive_strength] Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18dt-binding: pinctrl: document NPCM7xx pin controller DT bindingsTomer Maimon1-0/+70
Added device tree binding documentation for Nuvoton NPCM7xx pin controller OpenBMC-Staging-Count: 1 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18ARM: dts: aspeed: Use 24MHz fixed clock for pwmLei YU2-2/+2
The aspeed pwm driver always sets the clock source to 24MHz, specify the fixed clock in device tree to make sure the driver is using the correct clock frequency to calculate the fan speed. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-18clk: aspeed: Add 24MHz fixed clockLei YU2-1/+8
Add a 24MHz fixed clock that is provided by the input oscillator. This clock will be used for certain devices, e.g. pwm. OpenBMC-Staging-Count: 1 Signed-off-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-17hwmon: (pmbus) Use 64bit math for DIRECT format valuesRobert Lippert1-9/+12
Power values in the 100s of watt range can easily blow past 32bit math limits when processing everything in microwatts. Use 64bit math instead to avoid these issues on common 32bit ARM BMC platforms. Fixes: 442aba78728e ("hwmon: PMBus device driver") Signed-off-by: Robert Lippert <rlippert@google.com> Signed-off-by: Guenter Roeck <linux@roeck-us.net> (cherry picked from commit bd467e4eababe4c04272c1e646f066db02734c79) Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-17fsi/fsi-master-gpio: Delay sampling of FSI data inputBenjamin Herrenschmidt1-0/+5
Most SoC GPIO implementations, including the Aspeed one, have synchronizers on the GPIO inputs. This means that the value read from a GPIO is a couple of clocks old, from whatever clock source feeds those synchronizers. In practice, this means that in no-delay mode, we are using a value that can potentially be a bit too old and too close to the clock edge establishing the data on the other side of the link. The voltage converters we use on some systems make this worse and sensitive to things like voltage fluctuations etc... This is, we believe, the cause of occasional CRC errors encountered during heavy activity on the LPC bus. This is fixed by introducing a dummy GPIO read before the actual data read. It slows down SBEFIFO by about 15% (less than any delay primitive) and the end result is so far solid. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11fsi/fsi-master-gpio: Reduce dpoll clocksBenjamin Herrenschmidt1-2/+3
FSI_GPIO_DPOLL_CLOCKS is the number of clocks before sending a DPOLL command after receiving a BUSY status. It should be at least tSendDelay (16 clocks). According to comments in the code, it needs to also be at least 21 clocks due to HW issues. It's currently 100 clocks which impacts performances negatively in some cases. Reduces it in half to 50 clocks which seems to still be solid. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11fsi/fsi-master-gpio: Reduce turnaround clocksBenjamin Herrenschmidt1-1/+1
FSI_GPIO_PRIME_SLAVE_CLOCKS is the number of clocks if the "idle" phase between the end of a response and the beginning of the next one. It corresponds to tSendDelay in the FSI specification. The default value in the slave is 16 clocks. 100 is way overkill and significantly reduces the driver performance. This changes it to 20 (which gives the HW a bit of margin still just in case). Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11fsi/fsi-master-gpio: Add "no-gpio-delays" optionBenjamin Herrenschmidt4-4/+19
This adds support for an optional device-tree property that makes the driver skip all the delays around clocking the GPIOs and set it in the device-tree of common POWER9 based OpenPower platforms. This useful on chips like the AST2500 where the GPIO block is running at a fairly low clock frequency (25Mhz typically). In this case, the delays are unnecessary and due to the low precision of the timers, actually quite harmful in terms of performance. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11fsi/fsi-master-gpio: Sample input data on different clock phaseBenjamin Herrenschmidt1-3/+5
We currently sample the input data right after we toggle the clock low, then high. The slave establishes the data on the rising edge, so this is not ideal. We should sample it on the low phase instead. This currently works because we have an extra delay, but subsequent patches will remove it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11gpio/aspeed: Use a cache of output data registersBenjamin Herrenschmidt1-2/+19
The current driver does a read/modify/write of the output registers when changing a bit in __aspeed_gpio_set(). This is sub-optimal for a couple of reasons: - If any of the neighbouring GPIOs (sharing the shared register) isn't (yet) configured as an output, it will read the current input value, and then apply it to the output latch, which may not be what the user expects. There should be no bug in practice as aspeed_gpio_dir_out() will establish a new value but it's not great either. - The GPIO block in the aspeed chip is clocked rather slowly (typically 25Mhz). That extra MMIO read halves the maximum speed at which we can toggle the GPIO. This provides a significant performance improvement to the GPIO based FSI master. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11gpio/aspeed: Set output latch before changing directionBenjamin Herrenschmidt1-2/+1
In aspeed_gpio_dir_out(), we need to establish the new output value in the output latch *before* we change the direction to output in order to avoid a glitch on the output line if the previous value of the latch was different. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-11ARM: dts: aspeed-g5: Clean up sio registersJoel Stanley1-19/+18
Remove the unnecessary reg property. Drop the 'rx' in the name, as this refers to a quirk in the datasheet and is not useful. Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-07ARM: configs: aspeed: Add watchdog sysfsEddie James2-0/+2
This kernel config adds sysfs entries for watchdog devices. This is needed in order to access the bootstatus sysfs file that will indicate whether or not the BMC has tripped the watchdog and subsequently switched sides. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-07fsi: occ: Add check for OCC response checksumEddie James1-2/+24
The OCC specification indicates that it is an error scenario if the response checksum doesn't match the sum of the bytes of the response. The driver needs to perform this calculation and check, and return an error if it's a mismatch. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-07ARM: dts: aspeed: Move random number deviceJoel Stanley2-12/+12
Move the node out from under the syscon/simple-mfd. Being a child of this node causes the driver to fail to probe, as platform_get_resource returns NULL due to dev->num_resources being zero. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-01fsi: occ: Use PutOCCSRAM in circular mode for OCC attentionAndrew Jeffery1-13/+9
We can't do SCOMs from the BMC when the host is booted in secure mode, and without triggering the attention of the OCC our commands won't be processed. Further, the SCOM operation fails, which causes the OCC driver's probe to fail, which leads the BMC to think that the OCC has failed. We have an alternative to the SCOM though: We can trigger the OCC by writing the correct attention magic in circular buffer mode. The PutOCCSRAM operation returns the written data length in the response payload before the 0xCODE word, so the condition testing the success of the operation is rearranged. OpenBMC-Staging-Count: 1 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Matt Spinler mspinler@linux.vnet.ibm.com Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-05-01ARM: dts: romulus: Enable the GFX IPJoel Stanley1-0/+12
The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and enables the GFX node. OpenBMC-Staging-Count: 1 Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-26ARM: dts: aspeed: Add Inventec Lanyang BMCBrian Yang2-0/+332
The Inventec Lanyang is Power 9 platform with ast2500 BMC. Tested-by: Brian Yang <yang.brianc.w@inventec.com> Signed-off-by: Brian Yang <yang.brianc.w@inventec.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-26ARM: dts: aspeed: Add Portwell Neptune machineAmithash Prasad3-1/+162
Initial introduction of Portwell Neptune family equipped with Aspeed 2500 BMC SoC. Neptune is a x86 server development kit with a ASPEED ast2500 BMC manufactured by Portwell. Specifically, This adds the neptune platform device tree file including the flash layout used by the neptune machines. Signed-off-by: Amithash Prasad <amithash@fb.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-26clk: aspeed: Fix reset assert logicJae Hyun Yoo1-1/+1
This commit fixes a bug in aspeed_reset_assert() which determines the second reset register using condition. OpenBMC-Staging-Count: 1 Fixes: 9e3efb97c78f ("clk: aspeed: Support second reset register") Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: aspeed-g5: Add DAC MUX userspace controlJoel Stanley1-2/+6
This exposes SCU2C "Misc. Control Register" bits 16 and 17 which control the input to the VGA DAC. They are used to select which graphics device drives the analog output: 00: VGA mode (default) 01: Graphics CRT mode 10: Pass-through mode from Video input port-A 11: Pass-through mode from Video input port-B We don't need the reg property, so remove it and the unit name. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: witherspoon: Enable the GFX IPJoel Stanley1-0/+8
The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: ast2500-evb: Enable the GFX IPJoel Stanley1-1/+20
The GFX controller is the internal graphics device used by the SoC (opposed to the one connected via the PCIe device and used by the host). This configures it with a framebuffer region and adds it to the command line so kernel boot messages appear on the display. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20ARM: dts: aspeed-g5: Add resets and clocks to GFX nodeJoel Stanley1-0/+4
The ast2500 has a reset for the CRT device that must be deasserted before it can be used. Similarly it has a clock gate for a clock called D1CLK that must be set to running. OpenBMC-Staging-Count: 1 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2018-04-20drm: aspeed: Debugfs interface for GFX registersJoel Stanley4-0/+83
This exposes the GFX registers in debugfs for debugging. The idea is borrowed from the Broadcom driver. OpenBMC-Staging-Count: 1 Signed-off-by: Joel Stanley <joel@jms.id.au>
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