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2021-11-04hwmon: (nct7802) Make temperature/voltage sensors configurableOskar Senft1-4/+125
This change allows LTD and RTD inputs to be configured via device tree bindings. If the DT bindings are not present or invalid, the input configuration is not modified and left at HW defaults. OpenBMC-Staging-Count: 1 Signed-off-by: Oskar Senft <osk@google.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20211020164213.174597-2-osk@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-04dt-bindings: hwmon: Add nct7802 bindingsOskar Senft1-0/+145
This change documents the device tree bindings for the Nuvoton NCT7802Y driver. OpenBMC-Staging-Count: 1 Signed-off-by: Oskar Senft <osk@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211020164213.174597-1-osk@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-03soc: aspeed: Fix UART routing driverChia-Wei Wang2-4/+15
The build changes relating to the routing driver were lost when backporting. Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-02soc: aspeed: Add UART routing supportChia-Wei Wang1-0/+603
Add driver support for the UART routing control. Users can perform runtime configuration of the RX muxes among the UART controllers and the UART IO pins. The sysfs interface is also exported for the convenience of routing paths check and update. Signed-off-by: Oskar Senft <osk@google.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Lei YU <yulei.sh@bytedance.com> Link: https://lore.kernel.org/r/20210927023053.6728-5-chiawei_wang@aspeedtech.com Link: https://lore.kernel.org/r/20211022000616.481772-1-joel@jms.id.au' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-11-01spi: fsi: Fix contention in the FSI2SPI engineEddie James1-22/+53
There was nothing to protect multiple SPI controllers on the same FSI2SPI device from being accessed through the FSI2SPI device at the same time. For example, multiple writes to the command and data registers might occur for different SPI controllers, resulting in complete chaos in the SPI engine. To prevent this, add a FSI2SPI device level mutex and lock it in the SPI register read and write functions. OpenBMC-Staging-Count: 1 Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver") Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20211026193327.52420-1-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: nuvoton: gbs: Change the name of the partitionsGeorge Hung1-10/+10
Change the name of the partitions for BIOS primary and secondary SPI EEPROMs. OpenBMC-Staging-Count: 2 Signed-off-by: George Hung <george.hung@quantatw.com> Link: https://lore.kernel.org/r/20211026054904.8888-1-george.hung@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01spi: fsi: Print status on errorEddie James1-21/+27
Print the SPI engine status register when an error is detected. This will aid tremendously in debugging failed transactions. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20211004195149.29759-1-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ipmi: bt-bmc: Use registers directlyJoel Stanley1-52/+16
This driver was originally written to use the regmap abstraction with no clear benefit. As the registers are always mmio and there is no sharing of the region with other devices, we can safely read and write without the locking that regmap provides. This reduces the code size of the driver by about 25%. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210903051039.307991-1-joel@jms.id.au> Signed-off-by: Corey Minyard <cminyard@mvista.com>
2021-11-01ARM: dts: nuvoton: gbs: split SPI flash partitionGeorge Hung1-0/+27
Split the primary and secondary BIOS SPI EEPROMs in 2 partitions OpenBMC-Staging-Count: 2 Signed-off-by: George Hung <george.hung@quantatw.com> Link: https://lore.kernel.org/r/20211008053006.31961-1-george.hung@quantatw.com
2021-11-01leds: pca955x: Allow zero LEDs to be specifiedAndrew Jeffery1-1/+1
It's valid to use the PCA955x devices just for GPIOs and not for LEDs. In this case, as PCA955X_TYPE_GPIO is now equivalent to PCA955X_TYPE_NONE, remove the test for whether we have any child nodes specified in the devicetree. A consequence of this is it's now possible to bind the driver to a PCA955x device when dynamically instantiated through the I2C subsystem's `new_device` interface. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210921043936.468001-3-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01leds: pca955x: Make the gpiochip always expose all pinsAndrew Jeffery1-31/+34
The devicetree binding allows specifying which pins are GPIO vs LED. Limiting the instantiated gpiochip to just these pins as the driver currently does requires an arbitrary mapping between pins and GPIOs, but such a mapping is not implemented by the driver. As a result, specifying GPIOs in such a way that they don't map 1-to-1 to pin indexes does not function as expected. Establishing such a mapping is more complex than not and even if we did, doing so leads to a slightly hairy userspace experience as the behaviour of the PCA955x gpiochip would depend on how the pins are assigned in the devicetree. Instead, always expose all pins via the gpiochip to provide a stable interface and track which pins are in use. Specifying a pin as `type = <PCA955X_TYPE_GPIO>;` in the devicetree becomes a no-op. I've assessed the impact of this change by looking through all of the affected devicetrees as of the tag leds-5.15-rc1: ``` $ git grep -l 'pca955[0123]' $(find . -name dts -type d) arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts arch/arm/boot/dts/aspeed-bmc-opp-swift.dts arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts ``` These are all IBM-associated platforms. I've analysed both the devicetrees and schematics where necessary to determine whether any systems hit the hazard of the current broken behaviour. For the most part, the systems specify the pins as either all LEDs or all GPIOs, or at least do so in a way such that the broken behaviour isn't exposed. The main counter-point to this observation is the Everest system whose devicetree describes a large number of PCA955x devices and in some cases has pin assignments that hit the hazard. However, there does not seem to be any use of the affected GPIOs in the userspace associated with Everest. Regardless, any use of the hazardous GPIOs in Everest is already broken, so let's fix the interface and then fix any already broken userspace with it. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210921043936.468001-2-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: configs: aspeed: Add openbmc kernel optionsJoel Stanley2-2/+37
Enable sensors and other drivers used by OpenBMC systems. Turn on some options to help debugging and testing. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: tacoma: Clean up KCS nodesAndrew Jeffery1-0/+11
Make the Tacoma KCS nodes reflect the configuration of the Rainier and Everest nodes. OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210709151119.2683600-1-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: ast2600evb: Enable EHCI controllerJoel Stanley1-0/+8
OpenBMC-Staging-Count: 3 Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ipmi: kcs_bmc: Add a "raw" character device interfaceAndrew Jeffery4-0/+490
The existing IPMI chardev encodes IPMI behaviours as the name suggests. However, KCS devices are useful beyond IPMI (or keyboards), as they provide a means to generate IRQs and exchange arbitrary data between a BMC and its host system. Implement a "raw" KCS character device that exposes the IDR, ODR and STR registers to userspace via read() and write() implemented on a character device: +--------+--------+---------+ | Offset | read() | write() | +--------+--------+---------+ | 0 | IDR | ODR | +--------+--------+---------+ | 1 | STR | STR | +--------+--------+---------+ This interface allows userspace to implement arbitrary (though somewhat inefficient) protocols for exchanging information between a BMC and host firmware. Conceptually the KCS interface can be used as an out-of-band mechanism for interrupt-signaled control messages while bulk data transfers occur over more appropriate interfaces between the BMC and the host (which may lack their own interrupt mechanism, e.g. LPC FW cycles). poll() is provided, which will wait for IBF or OBE conditions for data reads and writes respectively. Reads of STR on its own never blocks, though accessing both offsets in the one system call may block if the data registers are not ready. OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210623033854.587464-3-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: aspeed: tacoma: Remove CFAM reset GPIOEddie James1-1/+0
witherspoon hardware and p9 chips have very sensitive requirements for the cfam-reset. We're seeing power faults with the kernel based cfam reset due to this. Could adapt the power application to use the new kernel based cfam reset interface but there's not a lot to be gained there since the power application is going away with p10 and this limitation is not present in p10. OpenBMC-Staging-Count: 3 Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210308225419.46530-17-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: configs: add defconfig for Nuvoton NPCM7xx BMCTomer Maimon1-0/+117
OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01watchdog: npcm: Modify get reset status functionTomer Maimon1-1/+3
Once the syscon phandle is not found the WD reset status will not be supported, so return to the function caller. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210119223412.223492-5-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01misc: Add NPCM7xx JTAG master driverTomer Maimon3-0/+846
The NPCM7xx JTAG master using GPIO lines and NPCM PSPI bus. OpenBMC-Staging-Count: 4 Signed-off-by: Stanley Chu <yschu@nuvoton.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-13-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: bmc: add NPCM7XX JTAG master documentationTomer Maimon1-0/+38
Added device tree binding documentation for Nuvoton NPCM7XX JTAG master. OpenBMC-Staging-Count: 4 Signed-off-by: Stanley Chu <yschu@nuvoton.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-12-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01spi: npcm-pspi: Add full duplex supportTomer Maimon1-45/+30
Modify the IRQ handler in the NPCM PSPI driver to support SPI full duplex communication. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-11-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01pinctrl: npcm7xx: Add pin persist configuration supportTomer Maimon1-0/+65
OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-10-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01pinctrl: pinconf: add pin persist configurationTomer Maimon1-0/+3
Add generic pin persist configuration support. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-9-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01pinctrl: npcm7xx: Add HGPIO pin support to NPCM7xx pinctrl driverTomer Maimon1-16/+49
OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-8-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01watchdog: npcm: Add DT restart priority and reset type supportTomer Maimon1-3/+114
Add device tree restart priority and three reset types support. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-7-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01iio: adc: Add calibration support to npcm ADCTomer Maimon1-0/+178
Add calibration to improve accuracy measurement when using internal reference voltage. Tthe calibration values taken are from the FUSE module. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-4-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01clk: npcm7xx: add read only flag to divider clocksTomer Maimon1-32/+38
Add read only flag to all divider clocks except SPI3 clock. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-2-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01net: ftgmac100: Ensure tx descriptor updates are visibleJoel Stanley1-0/+10
We must ensure the tx descriptor updates are visible before updating the tx pointer. This resolves the tx hangs observed on the 2600 when running iperf: root@ast2600:~# iperf3 -c 192.168.86.146 -R Connecting to host 192.168.86.146, port 5201 Reverse mode, remote host 192.168.86.146 is sending [ 5] local 192.168.86.173 port 43886 connected to 192.168.86.146 port 5201 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 90.7 MBytes 760 Mbits/sec [ 5] 1.00-2.00 sec 91.7 MBytes 769 Mbits/sec [ 5] 2.00-3.00 sec 91.7 MBytes 770 Mbits/sec [ 5] 3.00-4.00 sec 91.7 MBytes 769 Mbits/sec [ 5] 4.00-5.00 sec 91.8 MBytes 771 Mbits/sec [ 5] 5.00-6.00 sec 91.8 MBytes 771 Mbits/sec [ 5] 6.00-7.00 sec 91.9 MBytes 771 Mbits/sec [ 5] 7.00-8.00 sec 91.4 MBytes 767 Mbits/sec [ 5] 8.00-9.00 sec 91.3 MBytes 766 Mbits/sec [ 5] 9.00-10.00 sec 91.9 MBytes 771 Mbits/sec [ 5] 10.00-11.00 sec 91.8 MBytes 770 Mbits/sec [ 5] 11.00-12.00 sec 91.8 MBytes 770 Mbits/sec [ 5] 12.00-13.00 sec 90.6 MBytes 761 Mbits/sec [ 5] 13.00-14.00 sec 45.2 KBytes 370 Kbits/sec [ 5] 14.00-15.00 sec 0.00 Bytes 0.00 bits/sec [ 5] 15.00-16.00 sec 0.00 Bytes 0.00 bits/sec [ 5] 16.00-17.00 sec 0.00 Bytes 0.00 bits/sec [ 5] 17.00-18.00 sec 0.00 Bytes 0.00 bits/sec [ 67.031671] ------------[ cut here ]------------ [ 67.036870] WARNING: CPU: 1 PID: 0 at net/sched/sch_generic.c:442 dev_watchdog+0x2dc/0x300 [ 67.046123] NETDEV WATCHDOG: eth2 (ftgmac100): transmit queue 0 timed out OpenBMC-Staging-Count: 4 Fixes: 52c0cae87465 ("ftgmac100: Remove tx descriptor accessors") Link: https://lore.kernel.org/r/20201020220639.130696-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01input: misc: Add IBM Operation Panel driverEddie James4-0/+209
Add a driver to get the button events from the panel and provide them to userspace with the input subsystem. The panel is connected with I2C and controls the bus, so the driver registers as an I2C slave device. OpenBMC-Staging-Count: 4 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200909203059.23427-3-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-bindings: input: Add documentation for IBM Operation PanelEddie James2-0/+47
Document the bindings for the IBM Operation Panel, which provides a simple interface to control a server. It has a display and three buttons. Also update MAINTAINERS for the new file. OpenBMC-Staging-Count: 4 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200909203059.23427-2-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01eeprom: at25: Split reads into chunks and cap write sizeBrad Bishop1-40/+54
Make use of spi_max_transfer_size to avoid requesting transfers that are too large for some spi controllers. Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200820170228.42053-8-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01clk: ast2600: enable BCLK for PCI/PCIe bus alwaysJae Hyun Yoo1-1/+1
BCLK for PCI/PCIe bus should be enabled always with having the CLK_IS_CRITICAL flag otherwise it will be disabled at kernel late initcall phase as an unused clock, and eventually it causes unexpected behavior on BMC features that are connected to the host through PCI/PCIe bus. OpenBMC-Staging-Count: 6 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01reset: simple: Add AST2600 compatibility stringBrad Bishop1-0/+1
The AST2600 SoC contains the same LPC register set as the AST2500. OpenBMC-Staging-Count: 7 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ipmi: aspeed-g6: Add compatible stringsBrad Bishop2-0/+2
The AST2600 SoC contains the same IPMI (BT/KCS) devices as the AST2500. OpenBMC-Staging-Count: 7 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01edac: npcm: Add Nuvoton NPCM7xx EDAC driverGeorge Hung4-0/+435
Add support for the Nuvoton NPCM7xx SoC EDAC driver NPCM7xx ECC datasheet from nuvoton.israel-Poleg: "Cadence DDR Controller User’s Manual For DDR3 & DDR4 Memories" Tested: Forcing an ECC error event Write a value to the xor_check_bits parameter that will trigger an ECC event once that word is read For example, to force a single-bit correctable error on bit 0 of the user-word space shown, write 0x75 into that byte of the xor_check_bits parameter and then assert fwc (force write check) bit to 'b1' (mem base: 0xf0824000, xor_check_bits reg addr: 0x178) $ devmem 0xf0824178 32 0x7501 To force a double-bit un-correctable error for the user-word space, write 0x03 into that byte of the xor_check_bits parameter $ devmem 0xf0824178 32 0x301 OpenBMC-Staging-Count: 9 Signed-off-by: George Hung <george.hung@quantatw.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: edac: add NPCM ECC documentationGeorge Hung1-0/+17
Add device tree documentation for Nuvoton BMC ECC OpenBMC-Staging-Count: 9 Signed-off-by: George Hung <george.hung@quantatw.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: npcm7xx: Link fuse syscon to adc and wdtTomer Maimon1-0/+4
These modules need a phandle reference to the fuse device in order to read out system specific settings. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210119223412.223492-2-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: npcm750: Add fuse regmap support nodeTomer Maimon1-0/+5
OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-5-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: olympus: Add non-mainline nodesTomer Maimon1-0/+112
This is the remaining non-mainline component of the patch that adds the Opympus machine. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: nuvoton: gsj: Add non-mainline nodesFran Hsu1-0/+36
This is the remaining non-mainline component of the patch that adds the GSJ machine. OpenBMC-Staging-Count: 4 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: nuvoton: npcm730: Add UDC deviceFran Hsu1-1/+14
This is the remaining non-mainline component of the patch that adds the NPCM730 common device tree. OpenBMC-Staging-Count: 4 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: npcm7xx: Add out of tree nodesTomer Maimon4-6/+2579
FIU, ADC, RST, VCD and SPI, PECI, regulator and HGPIO pins nodes. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01ARM: dts: aspeed: witherspoon: Update max31785 nodeAndrew Jeffery1-0/+52
Witherspoon contains four dual-tach fans. We configure them go to 100% when the fault pin is asserted, and disable the fan ramp watchdog. This preserves the behaviour of the previous driver. OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01net: npcm: Support for fixed PHYsWilliam A. Kennington III1-1/+30
Most of our machines don't have PHYs between the NIC and the BMC over their NC-SI port. We don't want to use the kernel NC-SI machinery, but we do want phyless support. OpenBMC-Staging-Count: 3 Signed-off-by: William A. Kennington III <wak@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210327004920.388957-1-wak@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01net: npcm: add NPCM7xx Ethernet MAC controllerTomer Maimon5-0/+2122
Add Nuvoton BMC NPCM7xx Ethernet MAC controller (EMC) driver. OpenBMC-Staging-Count: 11 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: net: document NPCM7xx EMC DT bindingsTomer Maimon1-0/+36
Added device tree binding documentation for Nuvoton NPCM7xx Ethernet MAC Controller (EMC). OpenBMC-Staging-Count: 11 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01misc: mbox: add npcm7xx pci mailbox driverTomer Maimon3-0/+296
Add Nuvoton BMC NPCM7XX PCI Mailbox driver. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [v5.0: Fix access_ok for API change] Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: bmc: add npcm7xx pci mailbox documentTomer Maimon1-0/+19
Added device tree binding documentation for Nuvoton BMC NPCM7XX PCI mailbox. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01misc: npcm7xx-lpc-bpc: add NPCM7xx BIOS post code driverTomer Maimon3-0/+403
Add NPCM7xx BIOS post code (BPC) driver, the BPC monitoring two I/O address written by the host on the LPC. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-11-01dt-binding: bmc: Add NPCM7xx LPC BPC documentationTomer Maimon1-0/+26
Added device tree binding documentation for Nuvoton BMC NPCM7xx BIOS Post Code (BPC). The NPCM7xx BPC monitoring two configurable I/O addresses written by the host on Low Pin Count (LPC) bus. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-02 08:55:11 +0300