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BMC/Intel-BMC/linux.git
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dev-4.10
dev-4.13
dev-4.17
dev-4.18
dev-4.19
dev-4.3
dev-4.4
dev-4.6
dev-4.7
dev-5.0
dev-5.1
dev-5.10-intel
dev-5.10.46-intel
dev-5.10.49-intel
dev-5.14-intel
dev-5.15-intel
dev-5.2
dev-5.3
dev-5.4
dev-5.7
dev-5.8
dev-5.8-intel
master
Intel OpenBMC Linux kernel source tree (mirror)
Andrey V.Kosteltsev
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path:
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arch
/
mips
/
include
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asm
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mach-rc32434
/
war.h
Age
Commit message (
Expand
)
Author
Files
Lines
2020-09-07
MIPS: Remove mach-*/war.h
Thomas Bogendoerfer
1
-11
/
+0
2020-09-07
MIPS: Get rid of BCM1250_M3_WAR
Thomas Bogendoerfer
1
-2
/
+0
2020-09-07
MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS
Thomas Bogendoerfer
1
-1
/
+0
2020-09-07
MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option
Thomas Bogendoerfer
1
-1
/
+0
2020-09-07
MIPS: Convert R10000_LLSC_WAR info a config option
Thomas Bogendoerfer
1
-1
/
+0
2020-09-07
MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option
Thomas Bogendoerfer
1
-1
/
+0
2020-09-07
MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option
Thomas Bogendoerfer
1
-1
/
+0
2020-09-07
MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR
Thomas Bogendoerfer
1
-2
/
+0
2020-09-07
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option
Thomas Bogendoerfer
1
-1
/
+0
2020-09-07
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option
Thomas Bogendoerfer
1
-1
/
+0
2020-09-07
MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Thomas Bogendoerfer
1
-1
/
+0
2019-07-24
MIPS: Remove unused R5432_CP0_INTERRUPT_WAR
Paul Burton
1
-1
/
+0
2012-12-13
MIPS: PMC-Sierra Yosemite: Remove support.
Ralf Baechle
1
-1
/
+0
2008-10-11
MIPS: Move headfiles to new location below arch/mips/include
Ralf Baechle
1
-0
/
+25