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path: root/arch/riscv/include/asm/tlbflush.h
AgeCommit message (Expand)AuthorFilesLines
2021-06-09riscv: fix build error when CONFIG_SMP is disabledBixuan Cui1-0/+5
2021-04-26riscv: sifive: Apply errata "cip-1200" patchVincent Chen1-1/+2
2019-11-18riscv: add nommu supportChristoph Hellwig1-3/+9
2019-10-14riscv: tlbflush: remove confusing comment on local_flush_tlb_all()Paul Walmsley1-4/+0
2019-09-05riscv: move the TLB flush logic out of lineChristoph Hellwig1-30/+7
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig1-1/+0
2019-08-14riscv: fix flush_tlb_range() end address for flush_tlb_page()Paul Walmsley1-2/+9
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2018-10-23RISC-V: Use Linux logical CPU number instead of hartidAtish Patra1-3/+13
2018-06-07riscv: use NULL instead of a plain 0Luc Van Oostenryck1-1/+1
2018-01-31RISC-V: Limit the scope of TLB shootdownsAndrew Waterman1-8/+12
2018-01-08riscv: remove CONFIG_MMU ifdefsChristoph Hellwig1-4/+0
2017-12-02RISC-V: User-Visible ChangesPalmer Dabbelt1-0/+2
2017-11-30RISC-V: Flush I$ when making a dirty page executableAndrew Waterman1-0/+2
2017-11-29RISC-V: `sfence.vma` orderes the instruction cachePalmer Dabbelt1-1/+4
2017-09-27RISC-V: Atomic and Locking CodePalmer Dabbelt1-0/+64