Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-11-18 | x86/cpu: Fix migration safety with X86_BUG_NULL_SEL | Jane Malalane | 1 | -0/+2 |
2021-06-01 | perf/x86/rapl: Use CPUID bit on AMD and Hygon parts | Andrew Cooper | 1 | -0/+4 |
2021-03-06 | x86/cpu/hygon: Set __max_die_per_package on Hygon | Pu Wen | 1 | -2/+2 |
2020-12-08 | x86/cpu/amd: Remove dead code for TSEG region remapping | Arvind Sankar | 1 | -20/+0 |
2020-11-19 | x86/CPU/AMD: Save AMD NodeId as cpu_die_id | Yazen Ghannam | 1 | -6/+5 |
2020-08-06 | locking/seqlock, headers: Untangle the spaghetti monster | Peter Zijlstra | 1 | -0/+1 |
2019-07-22 | x86: Remove X86_FEATURE_MFENCE_RDTSC | Josh Poimboeuf | 1 | -18/+3 |
2019-03-23 | x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors | Pu Wen | 1 | -0/+5 |
2018-09-27 | x86/cpu: Get cache info and setup cache cpumap for Hygon Dhyana | Pu Wen | 1 | -0/+3 |
2018-09-27 | x86/cpu: Create Hygon Dhyana architecture support file | Pu Wen | 1 | -0/+405 |