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path: root/drivers/clk/socfpga
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2021-09-25clk: socfpga: agilex: fix duplicate s2f_user0_clkDinh Nguyen1-9/+0
2021-07-27clk: socfpga: agilex: add the bypass register for s2f_usr0 clockDinh Nguyen1-1/+1
2021-07-27clk: socfpga: agilex: fix up s2f_user0_clk representationDinh Nguyen1-0/+9
2021-07-27clk: socfpga: agilex: fix the parents of the psi_ref_clkDinh Nguyen1-4/+4
2021-06-28clk: socfpga: clk-pll: Remove unused variable 'rc'Jian Xin1-2/+1
2021-06-28clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen1-3/+8
2021-06-28clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen3-2/+123
2021-06-28clk: agilex/stratix10: fix bypass representationDinh Nguyen2-21/+91
2021-06-28clk: agilex/stratix10: remove noc_clkDinh Nguyen2-34/+30
2021-04-29Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds12-180/+202
2021-04-28Merge branches 'clk-cleanup', 'clk-renesas', 'clk-socfpga', 'clk-allwinner' a...Stephen Boyd12-181/+203
2021-04-09clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski1-1/+1
2021-04-08clk: socfpga: remove redundant initialization of variable divColin Ian King2-2/+2
2021-04-08clk: socfpga: arria10: Fix memory leak of socfpga_clk on error returnColin Ian King1-0/+1
2021-03-31clk: socfpga: Fix code formattingStephen Boyd1-1/+2
2021-03-31clk: socfpga: Convert to s10/agilex/n5x to use clk_hwDinh Nguyen6-147/+159
2021-03-31clk: socfpga: arria10: convert to use clk_hwDinh Nguyen3-15/+16
2021-03-31clk: socfpga: use clk_hw_register for a5/c5Dinh Nguyen3-15/+22
2021-03-29clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski1-1/+1
2021-03-23clk: socfpga: use ARCH_INTEL_SOCFPGA also for 32-bit ARM SoCs (and compile test)Krzysztof Kozlowski2-3/+7
2021-03-23clk: socfpga: allow compile testing of Stratix 10 / Agilex clocksKrzysztof Kozlowski1-3/+12
2021-03-23arm64: socfpga: merge Agilex and N5X into ARCH_INTEL_SOCFPGAKrzysztof Kozlowski1-2/+2
2021-03-23clk: socfpga: build together Stratix 10, Agilex and N5X clock driversKrzysztof Kozlowski2-7/+6
2021-03-23clk: socfpga: allow building N5X clocks with ARCH_N5XKrzysztof Kozlowski2-2/+8
2021-02-17Merge branches 'clk-socfpga', 'clk-mstar', 'clk-qcom' and 'clk-warnings' into...Stephen Boyd6-7/+240
2021-02-13clk: socfpga: agilex: add clock driver for eASIC N5X platformDinh Nguyen4-3/+238
2021-02-11clk: socfpga: clk-pll-a10: Remove set but unused variable 'rc'Lee Jones1-2/+1
2021-02-11clk: socfpga: clk-pll: Remove unused variable 'rc'Lee Jones1-2/+1
2020-10-22Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-13/+0
2020-09-22clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clkDinh Nguyen1-1/+1
2020-09-22clk: socfpga: agilex: Remove unused variable 'cntr_mux'YueHaibing1-13/+0
2020-06-20clk: socfpga: agilex: mpu_l2ram_clk should be mpu_ccu_clkDinh Nguyen1-1/+1
2020-06-20clk: socfpga: agilex: add nand_x_clk and nand_ecc_clkDinh Nguyen1-1/+5
2020-05-27clk: socfpga: agilex: add clock driver for the Agilex platformDinh Nguyen4-0/+526
2020-05-27clk: socfpga: add const to _ops data structuresDinh Nguyen3-4/+4
2020-05-27clk: socfpga: remove clk_ops enable/disable methodsDinh Nguyen3-6/+0
2020-05-27clk: socfpga: stratix10: use new parent data schemeDinh Nguyen5-41/+146
2020-02-13clk: socfpga: stratix10: simplify parameter passingDinh Nguyen5-92/+57
2020-02-13clk: stratix10: use do_div() for 64-bit calculationDinh Nguyen1-1/+3
2019-09-21Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2-14/+17
2019-08-16clk: socfpga: deindent code to proper indentationStephen Boyd1-2/+2
2019-08-16clk: socfpga: Don't reference clk_init_data after registrationStephen Boyd2-13/+16
2019-08-14clk: socfpga: stratix10: fix rate caclulationg for cnt_clksDinh Nguyen1-1/+1
2019-07-17Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-1/+5
2019-06-28Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/...Linus Torvalds1-2/+2
2019-06-26clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen1-2/+2
2019-06-26clk: socfpga: stratix10: add additional clocks needed for the NAND IPDinh Nguyen1-1/+5
2019-06-25clk: socfpga: stratix10: fix divider entry for the emac clocksDinh Nguyen1-2/+2
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288Thomas Gleixner1-10/+1
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201Thomas Gleixner3-36/+3