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2016-11-16clk: rockchip: add clock controller for rk1108Shawn Lin3-0/+547
Add the clock tree definition and driver for rk1108 SoC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Tested-by: Jacob Chen <jacob2.chen@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-16clk: rockchip: fix copy-paste error in rk3399 testclkJianqun Xu1-2/+2
Fix RK3368_* to RK3399_* for rk3399 clk_test clock. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-15clk: Hi6220: enable stub clock driver for ARCH_HISILeo Yan1-0/+1
In current kernel config 'CONFIG_STUB_CLK_HI6220' is disabled by default, as result stub clock driver has not been registered and CPUFreq driver cannot work. This patch is to enable stub clock driver in config for ARCH_HISI. Reported-by: Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-15Merge tag 'v4.10-rockchip-clk1' of ↵Stephen Boyd3-21/+25
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull Rockchip clk driver updates from Heiko Stuebner: PLL initialization for PLLs having both an integral and fractional mode (rk3036, rk3399) does now take into account the mode that the PLL is actually running at. As always also some additional and optimized PLL rates for rk3066 and rk3399, some additional clock ids for rk3066 and some additional clocks on rk3399 are now sucessfully handled inside their respective driver. * tag 'v4.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: Ignore frac divisor for PLL equivalence when it's unused clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktree clk: rockchip: add 400MHz to rk3066 clock rates table clk: rockchip: optimize 800MHz and 1GHz pll rates on RK3399 clk: rockchip: Use clock ids for cpu and peri clocks on rk3066 clk: rockchip: Add binding ids for cpu and peri clocks on rk3066 clk: rockchip: add 533.25MHz to rk3399 clock rates table
2016-11-15Merge tag 'clk-renesas-for-v4.10-tag1' of ↵Stephen Boyd3-14/+58
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next Pull Renesas clk driver updates from Geert Uytterhoeven: - SYS-DMAC, (H)SCIF, I2C, DRIF, and graphics related clocks for R-Car M3-W, - Minor fixes and cleanups. * tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r8a7796: Add DU and LVDS clocks clk: renesas: r8a7796: Add VSP clocks clk: renesas: r8a7796: Add FCP clocks clk: renesas: cpg-mssr: Remove bogus commas from error messages clk: renesas: r8a7796: Add DRIF clock clk: renesas: cpg-mssr: Fix inverted debug check clk: renesas: rcar-gen3-cpg: Always use readl()/writel() clk: renesas: cpg-mssr: Always use readl()/writel() clk: renesas: r8a7796: Add I2C clocks clk: renesas: r8a7796: Add HSCIF clocks clk: renesas: r8a7796: Add SCIF clocks clk: renesas: r8a7796: Add SYS-DMAC clocks
2016-11-15clk: imx: clk-imx6ul: add clk support for imx6ullBai Ping1-11/+61
imx6ull is the derived SoC from imx6ul Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peter Chen <peter.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-11-15Merge branch 'clk-hisi' into clk-nextStephen Boyd5-0/+719
* clk-hisi: clk: hisilicon: add CRG driver for Hi3516CV300 SoC clk: hisilicon: add CRG driver for Hi3798CV200 SoC
2016-11-14clk: hisilicon: add CRG driver for Hi3516CV300 SoCPan Wen3-0/+339
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Pan Wen <wenpan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-14clk: rockchip: validity should be checked prior to cpu clock rate changeElaine Zhang1-0/+9
If validity is not checked prior to clock rate change, clk_set_rate( cpu_clk, unsupported_rate) will return success, but the real clock rate change operation is prohibited in post clock change event. Alough post clock change event will report error due to unsupported clock rate is set, but this error message is ignored by clock framework. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Rocky Hao <rocky.hao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-12clk: hisilicon: add CRG driver for Hi3798CV200 SoCJiancheng Xue4-0/+380
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-11clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocksChen-Yu Tsai1-5/+5
The audio module clocks are supposed to be set according to the sample rate of the audio stream. The audio PLL provides the clock signal for these module clocks, and only it is freely tunable. Set CLK_SET_RATE_PARENT for the audio module clocks so their users can properly tune the clock rate. Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-11clk: sunxi-ng: sun8i-a23: Set CLK_SET_RATE_PARENT for audio module clocksChen-Yu Tsai1-3/+3
The audio module clocks are supposed to be set according to the sample rate of the audio stream. The audio PLL provides the clock signal for these module clocks, and only it is freely tunable. Set CLK_SET_RATE_PARENT for the audio module clocks so their users can properly tune the clock rate. Fixes: 5690879d93e8 ("clk: sunxi-ng: Add A23 CCU") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-11Merge branch 'clk-qcom-rpm' into clk-nextStephen Boyd5-9/+1096
* clk-qcom-rpm: clk: qcom: Add support for RPM Clocks clk: qcom: Add support for SMD-RPM Clocks clk: qcom: Always add factor clock for xo clocks
2016-11-11clk: qcom: Add support for RPM ClocksGeorgi Djakov3-0/+503
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_rpm driver to communicate with RPM. Such platforms are apq8064 and msm8960. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-11clk: qcom: Add support for SMD-RPM ClocksGeorgi Djakov3-0/+587
This adds initial support for clocks controlled by the Resource Power Manager (RPM) processor on some Qualcomm SoCs, which use the qcom_smd_rpm driver to communicate with RPM. Such platforms are msm8916, apq8084 and msm8974. The RPM is a dedicated hardware engine for managing the shared SoC resources in order to keep the lowest power profile. It communicates with other hardware subsystems via shared memory and accepts clock requests, aggregates the requests and turns the clocks on/off or scales them on demand. This driver is based on the codeaurora.org driver: https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Acked-by: Rob Herring <robh@kernel.org> [sboyd@codeaurora.org: Remove useless braces for single line if] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-11clk: qcom: Always add factor clock for xo clocksGeorgi Djakov1-9/+6
Currently the RPM/RPM-SMD clock drivers do not register the xo clocks, so we should always add factor clock. When we later add xo clocks support into the drivers, we should update this function to skip registration. By doing so we avoid any DT dependencies. Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-11Merge branch 'clk-qcom-8994' into clk-nextStephen Boyd3-0/+2309
* clk-qcom-8994: clk: qcom: Add support for msm8994 global clock controller dt-bindings: qcom: clocks: Add msm8994 clock bindings
2016-11-11clk: qcom: Add support for msm8994 global clock controllerBastian Köcher3-0/+2309
The clock definition was ported from the Google 3.10 kernel tree to work with the latest kernel. Signed-off-by: Bastian Köcher <mail@kchr.de> [jeremymc@redhat.com: created new commit of just dt-bindings] Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com> [sboyd@codeaurora.org: Tidy up commit text and Kconfig help] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-11clk: tegra: dfll: Use builtin_platform_driver to simplify the codeWei Yongjun1-6/+1
Use the builtin_platform_driver() macro to make the code simpler. Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-10clk: renesas: cpg-mssr: Add R8A7745 supportSergei Shtylyov5-0/+268
Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-10clk: renesas: cpg-mssr: Add R8A7743 supportSergei Shtylyov5-0/+279
Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-10clk: renesas: cpg-mssr: Add common R-Car Gen2 supportSergei Shtylyov2-0/+414
Add the common R-Car Gen2 (and RZ/G) Clock Pulse Generator / Module Standby and Software Reset support code, using the CPG/MSSR driver core. Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <geert+renesas@glider.be>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-10clk: qcom: ipq806x: Fix board clk ratesStephen Boyd1-2/+2
The clocks on these boards run at 25 MHz, not 19.2 and 27 like other platforms. Unfortunately I copy/pasted from other similar SoCs but forgot this one is different. Fix it. Fixes: a085f877a882 ("clk: qcom: Move cxo/pxo/xo into dt files") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: pxa: Use __iomem properly and staticize lock variableStephen Boyd2-5/+6
This function is passed an __iomem pointer but we use a u32 pointer instead which makes checkers like spare complain. Furthermore, "lock" is a pretty poor variable name for a string that will go into lockdep reports and the symbol isn't marked static. Cleanup all this. Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: gate: fix coding styleUwe Kleine-König1-2/+2
The : of the ?: operator should have a leading space. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> [sboyd@codeaurora.org: Also remove useless parenthesis] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: pxa: fix pxa2xx_determine_rate returnArnd Bergmann1-11/+12
The new pxa2xx_determine_rate() function seems lacking in a few regards: - For an exact match or no match at all, the rate is uninitialized as reported by gcc -Wmaybe-unintialized: drivers/clk/pxa/clk-pxa.c: In function 'pxa2xx_determine_rate': drivers/clk/pxa/clk-pxa.c:243:5: error: 'rate' may be used uninitialized in this function - If we get a non-exact match, the req->rate output is never set to the actual rate but remains at the requested rate. - We should not attempt to print a rate if none could be found This rewrites the logic accordingly. Fixes: 9fe694295098 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09reset: mediatek: Add MT2701 reset driverShunli Wang2-4/+16
In infrasys and perifsys, there are many reset control bits for kinds of modules. These bits are used as actual reset controllers to be registered into kernel's generic reset controller framework. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: mediatek: Add MT2701 clock supportShunli Wang14-5/+1797
Add MT2701 clock support, include topckgen, apmixedsys, infracfg, pericfg and subsystem clocks. Signed-off-by: Shunli Wang <shunli.wang@mediatek.com> Signed-off-by: James Liao <jamesjj.liao@mediatek.com> Signed-off-by: Erin Lo <erin.lo@mediatek.com> Tested-by: John Crispin <blogic@openwrt.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-09clk: pxa mark dummy helper as 'inline'Arnd Bergmann1-1/+1
The dummy_clk_set_parent function is marked as 'static' but is no longer referenced from the pxa25x clk driver after the last use of the RATE_RO_OPS() macro is gone from this file, causing a harmless build warning: In file included from drivers/clk/pxa/clk-pxa25x.c:24:0: drivers/clk/pxa/clk-pxa.h:146:12: error: 'dummy_clk_set_parent' defined but not used [-Werror=unused-function] This marks the functon as 'inline', which lets the compiler simply drop it when it gets referenced. Fixes: 9fe694295098 ("clk: pxa: transfer CPU clock setting from pxa2xx-cpufreq") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-07clk: renesas: r8a7795: Fix HDMI parent clockTakeshi Kihara1-1/+1
Correct HDMI parent clock so that the rate of the HDMI clock is 1/4 rather than 1/2 of the rate of PLL1 as per the v0.52 (Jun, 15) manual. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07clk: renesas: r8a7796: Add VIN clocksNiklas Söderlund1-0/+8
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-07clk: renesas: r8a7796: Add CSI2 clocksNiklas Söderlund1-0/+4
Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-11-06clk: rockchip: Ignore frac divisor for PLL equivalence when it's unusedJulius Werner1-2/+4
Rockchip RK3399 PLLs can be used in two separate modes: integral and fractional. We can select between these two modes with the unambiguously named DSMPD bit. During boot, we check all PLL settings to confirm that they match our PLL table for that frequency, and reinitialize the PLLs where they don't. The settings checked for this include the fractional divider field that is only used in fractional mode, even if we're in integral mode (DSMPD = 1) and that field has no effect. This patch changes the check to only compare the fractional divider if we're actually in fractional mode. This way, we won't reinitialize the PLL in cases where there's absolutely no reason for that, which may avoid glitching child clocks that should better not be glitched (e.g. PWM regulators). Signed-off-by: Julius Werner <jwerner@chromium.org> [cloned the fix to the pretty similar rk3036 pll] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-06clk: rockchip: remove more CLK_IGNORE_UNUSED for rk3399 clocktreeJianqun Xu1-11/+11
Optimize rk3399 clocktree by removing CLK_IGNORE_UNUSED of some clocks. clocks will managered by usb: - clk_usbphy0_480m_src - clk_usbphy1_480m_src - clk_usbphy_480m clocks will be managered by pvtm: - clk_pvtm_core_l - clk_pvtm_core_b - clk_pvtm_ddr clocks will be managered by dfi: - pclk_ddr_mon - clk_dfimon0_timer - clk_dfimon1_timer - aclk_dcf - pclk_dcf Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-06clk: rockchip: add 400MHz to rk3066 clock rates tablePaweł Jarosz1-0/+1
We need this to init PLL_CPLL to 400MHz at boot. Signed-off-by: Paweł Jarosz <paweljarosz3691@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-11-04clk: ti: make clk-dra7-atl explicitly non-modularPaul Gortmaker1-17/+3
The Kconfig currently controlling compilation of this code is: arch/arm/mach-omap2/Kconfig:config SOC_DRA7XX arch/arm/mach-omap2/Kconfig: bool "TI DRA7XX" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tags etc. since all that information is already contained at the top of the file in the comments. Cc: Tero Kristo <t-kristo@ti.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Peter Ujfalusi <peter.ujfalusi@ti.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-omap@vger.kernel.org Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: tegra: make clk-tegra124-dfll-fcpu explicitly non-modularPaul Gortmaker1-14/+2
The Kconfig currently controlling compilation of this code is: arch/arm/mach-tegra/Kconfig:config ARCH_TEGRA_124_SOC arch/arm/mach-tegra/Kconfig: bool "Enable support for Tegra124 family" ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. Since module_init translates to device_initcall in the non-modular case, the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tags etc. since all that information is already contained at the top of the file in the comments. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Alexandre Courbot <gnurou@gmail.com> Cc: Aleksandr Frid <afrid@nvidia.com> Cc: Paul Walmsley <pwalmsley@nvidia.com> Cc: linux-clk@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: mvebu: make ap806-system-controller explicitly non-modularPaul Gortmaker1-20/+3
The Kconfig currently controlling compilation of this code is: drivers/clk/mvebu/Kconfig:config ARMADA_AP806_SYSCON drivers/clk/mvebu/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: mvebu: make cp110-system-controller explicitly non-modularPaul Gortmaker1-32/+3
The Kconfig currently controlling compilation of this code is: drivers/clk/mvebu/Kconfig:config ARMADA_CP110_SYSCON drivers/clk/mvebu/Kconfig: bool ...meaning that it currently is not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the driver there is no doubt it is builtin-only. We explicitly disallow a driver unbind, since that doesn't have a sensible use case anyway, and it allows us to drop the ".remove" code for non-modular drivers. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE tag etc. since all that information is already contained at the top of the file in the comments. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: linux-clk@vger.kernel.org Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: pxa: transfer CPU clock setting from pxa2xx-cpufreqRobert Jarzmik4-27/+414
This is the initial stage to transfer the pxa25x and pxa27x CPU clocks handling from cpufreq to the clock API. More precisely, the clocks transferred are : - cpll : core pll, known also as the CPU core turbo frequency - core : core, known also as the CPU actual frequency, being either the CPU core turbo frequency or the CPU core run frequency This transfer is a prequel to shrink the code in pxa2xx-cpufreq.c, so that it can become, at least in devicetree builds, the casual cpufreq-dt driver. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-04clk: sunxi: Fix M factor computation for APB1Stéphan Rafin1-1/+1
commit cfa636886033 ("clk: sunxi: factors: Consolidate get_factors parameters into a struct") introduced a regression for m factor computation in sun4i_get_apb1_factors function. The old code reassigned the "parent_rate" parameter to the targeted divisor value and was buggy for the returned frequency but not for the computed factors. Now, returned frequency is good but m factor is incorrectly computed (its max value 31 is always set resulting in a significantly slower frequency than the requested one...) This patch simply restores the original proper computation for m while keeping the good changes for returned rate. Fixes: cfa636886033 ("clk: sunxi: factors: Consolidate get_factors parameters into a struct") Signed-off-by: Stéphan Rafin <stephan@soliotek.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-03clk: sunxi-ng: Add A64 clocksMaxime Ripard4-0/+999
Add the A64 CCU clocks set. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-11-03clk: qcom: Add freq tables for a few rcgsRajendra Nayak1-0/+25
Add frequency tables for a few RCG clocks in msm8996 Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-03clk: qcom: Add .is_enabled ops for clk-alpha-pllRajendra Nayak1-0/+26
This would be useful in subsequent patches when the .set_rate operation would need to identify if the PLL is actually enabled Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> [sboyd@codeaurora.org: Simplify return statement of is_enabled op] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2016-11-02Merge branch 'rcar-rst' into clk-renesas-for-v4.10Geert Uytterhoeven7-51/+59
soc: renesas: Add R-Car RST driver for obtaining mode pin state
2016-11-02clk: renesas: rcar-gen2: Remove obsolete rcar_gen2_clocks_init()Geert Uytterhoeven1-7/+0
The R-Car Gen2 board code no longer calls rcar_gen2_clocks_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init()Geert Uytterhoeven1-9/+0
The R-Car H1 board code no longer calls r8a7779_clocks_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init()Geert Uytterhoeven1-13/+0
The R-Car M1A board code no longer calls r8a7778_clocks_init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
2016-11-02clk: renesas: rcar-gen3-cpg: Remove obsolete rcar_gen3_read_mode_pins()Geert Uytterhoeven2-18/+0
All R-Car Gen3 clock drivers now obtain the values of the mode pins from the R-Car RST driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2016-11-02clk: renesas: r8a7796: Obtain mode pin values from R-Car RST driverGeert Uytterhoeven1-1/+7
Obtain the values of the mode pins from the R-Car RST driver, which relies on the presence in DT of a device node for the RST module. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-08-27 23:13:38 +0300