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2020-06-30Revert "i2c: tegra: Fix suspending in active runtime PM state"Thierry Reding1-9/+0
[ Upstream commit 78ad73421831247e46c31899a7bead02740e4bef ] This reverts commit 9f42de8d4ec2304f10bbc51dc0484f3503d61196. It's not safe to use pm_runtime_force_{suspend,resume}(), especially during the noirq phase of suspend. See also the guidance provided in commit 1e2ef05bb8cf ("PM: Limit race conditions between runtime PM and system sleep (v2)"). Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
2020-04-28Revert "i2c: tegra: Better handle case where CPU0 is busy for a long time"Wolfram Sang1-15/+12
This reverts commit a900aeac253729411cf33c6cb598c152e9e4137f because regressions were showing up. Suggested-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/dmaengine/20200319201140.17451-1-digetx@gmail.com/ Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-04-28Revert "i2c: tegra: Synchronize DMA before termination"Wolfram Sang1-9/+0
This reverts commit 8814044fe0fa182abc9ff818d3da562de98bc9a7 because regressions were showing up. Suggested-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/dmaengine/20200319201140.17451-1-digetx@gmail.com/ Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-04-15i2c: tegra: Synchronize DMA before terminationDmitry Osipenko1-0/+9
DMA transfer could be completed, but CPU (which handles DMA interrupt) may get too busy and can't handle the interrupt in a timely manner, despite of DMA IRQ being raised. In this case the DMA state needs to synchronized before terminating DMA transfer in order not to miss the DMA transfer completion. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-04-15i2c: tegra: Better handle case where CPU0 is busy for a long timeDmitry Osipenko1-12/+15
Boot CPU0 always handle I2C interrupt and under some rare circumstances (like running KASAN + NFS root) it may stuck in uninterruptible state for a significant time. In this case we will get timeout if I2C transfer is running on a sibling CPU, despite of IRQ being raised. In order to handle this rare condition, the IRQ status needs to be checked after completion timeout. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-03-25i2c: drivers: Use generic definitions for bus frequenciesAndy Shevchenko1-11/+7
Since we have generic definitions for bus frequencies, let's use them. Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Acked-by: Robert Richter <rrichter@marvell.com> Reviewed-by: Thor Thayer <thor.thayer@linux.intel.com> Acked-by: Elie Morisse <syniurge@gmail.com> Acked-by: Nehal Shah <nehal-bakulchandra.shah@amd.com> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Acked-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Acked-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Reviewed-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Check DMA completion status in addition to left timeDmitry Osipenko1-1/+1
It is more robust to check completion status in addition to the left time in a case of DMA transfer because transfer's completion happens in two phases [one is ISR, other is tasklet] and thus it is possible that DMA is completed while I2C completion awaiting times out because of the deferred notification done by the DMA driver. The DMA completion status becomes 100% actual after DMA synchronization. This fixes spurious DMA timeouts when system is under load. Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Always terminate DMA transferDmitry Osipenko1-8/+4
It is possible that I2C could error out in the middle of DMA transfer and in this case DMA channel needs to be reset, otherwise a follow up transfer will fail because DMA channel stays blocked. Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Use relaxed versions of readl/writelDmitry Osipenko1-10/+11
There is nothing to synchronize in regards to memory accesses for PIO transfers and for DMA transfers the DMA API takes care of the syncing. Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Rename I2C_PIO_MODE_MAX_LEN to I2C_PIO_MODE_PREFERRED_LENDmitry Osipenko1-5/+6
DMA is preferred for a larger transfers, while PIO is preferred for a smaller transfers to avoid unnecessary DMA overhead. There is no strict size limitations for the PIO-mode transfers, so let's rename the constant for clarity. Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Support atomic transfersDmitry Osipenko1-15/+69
System shutdown may happen with interrupts being disabled and in this case kernel may hang if atomic transfer isn't supported by driver. There were several occurrences where I found my Nexus 7 completely discharged despite of being turned off and then one day I spotted this in the log: reboot: Power down ------------[ cut here ]------------ WARNING: CPU: 0 PID: 1 at drivers/i2c/i2c-core.h:40 i2c_transfer+0x95/0x9c No atomic I2C transfer handler for 'i2c-1' Modules linked in: tegra30_devfreq CPU: 0 PID: 1 Comm: systemd-shutdow Not tainted 5.4.0-next-20191202-00120-gf7ecd80fb803-dirty #3195 Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [<c010e4b5>] (unwind_backtrace) from [<c010a0fd>] (show_stack+0x11/0x14) [<c010a0fd>] (show_stack) from [<c09995e5>] (dump_stack+0x85/0x94) [<c09995e5>] (dump_stack) from [<c011f3d1>] (__warn+0xc1/0xc4) [<c011f3d1>] (__warn) from [<c011f691>] (warn_slowpath_fmt+0x61/0x78) [<c011f691>] (warn_slowpath_fmt) from [<c069a8dd>] (i2c_transfer+0x95/0x9c) [<c069a8dd>] (i2c_transfer) from [<c05667f1>] (regmap_i2c_read+0x4d/0x6c) [<c05667f1>] (regmap_i2c_read) from [<c0563601>] (_regmap_raw_read+0x99/0x1cc) [<c0563601>] (_regmap_raw_read) from [<c0563757>] (_regmap_bus_read+0x23/0x38) [<c0563757>] (_regmap_bus_read) from [<c056293d>] (_regmap_read+0x3d/0xfc) [<c056293d>] (_regmap_read) from [<c0562d3b>] (_regmap_update_bits+0x87/0xc4) [<c0562d3b>] (_regmap_update_bits) from [<c0563add>] (regmap_update_bits_base+0x39/0x50) [<c0563add>] (regmap_update_bits_base) from [<c056fd39>] (max77620_pm_power_off+0x29/0x2c) [<c056fd39>] (max77620_pm_power_off) from [<c013bbdd>] (__do_sys_reboot+0xe9/0x170) [<c013bbdd>] (__do_sys_reboot) from [<c0101001>] (ret_fast_syscall+0x1/0x28) Exception stack(0xde907fa8 to 0xde907ff0) 7fa0: 00000000 00000000 fee1dead 28121969 4321fedc 00000000 7fc0: 00000000 00000000 00000000 00000058 00000000 00000000 00000000 00000000 7fe0: 0045adf0 bed9abb8 004444a0 b6c666d0 ---[ end trace bdd18f87595b1a5e ]--- The atomic transferring is implemented by enforcing PIO mode for the transfer and by polling interrupt status until transfer is completed or failed. Now system shuts down properly every time. Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Prevent interrupt triggering after transfer timeoutDmitry Osipenko1-34/+36
Potentially it is possible that interrupt may fire after transfer timeout. That may not end up well for the next transfer because interrupt handling may race with hardware resetting. This is very unlikely to happen in practice, but anyway let's prevent the potential problem by enabling interrupt only at the moments when it is actually necessary to get some interrupt event. Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Properly disable runtime PM on driver's probe errorDmitry Osipenko1-10/+19
One of the recent Tegra I2C commits made a change that resumes runtime PM during driver's probe, but it missed to put the RPM in a case of error. Note that it's not correct to use pm_runtime_status_suspended because it breaks RPM refcounting. Fixes: 8ebf15e9c869 ("i2c: tegra: Move suspend handling to NOIRQ phase") Cc: <stable@vger.kernel.org> # v5.4+ Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2020-01-15i2c: tegra: Fix suspending in active runtime PM stateDmitry Osipenko1-0/+9
I noticed that sometime I2C clock is kept enabled during suspend-resume. This happens because runtime PM defers dynamic suspension and thus it may happen that runtime PM is in active state when system enters into suspend. In particular I2C controller that is used for CPU's DVFS is often kept ON during suspend because CPU's voltage scaling happens quite often. Fixes: 8ebf15e9c869 ("i2c: tegra: Move suspend handling to NOIRQ phase") Cc: <stable@vger.kernel.org> # v5.4+ Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-11-14i2c: tegra: Use dma_request_chan() directly for channel requestPeter Ujfalusi1-2/+2
dma_request_slave_channel_reason() is: #define dma_request_slave_channel_reason(dev, name) \ dma_request_chan(dev, name) Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-09-13i2c: tegra: Move suspend handling to NOIRQ phaseJon Hunter1-18/+22
Commit acc8abcb2a9c ("i2c: tegra: Add suspend-resume support") added suspend support for the Tegra I2C driver and following this change on Tegra30 the following WARNING is seen on entering suspend ... WARNING: CPU: 2 PID: 689 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/i2c/i2c-core.h:54 __i2c_transfer+0x35c/0x70c i2c i2c-4: Transfer while suspended Modules linked in: brcmfmac brcmutil CPU: 2 PID: 689 Comm: rtcwake Not tainted 5.3.0-rc7-g089cf7f6ecb2 #1 Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [<c0112264>] (unwind_backtrace) from [<c010ca94>] (show_stack+0x10/0x14) [<c010ca94>] (show_stack) from [<c0a77024>] (dump_stack+0xb4/0xc8) [<c0a77024>] (dump_stack) from [<c0124198>] (__warn+0xe0/0xf8) [<c0124198>] (__warn) from [<c01241f8>] (warn_slowpath_fmt+0x48/0x6c) [<c01241f8>] (warn_slowpath_fmt) from [<c06f6c40>] (__i2c_transfer+0x35c/0x70c) [<c06f6c40>] (__i2c_transfer) from [<c06f7048>] (i2c_transfer+0x58/0xf4) [<c06f7048>] (i2c_transfer) from [<c06f7130>] (i2c_transfer_buffer_flags+0x4c/0x70) [<c06f7130>] (i2c_transfer_buffer_flags) from [<c05bee78>] (regmap_i2c_write+0x14/0x30) [<c05bee78>] (regmap_i2c_write) from [<c05b9cac>] (_regmap_raw_write_impl+0x35c/0x868) [<c05b9cac>] (_regmap_raw_write_impl) from [<c05b984c>] (_regmap_update_bits+0xe4/0xec) [<c05b984c>] (_regmap_update_bits) from [<c05bad04>] (regmap_update_bits_base+0x50/0x74) [<c05bad04>] (regmap_update_bits_base) from [<c04d453c>] (regulator_disable_regmap+0x44/0x54) [<c04d453c>] (regulator_disable_regmap) from [<c04cf9d4>] (_regulator_do_disable+0xf8/0x268) [<c04cf9d4>] (_regulator_do_disable) from [<c04d1694>] (_regulator_disable+0xf4/0x19c) [<c04d1694>] (_regulator_disable) from [<c04d1770>] (regulator_disable+0x34/0x64) [<c04d1770>] (regulator_disable) from [<c04d2310>] (regulator_bulk_disable+0x28/0xb4) [<c04d2310>] (regulator_bulk_disable) from [<c0495cd4>] (tegra_pcie_power_off+0x64/0xa8) [<c0495cd4>] (tegra_pcie_power_off) from [<c0495f74>] (tegra_pcie_pm_suspend+0x25c/0x3f4) [<c0495f74>] (tegra_pcie_pm_suspend) from [<c05af48c>] (dpm_run_callback+0x38/0x1d4) [<c05af48c>] (dpm_run_callback) from [<c05afe30>] (__device_suspend_noirq+0xc0/0x2b8) [<c05afe30>] (__device_suspend_noirq) from [<c05b1c24>] (dpm_noirq_suspend_devices+0x100/0x37c) [<c05b1c24>] (dpm_noirq_suspend_devices) from [<c05b1ebc>] (dpm_suspend_noirq+0x1c/0x48) [<c05b1ebc>] (dpm_suspend_noirq) from [<c017d2c0>] (suspend_devices_and_enter+0x1d0/0xa00) [<c017d2c0>] (suspend_devices_and_enter) from [<c017dd10>] (pm_suspend+0x220/0x74c) [<c017dd10>] (pm_suspend) from [<c017c2c8>] (state_store+0x6c/0xc8) [<c017c2c8>] (state_store) from [<c02ef398>] (kernfs_fop_write+0xe8/0x1c4) [<c02ef398>] (kernfs_fop_write) from [<c0271e38>] (__vfs_write+0x2c/0x1c4) [<c0271e38>] (__vfs_write) from [<c02748dc>] (vfs_write+0xa4/0x184) [<c02748dc>] (vfs_write) from [<c0274b7c>] (ksys_write+0x9c/0xdc) [<c0274b7c>] (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x54) Exception stack(0xe9f21fa8 to 0xe9f21ff0) 1fa0: 0000006c 004b2438 00000004 004b2438 00000004 00000000 1fc0: 0000006c 004b2438 004b1228 00000004 00000004 00000004 0049e78c 004b1228 1fe0: 00000004 be9809b8 b6f0bc0b b6e96206 The problem is that the Tegra PCIe driver indirectly uses I2C for controlling some regulators and the I2C driver is now being suspended before the PCIe driver causing the PCIe suspend to fail. The Tegra PCIe driver is suspended during the NOIRQ phase and this cannot be changed due to other dependencies. Therefore, we also need to move the suspend handling for the Tegra I2C driver to the NOIRQ phase as well. In order to move the I2C suspend handling to the NOIRQ phase we also need to avoid calling pm_runtime_get/put() because per commit 1e2ef05bb8cf ("PM: Limit race conditions between runtime PM and system sleep (v2)") these cannot be called early in resume. The function tegra_i2c_init(), called during resume, calls pm_runtime_get/put() and so move these calls outside of tegra_i2c_init(), so this function can be used during the NOIRQ resume phase. Fixes: acc8abcb2a9c ("i2c: tegra: Add suspend-resume support") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-08-01i2c: tegra: Compile PM functions unconditionallyDmitry Osipenko1-11/+5
The I2C driver fails to probe if CONFIG_PM_SLEEP=n because runtime PM doesn't depend on the PM sleep and in this case the runtime PM ops are not included in the driver, resulting in I2C clock not being enabled. It's much cleaner to simply allow compiler to remove the dead code instead of messing with the #ifdefs. This patch fixes such errors when CONFIG_PM_SLEEP=n: tegra-i2c 7000c400.i2c: timeout waiting for fifo flush tegra-i2c 7000c400.i2c: Failed to initialize i2c controller Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-22i2c: tegra: remove BUG() macroBitan Biswas1-8/+39
The usage of BUG() macro is generally discouraged in kernel, unless it's a problem that results in a physical damage or loss of data. This patch removes unnecessary BUG() macros and replaces the rest with warning. Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-15i2c: tegra: Add suspend-resume supportBitan Biswas1-0/+24
Post suspend I2C registers have power on reset values. Before any transfer initialize I2C registers to prevent I2C transfer timeout and implement suspend and resume callbacks needed. Fix below errors post suspend: 1) Tegra I2C transfer timeout during jetson tx2 resume: [ 27.520613] pca953x 1-0074: calling pca953x_resume+0x0/0x1b0 @ 2939, parent: i2c-1 [ 27.633623] tegra-i2c 3160000.i2c: i2c transfer timed out [ 27.639162] pca953x 1-0074: Unable to sync registers 0x3-0x5. -110 [ 27.645336] pca953x 1-0074: Failed to sync GPIO dir registers: -110 [ 27.651596] PM: dpm_run_callback(): pca953x_resume+0x0/0x1b0 returns -110 [ 27.658375] pca953x 1-0074: pca953x_resume+0x0/0x1b0 returned -110 after 127152 usecs [ 27.666194] PM: Device 1-0074 failed to resume: error -110 2) Tegra I2C transfer timeout error on jetson Xavier post resume. Remove i2c bus lock-unlock calls in resume callback as i2c_mark_adapter_* (suspended-resumed) help ensure i2c core calls from client are not executed before i2c-tegra resume. Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-15i2c: tegra: Avoid error message on deferred probeThierry Reding1-1/+3
If the driver defers probe because of a missing clock, avoid outputting an error message. The clock will show up eventually. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-12i2c: tegra: fix msleep warningBitan Biswas1-1/+1
Fix checkpatch.pl WARNING for delay of approximately 1msec in flush i2c FIFO polling loop by using usleep_range(1000, 2000): WARNING: msleep < 20ms can sleep for up to 20ms; see ... Documentation/timers/timers-howto.txt + msleep(1); Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-12i2c: tegra: add spinlock definition commentBitan Biswas1-0/+1
Fix checkpatch.pl CHECK as follows: CHECK: spinlock_t definition without comment + spinlock_t xfer_lock; Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-12i2c: tegra: fix alignment and spacing violationsBitan Biswas1-16/+19
Fix checkpatch.pl alignment and blank line check(s) in i2c-tegra.c Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-12i2c: tegra: remove unnecessary variable initBitan Biswas1-3/+3
Remove variable initializations in functions that are followed by assignments before use Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-06-12i2c: tegra: clean up macrosBitan Biswas1-14/+3
Clean up macros by: 1) removing unused macros 2) replace constants by macro BIT() Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-23i2c: tegra: Only display error messages if DMA setup failsJonathan Hunter1-4/+6
Commit 86c92b9965ff ("i2c: tegra: Add DMA support") added DMA support to the Tegra I2C driver for Tegra devices that support the APB DMA controller. One side-effect of this change is that even for Tegra devices that do not have an APB DMA controller and hence, cannot support DMA tranfers for I2C transactions, the following error messages are still displayed ... ERR KERN tegra-i2c 31c0000.i2c: cannot use DMA: -19 ERR KERN tegra-i2c 31c0000.i2c: falling back to PIO There is no point displaying the above messages for devices that do not have an APB DMA controller and so fix this by returning from the tegra_i2c_init_dma() function if 'has_apb_dma' is not true. Furthermore, if CONFIG_TEGRA20_APB_DMA is not set, then rather than printing an error message, print an debug message as for whatever reason this could be intentional. Fixes: 86c92b9965ff ("i2c: tegra: Add DMA support") Signed-off-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-23i2c: tegra: remove multi-master supportSowjanya Komatineni1-2/+2
Multi-master support is defeatured on Tegra210 and Tegra186 due to known bugs. This patch removes multi-master support for Tegra210 and Tegra186 I2C HW feature. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-23i2c: tegra: remove master fifo support on tegra186Sowjanya Komatineni1-1/+1
Tegra186 does not have master FIFO control register and instead uses FIFO control register like prior Tegra chipset. This patch fixes this and prevents crashing during boot when accessing FIFO control registers. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-16i2c: tegra: change phrasing, "fallbacking" to "falling back"Colin Ian King1-2/+2
The phrasing in two dev_err messages is using fallbacking which os less understandable than "falling back", so fix this up. Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: add i2c interface timing supportSowjanya Komatineni1-30/+159
This patch adds I2C interface timing registers support for proper bus rate configuration along with meeting the I2C spec setup and hold times based on the tuning performed on Tegra210, Tegra186 and Tegra194 platforms. I2C_INTERFACE_TIMING_0 register contains TLOW and THIGH field and Tegra I2C controller design uses them as a part of internal clock divisor. I2C_INTERFACE_TIMING_1 register contains the setup and hold times for start and stop conditions. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: update transfer timeoutSowjanya Komatineni1-4/+11
Tegra194 allows max of 64K bytes and Tegra186 and prior allows max of 4K bytes of transfer per packet. one sec timeout is not enough for transfers more than 10K bytes at STD bus rate. This patch updates I2C transfer timeout based on the transfer size and I2C bus rate to allow enough time during max transfer size at lower bus speed. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: Add DMA supportSowjanya Komatineni1-49/+383
This patch adds DMA support for Tegra I2C. Tegra I2C TX and RX FIFO depth is 8 words. PIO mode is used for transfer size of the max FIFO depth and DMA mode is used for transfer size higher than max FIFO depth to save CPU overhead. PIO mode needs full intervention of CPU to fill or empty FIFO's and also need to service multiple data requests interrupt for the same transaction. This adds delay between data bytes of the same transfer when CPU is fully loaded and some slave devices has internal timeout for no bus activity and stops transaction to avoid bus hang. DMA mode is helpful in such cases. DMA mode is also helpful for Large transfers during downloading or uploading FW over I2C to some external devices. Tegra210 and prior Tegra chips use APBDMA driver which is replaced with GPCDMA on Tegra186 and Tegra194. This patch uses has_apb_dma flag in hw_feature to differentiate DMA driver change between Tegra chipset. APBDMA driver is registered from module-init level and this patch also has a change to register I2C driver at module-init level rather than subsys-init to avoid deferring I2C probe till APBDMA driver is registered. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: update maximum transfer sizeSowjanya Komatineni1-2/+6
Tegra194 supports maximum 64K bytes per packet including 12 bytes of packet header irrespective of PIO or DMA mode transfer. This patch updates Tegra194 max write length to account for packet header size for transfers. Cc: stable@vger.kernel.org # 4.20+ Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: fix maximum transfer sizeSowjanya Komatineni1-1/+1
Tegra186 and prior supports maximum 4K bytes per packet transfer including 12 bytes of packet header. This patch fixes max write length limit to account packet header size for transfers. Cc: stable@vger.kernel.org # 4.4+ Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: add bus clear Master SupportSowjanya Komatineni1-0/+81
Bus clear feature of Tegra I2C controller helps to recover from bus hang when I2C master loses the bus arbitration due to the slave device holding SDA LOW continuously for some unknown reasons. Per I2C specification, the device that held the bus LOW should release it within 9 clock pulses. During bus clear operation, Tegra I2C controller sends 9 clock pulses and terminates the transaction with STOP condition. Upon successful bus clear operation, bus goes to idle state and driver retries the transaction. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-02-14i2c: tegra: sort all the include headers alphabeticallySowjanya Komatineni1-11/+8
This patch sorts all the include headers alphabetically for the I2C Tegra driver. Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2019-01-11i2c: tegra: Fix Maximum transfer sizeSowjanya Komatineni1-1/+14
Tegra194 supports maximum 64K Bytes transfer per packet. Tegra186 and prior supports maximum 4K Bytes transfer per packet. This patch fixes this payload difference between Tegra194 and prior Tegra chipsets using separate i2c_adapter_quirks. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-18i2c: tegra: Switch to SPDX identifierThierry Reding1-10/+1
Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-18i2c: tegra: Add missing kerneldoc for some fieldsThierry Reding1-0/+15
Not all fields were properly documented. Add kerneldoc for the missing fields to prevent the build from flagging them. Reported-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-18i2c: tegra: Cleanup kerneldoc commentsThierry Reding1-12/+11
Some of the kerneldoc uses a strange spelling for abbreviations. Turn them into all-uppercase and clean up some whitespace issues while at it. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-12-11i2c: tegra: replace spin_lock_irqsave with spin_lock in ISRjun qian1-3/+2
As you are already in ISR, it is unnecessary to call spin_lock_irqsave. Signed-off-by: jun qian <hangdianqj@163.com> Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-10-05i2c: tegra: use core to detect 'no zero length' quirkWolfram Sang1-3/+1
And don't reimplement in the driver. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-07-17Merge tag 'v4.18-rc5' into i2c/for-4.19Wolfram Sang1-9/+8
Linux 4.18-rc5
2018-07-10i2c: tegra: Fix NACK error handlingJon Hunter1-9/+8
On Tegra30 Cardhu the PCA9546 I2C mux is not ACK'ing I2C commands on resume from suspend (which is caused by the reset signal for the I2C mux not being configured correctl). However, this NACK is causing the Tegra30 to hang on resuming from suspend which is not expected as we detect NACKs and handle them. The hang observed appears to occur when resetting the I2C controller to recover from the NACK. Commit 77821b4678f9 ("i2c: tegra: proper handling of error cases") added additional error handling for some error cases including NACK, however, it appears that this change conflicts with an early fix by commit f70893d08338 ("i2c: tegra: Add delay before resetting the controller after NACK"). After commit 77821b4678f9 was made we now disable 'packet mode' before the delay from commit f70893d08338 happens. Testing shows that moving the delay to before disabling 'packet mode' fixes the hang observed on Tegra30. The delay was added to give the I2C controller chance to send a stop condition and so it makes sense to move this to before we disable packet mode. Please note that packet mode is always enabled for Tegra. Fixes: 77821b4678f9 ("i2c: tegra: proper handling of error cases") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Cc: stable@vger.kernel.org
2018-07-04i2c: tegra: Add support for Tegra194Thierry Reding1-14/+76
In order to support advanced features, the I2C FIFO interface was changed in the version of the Tegra I2C controller found in Tegra194. The changes are backwards incompatible, so the driver needs to be programmed in a slightly different way on new chips. Add support for MST FIFO programming and add an OF match entry for Tegra194. At the same time, mark all prior generations of this controller as not having the MST FIFO interface. Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2018-05-30i2c: tegra: Remove suspend-resumeDmitry Osipenko1-33/+0
Nothing prevents I2C clients to access I2C while Tegra's driver is being suspended, this results in -EBUSY error returned to the clients and that may have unfortunate consequences. In particular this causes problems for the TPS6586x MFD driver which emits hundreds of "failed to read interrupt status" error messages on resume from suspend. This happens if TPS6586X is used to wake system from suspend by the expired RTC alarm timer because TPS6586X is an I2C device driver and its IRQ handler reads the status register while Tegra's I2C driver is suspended, i.e. just after kernel enabled IRQ's during of resume-from-suspend process. Note that the removed tegra_i2c_resume() invoked tegra_i2c_init() which performs HW reset. That seems was also not entirely correct because moving tegra_i2c_resume to an earlier stage of resume-from-suspend process causes I2C transfer to fail in the case of TPS6586X. It is fine to remove the HW-reinitialization for now because it should be only needed in a case of using lowest power-mode during suspend, which upstream kernel doesn't support. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2017-08-29i2c: busses: make i2c_adapter_quirks constBhumika Goyal1-1/+1
Make these const as they are only stored as a reference in the quirks field of an i2c_adapter structure, which is const. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2017-08-14i2c: tegra: explicitly request exclusive reset controlPhilipp Zabel1-1/+1
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting reset lines") started to transition the reset control request API calls to explicitly state whether the driver needs exclusive or shared reset control behavior. Convert all drivers requesting exclusive resets to the explicit API call so the temporary transition helpers can be removed. No functional changes. Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Wolfram Sang <wsa@the-dreams.de> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: linux-i2c@vger.kernel.org Cc: linux-tegra@vger.kernel.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-09-08i2c: tegra: Fix assignment of boolean variablesJon Hunter1-2/+2
Fix the following warnings reported by coccinelle for the Tegra I2C driver. drivers/i2c/busses/i2c-tegra.c:513:2-23: WARNING: Assignment of bool to 0/1 drivers/i2c/busses/i2c-tegra.c:539:3-24: WARNING: Assignment of bool to 0/1 Reported-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2016-09-08i2c: tegra: proper handling of error casesShardar Shariff Md1-2/+27
To summarize the issue observed in error cases: SW Flow: For i2c message transfer, packet header and data payload is posted and then required error/packet completion interrupts are enabled later. HW flow: HW process the packet just after packet header is posted, if ARB lost/NACK error occurs (SW will not handle immediately when error happens as error interrupts are not enabled at this point). HW assumes error is acknowledged and clears current data in FIFO, But SW here posts the remaining data payload which still stays in FIFO as stale data (data without packet header). Now once the interrupts are enabled, SW handles ARB lost/NACK error by clearing the ARB lost/NACK interrupt. Now HW assumes that SW attended the error and will parse/process stale data (data without packet header) present in FIFO which causes invalid NACK errors. Fix: Enable the error interrupts before posting the packet into FIFO which make sure HW to not clear the fifo. Also disable the packet mode before acknowledging errors (ARB lost/NACK error) to not process any stale data. As error interrupts are enabled before posting the packet header use spinlock to avoid preempting. Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
generated by cgit v1.2.3 (git 2.39.0) at 2024-10-04 01:38:27 +0300