Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2021-11-05 | ASD Add Shift IR/DR from Exit IR/DR for HW2 JTAG xfers | Ernesto Corona | 1 | -0/+1 |
2021-11-05 | ASD Fix AST26xx HW mode end tap state support | Ernesto Corona | 1 | -3/+13 |
2021-11-05 | ASD Disable JTAG Master controller output when driver is released | Ernesto Corona | 1 | -0/+1 |
2021-11-05 | ASD AST26xx Add a delay in SW bitbang operations | Ernesto Corona | 1 | -2/+27 |
2021-11-05 | Move JTAG state matrix to JTAG core header file | Castro, Omar Eduardo | 1 | -128/+0 |
2021-11-05 | ASD Prevent TDI remaining bits to be override during JTAG xfer | Ernesto Corona | 1 | -1/+17 |
2021-11-05 | ASD AST26xx HW mode 2 interrupt support | Ernesto Corona | 1 | -25/+50 |
2021-11-05 | ASD AST26xx JTAG Controller HW1/HW2 FIFO Read/Write Delay | Ernesto Corona | 1 | -12/+42 |
2021-11-05 | Add Aspeed SoC 24xx/25xx/26xx families JTAG master driver | Ernesto Corona | 3 | -0/+1625 |
2021-11-05 | drivers: jtag: Add JTAG core driver | Ernesto Corona | 3 | -0/+339 |