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path: root/drivers/phy/phy-lpc18xx-usb-otg.c
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2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-5/+1
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2018-03-16phy: lpc18xx-usb-otg: error handling in lpc18xx_usb_otg_phy_power_on()Alexey Khoroshilov1-1/+7
If regmap_update_bits() fails in lpc18xx_usb_otg_phy_power_on(), lpc->clk is left enabled. Found by Linux Driver Verification project (linuxtesting.org). Signed-off-by: Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-08-10phy: lpc18xx-usb-otg: fix clock order in phy initJoachim Eastwood1-3/+3
Changing the frequency of the USB clock must be done before the PLL is powered on (prepared). This matters when the USB clock is not setup by either boot ROM or boot loader. Reorder the function calls to adhere to the order noted in the user manual. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
2015-07-25phy: add lpc18xx usb otg phy driverJoachim Eastwood1-0/+143
Add PHY driver for the internal USB OTG PHY found on NXP LPC18xx and LPC43xx devices. This driver takes care of enabling the PHY in CREG (syscon) and setting the required clock frequency. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>