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2021-08-11pinctrl: Add Intel Keem Bay pinctrl driverLakshmi Sowjanya D3-0/+1751
About Intel Keem Bay: ------------------- Intel Keem Bay is a computer vision AI accelerator SoC based on ARM CPU. Documentation of Keem Bay: Documentation/vpu/vpu-stack-overview.rst. Pinctrl IP: ---------- The SoC has a customised pinmux controller IP which controls pin multiplexing and configuration. Keem Bay pinctrl IP is not based on and have nothing in common with the existing pinctrl drivers. The registers used are incompatible with the existing drivers, so it requires a new driver. Add pinctrl driver to enable pin control support in the Intel Keem Bay SoC. Co-developed-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Signed-off-by: Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com> Co-developed-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> Signed-off-by: Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com> Reviewed-by: Mark Gross <mgross@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20210806142527.29113-3-lakshmi.sowjanya.d@intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11Merge tag 'intel-pinctrl-v5.14-2' of ↵Linus Walleij1-13/+13
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into fixes intel-pinctrl for v5.14-2 * Fix the software mapping of GPIOs on Intel Tiger Lake-H The following is an automated git shortlog grouped by driver: tigerlake: - Fix GPIO mapping for newer version of software
2021-08-11pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered deviceYang Yingliang1-10/+0
It's not necessary to unregister pin controller device registered with devm_pinctrl_register() and using pinctrl_unregister() leads to a double free. Fixes: fa99e7013827 ("pinctrl: zynqmp: some code cleanups") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20210729071905.3235953-1-yangyingliang@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: k210: Fix k210_fpioa_probe()Damien Le Moal1-6/+20
In k210_fpioa_probe(), add missing calls to clk_disable_unprepare() in case of error after cenabling the clk and pclk clocks. Also add missing error handling when enabling pclk. Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Fixes: d4c34d09ab03 ("pinctrl: Add RISC-V Canaan Kendryte K210 FPIOA driver") Cc: <stable@vger.kernel.org> Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Link: https://lore.kernel.org/r/20210806004311.52859-1-damien.lemoal@wdc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: ingenic: Add .max_register in regmap_configPaul Cercueil1-2/+5
Compute the max register from the GPIO chip offset and number of GPIO chips. This permits to read all registers from debugfs. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-3-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: ingenic: Fix bias config for X2000(E)Paul Cercueil1-3/+3
The ingenic_set_bias() function's "bias" argument is not a "enum pin_config_param", so its value should not be compared against values of that enum. This should fix the bias config not working on the X2000(E) SoCs. Fixes: 943e0da15370 ("pinctrl: Ingenic: Add pinctrl driver for X2000.") Cc: <stable@vger.kernel.org> # v5.12 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-2-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: ingenic: Fix incorrect pull up/down infoPaul Cercueil1-3/+3
Fix the pull up/down info for both the JZ4760 and JZ4770 SoCs, as the previous values sometimes contradicted what's written in the programming manual. Fixes: b5c23aa46537 ("pinctrl: add a pinctrl driver for the Ingenic jz47xx SoCs") Cc: <stable@vger.kernel.org> # v4.12 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/20210717174836.14776-1-paul@crapouillou.net Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: Ingenic: Add pinctrl driver for X2100.周琰杰 (Zhou Yanjie)1-0/+216
Add support for probing the pinctrl-ingenic driver on the X2100 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-5-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760.周琰杰 (Zhou Yanjie)1-0/+155
Add SSI pins support for the JZ4755 SoC and the JZ4760 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-3-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-11pinctrl: Ingenic: Improve the code.周琰杰 (Zhou Yanjie)1-66/+89
1.Rename the original "dmicx" ABIs to "dmic-ifx", since these devices have only one DMIC module which has multiple input interfaces. The original naming is easy to make users mistakenly think that the device has multiple dmic modules. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 2.Rename the original "ssix-ce0" ABIs to "ssix-ce", since the X2000 have only one ce pin. The original naming is easy to make users mistakenly think that the device has multiple ce pins. Currently, in the mainline, no other devicetree out there is using the "ssix-ce0" ABIs, so we should be able to replace it safely. 3.Split the original "sfc" ABI into "sfc-data", "sfc-ce", "sfc-clk" to increase the flexibility when configuring the pins. Currently, in the mainline, no other devicetree out there is using the "sfc" ABI, so we should be able to replace it safely. 4.There is more than one compatible string in the match table, so renaming "ingenic_xxxx_of_match[]" to "ingenic_xxxx_of_matches" is more reasonable, and remove the unnecessary commas in "ingenic_gpio_of_matches[]" to reduce code size as much as possible. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Link: https://lore.kernel.org/r/1627108604-91304-2-git-send-email-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10pinctrl: aspeed: placate kernel-doc warningsRandy Dunlap2-3/+4
Eliminate kernel-doc warnings in drivers/pinctrl/aspeed by using proper kernel-doc notation. Fixes these kernel-doc warnings: drivers/pinctrl/aspeed/pinmux-aspeed.c:61: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Query the enabled or disabled state for a mux function's signal on a pin drivers/pinctrl/aspeed/pinctrl-aspeed.c:135: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Search for the signal expression needed to enable the pin's signal for the Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Aditya Srivastava <yashsri421@gmail.com> Cc: Andrew Jeffery <andrew@aj.id.au> Cc: linux-aspeed@lists.ozlabs.org Cc: openbmc@lists.ozlabs.org Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Acked-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210723034840.8752-1-rdunlap@infradead.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10pinctrl: sunxi: Don't underestimate number of functionsAndre Przywara1-3/+5
When we are building all the various pinctrl structures for the Allwinner pinctrl devices, we do some estimation about the maximum number of distinct function (names) that we will need. So far we take the number of pins as an upper bound, even though we can actually have up to four special functions per pin. This wasn't a problem until now, since we indeed have typically far more pins than functions, and most pins share common functions. However the H616 "-r" pin controller has only two pins, but four functions, so we run over the end of the array when we are looking for a matching function name in sunxi_pinctrl_add_function - there is no NULL sentinel left that would terminate the loop: [ 8.200648] Unable to handle kernel paging request at virtual address fffdff7efbefaff5 [ 8.209179] Mem abort info: .... [ 8.368456] Call trace: [ 8.370925] __pi_strcmp+0x90/0xf0 [ 8.374559] sun50i_h616_r_pinctrl_probe+0x1c/0x28 [ 8.379557] platform_probe+0x68/0xd8 Do an actual worst case allocation (4 functions per pin, three common functions and the sentinel) for the initial array allocation. This is now heavily overestimating the number of functions in the common case, but we will reallocate this array later with the actual number of functions, so it's only temporarily. Fixes: 561c1cf17c46 ("pinctrl: sunxi: Add support for the Allwinner H616-R pin controller") Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20210722132548.22121-1-andre.przywara@arm.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10pinctrl: stmfx: Fix hazardous u8[] to unsigned long castMarc Zyngier1-2/+4
Casting a small array of u8 to an unsigned long is *never* OK: - it does funny thing when the array size is less than that of a long, as it accesses random places in the stack - it makes everything even more fun with a BE kernel Fix this by building the unsigned long used as a bitmap byte by byte, in a way that works across endianess and has no undefined behaviours. An extra BUILD_BUG_ON() catches the unlikely case where the array would be larger than a single unsigned long. Fixes: 1490d9f841b1 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver") Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Cc: Amelie Delaunay <amelie.delaunay@foss.st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Link: https://lore.kernel.org/r/20210725180830.250218-1-maz@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10pinctrl: stm32: Add STM32MP135 SoC supportAlexandre Torgue3-0/+1686
STM32MP135 SoC embeds 9 GPIO banks of 16 gpios each. Those GPIO banks contain same features as STM32MP157 GPIO banks except that each GPIO line of the STM32MP135 can be secured. Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> Acked-by: Arnd Bergmann <arnd@arndb.de Link: https://lore.kernel.org/r/20210723132810.25728-3-alexandre.torgue@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10pinctrl: single: Move test PCS_HAS_PINCONF in ↵Zhen Lei1-14/+8
pcs_parse_bits_in_pinctrl_entry() to the beginning The value of pcs->flags is not overwritten in function pcs_parse_bits_in_pinctrl_entry() and its subfunctions, so moving this check to the beginning of the function eliminates unnecessary rollback operations. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Reviewed-by: Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20210722033930.4034-3-thunder.leizhen@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10pinctrl: single: Fix error return code in pcs_parse_bits_in_pinctrl_entry()Zhen Lei1-0/+1
Fix to return -ENOTSUPP instead of 0 when PCS_HAS_PINCONF is true, which is the same as that returned in pcs_parse_pinconf(). Fixes: 4e7e8017a80e ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Link: https://lore.kernel.org/r/20210722033930.4034-2-thunder.leizhen@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-10pinctrl: qcom: spmi-gpio: Add pmc8180 & pmc8180cBjorn Andersson1-0/+2
The SC8180x platform comes with PMC8180 and PMC8180c, add support for the GPIO controller in these PMICs. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210629003851.1787673-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-08-04pinctrl: tigerlake: Fix GPIO mapping for newer version of softwareAndy Shevchenko1-13/+13
The software mapping for GPIO, which initially comes from Microsoft, is subject to change by respective Windows and firmware developers. Due to the above the driver had been written and published way ahead of the schedule, and thus the numbering schema used in it is outdated. Fix the numbering schema in accordance with the real products on market. Fixes: 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H") Reported-and-tested-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Reported-by: Riccardo Mori <patacca@autistici.org> Reported-and-tested-by: Lovesh <lovesh.bond@gmail.com> BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=213463 BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=213579 BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=213857 Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
2021-08-02pinctrl: samsung: Fix pinctrl bank pin countJaehyoung Choi1-1/+1
Commit 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") changes the order of GPIO and pinctrl registration: now pinctrl is registered before GPIO. That means gpio_chip->ngpio is not set when samsung_pinctrl_register() called, and one cannot rely on that value anymore. Use `pin_bank->nr_pins' instead of `pin_bank->gpio_chip.ngpio' to fix mentioned inconsistency. Fixes: 1abd18d1a51a ("pinctrl: samsung: Register pinctrl before GPIO") Signed-off-by: Jaehyoung Choi <jkkkkk.choi@samsung.com> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20210730192905.7173-1-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
2021-08-01drivers: qcom: pinctrl: Add pinctrl driver for sm6115Iskren Chernev3-0/+933
Based on CAF implementation with egpio/wake_reg support removed. Similar function names were merged to reduce total number of functions. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210723192352.546902-3-iskren.chernev@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30Merge tag 'renesas-pinctrl-for-v5.15-tag1' of ↵Linus Walleij4-35/+337
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.15 - Add bias support for the R-Car D3 SoC, - Miscellaneous fixes and improvements.
2021-07-30pinctrl: pinctrl-zynq: Add support for 'power-source' parameterSai Krishna Potthuri1-0/+2
Add support for generic pin parameter 'power-source'. To maintain the backward compatibility, 'io-standard' parameter is still supported in the driver. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1626868353-96475-4-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30pinctrl: pistachio: Make it as an optionJiaxun Yang1-1/+4
So it will be avilable for generic MIPS kernel. -- Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> v3: Depend on OF as well Link: https://lore.kernel.org/r/20210721030134.10562-7-jiaxun.yang@flygoat.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30pinctrl: imx8dxl: Constify imx_pinctrl_soc_infoFabio Estevam1-1/+1
The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Reported-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210716131341.3370620-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30pinctrl: imx8qxp: Constify imx_pinctrl_soc_infoFabio Estevam1-1/+1
The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20210713122513.3112941-2-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-30pinctrl: imx8mn: Constify imx_pinctrl_soc_infoFabio Estevam1-1/+1
The imx_pinctrl_soc_info structure content is never changed, so it can be declared as 'const', like it is done on all other i.MX pinctrl drivers. Make it 'const' in this driver too. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20210713122513.3112941-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-27pinctrl: renesas: Fix pin control matching on R-Car H3e-2GGeert Uytterhoeven2-19/+14
As R-Car H3 ES1.x (R8A77950) and R-Car ES2.0+ (R8A77951) use the same compatible value, the pin control driver relies on soc_device_match() with soc_id = "r8a7795" and the (non)matching of revision = "ES1.*" to match with and distinguish between the two SoC variants. The corresponding entries in the normal of_match_table are present only to make the optional sanity checks work. The R-Car H3e-2G (R8A779M1) SoC is a different grading of the R-Car H3 ES3.0 (R8A77951) SoC. It uses the same compatible values for individual devices, but has an additional compatible value for the root node. When running on an R-Car H3e-2G SoC, soc_device_match() with soc_id = "r8a7795" does not return a match. Hence the pin control driver falls back to the normal of_match_table, and, as the R8A77950 entry is listed first, incorrectly uses the sub-driver for R-Car H3 ES1.x. Fix this by moving the entry for R8A77951 before the entry for R8A77950. Simplify sh_pfc_quirk_match() to only handle R-Car H3 ES1,x, as R-Car H3 ES2.0+ can now be matched using the normal of_match_table as well. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/6cdc5bfa424461105779b56f455387e03560cf66.1626707688.git.geert+renesas@glider.be
2021-07-23pinctrl: imx8ulp: Initialize pin_regFabio Estevam1-0/+4
The initialization of pin_reg is missing, causing the following build warning: drivers/pinctrl/freescale/pinctrl-imx8ulp.c:228:35: warning: 'pin_reg' is used uninitialized in this function [-Wuninitialized] Initialize pin_reg the same way as it is done on vf610 and imx7ulp to fix the problem. Fixes: 16b343e8e0ef ("pinctrl: imx8ulp: Add pinctrl driver support") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Fabio Estevam <festevam@gmail.com> Link: https://lore.kernel.org/r/20210723203242.88845-1-festevam@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom/pinctrl-spmi-gpio: Add compatible for pmic-gpio on SA8155p-adpBhupesh Sharma1-0/+1
SA8155p-adp PMIC (PMM8155AU) exposes 10 GPIOs. Add support for the same in the pinctrl driver. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210629123407.82561-5-bhupesh.sharma@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom/pinctrl-spmi-gpio: Arrange compatibles alphabeticallyBhupesh Sharma1-17/+17
Arrange the compatibles inside qcom pinctrl-spmi gpio driver alphabetically. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210629123407.82561-4-bhupesh.sharma@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: mediatek: fix platform_no_drv_owner.cocci warningskernel test robot1-1/+0
drivers/pinctrl/mediatek/pinctrl-mt8365.c:488:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC") CC: Fabien Parent <fparent@baylibre.com> Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210626051550.GA37544@d0c207d51ce8 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: imx8ulp: Add pinctrl driver supportAnson Huang3-0/+282
Add i.MX8ULP pinctrl driver support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Link: https://lore.kernel.org/r/20210607061041.2654568-2-ping.bai@nxp.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: armada-37xx: Correct PWM pins definitionsMarek Behún1-8/+8
The PWM pins on North Bridge on Armada 37xx can be configured into PWM or GPIO functions. When in PWM function, each pin can also be configured to drive low on 0 and tri-state on 1 (LED mode). The current definitions handle this by declaring two pin groups for each pin: - group "pwmN" with functions "pwm" and "gpio" - group "ledN_od" ("od" for open drain) with functions "led" and "gpio" This is semantically incorrect. The correct definition for each pin should be one group with three functions: "pwm", "led" and "gpio". Change the "pwmN" groups to support "led" function. Remove "ledN_od" groups. This cannot break backwards compatibility with older device trees: no device tree uses it since there is no PWM driver for this SOC yet. Also "ledN_od" groups are not even documented. Fixes: b835d6953009 ("pinctrl: armada-37xx: swap polarity on LED group") Signed-off-by: Marek Behún <kabel@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210719112938.27594-1-kabel@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: bcm2835: Replace BUG with BUG_ONJason Wang1-2/+1
The if condition followed by BUG can be replaced to BUG_ON which is more compact and formal in linux source. Signed-off-by: Jason Wang <wangborong@cdjrlc.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20210624064913.41788-1-wangborong@cdjrlc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom: Add MDM9607 pinctrl driverKonrad Dybcio3-0/+1096
Add a pinctrl driver to allow for managing SoC pins. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210624191743.617073-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: mediatek: Fix fallback behavior for bias_set_comboHsin-Yi Wang1-5/+3
Some pin doesn't support PUPD register, if it fails and fallbacks with bias_set_combo case, it will call mtk_pinconf_bias_set_pupd_r1_r0() to modify the PUPD pin again. Since the general bias set are either PU/PD or PULLSEL/PULLEN, try bias_set or bias_set_rev1 for the other fallback case. If the pin doesn't support neither PU/PD nor PULLSEL/PULLEN, it will return -ENOTSUPP. Fixes: 81bd1579b43e ("pinctrl: mediatek: Fix fallback call path") Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Reviewed-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Link: https://lore.kernel.org/r/20210701080955.2660294-1-hsinyi@chromium.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-23pinctrl: qcom: fix GPIOLIB dependenciesArnd Bergmann1-32/+31
Enabling the PINCTRL_SM8350 symbol without GPIOLIB or SCM causes a build failure: WARNING: unmet direct dependencies detected for PINCTRL_MSM Depends on [m]: PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && (QCOM_SCM [=m] || !QCOM_SCM [=m]) Selected by [y]: - PINCTRL_SM8350 [=y] && PINCTRL [=y] && (ARCH_QCOM [=y] || COMPILE_TEST [=y]) && GPIOLIB [=y] && OF [=y] aarch64-linux-ld: drivers/pinctrl/qcom/pinctrl-msm.o: in function `msm_gpio_irq_set_type': pinctrl-msm.c:(.text.msm_gpio_irq_set_type+0x1c8): undefined reference to `qcom_scm_io_readl' The main problem here is the 'select PINCTRL_MSM', which needs to be a 'depends on' as it is for all the other front-ends. As the GPIOLIB dependency is now implied by that, symbol, remove the duplicate dependencies in the process. Fixes: d5d348a3271f ("pinctrl: qcom: Add SM8350 pinctrl driver") Fixes: 376f9e34c10f ("drivers: pinctrl: qcom: fix Kconfig dependency on GPIOLIB") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20210723091400.1669716-1-arnd@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-07-13pinctrl: renesas: r8a77995: Add bias pinconf supportGeert Uytterhoeven3-9/+316
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
2021-07-13pinctrl: renesas: rcar: Avoid changing PUDn when disabling biasGeert Uytterhoeven1-7/+7
When disabling pin bias, there is no need to touch the LSI pin pull-up/down control register (PUDn), which selects between pull-up and pull-down. Just disabling the pull-up/down function through the LSI pin pull-enable register (PUENn) is sufficient. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/071ec644de2555da593a4531ef5d3e4d79cf997d.1625064076.git.geert+renesas@glider.be
2021-07-02Merge tag 'pinctrl-v5.14-1' of ↵Linus Torvalds62-283/+6315
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.14 kernel. Not so much going on. No core changes, just drivers. The most interesting would be that MIPS Ralink is migrating to pin control and we have some bindings but not yet code for the Apple M1 pin controller. New drivers: - Last merge window we created a driver for the Ralink RT2880. We are now moving the Ralink SoC pin control drivers out of the MIPS architecture code and into the pin control subsystem. This concerns RT288X, MT7620, RT305X, RT3883 and MT7621. - Qualcomm SM6125 SoC pin control driver. - Qualcomm spmi-gpio support for PM7325. - Qualcomm spmi-mpp also handles PMI8994 (just a compatible string) - Mediatek MT8365 SoC pin controller. - New device HID for the AMD GPIO controller. Improvements: - Pin bias config support for a slew of Renesas pin controllers. - Incremental improvements and non-urgent bug fixes to the Renesas SoC drivers. - Implement irq_set_wake on the AMD pin controller so we can wake up from external pin events. Misc: - Devicetree bindings for the Apple M1 pin controller, we will probably see a proper driver for this soon as well" * tag 'pinctrl-v5.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (54 commits) pinctrl: ralink: rt305x: add missing include pinctrl: stm32: check for IRQ MUX validity during alloc() pinctrl: zynqmp: some code cleanups drivers: qcom: pinctrl: Add pinctrl driver for sm6125 dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios pinctrl: mcp23s08: Add optional reset GPIO pinctrl: mediatek: fix mode encoding pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq() pinctrl: bcm: Constify static pinmux_ops pinctrl: bcm: Constify static pinctrl_ops pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file pinctrl: ralink: move ralink architecture pinmux header into the driver pinctrl: single: config: enable the pin's input pinctrl: mtk: Fix mt8365 Kconfig dependency pinctrl: mcp23s08: fix race condition in irq handler ...
2021-06-30pinctrl: ralink: rt305x: add missing includeSergio Paracuellos1-0/+1
Header 'rt305x.h' is ralink architecture dependent file where other general definitions which are in 'ralink_regs.h' are being used. This 'rt305x.h' is only being included in two different files: 'rt305x.c' and 'pinctrl-rt305x.c'. When file 'pinctrl-rt305x.c' is being compiled definitions in 'ralink_regs.h' are need to build it properly. Hence, add missing include 'ralink_regs.h' in 'pinctrl-rt305x.c' source to avoid compilation problems. Fixes: 3a1b0ca5a83b ("pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Link: https://lore.kernel.org/r/20210629143407.14703-1-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-26pinctrl: stm32: check for IRQ MUX validity during alloc()Fabien Dessenne1-39/+40
Considering the following irq_domain_ops call chain: - .alloc() is called when a clients calls platform_get_irq() or gpiod_to_irq() - .activate() is called next, when the clients calls request_threaded_irq() Check for the IRQ MUX conflict during the first stage (alloc instead of activate). This avoids to provide the client with an IRQ that can't be used. Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210617144602.2557619-1-fabien.dessenne@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-26pinctrl: zynqmp: some code cleanupsSai Krishna Potthuri2-30/+22
Some minor code cleanups and updates which includes - Mention module name under help in Kconfig. - Remove extra lines and duplicate Pin range checks. - Replace 'return ret' with 'return 0' in success path. - Copyright year update. - use devm_pinctrl_register() instead pinctrl_register() in probe. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> Link: https://lore.kernel.org/r/1624273214-66849-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18pinctrl: stm32: fix the reported number of GPIO lines per bankFabien Dessenne1-2/+7
Each GPIO bank supports a variable number of lines which is usually 16, but is less in some cases : this is specified by the last argument of the "gpio-ranges" bank node property. Report to the framework, the actual number of lines, so the libgpiod gpioinfo command lists the actually existing GPIO lines. Fixes: 1dc9d289154b ("pinctrl: stm32: add possibility to use gpio-ranges to declare bank range") Signed-off-by: Fabien Dessenne <fabien.dessenne@foss.st.com> Link: https://lore.kernel.org/r/20210617144629.2557693-1-fabien.dessenne@foss.st.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18drivers: qcom: pinctrl: Add pinctrl driver for sm6125Martin Botka3-0/+1287
This patch adds pinctrl driver for sm6125. Signed-off-by: Martin Botka <martin.botka@somainline.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210614172713.558192-2-martin.botka@somainline.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-18pinctrl: microchip-sgpio: Put fwnode in error case during ->probe()Andy Shevchenko1-1/+3
device_for_each_child_node() bumps a reference counting of a returned variable. We have to balance it whenever we return to the caller. Fixes: 7e5ea974e61c ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO") Cc: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210606191940.29312-1-andy.shevchenko@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-12Merge tag 'renesas-pinctrl-for-v5.14-tag2' of ↵Linus Walleij6-80/+1844
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.14 (take two) - Add bias support for the R-Car H2, V2H, E2, V3M, and V3H, and RZ/G1C, RZ/G1H, and RZ/G1E SoCs.
2021-06-12pinctrl: mcp23s08: Add optional reset GPIOAndreas Kaessens2-0/+4
The MCP23x port expander RESET# line can be connected to a host GPIO. The optional reset-gpio must be set to LOW if the reset is asserted at probing time. On page 5 in the datasheet [0] the "Device Active After Reset high" time is specified at 0 µs. Therefore no waiting is needed after the reset transition. [0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf Signed-off-by: Andreas Kaessens <akaessens@gmail.com> Signed-off-by: Darian Biastoch <d.biastoch@gmail.com> Link: https://lore.kernel.org/r/20210610132438.3085841-1-akaessens@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2021-06-09Merge tag 'intel-pinctrl-v5.14-1' of ↵Linus Walleij1-0/+1
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.14-1 * Enabling pin controller on Intel Alder Lake-M The following is an automated git shortlog grouped by driver: tigerlake: - Add Alder Lake-M ACPI ID
2021-06-09pinctrl: mediatek: fix mode encodingMatthias Brugger1-2/+2
Pin modes are encoded in the SoC data structure. Use that value to set IES SMT. Cc: Fabien Parent <fparent@baylibre.com> Cc: Sean Wang <sean.wang@kernel.org> Cc: Mattijs Korpershoek <mkorpershoek@baylibre.com> Cc: linux-mediatek@lists.infradead.org Fixes: 696beef77521 ("pinctrl: mediatek: move bit assignment") Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com> Link: https://lore.kernel.org/r/20210608150656.29007-1-matthias.bgg@kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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