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2020-08-13eeprom: at25: Split reads into chunks and cap write sizeBrad Bishop1-40/+54
Make use of spi_max_transfer_size to avoid requesting transfers that are too large for some spi controllers. OpenBMC-Staging-Count: 1 Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-13spi: fsi: Check mux status before transfersEddie James1-13/+27
The SPI controllers are not accessible if the mux isn't set. Therefore, check the mux status before starting a transfer and fail out if it isn't set. OpenBMC-Staging-Count: 1 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-13spi: fsi: Implement restricted size for certain controllersEddie James1-12/+53
Some of the FSI-attached SPI controllers cannot use the loop command in programming the sequencer due to security requirements. Add a boolean devicetree property that describes this condition and restrict the size for these controllers. Also, add more transfers directly in the sequence up to the length of the sequence register. OpenBMC-Staging-Count: 1 Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver") Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-13spi: fsi: Fix use of the bneq+ sequencer instructionBrad Bishop1-3/+25
All of the switches in N2_count_control in the counter configuration are required to make the branch if not equal and increment command work. Set them when using bneq+. A side effect of this mode requires a dummy write to TDR when both transmitting and receiving otherwise the controller won't start shifting receive data. It is likely not possible to avoid TDR underrun errors in this mode and they are harmless, so do not check for them. OpenBMC-Staging-Count: 1 Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver") Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-13spi: fsi: Fix clock running too fastBrad Bishop1-1/+1
Use a clock divider tuned to a 200MHz FSI clock. Use of the previous divider at 200MHz results in corrupt data from endpoint devices. Ideally the clock divider would be calculated from the FSI clock, but that would require some significant work on the FSI driver. OpenBMC-Staging-Count: 1 Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-13spi: fsi: Handle 9 to 15 byte transfers lengthsBrad Bishop1-3/+3
The trailing <len> - 8 bytes of transfer data in this size range is no longer ignored. OpenBMC-Staging-Count: 1 Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver") Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-13mtd: spi-nor: sfdp: Revert "default to addr_width of 3 for configurable widths"Joel Stanley1-1/+0
This reverts commit f9acd7fa80be6ee14aecdc54429f2a48e56224e8 which breaks mounting of UBI volumes with the aspeed-smc driver: ubi0: default fastmap pool size: 25 ubi0: default fastmap WL pool size: 12 ubi0: attaching mtd3 ubi0: scanning is finished ubi0 error: ubi_read_volume_table: the layout volume was not found ubi0 error: ubi_attach_mtd_dev: failed to attach mtd3, error -22 Found by bisecting between v5.7 and v5.8. OpenBMC-Staging-Count: 1 Fixes: f9acd7fa80be ("mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths") Tested-by: Alexander A. Filippov <a.filippov@yadro.com> Tested-by: Adriana Kobylak <anoo@us.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06leds: pca955x: Add an IBM software implementation of the PCA9552 chipEddie James1-0/+8
IBM created an implementation of the PCA9552 on a PIC16F microcontroller. The I2C device addresses are different from the hardware PCA9552, so add a new compatible string and associated platform data to be able to probe this device. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Vishwanatha Subbanna <vishwa@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed-lpc-ctrl: Fix printf warningJoel Stanley1-4/+4
>> drivers/soc/aspeed/aspeed-lpc-ctrl.c:247:17: warning: format '%zu' expects argument of type 'size_t', but argument 3 has type 'resource_size_t' {aka 'unsigned int'} [-Wformat=] Documentation/core-api/printk-formats.rst suggests %pa should work for resouce_size_t, but it did not: %pa[p] 0x01234567 or 0x0123456789abcdef For printing a phys_addr_t type (and its derivatives, such as resource_size_t) which can vary based on build options, regardless of the width of the CPU data path. Instead cast to an integer which works as all aspeed processors are 32-bit. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed: xdma: Add reset ioctlEddie James1-0/+32
Users of the XDMA engine need a way to reset it if something goes wrong. Problems on the host side, or user error, such as incorrect host address, may result in the DMA operation never completing and no way to determine what went wrong. Therefore, add an ioctl to reset the engine so that users can recover in this situation. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed: xdma: Add user interfaceEddie James1-0/+218
This commits adds a miscdevice to provide a user interface to the XDMA engine. The interface provides the write operation to start DMA operations. The DMA parameters are passed as the data to the write call. The actual data to transfer is NOT passed through write. Note that both directions of DMA operation are accomplished through the write command; BMC to host and host to BMC. The XDMA driver reserves an area of physical memory for DMA operations, as the XDMA engine is restricted to accessing certain physical memory areas on some platforms. This memory forms a pool from which users can allocate pages for their usage with calls to mmap. The space allocated by a client will be the space used in the DMA operation. For an "upstream" (BMC to host) operation, the data in the client's area will be transferred to the host. For a "downstream" (host to BMC) operation, the host data will be placed in the client's memory area. Poll is also provided in order to determine when the DMA operation is complete for non-blocking IO. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed: Add XDMA Engine DriverEddie James3-0/+964
The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. This commit adds a driver to control the XDMA engine and adds functions to initialize the hardware and memory and start DMA operations. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06i2c: fsi: Prevent adding adapters for ports without dts nodesEddie James1-1/+6
Ports should be defined in the devicetree if they are to be enabled on the system. OpenBMC-Staging-Count: 3 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06pinctrl: aspeed: Describe the heartbeat function on ball Y23Andrew Jeffery1-1/+6
The default pinmux configuration for Y23 is to route a heartbeat to drive a LED. Previous revisions of the AST2600 datasheet did not include a description of this function OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06hwmon: (occ) Add new temperature sensor typeEddie James1-0/+65
The latest version of the On-Chip Controller (OCC) has a different format for the temperature sensor data. Add a new temperature sensor version to handle this data. OpenBMC-Staging-Count: 3 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06fsi: occ: Add support for P10Eddie James1-34/+92
The P10 OCC has a different SRAM address for the command and response buffers. In addition, the SBE commands to access the SRAM have changed format. Add versioning to the driver to handle these differences. OpenBMC-Staging-Count: 3 Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06misc: Add ASPEED KCS driver for MCTP purposesAndrew Jeffery3-0/+451
IBM have developed a vendor-defined MCTP binding that utilises LPC IO and FW interfaces to exchange MCTP messages. A KCS device in the IO space is used to send single-byte control messages initialising the MCTP channel and exchanging ownership of data buffers. This driver exposes the KCS message stream to userspace, allowing an MCTP-capable application to manipulate the data exposed via the FW space. OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600Joel Stanley1-0/+17
The ast2600 disables the mapping of AHB memory regions by default, only allowing the LPC window to point to SPI NOR. In order to point the window to any AHB address, an ast2600 specific bit must be toggled. OpenBMC-Staging-Count: 3 Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06hwmon: Add PECI dimmtemp driverJae Hyun Yoo3-0/+440
This commit adds PECI dimmtemp hwmon driver. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06hwmon: Add PECI cputemp driverJae Hyun Yoo4-0/+535
This commit adds PECI cputemp hwmon driver. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mfd: intel-peci-client: Add Intel PECI client driverJae Hyun Yoo3-0/+166
This commit adds Intel PECI client driver. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06peci: npcm: add NPCM PECI driverTomer Maimon3-0/+421
Add support for the Nuvoton NPCM BMC hardware to the Platform Environment Control Interface (PECI) subsystem. OpenBMC-Staging-Count: 3 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06peci: Add Aspeed PECI adapter driverJae Hyun Yoo3-0/+499
This commit adds Aspeed PECI adapter driver for Aspeed AST24xx/25xx/26xx SoCs. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06peci: Add support for PECI bus driver coreJae Hyun Yoo8-0/+2500
This commit adds driver implementation for PECI bus core into linux driver framework. PECI (Platform Environment Control Interface) is a one-wire bus interface that provides a communication channel from Intel processors and chipset components to external monitoring or control devices. PECI is designed to support the following sideband functions: * Processor and DRAM thermal management - Processor fan speed control is managed by comparing Digital Thermal Sensor (DTS) thermal readings acquired via PECI against the processor-specific fan speed control reference point, or TCONTROL. Both TCONTROL and DTS thermal readings are accessible via the processor PECI client. These variables are referenced to a common temperature, the TCC activation point, and are both defined as negative offsets from that reference. - PECI based access to the processor package configuration space provides a means for Baseboard Management Controllers (BMC) or other platform management devices to actively manage the processor and memory power and thermal features. * Platform Manageability - Platform manageability functions including thermal, power, and error monitoring. Note that platform 'power' management includes monitoring and control for both the processor and DRAM subsystem to assist with data center power limiting. - PECI allows read access to certain error registers in the processor MSR space and status monitoring registers in the PCI configuration space within the processor and downstream devices. - PECI permits writes to certain registers in the processor PCI configuration space. * Processor Interface Tuning and Diagnostics - Processor interface tuning and diagnostics capabilities (Intel Interconnect BIST). The processors Intel Interconnect Built In Self Test (Intel IBIST) allows for infield diagnostic capabilities in the Intel UPI and memory controller interfaces. PECI provides a port to execute these diagnostics via its PCI Configuration read and write capabilities. * Failure Analysis - Output the state of the processor after a failure for analysis via Crashdump. PECI uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple. The interface design was optimized for interfacing between an Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information. This implementation provides the basic framework to add PECI extensions to the Linux bus and device models. A hardware specific 'Adapter' driver can be attached to the PECI bus to provide sideband functions described above. It is also possible to access all devices on an adapter from userspace through the /dev interface. A device specific 'Client' driver also can be attached to the PECI bus so each processor client's features can be supported by the 'Client' driver through an adapter connection in the bus. OpenBMC-Staging-Count: 3 Signed-off-by: Jason M Biils <jason.m.bills@linux.intel.com> Signed-off-by: Yunge Zhu <yunge.zhu@linux.intel.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: James Feist <james.feist@linux.intel.com> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06clk: ast2600: enable BCLK for PCI/PCIe bus alwaysJae Hyun Yoo1-1/+1
BCLK for PCI/PCIe bus should be enabled always with having the CLK_IS_CRITICAL flag otherwise it will be disabled at kernel late initcall phase as an unused clock, and eventually it causes unexpected behavior on BMC features that are connected to the host through PCI/PCIe bus. OpenBMC-Staging-Count: 3 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed: Fail probe of lpc-ctrl if reserved memory is not alignedAndrew Jeffery1-0/+13
Alignment is a hardware constraint of the LPC2AHB bridge, and misaligned reserved memory will present as corrupted data. OpenBMC-Staging-Count: 4 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06pinctrl: aspeed: Improve debug outputAndrew Jeffery1-3/+22
We need to iterate over each pin in a group for a function and disable higher priority mux configurations on the pin before finally muxing the relevant function's signal. With the current debug output it is hard to track what register output is relevant to which operation, so break up the actions in the debug output by providing some more context. Before: [ 5.446656] aspeed-g6-pinctrl 1e6e2000.syscon:pinctrl: request pin 37 (B26) for 1e780000.gpio:341 [ 5.447377] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.447854] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.448340] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 After: [ 5.298053] Muxing pin 37 for GPIO [ 5.298294] Disabling signal NRI4 for NRI4 [ 5.298593] Want SCU414[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.298983] Disabling signal RGMII4RXD1 for RGMII4 [ 5.299309] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.299694] Disabling signal RMII4RXD1 for RMII4 [ 5.300014] Want SCU4B4[0x00000020]=0x1, got 0x0 from 0x00000000 [ 5.300396] Enabling signal GPIOE5 for GPIOE5 [ 5.300687] Muxed pin 37 as GPIOE5 OpenBMC-Staging-Count: 4 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06reset: simple: Add AST2600 compatibility stringBrad Bishop1-0/+1
The AST2600 SoC contains the same LPC register set as the AST2500. OpenBMC-Staging-Count: 4 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06ipmi: aspeed-g6: Add compatible stringsBrad Bishop2-0/+2
The AST2600 SoC contains the same IPMI (BT/KCS) devices as the AST2500. OpenBMC-Staging-Count: 4 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed: lpc: Add G6 compatible stringsBrad Bishop2-0/+3
The AST2600(G6) has the same lpc-ctrl and lpc-snoop devices as the AST2500. OpenBMC-Staging-Count: 4 Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06edac: npcm: Add Nuvoton NPCM7xx EDAC driverGeorge Hung3-0/+429
Add support for the Nuvoton NPCM7xx SoC EDAC driver NPCM7xx ECC datasheet from nuvoton.israel-Poleg: "Cadence DDR Controller User’s Manual For DDR3 & DDR4 Memories" Tested: Forcing an ECC error event Write a value to the xor_check_bits parameter that will trigger an ECC event once that word is read For example, to force a single-bit correctable error on bit 0 of the user-word space shown, write 0x75 into that byte of the xor_check_bits parameter and then assert fwc (force write check) bit to 'b1' (mem base: 0xf0824000, xor_check_bits reg addr: 0x178) $ devmem 0xf0824178 32 0x7501 To force a double-bit un-correctable error for the user-word space, write 0x03 into that byte of the xor_check_bits parameter $ devmem 0xf0824178 32 0x301 OpenBMC-Staging-Count: 6 Signed-off-by: George Hung <george.hung@quantatw.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06net: npcm: add NPCM7xx Ethernet MAC controllerTomer Maimon5-0/+2128
Add Nuvoton BMC NPCM7xx Ethernet MAC controller (EMC) driver. OpenBMC-Staging-Count: 8 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06misc: mbox: add npcm7xx pci mailbox driverTomer Maimon3-0/+296
Add Nuvoton BMC NPCM7XX PCI Mailbox driver. OpenBMC-Staging-Count: 8 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [v5.0: Fix access_ok for API change] Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06misc: npcm7xx-lpc-bpc: add NPCM7xx BIOS post code driverTomer Maimon3-0/+403
Add NPCM7xx BIOS post code (BPC) driver, the BPC monitoring two I/O address written by the host on the LPC. OpenBMC-Staging-Count: 8 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06/dev/mem: add a devmem kernel parameter to activate the deviceCédric Le Goater2-0/+20
For security reasons, some configuration needs to run without /dev/mem but on some occasions, to debug HW for instance, it's still useful to be able to reboot the system with access to physical memory. Add a kernel parameter which activates the /dev/mem device only when 'mem.devmem' is enabled. OpenBMC-Staging-Count: 9 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06soc: aspeed: Miscellaneous control interfacesAndrew Jeffery3-0/+199
The ASPEED BMC SoCs have many knobs and switches that are sometimes design-specific and often defy any approach to unify them under an existing subsystem. Add a driver to translate a devicetree table into sysfs entries to expose bits and fields for manipulation from userspace. This encompasses concepts from scratch registers to boolean conditions to enable or disable host interface features. OpenBMC-Staging-Count: 11 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06pmbus (max31785): Wrap all I2C accessors in one-shot failure handlersAndrew Jeffery1-42/+165
The MAX31785(A) has shown erratic behaviour across multiple system designs, unexpectedly clock stretching and NAKing transactions. Perform a one-shot retry if necessary for all access attempts. OpenBMC-Staging-Count: 12 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06pmbus (core): One-shot retries for failure to set pageAndrew Jeffery1-2/+12
Work around the shonky behaviour seen with the MAX31785 where we fail to set the page register in some circumstances. There's no real elegant way to do this. We can propagate the error up, but that forces us to retry the operation way up the call tree in any number of places. It also forces callers to split out pmbus_set_page() from the pmbus_{read,write}_{byte,word}_data() functions in order to differentiate between a failure to set the page and a failure to read a register (that might not exist, in which case an error is anticiptated). OpenBMC-Staging-Count: 12 Cc: Eddie James <eajames@linux.vnet.ibm.com> Cc: Matt Spinler <mspinler@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06pmbus (core): Use driver callbacks in pmbus_get_fan_rate()Andrew Jeffery1-4/+4
The driver may have overridden the pmbus_read_byte_data() callback, so make sure we use that to achieve expected behaviour. This helps in the MAX31785 case where we may need to perform a one-shot retry of transfers in the face of a failure. OpenBMC-Staging-Count: 12 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06pmbus (max31785): Add support for devicetree configurationAndrew Jeffery1-0/+318
OpenBMC-Staging-Count: 12 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06spi-nor: aspeed-smc: Detect 4b opcodes differentlyCédric Le Goater1-1/+3
SNOR_F_4B_OPCODES and related defines were removed from spi-nor.h in 829ec6408dc5 ("mtd: spi-nor: Trim what is exposed in spi-nor.h"). Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: fix options for mx66l51235fAlexander Amelkin1-1/+1
Currently in driver spi-nor there is a line for mx66l51235l. According to Macronix site there is no such part number. The chip detected as such is actually mx66l51235f. According to the datasheet for mx66l51235f, "The device default is in 24-bit address mode" (section 9-10). Hence we removed SPI_NOR_4B_OPCODES option with this commit. OpenBMC-Staging-Count: 10 Fixes: d342b6a973af ("mtd: spi-nor: enable 4B opcodes for mx66l51235l") Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Lei YU <mine260309@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Disable zero size segments on the AST2600Cédric Le Goater1-2/+6
A disabled segment for a CS should have a zero value in its segment register. The driver was generating an incorrect value which overlapped with segment CS0. Accesses to the flash were blocked and Linux hung. OpenBMC-Staging-Count: 4 Fixes: 3635b880313a ("mtd: spi-nor: aspeed: add initial support for ast2600") Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: fix training of multiple CS on the AST2600Cédric Le Goater1-4/+5
Each CE has its own read timing compensation register. OpenBMC-Staging-Count: 4 Fixes: c62871befcdb ("mtd: spi-nor: aspeed: add support for AST2600 training") Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: add support for AST2600 trainingCédric Le Goater1-0/+68
The training consists of finding the appropriate read timing delays for the HCLK dividers 2, 3, 4, and 5 and store the results in the Read Timing Compensation register. The previous SoC AST2500 and AST2400 were covering a broader HCLK range [ 1 - 5 ] because the AHB frequency was lower. The algorithm first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find a breaking point. This selects the default clock frequency for the CEx control register. The current settings are bit optimistic as we pick the first delay giving good results. A safer approach would be to determine an interval and choose the middle value. We might change the approach depending on the results on other systems. Only CS0 is taken into account for the moment. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: check upper freq limit when doing trainingCédric Le Goater1-1/+1
OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Introduce a HCLK mask for trainingCédric Le Goater1-1/+6
The AST2600 handles more HCLK divisors than its predecessors. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Introduce training operations per platformCédric Le Goater1-4/+22
The read timing compensation register is different on the AST2600 and training will be slightly more complex. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: Check for disabled segments on the AST2600Cédric Le Goater1-4/+11
The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. For multiple CS, we will need firmware or a DT property to reopen the flash AHB window. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
2020-08-06mtd: spi-nor: aspeed: add initial support for ast2600Cédric Le Goater1-0/+73
The Segment Registers of the AST2600 have a different encoding. A 1MB unit is used and the address range of a flash SPI slave is encoded with offsets in the overall controller window. The previous SoC AST2400 and AST2500 used absolute addresses. Only bits [27:20] are relevant and the end address is an upper bound limit. SPI training yet to come. OpenBMC-Staging-Count: 4 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>
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