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When an arbitration loss happens in a multi-master bus, driver
drops the packet induce I2C subsystem to retry the transaction
by returning -EAGAIN. During this handling, tx_ack comes along
sometimes and it causes this this garbage printing
out:
aspeed-i2c-bus 1e78a400.i2c-bus: irq handled != irq. expected 0x00000009, but was 0x00000008
To fix this issue, this commit adds the tx_ack flag clearing into
the arbitration loss handling logic.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit refines clock settings with cherry picking the latest
code from Aspeed SDK v00.05.05
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Modifying the mailbox driver to use FIFO queue while using interrupt.
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
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This commit includes additions/changes in driver code
to support 9 PWM outputs and 9 fan tachometer inputs for
ast2600 as per archer city usage
Signed-off-by: Ayushi Smriti <smriti.ayushi@intel.com>
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The ftgmac100_open function initializes state for the NCSI
channel. The get link settings function does not return this
data. This caused the link speed, and the duplex value to be returned
incorrectly by the PHY driver (0 Mbps, and duplex off).
Update the driver to return either the PHY settings when not using
NCSI, or the NCSI values that were assigned when the driver is opened.
Signed-off-by: Johnathan Mantey <johnathanx.mantey@intel.com>
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This commit adds quick fix for cases of run time registration
through sysfs. It should be fixed later by adding parsing code for
ipmb_id instead.
This is a temporary fix. Do not upstream it.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds spi driver quad io support for AST2600
Note:- Removed n25q00 Quad I/O support for the time being due to clock issue
with chip 'Micron 8UA15 - rw182 (128MB)' while enabling Quad I/O mode.
Signed-off-by: arun-pm <arun.p.m@linux.intel.com>
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Tested:
1. Config baud rate to 921600 in BIOS setup page
2. BMC could change env variable "hostserialcfg" to 1.
3. BMC is force to reboot and SPA baud rate is changed to 921600 successfully.
4. It is same for back to 115200.
Signed-off-by: Kuiying Wang <kuiying.wang@intel.com>
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To support continous eSPI H/W handshaking, this patch enables
ESPICLK always so that there discontinuity of eSPI handshaking while
boot BMC.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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AST2600 makes a garbage interrupt which is decribed as 'reserved'
in datasheet so filter them out.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Add the pwm_tacho driver from Aspeed to get pwm working until an
upstream PWM/Tacho driver is available. This was copied from the v5.02
BSP from Aspeed.
Signed-off-by: Vernon Mauery <vernon.mauery@intel.com>
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Since we enabled I2C busses in u-boot, we need to disable the I2C
bus and clear all garbage interrupts when kernel probes the bus.
This commit refines the initialization flow by adding a bus reset
at the beginning of probe function and by moving bus init function
after interrupt handling setup.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Introduces new attribute to Mass Storage Gadget ConfigFS : stats.
It's read-only attribute which contains statistics of read/write operations
based on LUN transaction counters (IO number and bytes transferred).
Goal is to provide a way to observe whether simulated device is actually
used by host. Statistics on hosted file / nbd level are not always viable
due to page cache having severe impact on actual IO statistics.
This attribute should provide information about host IO on USB Gadget as
close to endpoint as possible.
Attribute is tied completely to configFS implementation and it's lifecycle
is managed by Kernel and user. Driver implements a handler which populates
output buffer on read.
Tests performed:
- mounted USB Mass Storage gadget, new attribute showed up in gadget tree
- attribute was monitored for changes during IO performed on host machine
- removed device, attribute (along with other device attributes) was gone
Signed-off-by: Adrian Ambrożewicz <adrian.ambrozewicz@intel.com>
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This commit adds two more attirbutes to reflect MFR_SPECIFIC bit in
the STATUS_WORD and 'Unit Off For Insufficient Input Voltage' bit in
the STATUS_INPUT into 'fault' and 'beep' attributes respectively.
The attributes will be enumerated as 'inX_fault' and 'inX_beep' in
a 'vin' group.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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If a peer master sends messages too quickly before it processes
previous slave DMA data handling, this indicator will be set. It's
just a indicator and driver can't recover this case so just ignore
it.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds I2C H/W timeout support.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds general call support into Aspeed I2C driver.
This is downstream only customization so it should not go into
upstream.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds DMA mode transfer support.
Only AST2500 supports DMA mode under some limitations:
I2C is sharing the DMA H/W with UHCI host controller and MCTP
controller. Since those controllers operate with DMA mode only, I2C
has to use buffer mode or byte mode instead if one of those
controllers is enabled. Also make sure that if SD/eMMC or Port80
snoop uses DMA mode instead of PIO or FIFO respectively, I2C can't
use DMA mode.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Byte mode currently this driver uses makes lots of interrupt call
which isn't good for performance and it makes the driver very
timing sensitive. To improve performance of the driver, this commit
adds buffer mode transfer support which uses I2C SRAM buffer
instead of using a single byte buffer.
AST2400:
It has 2 KBytes (256 Bytes x 8 pages) of I2C SRAM buffer pool from
0x1e78a800 to 0x1e78afff that can be used for all busses with
buffer pool manipulation. To simplify implementation for supporting
both AST2400 and AST2500, it assigns each 128 Bytes per bus without
using buffer pool manipulation so total 1792 Bytes of I2C SRAM
buffer will be used.
AST2500:
It has 16 Bytes of individual I2C SRAM buffer per each bus and its
range is from 0x1e78a200 to 0x1e78a2df, so it doesn't have 'buffer
page selection' bit field in the Function control register, and
neither 'base address pointer' bit field in the Pool buffer control
register it has. To simplify implementation for supporting both
AST2400 and AST2500, it writes zeros on those register bit fields
but it's okay because it does nothing in AST2500.
It provides buffer based master and slave data transfer.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Driver adds support of Aspeed 2400-2600 series SOC JTAG master controller.
Driver implements the following jtag ops:
- freq_get;
- freq_set;
- status_get;
- status_set
- xfer;
- mode_set;
- bitbang;
- enable;
- disable;
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
It has also been tested on Intel system using Aspeed 25xx SoC
for JTAG communication.
Tested on Intel system using Aspeed 26xx SoC for JTAG communication.
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Joel Stanley <joel@jms.id.au>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Andrew Jeffery <andrew@aj.id.au>
Cc: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Steven Filary <steven.a.filary@intel.com>
Cc: Vadim Pasternak <vadimp@mellanox.com>
Cc: Amithash Prasad <amithash@fb.com>
Cc: Patrick Williams <patrickw3@fb.com>
Cc: Rgrs <rgrs@protonmail.com>
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JTAG class driver provide infrastructure to support hardware/software
JTAG platform drivers. It provide user layer API interface for flashing
and debugging external devices which equipped with JTAG interface
using standard transactions.
Driver exposes set of IOCTL to user space for:
- XFER:
SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
- GIOCSTATUS read the current TAPC state of the JTAG controller
- SIOCSTATE Forces the JTAG TAPC to go into a particular state.
- SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
- IOCBITBANG for low level control of JTAG signals.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Signed-off-by: Ernesto Corona <ernesto.corona@intel.com>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Boris Brezillon <bbrezillon@kernel.org>
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Johan Hovold <johan@kernel.org>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Joel Stanley <joel@jms.id.au>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Kees Cook <keescook@chromium.org>
Cc: William Breathitt Gray <vilhelm.gray@gmail.com>
Cc: Federico Vaga <federico.vaga@cern.ch>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: Christian Gromm <christian.gromm@microchip.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Yiwei Zhang <zzyiwei@google.com>
Cc: Alessandro Rubini <rubini@gnudd.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Steven Filary <steven.a.filary@intel.com>
Cc: Vadim Pasternak <vadimp@mellanox.com>
Cc: Amithash Prasad <amithash@fb.com>
Cc: Patrick Williams <patrickw3@fb.com>
Cc: Rgrs <rgrs@protonmail.com>
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HID events can be sent even when the host disconnects the HID
device according to the current graphic mode. For an example, if
KVM mouse events are sent when the host is in text mode, queueing
of end point messages will be dropped with this message:
configfs-gadget gadget: usb_ep_queue error on int endpoint -108
This case is very usual case in BMC since BMC can control power
status of the host, so this commit suppress the error printing outs
with making HID gadget driver drop events quietly in the case.
This should be a downstream only customization. Do not upstream it.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds a checking code when it gets -EPROBE_DEFER while
getting a clock resource. In this case it doesn't need to print
out an error message because the probing will be re-visited.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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If LPC KCS driver is registered ahead of lpc-ctrl module, LPC KCS
block will be enabled without heart beating of LCLK until lpc-ctrl
enables the LCLK. This issue causes improper handling on host
interrupts when the host sends interrupt in that time frame. Then
kernel eventually forcibly disables the interrupt with dumping
stack and printing a 'nobody cared this irq' message out.
To prevent this issue, all LPC sub-nodes should enable LCLK
individually so this patch adds clock control logic into the LPC
KCS driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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If LPC BT driver is registered ahead of lpc-ctrl module, LPC BT
block will be enabled without heart beating of LCLK until lpc-ctrl
enables the LCLK. This issue causes improper handling on host
interrupts when the host sends interrupt in that time frame. Then
kernel eventually forcibly disables the interrupt with dumping
stack and printing a 'nobody cared this irq' message out.
To prevent this issue, all LPC sub-nodes should enable LCLK
individually so this patch adds clock control logic into the LPC
BT driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Signed-off-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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BMC uses I2C bus 7 as a PMBus channel to communicate with PSUs,
also ME uses this bus as SMLink to control PSUs so this bus is
managed by multi-masters. In this use case, some arbitration errors
are expected so we need to add retry logic. And PMBus subsystem
uses I2C bus in kernel internally so retry logic should be
supported in kernel level.
To support the use case, this commit adds 'bus-timeout-ms' and
'#retries' device tree properties to set the bus specific
parameters at kernel boot time without using any additional ioctls
from user space.
This patch would not be accepted by I2C maintainer in linux
upstream because he doesn't like adding these legacy properties
into device tree, so keep it only in downstream.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds mux hold/unhold message types to support extended
mux control for IPMB and MCTP devices. A hold or an unhold message
can be added at the end of I2C message stream wrapped by
repeated-start, also can be used as a single message independantly.
This mux hold/unhold message will be delivered throughout all mux
levels in the path. Means that if it goes to multi-level mux path,
all muxes will be held/unheld by this message.
1. Hold message
struct i2c_msg msg;
uint16_t timeout = 5000; // timeout in ms. 5 secs in this example.
msg.addr = 0x0; // any value can be used. addr will be ignored in this packet.
msg.flags = I2C_M_HOLD; // set this flag to indicate it's a hold message.
msg.len = sizeof(uint16_t); // timeout value will be delivered using two bytes buffer.
msg.buf = (uint8_t *)&timeout; // set timeout value.
2. Unhold message
struct i2c_msg msg;
uint16_t timeout = 0; // set 0 for an unhold message.
msg.addr = 0x0; // any value can be used. addr will be ignored in this packet.
msg.flags = I2C_M_HOLD; // set this flag to indicate it's an unhold message.
msg.len = sizeof(uint16_t); // timeout value will be delivered using two bytes buffer.
msg.buf = (uint8_t *)&timeout; // set timeout value.
This unhold message can be delivered to a mux adapter even when
a bus is locked so that any holding state can be unheld
immediately by invoking this unhold message.
This patch would not be welcomed from upstream so it should be kept
in downstream only.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds Aspeed PWM driver which uses timer pulse output
feature in Aspeed SoCs. The timer IP is derived from Faraday
Technologies FTTMR010 IP but has some customized register
structure changes only for Aspeed SoCs.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Implement a memory driver for BMC to access VGA share memory.
The driver is used by MDRV2. In MDRV2 BIOS will send whole
SMBIOS table to VGA memory and BMC can get the table from VGA
memory through this driver.
Signed-off-by: Cheng C Yang <cheng.c.yang@intel.com>
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In order to support high speed baud rate(921600 bps),
the default UART clock(24MHz) needs to be switched
to 192MHz(from USB2.0 port1 PHY).
Create a new 192M Hz clock and assign it to uart,
based on uart clock source configuration in SCU4C.
bootloader(u-boot) will set SCU4C based on the environment configuration
Signed-off-by: Yong Li <yong.b.li@linux.intel.com>
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This commit enables dump debug of master and slave I2C drivers.
This is only for downstream debug purpose so it shouldn't go to
the upstream.
Usage (in case of bus 5 for an example):
echo 5 > /sys/module/i2c_aspeed/parameters/dump_debug_bus_id
echo 1 > /sys/module/i2c_aspeed/parameters/dump_debug
echo 5 > /sys/module/i2c_slave_mqueue/parameters/dump_debug_bus_id
echo 1 > /sys/module/i2c_slave_mqueue/parameters/dump_debug
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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Add lpc sio device driver for AST2500/2400
Signed-off-by: Yong Li <yong.b.li@intel.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
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This commit adds back the lpc mbox driver which was removed from
the openbmc linux dev-5.2 tree.
This driver should be rewritten later.
Signed-off-by: Cyril Bur <cyrilbur@gmail.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@intel.com>
Signed-off-by: Arun P. Mohanan <arun.p.m@linux.intel.com>
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Some protocols over I2C are designed for bi-directional transferring
messages by using I2C Master Write protocol. Like the MCTP (Management
Component Transport Protocol) and IPMB (Intelligent Platform Management
Bus), they both require that the userspace can receive messages from
I2C dirvers under slave mode.
This new slave mqueue backend is used to receive and queue messages, it
will exposes these messages to userspace by sysfs bin file.
Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com>
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Change it from max to 58%
Signed-off-by: James Feist <james.feist@linux.intel.com>
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The pass-through input GPIOs cannot be monitored because when
requested, pass-through is disabled which causes a change on the
pass-through output.
The SIO GPIOs cannot be monitored because when requested, the
request is rejected based on the value of the ACPI strap.
This change removes the register check condition from the pass-
through and desired SIO GPIOs so they can be requsted and
monitored from power control.
Tested:
For pass-through, I used gpioset to hold a request on the input
GPIOs and confirmed that pass-through remained enabled.
For SIO, I used gpioget to confirm that I can successfully request
and read the GPIO value.
Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
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This change adds a gpio_disable_free() implementation that checks
if the GPIO being freed is GPIOE1 (33) or GPIOE3 (35) and will
re-enable the pass-through mux.
Tested:
Requested GPIOs 33 and 35 and used devmem to check that pass-through
was disabled. Then freed them and checked that pass-through was
enabled again.
Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
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peci-cpupower reads CPU energy counter through peci
and computes average power in mW since last read.
Signed-off-by: ZhikuiRen <zhikui.ren@intel.com>
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peci_get_xfer_msg() returns NULL on failure, not an ERR_PTR. Also
avoid calling kfree() on an ERR_PTR.
Fixes: 90ddc4e972b5 ("peci: Add support for PECI bus driver core")
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Reviewed-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20200926212734.23836-2-zev@bewilderbeest.net
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This commit adds PECI dimmtemp hwmon driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: James Feist <james.feist@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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This commit adds PECI cputemp hwmon driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: James Feist <james.feist@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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This commit adds Intel PECI client driver.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
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Add support for the Nuvoton NPCM BMC hardware to the Platform
Environment Control Interface (PECI) subsystem.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
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This commit adds Aspeed PECI adapter driver for Aspeed
AST24xx/25xx/26xx SoCs.
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: James Feist <james.feist@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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This commit adds driver implementation for PECI bus core into linux
driver framework.
PECI (Platform Environment Control Interface) is a one-wire bus interface
that provides a communication channel from Intel processors and chipset
components to external monitoring or control devices. PECI is designed to
support the following sideband functions:
* Processor and DRAM thermal management
- Processor fan speed control is managed by comparing Digital Thermal
Sensor (DTS) thermal readings acquired via PECI against the
processor-specific fan speed control reference point, or TCONTROL. Both
TCONTROL and DTS thermal readings are accessible via the processor PECI
client. These variables are referenced to a common temperature, the TCC
activation point, and are both defined as negative offsets from that
reference.
- PECI based access to the processor package configuration space provides
a means for Baseboard Management Controllers (BMC) or other platform
management devices to actively manage the processor and memory power
and thermal features.
* Platform Manageability
- Platform manageability functions including thermal, power, and error
monitoring. Note that platform 'power' management includes monitoring
and control for both the processor and DRAM subsystem to assist with
data center power limiting.
- PECI allows read access to certain error registers in the processor MSR
space and status monitoring registers in the PCI configuration space
within the processor and downstream devices.
- PECI permits writes to certain registers in the processor PCI
configuration space.
* Processor Interface Tuning and Diagnostics
- Processor interface tuning and diagnostics capabilities
(Intel Interconnect BIST). The processors Intel Interconnect Built In
Self Test (Intel IBIST) allows for infield diagnostic capabilities in
the Intel UPI and memory controller interfaces. PECI provides a port to
execute these diagnostics via its PCI Configuration read and write
capabilities.
* Failure Analysis
- Output the state of the processor after a failure for analysis via
Crashdump.
PECI uses a single wire for self-clocking and data transfer. The bus
requires no additional control lines. The physical layer is a self-clocked
one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on
whether the bit value is a logic '0' or logic '1'. PECI also includes
variable data transfer rate established with every message. In this way, it
is highly flexible even though underlying logic is simple.
The interface design was optimized for interfacing between an Intel
processor and chipset components in both single processor and multiple
processor environments. The single wire interface provides low board
routing overhead for the multiple load connections in the congested routing
area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability
to transfer critical device operating conditions and configuration
information.
This implementation provides the basic framework to add PECI extensions to
the Linux bus and device models. A hardware specific 'Adapter' driver can
be attached to the PECI bus to provide sideband functions described above.
It is also possible to access all devices on an adapter from userspace
through the /dev interface. A device specific 'Client' driver also can be
attached to the PECI bus so each processor client's features can be
supported by the 'Client' driver through an adapter connection in the bus.
Signed-off-by: Jason M Biils <jason.m.bills@linux.intel.com>
Signed-off-by: Yunge Zhu <yunge.zhu@linux.intel.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Reviewed-by: James Feist <james.feist@linux.intel.com>
Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com>
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This change allows LTD and RTD inputs to be configured via
device tree bindings. If the DT bindings are not present or
invalid, the input configuration is not modified and left at
HW defaults.
OpenBMC-Staging-Count: 1
Signed-off-by: Oskar Senft <osk@google.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20211020164213.174597-2-osk@google.com
Signed-off-by: Joel Stanley <joel@jms.id.au>
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The build changes relating to the routing driver were lost when
backporting.
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Add driver support for the UART routing control. Users can perform
runtime configuration of the RX muxes among the UART controllers and
the UART IO pins.
The sysfs interface is also exported for the convenience of routing paths
check and update.
Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Tested-by: Lei YU <yulei.sh@bytedance.com>
Link: https://lore.kernel.org/r/20210927023053.6728-5-chiawei_wang@aspeedtech.com
Link: https://lore.kernel.org/r/20211022000616.481772-1-joel@jms.id.au'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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There was nothing to protect multiple SPI controllers on the same FSI2SPI
device from being accessed through the FSI2SPI device at the same time.
For example, multiple writes to the command and data registers might occur
for different SPI controllers, resulting in complete chaos in the SPI
engine. To prevent this, add a FSI2SPI device level mutex and lock it in
the SPI register read and write functions.
OpenBMC-Staging-Count: 1
Fixes: bbb6b2f9865b ("spi: Add FSI-attached SPI controller driver")
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20211026193327.52420-1-eajames@linux.ibm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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Print the SPI engine status register when an error is detected. This
will aid tremendously in debugging failed transactions.
OpenBMC-Staging-Count: 2
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://lore.kernel.org/r/20211004195149.29759-1-eajames@linux.ibm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
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