From 99e71543521ce1646fb8d3de1e68fe56a3ba5f8e Mon Sep 17 00:00:00 2001 From: Yisheng Xie Date: Thu, 31 May 2018 19:11:13 +0800 Subject: clk: bcm2835: use match_string() helper match_string() returns the index of an array for a matching string, which can be used instead of open coded variant. Reviewed-by: Eric Anholt Cc: Michael Turquette Cc: Eric Anholt Cc: Stefan Wahren Cc: linux-clk@vger.kernel.org Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Yisheng Xie Signed-off-by: Stephen Boyd --- drivers/clk/bcm/clk-bcm2835.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index fa0d5c8611a0..5e1843321bc8 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -1395,7 +1395,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, struct bcm2835_clock *clock; struct clk_init_data init; const char *parents[1 << CM_SRC_BITS]; - size_t i, j; + size_t i; int ret; /* @@ -1405,12 +1405,11 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, for (i = 0; i < data->num_mux_parents; i++) { parents[i] = data->parents[i]; - for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) { - if (strcmp(parents[i], cprman_parent_names[j]) == 0) { - parents[i] = cprman->real_parent_names[j]; - break; - } - } + ret = match_string(cprman_parent_names, + ARRAY_SIZE(cprman_parent_names), + parents[i]); + if (ret >= 0) + parents[i] = cprman->real_parent_names[ret]; } memset(&init, 0, sizeof(init)); -- cgit v1.2.3 From d6347445c49637237c5316fd76833be1d0ffa695 Mon Sep 17 00:00:00 2001 From: Yisheng Xie Date: Thu, 31 May 2018 19:11:14 +0800 Subject: clk: use match_string() helper match_string() returns the index of an array for a matching string, which can be used instead of open coded variant. Cc: Michael Turquette Cc: linux-clk@vger.kernel.org Signed-off-by: Yisheng Xie Signed-off-by: Stephen Boyd --- drivers/clk/clk.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index ea67ac81c6f9..b7d1a5634164 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -2170,7 +2170,6 @@ void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent) bool clk_has_parent(struct clk *clk, struct clk *parent) { struct clk_core *core, *parent_core; - unsigned int i; /* NULL clocks should be nops, so return success if either is NULL. */ if (!clk || !parent) @@ -2183,11 +2182,8 @@ bool clk_has_parent(struct clk *clk, struct clk *parent) if (core->parent == parent_core) return true; - for (i = 0; i < core->num_parents; i++) - if (strcmp(core->parent_names[i], parent_core->name) == 0) - return true; - - return false; + return match_string(core->parent_names, core->num_parents, + parent_core->name) >= 0; } EXPORT_SYMBOL_GPL(clk_has_parent); -- cgit v1.2.3 From 7ef3844fc5198065dbe8776798206c10859d209e Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 20 May 2018 16:31:12 +0000 Subject: clk: ingenic: Add support for clocks whose gate bit is inverted Support the clocks which are gated when their gate bit is cleared instead of set. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/cgu.c | 5 +++-- drivers/clk/ingenic/cgu.h | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 56a712c9075f..4b31145eb8aa 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -43,7 +43,8 @@ static inline bool ingenic_cgu_gate_get(struct ingenic_cgu *cgu, const struct ingenic_cgu_gate_info *info) { - return readl(cgu->base + info->reg) & BIT(info->bit); + return !!(readl(cgu->base + info->reg) & BIT(info->bit)) + ^ info->clear_to_gate; } /** @@ -62,7 +63,7 @@ ingenic_cgu_gate_set(struct ingenic_cgu *cgu, { u32 clkgr = readl(cgu->base + info->reg); - if (val) + if (val ^ info->clear_to_gate) clkgr |= BIT(info->bit); else clkgr &= ~BIT(info->bit); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 9da34910bd80..4d2e3fad0e30 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -111,10 +111,12 @@ struct ingenic_cgu_fixdiv_info { * struct ingenic_cgu_gate_info - information about a clock gate * @reg: offset of the gate control register within the CGU * @bit: offset of the bit in the register that controls the gate + * @clear_to_gate: if set, the clock is gated when the bit is cleared */ struct ingenic_cgu_gate_info { unsigned reg; u8 bit; + bool clear_to_gate; }; /** -- cgit v1.2.3 From 261a831f042c906412099e8a4f73d954cb5370b4 Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 20 May 2018 16:31:13 +0000 Subject: clk: ingenic: Support specifying "wait for clock stable" delay Some clocks need a small delay after being ungated to run stable, as using them too soon might result in hardware lockups. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/cgu.c | 3 +++ drivers/clk/ingenic/cgu.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 4b31145eb8aa..5ef7d9ba2195 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -512,6 +512,9 @@ static int ingenic_clk_enable(struct clk_hw *hw) spin_lock_irqsave(&cgu->lock, flags); ingenic_cgu_gate_set(cgu, &clk_info->gate, false); spin_unlock_irqrestore(&cgu->lock, flags); + + if (clk_info->gate.delay_us) + udelay(clk_info->gate.delay_us); } return 0; diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 4d2e3fad0e30..542192376ebf 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -112,11 +112,13 @@ struct ingenic_cgu_fixdiv_info { * @reg: offset of the gate control register within the CGU * @bit: offset of the bit in the register that controls the gate * @clear_to_gate: if set, the clock is gated when the bit is cleared + * @delay_us: delay in microseconds after which the clock is considered stable */ struct ingenic_cgu_gate_info { unsigned reg; u8 bit; bool clear_to_gate; + u16 delay_us; }; /** -- cgit v1.2.3 From 11b689a3e790791ceeb17e3fe25046ad56ac966d Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 20 May 2018 16:31:14 +0000 Subject: clk: ingenic: jz4770: Change OTG from custom to standard gated clock We now have the means to express the specificities of the OTG clock with the common CGU code. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/jz4770-cgu.c | 42 +++++----------------------------------- 1 file changed, 5 insertions(+), 37 deletions(-) diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index c78d369b9403..226c8016f6b0 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -42,7 +42,6 @@ /* bits within the OPCR register */ #define OPCR_SPENDH BIT(5) /* UHC PHY suspend */ -#define OPCR_SPENDN BIT(7) /* OTG PHY suspend */ /* bits within the USBPCR1 register */ #define USBPCR1_UHC_POWER BIT(5) /* UHC PHY power down */ @@ -83,37 +82,6 @@ static const struct clk_ops jz4770_uhc_phy_ops = { .is_enabled = jz4770_uhc_phy_is_enabled, }; -static int jz4770_otg_phy_enable(struct clk_hw *hw) -{ - void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; - - writel(readl(reg_opcr) | OPCR_SPENDN, reg_opcr); - - /* Wait for the clock to be stable */ - udelay(50); - return 0; -} - -static void jz4770_otg_phy_disable(struct clk_hw *hw) -{ - void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; - - writel(readl(reg_opcr) & ~OPCR_SPENDN, reg_opcr); -} - -static int jz4770_otg_phy_is_enabled(struct clk_hw *hw) -{ - void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; - - return !!(readl(reg_opcr) & OPCR_SPENDN); -} - -static const struct clk_ops jz4770_otg_phy_ops = { - .enable = jz4770_otg_phy_enable, - .disable = jz4770_otg_phy_disable, - .is_enabled = jz4770_otg_phy_is_enabled, -}; - static const s8 pll_od_encoding[8] = { 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3, }; @@ -410,6 +378,11 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .parents = { JZ4770_CLK_MMC2_MUX, }, .gate = { CGU_REG_CLKGR0, 12 }, }, + [JZ4770_CLK_OTG_PHY] = { + "usb_phy", CGU_CLK_GATE, + .parents = { JZ4770_CLK_OTG }, + .gate = { CGU_REG_OPCR, 7, true, 50 }, + }, /* Custom clocks */ @@ -418,11 +391,6 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .parents = { JZ4770_CLK_UHC, -1, -1, -1 }, .custom = { &jz4770_uhc_phy_ops }, }, - [JZ4770_CLK_OTG_PHY] = { - "usb_phy", CGU_CLK_CUSTOM, - .parents = { JZ4770_CLK_OTG, -1, -1, -1 }, - .custom = { &jz4770_otg_phy_ops }, - }, [JZ4770_CLK_EXT512] = { "ext/512", CGU_CLK_FIXDIV, -- cgit v1.2.3 From 45ba63a29fd9b8a461110185e3abc5b4c90b806a Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 20 May 2018 16:31:15 +0000 Subject: clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle When the main processor goes idle, by default its clock is stopped. However, this also stops the clock of the co-processor. Here, if the C1CLK clock is enabled, we disable this functionality. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/jz4770-cgu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 226c8016f6b0..a5ad69464e57 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -162,9 +162,10 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 }, }, [JZ4770_CLK_C1CLK] = { - "c1clk", CGU_CLK_DIV, + "c1clk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 }, + .gate = { CGU_REG_OPCR, 31, true }, // disable CCLK stop on idle }, [JZ4770_CLK_PCLK] = { "pclk", CGU_CLK_DIV, -- cgit v1.2.3 From a6523b6fb8b54bd53b63c1ca171bed7d9dd3f68e Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 20 May 2018 16:31:16 +0000 Subject: clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock This was broken before, because the AHB1 bus was enabled before the VPU clock was ungated, while it must be done afterwards. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/jz4770-cgu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index a5ad69464e57..314f3143ca61 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -154,7 +154,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { "h1clk", CGU_CLK_DIV | CGU_CLK_GATE, .parents = { JZ4770_CLK_PLL0, }, .div = { CGU_REG_CPCCR, 24, 1, 4, 22, -1, -1 }, - .gate = { CGU_REG_LCR, 30 }, + .gate = { CGU_REG_CLKGR1, 7 }, }, [JZ4770_CLK_H2CLK] = { "h2clk", CGU_CLK_DIV, @@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_VPU] = { "vpu", CGU_CLK_GATE, .parents = { JZ4770_CLK_H1CLK, }, - .gate = { CGU_REG_CLKGR1, 7 }, + .gate = { CGU_REG_LCR, 30 }, }, [JZ4770_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, -- cgit v1.2.3 From 6ee3d385c263248ce0ab2fcd679835082530445d Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 20 May 2018 16:31:17 +0000 Subject: clk: ingenic: jz4770: Add 150us delay after enabling VPU clock This is required, as we must not use the AHB1 bus before it is stable. Signed-off-by: Paul Cercueil Signed-off-by: Stephen Boyd --- drivers/clk/ingenic/jz4770-cgu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 314f3143ca61..bf46a0df2004 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -362,7 +362,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { [JZ4770_CLK_VPU] = { "vpu", CGU_CLK_GATE, .parents = { JZ4770_CLK_H1CLK, }, - .gate = { CGU_REG_LCR, 30 }, + .gate = { CGU_REG_LCR, 30, false, 150 }, }, [JZ4770_CLK_MMC0] = { "mmc0", CGU_CLK_GATE, -- cgit v1.2.3 From 4d3f36c5e9ca0f947eed71660239c529c501141a Mon Sep 17 00:00:00 2001 From: Mike Looijmans Date: Thu, 31 May 2018 16:03:55 +0200 Subject: clk-si544: Properly round requested frequency to nearest match The si544 driver had a rounding problem that using the result of clk_round_rate may set the clock to yet another rate, for example: clk_round_rate(195000000) = 194999999 clk_round_rate(194999999) = 194999998 Clients would expect that after clk_set_rate(clk, freq2=clk_round_rate(clk, freq)) the chip will be running at exactly freq2. The problem was in the calculation of the feedback divider, it was always rounded down instead of to the nearest possible VCO value. After this change, the following holds true for any supported frequency: actual_freq = clk_round_rate(clk, freq); clk_set_rate(clk, actual_freq); clk_round_rate(clk, actual_freq) == actual_freq && clk_get_rate(clk) == actual_freq Signed-off-by: Mike Looijmans Fixes: 953cc3e81170 ("clk: Add driver for the si544 clock generator chip") Signed-off-by: Stephen Boyd --- drivers/clk/clk-si544.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/clk-si544.c b/drivers/clk/clk-si544.c index 1c96a9f6c022..1e2a3b8f9454 100644 --- a/drivers/clk/clk-si544.c +++ b/drivers/clk/clk-si544.c @@ -207,6 +207,7 @@ static int si544_calc_muldiv(struct clk_si544_muldiv *settings, /* And the fractional bits using the remainder */ vco = (u64)tmp << 32; + vco += FXO / 2; /* Round to nearest multiple */ do_div(vco, FXO); settings->fb_div_frac = vco; -- cgit v1.2.3 From 48bf9a522c14449cc7c214c6062668ac54e4e88f Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Fri, 1 Jun 2018 17:56:06 -0700 Subject: dt-bindings: clk: Update Stingray binding doc Update Stingray clock binding document to add additional clock entries with names matching the latest ASIC datasheet. Also modify a few existing entries to make their naming more consistent with the rest of the entries Signed-off-by: Pramod Kumar Signed-off-by: Ray Jui Signed-off-by: Stephen Boyd --- .../bindings/clock/brcm,iproc-clocks.txt | 26 ++++++++++++---------- include/dt-bindings/clock/bcm-sr.h | 24 ++++++++++++++------ 2 files changed, 31 insertions(+), 19 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt index f8e4a93466cb..ab730ea0a560 100644 --- a/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt +++ b/Documentation/devicetree/bindings/clock/brcm,iproc-clocks.txt @@ -276,36 +276,38 @@ These clock IDs are defined in: clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK - clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH + clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK + clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK genpll3 crystal 0 BCM_SR_GENPLL3 clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK genpll4 crystal 0 BCM_SR_GENPLL4 - ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK + clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK - noc_clk genpll4 3 BCM_SR_GENPLL4_NOC_CLK + clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK - genpll5 crystal 0 BCM_SR_GENPLL5 - fs4_hf_clk genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK - crypto_ae_clk genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK - raid_ae_clk genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK + clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK + clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK + clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK genpll6 crystal 0 BCM_SR_GENPLL6 - 48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK + clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK lcpll0 crystal 0 BCM_SR_LCPLL0 clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK - clk_usb_ref lcpll0 3 BCM_SR_LCPLL0_USB_REF_CLK - sata_refpn lcpll0 3 BCM_SR_LCPLL0_SATA_REFPN_CLK + clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK + clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK lcpll1 crystal 0 BCM_SR_LCPLL1 - wan lcpll1 1 BCM_SR_LCPLL0_WAN_CLK + clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK + clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK + clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE - pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK + clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK diff --git a/include/dt-bindings/clock/bcm-sr.h b/include/dt-bindings/clock/bcm-sr.h index cff6c6fe2947..419011ba1a94 100644 --- a/include/dt-bindings/clock/bcm-sr.h +++ b/include/dt-bindings/clock/bcm-sr.h @@ -35,7 +35,7 @@ /* GENPLL 0 clock channel ID SCR HSLS FS PCIE */ #define BCM_SR_GENPLL0 0 -#define BCM_SR_GENPLL0_SATA_CLK 1 +#define BCM_SR_GENPLL0_125M_CLK 1 #define BCM_SR_GENPLL0_SCR_CLK 2 #define BCM_SR_GENPLL0_250M_CLK 3 #define BCM_SR_GENPLL0_PCIE_AXI_CLK 4 @@ -50,9 +50,11 @@ /* GENPLL 2 clock channel ID NITRO MHB*/ #define BCM_SR_GENPLL2 0 #define BCM_SR_GENPLL2_NIC_CLK 1 -#define BCM_SR_GENPLL2_250_NITRO_CLK 2 +#define BCM_SR_GENPLL2_TS_500_CLK 2 #define BCM_SR_GENPLL2_125_NITRO_CLK 3 #define BCM_SR_GENPLL2_CHIMP_CLK 4 +#define BCM_SR_GENPLL2_NIC_FLASH_CLK 5 +#define BCM_SR_GENPLL2_FS4_CLK 6 /* GENPLL 3 HSLS clock channel ID */ #define BCM_SR_GENPLL3 0 @@ -62,11 +64,16 @@ /* GENPLL 4 SCR clock channel ID */ #define BCM_SR_GENPLL4 0 #define BCM_SR_GENPLL4_CCN_CLK 1 +#define BCM_SR_GENPLL4_TPIU_PLL_CLK 2 +#define BCM_SR_GENPLL4_NOC_CLK 3 +#define BCM_SR_GENPLL4_CHCLK_FS4_CLK 4 +#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK 5 /* GENPLL 5 FS4 clock channel ID */ #define BCM_SR_GENPLL5 0 -#define BCM_SR_GENPLL5_FS_CLK 1 -#define BCM_SR_GENPLL5_SPU_CLK 2 +#define BCM_SR_GENPLL5_FS4_HF_CLK 1 +#define BCM_SR_GENPLL5_CRYPTO_AE_CLK 2 +#define BCM_SR_GENPLL5_RAID_AE_CLK 3 /* GENPLL 6 NITRO clock channel ID */ #define BCM_SR_GENPLL6 0 @@ -74,13 +81,16 @@ /* LCPLL0 clock channel ID */ #define BCM_SR_LCPLL0 0 -#define BCM_SR_LCPLL0_SATA_REF_CLK 1 -#define BCM_SR_LCPLL0_USB_REF_CLK 2 -#define BCM_SR_LCPLL0_SATA_REFPN_CLK 3 +#define BCM_SR_LCPLL0_SATA_REFP_CLK 1 +#define BCM_SR_LCPLL0_SATA_REFN_CLK 2 +#define BCM_SR_LCPLL0_SATA_350_CLK 3 +#define BCM_SR_LCPLL0_SATA_500_CLK 4 /* LCPLL1 clock channel ID */ #define BCM_SR_LCPLL1 0 #define BCM_SR_LCPLL1_WAN_CLK 1 +#define BCM_SR_LCPLL1_USB_REF_CLK 2 +#define BCM_SR_LCPLL1_CRMU_TS_CLK 3 /* LCPLL PCIE clock channel ID */ #define BCM_SR_LCPLL_PCIE 0 -- cgit v1.2.3 From 5afa881c6635427e68c73861a2c22d8cac00b984 Mon Sep 17 00:00:00 2001 From: Pramod Kumar Date: Fri, 1 Jun 2018 17:56:07 -0700 Subject: clk: bcm: Update and add Stingray clock entries Update and add Stingray clock definitions and tables so they match the binding document and the latest ASIC datasheet Signed-off-by: Pramod Kumar Signed-off-by: Ray Jui Signed-off-by: Stephen Boyd --- drivers/clk/bcm/clk-sr.c | 135 +++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 120 insertions(+), 15 deletions(-) diff --git a/drivers/clk/bcm/clk-sr.c b/drivers/clk/bcm/clk-sr.c index adc74f4584cf..7b9efc0212a8 100644 --- a/drivers/clk/bcm/clk-sr.c +++ b/drivers/clk/bcm/clk-sr.c @@ -56,8 +56,8 @@ static const struct iproc_pll_ctrl sr_genpll0 = { }; static const struct iproc_clk_ctrl sr_genpll0_clk[] = { - [BCM_SR_GENPLL0_SATA_CLK] = { - .channel = BCM_SR_GENPLL0_SATA_CLK, + [BCM_SR_GENPLL0_125M_CLK] = { + .channel = BCM_SR_GENPLL0_125M_CLK, .flags = IPROC_CLK_AON, .enable = ENABLE_VAL(0x4, 6, 0, 12), .mdiv = REG_VAL(0x18, 0, 9), @@ -102,6 +102,65 @@ static int sr_genpll0_clk_init(struct platform_device *pdev) return 0; } +static const struct iproc_pll_ctrl sr_genpll2 = { + .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | + IPROC_CLK_PLL_NEEDS_SW_CFG, + .aon = AON_VAL(0x0, 1, 13, 12), + .reset = RESET_VAL(0x0, 12, 11), + .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), + .sw_ctrl = SW_CTRL_VAL(0x10, 31), + .ndiv_int = REG_VAL(0x10, 20, 10), + .ndiv_frac = REG_VAL(0x10, 0, 20), + .pdiv = REG_VAL(0x14, 0, 4), + .status = REG_VAL(0x30, 12, 1), +}; + +static const struct iproc_clk_ctrl sr_genpll2_clk[] = { + [BCM_SR_GENPLL2_NIC_CLK] = { + .channel = BCM_SR_GENPLL2_NIC_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 6, 0, 12), + .mdiv = REG_VAL(0x18, 0, 9), + }, + [BCM_SR_GENPLL2_TS_500_CLK] = { + .channel = BCM_SR_GENPLL2_TS_500_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 7, 1, 13), + .mdiv = REG_VAL(0x18, 10, 9), + }, + [BCM_SR_GENPLL2_125_NITRO_CLK] = { + .channel = BCM_SR_GENPLL2_125_NITRO_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 8, 2, 14), + .mdiv = REG_VAL(0x18, 20, 9), + }, + [BCM_SR_GENPLL2_CHIMP_CLK] = { + .channel = BCM_SR_GENPLL2_CHIMP_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 9, 3, 15), + .mdiv = REG_VAL(0x1c, 0, 9), + }, + [BCM_SR_GENPLL2_NIC_FLASH_CLK] = { + .channel = BCM_SR_GENPLL2_NIC_FLASH_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 10, 4, 16), + .mdiv = REG_VAL(0x1c, 10, 9), + }, + [BCM_SR_GENPLL2_FS4_CLK] = { + .channel = BCM_SR_GENPLL2_FS4_CLK, + .enable = ENABLE_VAL(0x4, 11, 5, 17), + .mdiv = REG_VAL(0x1c, 20, 9), + }, +}; + +static int sr_genpll2_clk_init(struct platform_device *pdev) +{ + iproc_pll_clk_setup(pdev->dev.of_node, + &sr_genpll2, NULL, 0, sr_genpll2_clk, + ARRAY_SIZE(sr_genpll2_clk)); + return 0; +} + static const struct iproc_pll_ctrl sr_genpll3 = { .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_PLL_NEEDS_SW_CFG, @@ -157,6 +216,30 @@ static const struct iproc_clk_ctrl sr_genpll4_clk[] = { .enable = ENABLE_VAL(0x4, 6, 0, 12), .mdiv = REG_VAL(0x18, 0, 9), }, + [BCM_SR_GENPLL4_TPIU_PLL_CLK] = { + .channel = BCM_SR_GENPLL4_TPIU_PLL_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 7, 1, 13), + .mdiv = REG_VAL(0x18, 10, 9), + }, + [BCM_SR_GENPLL4_NOC_CLK] = { + .channel = BCM_SR_GENPLL4_NOC_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 8, 2, 14), + .mdiv = REG_VAL(0x18, 20, 9), + }, + [BCM_SR_GENPLL4_CHCLK_FS4_CLK] = { + .channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 9, 3, 15), + .mdiv = REG_VAL(0x1c, 0, 9), + }, + [BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK] = { + .channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x4, 10, 4, 16), + .mdiv = REG_VAL(0x1c, 10, 9), + }, }; static int sr_genpll4_clk_init(struct platform_device *pdev) @@ -181,18 +264,21 @@ static const struct iproc_pll_ctrl sr_genpll5 = { }; static const struct iproc_clk_ctrl sr_genpll5_clk[] = { - [BCM_SR_GENPLL5_FS_CLK] = { - .channel = BCM_SR_GENPLL5_FS_CLK, - .flags = IPROC_CLK_AON, + [BCM_SR_GENPLL5_FS4_HF_CLK] = { + .channel = BCM_SR_GENPLL5_FS4_HF_CLK, .enable = ENABLE_VAL(0x4, 6, 0, 12), .mdiv = REG_VAL(0x18, 0, 9), }, - [BCM_SR_GENPLL5_SPU_CLK] = { - .channel = BCM_SR_GENPLL5_SPU_CLK, - .flags = IPROC_CLK_AON, - .enable = ENABLE_VAL(0x4, 6, 0, 12), + [BCM_SR_GENPLL5_CRYPTO_AE_CLK] = { + .channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK, + .enable = ENABLE_VAL(0x4, 7, 1, 12), .mdiv = REG_VAL(0x18, 10, 9), }, + [BCM_SR_GENPLL5_RAID_AE_CLK] = { + .channel = BCM_SR_GENPLL5_RAID_AE_CLK, + .enable = ENABLE_VAL(0x4, 8, 2, 14), + .mdiv = REG_VAL(0x18, 20, 9), + }, }; static int sr_genpll5_clk_init(struct platform_device *pdev) @@ -214,24 +300,30 @@ static const struct iproc_pll_ctrl sr_lcpll0 = { }; static const struct iproc_clk_ctrl sr_lcpll0_clk[] = { - [BCM_SR_LCPLL0_SATA_REF_CLK] = { - .channel = BCM_SR_LCPLL0_SATA_REF_CLK, + [BCM_SR_LCPLL0_SATA_REFP_CLK] = { + .channel = BCM_SR_LCPLL0_SATA_REFP_CLK, .flags = IPROC_CLK_AON, .enable = ENABLE_VAL(0x0, 7, 1, 13), .mdiv = REG_VAL(0x14, 0, 9), }, - [BCM_SR_LCPLL0_USB_REF_CLK] = { - .channel = BCM_SR_LCPLL0_USB_REF_CLK, + [BCM_SR_LCPLL0_SATA_REFN_CLK] = { + .channel = BCM_SR_LCPLL0_SATA_REFN_CLK, .flags = IPROC_CLK_AON, .enable = ENABLE_VAL(0x0, 8, 2, 14), .mdiv = REG_VAL(0x14, 10, 9), }, - [BCM_SR_LCPLL0_SATA_REFPN_CLK] = { - .channel = BCM_SR_LCPLL0_SATA_REFPN_CLK, + [BCM_SR_LCPLL0_SATA_350_CLK] = { + .channel = BCM_SR_LCPLL0_SATA_350_CLK, .flags = IPROC_CLK_AON, .enable = ENABLE_VAL(0x0, 9, 3, 15), .mdiv = REG_VAL(0x14, 20, 9), }, + [BCM_SR_LCPLL0_SATA_500_CLK] = { + .channel = BCM_SR_LCPLL0_SATA_500_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x0, 10, 4, 16), + .mdiv = REG_VAL(0x18, 0, 9), + }, }; static int sr_lcpll0_clk_init(struct platform_device *pdev) @@ -259,6 +351,18 @@ static const struct iproc_clk_ctrl sr_lcpll1_clk[] = { .enable = ENABLE_VAL(0x0, 7, 1, 13), .mdiv = REG_VAL(0x14, 0, 9), }, + [BCM_SR_LCPLL1_USB_REF_CLK] = { + .channel = BCM_SR_LCPLL1_USB_REF_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x0, 8, 2, 14), + .mdiv = REG_VAL(0x14, 10, 9), + }, + [BCM_SR_LCPLL1_CRMU_TS_CLK] = { + .channel = BCM_SR_LCPLL1_CRMU_TS_CLK, + .flags = IPROC_CLK_AON, + .enable = ENABLE_VAL(0x0, 9, 3, 15), + .mdiv = REG_VAL(0x14, 20, 9), + }, }; static int sr_lcpll1_clk_init(struct platform_device *pdev) @@ -298,6 +402,7 @@ static int sr_lcpll_pcie_clk_init(struct platform_device *pdev) static const struct of_device_id sr_clk_dt_ids[] = { { .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init }, + { .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init }, { .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init }, { .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init }, { .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init }, -- cgit v1.2.3