From 592693a1f881630f744b69b8bc315caa99272d64 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Wed, 16 Sep 2020 22:27:31 +0930 Subject: soc: aspeed: Improve kconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reword the kconfig text to be consistent and reflect that most drivers are available for all supported ASPEED chips (2400, 2500 and 2600). Rearrange the symbols the SoC drivers depend on so the menu doesn't appear unless you are building for ASPEED for compile testing. The SYSCON_MFD and REGMAP options are usually selected by drivers that need them, so do this. Reviewed-by: Cédric Le Goater Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20200916125731.784527-1-joel@jms.id.au Signed-off-by: Joel Stanley --- drivers/soc/Makefile | 2 +- drivers/soc/aspeed/Kconfig | 36 ++++++++++++++++++++---------------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 36452bed86ef..8fa43a2d17e7 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -4,7 +4,7 @@ # obj-$(CONFIG_ARCH_ACTIONS) += actions/ -obj-$(CONFIG_SOC_ASPEED) += aspeed/ +obj-y += aspeed/ obj-$(CONFIG_ARCH_AT91) += atmel/ obj-y += bcm/ obj-$(CONFIG_ARCH_DOVE) += dove/ diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index c95fa30f1a76..9ce252445605 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -1,32 +1,36 @@ # SPDX-License-Identifier: GPL-2.0-only -menu "Aspeed SoC drivers" -config SOC_ASPEED - def_bool y - depends on ARCH_ASPEED || COMPILE_TEST +if ARCH_ASPEED || COMPILE_TEST + +menu "ASPEED SoC drivers" config ASPEED_LPC_CTRL - depends on SOC_ASPEED && REGMAP && MFD_SYSCON - tristate "Aspeed ast2400/2500 HOST LPC to BMC bridge control" + tristate "ASPEED LPC firmware cycle control" + select REGMAP + select MFD_SYSCON help - Control Aspeed ast2400/2500 HOST LPC to BMC mappings through - ioctl()s, the driver also provides a read/write interface to a BMC ram - region where the host LPC read/write region can be buffered. + Control LPC firmware cycle mappings through ioctl()s. The driver + also provides a read/write interface to a BMC ram region where the + host LPC read/write region can be buffered. config ASPEED_LPC_SNOOP - tristate "Aspeed ast2500 HOST LPC snoop support" - depends on SOC_ASPEED && REGMAP && MFD_SYSCON + tristate "ASPEED LPC snoop support" + select REGMAP + select MFD_SYSCON help Provides a driver to control the LPC snoop interface which allows the BMC to listen on and save the data written by the host to an arbitrary LPC I/O port. config ASPEED_P2A_CTRL - depends on SOC_ASPEED && REGMAP && MFD_SYSCON - tristate "Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC bridge control" + tristate "ASPEED P2A (VGA MMIO to BMC) bridge control" + select REGMAP + select MFD_SYSCON help - Control Aspeed ast2400/2500 HOST P2A VGA MMIO to BMC mappings through - ioctl()s, the driver also provides an interface for userspace mappings to - a pre-defined region. + Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The + driver also provides an interface for userspace mappings to a + pre-defined region. endmenu + +endif -- cgit v1.2.3 From 7c1f6281549bda39ab32f65eb93bfcf2aa75fe94 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 21 Sep 2020 18:46:42 +0930 Subject: dt-bindings: aspeed: Add silicon id node to SCU Different ASPEED families have various unique hardware silicon identifiers within the SoC. Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20200921091644.133107-2-joel@jms.id.au Signed-off-by: Joel Stanley --- .../devicetree/bindings/mfd/aspeed-scu.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt index 4d92c0bb6687..857ee33f7329 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt @@ -20,3 +20,29 @@ syscon: syscon@1e6e2000 { #clock-cells = <1>; #reset-cells = <1>; }; + +Silicon ID +----------------- + +Families have unique hardware silicon identifiers within the SoC. + +Required properties: + + - compatible: "aspeed,silicon-id" or: + "aspeed,ast2400-silicon-id" or + "aspeed,ast2500-silicon-id" or + "aspeed,ast2600-silicon-id" + + - reg: offset and length of the silicon id information + optionally, a second offset and length describes the unique chip id + + The reg should be the unique silicon id register, and + not backwards compatible one in eg. the 2600. + +Example: + + +silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4 0x150 0x8>; +}; -- cgit v1.2.3 From e0218dca5787c851b403fcbc33cdfec795446fca Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 21 Sep 2020 18:46:43 +0930 Subject: soc: aspeed: Add soc info driver This adds a SOC_BUS info driver for the ASPEED platform. The full ID table is preserved in this commit message in case someone finds a need to change the implemntation in the future. { "AST1100-A0", 0x00000200 }, { "AST1100-A1", 0x00000201 }, { "AST1100-A2", 0x00000202 }, { "AST1100-A3", 0x00000202 }, { "AST2050-A0", 0x00000200 }, { "AST2050-A1", 0x00000201 }, { "AST2050-A2", 0x00000202 }, { "AST2050-A3", 0x00000202 }, { "AST2100-A0", 0x00000300 }, { "AST2100-A1", 0x00000301 }, { "AST2100-A2", 0x00000302 }, { "AST2100-A3", 0x00000302 }, { "AST2150-A0", 0x00000202 }, { "AST2150-A1", 0x00000202 }, { "AST2200-A0", 0x00000102 }, { "AST2200-A1", 0x00000102 }, { "AST2300-A0", 0x01000003 }, { "AST2300-A1", 0x01010303 }, { "AST1300-A1", 0x01010003 }, { "AST1050-A1", 0x01010203 }, { "AST2400-A0", 0x02000303 }, { "AST2400-A1", 0x02010303 }, { "AST1400-A1", 0x02010103 }, { "AST1250-A1", 0x02010303 }, { "AST2500-A0", 0x04000303 }, { "AST2510-A0", 0x04000103 }, { "AST2520-A0", 0x04000203 }, { "AST2530-A0", 0x04000403 }, { "AST2500-A1", 0x04010303 }, { "AST2510-A1", 0x04010103 }, { "AST2520-A1", 0x04010203 }, { "AST2530-A1", 0x04010403 }, { "AST2500-A2", 0x04030303 }, { "AST2510-A2", 0x04030103 }, { "AST2520-A2", 0x04030203 }, { "AST2530-A2", 0x04030403 }, { "AST2600-A0", 0x05000303 }, { "AST2600-A1", 0x05010303 }, { "AST2600-A2", 0x05020303 }, { "AST2620-A1", 0x05010203 }, { "AST2620-A2", 0x05020203 }, Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20200921091644.133107-3-joel@jms.id.au Signed-off-by: Joel Stanley --- drivers/soc/aspeed/Kconfig | 7 ++ drivers/soc/aspeed/Makefile | 1 + drivers/soc/aspeed/aspeed-socinfo.c | 133 ++++++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/soc/aspeed/aspeed-socinfo.c diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index 9ce252445605..7ece0675b1fa 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -31,6 +31,13 @@ config ASPEED_P2A_CTRL driver also provides an interface for userspace mappings to a pre-defined region. +config ASPEED_SOCINFO + bool "ASPEED SoC Information driver" + default ARCH_ASPEED + select SOC_BUS + help + Say yes to support decoding of ASPEED BMC information. + endmenu endif diff --git a/drivers/soc/aspeed/Makefile b/drivers/soc/aspeed/Makefile index b64be47f2b1f..fcab7192e1a4 100644 --- a/drivers/soc/aspeed/Makefile +++ b/drivers/soc/aspeed/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_ASPEED_LPC_CTRL) += aspeed-lpc-ctrl.o obj-$(CONFIG_ASPEED_LPC_SNOOP) += aspeed-lpc-snoop.o obj-$(CONFIG_ASPEED_P2A_CTRL) += aspeed-p2a-ctrl.o +obj-$(CONFIG_ASPEED_SOCINFO) += aspeed-socinfo.o diff --git a/drivers/soc/aspeed/aspeed-socinfo.c b/drivers/soc/aspeed/aspeed-socinfo.c new file mode 100644 index 000000000000..26db42ef6aae --- /dev/null +++ b/drivers/soc/aspeed/aspeed-socinfo.c @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright 2019 IBM Corp. */ + +#include +#include +#include +#include +#include +#include +#include + +static struct { + const char *name; + const u32 id; +} const rev_table[] = { + /* AST2400 */ + { "AST2400", 0x02000303 }, + { "AST1400", 0x02010103 }, + { "AST1250", 0x02010303 }, + /* AST2500 */ + { "AST2500", 0x04000303 }, + { "AST2510", 0x04000103 }, + { "AST2520", 0x04000203 }, + { "AST2530", 0x04000403 }, + /* AST2600 */ + { "AST2600", 0x05000303 }, + { "AST2620", 0x05010203 }, +}; + +static const char *siliconid_to_name(u32 siliconid) +{ + unsigned int id = siliconid & 0xff00ffff; + unsigned int i; + + for (i = 0 ; i < ARRAY_SIZE(rev_table) ; ++i) { + if (rev_table[i].id == id) + return rev_table[i].name; + } + + return "Unknown"; +} + +static const char *siliconid_to_rev(u32 siliconid) +{ + unsigned int rev = (siliconid >> 16) & 0xff; + + switch (rev) { + case 0: + return "A0"; + case 1: + return "A1"; + case 3: + return "A2"; + }; + + return "??"; +} + +static int __init aspeed_socinfo_init(void) +{ + struct soc_device_attribute *attrs; + struct soc_device *soc_dev; + struct device_node *np; + void __iomem *reg; + bool has_chipid = false; + u32 siliconid; + u32 chipid[2]; + const char *machine = NULL; + + np = of_find_compatible_node(NULL, NULL, "aspeed,silicon-id"); + if (!of_device_is_available(np)) { + of_node_put(np); + return -ENODEV; + } + + reg = of_iomap(np, 0); + if (!reg) + return -ENODEV; + siliconid = readl(reg); + iounmap(reg); + + /* This is optional, the ast2400 does not have it */ + reg = of_iomap(np, 1); + if (reg) { + has_chipid = true; + chipid[0] = readl(reg); + chipid[1] = readl(reg + 4); + iounmap(reg); + } + of_node_put(np); + + attrs = kzalloc(sizeof(*attrs), GFP_KERNEL); + if (!attrs) + return -ENODEV; + + /* + * Machine: Romulus BMC + * Family: AST2500 + * Revision: A1 + * SoC ID: raw silicon revision id + * Serial Number: 64-bit chipid + */ + + np = of_find_node_by_path("/"); + of_property_read_string(np, "model", &machine); + if (machine) + attrs->machine = kstrdup(machine, GFP_KERNEL); + of_node_put(np); + + attrs->family = siliconid_to_name(siliconid); + attrs->revision = siliconid_to_rev(siliconid); + attrs->soc_id = kasprintf(GFP_KERNEL, "%08x", siliconid); + + if (has_chipid) + attrs->serial_number = kasprintf(GFP_KERNEL, "%08x%08x", + chipid[1], chipid[0]); + + soc_dev = soc_device_register(attrs); + if (IS_ERR(soc_dev)) { + kfree(attrs->soc_id); + kfree(attrs->serial_number); + kfree(attrs); + return PTR_ERR(soc_dev); + } + + pr_info("ASPEED %s rev %s (%s)\n", + attrs->family, + attrs->revision, + attrs->soc_id); + + return 0; +} +early_initcall(aspeed_socinfo_init); -- cgit v1.2.3 From fe100b382c1c052b63c14091fd8bb3fe932453ae Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Mon, 21 Sep 2020 18:46:44 +0930 Subject: ARM: dts: aspeed: Add silicon id node This register describes the silicon id and chip unique id. It varies between CPU revisions, but is always part of the SCU. Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20200921091644.133107-4-joel@jms.id.au Signed-off-by: Joel Stanley --- arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++ arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++ arch/arm/boot/dts/aspeed-g6.dtsi | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 82f0213e3a3c..b3dafbc8caca 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -192,6 +192,11 @@ status = "disabled"; }; + silicon-id@7c { + compatible = "aspeed,ast2400-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4>; + }; + pinctrl: pinctrl@80 { reg = <0x80 0x18>, <0xa0 0x10>; compatible = "aspeed,ast2400-pinctrl"; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi index 9c91afb2b404..c6862182313a 100644 --- a/arch/arm/boot/dts/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -239,6 +239,11 @@ status = "disabled"; }; + silicon-id@7c { + compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; + reg = <0x7c 0x4 0x150 0x8>; + }; + pinctrl: pinctrl@80 { compatible = "aspeed,ast2500-pinctrl"; reg = <0x80 0x18>, <0xa0 0x10>; diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index b58220a49cbd..1ce3a1f06f7f 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -311,6 +311,11 @@ compatible = "aspeed,ast2600-pinctrl"; }; + silicon-id@14 { + compatible = "aspeed,ast2600-silicon-id", "aspeed,silicon-id"; + reg = <0x14 0x4 0x5b0 0x8>; + }; + smp-memram@180 { compatible = "aspeed,ast2600-smpmem"; reg = <0x180 0x40>; -- cgit v1.2.3 From e8589796a6d1255f0f6cbbe9706f1f70362ba0c8 Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 08:56:01 -0400 Subject: dt-bindings: aspeed-lpc: Add AST2600 compatible strings The AST2600 datasheet indicates the same register set behind the LPC controller address space. Signed-off-by: Brad Bishop Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20190925125610.12096-2-bradleyb@fuzziesquirrel.com Signed-off-by: Joel Stanley --- Documentation/devicetree/bindings/mfd/aspeed-lpc.txt | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt index a92acf1dd491..d0a38ba8b9ce 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt @@ -46,6 +46,7 @@ Required properties - compatible: One of: "aspeed,ast2400-lpc", "simple-mfd" "aspeed,ast2500-lpc", "simple-mfd" + "aspeed,ast2600-lpc", "simple-mfd" - reg: contains the physical address and length values of the Aspeed LPC memory region. @@ -64,6 +65,7 @@ BMC Node - compatible: One of: "aspeed,ast2400-lpc-bmc" "aspeed,ast2500-lpc-bmc" + "aspeed,ast2600-lpc-bmc" - reg: contains the physical address and length values of the H8S/2168-compatible LPC controller memory region @@ -74,6 +76,7 @@ Host Node - compatible: One of: "aspeed,ast2400-lpc-host", "simple-mfd", "syscon" "aspeed,ast2500-lpc-host", "simple-mfd", "syscon" + "aspeed,ast2600-lpc-host", "simple-mfd", "syscon" - reg: contains the address and length values of the host-related register space for the Aspeed LPC controller @@ -128,6 +131,7 @@ Required properties: - compatible: One of: "aspeed,ast2400-lpc-ctrl"; "aspeed,ast2500-lpc-ctrl"; + "aspeed,ast2600-lpc-ctrl"; - reg: contains offset/length values of the host interface controller memory regions @@ -168,6 +172,7 @@ Required properties: - compatible: One of: "aspeed,ast2400-lhc"; "aspeed,ast2500-lhc"; + "aspeed,ast2600-lhc"; - reg: contains offset/length values of the LHC memory regions. In the AST2400 and AST2500 there are two regions. @@ -187,7 +192,8 @@ state of the LPC bus. Some systems may chose to modify this configuration. Required properties: - - compatible: "aspeed,ast2500-lpc-reset" or + - compatible: "aspeed,ast2600-lpc-reset" or + "aspeed,ast2500-lpc-reset" "aspeed,ast2400-lpc-reset" - reg: offset and length of the IP in the LHC memory region - #reset-controller indicates the number of reset cells expected -- cgit v1.2.3 From 44ddc4de87a54b32ead77d3ec67f0bf93d8c0055 Mon Sep 17 00:00:00 2001 From: Brad Bishop Date: Wed, 25 Sep 2019 08:56:03 -0400 Subject: soc: aspeed: lpc: Add AST2600 compatible strings The AST2600 has the same lpc-ctrl and lpc-snoop devices as the AST2500. Signed-off-by: Brad Bishop Acked-by: Andrew Jeffery Link: https://lore.kernel.org/r/20190925125610.12096-4-bradleyb@fuzziesquirrel.com Signed-off-by: Joel Stanley --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 1 + drivers/soc/aspeed/aspeed-lpc-snoop.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index 01ed21e8bfee..12e4421dee37 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -291,6 +291,7 @@ static int aspeed_lpc_ctrl_remove(struct platform_device *pdev) static const struct of_device_id aspeed_lpc_ctrl_match[] = { { .compatible = "aspeed,ast2400-lpc-ctrl" }, { .compatible = "aspeed,ast2500-lpc-ctrl" }, + { .compatible = "aspeed,ast2600-lpc-ctrl" }, { }, }; diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c index f3d8d53ab84d..682ba0eb4eba 100644 --- a/drivers/soc/aspeed/aspeed-lpc-snoop.c +++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c @@ -325,6 +325,8 @@ static const struct of_device_id aspeed_lpc_snoop_match[] = { .data = &ast2400_model_data }, { .compatible = "aspeed,ast2500-lpc-snoop", .data = &ast2500_model_data }, + { .compatible = "aspeed,ast2600-lpc-snoop", + .data = &ast2500_model_data }, { }, }; -- cgit v1.2.3 From 6bf4ddbe2b4805f0628922446a7e85e34013cd10 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 17 Oct 2019 10:09:50 +1030 Subject: soc: aspeed-lpc-ctrl: Fail probe of lpc-ctrl if reserved memory is not aligned Alignment is a hardware constraint of the LPC2AHB bridge, and misaligned reserved memory will present as corrupted data. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20191016233950.10100-1-andrew@aj.id.au Signed-off-by: Joel Stanley --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index 12e4421dee37..d8f3dff97cd4 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -241,6 +242,18 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev) lpc_ctrl->mem_size = resource_size(&resm); lpc_ctrl->mem_base = resm.start; + + if (!is_power_of_2(lpc_ctrl->mem_size)) { + dev_err(dev, "Reserved memory size must be a power of 2, got %u\n", + (unsigned int)lpc_ctrl->mem_size); + return -EINVAL; + } + + if (!IS_ALIGNED(lpc_ctrl->mem_base, lpc_ctrl->mem_size)) { + dev_err(dev, "Reserved memory must be naturally aligned for size %u\n", + (unsigned int)lpc_ctrl->mem_size); + return -EINVAL; + } } lpc_ctrl->regmap = syscon_node_to_regmap( -- cgit v1.2.3 From 5042d3f278de45e215291d2adcf1024cc3c7f73a Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 12 Mar 2020 22:44:13 +1030 Subject: soc: aspeed-lpc-ctrl: LPC to AHB mapping on ast2600 The ast2600 disables the mapping of AHB memory regions by default, only allowing the LPC window to point to SPI NOR. In order to point the window to any AHB address, an ast2600 specific bit must be toggled. Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20200312121413.294384-1-joel@jms.id.au Signed-off-by: Joel Stanley --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index d8f3dff97cd4..ee2def4ffda3 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -22,6 +22,9 @@ #define HICR5_ENL2H BIT(8) #define HICR5_ENFWH BIT(10) +#define HICR6 0x4 +#define SW_FWH2AHB BIT(17) + #define HICR7 0x8 #define HICR8 0xc @@ -33,6 +36,7 @@ struct aspeed_lpc_ctrl { resource_size_t mem_size; u32 pnor_size; u32 pnor_base; + bool fwh2ahb; }; static struct aspeed_lpc_ctrl *file_aspeed_lpc_ctrl(struct file *file) @@ -177,6 +181,16 @@ static long aspeed_lpc_ctrl_ioctl(struct file *file, unsigned int cmd, if (rc) return rc; + /* + * Switch to FWH2AHB mode, AST2600 only. + * + * The other bits in this register are interrupt status bits + * that are cleared by writing 1. As we don't want to clear + * them, set only the bit of interest. + */ + if (lpc_ctrl->fwh2ahb) + regmap_write(lpc_ctrl->regmap, HICR6, SW_FWH2AHB); + /* * Enable LPC FHW cycles. This is required for the host to * access the regions specified. @@ -274,6 +288,9 @@ static int aspeed_lpc_ctrl_probe(struct platform_device *pdev) return rc; } + if (of_device_is_compatible(dev->of_node, "aspeed,ast2600-lpc-ctrl")) + lpc_ctrl->fwh2ahb = true; + lpc_ctrl->miscdev.minor = MISC_DYNAMIC_MINOR; lpc_ctrl->miscdev.name = DEVICE_NAME; lpc_ctrl->miscdev.fops = &aspeed_lpc_ctrl_fops; -- cgit v1.2.3 From 4d1d81dbc9d51ac383f3979da5eba13870183c4d Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Fri, 25 Sep 2020 14:52:44 +0930 Subject: soc: aspeed-lpc-ctrl: Fix whitespace Some misaligned indentation I noticed when applying another patch. Signed-off-by: Joel Stanley --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index ee2def4ffda3..53373c164cd5 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -34,8 +34,8 @@ struct aspeed_lpc_ctrl { struct clk *clk; phys_addr_t mem_base; resource_size_t mem_size; - u32 pnor_size; - u32 pnor_base; + u32 pnor_size; + u32 pnor_base; bool fwh2ahb; }; -- cgit v1.2.3 From cd460be0460fd4edeef194a26d90c7ac02a8dadd Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Fri, 25 Sep 2020 14:53:25 +0930 Subject: soc: aspeed-lpc-ctrl: Fix driver name Clarify the string now that it supports the AST2600 too. Signed-off-by: Joel Stanley --- drivers/soc/aspeed/aspeed-lpc-ctrl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/aspeed/aspeed-lpc-ctrl.c b/drivers/soc/aspeed/aspeed-lpc-ctrl.c index 53373c164cd5..439bcd6b8c4a 100644 --- a/drivers/soc/aspeed/aspeed-lpc-ctrl.c +++ b/drivers/soc/aspeed/aspeed-lpc-ctrl.c @@ -339,4 +339,4 @@ module_platform_driver(aspeed_lpc_ctrl_driver); MODULE_DEVICE_TABLE(of, aspeed_lpc_ctrl_match); MODULE_LICENSE("GPL"); MODULE_AUTHOR("Cyril Bur "); -MODULE_DESCRIPTION("Control for aspeed 2400/2500 LPC HOST to BMC mappings"); +MODULE_DESCRIPTION("Control for ASPEED LPC HOST to BMC mappings"); -- cgit v1.2.3 From 57222a1be27e06ecb81cc2f945e897814d5f461c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 22 Apr 2020 16:00:47 +0300 Subject: tee: optee: Use UUID API for exporting the UUID There is export_uuid() function which exports uuid_t to the u8 array. Use it instead of open coding variant. This allows to hide the uuid_t internals. Reviewed-by: Sumit Garg Signed-off-by: Andy Shevchenko Signed-off-by: Jens Wiklander --- drivers/tee/optee/device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/tee/optee/device.c b/drivers/tee/optee/device.c index 7a897d51969f..ec1d24693eba 100644 --- a/drivers/tee/optee/device.c +++ b/drivers/tee/optee/device.c @@ -98,7 +98,7 @@ static int __optee_enumerate_devices(u32 func) return -ENODEV; /* Open session with device enumeration pseudo TA */ - memcpy(sess_arg.uuid, pta_uuid.b, TEE_IOCTL_UUID_LEN); + export_uuid(sess_arg.uuid, &pta_uuid); sess_arg.clnt_login = TEE_IOCTL_LOGIN_PUBLIC; sess_arg.num_params = 0; -- cgit v1.2.3 From cf25d802e029c31efac8bdc979236927f37183bd Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 23 Sep 2020 14:31:42 +0300 Subject: soc: renesas: rmobile-sysc: Fix some leaks in rmobile_init_pm_domains() This code needs to call iounmap() on one error path. Fixes: 2173fc7cb681 ("ARM: shmobile: R-Mobile: Add DT support for PM domains") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20200923113142.GC1473821@mwanda Signed-off-by: Geert Uytterhoeven --- drivers/soc/renesas/rmobile-sysc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/renesas/rmobile-sysc.c b/drivers/soc/renesas/rmobile-sysc.c index 54b616ad4a62..beb1c7211c3d 100644 --- a/drivers/soc/renesas/rmobile-sysc.c +++ b/drivers/soc/renesas/rmobile-sysc.c @@ -327,6 +327,7 @@ static int __init rmobile_init_pm_domains(void) pmd = of_get_child_by_name(np, "pm-domains"); if (!pmd) { + iounmap(base); pr_warn("%pOF lacks pm-domains node\n", np); continue; } -- cgit v1.2.3 From 96999c797ec1ef41259f00b4ddf9cf33b342cb78 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 3 Aug 2020 17:36:07 +0300 Subject: memory: jz4780_nemc: Fix an error pointer vs NULL check in probe() The devm_ioremap() function returns NULL on error, it doesn't return error pointers. This bug could lead to an Oops during probe. Fixes: f046e4a3f0b9 ("memory: jz4780_nemc: Only request IO memory the driver will use") Cc: Signed-off-by: Dan Carpenter Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20200803143607.GC346925@mwanda Signed-off-by: Krzysztof Kozlowski --- drivers/memory/jz4780-nemc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c index 3ec5cb0fce1e..608ae925e641 100644 --- a/drivers/memory/jz4780-nemc.c +++ b/drivers/memory/jz4780-nemc.c @@ -304,9 +304,9 @@ static int jz4780_nemc_probe(struct platform_device *pdev) } nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN); - if (IS_ERR(nemc->base)) { + if (!nemc->base) { dev_err(dev, "failed to get I/O memory\n"); - return PTR_ERR(nemc->base); + return -ENOMEM; } writel(0, nemc->base + NEMC_NFCSR); -- cgit v1.2.3 From f1118a28bef94086c89398cee26987faa6c43a01 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Tue, 16 Jun 2020 10:12:28 +0200 Subject: cpuidle: big.LITTLE: enable driver only on Peach-Pit/Pi Chromebooks This driver always worked properly only on the Exynos 5420/5800 based Chromebooks (Peach-Pit/Pi), so change the required compatible string to the 'google,peach', to avoid enabling it on the other Exynos 542x/5800 boards, which hangs in such case. The main difference between Peach-Pit/Pi and other Exynos 542x/5800 boards is the firmware - Peach platform doesn't use secure firmware at all. Signed-off-by: Marek Szyprowski Reviewed-by: Bartlomiej Zolnierkiewicz Acked-by: Daniel Lezcano Signed-off-by: Krzysztof Kozlowski --- drivers/cpuidle/cpuidle-big_little.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/cpuidle/cpuidle-big_little.c b/drivers/cpuidle/cpuidle-big_little.c index 7f8ddc04342d..abe51185f243 100644 --- a/drivers/cpuidle/cpuidle-big_little.c +++ b/drivers/cpuidle/cpuidle-big_little.c @@ -155,8 +155,7 @@ static int __init bl_idle_driver_init(struct cpuidle_driver *drv, int part_id) static const struct of_device_id compatible_machine_match[] = { { .compatible = "arm,vexpress,v2p-ca15_a7" }, - { .compatible = "samsung,exynos5420" }, - { .compatible = "samsung,exynos5800" }, + { .compatible = "google,peach" }, {}, }; -- cgit v1.2.3 From 4007844b05815717f522c7ea9914e24ad0ff6c79 Mon Sep 17 00:00:00 2001 From: Nicolas Boichat Date: Mon, 28 Sep 2020 11:31:35 +0800 Subject: soc: mediatek: Check if power domains can be powered on at boot time In the error case, where a power domain cannot be powered on successfully at boot time (in mtk_register_power_domains), pm_genpd_init would still be called with is_off=false, and the system would later try to disable the power domain again, triggering warnings as disabled clocks are disabled again (and other potential issues). Also print a warning splat in that case, as this should never happen. Fixes: c84e358718a66f7 ("soc: Mediatek: Add SCPSYS power domain driver") Signed-off-by: Nicolas Boichat Link: https://lore.kernel.org/r/20200928113107.v2.1.I5e6f8c262031d0451fe7241b744f4f3111c1ce71@changeid Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-scpsys.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c index f669d3754627..ca75b14931ec 100644 --- a/drivers/soc/mediatek/mtk-scpsys.c +++ b/drivers/soc/mediatek/mtk-scpsys.c @@ -524,6 +524,7 @@ static void mtk_register_power_domains(struct platform_device *pdev, for (i = 0; i < num; i++) { struct scp_domain *scpd = &scp->domains[i]; struct generic_pm_domain *genpd = &scpd->genpd; + bool on; /* * Initially turn on all domains to make the domains usable @@ -531,9 +532,9 @@ static void mtk_register_power_domains(struct platform_device *pdev, * software. The unused domains will be switched off during * late_init time. */ - genpd->power_on(genpd); + on = !WARN_ON(genpd->power_on(genpd) < 0); - pm_genpd_init(genpd, NULL, false); + pm_genpd_init(genpd, NULL, !on); } /* -- cgit v1.2.3 From cc7a16b14f386a9f67ba16195dfb85d2a9f3a007 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Tue, 20 Oct 2020 17:26:39 +0200 Subject: MAINTAINERS: change mediatek wiki page The old wiki page unfortunately got lost by server crash. The new wiki can be found on the kernel.org infrastructure Signed-off-by: Matthias Brugger Reviewed-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20201020152639.21950-1-matthias.bgg@kernel.org Signed-off-by: Matthias Brugger --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..0e1289658d55 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2067,7 +2067,7 @@ M: Matthias Brugger L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained -W: https://mtk.bcnfs.org/ +W: https://mtk.wiki.kernel.org/ C: irc://chat.freenode.net/linux-mediatek F: arch/arm/boot/dts/mt6* F: arch/arm/boot/dts/mt7* -- cgit v1.2.3 From fc3e62e25c3896855b7c3d72df19ca6be3459c9f Mon Sep 17 00:00:00 2001 From: Evan Green Date: Tue, 29 Sep 2020 13:30:57 -0700 Subject: soc: qcom: smp2p: Safely acquire spinlock without IRQs smp2p_update_bits() should disable interrupts when it acquires its spinlock. This is important because without the _irqsave, a priority inversion can occur. This function is called both with interrupts enabled in qcom_q6v5_request_stop(), and with interrupts disabled in ipa_smp2p_panic_notifier(). IRQ handling of spinlocks should be consistent to avoid the panic notifier deadlocking because it's sitting on the thread that's already got the lock via _request_stop(). Found via lockdep. Cc: stable@vger.kernel.org Fixes: 50e99641413e7 ("soc: qcom: smp2p: Qualcomm Shared Memory Point to Point") Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Signed-off-by: Evan Green Link: https://lore.kernel.org/r/20200929133040.RESEND.1.Ideabf6dcdfc577cf39ce3d95b0e4aa1ac8b38f0c@changeid Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smp2p.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index 07183d731d74..a9709aae54ab 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -318,15 +318,16 @@ static int qcom_smp2p_inbound_entry(struct qcom_smp2p *smp2p, static int smp2p_update_bits(void *data, u32 mask, u32 value) { struct smp2p_entry *entry = data; + unsigned long flags; u32 orig; u32 val; - spin_lock(&entry->lock); + spin_lock_irqsave(&entry->lock, flags); val = orig = readl(entry->value); val &= ~mask; val |= value; writel(val, entry->value); - spin_unlock(&entry->lock); + spin_unlock_irqrestore(&entry->lock, flags); if (val != orig) qcom_smp2p_kick(entry->smp2p); -- cgit v1.2.3 From af7244c076374c065d42f8bd24254e7ea2fae4f1 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Tue, 15 Sep 2020 12:25:25 +0530 Subject: soc: qcom: llcc: Move llcc configuration to its own function Cleanup qcom_llcc_cfg_program() by moving llcc configuration to a separate function of its own. Also correct misspelled 'instance' caught by checkpatch. Reviewed-by: Bjorn Andersson Reviewed-by: Stephen Boyd Suggested-by: Stephen Boyd Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/51f9ad67333eedf326212dd1b040aade6978e5b1.1600151951.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/llcc-qcom.c | 89 +++++++++++++++++++++++++------------------- 1 file changed, 50 insertions(+), 39 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 70fbe70c6213..95dad1c10198 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -318,62 +318,73 @@ size_t llcc_get_slice_size(struct llcc_slice_desc *desc) } EXPORT_SYMBOL_GPL(llcc_get_slice_size); -static int qcom_llcc_cfg_program(struct platform_device *pdev) +static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config) { - int i; + int ret; u32 attr1_cfg; u32 attr0_cfg; u32 attr1_val; u32 attr0_val; u32 max_cap_cacheline; + struct llcc_slice_desc desc; + + attr1_val = config->cache_mode; + attr1_val |= config->probe_target_ways << ATTR1_PROBE_TARGET_WAYS_SHIFT; + attr1_val |= config->fixed_size << ATTR1_FIXED_SIZE_SHIFT; + attr1_val |= config->priority << ATTR1_PRIORITY_SHIFT; + + max_cap_cacheline = MAX_CAP_TO_BYTES(config->max_cap); + + /* + * LLCC instances can vary for each target. + * The SW writes to broadcast register which gets propagated + * to each llcc instance (llcc0,.. llccN). + * Since the size of the memory is divided equally amongst the + * llcc instances, we need to configure the max cap accordingly. + */ + max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; + max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; + attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; + + attr1_cfg = LLCC_TRP_ATTR1_CFGn(config->slice_id); + + ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, attr1_val); + if (ret) + return ret; + + attr0_val = config->res_ways & ATTR0_RES_WAYS_MASK; + attr0_val |= config->bonus_ways << ATTR0_BONUS_WAYS_SHIFT; + + attr0_cfg = LLCC_TRP_ATTR0_CFGn(config->slice_id); + + ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, attr0_val); + if (ret) + return ret; + + if (config->activate_on_init) { + desc.slice_id = config->slice_id; + ret = llcc_slice_activate(&desc); + } + + return ret; +} + +static int qcom_llcc_cfg_program(struct platform_device *pdev) +{ + int i; u32 sz; int ret = 0; const struct llcc_slice_config *llcc_table; - struct llcc_slice_desc desc; sz = drv_data->cfg_size; llcc_table = drv_data->cfg; for (i = 0; i < sz; i++) { - attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); - attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); - - attr1_val = llcc_table[i].cache_mode; - attr1_val |= llcc_table[i].probe_target_ways << - ATTR1_PROBE_TARGET_WAYS_SHIFT; - attr1_val |= llcc_table[i].fixed_size << - ATTR1_FIXED_SIZE_SHIFT; - attr1_val |= llcc_table[i].priority << - ATTR1_PRIORITY_SHIFT; - - max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap); - - /* LLCC instances can vary for each target. - * The SW writes to broadcast register which gets propagated - * to each llcc instace (llcc0,.. llccN). - * Since the size of the memory is divided equally amongst the - * llcc instances, we need to configure the max cap accordingly. - */ - max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; - max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; - attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; - - attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK; - attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT; - - ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, - attr1_val); + ret = _qcom_llcc_cfg_program(&llcc_table[i]); if (ret) return ret; - ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, - attr0_val); - if (ret) - return ret; - if (llcc_table[i].activate_on_init) { - desc.slice_id = llcc_table[i].slice_id; - ret = llcc_slice_activate(&desc); - } } + return ret; } -- cgit v1.2.3 From c14e64b46944fe480d94ff33512e1855b246e690 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Tue, 15 Sep 2020 12:25:26 +0530 Subject: soc: qcom: llcc: Support chipsets that can write to llcc Older chipsets may not be allowed to configure certain LLCC registers as that is handled by the secure side software. However, this is not the case for newer chipsets and they must configure these registers according to the contents of the SCT table, while keeping in mind that older targets may not have these capabilities. So add support to allow such configuration of registers to enable capacity based allocation and power collapse retention for capable chipsets. Reason for choosing capacity based allocation rather than the default way based allocation is because capacity based allocation allows more finer grain partition and provides more flexibility in configuration. As for the retention through power collapse, it has an advantage where the cache hits are more when we wake up from power collapse although it does burn more power but the exact power numbers are not known at the moment. Signed-off-by: Isaac J. Manjarres Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd [saiprakash.ranjan@codeaurora.org: use existing config and reword commit msg] Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/dac7e11cf654fc6d75a6b5ca062ab87b01547810.1600151951.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/llcc-qcom.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 95dad1c10198..40e7df1e1cbb 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -45,6 +45,9 @@ #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) +#define LLCC_TRP_SCID_DIS_CAP_ALLOC 0x21f00 +#define LLCC_TRP_PCB_ACT 0x21f04 + #define BANK_OFFSET_STRIDE 0x80000 /** @@ -89,6 +92,7 @@ struct llcc_slice_config { struct qcom_llcc_config { const struct llcc_slice_config *sct_data; int size; + bool need_llcc_cfg; }; static const struct llcc_slice_config sc7180_data[] = { @@ -122,11 +126,13 @@ static const struct llcc_slice_config sdm845_data[] = { static const struct qcom_llcc_config sc7180_cfg = { .sct_data = sc7180_data, .size = ARRAY_SIZE(sc7180_data), + .need_llcc_cfg = true, }; static const struct qcom_llcc_config sdm845_cfg = { .sct_data = sdm845_data, .size = ARRAY_SIZE(sdm845_data), + .need_llcc_cfg = false, }; static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; @@ -318,7 +324,8 @@ size_t llcc_get_slice_size(struct llcc_slice_desc *desc) } EXPORT_SYMBOL_GPL(llcc_get_slice_size); -static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config) +static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config, + const struct qcom_llcc_config *cfg) { int ret; u32 attr1_cfg; @@ -361,6 +368,22 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config) if (ret) return ret; + if (cfg->need_llcc_cfg) { + u32 disable_cap_alloc, retain_pc; + + disable_cap_alloc = config->dis_cap_alloc << config->slice_id; + ret = regmap_write(drv_data->bcast_regmap, + LLCC_TRP_SCID_DIS_CAP_ALLOC, disable_cap_alloc); + if (ret) + return ret; + + retain_pc = config->retain_on_pc << config->slice_id; + ret = regmap_write(drv_data->bcast_regmap, + LLCC_TRP_PCB_ACT, retain_pc); + if (ret) + return ret; + } + if (config->activate_on_init) { desc.slice_id = config->slice_id; ret = llcc_slice_activate(&desc); @@ -369,7 +392,8 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config) return ret; } -static int qcom_llcc_cfg_program(struct platform_device *pdev) +static int qcom_llcc_cfg_program(struct platform_device *pdev, + const struct qcom_llcc_config *cfg) { int i; u32 sz; @@ -380,7 +404,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev) llcc_table = drv_data->cfg; for (i = 0; i < sz; i++) { - ret = _qcom_llcc_cfg_program(&llcc_table[i]); + ret = _qcom_llcc_cfg_program(&llcc_table[i], cfg); if (ret) return ret; } @@ -483,7 +507,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) mutex_init(&drv_data->lock); platform_set_drvdata(pdev, drv_data); - ret = qcom_llcc_cfg_program(pdev); + ret = qcom_llcc_cfg_program(pdev, cfg); if (ret) goto err; -- cgit v1.2.3 From 7bb7a83f4d91a09ed02f6c22d10842d26528ba40 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Mon, 5 Oct 2020 11:29:55 +0530 Subject: Revert "drivers: qcom: rpmh-rsc: Use rcuidle tracepoints for rpmh" Commit efde2659b0fe ("drivers: qcom: rpmh-rsc: Use rcuidle tracepoints for rpmh") was written to fix a bug seen in an unmerged series that implemented a struct generic_pm_domain::power_off() callback calling rpmh_flush(). See stack trace below. Call trace: dump_backtrace+0x0/0x174 show_stack+0x20/0x2c dump_stack+0xc8/0x124 lockdep_rcu_suspicious+0xe4/0x104 __tcs_buffer_write+0x230/0x2d0 rpmh_rsc_write_ctrl_data+0x210/0x270 rpmh_flush+0x84/0x24c rpmh_domain_power_off+0x78/0x98 _genpd_power_off+0x40/0xc0 genpd_power_off+0x168/0x208 Later the final merged solution is to use CPU PM notification to invoke rpmh_flush() and power_off() callback of genpd is not implemented in the driver. CPU PM notifiers are run with RCU enabled/watching (see cpu_pm_notify() and how it calls rcu_irq_enter_irqson() before calling the notifiers). Remove this change since RCU will not be idle during CPU PM notifications hence not required to use _rcuidle tracepoint. Using _rcuidle tracepoint prevented rpmh driver to be loadable module as these are not exported symbols. This reverts commit efde2659b0fe835732047357b2902cca14f054d9. Cc: Sai Prakash Ranjan Cc: John Stultz Cc: Stephen Rothwell Reviewed-by: Stephen Boyd Reviewed-by: Sai Prakash Ranjan Reviewed-by: Ulf Hansson Signed-off-by: Maulik Shah Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1601877596-32676-2-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmh-rsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index a297911afe57..35a7a503f92e 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -497,7 +497,7 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id, write_tcs_cmd(drv, RSC_DRV_CMD_MSGID, tcs_id, j, msgid); write_tcs_cmd(drv, RSC_DRV_CMD_ADDR, tcs_id, j, cmd->addr); write_tcs_cmd(drv, RSC_DRV_CMD_DATA, tcs_id, j, cmd->data); - trace_rpmh_send_msg_rcuidle(drv, tcs_id, j, msgid, cmd); + trace_rpmh_send_msg(drv, tcs_id, j, msgid, cmd); } write_tcs_reg(drv, RSC_DRV_CMD_WAIT_FOR_CMPL, tcs_id, cmd_complete); -- cgit v1.2.3 From cb3659268a12602a2ad1e8e8d34ce155bb43ae6e Mon Sep 17 00:00:00 2001 From: John Stultz Date: Mon, 5 Oct 2020 11:29:56 +0530 Subject: soc: qcom: rpmh: Allow RPMH driver to be loaded as a module This patch allow the rpmh driver to be loaded as a permenent module. Meaning it can be loaded from a module, but then cannot be unloaded. Ideally, it would include a remove hook and related logic, but the rpmh driver is fairly core to the system, so once its loaded with almost anything else to get the system to go, the dependencies are not likely to ever also be removed. So making it a permanent module at least improves things slightly over requiring it to be a built in driver. Cc: Todd Kjos Cc: Saravana Kannan Cc: Andy Gross Cc: Bjorn Andersson Cc: Rajendra Nayak Cc: linux-arm-msm@vger.kernel.org Signed-off-by: John Stultz Signed-off-by: Bjorn Andersson [mkshah: Fix typos in commit message, send after removing _rcuidle trace] Signed-off-by: Maulik Shah Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1601877596-32676-3-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/Kconfig | 2 +- drivers/soc/qcom/rpmh-rsc.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 6a3b69b43ad5..a6c00aa9c09e 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -108,7 +108,7 @@ config QCOM_RMTFS_MEM Say y here if you intend to boot the modem remoteproc. config QCOM_RPMH - bool "Qualcomm RPM-Hardened (RPMH) Communication" + tristate "Qualcomm RPM-Hardened (RPMH) Communication" depends on ARCH_QCOM || COMPILE_TEST help Support for communication with the hardened-RPM blocks in diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 35a7a503f92e..37969dcbaf14 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -1018,6 +1019,7 @@ static const struct of_device_id rpmh_drv_match[] = { { .compatible = "qcom,rpmh-rsc", }, { } }; +MODULE_DEVICE_TABLE(of, rpmh_drv_match); static struct platform_driver rpmh_driver = { .probe = rpmh_rsc_probe, @@ -1033,3 +1035,6 @@ static int __init rpmh_driver_init(void) return platform_driver_register(&rpmh_driver); } arch_initcall(rpmh_driver_init); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. RPMh Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From ee84049c1391d45c6e3ecccf45b5f679e4914253 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 18 Oct 2020 14:26:20 +0200 Subject: dt-bindings: power: rpmpd: Add SDM660 power-domains bindings Add the new bindings for SDM660 rpmpd power domains. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20201018122620.9735-2-kholk11@gmail.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 8058955fb3b9..45ec2439ff51 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -20,6 +20,7 @@ properties: - qcom,msm8996-rpmpd - qcom,msm8998-rpmpd - qcom,qcs404-rpmpd + - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sdm845-rpmhpd - qcom,sm8150-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 5e61eaf73bdd..2a39dc40483d 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -102,6 +102,18 @@ #define QCS404_LPIMX 5 #define QCS404_LPIMX_VFL 6 +/* SDM660 Power Domains */ +#define SDM660_VDDCX 0 +#define SDM660_VDDCX_AO 1 +#define SDM660_VDDCX_VFL 2 +#define SDM660_VDDMX 3 +#define SDM660_VDDMX_AO 4 +#define SDM660_VDDMX_VFL 5 +#define SDM660_SSCCX 6 +#define SDM660_SSCCX_VFL 7 +#define SDM660_SSCMX 8 +#define SDM660_SSCMX_VFL 9 + /* RPM SMD Power Domain performance levels */ #define RPM_SMD_LEVEL_RETENTION 16 #define RPM_SMD_LEVEL_RETENTION_PLUS 32 -- cgit v1.2.3 From 5fd7fb438b7ce40918fc059afe77b12b5fe46ce2 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sun, 18 Oct 2020 14:26:19 +0200 Subject: soc: qcom: rpmpd: Add SDM660 power-domains Add the shared cx/mx and sensor sub-system's cx and mx power-domains found on SDM660. Signed-off-by: Konrad Dybcio Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20201018122620.9735-1-kholk11@gmail.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmpd.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index f2168e4259b2..0de40ac1b42c 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -220,11 +220,44 @@ static const struct rpmpd_desc qcs404_desc = { .max_state = RPM_SMD_LEVEL_BINNING, }; +/* sdm660 RPM Power domains */ +DEFINE_RPMPD_PAIR(sdm660, vddcx, vddcx_ao, RWCX, LEVEL, 0); +DEFINE_RPMPD_VFL(sdm660, vddcx_vfl, RWCX, 0); + +DEFINE_RPMPD_PAIR(sdm660, vddmx, vddmx_ao, RWMX, LEVEL, 0); +DEFINE_RPMPD_VFL(sdm660, vddmx_vfl, RWMX, 0); + +DEFINE_RPMPD_LEVEL(sdm660, vdd_ssccx, RWLC, 0); +DEFINE_RPMPD_VFL(sdm660, vdd_ssccx_vfl, RWLC, 0); + +DEFINE_RPMPD_LEVEL(sdm660, vdd_sscmx, RWLM, 0); +DEFINE_RPMPD_VFL(sdm660, vdd_sscmx_vfl, RWLM, 0); + +static struct rpmpd *sdm660_rpmpds[] = { + [SDM660_VDDCX] = &sdm660_vddcx, + [SDM660_VDDCX_AO] = &sdm660_vddcx_ao, + [SDM660_VDDCX_VFL] = &sdm660_vddcx_vfl, + [SDM660_VDDMX] = &sdm660_vddmx, + [SDM660_VDDMX_AO] = &sdm660_vddmx_ao, + [SDM660_VDDMX_VFL] = &sdm660_vddmx_vfl, + [SDM660_SSCCX] = &sdm660_vdd_ssccx, + [SDM660_SSCCX_VFL] = &sdm660_vdd_ssccx_vfl, + [SDM660_SSCMX] = &sdm660_vdd_sscmx, + [SDM660_SSCMX_VFL] = &sdm660_vdd_sscmx_vfl, +}; + +static const struct rpmpd_desc sdm660_desc = { + .rpmpds = sdm660_rpmpds, + .num_pds = ARRAY_SIZE(sdm660_rpmpds), + .max_state = RPM_SMD_LEVEL_TURBO, +}; + static const struct of_device_id rpmpd_match_table[] = { { .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc }, { .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc }, { .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc }, { .compatible = "qcom,qcs404-rpmpd", .data = &qcs404_desc }, + { .compatible = "qcom,sdm660-rpmpd", .data = &sdm660_desc }, { } }; MODULE_DEVICE_TABLE(of, rpmpd_match_table); -- cgit v1.2.3 From 043323da2255a2309af8c940c848b676e38f3a59 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:26 +0200 Subject: soc: qcom: rpmpd: Rename MAX_8996_RPMPD_STATE to MAX_CORNER_RPMPD_STATE Older SoCs like MSM8916, MSM8939, MSM8974, MSM8996, ... use "voltage corners" instead of "voltage levels". It seems like they all use exactly the same set of corner values, a value from 0-6 where 6 is the maximum corner (super turbo). In preparation to add the power domains for MSM8916, rename MAX_8996_RPMPD_STATE to MAX_CORNER_RPMPD_STATE to make it clear that this is the max_state to be used for all SoCs using corners. - Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmpd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 0de40ac1b42c..55718f4a0971 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -35,7 +35,7 @@ #define KEY_FLOOR_LEVEL 0x6c6676 /* vfl */ #define KEY_LEVEL 0x6c766c76 /* vlvl */ -#define MAX_8996_RPMPD_STATE 6 +#define MAX_CORNER_RPMPD_STATE 6 #define DEFINE_RPMPD_PAIR(_platform, _name, _active, r_type, r_key, \ r_id) \ @@ -159,7 +159,7 @@ static struct rpmpd *msm8996_rpmpds[] = { static const struct rpmpd_desc msm8996_desc = { .rpmpds = msm8996_rpmpds, .num_pds = ARRAY_SIZE(msm8996_rpmpds), - .max_state = MAX_8996_RPMPD_STATE, + .max_state = MAX_CORNER_RPMPD_STATE, }; /* msm8998 RPM Power domains */ -- cgit v1.2.3 From 1dd50f17d6ce36b7d92765dc58a9f4abf78f29b9 Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Wed, 30 Sep 2020 18:01:44 +0800 Subject: dt-bindings: power: rpmpd: Add MSM8939 RPM power domains MSM8939 has three RPM power domains: VDDCX and VDDMX and VDDMDCX. Add the device tree bindings to manage them through rpmpd. Reviewed-by: Stephan Gerhold Acked-by: Rob Herring Signed-off-by: Jun Nie Link: https://lore.kernel.org/r/20200930100145.9457-2-jun.nie@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 45ec2439ff51..bd628da9318f 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,msm8939-rpmpd - qcom,msm8976-rpmpd - qcom,msm8996-rpmpd - qcom,msm8998-rpmpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 2a39dc40483d..f099de1c7912 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -64,6 +64,16 @@ #define RPMH_REGULATOR_LEVEL_TURBO 384 #define RPMH_REGULATOR_LEVEL_TURBO_L1 416 +/* MSM8939 Power Domains */ +#define MSM8939_VDDMDCX 0 +#define MSM8939_VDDMDCX_AO 1 +#define MSM8939_VDDMDCX_VFC 2 +#define MSM8939_VDDCX 3 +#define MSM8939_VDDCX_AO 4 +#define MSM8939_VDDCX_VFC 5 +#define MSM8939_VDDMX 6 +#define MSM8939_VDDMX_AO 7 + /* MSM8976 Power Domain Indexes */ #define MSM8976_VDDCX 0 #define MSM8976_VDDCX_AO 1 -- cgit v1.2.3 From b5a3bf66d7fa107172c7c0d013e2eea3774ec48e Mon Sep 17 00:00:00 2001 From: Jun Nie Date: Wed, 30 Sep 2020 18:01:45 +0800 Subject: soc: qcom: rpmpd: Add MSM8939 power-domains Add the shared modemcx/cx/mx power-domains found on MSM8939. Reviewed-by: Stephan Gerhold Signed-off-by: Jun Nie Link: https://lore.kernel.org/r/20200930100145.9457-3-jun.nie@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmpd.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 55718f4a0971..dfff128c0908 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -116,6 +116,32 @@ struct rpmpd_desc { static DEFINE_MUTEX(rpmpd_lock); +/* msm8939 RPM Power Domains */ +DEFINE_RPMPD_PAIR(msm8939, vddmd, vddmd_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_VFC(msm8939, vddmd_vfc, SMPA, 1); + +DEFINE_RPMPD_PAIR(msm8939, vddcx, vddcx_ao, SMPA, CORNER, 2); +DEFINE_RPMPD_VFC(msm8939, vddcx_vfc, SMPA, 2); + +DEFINE_RPMPD_PAIR(msm8939, vddmx, vddmx_ao, LDOA, CORNER, 3); + +static struct rpmpd *msm8939_rpmpds[] = { + [MSM8939_VDDMDCX] = &msm8939_vddmd, + [MSM8939_VDDMDCX_AO] = &msm8939_vddmd_ao, + [MSM8939_VDDMDCX_VFC] = &msm8939_vddmd_vfc, + [MSM8939_VDDCX] = &msm8939_vddcx, + [MSM8939_VDDCX_AO] = &msm8939_vddcx_ao, + [MSM8939_VDDCX_VFC] = &msm8939_vddcx_vfc, + [MSM8939_VDDMX] = &msm8939_vddmx, + [MSM8939_VDDMX_AO] = &msm8939_vddmx_ao, +}; + +static const struct rpmpd_desc msm8939_desc = { + .rpmpds = msm8939_rpmpds, + .num_pds = ARRAY_SIZE(msm8939_rpmpds), + .max_state = MAX_CORNER_RPMPD_STATE, +}; + /* msm8976 RPM Power Domains */ DEFINE_RPMPD_PAIR(msm8976, vddcx, vddcx_ao, SMPA, LEVEL, 2); DEFINE_RPMPD_PAIR(msm8976, vddmx, vddmx_ao, SMPA, LEVEL, 6); @@ -253,6 +279,7 @@ static const struct rpmpd_desc sdm660_desc = { }; static const struct of_device_id rpmpd_match_table[] = { + { .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc }, { .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc }, { .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc }, { .compatible = "qcom,msm8998-rpmpd", .data = &msm8998_desc }, -- cgit v1.2.3 From 819f7d91ad97d0660a4915e4ff4241c786fa613a Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:27 +0200 Subject: dt-bindings: power: rpmpd: Add MSM8916 RPM power domains MSM8916 has two RPM power domains: VDDCX and VDDMX. Add the device tree bindings to manage them through rpmpd. Reviewed-by: Rob Herring Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index bd628da9318f..e07453417f45 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - qcom,msm8916-rpmpd - qcom,msm8939-rpmpd - qcom,msm8976-rpmpd - qcom,msm8996-rpmpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index f099de1c7912..973329c62509 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -74,6 +74,13 @@ #define MSM8939_VDDMX 6 #define MSM8939_VDDMX_AO 7 +/* MSM8916 Power Domain Indexes */ +#define MSM8916_VDDCX 0 +#define MSM8916_VDDCX_AO 1 +#define MSM8916_VDDCX_VFC 2 +#define MSM8916_VDDMX 3 +#define MSM8916_VDDMX_AO 4 + /* MSM8976 Power Domain Indexes */ #define MSM8976_VDDCX 0 #define MSM8976_VDDCX_AO 1 -- cgit v1.2.3 From 84314cf7d0aa4f67cc791d8b858333e9b17f5371 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Wed, 16 Sep 2020 12:41:28 +0200 Subject: soc: qcom: rpmpd: Add MSM8916 power domains MSM8916 has two RPM power domains: VDDCX and VDDMX. Add the necessary definitions to manage them with rpmpd. Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20200916104135.25085-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmpd.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index dfff128c0908..85d1207b72d7 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -142,6 +142,26 @@ static const struct rpmpd_desc msm8939_desc = { .max_state = MAX_CORNER_RPMPD_STATE, }; +/* msm8916 RPM Power Domains */ +DEFINE_RPMPD_PAIR(msm8916, vddcx, vddcx_ao, SMPA, CORNER, 1); +DEFINE_RPMPD_PAIR(msm8916, vddmx, vddmx_ao, LDOA, CORNER, 3); + +DEFINE_RPMPD_VFC(msm8916, vddcx_vfc, SMPA, 1); + +static struct rpmpd *msm8916_rpmpds[] = { + [MSM8916_VDDCX] = &msm8916_vddcx, + [MSM8916_VDDCX_AO] = &msm8916_vddcx_ao, + [MSM8916_VDDCX_VFC] = &msm8916_vddcx_vfc, + [MSM8916_VDDMX] = &msm8916_vddmx, + [MSM8916_VDDMX_AO] = &msm8916_vddmx_ao, +}; + +static const struct rpmpd_desc msm8916_desc = { + .rpmpds = msm8916_rpmpds, + .num_pds = ARRAY_SIZE(msm8916_rpmpds), + .max_state = MAX_CORNER_RPMPD_STATE, +}; + /* msm8976 RPM Power Domains */ DEFINE_RPMPD_PAIR(msm8976, vddcx, vddcx_ao, SMPA, LEVEL, 2); DEFINE_RPMPD_PAIR(msm8976, vddmx, vddmx_ao, SMPA, LEVEL, 6); @@ -279,6 +299,7 @@ static const struct rpmpd_desc sdm660_desc = { }; static const struct of_device_id rpmpd_match_table[] = { + { .compatible = "qcom,msm8916-rpmpd", .data = &msm8916_desc }, { .compatible = "qcom,msm8939-rpmpd", .data = &msm8939_desc }, { .compatible = "qcom,msm8976-rpmpd", .data = &msm8976_desc }, { .compatible = "qcom,msm8996-rpmpd", .data = &msm8996_desc }, -- cgit v1.2.3 From 5d2fc13ba052149e35675da108607846659a8b14 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 19 Oct 2020 15:46:48 -0700 Subject: soc: amlogic: socinfo: build for specific arch The MX driver only supports 32-bit ARM SoCs and the GX driver only supports 64-bit SoCs. Only build for the right architecture. Reviewed-by: Jerome Brunet Reviewed-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig index 321c5e26a268..08a27d9cbc7f 100644 --- a/drivers/soc/amlogic/Kconfig +++ b/drivers/soc/amlogic/Kconfig @@ -19,7 +19,7 @@ config MESON_CLK_MEASURE config MESON_GX_SOCINFO bool "Amlogic Meson GX SoC Information driver" - depends on ARCH_MESON || COMPILE_TEST + depends on (ARM64 && ARCH_MESON) || COMPILE_TEST default ARCH_MESON select SOC_BUS help @@ -63,7 +63,7 @@ config MESON_SECURE_PM_DOMAINS config MESON_MX_SOCINFO bool "Amlogic Meson MX SoC Information driver" - depends on ARCH_MESON || COMPILE_TEST + depends on (ARM && ARCH_MESON) || COMPILE_TEST default ARCH_MESON select SOC_BUS help -- cgit v1.2.3 From d9da1785ec0caed9a52183f994afefff0da25d7e Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 19 Oct 2020 15:46:49 -0700 Subject: soc: meson: enable building drivers as modules Enable SoC drivers for 64-bit Amlogic SoCs to be built as modules. Signed-off-by: Kevin Hilman --- drivers/soc/amlogic/Kconfig | 8 ++++---- drivers/soc/amlogic/meson-clk-measure.c | 5 ++++- drivers/soc/amlogic/meson-ee-pwrc.c | 5 ++++- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 5 ++++- drivers/soc/amlogic/meson-secure-pwrc.c | 5 ++++- 5 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig index 08a27d9cbc7f..174a9b011461 100644 --- a/drivers/soc/amlogic/Kconfig +++ b/drivers/soc/amlogic/Kconfig @@ -9,7 +9,7 @@ config MESON_CANVAS Say yes to support the canvas IP for Amlogic SoCs. config MESON_CLK_MEASURE - bool "Amlogic Meson SoC Clock Measure driver" + tristate "Amlogic Meson SoC Clock Measure driver" depends on ARCH_MESON || COMPILE_TEST default ARCH_MESON select REGMAP_MMIO @@ -27,7 +27,7 @@ config MESON_GX_SOCINFO information about the type, package and version. config MESON_GX_PM_DOMAINS - bool "Amlogic Meson GX Power Domains driver" + tristate "Amlogic Meson GX Power Domains driver" depends on ARCH_MESON || COMPILE_TEST depends on PM && OF default ARCH_MESON @@ -38,7 +38,7 @@ config MESON_GX_PM_DOMAINS Generic Power Domains. config MESON_EE_PM_DOMAINS - bool "Amlogic Meson Everything-Else Power Domains driver" + tristate "Amlogic Meson Everything-Else Power Domains driver" depends on ARCH_MESON || COMPILE_TEST depends on PM && OF default ARCH_MESON @@ -49,7 +49,7 @@ config MESON_EE_PM_DOMAINS Generic Power Domains. config MESON_SECURE_PM_DOMAINS - bool "Amlogic Meson Secure Power Domains driver" + tristate "Amlogic Meson Secure Power Domains driver" depends on (ARCH_MESON || COMPILE_TEST) && MESON_SM depends on PM && OF depends on HAVE_ARM_SMCCC diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c index 0fa47d77577d..e1957476a006 100644 --- a/drivers/soc/amlogic/meson-clk-measure.c +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -10,6 +10,7 @@ #include #include #include +#include static DEFINE_MUTEX(measure_lock); @@ -681,6 +682,7 @@ static const struct of_device_id meson_msr_match_table[] = { }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, meson_msr_match_table); static struct platform_driver meson_msr_driver = { .probe = meson_msr_probe, @@ -689,4 +691,5 @@ static struct platform_driver meson_msr_driver = { .of_match_table = meson_msr_match_table, }, }; -builtin_platform_driver(meson_msr_driver); +module_platform_driver(meson_msr_driver); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c index 5164a4dc2352..ed7d2fbb47f2 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -602,6 +603,7 @@ static const struct of_device_id meson_ee_pwrc_match_table[] = { }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, meson_ee_pwrc_match_table); static struct platform_driver meson_ee_pwrc_driver = { .probe = meson_ee_pwrc_probe, @@ -611,4 +613,5 @@ static struct platform_driver meson_ee_pwrc_driver = { .of_match_table = meson_ee_pwrc_match_table, }, }; -builtin_platform_driver(meson_ee_pwrc_driver); +module_platform_driver(meson_ee_pwrc_driver); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c index 21b4bc811c00..8790627e3098 100644 --- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c +++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c @@ -14,6 +14,7 @@ #include #include #include +#include /* AO Offsets */ @@ -364,6 +365,7 @@ static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = { }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, meson_gx_pwrc_vpu_match_table); static struct platform_driver meson_gx_pwrc_vpu_driver = { .probe = meson_gx_pwrc_vpu_probe, @@ -373,4 +375,5 @@ static struct platform_driver meson_gx_pwrc_vpu_driver = { .of_match_table = meson_gx_pwrc_vpu_match_table, }, }; -builtin_platform_driver(meson_gx_pwrc_vpu_driver); +module_platform_driver(meson_gx_pwrc_vpu_driver); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c index 5fb29a475879..59bd195fa9c9 100644 --- a/drivers/soc/amlogic/meson-secure-pwrc.c +++ b/drivers/soc/amlogic/meson-secure-pwrc.c @@ -13,6 +13,7 @@ #include #include #include +#include #define PWRC_ON 1 #define PWRC_OFF 0 @@ -193,6 +194,7 @@ static const struct of_device_id meson_secure_pwrc_match_table[] = { }, { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, meson_secure_pwrc_match_table); static struct platform_driver meson_secure_pwrc_driver = { .probe = meson_secure_pwrc_probe, @@ -201,4 +203,5 @@ static struct platform_driver meson_secure_pwrc_driver = { .of_match_table = meson_secure_pwrc_match_table, }, }; -builtin_platform_driver(meson_secure_pwrc_driver); +module_platform_driver(meson_secure_pwrc_driver); +MODULE_LICENSE("Dual MIT/GPL"); -- cgit v1.2.3 From e2bcad676c6bb36af4c1cec197ff1b89fb70af64 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 2 Oct 2020 17:57:13 +0200 Subject: MAINTAINERS: add dt binding headers to memory controller drivers entry Cover also the include/dt-bindings/memory/ headers in the memory controller drivers entry. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201002155713.3569-1-krzk@kernel.org --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index e73636b75f29..31121657ac6a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11332,6 +11332,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git F: Documentation/devicetree/bindings/memory-controllers/ F: drivers/memory/ +F: include/dt-bindings/memory/ MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA M: Dmitry Osipenko -- cgit v1.2.3 From 4a434abc40d2a0c15032f88e30aeb7ad271ba795 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Mon, 21 Sep 2020 15:11:19 -0700 Subject: firmware: meson-sm: enable build as module Enable secure module driver as module. Default remains built-in. Signed-off-by: Kevin Hilman --- drivers/firmware/meson/Kconfig | 5 +++-- drivers/firmware/meson/meson_sm.c | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/firmware/meson/Kconfig b/drivers/firmware/meson/Kconfig index 2671dcd0ad92..f2fdd3756648 100644 --- a/drivers/firmware/meson/Kconfig +++ b/drivers/firmware/meson/Kconfig @@ -3,8 +3,9 @@ # Amlogic Secure Monitor driver # config MESON_SM - bool - default ARCH_MESON + tristate "Amlogic Secure Monitor driver" + depends on ARCH_MESON || COMPILE_TEST + default y depends on ARM64_4K_PAGES help Say y here to enable the Amlogic secure monitor driver diff --git a/drivers/firmware/meson/meson_sm.c b/drivers/firmware/meson/meson_sm.c index 2854b56f6e0b..77aa5c6398aa 100644 --- a/drivers/firmware/meson/meson_sm.c +++ b/drivers/firmware/meson/meson_sm.c @@ -331,3 +331,4 @@ static struct platform_driver meson_sm_driver = { }, }; module_platform_driver_probe(meson_sm_driver, meson_sm_probe); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From 778279f4f5e4e89ff31803ba48135256563825c2 Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Thu, 1 Oct 2020 09:41:44 -0600 Subject: soc: qcom: cmd-db: allow loading as a module This patch enables Command DB driver to be loaded as a module. Command DB is inherent to RPMH interaction and as such would never be unloaded. Add supress_bind_attrs to make it a permanently loaded module. Reviewed-by: John Stultz Reviewed-by: Greg Kroah-Hartman Tested-by: John Stultz Signed-off-by: Lina Iyer Link: https://lore.kernel.org/r/20201001154144.5226-1-ilina@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/Kconfig | 2 +- drivers/soc/qcom/cmd-db.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index a6c00aa9c09e..9b4ae9c16ba7 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -17,7 +17,7 @@ config QCOM_AOSS_QMP Subsystem (AOSS) using Qualcomm Messaging Protocol (QMP). config QCOM_COMMAND_DB - bool "Qualcomm Command DB" + tristate "Qualcomm Command DB" depends on ARCH_QCOM || COMPILE_TEST depends on OF_RESERVED_MEM help diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index fc5610603b17..dd872017f345 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -1,8 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. */ +/* Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved. */ #include #include +#include #include #include #include @@ -340,12 +341,14 @@ static const struct of_device_id cmd_db_match_table[] = { { .compatible = "qcom,cmd-db" }, { } }; +MODULE_DEVICE_TABLE(of, cmd_db_match_table); static struct platform_driver cmd_db_dev_driver = { .probe = cmd_db_dev_probe, .driver = { .name = "cmd-db", .of_match_table = cmd_db_match_table, + .suppress_bind_attrs = true, }, }; @@ -354,3 +357,6 @@ static int __init cmd_db_device_init(void) return platform_driver_register(&cmd_db_dev_driver); } arch_initcall(cmd_db_device_init); + +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Command DB Driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From c14bea053775e0c79a6fdd2d1b5a1d9de4fbd7c7 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:42 -0700 Subject: memory: tegra: Correct la.reg address of seswr According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field [23:16] of register at address 0x3e0 with a reset value of 0x80 at register 0x3e0, while bit-1 of register 0xb98 is for enable bit of seswr. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-2-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 7fb8b5438bf4..088814279616 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -897,7 +897,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .bit = 1, }, .la = { - .reg = 0xb98, + .reg = 0x3e0, .shift = 16, .mask = 0xff, .def = 0x80, -- cgit v1.2.3 From f68ac0e6bd83582b1a8ebf1b76c03eacea25fa49 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:43 -0700 Subject: memory: tegra: Correct tegra210_mc_clients def values Some def values are mismatched with Tegra X1 TRM, probably because being copied from tegra124.c file. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-3-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index 088814279616..e8a7d266802c 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -24,7 +24,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2e8, .shift = 0, .mask = 0xff, - .def = 0xc2, + .def = 0x1e, }, }, { .id = 0x02, @@ -38,7 +38,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f4, .shift = 0, .mask = 0xff, - .def = 0xc6, + .def = 0x1e, }, }, { .id = 0x03, @@ -52,7 +52,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2e8, .shift = 16, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x04, @@ -66,7 +66,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f4, .shift = 16, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x05, @@ -80,7 +80,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2ec, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x06, @@ -94,7 +94,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f8, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x0e, @@ -108,7 +108,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2e0, .shift = 0, .mask = 0xff, - .def = 0x13, + .def = 0x2e, }, }, { .id = 0x0f, @@ -136,7 +136,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f0, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x11, @@ -150,7 +150,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2fc, .shift = 0, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x15, @@ -380,7 +380,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x350, .shift = 16, .mask = 0xff, - .def = 0x65, + .def = 0x80, }, }, { .id = 0x44, @@ -620,7 +620,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x2f0, .shift = 16, .mask = 0xff, - .def = 0x50, + .def = 0x1e, }, }, { .id = 0x60, @@ -648,7 +648,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x3bc, .shift = 0, .mask = 0xff, - .def = 0x49, + .def = 0x5a, }, }, { .id = 0x62, @@ -676,7 +676,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x3c4, .shift = 0, .mask = 0xff, - .def = 0x49, + .def = 0x5a, }, }, { .id = 0x64, @@ -956,7 +956,7 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { .reg = 0x3ec, .shift = 16, .mask = 0xff, - .def = 0xff, + .def = 0x80, }, }, { .id = 0x86, -- cgit v1.2.3 From 78e4ea785c0737c906f4830c79d21dc6cb928f68 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:44 -0700 Subject: memory: tegra: Sort tegra210_swgroups by reg address Cleanup the list of swgroups (ordering by register address) to prepare for new ones. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-4-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index e8a7d266802c..b400802c9f14 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1020,32 +1020,32 @@ static const struct tegra_mc_client tegra210_mc_clients[] = { }; static const struct tegra_smmu_swgroup tegra210_swgroups[] = { - { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, - { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 }, { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c }, - { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, + { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 }, + { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 }, { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 }, + { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, + { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, - { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, + { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, + { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 }, { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, - { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, - { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, - { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, + { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 }, { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 }, { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c }, { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 }, - { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 }, - { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, + { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, + { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 }, { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 }, - { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc }, + { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc }, { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 }, { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 }, -- cgit v1.2.3 From 65abc8ef57009b95fcded5136aed8ccaff46b903 Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:45 -0700 Subject: dt-bindings: memory: tegra: Add missing swgroups According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them in bindings. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-5-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- include/dt-bindings/memory/tegra210-mc.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h index cacf05617e03..5e082547f179 100644 --- a/include/dt-bindings/memory/tegra210-mc.h +++ b/include/dt-bindings/memory/tegra210-mc.h @@ -33,6 +33,16 @@ #define TEGRA_SWGROUP_AXIAP 28 #define TEGRA_SWGROUP_ETR 29 #define TEGRA_SWGROUP_TSECB 30 +#define TEGRA_SWGROUP_NV 31 +#define TEGRA_SWGROUP_NV2 32 +#define TEGRA_SWGROUP_PPCS1 33 +#define TEGRA_SWGROUP_DC1 34 +#define TEGRA_SWGROUP_PPCS2 35 +#define TEGRA_SWGROUP_HC1 36 +#define TEGRA_SWGROUP_SE1 37 +#define TEGRA_SWGROUP_TSEC1 38 +#define TEGRA_SWGROUP_TSECB1 39 +#define TEGRA_SWGROUP_NVDEC1 40 #define TEGRA210_MC_RESET_AFI 0 #define TEGRA210_MC_RESET_AVPC 1 -- cgit v1.2.3 From 827b5e6ec1144a34de27247a45a2f78b25d753a3 Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Wed, 7 Oct 2020 22:09:07 -0600 Subject: soc: qcom: Kconfig: make RPMH match Command DB setting RPMH and drivers that use RPMH APIs need Command DB API to find the dynamic resource information. Let's match the RPMH to match the Command DB configuration. This should fix undefined symbol references reported by CI : aarch64-linux-ld: drivers/clk/qcom/clk-rpmh.o: in function `clk_rpmh_probe': >> clk-rpmh.c:(.text+0xac): undefined reference to `cmd_db_read_addr' >> aarch64-linux-ld: clk-rpmh.c:(.text+0xc0): undefined reference to `cmd_db_read_aux_data' aarch64-linux-ld: drivers/soc/qcom/rpmh-rsc.o: in function `rpmh_rsc_probe': >> rpmh-rsc.c:(.text+0x42c): undefined reference to `cmd_db_ready' aarch64-linux-ld: drivers/regulator/qcom-rpmh-regulator.o: in function `rpmh_regulator_probe': >> qcom-rpmh-regulator.c:(.text+0x3e0): undefined reference to `cmd_db_read_addr' Cc: Todd Kjos Cc: John Stultz Cc: Maulik Shah Reported-by: kernel test robot Signed-off-by: Lina Iyer Link: https://lore.kernel.org/r/20201008040907.7036-1-ilina@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 9b4ae9c16ba7..79b568f82a1c 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -110,6 +110,7 @@ config QCOM_RMTFS_MEM config QCOM_RPMH tristate "Qualcomm RPM-Hardened (RPMH) Communication" depends on ARCH_QCOM || COMPILE_TEST + depends on (QCOM_COMMAND_DB || !QCOM_COMMAND_DB) help Support for communication with the hardened-RPM blocks in Qualcomm Technologies Inc (QTI) SoCs. RPMH communication uses an -- cgit v1.2.3 From 95de5094f5ac50b6f355f4e7dffcb6f34bd5dada Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 22 Sep 2020 18:24:29 +0800 Subject: firmware: imx: add dummy functions add dummy functions to avoid build failure when header files are included, but drivers are not built. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- include/linux/firmware/imx/ipc.h | 13 +++++++++++++ include/linux/firmware/imx/sci.h | 27 +++++++++++++++++++++++++++ include/linux/firmware/imx/svc/misc.h | 19 +++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/include/linux/firmware/imx/ipc.h b/include/linux/firmware/imx/ipc.h index 891057434858..0b4643571625 100644 --- a/include/linux/firmware/imx/ipc.h +++ b/include/linux/firmware/imx/ipc.h @@ -34,6 +34,7 @@ struct imx_sc_rpc_msg { uint8_t func; }; +#ifdef CONFIG_IMX_SCU /* * This is an function to send an RPC message over an IPC channel. * It is called by client-side SCFW API function shims. @@ -55,4 +56,16 @@ int imx_scu_call_rpc(struct imx_sc_ipc *ipc, void *msg, bool have_resp); * @return Returns an error code (0 = success, failed if < 0) */ int imx_scu_get_handle(struct imx_sc_ipc **ipc); +#else +static inline int imx_scu_call_rpc(struct imx_sc_ipc *ipc, void *msg, + bool have_resp) +{ + return -ENOTSUPP; +} + +static inline int imx_scu_get_handle(struct imx_sc_ipc **ipc) +{ + return -ENOTSUPP; +} +#endif #endif /* _SC_IPC_H */ diff --git a/include/linux/firmware/imx/sci.h b/include/linux/firmware/imx/sci.h index 22c76571a294..5cc63fe7e84d 100644 --- a/include/linux/firmware/imx/sci.h +++ b/include/linux/firmware/imx/sci.h @@ -16,9 +16,36 @@ #include #include +#if IS_ENABLED(CONFIG_IMX_SCU) int imx_scu_enable_general_irq_channel(struct device *dev); int imx_scu_irq_register_notifier(struct notifier_block *nb); int imx_scu_irq_unregister_notifier(struct notifier_block *nb); int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable); int imx_scu_soc_init(struct device *dev); +#else +static inline int imx_scu_soc_init(struct device *dev) +{ + return -ENOTSUPP; +} + +static inline int imx_scu_enable_general_irq_channel(struct device *dev) +{ + return -ENOTSUPP; +} + +static inline int imx_scu_irq_register_notifier(struct notifier_block *nb) +{ + return -ENOTSUPP; +} + +static inline int imx_scu_irq_unregister_notifier(struct notifier_block *nb) +{ + return -ENOTSUPP; +} + +static inline int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) +{ + return -ENOTSUPP; +} +#endif #endif /* _SC_SCI_H */ diff --git a/include/linux/firmware/imx/svc/misc.h b/include/linux/firmware/imx/svc/misc.h index 031dd4d3c766..760db08a67fc 100644 --- a/include/linux/firmware/imx/svc/misc.h +++ b/include/linux/firmware/imx/svc/misc.h @@ -46,6 +46,7 @@ enum imx_misc_func { * Control Functions */ +#ifdef CONFIG_IMX_SCU int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource, u8 ctrl, u32 val); @@ -54,5 +55,23 @@ int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource, int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource, bool enable, u64 phys_addr); +#else +static inline int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, + u32 resource, u8 ctrl, u32 val) +{ + return -ENOTSUPP; +} +static inline int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, + u32 resource, u8 ctrl, u32 *val) +{ + return -ENOTSUPP; +} + +static inline int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource, + bool enable, u64 phys_addr) +{ + return -ENOTSUPP; +} +#endif #endif /* _SC_MISC_API_H */ -- cgit v1.2.3 From 39613eaad3ceff320da344427a70c655e783475e Mon Sep 17 00:00:00 2001 From: Viresh Kumar Date: Wed, 28 Oct 2020 12:16:10 +0530 Subject: qcom-geni-se: remove has_opp_table has_opp_table isn't used anymore, remove it. Signed-off-by: Viresh Kumar Link: https://lore.kernel.org/r/08ec1ee1d4252a266956abb5f1e0e0026d753564.1603867487.git.viresh.kumar@linaro.org Signed-off-by: Bjorn Andersson --- include/linux/qcom-geni-se.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h index f7bbea3f09ca..ec2ad4b0fe14 100644 --- a/include/linux/qcom-geni-se.h +++ b/include/linux/qcom-geni-se.h @@ -48,7 +48,6 @@ struct geni_icc_path { * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE * @opp_table: Pointer to the OPP table - * @has_opp_table: Specifies if the SE has an OPP table */ struct geni_se { void __iomem *base; @@ -59,7 +58,6 @@ struct geni_se { unsigned long *clk_perf_tbl; struct geni_icc_path icc_paths[3]; struct opp_table *opp_table; - bool has_opp_table; }; /* Common SE registers */ -- cgit v1.2.3 From 786c395dbe4216c2349914952b8cdb57ea8a326a Mon Sep 17 00:00:00 2001 From: Kai Stuhlemmer Date: Thu, 8 Oct 2020 14:50:28 +0200 Subject: ARM: at91: sam9x60 SiP types added to soc description Adding SAM9X60 SIP variants to the soc description list. Signed-off-by: Kai Stuhlemmer Signed-off-by: Nicolas Ferre Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20201008125028.21071-1-nicolas.ferre@microchip.com --- drivers/soc/atmel/soc.c | 6 ++++++ drivers/soc/atmel/soc.h | 3 +++ 2 files changed, 9 insertions(+) diff --git a/drivers/soc/atmel/soc.c b/drivers/soc/atmel/soc.c index 55a1f57a4d8c..c4472b68b7c2 100644 --- a/drivers/soc/atmel/soc.c +++ b/drivers/soc/atmel/soc.c @@ -69,6 +69,12 @@ static const struct at91_soc __initconst socs[] = { #endif #ifdef CONFIG_SOC_SAM9X60 AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_EXID_MATCH, "sam9x60", "sam9x60"), + AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, + "sam9x60 64MiB DDR2 SiP", "sam9x60"), + AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, + "sam9x60 128MiB DDR2 SiP", "sam9x60"), + AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, + "sam9x60 8MiB SDRAM SiP", "sam9x60"), #endif #ifdef CONFIG_SOC_SAMA5 AT91_SOC(SAMA5D2_CIDR_MATCH, SAMA5D21CU_EXID_MATCH, diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h index ee652e4841a5..5849846a69d6 100644 --- a/drivers/soc/atmel/soc.h +++ b/drivers/soc/atmel/soc.h @@ -60,6 +60,9 @@ at91_soc_init(const struct at91_soc *socs); #define AT91SAM9CN11_EXID_MATCH 0x00000009 #define SAM9X60_EXID_MATCH 0x00000000 +#define SAM9X60_D5M_EXID_MATCH 0x00000001 +#define SAM9X60_D1G_EXID_MATCH 0x00000010 +#define SAM9X60_D6K_EXID_MATCH 0x00000011 #define AT91SAM9XE128_CIDR_MATCH 0x329973a0 #define AT91SAM9XE256_CIDR_MATCH 0x329a93a0 -- cgit v1.2.3 From 93618e344a5ee995249ab6af813092d08313ea83 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 18:56:45 +0200 Subject: soc: samsung: exynos-pmu: instantiate clkout driver as MFD The Exynos clock output (clkout) driver uses same register address space (Power Management Unit address space) as Exynos PMU driver and same set of compatibles. It was modeled as clock provider instantiated with CLK_OF_DECLARE_DRIVER(). This however brings ordering problems and lack of probe deferral, therefore clkout driver should be converted to a regular module and instantiated as a child of PMU driver to be able to use existing compatibles and address space. Signed-off-by: Krzysztof Kozlowski Tested-by: Sylwester Nawrocki Reviewed-by: Sylwester Nawrocki Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20201001165646.32279-2-krzk@kernel.org --- drivers/soc/samsung/exynos-pmu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 17304fa18429..a18c93a4646c 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -97,6 +98,10 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { { /*sentinel*/ }, }; +static const struct mfd_cell exynos_pmu_devs[] = { + { .name = "exynos-clkout", }, +}; + struct regmap *exynos_get_pmu_regmap(void) { struct device_node *np = of_find_matching_node(NULL, @@ -110,6 +115,7 @@ EXPORT_SYMBOL_GPL(exynos_get_pmu_regmap); static int exynos_pmu_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + int ret; pmu_base_addr = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pmu_base_addr)) @@ -128,6 +134,11 @@ static int exynos_pmu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pmu_context); + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, exynos_pmu_devs, + ARRAY_SIZE(exynos_pmu_devs), NULL, 0, NULL); + if (ret) + return ret; + if (devm_of_platform_populate(dev)) dev_err(dev, "Error populating children, reboot and poweroff might not work properly\n"); -- cgit v1.2.3 From 9484f2cb83327c4197c0809cdf3156d4213c44e5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 1 Oct 2020 18:56:46 +0200 Subject: clk: samsung: exynos-clkout: convert to module driver The Exynos clkout driver depends on board input clock (typically XXTI or XUSBXTI), however on Exynos4 boards these clocks were modeled as part of SoC clocks (Exynos4 clocks driver). Obviously this is not proper, but correcting it would break DT backward compatibility. Both drivers - clkout and Exynos4 clocks - register the clock providers with CLK_OF_DECLARE/OF_DECLARE_1 so their order is fragile (in the Makefile clkout is behind Exynos4 clock). It will work only if the Exynos4 clock driver comes up before clkout. A change in DTS adding input clock reference to Exynos4 clocks input PLL, see reverted commit eaf2d2f6895d ("ARM: dts: exynos: add input clock to CMU in Exynos4412 Odroid"), caused probe reorder: the clkout appeared before Exynos4 clock provider. Since clkout depends on Exynos4 clocks and does not support deferred probe, this did not work and caused later failure of usb3503 USB hub probe which needs clkout: [ 5.007442] usb3503 0-0008: unable to request refclk (-517) The Exynos clkout driver is not a critical/core clock so there is actually no problem in instantiating it later, as a regular module. This removes specific probe ordering and adds support for probe deferral. Signed-off-by: Krzysztof Kozlowski Tested-by: Sylwester Nawrocki Reviewed-by: Sylwester Nawrocki Link: https://lore.kernel.org/r/20201001165646.32279-3-krzk@kernel.org --- drivers/clk/samsung/clk-exynos-clkout.c | 198 +++++++++++++++++++++++--------- 1 file changed, 141 insertions(+), 57 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 34ccb1d23bc3..f5f8a956b316 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -9,10 +9,13 @@ #include #include #include +#include #include #include #include -#include +#include +#include +#include #define EXYNOS_CLKOUT_NR_CLKS 1 #define EXYNOS_CLKOUT_PARENTS 32 @@ -28,41 +31,102 @@ struct exynos_clkout { struct clk_mux mux; spinlock_t slock; void __iomem *reg; + struct device_node *np; u32 pmu_debug_save; struct clk_hw_onecell_data data; }; -static struct exynos_clkout *clkout; +struct exynos_clkout_variant { + u32 mux_mask; +}; -static int exynos_clkout_suspend(void) -{ - clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG); +static const struct exynos_clkout_variant exynos_clkout_exynos4 = { + .mux_mask = EXYNOS4_CLKOUT_MUX_MASK, +}; - return 0; -} +static const struct exynos_clkout_variant exynos_clkout_exynos5 = { + .mux_mask = EXYNOS5_CLKOUT_MUX_MASK, +}; -static void exynos_clkout_resume(void) +static const struct of_device_id exynos_clkout_ids[] = { + { + .compatible = "samsung,exynos3250-pmu", + .data = &exynos_clkout_exynos4, + }, { + .compatible = "samsung,exynos4210-pmu", + .data = &exynos_clkout_exynos4, + }, { + .compatible = "samsung,exynos4412-pmu", + .data = &exynos_clkout_exynos4, + }, { + .compatible = "samsung,exynos5250-pmu", + .data = &exynos_clkout_exynos5, + }, { + .compatible = "samsung,exynos5410-pmu", + .data = &exynos_clkout_exynos5, + }, { + .compatible = "samsung,exynos5420-pmu", + .data = &exynos_clkout_exynos5, + }, { + .compatible = "samsung,exynos5433-pmu", + .data = &exynos_clkout_exynos5, + }, { } +}; + +/* + * Device will be instantiated as child of PMU device without its own + * device node. Therefore match compatibles against parent. + */ +static int exynos_clkout_match_parent_dev(struct device *dev, u32 *mux_mask) { - writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG); -} + const struct exynos_clkout_variant *variant; + const struct of_device_id *match; -static struct syscore_ops exynos_clkout_syscore_ops = { - .suspend = exynos_clkout_suspend, - .resume = exynos_clkout_resume, -}; + if (!dev->parent) { + dev_err(dev, "not instantiated from MFD\n"); + return -EINVAL; + } + + match = of_match_device(exynos_clkout_ids, dev->parent); + if (!match) { + dev_err(dev, "cannot match parent device\n"); + return -EINVAL; + } + variant = match->data; -static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) + *mux_mask = variant->mux_mask; + + return 0; +} + +static int exynos_clkout_probe(struct platform_device *pdev) { const char *parent_names[EXYNOS_CLKOUT_PARENTS]; struct clk *parents[EXYNOS_CLKOUT_PARENTS]; - int parent_count; - int ret; - int i; + struct exynos_clkout *clkout; + int parent_count, ret, i; + u32 mux_mask; - clkout = kzalloc(struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS), - GFP_KERNEL); + clkout = devm_kzalloc(&pdev->dev, + struct_size(clkout, data.hws, EXYNOS_CLKOUT_NR_CLKS), + GFP_KERNEL); if (!clkout) - return; + return -ENOMEM; + + ret = exynos_clkout_match_parent_dev(&pdev->dev, &mux_mask); + if (ret) + return ret; + + clkout->np = pdev->dev.of_node; + if (!clkout->np) { + /* + * pdev->dev.parent was checked by exynos_clkout_match_parent_dev() + * so it is not NULL. + */ + clkout->np = pdev->dev.parent->of_node; + } + + platform_set_drvdata(pdev, clkout); spin_lock_init(&clkout->slock); @@ -71,7 +135,7 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) char name[] = "clkoutXX"; snprintf(name, sizeof(name), "clkout%d", i); - parents[i] = of_clk_get_by_name(node, name); + parents[i] = of_clk_get_by_name(clkout->np, name); if (IS_ERR(parents[i])) { parent_names[i] = "none"; continue; @@ -82,11 +146,13 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) } if (!parent_count) - goto free_clkout; + return -EINVAL; - clkout->reg = of_iomap(node, 0); - if (!clkout->reg) + clkout->reg = of_iomap(clkout->np, 0); + if (!clkout->reg) { + ret = -ENODEV; goto clks_put; + } clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG; clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT; @@ -103,17 +169,17 @@ static void __init exynos_clkout_init(struct device_node *node, u32 mux_mask) &clk_mux_ops, NULL, NULL, &clkout->gate.hw, &clk_gate_ops, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT); - if (IS_ERR(clkout->data.hws[0])) + if (IS_ERR(clkout->data.hws[0])) { + ret = PTR_ERR(clkout->data.hws[0]); goto err_unmap; + } clkout->data.num = EXYNOS_CLKOUT_NR_CLKS; - ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clkout->data); + ret = of_clk_add_hw_provider(clkout->np, of_clk_hw_onecell_get, &clkout->data); if (ret) goto err_clk_unreg; - register_syscore_ops(&exynos_clkout_syscore_ops); - - return; + return 0; err_clk_unreg: clk_hw_unregister(clkout->data.hws[0]); @@ -123,38 +189,56 @@ clks_put: for (i = 0; i < EXYNOS_CLKOUT_PARENTS; ++i) if (!IS_ERR(parents[i])) clk_put(parents[i]); -free_clkout: - kfree(clkout); - pr_err("%s: failed to register clkout clock\n", __func__); + dev_err(&pdev->dev, "failed to register clkout clock\n"); + + return ret; } -/* - * We use CLK_OF_DECLARE_DRIVER initialization method to avoid setting - * the OF_POPULATED flag on the pmu device tree node, so later the - * Exynos PMU platform device can be properly probed with PMU driver. - */ +static int exynos_clkout_remove(struct platform_device *pdev) +{ + struct exynos_clkout *clkout = platform_get_drvdata(pdev); + + of_clk_del_provider(clkout->np); + clk_hw_unregister(clkout->data.hws[0]); + iounmap(clkout->reg); + + return 0; +} -static void __init exynos4_clkout_init(struct device_node *node) +static int exynos_clkout_suspend(struct device *dev) { - exynos_clkout_init(node, EXYNOS4_CLKOUT_MUX_MASK); + struct exynos_clkout *clkout = dev_get_drvdata(dev); + + clkout->pmu_debug_save = readl(clkout->reg + EXYNOS_PMU_DEBUG_REG); + + return 0; } -CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu", - exynos4_clkout_init); -CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu", - exynos4_clkout_init); -CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu", - exynos4_clkout_init); - -static void __init exynos5_clkout_init(struct device_node *node) + +static int exynos_clkout_resume(struct device *dev) { - exynos_clkout_init(node, EXYNOS5_CLKOUT_MUX_MASK); + struct exynos_clkout *clkout = dev_get_drvdata(dev); + + writel(clkout->pmu_debug_save, clkout->reg + EXYNOS_PMU_DEBUG_REG); + + return 0; } -CLK_OF_DECLARE_DRIVER(exynos5250_clkout, "samsung,exynos5250-pmu", - exynos5_clkout_init); -CLK_OF_DECLARE_DRIVER(exynos5410_clkout, "samsung,exynos5410-pmu", - exynos5_clkout_init); -CLK_OF_DECLARE_DRIVER(exynos5420_clkout, "samsung,exynos5420-pmu", - exynos5_clkout_init); -CLK_OF_DECLARE_DRIVER(exynos5433_clkout, "samsung,exynos5433-pmu", - exynos5_clkout_init); + +static SIMPLE_DEV_PM_OPS(exynos_clkout_pm_ops, exynos_clkout_suspend, + exynos_clkout_resume); + +static struct platform_driver exynos_clkout_driver = { + .driver = { + .name = "exynos-clkout", + .of_match_table = exynos_clkout_ids, + .pm = &exynos_clkout_pm_ops, + }, + .probe = exynos_clkout_probe, + .remove = exynos_clkout_remove, +}; +module_platform_driver(exynos_clkout_driver); + +MODULE_AUTHOR("Krzysztof Kozlowski "); +MODULE_AUTHOR("Tomasz Figa "); +MODULE_DESCRIPTION("Samsung Exynos clock output driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 0f12999e27e087cd4c832760b59efd58c9642bb2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 11 Sep 2020 16:33:41 +0200 Subject: Documentation: Update paths of Samsung S3C machine files Documentation references Samsung S3C24xx and S3C64xx machine files in multiple places but the files were traveling around the kernel multiple times. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200911143343.498-1-krzk@kernel.org --- Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/arm/samsung-s3c24xx/gpio.rst | 4 ++-- Documentation/arm/samsung-s3c24xx/overview.rst | 22 +++++++--------------- Documentation/arm/samsung-s3c24xx/usb-host.rst | 6 +++--- Documentation/arm/samsung/gpio.rst | 3 +-- .../device_drivers/ethernet/davicom/dm9000.rst | 2 +- 6 files changed, 15 insertions(+), 24 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 526d65d8573a..bd512b70286d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2951,7 +2951,7 @@ mtdset= [ARM] ARM/S3C2412 JIVE boot control - See arch/arm/mach-s3c2412/mach-jive.c + See arch/arm/mach-s3c/mach-jive.c mtouchusb.raw_coordinates= [HW] Make the MicroTouch USB driver use raw coordinates diff --git a/Documentation/arm/samsung-s3c24xx/gpio.rst b/Documentation/arm/samsung-s3c24xx/gpio.rst index f7c3d7d011a2..f4a8c800a457 100644 --- a/Documentation/arm/samsung-s3c24xx/gpio.rst +++ b/Documentation/arm/samsung-s3c24xx/gpio.rst @@ -29,7 +29,7 @@ GPIOLIB The following functions now either have a `s3c_` specific variant or are merged into gpiolib. See the definitions in - arch/arm/plat-samsung/include/plat/gpio-cfg.h: + arch/arm/mach-s3c/gpio-cfg.h: - s3c2410_gpio_setpin() gpio_set_value() or gpio_direction_output() - s3c2410_gpio_getpin() gpio_get_value() or gpio_direction_input() @@ -86,7 +86,7 @@ between the calls. Headers ------- - See arch/arm/mach-s3c24xx/include/mach/regs-gpio.h for the list + See arch/arm/mach-s3c/regs-gpio-s3c24xx.h for the list of GPIO pins, and the configuration values for them. This is included by using #include diff --git a/Documentation/arm/samsung-s3c24xx/overview.rst b/Documentation/arm/samsung-s3c24xx/overview.rst index e9a1dc7276b5..14535e5cffb7 100644 --- a/Documentation/arm/samsung-s3c24xx/overview.rst +++ b/Documentation/arm/samsung-s3c24xx/overview.rst @@ -18,7 +18,7 @@ Introduction versions. The S3C2416 and S3C2450 devices are very similar and S3C2450 support is - included under the arch/arm/mach-s3c2416 directory. Note, while core + included under the arch/arm/mach-s3c directory. Note, while core support for these SoCs is in, work on some of the extra peripherals and extra interrupts is still ongoing. @@ -37,19 +37,11 @@ Configuration Layout ------ - The core support files are located in the platform code contained in - arch/arm/plat-s3c24xx with headers in include/asm-arm/plat-s3c24xx. - This directory should be kept to items shared between the platform - code (arch/arm/plat-s3c24xx) and the arch/arm/mach-s3c24* code. + The core support files, register, kernel and paltform data are located in the + platform code contained in arch/arm/mach-s3c with headers in + arch/arm/mach-s3c/include - Each cpu has a directory with the support files for it, and the - machines that carry the device. For example S3C2410 is contained - in arch/arm/mach-s3c2410 and S3C2440 in arch/arm/mach-s3c2440 - - Register, kernel and platform data definitions are held in the - arch/arm/mach-s3c2410 directory./include/mach - -arch/arm/plat-s3c24xx: +arch/arm/mach-s3c: Files in here are either common to all the s3c24xx family, or are common to only some of them with names to indicate this @@ -134,7 +126,7 @@ Adding New Machines should keep this in mind before altering items outside of their own machine files. - Machine definitions should be kept in linux/arch/arm/mach-s3c2410, + Machine definitions should be kept in arch/arm/mach-s3c, and there are a number of examples that can be looked at. Read the kernel patch submission policies as well as the @@ -293,7 +285,7 @@ Platform Data } Note, since the code is marked as __init, it should not be - exported outside arch/arm/mach-s3c2410/, or exported to + exported outside arch/arm/mach-s3c/, or exported to modules via EXPORT_SYMBOL() and related functions. diff --git a/Documentation/arm/samsung-s3c24xx/usb-host.rst b/Documentation/arm/samsung-s3c24xx/usb-host.rst index c84268bd1884..7aaffac89e04 100644 --- a/Documentation/arm/samsung-s3c24xx/usb-host.rst +++ b/Documentation/arm/samsung-s3c24xx/usb-host.rst @@ -36,7 +36,7 @@ Board Support ------------- The driver attaches to a platform device, which will need to be - added by the board specific support file in linux/arch/arm/mach-s3c2410, + added by the board specific support file in arch/arm/mach-s3c, such as mach-bast.c or mach-smdk2410.c The platform device's platform_data field is only needed if the @@ -51,9 +51,9 @@ Board Support Platform Data ------------- - See arch/arm/mach-s3c2410/include/mach/usb-control.h for the + See include/linux/platform_data/usb-ohci-s3c2410.h for the descriptions of the platform device data. An implementation - can be found in linux/arch/arm/mach-s3c2410/usb-simtec.c . + can be found in arch/arm/mach-s3c/simtec-usb.c . The `struct s3c2410_hcd_info` contains a pair of functions that get called to enable over-current detection, and to diff --git a/Documentation/arm/samsung/gpio.rst b/Documentation/arm/samsung/gpio.rst index 5f7cadd7159e..f6e27b07c993 100644 --- a/Documentation/arm/samsung/gpio.rst +++ b/Documentation/arm/samsung/gpio.rst @@ -37,5 +37,4 @@ implementation to configure pins as necessary. The s3c_gpio_cfgpin() and s3c_gpio_setpull() provide the means for a driver or machine to change gpio configuration. -See arch/arm/plat-samsung/include/plat/gpio-cfg.h for more information -on these functions. +See arch/arm/mach-s3c/gpio-cfg.h for more information on these functions. diff --git a/Documentation/networking/device_drivers/ethernet/davicom/dm9000.rst b/Documentation/networking/device_drivers/ethernet/davicom/dm9000.rst index d5458da01083..14eb0a4d4e4e 100644 --- a/Documentation/networking/device_drivers/ethernet/davicom/dm9000.rst +++ b/Documentation/networking/device_drivers/ethernet/davicom/dm9000.rst @@ -34,7 +34,7 @@ These resources should be specified in that order, as the ordering of the two address regions is important (the driver expects these to be address and then data). -An example from arch/arm/mach-s3c2410/mach-bast.c is:: +An example from arch/arm/mach-s3c/mach-bast.c is:: static struct resource bast_dm9k_resource[] = { [0] = { -- cgit v1.2.3 From 3ebc0ef06e4a78522e9d1488dcf61b7d8fcfb792 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 11 Sep 2020 16:33:42 +0200 Subject: serial: s3c: Update path of Samsung S3C machine file Correct the path to Samsung S3C24xx machine file, mentioned in documentation. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200911143343.498-2-krzk@kernel.org --- include/linux/serial_s3c.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h index 463ed28d2b27..ca2c5393dc6b 100644 --- a/include/linux/serial_s3c.h +++ b/include/linux/serial_s3c.h @@ -254,7 +254,7 @@ * serial port * * the pointer is setup by the machine specific initialisation from the - * arch/arm/mach-s3c2410/ directory. + * arch/arm/mach-s3c/ directory. */ struct s3c2410_uartcfg { -- cgit v1.2.3 From 1c552e08b29895d31bbf82bdb549811cfde31db4 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:02 -0700 Subject: firmware: ti_sci: rm: Add support for tx_tdtype parameter for tx channel The system controller's resource manager have support for configuring the TDTYPE of TCHAN_CFG register on j721e. With this parameter the teardown completion can be controlled: TDTYPE == 0: Return without waiting for peer to complete the teardown TDTYPE == 1: Wait for peer to complete the teardown Signed-off-by: Peter Ujfalusi Reviewed-by: Tero Kristo Tested-by: Keerthy Reviewed-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- drivers/firmware/ti_sci.c | 1 + drivers/firmware/ti_sci.h | 7 +++++++ include/linux/soc/ti/ti_sci_protocol.h | 2 ++ 3 files changed, 10 insertions(+) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 896f53ec7857..65a8c2e82093 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -2362,6 +2362,7 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(const struct ti_sci_handle *handle, req->fdepth = params->fdepth; req->tx_sched_priority = params->tx_sched_priority; req->tx_burst_size = params->tx_burst_size; + req->tx_tdtype = params->tx_tdtype; ret = ti_sci_do_xfer(info, xfer); if (ret) { diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index 57cd04062994..dca19ca5fc49 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -910,6 +910,7 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size + * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype * * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located * @@ -973,6 +974,11 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { * * @tx_burst_size: UDMAP transmit channel burst size configuration to be * programmed into the tx_burst_size field of the TCHAN_TCFG register. + * + * @tx_tdtype: UDMAP transmit channel teardown type configuration to be + * programmed into the tdtype field of the TCHAN_TCFG register: + * 0 - Return immediately + * 1 - Wait for completion message from remote peer */ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { struct ti_sci_msg_hdr hdr; @@ -994,6 +1000,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { u16 fdepth; u8 tx_sched_priority; u8 tx_burst_size; + u8 tx_tdtype; } __packed; /** diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index cf27b080e148..d254d99fd45b 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -345,6 +345,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15) u16 nav_id; u16 index; u8 tx_pause_on_err; @@ -362,6 +363,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { u16 fdepth; u8 tx_sched_priority; u8 tx_burst_size; + u8 tx_tdtype; }; /** -- cgit v1.2.3 From 967a020bd3deddf9a0af73aeb4d4b46d90030937 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:03 -0700 Subject: firmware: ti_sci: Use struct ti_sci_resource_desc in get_range ops Use the ti_sci_resource_desc directly and update it's start and num members directly instead of requiring individual parameters for them. This will allow easy extension of the RM parameters without changing API. Signed-off-by: Peter Ujfalusi Signed-off-by: Santosh Shilimkar --- drivers/firmware/ti_sci.c | 32 +++++++++++++++----------------- include/linux/soc/ti/ti_sci_protocol.h | 32 ++++++++++++++++---------------- 2 files changed, 31 insertions(+), 33 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 65a8c2e82093..7a777e91ce3e 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -1703,14 +1703,14 @@ fail: * @subtype: Resource assignment subtype that is being requested * from the given device. * @s_host: Host processor ID to which the resources are allocated - * @range_start: Start index of the resource range - * @range_num: Number of resources in the range + * @desc: Pointer to ti_sci_resource_desc to be updated with the + * resource range start index and number of resources * * Return: 0 if all went fine, else return appropriate error. */ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, - u16 *range_start, u16 *range_num) + struct ti_sci_resource_desc *desc) { struct ti_sci_msg_resp_get_resource_range *resp; struct ti_sci_msg_req_get_resource_range *req; @@ -1721,7 +1721,7 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle, if (IS_ERR(handle)) return PTR_ERR(handle); - if (!handle) + if (!handle || !desc) return -EINVAL; info = handle_to_ti_sci_info(handle); @@ -1754,8 +1754,8 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle, } else if (!resp->range_start && !resp->range_num) { ret = -ENODEV; } else { - *range_start = resp->range_start; - *range_num = resp->range_num; + desc->start = resp->range_start; + desc->num = resp->range_num; }; fail: @@ -1771,18 +1771,18 @@ fail: * @dev_id: TISCI device ID. * @subtype: Resource assignment subtype that is being requested * from the given device. - * @range_start: Start index of the resource range - * @range_num: Number of resources in the range + * @desc: Pointer to ti_sci_resource_desc to be updated with the + * resource range start index and number of resources * * Return: 0 if all went fine, else return appropriate error. */ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, - u16 *range_start, u16 *range_num) + struct ti_sci_resource_desc *desc) { return ti_sci_get_resource_range(handle, dev_id, subtype, TI_SCI_IRQ_SECONDARY_HOST_INVALID, - range_start, range_num); + desc); } /** @@ -1793,18 +1793,17 @@ static int ti_sci_cmd_get_resource_range(const struct ti_sci_handle *handle, * @subtype: Resource assignment subtype that is being requested * from the given device. * @s_host: Host processor ID to which the resources are allocated - * @range_start: Start index of the resource range - * @range_num: Number of resources in the range + * @desc: Pointer to ti_sci_resource_desc to be updated with the + * resource range start index and number of resources * * Return: 0 if all went fine, else return appropriate error. */ static int ti_sci_cmd_get_resource_range_from_shost(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, - u16 *range_start, u16 *range_num) + struct ti_sci_resource_desc *desc) { - return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, - range_start, range_num); + return ti_sci_get_resource_range(handle, dev_id, subtype, s_host, desc); } /** @@ -3243,8 +3242,7 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle, for (i = 0; i < res->sets; i++) { ret = handle->ops.rm_core_ops.get_range(handle, dev_id, sub_types[i], - &res->desc[i].start, - &res->desc[i].num); + &res->desc[i]); if (ret) { dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n", dev_id, sub_types[i]); diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index d254d99fd45b..6cd537db4d33 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -195,6 +195,18 @@ struct ti_sci_clk_ops { u64 *current_freq); }; +/** + * struct ti_sci_resource_desc - Description of TI SCI resource instance range. + * @start: Start index of the resource. + * @num: Number of resources. + * @res_map: Bitmap to manage the allocation of these resources. + */ +struct ti_sci_resource_desc { + u16 start; + u16 num; + unsigned long *res_map; +}; + /** * struct ti_sci_rm_core_ops - Resource management core operations * @get_range: Get a range of resources belonging to ti sci host. @@ -209,15 +221,15 @@ struct ti_sci_clk_ops { * - dev_id: TISCI device ID. * - subtype: Resource assignment subtype that is being requested * from the given device. - * - range_start: Start index of the resource range - * - range_end: Number of resources in the range + * - desc: Pointer to ti_sci_resource_desc to be updated with the resource + * range start index and number of resources */ struct ti_sci_rm_core_ops { int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id, - u8 subtype, u16 *range_start, u16 *range_num); + u8 subtype, struct ti_sci_resource_desc *desc); int (*get_range_from_shost)(const struct ti_sci_handle *handle, u32 dev_id, u8 subtype, u8 s_host, - u16 *range_start, u16 *range_num); + struct ti_sci_resource_desc *desc); }; #define TI_SCI_RESASG_SUBTYPE_IR_OUTPUT 0 @@ -522,18 +534,6 @@ struct ti_sci_handle { #define TI_SCI_RESOURCE_NULL 0xffff -/** - * struct ti_sci_resource_desc - Description of TI SCI resource instance range. - * @start: Start index of the resource. - * @num: Number of resources. - * @res_map: Bitmap to manage the allocation of these resources. - */ -struct ti_sci_resource_desc { - u16 start; - u16 num; - unsigned long *res_map; -}; - /** * struct ti_sci_resource - Structure representing a resource assigned * to a device. -- cgit v1.2.3 From 519c5c0c558b529f835c9bb30f9a1eb2034d585c Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:03 -0700 Subject: firmware: ti_sci: rm: Add support for second resource range Sysfw added support for a second range in the resource range API to be able to describe complex allocations mainly for DMA channels. Update the ti_sci part to consider the second range as well. Signed-off-by: Peter Ujfalusi Signed-off-by: Santosh Shilimkar --- drivers/firmware/ti_sci.c | 48 ++++++++++++++++++++++------------ drivers/firmware/ti_sci.h | 8 ++++-- include/linux/soc/ti/ti_sci_protocol.h | 8 ++++-- 3 files changed, 43 insertions(+), 21 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 7a777e91ce3e..2793bb923881 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -1751,11 +1751,14 @@ static int ti_sci_get_resource_range(const struct ti_sci_handle *handle, if (!ti_sci_is_response_ack(resp)) { ret = -ENODEV; - } else if (!resp->range_start && !resp->range_num) { + } else if (!resp->range_num && !resp->range_num_sec) { + /* Neither of the two resource range is valid */ ret = -ENODEV; } else { desc->start = resp->range_start; desc->num = resp->range_num; + desc->start_sec = resp->range_start_sec; + desc->num_sec = resp->range_num_sec; }; fail: @@ -3157,12 +3160,18 @@ u16 ti_sci_get_free_resource(struct ti_sci_resource *res) raw_spin_lock_irqsave(&res->lock, flags); for (set = 0; set < res->sets; set++) { - free_bit = find_first_zero_bit(res->desc[set].res_map, - res->desc[set].num); - if (free_bit != res->desc[set].num) { - set_bit(free_bit, res->desc[set].res_map); + struct ti_sci_resource_desc *desc = &res->desc[set]; + int res_count = desc->num + desc->num_sec; + + free_bit = find_first_zero_bit(desc->res_map, res_count); + if (free_bit != res_count) { + set_bit(free_bit, desc->res_map); raw_spin_unlock_irqrestore(&res->lock, flags); - return res->desc[set].start + free_bit; + + if (desc->num && free_bit < desc->num) + return desc->start + free_bit; + else + return desc->start_sec + free_bit; } } raw_spin_unlock_irqrestore(&res->lock, flags); @@ -3183,10 +3192,14 @@ void ti_sci_release_resource(struct ti_sci_resource *res, u16 id) raw_spin_lock_irqsave(&res->lock, flags); for (set = 0; set < res->sets; set++) { - if (res->desc[set].start <= id && - (res->desc[set].num + res->desc[set].start) > id) - clear_bit(id - res->desc[set].start, - res->desc[set].res_map); + struct ti_sci_resource_desc *desc = &res->desc[set]; + + if (desc->num && desc->start <= id && + (desc->start + desc->num) > id) + clear_bit(id - desc->start, desc->res_map); + else if (desc->num_sec && desc->start_sec <= id && + (desc->start_sec + desc->num_sec) > id) + clear_bit(id - desc->start_sec, desc->res_map); } raw_spin_unlock_irqrestore(&res->lock, flags); } @@ -3203,7 +3216,7 @@ u32 ti_sci_get_num_resources(struct ti_sci_resource *res) u32 set, count = 0; for (set = 0; set < res->sets; set++) - count += res->desc[set].num; + count += res->desc[set].num + res->desc[set].num_sec; return count; } @@ -3227,7 +3240,7 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle, { struct ti_sci_resource *res; bool valid_set = false; - int i, ret; + int i, ret, res_count; res = devm_kzalloc(dev, sizeof(*res), GFP_KERNEL); if (!res) @@ -3246,18 +3259,19 @@ devm_ti_sci_get_resource_sets(const struct ti_sci_handle *handle, if (ret) { dev_dbg(dev, "dev = %d subtype %d not allocated for this host\n", dev_id, sub_types[i]); - res->desc[i].start = 0; - res->desc[i].num = 0; + memset(&res->desc[i], 0, sizeof(res->desc[i])); continue; } - dev_dbg(dev, "dev = %d, subtype = %d, start = %d, num = %d\n", + dev_dbg(dev, "dev/sub_type: %d/%d, start/num: %d/%d | %d/%d\n", dev_id, sub_types[i], res->desc[i].start, - res->desc[i].num); + res->desc[i].num, res->desc[i].start_sec, + res->desc[i].num_sec); valid_set = true; + res_count = res->desc[i].num + res->desc[i].num_sec; res->desc[i].res_map = - devm_kzalloc(dev, BITS_TO_LONGS(res->desc[i].num) * + devm_kzalloc(dev, BITS_TO_LONGS(res_count) * sizeof(*res->desc[i].res_map), GFP_KERNEL); if (!res->desc[i].res_map) return ERR_PTR(-ENOMEM); diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index dca19ca5fc49..4d980eb592c4 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -574,8 +574,10 @@ struct ti_sci_msg_req_get_resource_range { /** * struct ti_sci_msg_resp_get_resource_range - Response to resource get range. * @hdr: Generic Header - * @range_start: Start index of the resource range. - * @range_num: Number of resources in the range. + * @range_start: Start index of the first resource range. + * @range_num: Number of resources in the first range. + * @range_start_sec: Start index of the second resource range. + * @range_num_sec: Number of resources in the second range. * * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE. */ @@ -583,6 +585,8 @@ struct ti_sci_msg_resp_get_resource_range { struct ti_sci_msg_hdr hdr; u16 range_start; u16 range_num; + u16 range_start_sec; + u16 range_num_sec; } __packed; /** diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 6cd537db4d33..9699b260de59 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -197,13 +197,17 @@ struct ti_sci_clk_ops { /** * struct ti_sci_resource_desc - Description of TI SCI resource instance range. - * @start: Start index of the resource. - * @num: Number of resources. + * @start: Start index of the first resource range. + * @num: Number of resources in the first range. + * @start_sec: Start index of the second resource range. + * @num_sec: Number of resources in the second range. * @res_map: Bitmap to manage the allocation of these resources. */ struct ti_sci_resource_desc { u16 start; u16 num; + u16 start_sec; + u16 num_sec; unsigned long *res_map; }; -- cgit v1.2.3 From f5087f68e7a55fe7f8f257283ae8aecf1b8c3a76 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:04 -0700 Subject: soc: ti: ti_sci_inta_msi: Add support for second range in resource ranges Allocate MSI entries for both first and second range if they are valid Signed-off-by: Peter Ujfalusi Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/ti_sci_inta_msi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/ti/ti_sci_inta_msi.c b/drivers/soc/ti/ti_sci_inta_msi.c index 0eb9462f609e..a1d9c027022a 100644 --- a/drivers/soc/ti/ti_sci_inta_msi.c +++ b/drivers/soc/ti/ti_sci_inta_msi.c @@ -89,6 +89,18 @@ static int ti_sci_inta_msi_alloc_descs(struct device *dev, list_add_tail(&msi_desc->list, dev_to_msi_list(dev)); count++; } + for (i = 0; i < res->desc[set].num_sec; i++) { + msi_desc = alloc_msi_entry(dev, 1, NULL); + if (!msi_desc) { + ti_sci_inta_msi_free_descs(dev); + return -ENOMEM; + } + + msi_desc->inta.dev_index = res->desc[set].start_sec + i; + INIT_LIST_HEAD(&msi_desc->list); + list_add_tail(&msi_desc->list, dev_to_msi_list(dev)); + count++; + } } return count; -- cgit v1.2.3 From ce1feed58534d8489afb4900bee75dff15d950e0 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:05 -0700 Subject: firmware: ti_sci: rm: Add support for extended_ch_type for tx channel Sysfw added 'extended_ch_type' to the tx_ch_cfg_req message which should be used when BCDMA block copy channels are configured: extended_ch_type = 0 : the channel is split tx channel (tchan) extended_ch_type = 1 : the channel is block copy channel (bchan) Signed-off-by: Peter Ujfalusi Signed-off-by: Santosh Shilimkar --- drivers/firmware/ti_sci.c | 1 + drivers/firmware/ti_sci.h | 6 ++++++ include/linux/soc/ti/ti_sci_protocol.h | 5 +++++ 3 files changed, 12 insertions(+) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 2793bb923881..0dd3fbb4f964 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -2365,6 +2365,7 @@ static int ti_sci_cmd_rm_udmap_tx_ch_cfg(const struct ti_sci_handle *handle, req->tx_sched_priority = params->tx_sched_priority; req->tx_burst_size = params->tx_burst_size; req->tx_tdtype = params->tx_tdtype; + req->extended_ch_type = params->extended_ch_type; ret = ti_sci_do_xfer(info, xfer); if (ret) { diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index 4d980eb592c4..ca15d8f1f8de 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -915,6 +915,7 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype + * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type * * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located * @@ -983,6 +984,10 @@ struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg { * programmed into the tdtype field of the TCHAN_TCFG register: * 0 - Return immediately * 1 - Wait for completion message from remote peer + * + * @extended_ch_type: Valid for BCDMA. + * 0 - the channel is split tx channel (tchan) + * 1 - the channel is block copy channel (bchan) */ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { struct ti_sci_msg_hdr hdr; @@ -1005,6 +1010,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg_req { u8 tx_sched_priority; u8 tx_burst_size; u8 tx_tdtype; + u8 extended_ch_type; } __packed; /** diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 9699b260de59..6978afc00823 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -336,6 +336,9 @@ struct ti_sci_rm_psil_ops { #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3 +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0 +#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1 + /* UDMAP TX/RX channel valid_params common declarations */ #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1) @@ -362,6 +365,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13) #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15) +#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16) u16 nav_id; u16 index; u8 tx_pause_on_err; @@ -380,6 +384,7 @@ struct ti_sci_msg_rm_udmap_tx_ch_cfg { u8 tx_sched_priority; u8 tx_burst_size; u8 tx_tdtype; + u8 extended_ch_type; }; /** -- cgit v1.2.3 From 4d8ddf673a420aa25668eceeb4fbf33e2521fdf2 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:05 -0700 Subject: firmware: ti_sci: rm: Remove ring_get_config support The ring_get_cfg (0x1111 message) is not used and it is not supported by sysfw for a long time. Signed-off-by: Peter Ujfalusi Reviewed-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- drivers/firmware/ti_sci.c | 80 ---------------------------------- drivers/firmware/ti_sci.h | 44 ------------------- include/linux/soc/ti/ti_sci_protocol.h | 6 --- 3 files changed, 130 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 0dd3fbb4f964..0b801e67e672 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -2119,85 +2119,6 @@ fail: return ret; } -/** - * ti_sci_cmd_ring_get_config() - get RA ring configuration - * @handle: Pointer to TI SCI handle. - * @nav_id: Device ID of Navigator Subsystem from which the ring is - * allocated - * @index: Ring index - * @addr_lo: Returns ring's base address lo 32 bits - * @addr_hi: Returns ring's base address hi 32 bits - * @count: Returns number of ring elements - * @mode: Returns mode of the ring - * @size: Returns ring element size - * @order_id: Returns ring's bus order ID - * - * Return: 0 if all went well, else returns appropriate error value. - * - * See @ti_sci_msg_rm_ring_get_cfg_req for more info. - */ -static int ti_sci_cmd_ring_get_config(const struct ti_sci_handle *handle, - u32 nav_id, u32 index, u8 *mode, - u32 *addr_lo, u32 *addr_hi, - u32 *count, u8 *size, u8 *order_id) -{ - struct ti_sci_msg_rm_ring_get_cfg_resp *resp; - struct ti_sci_msg_rm_ring_get_cfg_req *req; - struct ti_sci_xfer *xfer; - struct ti_sci_info *info; - struct device *dev; - int ret = 0; - - if (IS_ERR_OR_NULL(handle)) - return -EINVAL; - - info = handle_to_ti_sci_info(handle); - dev = info->dev; - - xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_GET_CFG, - TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, - sizeof(*req), sizeof(*resp)); - if (IS_ERR(xfer)) { - ret = PTR_ERR(xfer); - dev_err(dev, - "RM_RA:Message get config failed(%d)\n", ret); - return ret; - } - req = (struct ti_sci_msg_rm_ring_get_cfg_req *)xfer->xfer_buf; - req->nav_id = nav_id; - req->index = index; - - ret = ti_sci_do_xfer(info, xfer); - if (ret) { - dev_err(dev, "RM_RA:Mbox get config send fail %d\n", ret); - goto fail; - } - - resp = (struct ti_sci_msg_rm_ring_get_cfg_resp *)xfer->xfer_buf; - - if (!ti_sci_is_response_ack(resp)) { - ret = -ENODEV; - } else { - if (mode) - *mode = resp->mode; - if (addr_lo) - *addr_lo = resp->addr_lo; - if (addr_hi) - *addr_hi = resp->addr_hi; - if (count) - *count = resp->count; - if (size) - *size = resp->size; - if (order_id) - *order_id = resp->order_id; - }; - -fail: - ti_sci_put_one_xfer(&info->minfo, xfer); - dev_dbg(dev, "RM_RA:get config ring %u ret:%d\n", index, ret); - return ret; -} - /** * ti_sci_cmd_rm_psil_pair() - Pair PSI-L source to destination thread * @handle: Pointer to TI SCI handle. @@ -2926,7 +2847,6 @@ static void ti_sci_setup_ops(struct ti_sci_info *info) iops->free_event_map = ti_sci_cmd_free_event_map; rops->config = ti_sci_cmd_ring_config; - rops->get_config = ti_sci_cmd_ring_get_config; psilops->pair = ti_sci_cmd_rm_psil_pair; psilops->unpair = ti_sci_cmd_rm_psil_unpair; diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index ca15d8f1f8de..1cdf918be861 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -49,7 +49,6 @@ #define TI_SCI_MSG_RM_RING_RECONFIG 0x1102 #define TI_SCI_MSG_RM_RING_RESET 0x1103 #define TI_SCI_MSG_RM_RING_CFG 0x1110 -#define TI_SCI_MSG_RM_RING_GET_CFG 0x1111 /* PSI-L requests */ #define TI_SCI_MSG_RM_PSIL_PAIR 0x1280 @@ -687,49 +686,6 @@ struct ti_sci_msg_rm_ring_cfg_req { u8 order_id; } __packed; -/** - * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration - * - * Gets the configuration of the non-real-time register fields of a ring. The - * host, or a supervisor of the host, who owns the ring must be the requesting - * host. The values of the non-real-time registers are returned in - * @ti_sci_msg_rm_ring_get_cfg_resp. - * - * @hdr: Generic Header - * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated - * @index: ring index. - */ -struct ti_sci_msg_rm_ring_get_cfg_req { - struct ti_sci_msg_hdr hdr; - u16 nav_id; - u16 index; -} __packed; - -/** - * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response - * - * Response received by host processor after RM has handled - * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's - * non-real-time register values. - * - * @hdr: Generic Header - * @addr_lo: Ring 32 LSBs of base address - * @addr_hi: Ring 16 MSBs of base address. - * @count: Ring number of elements. - * @mode: Ring mode. - * @size: encoded Ring element size - * @order_id: ing order ID. - */ -struct ti_sci_msg_rm_ring_get_cfg_resp { - struct ti_sci_msg_hdr hdr; - u32 addr_lo; - u32 addr_hi; - u32 count; - u8 mode; - u8 size; - u8 order_id; -} __packed; - /** * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination * thread diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 6978afc00823..6710d7ac7a72 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -286,8 +286,6 @@ struct ti_sci_rm_irq_ops { /** * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations * @config: configure the SoC Navigator Subsystem Ring Accelerator ring - * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring - * configuration */ struct ti_sci_rm_ringacc_ops { int (*config)(const struct ti_sci_handle *handle, @@ -295,10 +293,6 @@ struct ti_sci_rm_ringacc_ops { u32 addr_lo, u32 addr_hi, u32 count, u8 mode, u8 size, u8 order_id ); - int (*get_config)(const struct ti_sci_handle *handle, - u32 nav_id, u32 index, u8 *mode, - u32 *addr_lo, u32 *addr_hi, u32 *count, - u8 *size, u8 *order_id); }; /** -- cgit v1.2.3 From 3c2017536f3a122bf246cc87f9327e9ec138db92 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:06 -0700 Subject: firmware: ti_sci: rm: Add new ops for ring configuration The sysfw ring configuration message has been extended to include virtid and asel value for the ring. Add the ASEL_VALID to TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER as it is required for DMA rings. Instead of extending the current .config() ops - which would need same patch change in the ringacc driver - add ti_sci_msg_rm_ring_cfg struct and a new ops using it to configure the ring. This will allow easy update path in case new members are added for the ring configuration. Signed-off-by: Peter Ujfalusi Reviewed-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- drivers/firmware/ti_sci.c | 63 ++++++++++++++++++++++++++++++++++ drivers/firmware/ti_sci.h | 7 ++++ include/linux/soc/ti/ti_sci_protocol.h | 31 ++++++++++++++++- 3 files changed, 100 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 0b801e67e672..a4d2b318795c 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -2119,6 +2119,68 @@ fail: return ret; } +/** + * ti_sci_cmd_rm_ring_cfg() - Configure a NAVSS ring + * @handle: Pointer to TI SCI handle. + * @params: Pointer to ti_sci_msg_rm_ring_cfg ring config structure + * + * Return: 0 if all went well, else returns appropriate error value. + * + * See @ti_sci_msg_rm_ring_cfg and @ti_sci_msg_rm_ring_cfg_req for + * more info. + */ +static int ti_sci_cmd_rm_ring_cfg(const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_ring_cfg *params) +{ + struct ti_sci_msg_rm_ring_cfg_req *req; + struct ti_sci_msg_hdr *resp; + struct ti_sci_xfer *xfer; + struct ti_sci_info *info; + struct device *dev; + int ret = 0; + + if (IS_ERR_OR_NULL(handle)) + return -EINVAL; + + info = handle_to_ti_sci_info(handle); + dev = info->dev; + + xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_CFG, + TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, + sizeof(*req), sizeof(*resp)); + if (IS_ERR(xfer)) { + ret = PTR_ERR(xfer); + dev_err(dev, "RM_RA:Message config failed(%d)\n", ret); + return ret; + } + req = (struct ti_sci_msg_rm_ring_cfg_req *)xfer->xfer_buf; + req->valid_params = params->valid_params; + req->nav_id = params->nav_id; + req->index = params->index; + req->addr_lo = params->addr_lo; + req->addr_hi = params->addr_hi; + req->count = params->count; + req->mode = params->mode; + req->size = params->size; + req->order_id = params->order_id; + req->virtid = params->virtid; + req->asel = params->asel; + + ret = ti_sci_do_xfer(info, xfer); + if (ret) { + dev_err(dev, "RM_RA:Mbox config send fail %d\n", ret); + goto fail; + } + + resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; + ret = ti_sci_is_response_ack(resp) ? 0 : -EINVAL; + +fail: + ti_sci_put_one_xfer(&info->minfo, xfer); + dev_dbg(dev, "RM_RA:config ring %u ret:%d\n", params->index, ret); + return ret; +} + /** * ti_sci_cmd_rm_psil_pair() - Pair PSI-L source to destination thread * @handle: Pointer to TI SCI handle. @@ -2847,6 +2909,7 @@ static void ti_sci_setup_ops(struct ti_sci_info *info) iops->free_event_map = ti_sci_cmd_free_event_map; rops->config = ti_sci_cmd_ring_config; + rops->set_cfg = ti_sci_cmd_rm_ring_cfg; psilops->pair = ti_sci_cmd_rm_psil_pair; psilops->unpair = ti_sci_cmd_rm_psil_unpair; diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index 1cdf918be861..ef3a8214d002 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -659,6 +659,8 @@ struct ti_sci_msg_req_manage_irq { * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id + * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid + * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated * @index: ring index to be configured. * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's @@ -672,6 +674,9 @@ struct ti_sci_msg_req_manage_irq { * the formula (log2(size_bytes) - 2), where size_bytes cannot be * greater than 256. * @order_id: Specifies the ring's bus order ID. + * @virtid: Ring virt ID value + * @asel: Ring ASEL (address select) value to be set into the ASEL field of the + * ring's RING_BA_HI register. */ struct ti_sci_msg_rm_ring_cfg_req { struct ti_sci_msg_hdr hdr; @@ -684,6 +689,8 @@ struct ti_sci_msg_rm_ring_cfg_req { u8 mode; u8 size; u8 order_id; + u16 virtid; + u8 asel; } __packed; /** diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index 6710d7ac7a72..d1711050cd9d 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -275,17 +275,44 @@ struct ti_sci_rm_irq_ops { #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4) /* RA config.order_id parameter is valid for RM ring configure TISCI message */ #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5) +/* RA config.virtid parameter is valid for RM ring configure TISCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_VIRTID_VALID BIT(6) +/* RA config.asel parameter is valid for RM ring configure TISCI message */ +#define TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID BIT(7) #define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \ (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \ TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \ TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \ TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \ - TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID) + TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID | \ + TI_SCI_MSG_VALUE_RM_RING_ASEL_VALID) + +/** + * struct ti_sci_msg_rm_ring_cfg - Ring configuration + * + * Parameters for Navigator Subsystem ring configuration + * See @ti_sci_msg_rm_ring_cfg_req + */ +struct ti_sci_msg_rm_ring_cfg { + u32 valid_params; + u16 nav_id; + u16 index; + u32 addr_lo; + u32 addr_hi; + u32 count; + u8 mode; + u8 size; + u8 order_id; + u16 virtid; + u8 asel; +}; /** * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations * @config: configure the SoC Navigator Subsystem Ring Accelerator ring + * Deprecated + * @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring */ struct ti_sci_rm_ringacc_ops { int (*config)(const struct ti_sci_handle *handle, @@ -293,6 +320,8 @@ struct ti_sci_rm_ringacc_ops { u32 addr_lo, u32 addr_hi, u32 count, u8 mode, u8 size, u8 order_id ); + int (*set_cfg)(const struct ti_sci_handle *handle, + const struct ti_sci_msg_rm_ring_cfg *params); }; /** -- cgit v1.2.3 From bb49ca00bd8a42c327c23a21a46e86142b5734a2 Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:07 -0700 Subject: soc: ti: k3-ringacc: Use the ti_sci set_cfg callback for ring configuration Switch to the new set_cfg to configure the ring. Signed-off-by: Peter Ujfalusi Reviewed-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/k3-ringacc.c | 79 ++++++++++++++++++--------------------------- 1 file changed, 32 insertions(+), 47 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 1147dc4c1d59..9ddd77113c5a 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -365,20 +365,16 @@ EXPORT_SYMBOL_GPL(k3_ringacc_request_rings_pair); static void k3_ringacc_ring_reset_sci(struct k3_ring *ring) { + struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 }; struct k3_ringacc *ringacc = ring->parent; int ret; - ret = ringacc->tisci_ring_ops->config( - ringacc->tisci, - TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID, - ringacc->tisci_dev_id, - ring->ring_id, - 0, - 0, - ring->size, - 0, - 0, - 0); + ring_cfg.nav_id = ringacc->tisci_dev_id; + ring_cfg.index = ring->ring_id; + ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID; + ring_cfg.count = ring->size; + + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI reset ring fail (%d) ring_idx %d\n", ret, ring->ring_id); @@ -398,20 +394,16 @@ EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset); static void k3_ringacc_ring_reconfig_qmode_sci(struct k3_ring *ring, enum k3_ring_mode mode) { + struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 }; struct k3_ringacc *ringacc = ring->parent; int ret; - ret = ringacc->tisci_ring_ops->config( - ringacc->tisci, - TI_SCI_MSG_VALUE_RM_RING_MODE_VALID, - ringacc->tisci_dev_id, - ring->ring_id, - 0, - 0, - 0, - mode, - 0, - 0); + ring_cfg.nav_id = ringacc->tisci_dev_id; + ring_cfg.index = ring->ring_id; + ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_RING_MODE_VALID; + ring_cfg.mode = mode; + + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI reconf qmode fail (%d) ring_idx %d\n", ret, ring->ring_id); @@ -478,20 +470,15 @@ EXPORT_SYMBOL_GPL(k3_ringacc_ring_reset_dma); static void k3_ringacc_ring_free_sci(struct k3_ring *ring) { + struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 }; struct k3_ringacc *ringacc = ring->parent; int ret; - ret = ringacc->tisci_ring_ops->config( - ringacc->tisci, - TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER, - ringacc->tisci_dev_id, - ring->ring_id, - 0, - 0, - 0, - 0, - 0, - 0); + ring_cfg.nav_id = ringacc->tisci_dev_id; + ring_cfg.index = ring->ring_id; + ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; + + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI ring free fail (%d) ring_idx %d\n", ret, ring->ring_id); @@ -575,28 +562,26 @@ EXPORT_SYMBOL_GPL(k3_ringacc_get_ring_irq_num); static int k3_ringacc_ring_cfg_sci(struct k3_ring *ring) { + struct ti_sci_msg_rm_ring_cfg ring_cfg = { 0 }; struct k3_ringacc *ringacc = ring->parent; - u32 ring_idx; int ret; if (!ringacc->tisci) return -EINVAL; - ring_idx = ring->ring_id; - ret = ringacc->tisci_ring_ops->config( - ringacc->tisci, - TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER, - ringacc->tisci_dev_id, - ring_idx, - lower_32_bits(ring->ring_mem_dma), - upper_32_bits(ring->ring_mem_dma), - ring->size, - ring->mode, - ring->elm_size, - 0); + ring_cfg.nav_id = ringacc->tisci_dev_id; + ring_cfg.index = ring->ring_id; + ring_cfg.valid_params = TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER; + ring_cfg.addr_lo = lower_32_bits(ring->ring_mem_dma); + ring_cfg.addr_hi = upper_32_bits(ring->ring_mem_dma); + ring_cfg.count = ring->size; + ring_cfg.mode = ring->mode; + ring_cfg.size = ring->elm_size; + + ret = ringacc->tisci_ring_ops->set_cfg(ringacc->tisci, &ring_cfg); if (ret) dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n", - ret, ring_idx); + ret, ring->ring_id); return ret; } -- cgit v1.2.3 From fed7552f1e69296461fca62ebaa0bb5a06fec0df Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:07 -0700 Subject: firmware: ti_sci: rm: Remove unused config() from ti_sci_rm_ringacc_ops The ringacc driver has been converted to use the new set_cfg function to configure the ring, the old config ops can be removed. Signed-off-by: Peter Ujfalusi Reviewed-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- drivers/firmware/ti_sci.c | 72 ---------------------------------- include/linux/soc/ti/ti_sci_protocol.h | 7 ---- 2 files changed, 79 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index a4d2b318795c..235c7e7869aa 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -2048,77 +2048,6 @@ static int ti_sci_cmd_free_event_map(const struct ti_sci_handle *handle, ia_id, vint, global_event, vint_status_bit, 0); } -/** - * ti_sci_cmd_ring_config() - configure RA ring - * @handle: Pointer to TI SCI handle. - * @valid_params: Bitfield defining validity of ring configuration - * parameters - * @nav_id: Device ID of Navigator Subsystem from which the ring is - * allocated - * @index: Ring index - * @addr_lo: The ring base address lo 32 bits - * @addr_hi: The ring base address hi 32 bits - * @count: Number of ring elements - * @mode: The mode of the ring - * @size: The ring element size. - * @order_id: Specifies the ring's bus order ID - * - * Return: 0 if all went well, else returns appropriate error value. - * - * See @ti_sci_msg_rm_ring_cfg_req for more info. - */ -static int ti_sci_cmd_ring_config(const struct ti_sci_handle *handle, - u32 valid_params, u16 nav_id, u16 index, - u32 addr_lo, u32 addr_hi, u32 count, - u8 mode, u8 size, u8 order_id) -{ - struct ti_sci_msg_rm_ring_cfg_req *req; - struct ti_sci_msg_hdr *resp; - struct ti_sci_xfer *xfer; - struct ti_sci_info *info; - struct device *dev; - int ret = 0; - - if (IS_ERR_OR_NULL(handle)) - return -EINVAL; - - info = handle_to_ti_sci_info(handle); - dev = info->dev; - - xfer = ti_sci_get_one_xfer(info, TI_SCI_MSG_RM_RING_CFG, - TI_SCI_FLAG_REQ_ACK_ON_PROCESSED, - sizeof(*req), sizeof(*resp)); - if (IS_ERR(xfer)) { - ret = PTR_ERR(xfer); - dev_err(dev, "RM_RA:Message config failed(%d)\n", ret); - return ret; - } - req = (struct ti_sci_msg_rm_ring_cfg_req *)xfer->xfer_buf; - req->valid_params = valid_params; - req->nav_id = nav_id; - req->index = index; - req->addr_lo = addr_lo; - req->addr_hi = addr_hi; - req->count = count; - req->mode = mode; - req->size = size; - req->order_id = order_id; - - ret = ti_sci_do_xfer(info, xfer); - if (ret) { - dev_err(dev, "RM_RA:Mbox config send fail %d\n", ret); - goto fail; - } - - resp = (struct ti_sci_msg_hdr *)xfer->xfer_buf; - ret = ti_sci_is_response_ack(resp) ? 0 : -ENODEV; - -fail: - ti_sci_put_one_xfer(&info->minfo, xfer); - dev_dbg(dev, "RM_RA:config ring %u ret:%d\n", index, ret); - return ret; -} - /** * ti_sci_cmd_rm_ring_cfg() - Configure a NAVSS ring * @handle: Pointer to TI SCI handle. @@ -2908,7 +2837,6 @@ static void ti_sci_setup_ops(struct ti_sci_info *info) iops->free_irq = ti_sci_cmd_free_irq; iops->free_event_map = ti_sci_cmd_free_event_map; - rops->config = ti_sci_cmd_ring_config; rops->set_cfg = ti_sci_cmd_rm_ring_cfg; psilops->pair = ti_sci_cmd_rm_psil_pair; diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index d1711050cd9d..0aad7009b50e 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -310,16 +310,9 @@ struct ti_sci_msg_rm_ring_cfg { /** * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations - * @config: configure the SoC Navigator Subsystem Ring Accelerator ring - * Deprecated * @set_cfg: configure the SoC Navigator Subsystem Ring Accelerator ring */ struct ti_sci_rm_ringacc_ops { - int (*config)(const struct ti_sci_handle *handle, - u32 valid_params, u16 nav_id, u16 index, - u32 addr_lo, u32 addr_hi, u32 count, u8 mode, - u8 size, u8 order_id - ); int (*set_cfg)(const struct ti_sci_handle *handle, const struct ti_sci_msg_rm_ring_cfg *params); }; -- cgit v1.2.3 From 8c42379e40e2db4199ceeb6a6ef9fff73ff132cf Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:22 -0700 Subject: soc: ti: k3-ringacc: Use correct device for allocation in RING mode In RING mode the ringacc does not access the ring memory. In this access mode the ringacc coherency does not have meaning. If the ring is configured in RING mode, then the ringacc itself will not access to the ring memory. Only the requester (user) of the ring is going to read/write to the memory. Extend the ring configuration parameters with a device pointer to be used for DMA API when the ring is configured in RING mode. Extending the ring configuration struct will allow per ring selection of device to be used for allocation, thus allowing per ring coherency. To avoid regression, fall back to use the ringacc dev in case the alloc_dev is not provided. Signed-off-by: Peter Ujfalusi Reviewed-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/k3-ringacc.c | 18 +++++++++++++----- include/linux/soc/ti/k3-ringacc.h | 5 +++++ 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 9ddd77113c5a..7fdb688452f7 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -141,6 +141,7 @@ struct k3_ring_state { * @parent: Pointer on struct @k3_ringacc * @use_count: Use count for shared rings * @proxy_id: RA Ring Proxy Id (only if @K3_RINGACC_RING_USE_PROXY) + * @dma_dev: device to be used for DMA API (allocation, mapping) */ struct k3_ring { struct k3_ring_rt_regs __iomem *rt; @@ -160,6 +161,7 @@ struct k3_ring { struct k3_ringacc *parent; u32 use_count; int proxy_id; + struct device *dma_dev; }; struct k3_ringacc_ops { @@ -508,11 +510,12 @@ int k3_ringacc_ring_free(struct k3_ring *ring) k3_ringacc_ring_free_sci(ring); - dma_free_coherent(ringacc->dev, + dma_free_coherent(ring->dma_dev, ring->size * (4 << ring->elm_size), ring->ring_mem_virt, ring->ring_mem_dma); ring->flags = 0; ring->ops = NULL; + ring->dma_dev = NULL; if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED) { clear_bit(ring->proxy_id, ringacc->proxy_inuse); ring->proxy = NULL; @@ -633,8 +636,12 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg) switch (ring->mode) { case K3_RINGACC_RING_MODE_RING: ring->ops = &k3_ring_mode_ring_ops; + ring->dma_dev = cfg->dma_dev; + if (!ring->dma_dev) + ring->dma_dev = ringacc->dev; break; case K3_RINGACC_RING_MODE_MESSAGE: + ring->dma_dev = ringacc->dev; if (ring->proxy) ring->ops = &k3_ring_mode_proxy_ops; else @@ -646,9 +653,9 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg) goto err_free_proxy; } - ring->ring_mem_virt = dma_alloc_coherent(ringacc->dev, - ring->size * (4 << ring->elm_size), - &ring->ring_mem_dma, GFP_KERNEL); + ring->ring_mem_virt = dma_alloc_coherent(ring->dma_dev, + ring->size * (4 << ring->elm_size), + &ring->ring_mem_dma, GFP_KERNEL); if (!ring->ring_mem_virt) { dev_err(ringacc->dev, "Failed to alloc ring mem\n"); ret = -ENOMEM; @@ -669,12 +676,13 @@ int k3_ringacc_ring_cfg(struct k3_ring *ring, struct k3_ring_cfg *cfg) return 0; err_free_mem: - dma_free_coherent(ringacc->dev, + dma_free_coherent(ring->dma_dev, ring->size * (4 << ring->elm_size), ring->ring_mem_virt, ring->ring_mem_dma); err_free_ops: ring->ops = NULL; + ring->dma_dev = NULL; err_free_proxy: ring->proxy = NULL; return ret; diff --git a/include/linux/soc/ti/k3-ringacc.h b/include/linux/soc/ti/k3-ringacc.h index 5a472eca5ee4..658dc71d2901 100644 --- a/include/linux/soc/ti/k3-ringacc.h +++ b/include/linux/soc/ti/k3-ringacc.h @@ -67,6 +67,9 @@ struct k3_ring; * few times. It's usable when the same ring is used as Free Host PD ring * for different flows, for example. * Note: Locking should be done by consumer if required + * @dma_dev: Master device which is using and accessing to the ring + * memory when the mode is K3_RINGACC_RING_MODE_RING. Memory allocations + * should be done using this device. */ struct k3_ring_cfg { u32 size; @@ -74,6 +77,8 @@ struct k3_ring_cfg { enum k3_ring_mode mode; #define K3_RINGACC_RING_SHARED BIT(1) u32 flags; + + struct device *dma_dev; }; #define K3_RINGACC_RING_ID_ANY (-1) -- cgit v1.2.3 From e643bd3809d4763cb85950782508f9a1ae78a8ac Mon Sep 17 00:00:00 2001 From: Peter Ujfalusi Date: Sun, 25 Oct 2020 12:10:23 -0700 Subject: soc: ti: k3-socinfo: Add entry for AM64X SoC family It's JTAG PARTNO is 0xBB38. Signed-off-by: Peter Ujfalusi Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/k3-socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index bbbc2d2b7091..fd91129de6e5 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -40,6 +40,7 @@ static const struct k3_soc_id { { 0xBB5A, "AM65X" }, { 0xBB64, "J721E" }, { 0xBB6D, "J7200" }, + { 0xBB38, "AM64X" } }; static int -- cgit v1.2.3 From 74b01dc395364f647fe2729b6a775fd9df3f57a2 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 1 Nov 2020 07:28:44 -0800 Subject: soc: samsung: exynos5422-asv: remove unneeded semicolon A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20201101152844.2290728-1-trix@redhat.com Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos5422-asv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/samsung/exynos5422-asv.c b/drivers/soc/samsung/exynos5422-asv.c index 01bb3050d678..ca409a976e34 100644 --- a/drivers/soc/samsung/exynos5422-asv.c +++ b/drivers/soc/samsung/exynos5422-asv.c @@ -383,7 +383,7 @@ static int __asv_offset_voltage(unsigned int index) return 25000; default: return 0; - }; + } } static void exynos5422_asv_offset_voltage_setup(struct exynos_asv *asv) -- cgit v1.2.3 From 4d05446ab0a61ea3519e3c389fc7435ad0557cd4 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:27 +0000 Subject: soc: samsung: s3c-pm-check: Fix incorrectly named variable 'val' Fixes the following W=1 kernel build warning(s): drivers/soc/samsung/s3c-pm-check.c:162: warning: Function parameter or member 'val' not described in 's3c_pm_runcheck' drivers/soc/samsung/s3c-pm-check.c:162: warning: Excess function parameter 'vak' description in 's3c_pm_runcheck' Signed-off-by: Lee Jones Cc: Ben Dooks Link: https://lore.kernel.org/r/20201103152838.1290217-15-lee.jones@linaro.org Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/s3c-pm-check.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/samsung/s3c-pm-check.c b/drivers/soc/samsung/s3c-pm-check.c index ff3e099fc208..439d5c372512 100644 --- a/drivers/soc/samsung/s3c-pm-check.c +++ b/drivers/soc/samsung/s3c-pm-check.c @@ -151,7 +151,7 @@ static inline int in_region(void *ptr, int size, void *what, size_t whatsz) /** * s3c_pm_runcheck() - helper to check a resource on restore. * @res: The resource to check - * @vak: Pointer to list of CRC32 values to check. + * @val: Pointer to list of CRC32 values to check. * * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this * function runs the given memory resource checking it against the stored -- cgit v1.2.3 From b96c0546b5908268716ed9b1d39fc604413c630b Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:14 +0000 Subject: soc: bcm: brcmstb: pm: pm-arm: Provide prototype for brcmstb_pm_s3_finish() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit brcmstb_pm_s3_finish() cannot be made static because it is referenced from brcmstb_pm_s3(), so let's provide a prototype for it instead. Fixes the following W=1 kernel build warning(s): drivers/soc/bcm/brcmstb/pm/pm-arm.c:395:14: warning: no previous prototype for ‘brcmstb_pm_s3_finish’ [-Wmissing-prototypes] Cc: Florian Fainelli Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Lee Jones Signed-off-by: Florian Fainelli --- drivers/soc/bcm/brcmstb/pm/pm-arm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index b1062334e608..a673fdffe216 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -111,6 +111,8 @@ enum bsp_initiate_command { static struct brcmstb_pm_control ctrl; +noinline int brcmstb_pm_s3_finish(void); + static int (*brcmstb_pm_do_s2_sram)(void __iomem *aon_ctrl_base, void __iomem *ddr_phy_pll_status); -- cgit v1.2.3 From 27bb0e42855abe22248800531beefe08e9d69eff Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Tue, 3 Nov 2020 13:41:58 +0800 Subject: dt-bindings: memory: mediatek: Convert SMI to DT schema Convert MediaTek SMI to DT schema. Signed-off-by: Yong Wu Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201103054200.21386-2-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski --- .../memory-controllers/mediatek,smi-common.txt | 50 -------- .../memory-controllers/mediatek,smi-common.yaml | 140 +++++++++++++++++++++ .../memory-controllers/mediatek,smi-larb.txt | 50 -------- .../memory-controllers/mediatek,smi-larb.yaml | 130 +++++++++++++++++++ 4 files changed, 270 insertions(+), 100 deletions(-) delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt deleted file mode 100644 index dbafffe3f41e..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt +++ /dev/null @@ -1,50 +0,0 @@ -SMI (Smart Multimedia Interface) Common - -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt - -Mediatek SMI have two generations of HW architecture, here is the list -which generation the SoCs use: -generation 1: mt2701 and mt7623. -generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183. - -There's slight differences between the two SMI, for generation 2, the -register which control the iommu port is at each larb's register base. But -for generation 1, the register is at smi ao base(smi always on register -base). Besides that, the smi async clock should be prepared and enabled for -SMI generation 1 to transform the smi clock into emi clock domain, but that is -not needed for SMI generation 2. - -Required properties: -- compatible : must be one of : - "mediatek,mt2701-smi-common" - "mediatek,mt2712-smi-common" - "mediatek,mt6779-smi-common" - "mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common" - "mediatek,mt8167-smi-common" - "mediatek,mt8173-smi-common" - "mediatek,mt8183-smi-common" -- reg : the register and size of the SMI block. -- power-domains : a phandle to the power domain of this local arbiter. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries - for generation 2 smi HW as follows: - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting - the register. - - "smi" : It's the clock for transfer data and command. - They may be the same if both source clocks are the same. - - "async" : asynchronous clock, it help transform the smi clock into the emi - clock domain, this clock is only needed by generation 1 smi HW. - and these 2 option clocks for generation 2 smi HW: - - "gals0": the path0 clock of GALS(Global Async Local Sync). - - "gals1": the path1 clock of GALS(Global Async Local Sync). - Here is the list which has this GALS: mt6779 and mt8183. - -Example: - smi_common: smi@14022000 { - compatible = "mediatek,mt8173-smi-common"; - reg = <0 0x14022000 0 0x1000>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; - clocks = <&mmsys CLK_MM_SMI_COMMON>, - <&mmsys CLK_MM_SMI_COMMON>; - clock-names = "apb", "smi"; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml new file mode 100644 index 000000000000..56c78317f9b7 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SMI (Smart Multimedia Interface) Common + +maintainers: + - Yong Wu + +description: | + The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml + + MediaTek SMI have two generations of HW architecture, here is the list + which generation the SoCs use: + generation 1: mt2701 and mt7623. + generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183. + + There's slight differences between the two SMI, for generation 2, the + register which control the iommu port is at each larb's register base. But + for generation 1, the register is at smi ao base(smi always on register + base). Besides that, the smi async clock should be prepared and enabled for + SMI generation 1 to transform the smi clock into emi clock domain, but that is + not needed for SMI generation 2. + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-smi-common + - mediatek,mt2712-smi-common + - mediatek,mt6779-smi-common + - mediatek,mt8167-smi-common + - mediatek,mt8173-smi-common + - mediatek,mt8183-smi-common + + - description: for mt7623 + items: + - const: mediatek,mt7623-smi-common + - const: mediatek,mt2701-smi-common + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + description: | + apb and smi are mandatory. the async is only for generation 1 smi HW. + gals(global async local sync) also is optional, see below. + minItems: 2 + maxItems: 4 + items: + - description: apb is Advanced Peripheral Bus clock, It's the clock for + setting the register. + - description: smi is the clock for transfer data and command. + - description: async is asynchronous clock, it help transform the smi + clock into the emi clock domain. + - description: gals0 is the path0 clock of gals. + - description: gals1 is the path1 clock of gals. + + clock-names: + minItems: 2 + maxItems: 4 + +required: + - compatible + - reg + - power-domains + - clocks + - clock-names + +allOf: + - if: # only for gen1 HW + properties: + compatible: + contains: + enum: + - mediatek,mt2701-smi-common + then: + properties: + clock: + items: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: apb + - const: smi + - const: async + + - if: # for gen2 HW that have gals + properties: + compatible: + enum: + - mediatek,mt6779-smi-common + - mediatek,mt8183-smi-common + + then: + properties: + clock: + items: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: apb + - const: smi + - const: gals0 + - const: gals1 + + else: # for gen2 HW that don't have gals + properties: + clock: + items: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: apb + - const: smi + +additionalProperties: false + +examples: + - |+ + #include + #include + + smi_common: smi@14022000 { + compatible = "mediatek,mt8173-smi-common"; + reg = <0x14022000 0x1000>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_COMMON>; + clock-names = "apb", "smi"; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt deleted file mode 100644 index 0c5de12b5496..000000000000 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt +++ /dev/null @@ -1,50 +0,0 @@ -SMI (Smart Multimedia Interface) Local Arbiter - -The hardware block diagram please check bindings/iommu/mediatek,iommu.txt - -Required properties: -- compatible : must be one of : - "mediatek,mt2701-smi-larb" - "mediatek,mt2712-smi-larb" - "mediatek,mt6779-smi-larb" - "mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb" - "mediatek,mt8167-smi-larb" - "mediatek,mt8173-smi-larb" - "mediatek,mt8183-smi-larb" -- reg : the register and size of this local arbiter. -- mediatek,smi : a phandle to the smi_common node. -- power-domains : a phandle to the power domain of this local arbiter. -- clocks : Must contain an entry for each entry in clock-names. -- clock-names: must contain 2 entries, as follows: - - "apb" : Advanced Peripheral Bus clock, It's the clock for setting - the register. - - "smi" : It's the clock for transfer data and command. - and this optional clock name: - - "gals": the clock for GALS(Global Async Local Sync). - Here is the list which has this GALS: mt8183. - -Required property for mt2701, mt2712, mt6779, mt7623 and mt8167: -- mediatek,larb-id :the hardware id of this larb. - -Example: - larb1: larb@16010000 { - compatible = "mediatek,mt8173-smi-larb"; - reg = <0 0x16010000 0 0x1000>; - mediatek,smi = <&smi_common>; - power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; - clocks = <&vdecsys CLK_VDEC_CKEN>, - <&vdecsys CLK_VDEC_LARB_CKEN>; - clock-names = "apb", "smi"; - }; - -Example for mt2701: - larb0: larb@14010000 { - compatible = "mediatek,mt2701-smi-larb"; - reg = <0 0x14010000 0 0x1000>; - mediatek,smi = <&smi_common>; - mediatek,larb-id = <0>; - clocks = <&mmsys CLK_MM_SMI_LARB0>, - <&mmsys CLK_MM_SMI_LARB0>; - clock-names = "apb", "smi"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml new file mode 100644 index 000000000000..06b623b34f48 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (c) 2020 MediaTek Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-larb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SMI (Smart Multimedia Interface) Local Arbiter + +maintainers: + - Yong Wu + +description: | + The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml + +properties: + compatible: + oneOf: + - enum: + - mediatek,mt2701-smi-larb + - mediatek,mt2712-smi-larb + - mediatek,mt6779-smi-larb + - mediatek,mt8167-smi-larb + - mediatek,mt8173-smi-larb + - mediatek,mt8183-smi-larb + + - description: for mt7623 + items: + - const: mediatek,mt7623-smi-larb + - const: mediatek,mt2701-smi-larb + + reg: + maxItems: 1 + + clocks: + description: | + apb and smi are mandatory. gals(global async local sync) is optional. + minItems: 2 + maxItems: 3 + items: + - description: apb is Advanced Peripheral Bus clock, It's the clock for + setting the register. + - description: smi is the clock for transfer data and command. + - description: the clock for gals. + + clock-names: + minItems: 2 + maxItems: 3 + + power-domains: + maxItems: 1 + + mediatek,smi: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: a phandle to the smi_common node. + + mediatek,larb-id: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 31 + description: the hardware id of this larb. It's only required when this + hardward id is not consecutive from its M4U point of view. + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +allOf: + - if: # HW has gals + properties: + compatible: + enum: + - mediatek,mt8183-smi-larb + + then: + properties: + clock: + items: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: apb + - const: smi + - const: gals + + else: + properties: + clock: + items: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: apb + - const: smi + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-smi-larb + - mediatek,mt2712-smi-larb + - mediatek,mt6779-smi-larb + - mediatek,mt8167-smi-larb + + then: + required: + - mediatek,larb-id + +additionalProperties: false + +examples: + - |+ + #include + #include + + larb1: larb@16010000 { + compatible = "mediatek,mt8173-smi-larb"; + reg = <0x16010000 0x1000>; + mediatek,smi = <&smi_common>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys CLK_VDEC_CKEN>, + <&vdecsys CLK_VDEC_LARB_CKEN>; + clock-names = "apb", "smi"; + }; -- cgit v1.2.3 From 31fc9f87fede778965e8ac5f902ae9106304f449 Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Tue, 3 Nov 2020 13:41:59 +0800 Subject: dt-bindings: memory: mediatek: Add mt8192 support Add mt8192 smi support in the bindings. Signed-off-by: Yong Wu Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201103054200.21386-3-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/mediatek,smi-common.yaml | 4 +++- .../devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index 56c78317f9b7..a08a32340987 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -16,7 +16,7 @@ description: | MediaTek SMI have two generations of HW architecture, here is the list which generation the SoCs use: generation 1: mt2701 and mt7623. - generation 2: mt2712, mt6779, mt8167, mt8173 and mt8183. + generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192. There's slight differences between the two SMI, for generation 2, the register which control the iommu port is at each larb's register base. But @@ -35,6 +35,7 @@ properties: - mediatek,mt8167-smi-common - mediatek,mt8173-smi-common - mediatek,mt8183-smi-common + - mediatek,mt8192-smi-common - description: for mt7623 items: @@ -98,6 +99,7 @@ allOf: enum: - mediatek,mt6779-smi-common - mediatek,mt8183-smi-common + - mediatek,mt8192-smi-common then: properties: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 06b623b34f48..7ed7839ff0a7 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt8167-smi-larb - mediatek,mt8173-smi-larb - mediatek,mt8183-smi-larb + - mediatek,mt8192-smi-larb - description: for mt7623 items: @@ -107,6 +108,7 @@ allOf: - mediatek,mt2712-smi-larb - mediatek,mt6779-smi-larb - mediatek,mt8167-smi-larb + - mediatek,mt8192-smi-larb then: required: -- cgit v1.2.3 From 02c02ddce4279adf0c4ddc4ab6d113084f36c6ac Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Tue, 3 Nov 2020 13:42:00 +0800 Subject: memory: mtk-smi: Add mt8192 support Add mt8192 SMI support. Signed-off-by: Yong Wu Link: https://lore.kernel.org/r/20201103054200.21386-4-yong.wu@mediatek.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/mtk-smi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index 691e4c344cf8..ac350f8d1e20 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -268,6 +268,10 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { /* IPU0 | IPU1 | CCU */ }; +static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { + .config_port = mtk_smi_larb_config_port_gen2_general, +}; + static const struct of_device_id mtk_smi_larb_of_ids[] = { { .compatible = "mediatek,mt8167-smi-larb", @@ -293,6 +297,10 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = { .compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183 }, + { + .compatible = "mediatek,mt8192-smi-larb", + .data = &mtk_smi_larb_mt8192 + }, {} }; @@ -432,6 +440,13 @@ static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { F_MMU1_LARB(7), }; +static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { + .gen = MTK_SMI_GEN2, + .has_gals = true, + .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | + F_MMU1_LARB(6), +}; + static const struct of_device_id mtk_smi_common_of_ids[] = { { .compatible = "mediatek,mt8173-smi-common", @@ -457,6 +472,10 @@ static const struct of_device_id mtk_smi_common_of_ids[] = { .compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183, }, + { + .compatible = "mediatek,mt8192-smi-common", + .data = &mtk_smi_common_mt8192, + }, {} }; -- cgit v1.2.3 From 21d3cdd0391bb01b348a47ec117eff3b9615d3a9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:40 +0300 Subject: dt-bindings: memory: tegra20: emc: Correct registers range in example There is superfluous zero in the registers base address and registers size should be twice bigger. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-5-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index add95367640b..567cffd37f3f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -21,7 +21,7 @@ Example: #address-cells = < 1 >; #size-cells = < 0 >; compatible = "nvidia,tegra20-emc"; - reg = <0x7000f4000 0x200>; + reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; } -- cgit v1.2.3 From e51a59f079c546b8b5c31604ad98e86b06ec93e9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:41 +0300 Subject: dt-bindings: memory: tegra20: emc: Document nvidia, memory-controller property Tegra20 External Memory Controller talks to DRAM chips and it needs to be reprogrammed when memory frequency changes. Tegra Memory Controller sits behind EMC and these controllers are tightly coupled. This patch adds the new phandle property which allows to properly express connection of EMC and MC hardware in a device-tree, it also put the Tegra20 EMC binding on par with Tegra30+ EMC bindings, which is handy to have. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-6-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 567cffd37f3f..1b0d4417aad8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -12,6 +12,7 @@ Properties: irrespective of ram-code configuration. - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. +- nvidia,memory-controller : Phandle of the Memory Controller node. Child device nodes describe the memory settings for different configurations and clock rates. @@ -24,6 +25,7 @@ Example: reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; + nvidia,memory-controller = <&mc>; } -- cgit v1.2.3 From 3ee81e021f2bd44b70312692b719995d398a84ee Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:42 +0300 Subject: dt-bindings: memory: tegra20: mc: Document new interconnect property Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-7-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt index e55328237df4..739b7c6f2e26 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.txt @@ -16,6 +16,8 @@ Required properties: IOMMU specifier needed to encode an address. GART supports only a single address space that is shared by all devices, therefore no additional information needed for the address encoding. +- #interconnect-cells : Should be 1. This cell represents memory client. + The assignments may be found in header file . Example: mc: memory-controller@7000f000 { @@ -27,6 +29,7 @@ Example: interrupts = ; #reset-cells = <1>; #iommu-cells = <0>; + #interconnect-cells = <1>; }; video-codec@6001a000 { -- cgit v1.2.3 From 5e768b1fe46e6644cdbbbfa8c879c6cccb5639ba Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:43 +0300 Subject: dt-bindings: memory: tegra20: emc: Document new interconnect property External Memory Controller is interconnected with memory controller and with external memory. Document new interconnect property which turns EMC into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-8-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 1b0d4417aad8..82bc5b2ae7e5 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -13,6 +13,7 @@ Properties: - interrupts : Should contain EMC General interrupt. - clocks : Should contain EMC clock. - nvidia,memory-controller : Phandle of the Memory Controller node. +- #interconnect-cells : Should be 0. Child device nodes describe the memory settings for different configurations and clock rates. @@ -21,6 +22,7 @@ Example: memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; + #interconnect-cells = <0>; compatible = "nvidia,tegra20-emc"; reg = <0x7000f400 0x400>; interrupts = <0 78 0x04>; -- cgit v1.2.3 From 95e638e8b0b4bd0d51262bb7d01693039fc5ae48 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:44 +0300 Subject: dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator The SoC core voltage can't be changed without taking into account the clock rate of External Memory Controller. Document OPP table that will be used for dynamic voltage frequency scaling, taking into account EMC voltage requirement. Document optional core voltage regulator, which is optional because some boards may have a fixed core regulator and still frequency scaling may be desired to have. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-9-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra20-emc.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 82bc5b2ae7e5..67ac8d1297da 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -14,11 +14,25 @@ Properties: - clocks : Should contain EMC clock. - nvidia,memory-controller : Phandle of the Memory Controller node. - #interconnect-cells : Should be 0. +- operating-points-v2: See ../bindings/opp/opp.txt for details. + +Optional properties: +- core-supply: Phandle of voltage regulator of the SoC "core" power domain. Child device nodes describe the memory settings for different configurations and clock rates. Example: + opp_table: opp-table { + compatible = "operating-points-v2"; + + opp@36000000 { + opp-microvolt = <950000 950000 1300000>; + opp-hz = /bits/ 64 <36000000>; + }; + ... + }; + memory-controller@7000f400 { #address-cells = < 1 >; #size-cells = < 0 >; @@ -28,6 +42,8 @@ Example: interrupts = <0 78 0x04>; clocks = <&tegra_car TEGRA20_CLK_EMC>; nvidia,memory-controller = <&mc>; + core-supply = <&core_vdd_reg>; + operating-points-v2 = <&opp_table>; } -- cgit v1.2.3 From ed7f6f2eaae850ee836bee05feb1df722c13efad Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:45 +0300 Subject: dt-bindings: memory: tegra30: mc: Document new interconnect property Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-10-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml index 84fd57bcf0dc..5436e6d420bc 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml @@ -57,6 +57,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -120,6 +123,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -135,6 +139,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-1 { nvidia,ram-code = <1>; -- cgit v1.2.3 From 6ec85c032aee0cde82b2c63a3e521132c97c4660 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:46 +0300 Subject: dt-bindings: memory: tegra30: emc: Document new interconnect property External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-11-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 112bae2fcbbd..c243986db420 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -31,6 +31,9 @@ properties: interrupts: maxItems: 1 + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -214,6 +217,7 @@ required: - interrupts - clocks - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -227,6 +231,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-1 { nvidia,ram-code = <1>; -- cgit v1.2.3 From 48126d7884ab56c2352ae328d5fd42c7d2d7b125 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:47 +0300 Subject: dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-12-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index c243986db420..0a2e2c0d0fdd 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -39,6 +39,15 @@ properties: description: Phandle of the Memory Controller node. + core-supply: + description: + Phandle of voltage regulator of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -218,6 +227,7 @@ required: - clocks - nvidia,memory-controller - "#interconnect-cells" + - operating-points-v2 additionalProperties: false @@ -230,6 +240,8 @@ examples: clocks = <&tegra_car 57>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; #interconnect-cells = <0>; -- cgit v1.2.3 From cac2a3552c9ef3ee2ff9ec72794e1ab0a1f64012 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:48 +0300 Subject: dt-bindings: memory: tegra124: mc: Document new interconnect property Memory controller is interconnected with memory clients and with the External Memory Controller. Document new interconnect property which turns memory controller into interconnect provider. Signed-off-by: Dmitry Osipenko Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-13-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml | 1 + .../devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 278549f9e051..8ae3dae42d6e 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -345,6 +345,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; }; external-memory-controller@7001b000 { diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 84d0339505b1..7b18b4d11e0a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -40,6 +40,9 @@ properties: "#iommu-cells": const: 1 + "#interconnect-cells": + const: 1 + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -104,6 +107,7 @@ required: - clock-names - "#reset-cells" - "#iommu-cells" + - "#interconnect-cells" additionalProperties: false @@ -119,6 +123,7 @@ examples: #iommu-cells = <1>; #reset-cells = <1>; + #interconnect-cells = <1>; emc-timings-3 { nvidia,ram-code = <3>; -- cgit v1.2.3 From cf3b2deb459df1d1f3cdbd4d24b35e9f3506d92f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:49 +0300 Subject: dt-bindings: memory: tegra124: emc: Document new interconnect property External memory controller is interconnected with memory controller and with external memory. Document new interconnect property which turns External Memory Controller into interconnect provider. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-14-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 8ae3dae42d6e..ac00832ceac1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -29,6 +29,9 @@ properties: items: - const: emc + "#interconnect-cells": + const: 0 + nvidia,memory-controller: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -327,6 +330,7 @@ required: - clocks - clock-names - nvidia,memory-controller + - "#interconnect-cells" additionalProperties: false @@ -356,6 +360,8 @@ examples: nvidia,memory-controller = <&mc>; + #interconnect-cells = <0>; + emc-timings-0 { nvidia,ram-code = <3>; -- cgit v1.2.3 From 881f68ed9d4e2d9f6e4247f2f01d9c457921e6c6 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:50 +0300 Subject: dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator Document new OPP table and voltage regulator properties which are needed for supporting dynamic voltage-frequency scaling of the memory controller. Some boards may have a fixed core voltage regulator, hence it's optional because frequency scaling still may be desired. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-15-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/nvidia,tegra124-emc.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index ac00832ceac1..09bde65e1955 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -37,6 +37,15 @@ properties: description: phandle of the memory controller node + core-supply: + description: + Phandle of voltage regulator of the SoC "core" power domain. + + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + patternProperties: "^emc-timings-[0-9]+$": type: object @@ -331,6 +340,7 @@ required: - clock-names - nvidia,memory-controller - "#interconnect-cells" + - operating-points-v2 additionalProperties: false @@ -359,6 +369,8 @@ examples: clock-names = "emc"; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; #interconnect-cells = <0>; -- cgit v1.2.3 From 254a42ac93900f92307a280daf4ccbd118c72255 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:51 +0300 Subject: dt-bindings: tegra30-actmon: Document OPP and interconnect properties Document EMC DFS OPP table and interconnect paths that will be used for scaling of system's memory bandwidth based on memory utilization statistics. Previously ACTMON was supposed to drive EMC clock rate directly, but now it should do it using interconnect framework in order to support shared voltage scaling in addition to the frequency scaling. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-16-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../bindings/arm/tegra/nvidia,tegra30-actmon.txt | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt index ea670a5d7ee3..897eedfa2bc8 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-actmon.txt @@ -18,8 +18,30 @@ clock-names. See ../../clock/clock-bindings.txt for details. ../../reset/reset.txt for details. - reset-names: Must include the following entries: - actmon +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- interconnects: Should contain entries for memory clients sitting on + MC->EMC memory interconnect path. +- interconnect-names: Should include name of the interconnect path for each + interconnect entry. Consult TRM documentation for + information about available memory clients, see MEMORY + CONTROLLER section. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: bitfield indicating SoC speedo ID mask +- opp-peak-kBps: peak bandwidth of the memory channel Example: + dfs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp@12750000 { + opp-hz = /bits/ 64 <12750000>; + opp-supported-hw = <0x000F>; + opp-peak-kBps = <51000>; + }; + ... + }; + actmon@6000c800 { compatible = "nvidia,tegra124-actmon"; reg = <0x0 0x6000c800 0x0 0x400>; @@ -29,4 +51,7 @@ Example: clock-names = "actmon", "emc"; resets = <&tegra_car 119>; reset-names = "actmon"; + operating-points-v2 = <&dfs_opp_table>; + interconnects = <&mc TEGRA124_MC_MPCORER &emc>; + interconnect-names = "cpu"; }; -- cgit v1.2.3 From c553bb54a486eab2b0d3671db4b985c8d1ba51e9 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:48:52 +0300 Subject: dt-bindings: host1x: Document new interconnect properties Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-17-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../display/tegra/nvidia,tegra20-host1x.txt | 68 ++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt index ac63ae4a3861..34d993338453 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt @@ -20,6 +20,10 @@ Required properties: - reset-names: Must include the following entries: - host1x +Each host1x client module having to perform DMA through the Memory Controller +should have the interconnect endpoints set to the Memory Client and External +Memory respectively. + The host1x top-level node defines a number of children, each representing one of the following host1x client modules: @@ -36,6 +40,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - mpe + Optional properties: + - interconnects: Must contain entry for the MPE memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - vi: video input Required properties: @@ -113,6 +123,12 @@ of the following host1x client modules: Required properties: - remote-endpoint: phandle to vi port 'endpoint' node. + Optional properties: + - interconnects: Must contain entry for the VI memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - epp: encoder pre-processor Required properties: @@ -126,6 +142,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - epp + Optional properties: + - interconnects: Must contain entry for the EPP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - isp: image signal processor Required properties: @@ -139,6 +161,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - isp + Optional properties: + - interconnects: Must contain entry for the ISP memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr2d: 2D graphics engine Required properties: @@ -152,6 +180,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - 2d + Optional properties: + - interconnects: Must contain entry for the GR2D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - gr3d: 3D graphics engine Required properties: @@ -170,6 +204,12 @@ of the following host1x client modules: - 3d - 3d2 (Only required on SoCs with two 3D clocks) + Optional properties: + - interconnects: Must contain entry for the GR3D memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + - dc: display controller Required properties: @@ -197,6 +237,10 @@ of the following host1x client modules: - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection - nvidia,edid: supplies a binary EDID blob - nvidia,panel: phandle of a display panel + - interconnects: Must contain entry for the DC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. - hdmi: High Definition Multimedia Interface @@ -345,6 +389,12 @@ of the following host1x client modules: - reset-names: Must include the following entries: - vic + Optional properties: + - interconnects: Must contain entry for the VIC memory clients. + - interconnect-names: Must include name of the interconnect path for each + interconnect entry. Consult TRM documentation for information about + available memory clients, see MEMORY CONTROLLER section. + Example: / { @@ -498,6 +548,15 @@ Example: resets = <&tegra_car 27>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, + <&mc TEGRA20_MC_DISPLAY0B &emc>, + <&mc TEGRA20_MC_DISPLAY0C &emc>, + <&mc TEGRA20_MC_DISPLAYHC &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; @@ -513,6 +572,15 @@ Example: resets = <&tegra_car 26>; reset-names = "dc"; + interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, + <&mc TEGRA20_MC_DISPLAY0BB &emc>, + <&mc TEGRA20_MC_DISPLAY0CB &emc>, + <&mc TEGRA20_MC_DISPLAYHCB &emc>; + interconnect-names = "wina", + "winb", + "winc", + "cursor"; + rgb { status = "disabled"; }; -- cgit v1.2.3 From 9294996f0be40e9da818ed891c82397ab63c00d0 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Mon, 26 Oct 2020 17:49:21 +0100 Subject: firmware: tegra: fix strncpy()/strncat() confusion The way that bpmp_populate_debugfs_inband() uses strncpy() and strncat() makes no sense since the size argument for the first is insufficient to contain the trailing '/' and the second passes the length of the input rather than the output, which triggers a warning: In function 'strncat', inlined from 'bpmp_populate_debugfs_inband' at ../drivers/firmware/tegra/bpmp-debugfs.c:422:4: include/linux/string.h:289:30: warning: '__builtin_strncat' specified bound depends on the length of the source argument [-Wstringop-overflow=] 289 | #define __underlying_strncat __builtin_strncat | ^ include/linux/string.h:367:10: note: in expansion of macro '__underlying_strncat' 367 | return __underlying_strncat(p, q, count); | ^~~~~~~~~~~~~~~~~~~~ drivers/firmware/tegra/bpmp-debugfs.c: In function 'bpmp_populate_debugfs_inband': include/linux/string.h:288:29: note: length computed here 288 | #define __underlying_strlen __builtin_strlen | ^ include/linux/string.h:321:10: note: in expansion of macro '__underlying_strlen' 321 | return __underlying_strlen(p); Simplify this to use an snprintf() instead. Fixes: 5e37b9c137ee ("firmware: tegra: Add support for in-band debug") Signed-off-by: Arnd Bergmann Acked-by: Jon Hunter Signed-off-by: Thierry Reding --- drivers/firmware/tegra/bpmp-debugfs.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/firmware/tegra/bpmp-debugfs.c b/drivers/firmware/tegra/bpmp-debugfs.c index c1bbba9ee93a..440d99c63638 100644 --- a/drivers/firmware/tegra/bpmp-debugfs.c +++ b/drivers/firmware/tegra/bpmp-debugfs.c @@ -412,16 +412,12 @@ static int bpmp_populate_debugfs_inband(struct tegra_bpmp *bpmp, goto out; } - len = strlen(ppath) + strlen(name) + 1; + len = snprintf(pathbuf, pathlen, "%s%s/", ppath, name); if (len >= pathlen) { err = -EINVAL; goto out; } - strncpy(pathbuf, ppath, pathlen); - strncat(pathbuf, name, strlen(name)); - strcat(pathbuf, "/"); - err = bpmp_populate_debugfs_inband(bpmp, dentry, pathbuf); if (err < 0) -- cgit v1.2.3 From ce034072f9a125b913d4869d614e414784334b8a Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:26 +0000 Subject: soc: tegra: fuse: speedo-tegra124: Remove some set but unused variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following W=1 kernel build warning(s): drivers/soc/tegra/fuse/speedo-tegra124.c: In function ‘tegra124_init_speedo_data’: drivers/soc/tegra/fuse/speedo-tegra124.c:105:38: warning: variable ‘soc_iddq_value’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra124.c:105:22: warning: variable ‘gpu_iddq_value’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra124.c:105:6: warning: variable ‘cpu_iddq_value’ set but not used [-Wunused-but-set-variable] Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Lee Jones [treding@nvidia.com: remove unnecessary reads altogether] Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/speedo-tegra124.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/drivers/soc/tegra/fuse/speedo-tegra124.c b/drivers/soc/tegra/fuse/speedo-tegra124.c index bdbf76bb184f..5b1ee28e4272 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra124.c +++ b/drivers/soc/tegra/fuse/speedo-tegra124.c @@ -101,8 +101,7 @@ static void __init rev_sku_to_speedo_ids(struct tegra_sku_info *sku_info, void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info) { - int i, threshold, cpu_speedo_0_value, soc_speedo_0_value; - int cpu_iddq_value, gpu_iddq_value, soc_iddq_value; + int i, threshold, soc_speedo_0_value; BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != THRESHOLD_INDEX_COUNT); @@ -111,25 +110,17 @@ void __init tegra124_init_speedo_data(struct tegra_sku_info *sku_info) BUILD_BUG_ON(ARRAY_SIZE(soc_process_speedos) != THRESHOLD_INDEX_COUNT); - cpu_speedo_0_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0); - - /* GPU Speedo is stored in CPU_SPEEDO_2 */ - sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2); - - soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0); - - cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ); - soc_iddq_value = tegra_fuse_read_early(FUSE_SOC_IDDQ); - gpu_iddq_value = tegra_fuse_read_early(FUSE_GPU_IDDQ); - - sku_info->cpu_speedo_value = cpu_speedo_0_value; - + sku_info->cpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_0); if (sku_info->cpu_speedo_value == 0) { pr_warn("Tegra Warning: Speedo value not fused.\n"); WARN_ON(1); return; } + /* GPU Speedo is stored in CPU_SPEEDO_2 */ + sku_info->gpu_speedo_value = tegra_fuse_read_early(FUSE_CPU_SPEEDO_2); + soc_speedo_0_value = tegra_fuse_read_early(FUSE_SOC_SPEEDO_0); + rev_sku_to_speedo_ids(sku_info, &threshold); sku_info->cpu_iddq_value = tegra_fuse_read_early(FUSE_CPU_IDDQ); -- cgit v1.2.3 From 6c37cb9fa67650c51b3a70c53202be31730d7e29 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:37 +0000 Subject: soc: tegra: fuse: speedo-tegra210: Remove a group of set but unused variables MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following W=1 kernel build warning(s): drivers/soc/tegra/fuse/speedo-tegra210.c: In function ‘tegra210_init_speedo_data’: drivers/soc/tegra/fuse/speedo-tegra210.c:105:56: warning: variable ‘soc_iddq’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra210.c:105:46: warning: variable ‘gpu_iddq’ set but not used [-Wunused-but-set-variable] drivers/soc/tegra/fuse/speedo-tegra210.c:105:36: warning: variable ‘cpu_iddq’ set but not used [-Wunused-but-set-variable] Cc: Thierry Reding Cc: Jonathan Hunter Cc: linux-tegra@vger.kernel.org Signed-off-by: Lee Jones [treding@nvidia.com: remove unnecessary reads altogether] Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/speedo-tegra210.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c index 70d3f6e1aa33..7394a8d694cb 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra210.c +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c @@ -102,7 +102,7 @@ static int get_process_id(int value, const u32 *speedos, unsigned int num) void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info) { - int cpu_speedo[3], soc_speedo[3], cpu_iddq, gpu_iddq, soc_iddq; + int cpu_speedo[3], soc_speedo[3]; unsigned int index; u8 speedo_revision; @@ -122,10 +122,6 @@ void __init tegra210_init_speedo_data(struct tegra_sku_info *sku_info) soc_speedo[1] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_1); soc_speedo[2] = tegra_fuse_read_early(FUSE_SOC_SPEEDO_2); - cpu_iddq = tegra_fuse_read_early(FUSE_CPU_IDDQ) * 4; - soc_iddq = tegra_fuse_read_early(FUSE_SOC_IDDQ) * 4; - gpu_iddq = tegra_fuse_read_early(FUSE_GPU_IDDQ) * 5; - /* * Determine CPU, GPU and SoC speedo values depending on speedo fusing * revision. Note that GPU speedo value is fused in CPU_SPEEDO_2. -- cgit v1.2.3 From 54f8ebda0dde59ae313bc6c87d307b0225d38fc5 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:15 +0000 Subject: soc: qcom: qcom_aoss: Remove set but unused variable 'tlen' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/qcom_aoss.c: In function ‘qmp_send’: drivers/soc/qcom/qcom_aoss.c:228:9: warning: variable ‘tlen’ set but not used [-Wunused-but-set-variable] Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-3-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_aoss.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index ed2c687c16b3..83589756cb1f 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -225,7 +225,6 @@ static bool qmp_message_empty(struct qmp *qmp) static int qmp_send(struct qmp *qmp, const void *data, size_t len) { long time_left; - size_t tlen; int ret; if (WARN_ON(len + sizeof(u32) > qmp->size)) @@ -242,7 +241,7 @@ static int qmp_send(struct qmp *qmp, const void *data, size_t len) writel(len, qmp->msgram + qmp->offset); /* Read back len to confirm data written in message RAM */ - tlen = readl(qmp->msgram + qmp->offset); + readl(qmp->msgram + qmp->offset); qmp_kick(qmp); time_left = wait_event_interruptible_timeout(qmp->event, -- cgit v1.2.3 From 96ec310d5d946372292f9abfc019a45012606c11 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:16 +0000 Subject: soc: qcom: qcom_aoss: Add missing description for 'cooling_devs' Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/qcom_aoss.c:86: warning: Function parameter or member 'cooling_devs' not described in 'qmp' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-4-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_aoss.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 83589756cb1f..b5840d624bc6 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -65,6 +65,7 @@ struct qmp_cooling_device { * @tx_lock: provides synchronization between multiple callers of qmp_send() * @qdss_clk: QDSS clock hw struct * @pd_data: genpd data + * @cooling_devs: thermal cooling devices */ struct qmp { void __iomem *msgram; -- cgit v1.2.3 From 08ad7061e4d4e7eace8a2993c8df53b0bd4fdf19 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:25 +0000 Subject: soc: qcom: qcom-geni-se: Fix misnamed function parameter 'rx_rfr' Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/qcom-geni-se.c:85: warning: Cannot understand * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core drivers/soc/qcom/qcom-geni-se.c:246: warning: Function parameter or member 'rx_rfr' not described in 'geni_se_init' drivers/soc/qcom/qcom-geni-se.c:246: warning: Excess function parameter 'rx_rfr_wm' description in 'geni_se_init' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-13-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom-geni-se.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 7649b2057b9a..9da904d137dc 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -82,10 +82,11 @@ #define NUM_AHB_CLKS 2 /** - * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core + * struct geni_wrapper - Data structure to represent the QUP Wrapper Core * @dev: Device pointer of the QUP wrapper core * @base: Base address of this instance of QUP wrapper core * @ahb_clks: Handle to the primary & secondary AHB clocks + * @to_core: Core ICC path */ struct geni_wrapper { struct device *dev; @@ -237,7 +238,7 @@ static void geni_se_irq_clear(struct geni_se *se) * geni_se_init() - Initialize the GENI serial engine * @se: Pointer to the concerned serial engine. * @rx_wm: Receive watermark, in units of FIFO words. - * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words. + * @rx_rfr: Ready-for-receive watermark, in units of FIFO words. * * This function is used to initialize the GENI serial engine, configure * receive watermark and ready-for-receive watermarks. -- cgit v1.2.3 From fc3699c69857abbdb690d7a34eba0181e93c903e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:29 +0000 Subject: soc: qcom: smem: Fix formatting and missing documentation issues Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/smem.c:135: warning: Function parameter or member 'toc' not described in 'smem_header' drivers/soc/qcom/smem.c:275: warning: Function parameter or member 'socinfo' not described in 'qcom_smem' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-17-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 28c19bcb2f20..7251827bac88 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -122,7 +122,7 @@ struct smem_global_entry { * @free_offset: index of the first unallocated byte in smem * @available: number of bytes available for allocation * @reserved: reserved field, must be 0 - * toc: array of references to items + * @toc: array of references to items */ struct smem_header { struct smem_proc_comm proc_comm[4]; @@ -255,6 +255,7 @@ struct smem_region { * processor/host * @cacheline: list of cacheline sizes for each host * @item_count: max accepted item number + * @socinfo: platform device pointer * @num_regions: number of @regions * @regions: list of the memory regions defining the shared memory */ -- cgit v1.2.3 From fac312df31ab39aeb1400eac7d3bb13a740c48fd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:30 +0000 Subject: soc: qcom: smsm: Fix some kernel-doc formatting and naming problems Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/smsm.c:140: warning: Function parameter or member 'mask' not described in 'smsm_update_bits' drivers/soc/qcom/smsm.c:140: warning: Excess function parameter 'offset' description in 'smsm_update_bits' drivers/soc/qcom/smsm.c:257: warning: bad line: drivers/soc/qcom/smsm.c:260: warning: bad line: Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-18-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smsm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/qcom/smsm.c b/drivers/soc/qcom/smsm.c index 70c3c90b997c..1d3d5e3ec2b0 100644 --- a/drivers/soc/qcom/smsm.c +++ b/drivers/soc/qcom/smsm.c @@ -130,7 +130,7 @@ struct smsm_host { /** * smsm_update_bits() - change bit in outgoing entry and inform subscribers * @data: smsm context pointer - * @offset: bit in the entry + * @mask: value mask * @value: new value * * Used to set and clear the bits in the outgoing/local entry and inform @@ -254,10 +254,8 @@ static void smsm_mask_irq(struct irq_data *irqd) * smsm_unmask_irq() - subscribe to cascades of IRQs of a certain status bit * @irqd: IRQ handle to be unmasked * - * This subscribes the local CPU to interrupts upon changes to the defined * status bit. The bit is also marked for cascading. - */ static void smsm_unmask_irq(struct irq_data *irqd) { -- cgit v1.2.3 From f5c805b1f188fe1498011a57a4ee2db4238f53c8 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:31 +0000 Subject: soc: qcom: wcnss_ctrl: Demote non-conformant struct header and fix function headers Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/wcnss_ctrl.c:81: warning: Function parameter or member 'major' not described in 'wcnss_version_resp' drivers/soc/qcom/wcnss_ctrl.c:81: warning: Function parameter or member 'minor' not described in 'wcnss_version_resp' drivers/soc/qcom/wcnss_ctrl.c:81: warning: Function parameter or member 'version' not described in 'wcnss_version_resp' drivers/soc/qcom/wcnss_ctrl.c:81: warning: Function parameter or member 'revision' not described in 'wcnss_version_resp' drivers/soc/qcom/wcnss_ctrl.c:122: warning: Function parameter or member 'rpdev' not described in 'wcnss_ctrl_smd_callback' drivers/soc/qcom/wcnss_ctrl.c:122: warning: Function parameter or member 'priv' not described in 'wcnss_ctrl_smd_callback' drivers/soc/qcom/wcnss_ctrl.c:122: warning: Function parameter or member 'addr' not described in 'wcnss_ctrl_smd_callback' drivers/soc/qcom/wcnss_ctrl.c:122: warning: Excess function parameter 'channel' description in 'wcnss_ctrl_smd_callback' drivers/soc/qcom/wcnss_ctrl.c:272: warning: Function parameter or member 'priv' not described in 'qcom_wcnss_open_channel' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-19-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/wcnss_ctrl.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/wcnss_ctrl.c b/drivers/soc/qcom/wcnss_ctrl.c index e5c68051fb17..32bed249f90e 100644 --- a/drivers/soc/qcom/wcnss_ctrl.c +++ b/drivers/soc/qcom/wcnss_ctrl.c @@ -68,9 +68,8 @@ struct wcnss_msg_hdr { u32 len; } __packed; -/** +/* * struct wcnss_version_resp - version request response - * @hdr: common packet wcnss_msg_hdr header */ struct wcnss_version_resp { struct wcnss_msg_hdr hdr; @@ -108,9 +107,11 @@ struct wcnss_download_nv_resp { /** * wcnss_ctrl_smd_callback() - handler from SMD responses - * @channel: smd channel handle + * @rpdev: remote processor message device pointer * @data: pointer to the incoming data packet * @count: size of the incoming data packet + * @priv: unused + * @addr: unused * * Handles any incoming packets from the remote WCNSS_CTRL service. */ @@ -267,6 +268,7 @@ free_req: * @wcnss: wcnss handle, retrieved from drvdata * @name: SMD channel name * @cb: callback to handle incoming data on the channel + * @priv: private data for use in the call-back */ struct rpmsg_endpoint *qcom_wcnss_open_channel(void *wcnss, const char *name, rpmsg_rx_cb_t cb, void *priv) { -- cgit v1.2.3 From 1f8933c25f9e9f33b147b596ccd9f446a00e9862 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:32 +0000 Subject: soc: qcom: smp2p: Remove unused struct attribute provide another Fixes the following W=1 kernel build warning: drivers/soc/qcom/smp2p.c:149: warning: Function parameter or member 'out' not described in 'qcom_smp2p' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-20-lee.jones@linaro.org [bjorn: Dropped hunk that fixed the same warning in smp2p_smem_item] Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smp2p.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/smp2p.c b/drivers/soc/qcom/smp2p.c index a9709aae54ab..2df488333be9 100644 --- a/drivers/soc/qcom/smp2p.c +++ b/drivers/soc/qcom/smp2p.c @@ -112,6 +112,7 @@ struct smp2p_entry { * struct qcom_smp2p - device driver context * @dev: device driver handle * @in: pointer to the inbound smem item + * @out: pointer to the outbound smem item * @smem_items: ids of the two smem items * @valid_entries: already scanned inbound entries * @local_pid: processor id of the inbound edge -- cgit v1.2.3 From 171c03171a4cdf23a07a6d3a63eb446b714fe45f Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:33 +0000 Subject: soc: qcom: llcc-qcom: Fix expected kernel-doc formatting Kernel-doc expects struct documentation to start with 'struct '. Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/llcc-qcom.c:77: warning: cannot understand function prototype: 'struct llcc_slice_config ' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-21-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/llcc-qcom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 40e7df1e1cbb..96c20e673436 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -51,7 +51,7 @@ #define BANK_OFFSET_STRIDE 0x80000 /** - * llcc_slice_config - Data associated with the llcc slice + * struct llcc_slice_config - Data associated with the llcc slice * @usecase_id: Unique id for the client's use case * @slice_id: llcc slice id for each client * @max_cap: The maximum capacity of the cache slice provided in KB -- cgit v1.2.3 From 5d16af6a921f5a4e7038671be5478cba4b7cfe81 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:34 +0000 Subject: soc: qcom: rpmhpd: Provide some missing struct member descriptions Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/rpmhpd.c:52: warning: Function parameter or member 'parent' not described in 'rpmhpd' drivers/soc/qcom/rpmhpd.c:52: warning: Function parameter or member 'corner' not described in 'rpmhpd' drivers/soc/qcom/rpmhpd.c:52: warning: Function parameter or member 'active_corner' not described in 'rpmhpd' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-22-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmhpd.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index e72426221a69..6bab57aa6d48 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -24,9 +24,12 @@ * struct rpmhpd - top level RPMh power domain resource data structure * @dev: rpmh power domain controller device * @pd: generic_pm_domain corrresponding to the power domain + * @parent: generic_pm_domain corrresponding to the parent's power domain * @peer: A peer power domain in case Active only Voting is * supported * @active_only: True if it represents an Active only peer + * @corner: current corner + * @active_corner: current active corner * @level: An array of level (vlvl) to corner (hlvl) mappings * derived from cmd-db * @level_count: Number of levels supported by the power domain. max -- cgit v1.2.3 From 9401f8dcf1ee4d18bc23a29f26c76910ab852757 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:35 +0000 Subject: soc: qcom: kryo-l2-accessors: Fix misnaming of 'val' Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/kryo-l2-accessors.c:25: warning: Function parameter or member 'val' not described in 'kryo_l2_set_indirect_reg' drivers/soc/qcom/kryo-l2-accessors.c:25: warning: Excess function parameter 'value' description in 'kryo_l2_set_indirect_reg' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-23-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/kryo-l2-accessors.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/kryo-l2-accessors.c b/drivers/soc/qcom/kryo-l2-accessors.c index c20cb92077c0..7886af4fd726 100644 --- a/drivers/soc/qcom/kryo-l2-accessors.c +++ b/drivers/soc/qcom/kryo-l2-accessors.c @@ -16,7 +16,7 @@ static DEFINE_RAW_SPINLOCK(l2_access_lock); /** * kryo_l2_set_indirect_reg() - write value to an L2 register * @reg: Address of L2 register. - * @value: Value to be written to register. + * @val: Value to be written to register. * * Use architecturally required barriers for ordering between system register * accesses, and system registers with respect to device memory -- cgit v1.2.3 From 1894b78ee6ff2d50e4afa4b80244d060c3773bfc Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:28 +0000 Subject: soc: qcom: rpmh: Fix possible doc-rot in rpmh_write()'s header Fixes the following W=1 kernel build warning(s): drivers/soc/qcom/rpmh.c:266: warning: Function parameter or member 'dev' not described in 'rpmh_write' drivers/soc/qcom/rpmh.c:266: warning: Excess function parameter 'rc' description in 'rpmh_write' Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20201103152838.1290217-16-lee.jones@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmh.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c index b61e183ede69..ad1f062620ff 100644 --- a/drivers/soc/qcom/rpmh.c +++ b/drivers/soc/qcom/rpmh.c @@ -254,7 +254,7 @@ EXPORT_SYMBOL(rpmh_write_async); /** * rpmh_write: Write a set of RPMH commands and block until response * - * @rc: The RPMH handle got from rpmh_get_client + * @dev: The device making the request * @state: Active/sleep set * @cmd: The payload data * @n: The number of elements in @cmd -- cgit v1.2.3 From a6a3a24c129d229a0eb26b329ab617e2a04245dd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:18 +0000 Subject: soc: rockchip: io-domain: Remove incorrect and incomplete comment header Fixes the following W=1 kernel build warning(s): drivers/soc/rockchip/io-domain.c:57: warning: Cannot understand * @supplies: voltage settings matching the register bits. Signed-off-by: Lee Jones Cc: Heiko Stuebner Cc: Liam Girdwood Cc: Mark Brown Cc: "Rafael J. Wysocki" Cc: Doug Anderson Cc: linux-rockchip@lists.infradead.org Link: https://lore.kernel.org/r/20201103152838.1290217-6-lee.jones@linaro.org Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/io-domain.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c index eece97f97ef8..d13d2d497720 100644 --- a/drivers/soc/rockchip/io-domain.c +++ b/drivers/soc/rockchip/io-domain.c @@ -53,9 +53,6 @@ struct rockchip_iodomain; -/** - * @supplies: voltage settings matching the register bits. - */ struct rockchip_iodomain_soc_data { int grf_offset; const char *supply_names[MAX_SUPPLIES]; -- cgit v1.2.3 From 124f035310adc781d91cdf0b7c6e4fb3c7e43e23 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 10 Nov 2020 20:37:49 +0100 Subject: clk: samsung: allow building the clkout driver as module The Exynos clock output driver can be built as module (it does not have to be part of core init process) for better customization. Adding a KConfig entry allows also compile testing for build coverage. Signed-off-by: Krzysztof Kozlowski Acked-by: Chanwoo Choi Acked-by: Sylwester Nawrocki Link: https://lore.kernel.org/r/20201110193749.261367-1-krzk@kernel.org --- drivers/clk/samsung/Kconfig | 10 ++++++++++ drivers/clk/samsung/Makefile | 2 +- drivers/clk/samsung/clk-exynos-clkout.c | 1 + 3 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 57d4b3f20417..7e9c186e57ef 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -19,6 +19,16 @@ config EXYNOS_AUDSS_CLK_CON on some Exynos SoC variants. Choose M or Y here if you want to use audio devices such as I2S, PCM, etc. +config EXYNOS_CLKOUT + tristate "Samsung Exynos clock output driver" + depends on COMMON_CLK_SAMSUNG + default y if ARCH_EXYNOS + help + Support for the clock output (XCLKOUT) present on some of Exynos SoC + variants. Usually the XCLKOUT is used to monitor the status of the + certains clocks from SoC, but it could also be tied to other devices + as an input clock. + # For S3C24XX platforms, select following symbols: config S3C2410_COMMON_CLK bool "Samsung S3C2410 clock controller support" if COMPILE_TEST diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 1a4e6b787978..6891b087acff 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -15,7 +15,7 @@ obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5-subcmu.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_EXYNOS_AUDSS_CLK_CON) += clk-exynos-audss.o -obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o +obj-$(CONFIG_EXYNOS_CLKOUT) += clk-exynos-clkout.o obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index f5f8a956b316..9ec2f40cc400 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -72,6 +72,7 @@ static const struct of_device_id exynos_clkout_ids[] = { .data = &exynos_clkout_exynos5, }, { } }; +MODULE_DEVICE_TABLE(of, exynos_clkout_ids); /* * Device will be instantiated as child of PMU device without its own -- cgit v1.2.3 From c1995e5afaf6abf3922b5395ad1f4096951e3276 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: soc: ti: omap-prm: Do not check rstst bit on deassert if already deasserted If a rstctrl reset bit is already deasserted, we can just bail out early not wait for rstst to clear. Otherwise we can have deassert fail for already deasserted resets. Fixes: c5117a78dd88 ("soc: ti: omap-prm: poll for reset complete during de-assert") Signed-off-by: Tony Lindgren --- drivers/soc/ti/omap_prm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 980b04c38fd9..4d41dc3cdce1 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -484,6 +484,10 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); int ret = 0; + /* Nothing to do if the reset is already deasserted */ + if (!omap_reset_status(rcdev, id)) + return 0; + has_rstst = reset->prm->data->rstst || (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); -- cgit v1.2.3 From 6bbdb46c4b1bd57839c9c0a110bd81b0be0a4046 Mon Sep 17 00:00:00 2001 From: Qinglang Miao Date: Tue, 10 Nov 2020 15:42:21 +0800 Subject: firmware: arm_scmi: Fix missing destroy_workqueue() destroy_workqueue is required before the return from scmi_notification_init in case devm_kcalloc fails to allocate registered_protocols. Fix this by simply moving registered_protocols allocation before alloc_workqueue. Link: https://lore.kernel.org/r/20201110074221.41235-1-miaoqinglang@huawei.com Fixes: bd31b249692e ("firmware: arm_scmi: Add notification dispatch and delivery") Suggested-by: Cristian Marussi Reviewed-by: Cristian Marussi Signed-off-by: Qinglang Miao Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/notify.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/firmware/arm_scmi/notify.c b/drivers/firmware/arm_scmi/notify.c index ce336899d636..66196b293b6c 100644 --- a/drivers/firmware/arm_scmi/notify.c +++ b/drivers/firmware/arm_scmi/notify.c @@ -1474,17 +1474,17 @@ int scmi_notification_init(struct scmi_handle *handle) ni->gid = gid; ni->handle = handle; + ni->registered_protocols = devm_kcalloc(handle->dev, SCMI_MAX_PROTO, + sizeof(char *), GFP_KERNEL); + if (!ni->registered_protocols) + goto err; + ni->notify_wq = alloc_workqueue(dev_name(handle->dev), WQ_UNBOUND | WQ_FREEZABLE | WQ_SYSFS, 0); if (!ni->notify_wq) goto err; - ni->registered_protocols = devm_kcalloc(handle->dev, SCMI_MAX_PROTO, - sizeof(char *), GFP_KERNEL); - if (!ni->registered_protocols) - goto err; - mutex_init(&ni->pending_mtx); hash_init(ni->pending_events_handlers); -- cgit v1.2.3 From 0b7a8e5a61a15014a450c0c36719a6ab175f17eb Mon Sep 17 00:00:00 2001 From: Mirela Rabulea Date: Thu, 12 Nov 2020 05:05:49 +0200 Subject: firmware: imx: scu-pd: Add power domains for imx-jpeg The power domains are for imx8qxp/imx8qm JPEG encoder & decoder. Each has 4 slots and a wrapper. Signed-off-by: Mirela Rabulea Acked-by: Daniel Baluta Signed-off-by: Shawn Guo --- drivers/firmware/imx/scu-pd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index 946eea292b52..a614d8dd868e 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -180,6 +180,12 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "cm41-pid", IMX_SC_R_M4_1_PID0, 5, true, 0}, { "cm41-mu-a1", IMX_SC_R_M4_1_MU_1A, 1, false, 0}, { "cm41-lpuart", IMX_SC_R_M4_1_UART, 1, false, 0}, + + /* IMAGE SS */ + { "img-jpegdec-mp", IMX_SC_R_MJPEG_DEC_MP, 1, false, 0 }, + { "img-jpegdec-s0", IMX_SC_R_MJPEG_DEC_S0, 4, true, 0 }, + { "img-jpegenc-mp", IMX_SC_R_MJPEG_ENC_MP, 1, false, 0 }, + { "img-jpegenc-s0", IMX_SC_R_MJPEG_ENC_S0, 4, true, 0 }, }; static const struct imx_sc_pd_soc imx8qxp_scu_pd = { -- cgit v1.2.3 From 4d3f4f0379b637b489a3eda9524a78d515390f06 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Wed, 11 Nov 2020 13:11:16 +0200 Subject: firmware: imx: Introduce imx_dsp_setup_channels Create a separate function that sets up DSP mailbox channels so that imx_dsp_probe function will be easier to read. Signed-off-by: Daniel Baluta Reviewed-by: Paul Olaru Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-dsp.c | 41 ++++++++++++++++++++++++++--------------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/firmware/imx/imx-dsp.c b/drivers/firmware/imx/imx-dsp.c index 4265e9dbed84..a3a018c87b52 100644 --- a/drivers/firmware/imx/imx-dsp.c +++ b/drivers/firmware/imx/imx-dsp.c @@ -60,22 +60,15 @@ static void imx_dsp_handle_rx(struct mbox_client *c, void *msg) } } -static int imx_dsp_probe(struct platform_device *pdev) +static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc) { - struct device *dev = &pdev->dev; - struct imx_dsp_ipc *dsp_ipc; + struct device *dev = dsp_ipc->dev; struct imx_dsp_chan *dsp_chan; struct mbox_client *cl; char *chan_name; int ret; int i, j; - device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent); - - dsp_ipc = devm_kzalloc(dev, sizeof(*dsp_ipc), GFP_KERNEL); - if (!dsp_ipc) - return -ENOMEM; - for (i = 0; i < DSP_MU_CHAN_NUM; i++) { if (i < 2) chan_name = kasprintf(GFP_KERNEL, "txdb%d", i); @@ -108,12 +101,6 @@ static int imx_dsp_probe(struct platform_device *pdev) kfree(chan_name); } - dsp_ipc->dev = dev; - - dev_set_drvdata(dev, dsp_ipc); - - dev_info(dev, "NXP i.MX DSP IPC initialized\n"); - return 0; out: kfree(chan_name); @@ -125,6 +112,30 @@ out: return ret; } +static int imx_dsp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct imx_dsp_ipc *dsp_ipc; + int ret; + + device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent); + + dsp_ipc = devm_kzalloc(dev, sizeof(*dsp_ipc), GFP_KERNEL); + if (!dsp_ipc) + return -ENOMEM; + + dsp_ipc->dev = dev; + dev_set_drvdata(dev, dsp_ipc); + + ret = imx_dsp_setup_channels(dsp_ipc); + if (ret < 0) + return ret; + + dev_info(dev, "NXP i.MX DSP IPC initialized\n"); + + return 0; +} + static int imx_dsp_remove(struct platform_device *pdev) { struct imx_dsp_chan *dsp_chan; -- cgit v1.2.3 From 046326989a1845db321d3b3db637e1336383b047 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Wed, 11 Nov 2020 13:11:17 +0200 Subject: firmware: imx: Save channel name for further use We want to request / free channels on demand later in order to save power. For this for each channel we save the name and use it to reference the channel later. Signed-off-by: Daniel Baluta Reviewed-by: Paul Olaru Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-dsp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/imx/imx-dsp.c b/drivers/firmware/imx/imx-dsp.c index a3a018c87b52..b6e95d6d34c0 100644 --- a/drivers/firmware/imx/imx-dsp.c +++ b/drivers/firmware/imx/imx-dsp.c @@ -79,6 +79,7 @@ static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc) return -ENOMEM; dsp_chan = &dsp_ipc->chans[i]; + dsp_chan->name = chan_name; cl = &dsp_chan->cl; cl->dev = dev; cl->tx_block = false; @@ -97,16 +98,14 @@ static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc) } dev_dbg(dev, "request mbox chan %s\n", chan_name); - /* chan_name is not used anymore by framework */ - kfree(chan_name); } return 0; out: - kfree(chan_name); for (j = 0; j < i; j++) { dsp_chan = &dsp_ipc->chans[j]; mbox_free_channel(dsp_chan->ch); + kfree(dsp_chan->name); } return ret; @@ -147,6 +146,7 @@ static int imx_dsp_remove(struct platform_device *pdev) for (i = 0; i < DSP_MU_CHAN_NUM; i++) { dsp_chan = &dsp_ipc->chans[i]; mbox_free_channel(dsp_chan->ch); + kfree(dsp_chan->name); } return 0; -- cgit v1.2.3 From 23d89aa0c2192f2d4582198b381d8805492c7925 Mon Sep 17 00:00:00 2001 From: Daniel Baluta Date: Wed, 11 Nov 2020 13:11:18 +0200 Subject: firmware: imx-dsp: Export functions to request/free channels In order to save power, we only need to request a channel when the communication with the DSP active. For this we export the following functions: - imx_dsp_request_channel, gets a channel with a given index - imx_dsp_free_channel, frees a channel with a given index Notice that we still request channels at probe to support devices that do not have PM callbacks implemented. More explanations about why requesting a channel has an effect on power savings: - requesting an mailbox channel will call mailbox's startup function. - startup function calls pm_runtime_get_sync which increments device usage count and will keep the device active. Specifically, mailbox clock will be always ON when a mailbox channel is requested. Signed-off-by: Daniel Baluta Reviewed-by: Paul Olaru Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-dsp.c | 25 +++++++++++++++++++++++++ include/linux/firmware/imx/dsp.h | 10 ++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/firmware/imx/imx-dsp.c b/drivers/firmware/imx/imx-dsp.c index b6e95d6d34c0..a6c06d7476c3 100644 --- a/drivers/firmware/imx/imx-dsp.c +++ b/drivers/firmware/imx/imx-dsp.c @@ -60,6 +60,31 @@ static void imx_dsp_handle_rx(struct mbox_client *c, void *msg) } } +struct mbox_chan *imx_dsp_request_channel(struct imx_dsp_ipc *dsp_ipc, int idx) +{ + struct imx_dsp_chan *dsp_chan; + + if (idx >= DSP_MU_CHAN_NUM) + return ERR_PTR(-EINVAL); + + dsp_chan = &dsp_ipc->chans[idx]; + dsp_chan->ch = mbox_request_channel_byname(&dsp_chan->cl, dsp_chan->name); + return dsp_chan->ch; +} +EXPORT_SYMBOL(imx_dsp_request_channel); + +void imx_dsp_free_channel(struct imx_dsp_ipc *dsp_ipc, int idx) +{ + struct imx_dsp_chan *dsp_chan; + + if (idx >= DSP_MU_CHAN_NUM) + return; + + dsp_chan = &dsp_ipc->chans[idx]; + mbox_free_channel(dsp_chan->ch); +} +EXPORT_SYMBOL(imx_dsp_free_channel); + static int imx_dsp_setup_channels(struct imx_dsp_ipc *dsp_ipc) { struct device *dev = dsp_ipc->dev; diff --git a/include/linux/firmware/imx/dsp.h b/include/linux/firmware/imx/dsp.h index 7562099c9e46..4f7895a3b73c 100644 --- a/include/linux/firmware/imx/dsp.h +++ b/include/linux/firmware/imx/dsp.h @@ -55,6 +55,9 @@ static inline void *imx_dsp_get_data(struct imx_dsp_ipc *ipc) int imx_dsp_ring_doorbell(struct imx_dsp_ipc *dsp, unsigned int chan_idx); +struct mbox_chan *imx_dsp_request_channel(struct imx_dsp_ipc *ipc, int idx); +void imx_dsp_free_channel(struct imx_dsp_ipc *ipc, int idx); + #else static inline int imx_dsp_ring_doorbell(struct imx_dsp_ipc *ipc, @@ -63,5 +66,12 @@ static inline int imx_dsp_ring_doorbell(struct imx_dsp_ipc *ipc, return -ENOTSUPP; } +struct mbox_chan *imx_dsp_request_channel(struct imx_dsp_ipc *ipc, int idx) +{ + return ERR_PTR(-EOPNOTSUPP); +} + +void imx_dsp_free_channel(struct imx_dsp_ipc *ipc, int idx) { } + #endif #endif /* _IMX_DSP_IPC_H */ -- cgit v1.2.3 From 4097c9a64d1009d97dcee772bd8b15381bc7507d Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: bus: ti-sysc: Assert reset only after disabling clocks The rstctrl reset must be asserted after gating the module clock as described in the TRM at least for IVA. Otherwise the rstctrl reset done with module clock enabled can hang the system. Note that this issue is has been only seen with related IVA changes that we do not currently have merged. So probably no need to apply this patch as a fix. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 16132e6e91f8..2b99fd5a4740 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1222,10 +1222,10 @@ static int __maybe_unused sysc_runtime_suspend(struct device *dev) ddata->enabled = false; err_allow_idle: - reset_control_assert(ddata->rsts); - sysc_clkdm_allow_idle(ddata); + reset_control_assert(ddata->rsts); + return error; } @@ -1945,6 +1945,7 @@ static int sysc_reset(struct sysc *ddata) */ static int sysc_init_module(struct sysc *ddata) { + bool rstctrl_deasserted = false; int error = 0; error = sysc_clockdomain_init(ddata); @@ -1969,6 +1970,7 @@ static int sysc_init_module(struct sysc *ddata) error = reset_control_deassert(ddata->rsts); if (error) goto err_main_clocks; + rstctrl_deasserted = true; } ddata->revision = sysc_read_revision(ddata); @@ -1978,13 +1980,13 @@ static int sysc_init_module(struct sysc *ddata) if (ddata->legacy_mode) { error = sysc_legacy_init(ddata); if (error) - goto err_reset; + goto err_main_clocks; } if (!ddata->legacy_mode) { error = sysc_enable_module(ddata->dev); if (error) - goto err_reset; + goto err_main_clocks; } error = sysc_reset(ddata); @@ -1994,10 +1996,6 @@ static int sysc_init_module(struct sysc *ddata) if (error && !ddata->legacy_mode) sysc_disable_module(ddata->dev); -err_reset: - if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) - reset_control_assert(ddata->rsts); - err_main_clocks: if (error) sysc_disable_main_clocks(ddata); @@ -2008,6 +2006,10 @@ err_opt_clocks: sysc_clkdm_allow_idle(ddata); } + if (error && rstctrl_deasserted && + !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) + reset_control_assert(ddata->rsts); + return error; } @@ -2975,9 +2977,6 @@ static int sysc_probe(struct platform_device *pdev) } /* Balance use counts as PM runtime should have enabled these all */ - if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) - reset_control_assert(ddata->rsts); - if (!(ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE | SYSC_QUIRK_NO_IDLE_ON_INIT))) { sysc_disable_main_clocks(ddata); @@ -2985,6 +2984,9 @@ static int sysc_probe(struct platform_device *pdev) sysc_clkdm_allow_idle(ddata); } + if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) + reset_control_assert(ddata->rsts); + sysc_show_registers(ddata); ddata->dev->type = &sysc_device_type; -- cgit v1.2.3 From 9261c5b2f51996e7d4e10089f73ea472ae9e996f Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Check for inited flag If we have no hwmods configured and omap_hwmod_init() is not called, we don't want to call omap_hwmod_setup_all() as it will fail with checks for configured MPU at least. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/omap_hwmod.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 15b29a179c8a..2310cd56e99b 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -627,6 +627,9 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh) { struct clk_hw_omap *clk; + if (!oh) + return NULL; + if (oh->clkdm) { return oh->clkdm; } else if (oh->_clk) { @@ -3677,6 +3680,9 @@ static void __init omap_hwmod_setup_earlycon_flags(void) */ static int __init omap_hwmod_setup_all(void) { + if (!inited) + return 0; + _ensure_mpu_hwmod_is_setup(NULL); omap_hwmod_for_each(_init, NULL); -- cgit v1.2.3 From ae5f70f707889dfd056905d9ea69e3f72dace213 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: ARM: OMAP2+: Probe PRCM first to probe l4_wkup with simple-pm-bus In preparation for probing the interconnects with simple-pm-bus to make use of genpd, we need to probe the always-on PRCM first for the clocks needed by l4_wkup instance. Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pdata-quirks.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 2a4fe3e68b82..6c925056b800 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -580,6 +580,8 @@ static void pdata_quirks_check(struct pdata_init *quirks) void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) { + struct device_node *np; + /* * We still need this for omap2420 and omap3 PM to work, others are * using drivers/misc/sram.c already. @@ -591,6 +593,15 @@ void __init pdata_quirks_init(const struct of_device_id *omap_dt_match_table) if (of_machine_is_compatible("ti,omap3")) omap3_mcbsp_init(); pdata_quirks_check(auxdata_quirks); + + /* Populate always-on PRCM in l4_wkup to probe l4_wkup */ + np = of_find_node_by_name(NULL, "prcm"); + if (!np) + np = of_find_node_by_name(NULL, "prm"); + if (np) + of_platform_populate(np, omap_dt_match_table, + omap_auxdata_lookup, NULL); + of_platform_populate(NULL, omap_dt_match_table, omap_auxdata_lookup, NULL); pdata_quirks_check(pdata_quirks); -- cgit v1.2.3 From 2928135c93f873b260ba1a88023f0bbe0f67e315 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: bus: ti-sysc: Support modules without control registers Some modules like MPU have a powerdomain and functional clock but not necessarily any control registers. Let's allow configuring interconnect target modules with no control registers. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 2b99fd5a4740..88a5d22091f3 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -853,8 +853,12 @@ static int sysc_ioremap(struct sysc *ddata) */ static int sysc_map_and_check_registers(struct sysc *ddata) { + struct device_node *np = ddata->dev->of_node; int error; + if (!of_get_property(np, "reg", NULL)) + return 0; + error = sysc_parse_and_check_child_range(ddata); if (error) return error; @@ -2911,6 +2915,9 @@ static int sysc_probe(struct platform_device *pdev) if (!ddata) return -ENOMEM; + ddata->offsets[SYSC_REVISION] = -ENODEV; + ddata->offsets[SYSC_SYSCONFIG] = -ENODEV; + ddata->offsets[SYSC_SYSSTATUS] = -ENODEV; ddata->dev = &pdev->dev; platform_set_drvdata(pdev, ddata); -- cgit v1.2.3 From cfeeea60af2f01c13b94d57a9bb1291e7bc181da Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: bus: ti-sysc: Implement GPMC debug quirk to drop platform data We need to enable no-reset-on-init quirk for GPMC if the config option for CONFIG_OMAP_GPMC_DEBUG is set. Otherwise the GPMC driver code is unable to show the bootloader configured timings. Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 10 ++++++++++ include/linux/platform_data/ti-sysc.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 88a5d22091f3..691cc39bfc5c 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1383,6 +1383,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK_CLKDM_NOAUTO), SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, SYSC_QUIRK_CLKDM_NOAUTO), + SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff, + SYSC_QUIRK_GPMC_DEBUG), SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff, SYSC_QUIRK_OPT_CLKS_NEEDED), SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, @@ -1818,6 +1820,14 @@ static void sysc_init_module_quirks(struct sysc *ddata) return; } +#ifdef CONFIG_OMAP_GPMC_DEBUG + if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) { + ddata->cfg.quirks |= SYSC_QUIRK_NO_RESET_ON_INIT; + + return; + } +#endif + if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) { ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c; ddata->post_reset_quirk = sysc_post_reset_quirk_i2c; diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h index 240dce553a0b..fafc1beea504 100644 --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h @@ -50,6 +50,7 @@ struct sysc_regbits { s8 emufree_shift; }; +#define SYSC_QUIRK_GPMC_DEBUG BIT(26) #define SYSC_MODULE_QUIRK_ENA_RESETDONE BIT(25) #define SYSC_MODULE_QUIRK_PRUSS BIT(24) #define SYSC_MODULE_QUIRK_DSS_RESET BIT(23) -- cgit v1.2.3 From 9fac08999c1010e7d1c95ed136a5e2551b82a527 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: clk: ti: am33xx: Keep am3 l3 main clock always on for genpd In order for suspend and resume to work with genpd on am3, we must keep l3 main clock always on. Otherwise prm_omap driver will shut down the l3 main clock on suspend when simple-pm-bus and GENPD_FLAG_PM_CLK are used. Note that we already keep the l3 main clock always on with the legacy platform code. Later on we may want to start managing the l3 main clock with a dedicated interconnect driver instead of using simple-pm-bus and GENPD_FLAG_PM_CLK. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette Cc: Stephen Boyd Cc: Tero Kristo Signed-off-by: Tony Lindgren --- drivers/clk/ti/clk-33xx.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/ti/clk-33xx.c b/drivers/clk/ti/clk-33xx.c index 7dc30dd6c8d5..f2c22120aaa7 100644 --- a/drivers/clk/ti/clk-33xx.c +++ b/drivers/clk/ti/clk-33xx.c @@ -266,6 +266,8 @@ static const char *enable_init_clks[] = { "dpll_ddr_m2_ck", "dpll_mpu_m2_ck", "l3_gclk", + /* AM3_L3_L3_MAIN_CLKCTRL, needed during suspend */ + "l3-clkctrl:00bc:0", "l4hs_gclk", "l4fw_gclk", "l4ls_gclk", -- cgit v1.2.3 From 176958dd8ea4e9adb373c929bd2590c4056cd617 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: soc: ti: omap-prm: Add pm_clk for genpd In order to probe l3 and l4 interconnects with simple-pm-bus, we want genpd to manage the clocks for the interconnects. For interconnect target modules, we already have ti-sysc manage the clocks so let's skipe managing clocks for ti-sysc modules. Cc: Santosh Shilimkar Signed-off-by: Tony Lindgren --- drivers/soc/ti/omap_prm.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 4d41dc3cdce1..3406c8276efe 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -41,6 +43,7 @@ struct omap_prm_domain { u16 pwrstst; const struct omap_prm_domain_map *cap; u32 pwrstctrl_saved; + unsigned int uses_pm_clk:1; }; struct omap_rst_map { @@ -325,6 +328,38 @@ static int omap_prm_domain_power_off(struct generic_pm_domain *domain) return 0; } +/* + * Note that ti-sysc already manages the module clocks separately so + * no need to manage those. Interconnect instances need clocks managed + * for simple-pm-bus. + */ +static int omap_prm_domain_attach_clock(struct device *dev, + struct omap_prm_domain *prmd) +{ + struct device_node *np = dev->of_node; + int error; + + if (!of_device_is_compatible(np, "simple-pm-bus")) + return 0; + + if (!of_property_read_bool(np, "clocks")) + return 0; + + error = pm_clk_create(dev); + if (error) + return error; + + error = of_pm_clk_add_clks(dev); + if (error < 0) { + pm_clk_destroy(dev); + return error; + } + + prmd->uses_pm_clk = 1; + + return 0; +} + static int omap_prm_domain_attach_dev(struct generic_pm_domain *domain, struct device *dev) { @@ -349,6 +384,10 @@ static int omap_prm_domain_attach_dev(struct generic_pm_domain *domain, genpd_data = dev_gpd_data(dev); genpd_data->data = NULL; + ret = omap_prm_domain_attach_clock(dev, prmd); + if (ret) + return ret; + return 0; } @@ -356,7 +395,11 @@ static void omap_prm_domain_detach_dev(struct generic_pm_domain *domain, struct device *dev) { struct generic_pm_domain_data *genpd_data; + struct omap_prm_domain *prmd; + prmd = genpd_to_prm_domain(domain); + if (prmd->uses_pm_clk) + pm_clk_destroy(dev); genpd_data = dev_gpd_data(dev); genpd_data->data = NULL; } @@ -393,6 +436,7 @@ static int omap_prm_domain_init(struct device *dev, struct omap_prm *prm) prmd->pd.power_off = omap_prm_domain_power_off; prmd->pd.attach_dev = omap_prm_domain_attach_dev; prmd->pd.detach_dev = omap_prm_domain_detach_dev; + prmd->pd.flags = GENPD_FLAG_PM_CLK; pm_genpd_init(&prmd->pd, NULL, true); error = of_genpd_add_provider_simple(np, &prmd->pd); -- cgit v1.2.3 From f29ef9807f85ba5b6afe84d9dca4743211b3507a Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: soc: ti: omap-prm: am3: add genpd support for remaining PRM instances Add genpd support for per, wkup, mpu, rtc and cefuse instances. Cc: Santosh Shilimkar Signed-off-by: Tero Kristo Signed-off-by: Tony Lindgren --- drivers/soc/ti/omap_prm.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 3406c8276efe..f97f629b6b6b 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -124,6 +124,10 @@ static const struct omap_prm_domain_map omap_prm_onoff_noauto = { .statechange = 1, }; +static const struct omap_prm_domain_map omap_prm_alwon = { + .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE), +}; + static const struct omap_rst_map rst_map_0[] = { { .rst = 0, .st = 0 }, { .rst = -1 }, @@ -190,14 +194,40 @@ static const struct omap_rst_map am3_wkup_rst_map[] = { }; static const struct omap_prm_data am3_prm_data[] = { - { .name = "per", .base = 0x44e00c00, .rstctrl = 0x0, .rstmap = am3_per_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL, .clkdm_name = "pruss_ocp" }, - { .name = "wkup", .base = 0x44e00d00, .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, - { .name = "device", .base = 0x44e00f00, .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { + .name = "per", .base = 0x44e00c00, + .pwrstctrl = 0xc, .pwrstst = 0x8, .dmap = &omap_prm_noinact, + .rstctrl = 0x0, .rstmap = am3_per_rst_map, + .flags = OMAP_PRM_HAS_RSTCTRL, .clkdm_name = "pruss_ocp" + }, + { + .name = "wkup", .base = 0x44e00d00, + .pwrstctrl = 0x4, .pwrstst = 0x4, .dmap = &omap_prm_alwon, + .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map, + .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM + }, + { + .name = "mpu", .base = 0x44e00e00, + .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_noinact, + }, + { + .name = "device", .base = 0x44e00f00, + .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01, + .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM + }, + { + .name = "rtc", .base = 0x44e01000, + .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_alwon, + }, { .name = "gfx", .base = 0x44e01100, .pwrstctrl = 0, .pwrstst = 0x10, .dmap = &omap_prm_noinact, .rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3", }, + { + .name = "cefuse", .base = 0x44e01200, + .pwrstctrl = 0x0, .pwrstst = 0x4, .dmap = &omap_prm_onoff_noauto, + }, { }, }; -- cgit v1.2.3 From 74033131d2467fda6b76ba10bc80a75fb47e03d1 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: soc: ti: pm33xx: Enable basic PM runtime support for genpd To prepare for moving to use genpd, let's enable basic PM runtime support. Cc: Dave Gerlach Cc: Santosh Shilimkar Cc: Suman Anna Signed-off-by: Tony Lindgren --- drivers/soc/ti/pm33xx.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/pm33xx.c b/drivers/soc/ti/pm33xx.c index d2f5e7001a93..c1d550e90c31 100644 --- a/drivers/soc/ti/pm33xx.c +++ b/drivers/soc/ti/pm33xx.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -555,16 +556,26 @@ static int am33xx_pm_probe(struct platform_device *pdev) suspend_wfi_flags |= WFI_FLAG_WAKE_M3; #endif /* CONFIG_SUSPEND */ + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + pm_runtime_put_noidle(dev); + goto err_pm_runtime_disable; + } + ret = pm_ops->init(am33xx_do_sram_idle); if (ret) { dev_err(dev, "Unable to call core pm init!\n"); ret = -ENODEV; - goto err_put_wkup_m3_ipc; + goto err_pm_runtime_put; } return 0; -err_put_wkup_m3_ipc: +err_pm_runtime_put: + pm_runtime_put_sync(dev); +err_pm_runtime_disable: + pm_runtime_disable(dev); wkup_m3_ipc_put(m3_ipc); err_free_sram: am33xx_pm_free_sram(); @@ -574,6 +585,8 @@ err_free_sram: static int am33xx_pm_remove(struct platform_device *pdev) { + pm_runtime_put_sync(&pdev->dev); + pm_runtime_disable(&pdev->dev); if (pm_ops->deinit) pm_ops->deinit(); suspend_set_ops(NULL); -- cgit v1.2.3 From 57df7e370d2ab83a64c07acd157acfed4169f114 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Mon, 16 Nov 2020 12:57:13 +0200 Subject: remoteproc/wkup_m3: Use reset control driver if available In order to move wkup_m3 to probe without platform data, let's add support for using optional reset control driver if configured in the dts. With this change and the related dts change, we can start dropping the platform data for am335x. And once wkup_m3 no longer needs platform data, we can simply drop the related legacy reset platform data callbacks from wkup_m3 driver later on after also am437x no longer depends on it. Cc: linux-remoteproc@vger.kernel.org Cc: Bjorn Andersson Cc: Dave Gerlach Cc: Philipp Zabel Cc: Suman Anna Signed-off-by: Tony Lindgren --- drivers/remoteproc/wkup_m3_rproc.c | 41 ++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/remoteproc/wkup_m3_rproc.c b/drivers/remoteproc/wkup_m3_rproc.c index b9349d684258..92d387dfc03b 100644 --- a/drivers/remoteproc/wkup_m3_rproc.c +++ b/drivers/remoteproc/wkup_m3_rproc.c @@ -17,6 +17,7 @@ #include #include #include +#include #include @@ -43,11 +44,13 @@ struct wkup_m3_mem { * @rproc: rproc handle * @pdev: pointer to platform device * @mem: WkupM3 memory information + * @rsts: reset control */ struct wkup_m3_rproc { struct rproc *rproc; struct platform_device *pdev; struct wkup_m3_mem mem[WKUPM3_MEM_MAX]; + struct reset_control *rsts; }; static int wkup_m3_rproc_start(struct rproc *rproc) @@ -56,13 +59,16 @@ static int wkup_m3_rproc_start(struct rproc *rproc) struct platform_device *pdev = wkupm3->pdev; struct device *dev = &pdev->dev; struct wkup_m3_platform_data *pdata = dev_get_platdata(dev); + int error = 0; - if (pdata->deassert_reset(pdev, pdata->reset_name)) { + error = reset_control_deassert(wkupm3->rsts); + + if (!wkupm3->rsts && pdata->deassert_reset(pdev, pdata->reset_name)) { dev_err(dev, "Unable to reset wkup_m3!\n"); - return -ENODEV; + error = -ENODEV; } - return 0; + return error; } static int wkup_m3_rproc_stop(struct rproc *rproc) @@ -71,13 +77,16 @@ static int wkup_m3_rproc_stop(struct rproc *rproc) struct platform_device *pdev = wkupm3->pdev; struct device *dev = &pdev->dev; struct wkup_m3_platform_data *pdata = dev_get_platdata(dev); + int error = 0; - if (pdata->assert_reset(pdev, pdata->reset_name)) { + error = reset_control_assert(wkupm3->rsts); + + if (!wkupm3->rsts && pdata->assert_reset(pdev, pdata->reset_name)) { dev_err(dev, "Unable to assert reset of wkup_m3!\n"); - return -ENODEV; + error = -ENODEV; } - return 0; + return error; } static void *wkup_m3_rproc_da_to_va(struct rproc *rproc, u64 da, size_t len) @@ -132,12 +141,6 @@ static int wkup_m3_rproc_probe(struct platform_device *pdev) int ret; int i; - if (!(pdata && pdata->deassert_reset && pdata->assert_reset && - pdata->reset_name)) { - dev_err(dev, "Platform data missing!\n"); - return -ENODEV; - } - ret = of_property_read_string(dev->of_node, "ti,pm-firmware", &fw_name); if (ret) { @@ -165,6 +168,18 @@ static int wkup_m3_rproc_probe(struct platform_device *pdev) wkupm3->rproc = rproc; wkupm3->pdev = pdev; + wkupm3->rsts = devm_reset_control_get_optional_shared(dev, "rstctrl"); + if (IS_ERR(wkupm3->rsts)) + return PTR_ERR(wkupm3->rsts); + if (!wkupm3->rsts) { + if (!(pdata && pdata->deassert_reset && pdata->assert_reset && + pdata->reset_name)) { + dev_err(dev, "Platform data missing!\n"); + ret = -ENODEV; + goto err_put_rproc; + } + } + for (i = 0; i < ARRAY_SIZE(mem_names); i++) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, mem_names[i]); @@ -173,7 +188,7 @@ static int wkup_m3_rproc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "devm_ioremap_resource failed for resource %d\n", i); ret = PTR_ERR(wkupm3->mem[i].cpu_addr); - goto err; + goto err_put_rproc; } wkupm3->mem[i].bus_addr = res->start; wkupm3->mem[i].size = resource_size(res); -- cgit v1.2.3 From 557acb3d2cd9c82de19f944f6cc967a347735385 Mon Sep 17 00:00:00 2001 From: Amjad Ouled-Ameur Date: Fri, 13 Nov 2020 00:00:43 +0100 Subject: reset: make shared pulsed reset controls re-triggerable The current reset framework API does not allow to release what is done by reset_control_reset(), IOW decrement triggered_count. Add the new reset_control_rearm() call to do so. When reset_control_reset() has been called once, the counter triggered_count, in the reset framework, is incremented i.e the resource under the reset is in-use and the reset should not be done again. reset_control_rearm() would be the way to state that the resource is no longer used and, that from the caller's perspective, the reset can be fired again if necessary. Signed-off-by: Amjad Ouled-Ameur Reported-by: Jerome Brunet Signed-off-by: Philipp Zabel --- drivers/reset/core.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/reset.h | 1 + 2 files changed, 74 insertions(+) diff --git a/drivers/reset/core.c b/drivers/reset/core.c index a2df88e90011..34e89aa0fb5e 100644 --- a/drivers/reset/core.c +++ b/drivers/reset/core.c @@ -208,6 +208,39 @@ static int reset_control_array_reset(struct reset_control_array *resets) return 0; } +static int reset_control_array_rearm(struct reset_control_array *resets) +{ + struct reset_control *rstc; + int i; + + for (i = 0; i < resets->num_rstcs; i++) { + rstc = resets->rstc[i]; + + if (!rstc) + continue; + + if (WARN_ON(IS_ERR(rstc))) + return -EINVAL; + + if (rstc->shared) { + if (WARN_ON(atomic_read(&rstc->deassert_count) != 0)) + return -EINVAL; + } else { + if (!rstc->acquired) + return -EPERM; + } + } + + for (i = 0; i < resets->num_rstcs; i++) { + rstc = resets->rstc[i]; + + if (rstc && rstc->shared) + WARN_ON(atomic_dec_return(&rstc->triggered_count) < 0); + } + + return 0; +} + static int reset_control_array_assert(struct reset_control_array *resets) { int ret, i; @@ -325,6 +358,46 @@ int reset_control_reset(struct reset_control *rstc) } EXPORT_SYMBOL_GPL(reset_control_reset); +/** + * reset_control_rearm - allow shared reset line to be re-triggered" + * @rstc: reset controller + * + * On a shared reset line the actual reset pulse is only triggered once for the + * lifetime of the reset_control instance, except if this call is used. + * + * Calls to this function must be balanced with calls to reset_control_reset, + * a warning is thrown in case triggered_count ever dips below 0. + * + * Consumers must not use reset_control_(de)assert on shared reset lines when + * reset_control_reset or reset_control_rearm have been used. + * + * If rstc is NULL the function will just return 0. + */ +int reset_control_rearm(struct reset_control *rstc) +{ + if (!rstc) + return 0; + + if (WARN_ON(IS_ERR(rstc))) + return -EINVAL; + + if (reset_control_is_array(rstc)) + return reset_control_array_rearm(rstc_to_array(rstc)); + + if (rstc->shared) { + if (WARN_ON(atomic_read(&rstc->deassert_count) != 0)) + return -EINVAL; + + WARN_ON(atomic_dec_return(&rstc->triggered_count) < 0); + } else { + if (!rstc->acquired) + return -EPERM; + } + + return 0; +} +EXPORT_SYMBOL_GPL(reset_control_rearm); + /** * reset_control_assert - asserts the reset line * @rstc: reset controller diff --git a/include/linux/reset.h b/include/linux/reset.h index 05aa9f440f48..439fec7112a9 100644 --- a/include/linux/reset.h +++ b/include/linux/reset.h @@ -13,6 +13,7 @@ struct reset_control; #ifdef CONFIG_RESET_CONTROLLER int reset_control_reset(struct reset_control *rstc); +int reset_control_rearm(struct reset_control *rstc); int reset_control_assert(struct reset_control *rstc); int reset_control_deassert(struct reset_control *rstc); int reset_control_status(struct reset_control *rstc); -- cgit v1.2.3 From 3bfe8933f9d187f93f0d0910b741a59070f58c4c Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Oct 2020 16:48:09 +0200 Subject: reset: meson: make it possible to build as a module In order to reduce the kernel Image size on multi-platform distributions, make it possible to build the reset controller driver as a module. This partially reverts commit 8290924e6878 ("reset: meson: make it explicitly non-modular"). Signed-off-by: Neil Armstrong Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Reviewed-by: Martin Blumenstingl Signed-off-by: Philipp Zabel --- drivers/reset/Kconfig | 3 ++- drivers/reset/reset-meson.c | 8 +++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 07d162b179fc..84baec01aa30 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -95,7 +95,8 @@ config RESET_LPC18XX This enables the reset controller driver for NXP LPC18xx/43xx SoCs. config RESET_MESON - bool "Meson Reset Driver" if COMPILE_TEST + tristate "Meson Reset Driver" + depends on ARCH_MESON || COMPILE_TEST default ARCH_MESON help This enables the reset driver for Amlogic Meson SoCs. diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 94d7ba88d7d2..c9bc325ad65a 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -104,6 +105,7 @@ static const struct of_device_id meson_reset_dt_ids[] = { { .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param}, { /* sentinel */ }, }; +MODULE_DEVICE_TABLE(of, meson_reset_dt_ids); static int meson_reset_probe(struct platform_device *pdev) { @@ -142,4 +144,8 @@ static struct platform_driver meson_reset_driver = { .of_match_table = meson_reset_dt_ids, }, }; -builtin_platform_driver(meson_reset_driver); +module_platform_driver(meson_reset_driver); + +MODULE_DESCRIPTION("Amlogic Meson Reset Controller driver"); +MODULE_AUTHOR("Neil Armstrong "); +MODULE_LICENSE("Dual BSD/GPL"); -- cgit v1.2.3 From b4bdc4fbf8d01227702068703ae2cd82ff25c3db Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 6 Nov 2020 15:52:30 +0100 Subject: soc: sunxi: Deal with the MBUS DMA offsets in a central place So far most of the drivers with the MBUS quirks had to duplicate the code to deal with DT compatibility and enforcing the DMA offsets. Let's move for a more maintainable solution by putting everything in a notifier that would take care of setting up the DMA offsets for all the MBUS devices. Suggested-by: Robin Murphy Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai Reviewed-by: Christoph Hellwig Acked-by: Daniel Vetter --- drivers/soc/sunxi/Kconfig | 8 +++ drivers/soc/sunxi/Makefile | 1 + drivers/soc/sunxi/sunxi_mbus.c | 132 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 drivers/soc/sunxi/sunxi_mbus.c diff --git a/drivers/soc/sunxi/Kconfig b/drivers/soc/sunxi/Kconfig index f10fd6cae13e..1fef0e711056 100644 --- a/drivers/soc/sunxi/Kconfig +++ b/drivers/soc/sunxi/Kconfig @@ -2,6 +2,14 @@ # # Allwinner sunXi SoC drivers # + +config SUNXI_MBUS + bool + default ARCH_SUNXI + help + Say y to enable the fixups needed to support the Allwinner + MBUS DMA quirks. + config SUNXI_SRAM bool default ARCH_SUNXI diff --git a/drivers/soc/sunxi/Makefile b/drivers/soc/sunxi/Makefile index 7816fbbec387..549159571d4f 100644 --- a/drivers/soc/sunxi/Makefile +++ b/drivers/soc/sunxi/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_SUNXI_MBUS) += sunxi_mbus.o obj-$(CONFIG_SUNXI_SRAM) += sunxi_sram.o diff --git a/drivers/soc/sunxi/sunxi_mbus.c b/drivers/soc/sunxi/sunxi_mbus.c new file mode 100644 index 000000000000..a9d077f73c3a --- /dev/null +++ b/drivers/soc/sunxi/sunxi_mbus.c @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (C) 2020 Maxime Ripard */ + +#include +#include +#include +#include +#include +#include + +static const char * const sunxi_mbus_devices[] = { + /* + * The display engine virtual devices are not strictly speaking + * connected to the MBUS, but since DRM will perform all the + * memory allocations and DMA operations through that device, we + * need to have the quirk on those devices too. + */ + "allwinner,sun4i-a10-display-engine", + "allwinner,sun5i-a10s-display-engine", + "allwinner,sun5i-a13-display-engine", + "allwinner,sun6i-a31-display-engine", + "allwinner,sun6i-a31s-display-engine", + "allwinner,sun7i-a20-display-engine", + "allwinner,sun8i-a23-display-engine", + "allwinner,sun8i-a33-display-engine", + "allwinner,sun8i-a83t-display-engine", + "allwinner,sun8i-h3-display-engine", + "allwinner,sun8i-r40-display-engine", + "allwinner,sun8i-v3s-display-engine", + "allwinner,sun9i-a80-display-engine", + "allwinner,sun50i-a64-display-engine", + + /* + * And now we have the regular devices connected to the MBUS + * (that we know of). + */ + "allwinner,sun4i-a10-csi1", + "allwinner,sun4i-a10-display-backend", + "allwinner,sun4i-a10-display-frontend", + "allwinner,sun4i-a10-video-engine", + "allwinner,sun5i-a13-display-backend", + "allwinner,sun5i-a13-video-engine", + "allwinner,sun6i-a31-csi", + "allwinner,sun6i-a31-display-backend", + "allwinner,sun7i-a20-csi0", + "allwinner,sun7i-a20-display-backend", + "allwinner,sun7i-a20-display-frontend", + "allwinner,sun7i-a20-video-engine", + "allwinner,sun8i-a23-display-backend", + "allwinner,sun8i-a23-display-frontend", + "allwinner,sun8i-a33-display-backend", + "allwinner,sun8i-a33-display-frontend", + "allwinner,sun8i-a33-video-engine", + "allwinner,sun8i-a83t-csi", + "allwinner,sun8i-h3-csi", + "allwinner,sun8i-h3-video-engine", + "allwinner,sun8i-v3s-csi", + "allwinner,sun9i-a80-display-backend", + "allwinner,sun50i-a64-csi", + "allwinner,sun50i-a64-video-engine", + "allwinner,sun50i-h5-video-engine", + NULL, +}; + +static int sunxi_mbus_notifier(struct notifier_block *nb, + unsigned long event, void *__dev) +{ + struct device *dev = __dev; + int ret; + + if (event != BUS_NOTIFY_ADD_DEVICE) + return NOTIFY_DONE; + + /* + * Only the devices that need a large memory bandwidth do DMA + * directly over the memory bus (called MBUS), instead of going + * through the regular system bus. + */ + if (!of_device_compatible_match(dev->of_node, sunxi_mbus_devices)) + return NOTIFY_DONE; + + /* + * Devices with an interconnects property have the MBUS + * relationship described in their DT and dealt with by + * of_dma_configure, so we can just skip them. + * + * Older DTs or SoCs who are not clearly understood need to set + * that DMA offset though. + */ + if (of_find_property(dev->of_node, "interconnects", NULL)) + return NOTIFY_DONE; + + ret = dma_direct_set_offset(dev, PHYS_OFFSET, 0, SZ_4G); + if (ret) + dev_err(dev, "Couldn't setup our DMA offset: %d\n", ret); + + return NOTIFY_DONE; +} + +static struct notifier_block sunxi_mbus_nb = { + .notifier_call = sunxi_mbus_notifier, +}; + +static const char * const sunxi_mbus_platforms[] __initconst = { + "allwinner,sun4i-a10", + "allwinner,sun5i-a10s", + "allwinner,sun5i-a13", + "allwinner,sun6i-a31", + "allwinner,sun7i-a20", + "allwinner,sun8i-a23", + "allwinner,sun8i-a33", + "allwinner,sun8i-a83t", + "allwinner,sun8i-h3", + "allwinner,sun8i-r40", + "allwinner,sun8i-v3", + "allwinner,sun8i-v3s", + "allwinner,sun9i-a80", + "allwinner,sun50i-a64", + "allwinner,sun50i-h5", + "nextthing,gr8", + NULL, +}; + +static int __init sunxi_mbus_init(void) +{ + if (!of_device_compatible_match(of_root, sunxi_mbus_platforms)) + return 0; + + bus_register_notifier(&platform_bus_type, &sunxi_mbus_nb); + return 0; +} +arch_initcall(sunxi_mbus_init); -- cgit v1.2.3 From 756668ba682ec50639362b081b305f3499bb180c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 6 Nov 2020 15:55:05 +0100 Subject: drm/sun4i: backend: Remove the MBUS quirks Now that the MBUS quirks are applied by our global notifier, we can remove them from our DRM driver. Suggested-by: Christoph Hellwig Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai Reviewed-by: Christoph Hellwig Acked-by: Daniel Vetter --- drivers/gpu/drm/sun4i/sun4i_backend.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index 55960cbb1019..522e51a404cc 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -805,25 +805,6 @@ static int sun4i_backend_bind(struct device *dev, struct device *master, ret = of_dma_configure(drm->dev, dev->of_node, true); if (ret) return ret; - } else { - /* - * If we don't have the interconnect property, most likely - * because of an old DT, we need to set the DMA offset by hand - * on our device since the RAM mapping is at 0 for the DMA bus, - * unlike the CPU. - * - * XXX(hch): this has no business in a driver and needs to move - * to the device tree. - * - * If we have two subsequent calls to dma_direct_set_offset - * returns -EINVAL. Unfortunately, this happens when we have two - * backends in the system, and will result in the driver - * reporting an error while it has been setup properly before. - * Ignore EINVAL, but it should really be removed eventually. - */ - ret = dma_direct_set_offset(drm->dev, PHYS_OFFSET, 0, SZ_4G); - if (ret && ret != -EINVAL) - return ret; } backend->engine.node = dev->of_node; -- cgit v1.2.3 From 13dd871011503e038a551e09ae004ae0da496a4c Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 6 Nov 2020 15:55:05 +0100 Subject: media: sun4i: Remove the MBUS quirks Now that the MBUS quirks are applied by our global notifier, we can remove them from our CSI driver for the A10. Suggested-by: Christoph Hellwig Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai Reviewed-by: Christoph Hellwig Acked-by: Hans Verkuil Acked-by: Daniel Vetter --- drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c | 27 ---------------------- 1 file changed, 27 deletions(-) diff --git a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c index eb15c8c725ca..ec46cff80fdb 100644 --- a/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c +++ b/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c @@ -167,33 +167,6 @@ static int sun4i_csi_probe(struct platform_device *pdev) if (!csi->traits) return -EINVAL; - /* - * On Allwinner SoCs, some high memory bandwidth devices do DMA - * directly over the memory bus (called MBUS), instead of the - * system bus. The memory bus has a different addressing scheme - * without the DRAM starting offset. - * - * In some cases this can be described by an interconnect in - * the device tree. In other cases where the hardware is not - * fully understood and the interconnect is left out of the - * device tree, fall back to a default offset. - */ - if (of_find_property(csi->dev->of_node, "interconnects", NULL)) { - ret = of_dma_configure(csi->dev, csi->dev->of_node, true); - if (ret) - return ret; - } else { - /* - * XXX(hch): this has no business in a driver and needs to move - * to the device tree. - */ -#ifdef PHYS_PFN_OFFSET - ret = dma_direct_set_offset(csi->dev, PHYS_OFFSET, 0, SZ_4G); - if (ret) - return ret; -#endif - } - csi->mdev.dev = csi->dev; strscpy(csi->mdev.model, "Allwinner Video Capture Device", sizeof(csi->mdev.model)); -- cgit v1.2.3 From d60ab69b607ffd72df1a9642cbd451498f924bb4 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 6 Nov 2020 15:55:05 +0100 Subject: media: sun6i: Remove the MBUS quirks Now that the MBUS quirks are applied by our global notifier, we can remove them from our CSI driver for the A31. Suggested-by: Christoph Hellwig Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai Reviewed-by: Christoph Hellwig Acked-by: Hans Verkuil Acked-by: Daniel Vetter --- drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c index e69e14379fc6..27935f1e9555 100644 --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c @@ -881,14 +881,6 @@ static int sun6i_csi_resource_request(struct sun6i_csi_dev *sdev, return 0; } -/* - * PHYS_OFFSET isn't available on all architectures. In order to - * accommodate for COMPILE_TEST, let's define it to something dumb. - */ -#if defined(CONFIG_COMPILE_TEST) && !defined(PHYS_OFFSET) -#define PHYS_OFFSET 0 -#endif - static int sun6i_csi_probe(struct platform_device *pdev) { struct sun6i_csi_dev *sdev; @@ -899,15 +891,6 @@ static int sun6i_csi_probe(struct platform_device *pdev) return -ENOMEM; sdev->dev = &pdev->dev; - /* - * The DMA bus has the memory mapped at 0. - * - * XXX(hch): this has no business in a driver and needs to move - * to the device tree. - */ - ret = dma_direct_set_offset(sdev->dev, PHYS_OFFSET, 0, SZ_4G); - if (ret) - return ret; ret = sun6i_csi_resource_request(sdev, pdev); if (ret) -- cgit v1.2.3 From c6e95daab1ccc17a6556c3c2034affbe15db8b3b Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 6 Nov 2020 15:55:05 +0100 Subject: media: cedrus: Remove the MBUS quirks Now that the MBUS quirks are applied by our global notifier, we can remove them from Cedrus. Since the only quirk was whether or not we had to apply that DMA quirk, we can also remove the quirks infrastructure. Suggested-by: Christoph Hellwig Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai Reviewed-by: Christoph Hellwig Acked-by: Hans Verkuil Acked-by: Daniel Vetter --- drivers/staging/media/sunxi/cedrus/cedrus.c | 1 - drivers/staging/media/sunxi/cedrus/cedrus.h | 3 --- drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 18 ------------------ 3 files changed, 22 deletions(-) diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c index e0e35502e34a..d5fca10ea5b4 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c @@ -523,7 +523,6 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = { static const struct cedrus_variant sun50i_h6_cedrus_variant = { .capabilities = CEDRUS_CAPABILITY_UNTILED | CEDRUS_CAPABILITY_H265_DEC, - .quirks = CEDRUS_QUIRK_NO_DMA_OFFSET, .mod_rate = 600000000, }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h index 93c843ae14bb..626090a5811c 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus.h +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h @@ -29,8 +29,6 @@ #define CEDRUS_CAPABILITY_UNTILED BIT(0) #define CEDRUS_CAPABILITY_H265_DEC BIT(1) -#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) - enum cedrus_codec { CEDRUS_CODEC_MPEG2, CEDRUS_CODEC_H264, @@ -150,7 +148,6 @@ struct cedrus_dec_ops { struct cedrus_variant { unsigned int capabilities; - unsigned int quirks; unsigned int mod_rate; }; diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c index bcf050a04ffc..286c7fe844c3 100644 --- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c +++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c @@ -222,24 +222,6 @@ int cedrus_hw_probe(struct cedrus_dev *dev) return ret; } - /* - * The VPU is only able to handle bus addresses so we have to subtract - * the RAM offset to the physcal addresses. - * - * This information will eventually be obtained from device-tree. - * - * XXX(hch): this has no business in a driver and needs to move - * to the device tree. - */ - -#ifdef PHYS_PFN_OFFSET - if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET)) { - ret = dma_direct_set_offset(dev->dev, PHYS_OFFSET, 0, SZ_4G); - if (ret) - return ret; - } -#endif - ret = of_reserved_mem_device_init(dev->dev); if (ret && ret != -ENODEV) { dev_err(dev->dev, "Failed to reserve memory\n"); -- cgit v1.2.3 From 5739301308fd1a4c4b7a561f9bf6c1356e5c0612 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Fri, 6 Nov 2020 15:58:50 +0100 Subject: media: sun8i-di: Remove the call to of_dma_configure of_dma_configure is called by the core before probe gets called so this is redundant. Signed-off-by: Maxime Ripard Reviewed-by: Chen-Yu Tsai Reviewed-by: Christoph Hellwig Acked-by: Hans Verkuil Acked-by: Daniel Vetter --- drivers/media/platform/sunxi/sun8i-di/sun8i-di.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c index ba5d07886607..ed863bf5ea80 100644 --- a/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c +++ b/drivers/media/platform/sunxi/sun8i-di/sun8i-di.c @@ -825,10 +825,6 @@ static int deinterlace_probe(struct platform_device *pdev) return ret; } - ret = of_dma_configure(dev->dev, dev->dev->of_node, true); - if (ret) - return ret; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); dev->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(dev->base)) -- cgit v1.2.3 From 16fee29b07358293f135759d9fdbf1267da57ebd Mon Sep 17 00:00:00 2001 From: Christoph Hellwig Date: Fri, 6 Nov 2020 17:02:17 +0100 Subject: dma-mapping: remove the dma_direct_set_offset export Drop the dma_direct_set_offset export and move the declaration to dma-map-ops.h now that the Allwinner drivers have stopped calling it. Signed-off-by: Christoph Hellwig Signed-off-by: Maxime Ripard --- arch/arm/mach-keystone/keystone.c | 2 +- arch/arm/mach-omap1/usb.c | 2 +- arch/sh/drivers/pci/pcie-sh7786.c | 2 +- arch/x86/pci/sta2x11-fixup.c | 3 ++- include/linux/dma-map-ops.h | 3 +++ include/linux/dma-mapping.h | 7 ------- kernel/dma/direct.c | 1 - 7 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index 09a65c2dfd73..cd711bfc591f 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -8,7 +8,7 @@ */ #include #include -#include +#include #include #include #include diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c index ba8566204ea9..86d3b3c157af 100644 --- a/arch/arm/mach-omap1/usb.c +++ b/arch/arm/mach-omap1/usb.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include diff --git a/arch/sh/drivers/pci/pcie-sh7786.c b/arch/sh/drivers/pci/pcie-sh7786.c index 4468289ab2ca..4d499476c33a 100644 --- a/arch/sh/drivers/pci/pcie-sh7786.c +++ b/arch/sh/drivers/pci/pcie-sh7786.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/arch/x86/pci/sta2x11-fixup.c b/arch/x86/pci/sta2x11-fixup.c index 5701d5ba3df4..7d2525691854 100644 --- a/arch/x86/pci/sta2x11-fixup.c +++ b/arch/x86/pci/sta2x11-fixup.c @@ -11,7 +11,8 @@ #include #include #include -#include +#include +#include #include #define STA2X11_SWIOTLB_SIZE (4*1024*1024) diff --git a/include/linux/dma-map-ops.h b/include/linux/dma-map-ops.h index a5f89fc4d6df..03925e438ec3 100644 --- a/include/linux/dma-map-ops.h +++ b/include/linux/dma-map-ops.h @@ -226,6 +226,9 @@ struct page *dma_alloc_from_pool(struct device *dev, size_t size, bool (*phys_addr_ok)(struct device *, phys_addr_t, size_t)); bool dma_free_from_pool(struct device *dev, void *start, size_t size); +int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start, + dma_addr_t dma_start, u64 size); + #ifdef CONFIG_ARCH_HAS_DMA_COHERENCE_H #include #elif defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \ diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h index 956151052d45..199d85285246 100644 --- a/include/linux/dma-mapping.h +++ b/include/linux/dma-mapping.h @@ -558,13 +558,6 @@ static inline int dma_mmap_wc(struct device *dev, #define dma_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) #endif -/* - * Legacy interface to set up the dma offset map. Drivers really should not - * actually use it, but we have a few legacy cases left. - */ -int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start, - dma_addr_t dma_start, u64 size); - extern const struct dma_map_ops dma_virt_ops; #endif /* _LINUX_DMA_MAPPING_H */ diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c index 06c111544f61..002268262c9a 100644 --- a/kernel/dma/direct.c +++ b/kernel/dma/direct.c @@ -547,4 +547,3 @@ int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start, dev->dma_range_map = map; return 0; } -EXPORT_SYMBOL_GPL(dma_direct_set_offset); -- cgit v1.2.3 From 5445a0c0d3366358e7ac44efa108b6fd359873e3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 29 Oct 2020 20:33:57 +0100 Subject: memory: pl353-smc: fix compile test on !ARM_AMBA The pl353-smc driver uses module_amba_driver so it has a build dependency on CONFIG_ARM_AMBA: /usr/bin/arm-linux-gnueabi-ld: drivers/memory/pl353-smc.o: in function `pl353_smc_driver_init': pl353-smc.c:(.init.text+0x10): undefined reference to `amba_driver_register' However it still can be compile tested on platforms other than ARM, which in practice is limited to those selecting ARM_AMBA (so only ARM64). Fixes: ea0c0ad6b6eb ("memory: Enable compile testing for most of the drivers") Reported-by: kernel test robot Signed-off-by: Krzysztof Kozlowski Acked-by: Michal Simek Link: https://lore.kernel.org/r/20201029193357.389593-1-krzk@kernel.org --- drivers/memory/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 00e013b14703..eebd2ddcd860 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -191,8 +191,8 @@ config DA8XX_DDRCTL config PL353_SMC tristate "ARM PL35X Static Memory Controller(SMC) driver" default y if ARM - depends on ARM - depends on ARM_AMBA || COMPILE_TEST + depends on ARM || COMPILE_TEST + depends on ARM_AMBA help This driver is for the ARM PL351/PL353 Static Memory Controller(SMC) module. -- cgit v1.2.3 From b9ce9b0f83b536a4ac7de7567a265d28d13e5bea Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 18 Nov 2020 20:44:57 -0800 Subject: soc/tegra: fuse: Fix index bug in get_process_id This patch simply fixes a bug of referencing speedos[num] in every for-loop iteration in get_process_id function. Fixes: 0dc5a0d83675 ("soc/tegra: fuse: Add Tegra210 support") Cc: Signed-off-by: Nicolin Chen Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/speedo-tegra210.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/tegra/fuse/speedo-tegra210.c b/drivers/soc/tegra/fuse/speedo-tegra210.c index 7394a8d694cb..695d0b7f9a8a 100644 --- a/drivers/soc/tegra/fuse/speedo-tegra210.c +++ b/drivers/soc/tegra/fuse/speedo-tegra210.c @@ -94,7 +94,7 @@ static int get_process_id(int value, const u32 *speedos, unsigned int num) unsigned int i; for (i = 0; i < num; i++) - if (value < speedos[num]) + if (value < speedos[i]) return i; return -EINVAL; -- cgit v1.2.3 From 959b981dc7bc144e0e256f8fe34b6ce23e839525 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Sun, 1 Nov 2020 07:06:22 -0800 Subject: soc: aspeed: remove unneeded semicolon A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20201101150622.2288203-1-trix@redhat.com Signed-off-by: Joel Stanley --- drivers/soc/aspeed/aspeed-socinfo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/aspeed/aspeed-socinfo.c b/drivers/soc/aspeed/aspeed-socinfo.c index 26db42ef6aae..20a1d4aeb051 100644 --- a/drivers/soc/aspeed/aspeed-socinfo.c +++ b/drivers/soc/aspeed/aspeed-socinfo.c @@ -51,7 +51,7 @@ static const char *siliconid_to_rev(u32 siliconid) return "A1"; case 3: return "A2"; - }; + } return "??"; } -- cgit v1.2.3 From 0f0c9c702241d839dbb1d355b77e5712a5a5793f Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Fri, 13 Nov 2020 13:08:50 +0300 Subject: soc: aspeed: Fix a reference leak in aspeed_socinfo_init() This needs to call of_node_put(np) before returning if of_iomap() fails. Fixes: e0218dca5787 ("soc: aspeed: Add soc info driver") Signed-off-by: Dan Carpenter Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20201113100850.GA168908@mwanda Signed-off-by: Joel Stanley --- drivers/soc/aspeed/aspeed-socinfo.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/soc/aspeed/aspeed-socinfo.c b/drivers/soc/aspeed/aspeed-socinfo.c index 20a1d4aeb051..773930e0cb10 100644 --- a/drivers/soc/aspeed/aspeed-socinfo.c +++ b/drivers/soc/aspeed/aspeed-socinfo.c @@ -74,8 +74,10 @@ static int __init aspeed_socinfo_init(void) } reg = of_iomap(np, 0); - if (!reg) + if (!reg) { + of_node_put(np); return -ENODEV; + } siliconid = readl(reg); iounmap(reg); -- cgit v1.2.3 From 4da595ddc06909d9ba8fcedcce0c4e1e0a4c3244 Mon Sep 17 00:00:00 2001 From: Joel Stanley Date: Thu, 19 Nov 2020 22:47:04 +1030 Subject: soc: aspeed: Enable drivers with ARCH_ASPEED Default the drivers to on as most configurations will use them. Signed-off-by: Joel Stanley --- drivers/soc/aspeed/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig index 7ece0675b1fa..243ca196e6ad 100644 --- a/drivers/soc/aspeed/Kconfig +++ b/drivers/soc/aspeed/Kconfig @@ -8,6 +8,7 @@ config ASPEED_LPC_CTRL tristate "ASPEED LPC firmware cycle control" select REGMAP select MFD_SYSCON + default ARCH_ASPEED help Control LPC firmware cycle mappings through ioctl()s. The driver also provides a read/write interface to a BMC ram region where the @@ -17,6 +18,7 @@ config ASPEED_LPC_SNOOP tristate "ASPEED LPC snoop support" select REGMAP select MFD_SYSCON + default ARCH_ASPEED help Provides a driver to control the LPC snoop interface which allows the BMC to listen on and save the data written by @@ -26,6 +28,7 @@ config ASPEED_P2A_CTRL tristate "ASPEED P2A (VGA MMIO to BMC) bridge control" select REGMAP select MFD_SYSCON + default ARCH_ASPEED help Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The driver also provides an interface for userspace mappings to a @@ -35,6 +38,7 @@ config ASPEED_SOCINFO bool "ASPEED SoC Information driver" default ARCH_ASPEED select SOC_BUS + default ARCH_ASPEED help Say yes to support decoding of ASPEED BMC information. -- cgit v1.2.3 From 1606173c53340fe165b2bffb51d16e713a1c0921 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 30 Sep 2020 13:44:12 +0530 Subject: dt-bindings: msm: Add LLCC for SM8150 Add LLCC compatible for SM8150 SoC. Acked-by: Rob Herring Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/141e7cf03932859243edec83451c04c655ba640b.1601452132.git.schowdhu@codeaurora.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index c3a8604dfa80..0a9889debc7c 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -23,6 +23,7 @@ properties: enum: - qcom,sc7180-llcc - qcom,sdm845-llcc + - qcom,sm8150-llcc reg: items: -- cgit v1.2.3 From ded5ed04d85e299770dcb7e82c2127b8054a00c8 Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 30 Sep 2020 13:44:13 +0530 Subject: soc: qcom: llcc: Add configuration data for SM8150 Add LLCC configuration data for SM8150 SoC which controls LLCC behaviour. Signed-off-by: Souradeep Chowdhury Link: https://lore.kernel.org/r/957e3ae50c75720ef6227529d5ce3d4b457802e9.1601452132.git.schowdhu@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/llcc-qcom.c | 30 ++++++++++++++++++++++++++++++ include/linux/soc/qcom/llcc-qcom.h | 6 ++++++ 2 files changed, 36 insertions(+) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 96c20e673436..16b421608e9c 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -123,6 +123,30 @@ static const struct llcc_slice_config sdm845_data[] = { { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, }; +static const struct llcc_slice_config sm8150_data[] = { + { LLCC_CPUSS, 1, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 1 }, + { LLCC_VIDSC0, 2, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_VIDSC1, 3, 512, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_AUDIO, 6, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MDMHPGRW, 7, 3072, 1, 0, 0xFF, 0xF00, 0, 0, 0, 1, 0 }, + { LLCC_MDM, 8, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MODHW, 9, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_CMPT, 10, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPUHTW , 11, 512, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_GPU, 12, 2560, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MMUHWT, 13, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 1 }, + { LLCC_CMPTDMA, 15, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_DISP, 16, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MDMHPFX, 20, 1024, 2, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MDMHPFX, 21, 1024, 0, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_AUDHW, 22, 1024, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_NPU, 23, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_WLHW, 24, 3072, 1, 1, 0xFFF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_MODPE, 29, 256, 1, 1, 0xF, 0x0, 0, 0, 0, 1, 0 }, + { LLCC_APTCM, 30, 256, 3, 1, 0x0, 0x1, 1, 0, 0, 1, 0 }, + { LLCC_WRCACHE, 31, 128, 1, 1, 0xFFF, 0x0, 0, 0, 0, 0, 0 }, +}; + static const struct qcom_llcc_config sc7180_cfg = { .sct_data = sc7180_data, .size = ARRAY_SIZE(sc7180_data), @@ -135,6 +159,11 @@ static const struct qcom_llcc_config sdm845_cfg = { .need_llcc_cfg = false, }; +static const struct qcom_llcc_config sm8150_cfg = { + .sct_data = sm8150_data, + .size = ARRAY_SIZE(sm8150_data), +}; + static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; /** @@ -529,6 +558,7 @@ err: static const struct of_device_id qcom_llcc_of_match[] = { { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, + { .compatible = "qcom,sm8150-llcc", .data = &sm8150_cfg }, { } }; diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index 90b864655822..3db6797ba6ff 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -16,6 +16,7 @@ #define LLCC_AUDIO 6 #define LLCC_MDMHPGRW 7 #define LLCC_MDM 8 +#define LLCC_MODHW 9 #define LLCC_CMPT 10 #define LLCC_GPUHTW 11 #define LLCC_GPU 12 @@ -26,6 +27,11 @@ #define LLCC_MDMHPFX 20 #define LLCC_MDMPNG 21 #define LLCC_AUDHW 22 +#define LLCC_NPU 23 +#define LLCC_WLHW 24 +#define LLCC_MODPE 29 +#define LLCC_APTCM 30 +#define LLCC_WRCACHE 31 /** * llcc_slice_desc - Cache slice descriptor -- cgit v1.2.3 From f25fb6de67205c71c542f51d7d2fbf16de16362a Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Thu, 19 Nov 2020 17:49:01 +0000 Subject: firmware: arm_scmi: Rework scmi_sensors_protocol_init Properly handle return values from initialization helpers and avoid setting sensor_ops before sensor_priv. Link: https://lore.kernel.org/r/20201119174906.43862-2-cristian.marussi@arm.com Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/sensors.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c index b4232d611033..6aaff478d032 100644 --- a/drivers/firmware/arm_scmi/sensors.c +++ b/drivers/firmware/arm_scmi/sensors.c @@ -2,7 +2,7 @@ /* * System Control and Management Interface (SCMI) Sensor Protocol * - * Copyright (C) 2018 ARM Ltd. + * Copyright (C) 2018-2020 ARM Ltd. */ #define pr_fmt(fmt) "SCMI Notifications SENSOR - " fmt @@ -334,6 +334,7 @@ static const struct scmi_event_ops sensor_event_ops = { static int scmi_sensors_protocol_init(struct scmi_handle *handle) { u32 version; + int ret; struct sensors_info *sinfo; scmi_version_get(handle, SCMI_PROTOCOL_SENSOR, &version); @@ -344,15 +345,19 @@ static int scmi_sensors_protocol_init(struct scmi_handle *handle) sinfo = devm_kzalloc(handle->dev, sizeof(*sinfo), GFP_KERNEL); if (!sinfo) return -ENOMEM; + sinfo->version = version; - scmi_sensor_attributes_get(handle, sinfo); - + ret = scmi_sensor_attributes_get(handle, sinfo); + if (ret) + return ret; sinfo->sensors = devm_kcalloc(handle->dev, sinfo->num_sensors, sizeof(*sinfo->sensors), GFP_KERNEL); if (!sinfo->sensors) return -ENOMEM; - scmi_sensor_description_get(handle, sinfo); + ret = scmi_sensor_description_get(handle, sinfo); + if (ret) + return ret; scmi_register_protocol_events(handle, SCMI_PROTOCOL_SENSOR, SCMI_PROTO_QUEUE_SZ, @@ -360,9 +365,8 @@ static int scmi_sensors_protocol_init(struct scmi_handle *handle) ARRAY_SIZE(sensor_events), sinfo->num_sensors); - sinfo->version = version; - handle->sensor_ops = &sensor_ops; handle->sensor_priv = sinfo; + handle->sensor_ops = &sensor_ops; return 0; } -- cgit v1.2.3 From 607a4672b458b12674b96724e2f9bd42a5e928c6 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Fri, 20 Nov 2020 10:55:17 +0000 Subject: firmware: arm_scmi: Add full list of sensor type enumeration SCMI v2.0 provides a big list of sensor type enumeration from the sensorUnits enumeration table of Distributed Management Task Force(DMTF) specification number DSP 0248 (Platform Level Data Model for Platform Monitoring and Control Specification). It is however not an exact replica of the sensorUnits enumeration table. Let us just update the table as per SCMI v2.0 specification. Link: https://lore.kernel.org/r/20201119174906.43862-3-cristian.marussi@arm.com Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- include/linux/scmi_protocol.h | 81 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 9cd312a1ff92..13d75956aa91 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -163,11 +163,92 @@ struct scmi_sensor_info { */ enum scmi_sensor_class { NONE = 0x0, + UNSPEC = 0x1, TEMPERATURE_C = 0x2, + TEMPERATURE_F = 0x3, + TEMPERATURE_K = 0x4, VOLTAGE = 0x5, CURRENT = 0x6, POWER = 0x7, ENERGY = 0x8, + CHARGE = 0x9, + VOLTAMPERE = 0xA, + NITS = 0xB, + LUMENS = 0xC, + LUX = 0xD, + CANDELAS = 0xE, + KPA = 0xF, + PSI = 0x10, + NEWTON = 0x11, + CFM = 0x12, + RPM = 0x13, + HERTZ = 0x14, + SECS = 0x15, + MINS = 0x16, + HOURS = 0x17, + DAYS = 0x18, + WEEKS = 0x19, + MILS = 0x1A, + INCHES = 0x1B, + FEET = 0x1C, + CUBIC_INCHES = 0x1D, + CUBIC_FEET = 0x1E, + METERS = 0x1F, + CUBIC_CM = 0x20, + CUBIC_METERS = 0x21, + LITERS = 0x22, + FLUID_OUNCES = 0x23, + RADIANS = 0x24, + STERADIANS = 0x25, + REVOLUTIONS = 0x26, + CYCLES = 0x27, + GRAVITIES = 0x28, + OUNCES = 0x29, + POUNDS = 0x2A, + FOOT_POUNDS = 0x2B, + OUNCE_INCHES = 0x2C, + GAUSS = 0x2D, + GILBERTS = 0x2E, + HENRIES = 0x2F, + FARADS = 0x30, + OHMS = 0x31, + SIEMENS = 0x32, + MOLES = 0x33, + BECQUERELS = 0x34, + PPM = 0x35, + DECIBELS = 0x36, + DBA = 0x37, + DBC = 0x38, + GRAYS = 0x39, + SIEVERTS = 0x3A, + COLOR_TEMP_K = 0x3B, + BITS = 0x3C, + BYTES = 0x3D, + WORDS = 0x3E, + DWORDS = 0x3F, + QWORDS = 0x40, + PERCENTAGE = 0x41, + PASCALS = 0x42, + COUNTS = 0x43, + GRAMS = 0x44, + NEWTON_METERS = 0x45, + HITS = 0x46, + MISSES = 0x47, + RETRIES = 0x48, + OVERRUNS = 0x49, + UNDERRUNS = 0x4A, + COLLISIONS = 0x4B, + PACKETS = 0x4C, + MESSAGES = 0x4D, + CHARS = 0x4E, + ERRORS = 0x4F, + CORRECTED_ERRS = 0x50, + UNCORRECTABLE_ERRS = 0x51, + SQ_MILS = 0x52, + SQ_INCHES = 0x53, + SQ_FEET = 0x54, + SQ_CM = 0x55, + SQ_METERS = 0x56, }; /** -- cgit v1.2.3 From 1fe00b8b4276ddf335216f884cb719edbea129e1 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Thu, 19 Nov 2020 17:49:02 +0000 Subject: firmware: arm_scmi: Add SCMI v3.0 sensors descriptors extensions Add support for new SCMI v3.0 Sensors extensions related to new sensors' features, like multiple axis and update intervals, while keeping compatibility with SCMI v2.0 features. While at that, refactor and simplify all the internal helpers macros and move struct scmi_sensor_info to use only non-fixed-size typing. Link: https://lore.kernel.org/r/20201119174906.43862-3-cristian.marussi@arm.com Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/sensors.c | 390 ++++++++++++++++++++++++++++++++++-- include/linux/scmi_protocol.h | 139 ++++++++++++- 2 files changed, 504 insertions(+), 25 deletions(-) diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c index 6aaff478d032..a85827f60a02 100644 --- a/drivers/firmware/arm_scmi/sensors.c +++ b/drivers/firmware/arm_scmi/sensors.c @@ -7,16 +7,22 @@ #define pr_fmt(fmt) "SCMI Notifications SENSOR - " fmt +#include #include #include "common.h" #include "notify.h" +#define SCMI_MAX_NUM_SENSOR_AXIS 63 +#define SCMIv2_SENSOR_PROTOCOL 0x10000 + enum scmi_sensor_protocol_cmd { SENSOR_DESCRIPTION_GET = 0x3, SENSOR_TRIP_POINT_NOTIFY = 0x4, SENSOR_TRIP_POINT_CONFIG = 0x5, SENSOR_READING_GET = 0x6, + SENSOR_AXIS_DESCRIPTION_GET = 0x7, + SENSOR_LIST_UPDATE_INTERVALS = 0x8, }; struct scmi_msg_resp_sensor_attributes { @@ -28,23 +34,100 @@ struct scmi_msg_resp_sensor_attributes { __le32 reg_size; }; +/* v3 attributes_low macros */ +#define SUPPORTS_UPDATE_NOTIFY(x) FIELD_GET(BIT(30), (x)) +#define SENSOR_TSTAMP_EXP(x) FIELD_GET(GENMASK(14, 10), (x)) +#define SUPPORTS_TIMESTAMP(x) FIELD_GET(BIT(9), (x)) +#define SUPPORTS_EXTEND_ATTRS(x) FIELD_GET(BIT(8), (x)) + +/* v2 attributes_high macros */ +#define SENSOR_UPDATE_BASE(x) FIELD_GET(GENMASK(31, 27), (x)) +#define SENSOR_UPDATE_SCALE(x) FIELD_GET(GENMASK(26, 22), (x)) + +/* v3 attributes_high macros */ +#define SENSOR_AXIS_NUMBER(x) FIELD_GET(GENMASK(21, 16), (x)) +#define SUPPORTS_AXIS(x) FIELD_GET(BIT(8), (x)) + +/* v3 resolution macros */ +#define SENSOR_RES(x) FIELD_GET(GENMASK(26, 0), (x)) +#define SENSOR_RES_EXP(x) FIELD_GET(GENMASK(31, 27), (x)) + +struct scmi_msg_resp_attrs { + __le32 min_range_low; + __le32 min_range_high; + __le32 max_range_low; + __le32 max_range_high; +}; + struct scmi_msg_resp_sensor_description { __le16 num_returned; __le16 num_remaining; - struct { + struct scmi_sensor_descriptor { + __le32 id; + __le32 attributes_low; +/* Common attributes_low macros */ +#define SUPPORTS_ASYNC_READ(x) FIELD_GET(BIT(31), (x)) +#define NUM_TRIP_POINTS(x) FIELD_GET(GENMASK(7, 0), (x)) + __le32 attributes_high; +/* Common attributes_high macros */ +#define SENSOR_SCALE(x) FIELD_GET(GENMASK(15, 11), (x)) +#define SENSOR_SCALE_SIGN BIT(4) +#define SENSOR_SCALE_EXTEND GENMASK(31, 5) +#define SENSOR_TYPE(x) FIELD_GET(GENMASK(7, 0), (x)) + u8 name[SCMI_MAX_STR_SIZE]; + /* only for version > 2.0 */ + __le32 power; + __le32 resolution; + struct scmi_msg_resp_attrs scalar_attrs; + } desc[]; +}; + +/* Base scmi_sensor_descriptor size excluding extended attrs after name */ +#define SCMI_MSG_RESP_SENS_DESCR_BASE_SZ 28 + +/* Sign extend to a full s32 */ +#define S32_EXT(v) \ + ({ \ + int __v = (v); \ + \ + if (__v & SENSOR_SCALE_SIGN) \ + __v |= SENSOR_SCALE_EXTEND; \ + __v; \ + }) + +struct scmi_msg_sensor_axis_description_get { + __le32 id; + __le32 axis_desc_index; +}; + +struct scmi_msg_resp_sensor_axis_description { + __le32 num_axis_flags; +#define NUM_AXIS_RETURNED(x) FIELD_GET(GENMASK(5, 0), (x)) +#define NUM_AXIS_REMAINING(x) FIELD_GET(GENMASK(31, 26), (x)) + struct scmi_axis_descriptor { __le32 id; __le32 attributes_low; -#define SUPPORTS_ASYNC_READ(x) ((x) & BIT(31)) -#define NUM_TRIP_POINTS(x) ((x) & 0xff) __le32 attributes_high; -#define SENSOR_TYPE(x) ((x) & 0xff) -#define SENSOR_SCALE(x) (((x) >> 11) & 0x1f) -#define SENSOR_SCALE_SIGN BIT(4) -#define SENSOR_SCALE_EXTEND GENMASK(7, 5) -#define SENSOR_UPDATE_SCALE(x) (((x) >> 22) & 0x1f) -#define SENSOR_UPDATE_BASE(x) (((x) >> 27) & 0x1f) - u8 name[SCMI_MAX_STR_SIZE]; - } desc[0]; + u8 name[SCMI_MAX_STR_SIZE]; + __le32 resolution; + struct scmi_msg_resp_attrs attrs; + } desc[]; +}; + +/* Base scmi_axis_descriptor size excluding extended attrs after name */ +#define SCMI_MSG_RESP_AXIS_DESCR_BASE_SZ 28 + +struct scmi_msg_sensor_list_update_intervals { + __le32 id; + __le32 index; +}; + +struct scmi_msg_resp_sensor_list_update_intervals { + __le32 num_intervals_flags; +#define NUM_INTERVALS_RETURNED(x) FIELD_GET(GENMASK(11, 0), (x)) +#define SEGMENTED_INTVL_FORMAT(x) FIELD_GET(BIT(12), (x)) +#define NUM_INTERVALS_REMAINING(x) FIELD_GET(GENMASK(31, 16), (x)) + __le32 intervals[]; }; struct scmi_msg_sensor_trip_point_notify { @@ -114,6 +197,194 @@ static int scmi_sensor_attributes_get(const struct scmi_handle *handle, return ret; } +static inline void scmi_parse_range_attrs(struct scmi_range_attrs *out, + struct scmi_msg_resp_attrs *in) +{ + out->min_range = get_unaligned_le64((void *)&in->min_range_low); + out->max_range = get_unaligned_le64((void *)&in->max_range_low); +} + +static int scmi_sensor_update_intervals(const struct scmi_handle *handle, + struct scmi_sensor_info *s) +{ + int ret, cnt; + u32 desc_index = 0; + u16 num_returned, num_remaining; + struct scmi_xfer *ti; + struct scmi_msg_resp_sensor_list_update_intervals *buf; + struct scmi_msg_sensor_list_update_intervals *msg; + + ret = scmi_xfer_get_init(handle, SENSOR_LIST_UPDATE_INTERVALS, + SCMI_PROTOCOL_SENSOR, sizeof(*msg), 0, &ti); + if (ret) + return ret; + + buf = ti->rx.buf; + do { + u32 flags; + + msg = ti->tx.buf; + /* Set the number of sensors to be skipped/already read */ + msg->id = cpu_to_le32(s->id); + msg->index = cpu_to_le32(desc_index); + + ret = scmi_do_xfer(handle, ti); + if (ret) + break; + + flags = le32_to_cpu(buf->num_intervals_flags); + num_returned = NUM_INTERVALS_RETURNED(flags); + num_remaining = NUM_INTERVALS_REMAINING(flags); + + /* + * Max intervals is not declared previously anywhere so we + * assume it's returned+remaining. + */ + if (!s->intervals.count) { + s->intervals.segmented = SEGMENTED_INTVL_FORMAT(flags); + s->intervals.count = num_returned + num_remaining; + /* segmented intervals are reported in one triplet */ + if (s->intervals.segmented && + (num_remaining || num_returned != 3)) { + dev_err(handle->dev, + "Sensor ID:%d advertises an invalid segmented interval (%d)\n", + s->id, s->intervals.count); + s->intervals.segmented = false; + s->intervals.count = 0; + ret = -EINVAL; + break; + } + /* Direct allocation when exceeding pre-allocated */ + if (s->intervals.count >= SCMI_MAX_PREALLOC_POOL) { + s->intervals.desc = + devm_kcalloc(handle->dev, + s->intervals.count, + sizeof(*s->intervals.desc), + GFP_KERNEL); + if (!s->intervals.desc) { + s->intervals.segmented = false; + s->intervals.count = 0; + ret = -ENOMEM; + break; + } + } + } else if (desc_index + num_returned > s->intervals.count) { + dev_err(handle->dev, + "No. of update intervals can't exceed %d\n", + s->intervals.count); + ret = -EINVAL; + break; + } + + for (cnt = 0; cnt < num_returned; cnt++) + s->intervals.desc[desc_index + cnt] = + le32_to_cpu(buf->intervals[cnt]); + + desc_index += num_returned; + + scmi_reset_rx_to_maxsz(handle, ti); + /* + * check for both returned and remaining to avoid infinite + * loop due to buggy firmware + */ + } while (num_returned && num_remaining); + + scmi_xfer_put(handle, ti); + return ret; +} + +static int scmi_sensor_axis_description(const struct scmi_handle *handle, + struct scmi_sensor_info *s) +{ + int ret, cnt; + u32 desc_index = 0; + u16 num_returned, num_remaining; + struct scmi_xfer *te; + struct scmi_msg_resp_sensor_axis_description *buf; + struct scmi_msg_sensor_axis_description_get *msg; + + s->axis = devm_kcalloc(handle->dev, s->num_axis, + sizeof(*s->axis), GFP_KERNEL); + if (!s->axis) + return -ENOMEM; + + ret = scmi_xfer_get_init(handle, SENSOR_AXIS_DESCRIPTION_GET, + SCMI_PROTOCOL_SENSOR, sizeof(*msg), 0, &te); + if (ret) + return ret; + + buf = te->rx.buf; + do { + u32 flags; + struct scmi_axis_descriptor *adesc; + + msg = te->tx.buf; + /* Set the number of sensors to be skipped/already read */ + msg->id = cpu_to_le32(s->id); + msg->axis_desc_index = cpu_to_le32(desc_index); + + ret = scmi_do_xfer(handle, te); + if (ret) + break; + + flags = le32_to_cpu(buf->num_axis_flags); + num_returned = NUM_AXIS_RETURNED(flags); + num_remaining = NUM_AXIS_REMAINING(flags); + + if (desc_index + num_returned > s->num_axis) { + dev_err(handle->dev, "No. of axis can't exceed %d\n", + s->num_axis); + break; + } + + adesc = &buf->desc[0]; + for (cnt = 0; cnt < num_returned; cnt++) { + u32 attrh, attrl; + struct scmi_sensor_axis_info *a; + size_t dsize = SCMI_MSG_RESP_AXIS_DESCR_BASE_SZ; + + attrl = le32_to_cpu(adesc->attributes_low); + + a = &s->axis[desc_index + cnt]; + + a->id = le32_to_cpu(adesc->id); + a->extended_attrs = SUPPORTS_EXTEND_ATTRS(attrl); + + attrh = le32_to_cpu(adesc->attributes_high); + a->scale = S32_EXT(SENSOR_SCALE(attrh)); + a->type = SENSOR_TYPE(attrh); + strlcpy(a->name, adesc->name, SCMI_MAX_STR_SIZE); + + if (a->extended_attrs) { + unsigned int ares = + le32_to_cpu(adesc->resolution); + + a->resolution = SENSOR_RES(ares); + a->exponent = + S32_EXT(SENSOR_RES_EXP(ares)); + dsize += sizeof(adesc->resolution); + + scmi_parse_range_attrs(&a->attrs, + &adesc->attrs); + dsize += sizeof(adesc->attrs); + } + + adesc = (typeof(adesc))((u8 *)adesc + dsize); + } + + desc_index += num_returned; + + scmi_reset_rx_to_maxsz(handle, te); + /* + * check for both returned and remaining to avoid infinite + * loop due to buggy firmware + */ + } while (num_returned && num_remaining); + + scmi_xfer_put(handle, te); + return ret; +} + static int scmi_sensor_description_get(const struct scmi_handle *handle, struct sensors_info *si) { @@ -131,9 +402,10 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle, buf = t->rx.buf; do { + struct scmi_sensor_descriptor *sdesc; + /* Set the number of sensors to be skipped/already read */ put_unaligned_le32(desc_index, t->tx.buf); - ret = scmi_do_xfer(handle, t); if (ret) break; @@ -147,22 +419,97 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle, break; } + sdesc = &buf->desc[0]; for (cnt = 0; cnt < num_returned; cnt++) { u32 attrh, attrl; struct scmi_sensor_info *s; + size_t dsize = SCMI_MSG_RESP_SENS_DESCR_BASE_SZ; - attrl = le32_to_cpu(buf->desc[cnt].attributes_low); - attrh = le32_to_cpu(buf->desc[cnt].attributes_high); s = &si->sensors[desc_index + cnt]; - s->id = le32_to_cpu(buf->desc[cnt].id); - s->type = SENSOR_TYPE(attrh); - s->scale = SENSOR_SCALE(attrh); - /* Sign extend to a full s8 */ - if (s->scale & SENSOR_SCALE_SIGN) - s->scale |= SENSOR_SCALE_EXTEND; + s->id = le32_to_cpu(sdesc->id); + + attrl = le32_to_cpu(sdesc->attributes_low); + /* common bitfields parsing */ s->async = SUPPORTS_ASYNC_READ(attrl); s->num_trip_points = NUM_TRIP_POINTS(attrl); - strlcpy(s->name, buf->desc[cnt].name, SCMI_MAX_STR_SIZE); + /** + * only SCMIv3.0 specific bitfield below. + * Such bitfields are assumed to be zeroed on non + * relevant fw versions...assuming fw not buggy ! + */ + s->update = SUPPORTS_UPDATE_NOTIFY(attrl); + s->timestamped = SUPPORTS_TIMESTAMP(attrl); + if (s->timestamped) + s->tstamp_scale = + S32_EXT(SENSOR_TSTAMP_EXP(attrl)); + s->extended_scalar_attrs = + SUPPORTS_EXTEND_ATTRS(attrl); + + attrh = le32_to_cpu(sdesc->attributes_high); + /* common bitfields parsing */ + s->scale = S32_EXT(SENSOR_SCALE(attrh)); + s->type = SENSOR_TYPE(attrh); + /* Use pre-allocated pool wherever possible */ + s->intervals.desc = s->intervals.prealloc_pool; + if (si->version == SCMIv2_SENSOR_PROTOCOL) { + s->intervals.segmented = false; + s->intervals.count = 1; + /* + * Convert SCMIv2.0 update interval format to + * SCMIv3.0 to be used as the common exposed + * descriptor, accessible via common macros. + */ + s->intervals.desc[0] = + (SENSOR_UPDATE_BASE(attrh) << 5) | + SENSOR_UPDATE_SCALE(attrh); + } else { + /* + * From SCMIv3.0 update intervals are retrieved + * via a dedicated (optional) command. + * Since the command is optional, on error carry + * on without any update interval. + */ + if (scmi_sensor_update_intervals(handle, s)) + dev_dbg(handle->dev, + "Update Intervals not available for sensor ID:%d\n", + s->id); + } + /** + * only > SCMIv2.0 specific bitfield below. + * Such bitfields are assumed to be zeroed on non + * relevant fw versions...assuming fw not buggy ! + */ + s->num_axis = min_t(unsigned int, + SUPPORTS_AXIS(attrh) ? + SENSOR_AXIS_NUMBER(attrh) : 0, + SCMI_MAX_NUM_SENSOR_AXIS); + strlcpy(s->name, sdesc->name, SCMI_MAX_STR_SIZE); + + if (s->extended_scalar_attrs) { + s->sensor_power = le32_to_cpu(sdesc->power); + dsize += sizeof(sdesc->power); + /* Only for sensors reporting scalar values */ + if (s->num_axis == 0) { + unsigned int sres = + le32_to_cpu(sdesc->resolution); + + s->resolution = SENSOR_RES(sres); + s->exponent = + S32_EXT(SENSOR_RES_EXP(sres)); + dsize += sizeof(sdesc->resolution); + + scmi_parse_range_attrs(&s->scalar_attrs, + &sdesc->scalar_attrs); + dsize += sizeof(sdesc->scalar_attrs); + } + } + if (s->num_axis > 0) { + ret = scmi_sensor_axis_description(handle, s); + if (ret) + goto out; + } + + sdesc = (typeof(sdesc))((u8 *)sdesc + dsize); } desc_index += num_returned; @@ -174,6 +521,7 @@ static int scmi_sensor_description_get(const struct scmi_handle *handle, */ } while (num_returned && num_remaining); +out: scmi_xfer_put(handle, t); return ret; } diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 13d75956aa91..0792b0be25a3 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -8,6 +8,7 @@ #ifndef _LINUX_SCMI_PROTOCOL_H #define _LINUX_SCMI_PROTOCOL_H +#include #include #include #include @@ -148,13 +149,135 @@ struct scmi_power_ops { u32 *state); }; +/** + * scmi_range_attrs - specifies a sensor or axis values' range + * @min_range: The minimum value which can be represented by the sensor/axis. + * @max_range: The maximum value which can be represented by the sensor/axis. + */ +struct scmi_range_attrs { + long long min_range; + long long max_range; +}; + +/** + * scmi_sensor_axis_info - describes one sensor axes + * @id: The axes ID. + * @type: Axes type. Chosen amongst one of @enum scmi_sensor_class. + * @scale: Power-of-10 multiplier applied to the axis unit. + * @name: NULL-terminated string representing axes name as advertised by + * SCMI platform. + * @extended_attrs: Flag to indicate the presence of additional extended + * attributes for this axes. + * @resolution: Extended attribute representing the resolution of the axes. + * Set to 0 if not reported by this axes. + * @exponent: Extended attribute representing the power-of-10 multiplier that + * is applied to the resolution field. Set to 0 if not reported by + * this axes. + * @attrs: Extended attributes representing minimum and maximum values + * measurable by this axes. Set to 0 if not reported by this sensor. + */ +struct scmi_sensor_axis_info { + unsigned int id; + unsigned int type; + int scale; + char name[SCMI_MAX_STR_SIZE]; + bool extended_attrs; + unsigned int resolution; + int exponent; + struct scmi_range_attrs attrs; +}; + +/** + * scmi_sensor_intervals_info - describes number and type of available update + * intervals + * @segmented: Flag for segmented intervals' representation. When True there + * will be exactly 3 intervals in @desc, with each entry + * representing a member of a segment in this order: + * {lowest update interval, highest update interval, step size} + * @count: Number of intervals described in @desc. + * @desc: Array of @count interval descriptor bitmask represented as detailed in + * the SCMI specification: it can be accessed using the accompanying + * macros. + * @prealloc_pool: A minimal preallocated pool of desc entries used to avoid + * lesser-than-64-bytes dynamic allocation for small @count + * values. + */ +struct scmi_sensor_intervals_info { + bool segmented; + unsigned int count; +#define SCMI_SENS_INTVL_SEGMENT_LOW 0 +#define SCMI_SENS_INTVL_SEGMENT_HIGH 1 +#define SCMI_SENS_INTVL_SEGMENT_STEP 2 + unsigned int *desc; +#define SCMI_SENS_INTVL_GET_SECS(x) FIELD_GET(GENMASK(20, 5), (x)) +#define SCMI_SENS_INTVL_GET_EXP(x) \ + ({ \ + int __signed_exp = FIELD_GET(GENMASK(4, 0), (x)); \ + \ + if (__signed_exp & BIT(4)) \ + __signed_exp |= GENMASK(31, 5); \ + __signed_exp; \ + }) +#define SCMI_MAX_PREALLOC_POOL 16 + unsigned int prealloc_pool[SCMI_MAX_PREALLOC_POOL]; +}; + +/** + * struct scmi_sensor_info - represents information related to one of the + * available sensors. + * @id: Sensor ID. + * @type: Sensor type. Chosen amongst one of @enum scmi_sensor_class. + * @scale: Power-of-10 multiplier applied to the sensor unit. + * @num_trip_points: Number of maximum configurable trip points. + * @async: Flag for asynchronous read support. + * @update: Flag for continuouos update notification support. + * @timestamped: Flag for timestamped read support. + * @tstamp_scale: Power-of-10 multiplier applied to the sensor timestamps to + * represent it in seconds. + * @num_axis: Number of supported axis if any. Reported as 0 for scalar sensors. + * @axis: Pointer to an array of @num_axis descriptors. + * @intervals: Descriptor of available update intervals. + * @sensor_config: A bitmask reporting the current sensor configuration as + * detailed in the SCMI specification: it can accessed and + * modified through the accompanying macros. + * @name: NULL-terminated string representing sensor name as advertised by + * SCMI platform. + * @extended_scalar_attrs: Flag to indicate the presence of additional extended + * attributes for this sensor. + * @sensor_power: Extended attribute representing the average power + * consumed by the sensor in microwatts (uW) when it is active. + * Reported here only for scalar sensors. + * Set to 0 if not reported by this sensor. + * @resolution: Extended attribute representing the resolution of the sensor. + * Reported here only for scalar sensors. + * Set to 0 if not reported by this sensor. + * @exponent: Extended attribute representing the power-of-10 multiplier that is + * applied to the resolution field. + * Reported here only for scalar sensors. + * Set to 0 if not reported by this sensor. + * @scalar_attrs: Extended attributes representing minimum and maximum + * measurable values by this sensor. + * Reported here only for scalar sensors. + * Set to 0 if not reported by this sensor. + */ struct scmi_sensor_info { - u32 id; - u8 type; - s8 scale; - u8 num_trip_points; + unsigned int id; + unsigned int type; + int scale; + unsigned int num_trip_points; bool async; + bool update; + bool timestamped; + int tstamp_scale; + unsigned int num_axis; + struct scmi_sensor_axis_info *axis; + struct scmi_sensor_intervals_info intervals; char name[SCMI_MAX_STR_SIZE]; + bool extended_scalar_attrs; + unsigned int sensor_power; + unsigned int resolution; + int exponent; + struct scmi_range_attrs scalar_attrs; }; /* @@ -249,6 +372,14 @@ enum scmi_sensor_class { SQ_FEET = 0x54, SQ_CM = 0x55, SQ_METERS = 0x56, + RADIANS_SEC = 0x57, + BPM = 0x58, + METERS_SEC_SQUARED = 0x59, + METERS_SEC = 0x5A, + CUBIC_METERS_SEC = 0x5B, + MM_MERCURY = 0x5C, + RADIANS_SEC_SQUARED = 0x5D, + OEM_UNIT = 0xFF }; /** -- cgit v1.2.3 From ec8684847d8062496c4619bc3fcff31c19d56847 Mon Sep 17 00:00:00 2001 From: Zhang Qilong Date: Sat, 21 Nov 2020 19:22:00 -0800 Subject: soc: ti: knav_qmss: fix reference leak in knav_queue_probe pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to pm_runtime_put_noidle will result in reference leak in knav_queue_probe, so we should fix it. Fixes: 41f93af900a20 ("soc: ti: add Keystone Navigator QMSS driver") Signed-off-by: Zhang Qilong Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/knav_qmss_queue.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index a460f201bf8e..54afa8f7f408 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -1784,6 +1784,7 @@ static int knav_queue_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); ret = pm_runtime_get_sync(&pdev->dev); if (ret < 0) { + pm_runtime_put_noidle(&pdev->dev); dev_err(dev, "Failed to enable QMSS\n"); return ret; } -- cgit v1.2.3 From fd79aebe5f7cc0bdc9656ddf1a52f04da9480cd7 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Sat, 21 Nov 2020 19:22:00 -0800 Subject: soc: ti: omap-prm: Do not check rstst bit on deassert if already deasserted If a rstctrl reset bit is already deasserted, we can just bail out early not wait for rstst to clear. Otherwise we can have deassert fail for already deasserted resets. Fixes: c5117a78dd88 ("soc: ti: omap-prm: poll for reset complete during de-assert") Signed-off-by: Tony Lindgren Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/omap_prm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 980b04c38fd9..4d41dc3cdce1 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -484,6 +484,10 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); int ret = 0; + /* Nothing to do if the reset is already deasserted */ + if (!omap_reset_status(rcdev, id)) + return 0; + has_rstst = reset->prm->data->rstst || (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); -- cgit v1.2.3 From e72501099c4c8308aa5f1a7eed92a0839ab0cbbd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 21 Nov 2020 19:22:00 -0800 Subject: soc: ti: knav_qmss_queue: Remove set but unchecked variable 'ret' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following W=1 kernel build warning(s): drivers/soc/ti/knav_qmss_queue.c: In function ‘knav_setup_queue_pools’: drivers/soc/ti/knav_qmss_queue.c:1310:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] Cc: Santosh Shilimkar Cc: Sandeep Nair Cc: Cyril Chemparathy Signed-off-by: Lee Jones Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/knav_qmss_queue.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index 54afa8f7f408..eb4cca430038 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -1307,12 +1307,11 @@ static int knav_setup_queue_pools(struct knav_device *kdev, struct device_node *queue_pools) { struct device_node *type, *range; - int ret; for_each_child_of_node(queue_pools, type) { for_each_child_of_node(type, range) { - ret = knav_setup_queue_range(kdev, range); /* return value ignored, we init the rest... */ + knav_setup_queue_range(kdev, range); } } -- cgit v1.2.3 From e8ebf411966f65d74693d21bd7b2ea7554a36b19 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 21 Nov 2020 19:22:00 -0800 Subject: soc: ti: knav_qmss_queue: Fix a whole host of function documentation issues Fixes the following W=1 kernel build warning(s): drivers/soc/ti/knav_qmss_queue.c:528: warning: Function parameter or member 'flags' not described in 'knav_queue_open' drivers/soc/ti/knav_qmss_queue.c:528: warning: Function parameter or member 'id' not described in 'knav_queue_open' drivers/soc/ti/knav_qmss_queue.c:528: warning: Function parameter or member 'name' not described in 'knav_queue_open' drivers/soc/ti/knav_qmss_queue.c:551: warning: Excess function parameter 'qh' description in 'knav_queue_close' drivers/soc/ti/knav_qmss_queue.c:551: warning: Function parameter or member 'qhandle' not described in 'knav_queue_close' drivers/soc/ti/knav_qmss_queue.c:583: warning: Excess function parameter 'qh' description in 'knav_queue_device_control' drivers/soc/ti/knav_qmss_queue.c:583: warning: Function parameter or member 'arg' not described in 'knav_queue_device_control' drivers/soc/ti/knav_qmss_queue.c:583: warning: Function parameter or member 'cmd' not described in 'knav_queue_device_control' drivers/soc/ti/knav_qmss_queue.c:583: warning: Function parameter or member 'qhandle' not described in 'knav_queue_device_control' drivers/soc/ti/knav_qmss_queue.c:635: warning: Excess function parameter 'data' description in 'knav_queue_push' drivers/soc/ti/knav_qmss_queue.c:635: warning: Excess function parameter 'qh' description in 'knav_queue_push' drivers/soc/ti/knav_qmss_queue.c:635: warning: Function parameter or member 'dma' not described in 'knav_queue_push' drivers/soc/ti/knav_qmss_queue.c:635: warning: Function parameter or member 'flags' not described in 'knav_queue_push' drivers/soc/ti/knav_qmss_queue.c:635: warning: Function parameter or member 'qhandle' not described in 'knav_queue_push' drivers/soc/ti/knav_qmss_queue.c:635: warning: Function parameter or member 'size' not described in 'knav_queue_push' drivers/soc/ti/knav_qmss_queue.c:655: warning: Excess function parameter 'qh' description in 'knav_queue_pop' drivers/soc/ti/knav_qmss_queue.c:655: warning: Function parameter or member 'qhandle' not described in 'knav_queue_pop' drivers/soc/ti/knav_qmss_queue.c:655: warning: Function parameter or member 'size' not described in 'knav_queue_pop' drivers/soc/ti/knav_qmss_queue.c:759: warning: Function parameter or member 'name' not described in 'knav_pool_create' drivers/soc/ti/knav_qmss_queue.c:759: warning: Function parameter or member 'num_desc' not described in 'knav_pool_create' drivers/soc/ti/knav_qmss_queue.c:759: warning: Function parameter or member 'region_id' not described in 'knav_pool_create' drivers/soc/ti/knav_qmss_queue.c:862: warning: Excess function parameter 'pool' description in 'knav_pool_destroy' drivers/soc/ti/knav_qmss_queue.c:862: warning: Function parameter or member 'ph' not described in 'knav_pool_destroy' drivers/soc/ti/knav_qmss_queue.c:892: warning: Excess function parameter 'pool' description in 'knav_pool_desc_get' drivers/soc/ti/knav_qmss_queue.c:892: warning: Function parameter or member 'ph' not described in 'knav_pool_desc_get' drivers/soc/ti/knav_qmss_queue.c:911: warning: Excess function parameter 'pool' description in 'knav_pool_desc_put' drivers/soc/ti/knav_qmss_queue.c:911: warning: Function parameter or member 'desc' not described in 'knav_pool_desc_put' drivers/soc/ti/knav_qmss_queue.c:911: warning: Function parameter or member 'ph' not described in 'knav_pool_desc_put' drivers/soc/ti/knav_qmss_queue.c:931: warning: Excess function parameter 'pool' description in 'knav_pool_desc_map' drivers/soc/ti/knav_qmss_queue.c:931: warning: Function parameter or member 'desc' not described in 'knav_pool_desc_map' drivers/soc/ti/knav_qmss_queue.c:931: warning: Function parameter or member 'dma' not described in 'knav_pool_desc_map' drivers/soc/ti/knav_qmss_queue.c:931: warning: Function parameter or member 'dma_sz' not described in 'knav_pool_desc_map' drivers/soc/ti/knav_qmss_queue.c:931: warning: Function parameter or member 'ph' not described in 'knav_pool_desc_map' drivers/soc/ti/knav_qmss_queue.c:931: warning: Function parameter or member 'size' not described in 'knav_pool_desc_map' drivers/soc/ti/knav_qmss_queue.c:956: warning: Excess function parameter 'pool' description in 'knav_pool_desc_unmap' drivers/soc/ti/knav_qmss_queue.c:956: warning: Function parameter or member 'dma' not described in 'knav_pool_desc_unmap' drivers/soc/ti/knav_qmss_queue.c:956: warning: Function parameter or member 'dma_sz' not described in 'knav_pool_desc_unmap' drivers/soc/ti/knav_qmss_queue.c:956: warning: Function parameter or member 'ph' not described in 'knav_pool_desc_unmap' drivers/soc/ti/knav_qmss_queue.c:975: warning: Excess function parameter 'pool' description in 'knav_pool_count' drivers/soc/ti/knav_qmss_queue.c:975: warning: Function parameter or member 'ph' not described in 'knav_pool_count' Cc: Santosh Shilimkar Cc: Sandeep Nair Cc: Cyril Chemparathy Signed-off-by: Lee Jones Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/knav_qmss_queue.c | 59 ++++++++++++++++++++-------------------- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index eb4cca430038..490423ecdcdd 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -79,7 +79,7 @@ EXPORT_SYMBOL_GPL(knav_qmss_device_ready); /** * knav_queue_notify: qmss queue notfier call * - * @inst: qmss queue instance like accumulator + * @inst: - qmss queue instance like accumulator */ void knav_queue_notify(struct knav_queue_inst *inst) { @@ -511,10 +511,10 @@ static int knav_queue_flush(struct knav_queue *qh) /** * knav_queue_open() - open a hardware queue - * @name - name to give the queue handle - * @id - desired queue number if any or specifes the type + * @name: - name to give the queue handle + * @id: - desired queue number if any or specifes the type * of queue - * @flags - the following flags are applicable to queues: + * @flags: - the following flags are applicable to queues: * KNAV_QUEUE_SHARED - allow the queue to be shared. Queues are * exclusive by default. * Subsequent attempts to open a shared queue should @@ -545,7 +545,7 @@ EXPORT_SYMBOL_GPL(knav_queue_open); /** * knav_queue_close() - close a hardware queue handle - * @qh - handle to close + * @qhandle: - handle to close */ void knav_queue_close(void *qhandle) { @@ -572,9 +572,9 @@ EXPORT_SYMBOL_GPL(knav_queue_close); /** * knav_queue_device_control() - Perform control operations on a queue - * @qh - queue handle - * @cmd - control commands - * @arg - command argument + * @qhandle: - queue handle + * @cmd: - control commands + * @arg: - command argument * * Returns 0 on success, errno otherwise. */ @@ -623,10 +623,10 @@ EXPORT_SYMBOL_GPL(knav_queue_device_control); /** * knav_queue_push() - push data (or descriptor) to the tail of a queue - * @qh - hardware queue handle - * @data - data to push - * @size - size of data to push - * @flags - can be used to pass additional information + * @qhandle: - hardware queue handle + * @dma: - DMA data to push + * @size: - size of data to push + * @flags: - can be used to pass additional information * * Returns 0 on success, errno otherwise. */ @@ -646,8 +646,8 @@ EXPORT_SYMBOL_GPL(knav_queue_push); /** * knav_queue_pop() - pop data (or descriptor) from the head of a queue - * @qh - hardware queue handle - * @size - (optional) size of the data pop'ed. + * @qhandle: - hardware queue handle + * @size: - (optional) size of the data pop'ed. * * Returns a DMA address on success, 0 on failure. */ @@ -746,9 +746,9 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_dma_to_virt); /** * knav_pool_create() - Create a pool of descriptors - * @name - name to give the pool handle - * @num_desc - numbers of descriptors in the pool - * @region_id - QMSS region id from which the descriptors are to be + * @name: - name to give the pool handle + * @num_desc: - numbers of descriptors in the pool + * @region_id: - QMSS region id from which the descriptors are to be * allocated. * * Returns a pool handle on success. @@ -856,7 +856,7 @@ EXPORT_SYMBOL_GPL(knav_pool_create); /** * knav_pool_destroy() - Free a pool of descriptors - * @pool - pool handle + * @ph: - pool handle */ void knav_pool_destroy(void *ph) { @@ -884,7 +884,7 @@ EXPORT_SYMBOL_GPL(knav_pool_destroy); /** * knav_pool_desc_get() - Get a descriptor from the pool - * @pool - pool handle + * @ph: - pool handle * * Returns descriptor from the pool. */ @@ -905,7 +905,8 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_get); /** * knav_pool_desc_put() - return a descriptor to the pool - * @pool - pool handle + * @ph: - pool handle + * @desc: - virtual address */ void knav_pool_desc_put(void *ph, void *desc) { @@ -918,11 +919,11 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_put); /** * knav_pool_desc_map() - Map descriptor for DMA transfer - * @pool - pool handle - * @desc - address of descriptor to map - * @size - size of descriptor to map - * @dma - DMA address return pointer - * @dma_sz - adjusted return pointer + * @ph: - pool handle + * @desc: - address of descriptor to map + * @size: - size of descriptor to map + * @dma: - DMA address return pointer + * @dma_sz: - adjusted return pointer * * Returns 0 on success, errno otherwise. */ @@ -945,9 +946,9 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_map); /** * knav_pool_desc_unmap() - Unmap descriptor after DMA transfer - * @pool - pool handle - * @dma - DMA address of descriptor to unmap - * @dma_sz - size of descriptor to unmap + * @ph: - pool handle + * @dma: - DMA address of descriptor to unmap + * @dma_sz: - size of descriptor to unmap * * Returns descriptor address on success, Use IS_ERR_OR_NULL() to identify * error values on return. @@ -968,7 +969,7 @@ EXPORT_SYMBOL_GPL(knav_pool_desc_unmap); /** * knav_pool_count() - Get the number of descriptors in pool. - * @pool - pool handle + * @ph: - pool handle * Returns number of elements in the pool. */ int knav_pool_count(void *ph) -- cgit v1.2.3 From ed93a9e2a1a8448597b4ed4f28b5b7048d4e09e8 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 21 Nov 2020 19:22:00 -0800 Subject: soc: ti: knav_dma: Fix a kernel function doc formatting issue Fixes the following W=1 kernel build warning(s): drivers/soc/ti/knav_dma.c:507: warning: Function parameter or member 'channel' not described in 'knav_dma_close_channel' Cc: Santosh Shilimkar Cc: Sandeep Nair Cc: Cyril Chemparathy Signed-off-by: Lee Jones Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/knav_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/ti/knav_dma.c b/drivers/soc/ti/knav_dma.c index 8c863ecb1c60..b2d63d8854d6 100644 --- a/drivers/soc/ti/knav_dma.c +++ b/drivers/soc/ti/knav_dma.c @@ -500,7 +500,7 @@ EXPORT_SYMBOL_GPL(knav_dma_open_channel); /** * knav_dma_close_channel() - Destroy a dma channel * - * channel: dma channel handle + * @channel: dma channel handle * */ void knav_dma_close_channel(void *channel) -- cgit v1.2.3 From edac869ed010814d56f766745c64476d5a96bbdd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 21 Nov 2020 19:22:01 -0800 Subject: soc: ti: pm33xx: Remove set but unused variable 'ret' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following W=1 kernel build warning(s): drivers/soc/ti/pm33xx.c: In function ‘am33xx_do_sram_idle’: drivers/soc/ti/pm33xx.c:138:6: warning: variable ‘ret’ set but not used [-Wunused-but-set-variable] Cc: Santosh Shilimkar Signed-off-by: Lee Jones Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/pm33xx.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/ti/pm33xx.c b/drivers/soc/ti/pm33xx.c index d2f5e7001a93..9c0670ab6be6 100644 --- a/drivers/soc/ti/pm33xx.c +++ b/drivers/soc/ti/pm33xx.c @@ -135,13 +135,11 @@ static int am33xx_push_sram_idle(void) static int am33xx_do_sram_idle(u32 wfi_flags) { - int ret = 0; - if (!m3_ipc || !pm_ops) return 0; if (wfi_flags & WFI_FLAG_WAKE_M3) - ret = m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE); + m3_ipc->ops->prepare_low_power(m3_ipc, WKUP_M3_IDLE); return pm_ops->cpu_suspend(am33xx_do_wfi_sram, wfi_flags); } -- cgit v1.2.3 From 7be1c9c1c00c39ac04e182f3de613c6f30da3d9c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 21 Nov 2020 19:22:01 -0800 Subject: soc: ti: wkup_m3_ipc: Document 'm3_ipc' parameter throughout Fixes the following W=1 kernel build warning(s): drivers/soc/ti/wkup_m3_ipc.c:227: warning: Function parameter or member 'm3_ipc' not described in 'wkup_m3_set_mem_type' drivers/soc/ti/wkup_m3_ipc.c:236: warning: Function parameter or member 'm3_ipc' not described in 'wkup_m3_set_resume_address' drivers/soc/ti/wkup_m3_ipc.c:248: warning: Function parameter or member 'm3_ipc' not described in 'wkup_m3_request_pm_status' drivers/soc/ti/wkup_m3_ipc.c:268: warning: Function parameter or member 'm3_ipc' not described in 'wkup_m3_prepare_low_power' drivers/soc/ti/wkup_m3_ipc.c:322: warning: Function parameter or member 'm3_ipc' not described in 'wkup_m3_finish_low_power' drivers/soc/ti/wkup_m3_ipc.c:369: warning: Function parameter or member 'm3_ipc' not described in 'wkup_m3_set_rtc_only' drivers/soc/ti/wkup_m3_ipc.c:369: warning: Excess function parameter 'wkup_m3_wakeup' description in 'wkup_m3_set_rtc_only' Cc: Santosh Shilimkar Cc: Dave Gerlach Signed-off-by: Lee Jones Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/wkup_m3_ipc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/wkup_m3_ipc.c b/drivers/soc/ti/wkup_m3_ipc.c index e9ece45d7a33..c3e2161df732 100644 --- a/drivers/soc/ti/wkup_m3_ipc.c +++ b/drivers/soc/ti/wkup_m3_ipc.c @@ -218,6 +218,7 @@ static int wkup_m3_is_available(struct wkup_m3_ipc *m3_ipc) /* Public functions */ /** * wkup_m3_set_mem_type - Pass wkup_m3 which type of memory is in use + * @m3_ipc: Pointer to wkup_m3_ipc context * @mem_type: memory type value read directly from emif * * wkup_m3 must know what memory type is in use to properly suspend @@ -230,6 +231,7 @@ static void wkup_m3_set_mem_type(struct wkup_m3_ipc *m3_ipc, int mem_type) /** * wkup_m3_set_resume_address - Pass wkup_m3 resume address + * @m3_ipc: Pointer to wkup_m3_ipc context * @addr: Physical address from which resume code should execute */ static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr) @@ -239,6 +241,7 @@ static void wkup_m3_set_resume_address(struct wkup_m3_ipc *m3_ipc, void *addr) /** * wkup_m3_request_pm_status - Retrieve wkup_m3 status code after suspend + * @m3_ipc: Pointer to wkup_m3_ipc context * * Returns code representing the status of a low power mode transition. * 0 - Successful transition @@ -260,6 +263,7 @@ static int wkup_m3_request_pm_status(struct wkup_m3_ipc *m3_ipc) /** * wkup_m3_prepare_low_power - Request preparation for transition to * low power state + * @m3_ipc: Pointer to wkup_m3_ipc context * @state: A kernel suspend state to enter, either MEM or STANDBY * * Returns 0 if preparation was successful, otherwise returns error code @@ -315,6 +319,7 @@ static int wkup_m3_prepare_low_power(struct wkup_m3_ipc *m3_ipc, int state) /** * wkup_m3_finish_low_power - Return m3 to reset state + * @m3_ipc: Pointer to wkup_m3_ipc context * * Returns 0 if reset was successful, otherwise returns error code */ @@ -362,8 +367,7 @@ static const char *wkup_m3_request_wake_src(struct wkup_m3_ipc *m3_ipc) /** * wkup_m3_set_rtc_only - Set the rtc_only flag - * @wkup_m3_wakeup: struct wkup_m3_wakeup_src * gets assigned the - * wakeup src value + * @m3_ipc: Pointer to wkup_m3_ipc context */ static void wkup_m3_set_rtc_only(struct wkup_m3_ipc *m3_ipc) { -- cgit v1.2.3 From 50883affe17e11dab530c97b407652193e60471c Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Sat, 21 Nov 2020 19:22:01 -0800 Subject: soc: ti: k3-ringacc: Provide documentation for 'k3_ring's 'state' Fixes the following W=1 kernel build warning(s): drivers/soc/ti/k3-ringacc.c:163: warning: Function parameter or member 'state' not described in 'k3_ring' Cc: Santosh Shilimkar Signed-off-by: Lee Jones Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/k3-ringacc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 7fdb688452f7..119164abcb41 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -137,6 +137,7 @@ struct k3_ring_state { * @elm_size: Size of the ring element * @mode: Ring mode * @flags: flags + * @state: Ring state * @ring_id: Ring Id * @parent: Pointer on struct @k3_ringacc * @use_count: Use count for shared rings -- cgit v1.2.3 From e83b2358ab7ef0d39563b4e66233b356f99b7e77 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Sat, 21 Nov 2020 19:22:01 -0800 Subject: soc: ti: Kconfig: Drop ARM64 SoC specific configs With the integration of chip-id detection scheme in kernel[1], there is no specific need to maintain multitudes of SoC specific config options, discussed as per [2], we have deprecated the usage in other places for v5.10-rc1. Drop the configuration for the follow on kernel. [1] drivers/soc/ti/k3-socinfo.c commit 907a2b7e2fc7 ("soc: ti: add k3 platforms chipid module driver") Signed-off-by: Nishanth Menon Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/Kconfig | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index f5b82ffa637b..7e2fb1c16af1 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -1,22 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only -# 64-bit ARM SoCs from TI -if ARM64 - -if ARCH_K3 - -config ARCH_K3_AM6_SOC - bool "K3 AM6 SoC" - help - Enable support for TI's AM6 SoC Family support - -config ARCH_K3_J721E_SOC - bool "K3 J721E SoC" - help - Enable support for TI's J721E SoC Family support - -endif - -endif # # TI SOC drivers -- cgit v1.2.3 From 8465c7d1001a86e87f03124dc4a35760e731af62 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Sat, 21 Nov 2020 19:22:25 -0800 Subject: soc: ti: pruss: Remove wrong check against *get_match_data return value Since the of_device_get_match_data() doesn't return error code, remove wrong IS_ERR test. Proper check against NULL pointer is already done later before usage: if (data && data->...). Additionally, proceeding with empty device data is valid (e.g. in case of "ti,am3356-pruss"). Reported-by: Wei Yongjun Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/pruss.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index cc0b4ad7a3d3..5d6e7132a5c4 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -126,8 +126,6 @@ static int pruss_clk_init(struct pruss *pruss, struct device_node *cfg_node) int ret = 0; data = of_device_get_match_data(dev); - if (IS_ERR(data)) - return -ENODEV; clks_np = of_get_child_by_name(cfg_node, "clocks"); if (!clks_np) { @@ -175,10 +173,6 @@ static int pruss_probe(struct platform_device *pdev) const char *mem_names[PRUSS_MEM_MAX] = { "dram0", "dram1", "shrdram2" }; data = of_device_get_match_data(&pdev->dev); - if (IS_ERR(data)) { - dev_err(dev, "missing private data\n"); - return -ENODEV; - } ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32)); if (ret) { -- cgit v1.2.3 From b4fa73358c306d747a2200aec6f7acb97e5750e6 Mon Sep 17 00:00:00 2001 From: Zhang Qilong Date: Sat, 21 Nov 2020 19:22:37 -0800 Subject: soc: ti: Fix reference imbalance in knav_dma_probe The patch fix two reference leak. 1) pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to call put operation will result in reference leak. 2) The pm_runtime_enable will increase power disable depth. Thus a pairing decrement is needed on the error handling path to keep it balanced. We fix it by: 1) adding call pm_runtime_put_noidle or pm_runtime_put_sync in error handling. 2) adding pm_runtime_disable in error handling, to keep usage counter and disable depth balanced. Fixes: 88139ed030583 ("soc: ti: add Keystone Navigator DMA support") Signed-off-by: Zhang Qilong Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/knav_dma.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/soc/ti/knav_dma.c b/drivers/soc/ti/knav_dma.c index b2d63d8854d6..7b5cb5d48f7d 100644 --- a/drivers/soc/ti/knav_dma.c +++ b/drivers/soc/ti/knav_dma.c @@ -749,8 +749,9 @@ static int knav_dma_probe(struct platform_device *pdev) pm_runtime_enable(kdev->dev); ret = pm_runtime_get_sync(kdev->dev); if (ret < 0) { + pm_runtime_put_noidle(kdev->dev); dev_err(kdev->dev, "unable to enable pktdma, err %d\n", ret); - return ret; + goto err_pm_disable; } /* Initialise all packet dmas */ @@ -764,7 +765,8 @@ static int knav_dma_probe(struct platform_device *pdev) if (list_empty(&kdev->list)) { dev_err(dev, "no valid dma instance\n"); - return -ENODEV; + ret = -ENODEV; + goto err_put_sync; } debugfs_create_file("knav_dma", S_IFREG | S_IRUGO, NULL, NULL, @@ -772,6 +774,13 @@ static int knav_dma_probe(struct platform_device *pdev) device_ready = true; return ret; + +err_put_sync: + pm_runtime_put_sync(kdev->dev); +err_pm_disable: + pm_runtime_disable(kdev->dev); + + return ret; } static int knav_dma_remove(struct platform_device *pdev) -- cgit v1.2.3 From 4cba398f37f868f515ff12868418dc28574853a1 Mon Sep 17 00:00:00 2001 From: Zhihao Cheng Date: Sat, 21 Nov 2020 19:22:38 -0800 Subject: drivers: soc: ti: knav_qmss_queue: Fix error return code in knav_queue_probe Fix to return the error code from of_get_child_by_name() instaed of 0 in knav_queue_probe(). Fixes: 41f93af900a20d1a0a ("soc: ti: add Keystone Navigator QMSS driver") Reported-by: Hulk Robot Signed-off-by: Zhihao Cheng Signed-off-by: Santosh Shilimkar --- drivers/soc/ti/knav_qmss_queue.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/ti/knav_qmss_queue.c b/drivers/soc/ti/knav_qmss_queue.c index 490423ecdcdd..2e521f1eda96 100644 --- a/drivers/soc/ti/knav_qmss_queue.c +++ b/drivers/soc/ti/knav_qmss_queue.c @@ -1852,9 +1852,10 @@ static int knav_queue_probe(struct platform_device *pdev) if (ret) goto err; - regions = of_get_child_by_name(node, "descriptor-regions"); + regions = of_get_child_by_name(node, "descriptor-regions"); if (!regions) { dev_err(dev, "descriptor-regions not specified\n"); + ret = -ENODEV; goto err; } ret = knav_queue_setup_regions(kdev, regions); -- cgit v1.2.3 From c16756c1187034c759c17db5c56b5365618173ba Mon Sep 17 00:00:00 2001 From: Roja Rani Yarubandi Date: Fri, 30 Oct 2020 20:29:57 +0530 Subject: soc: qcom: geni: Remove "iova" check Remove "iova" check from geni_se_tx_dma_unprep and geni_se_rx_dma_unprep functions as checking with dma_mapping_error() is enough. Signed-off-by: Roja Rani Yarubandi Link: https://lore.kernel.org/r/20201030145959.505-2-rojay@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom-geni-se.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 9da904d137dc..f42954e2c98e 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -733,7 +733,7 @@ void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) { struct geni_wrapper *wrapper = se->wrapper; - if (iova && !dma_mapping_error(wrapper->dev, iova)) + if (!dma_mapping_error(wrapper->dev, iova)) dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); } EXPORT_SYMBOL(geni_se_tx_dma_unprep); @@ -750,7 +750,7 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len) { struct geni_wrapper *wrapper = se->wrapper; - if (iova && !dma_mapping_error(wrapper->dev, iova)) + if (!dma_mapping_error(wrapper->dev, iova)) dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); } EXPORT_SYMBOL(geni_se_rx_dma_unprep); -- cgit v1.2.3 From 903b08340b885689646713bc2ec5ae10c7dbe8db Mon Sep 17 00:00:00 2001 From: Vladimir Lypak Date: Sun, 4 Oct 2020 11:22:24 +0300 Subject: soc: qcom: socinfo: add soc ids for msm8953 variants Add SoC IDs for MSM8953, APQ8053, SDM(SDA)450, SDM(SDA)632. Signed-off-by: Vladimir Lypak Link: https://lore.kernel.org/r/20201004082223.324019-1-junak.pub@gmail.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index b44ede48decc..d21530d24253 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -218,13 +218,19 @@ static const struct soc_id soc_id[] = { { 251, "MSM8992" }, { 253, "APQ8094" }, { 291, "APQ8096" }, + { 293, "MSM8953" }, + { 304, "APQ8053" }, { 305, "MSM8996SG" }, { 310, "MSM8996AU" }, { 311, "APQ8096AU" }, { 312, "APQ8096SG" }, { 318, "SDM630" }, { 321, "SDM845" }, + { 338, "SDM450" }, { 341, "SDA845" }, + { 349, "SDM632" }, + { 350, "SDA632" }, + { 351, "SDA450" }, { 356, "SM8250" }, { 402, "IPQ6018" }, { 425, "SC7180" }, -- cgit v1.2.3 From a161ffe4b877721d8917e18e70461d255a090f19 Mon Sep 17 00:00:00 2001 From: Tom Rix Date: Wed, 19 Aug 2020 11:46:37 -0700 Subject: soc: qcom: initialize local variable clang static analysis reports this problem pdr_interface.c:596:6: warning: Branch condition evaluates to a garbage value if (!req.service_path[0]) ^~~~~~~~~~~~~~~~~~~~ This check that req.service_path was set in an earlier loop. However req is a stack variable and its initial value is undefined. So initialize req to 0. Fixes: fbe639b44a82 ("soc: qcom: Introduce Protection Domain Restart helpers") Reviewed-by: Sibi Sankar Signed-off-by: Tom Rix Link: https://lore.kernel.org/r/20200819184637.15648-1-trix@redhat.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pdr_interface.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c index 088dc99f77f3..f63135c09667 100644 --- a/drivers/soc/qcom/pdr_interface.c +++ b/drivers/soc/qcom/pdr_interface.c @@ -569,7 +569,7 @@ EXPORT_SYMBOL(pdr_add_lookup); int pdr_restart_pd(struct pdr_handle *pdr, struct pdr_service *pds) { struct servreg_restart_pd_resp resp; - struct servreg_restart_pd_req req; + struct servreg_restart_pd_req req = { 0 }; struct sockaddr_qrtr addr; struct pdr_service *tmp; struct qmi_txn txn; -- cgit v1.2.3 From d7971d57d2737002dc0ef2f9d9c9494184d41348 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Thu, 19 Nov 2020 17:49:03 +0000 Subject: hwmon: (scmi) Update hwmon internal scale data type Use an int to calculate scale values inside scmi_hwmon_scale() to match the updated scale data type in struct scmi_sensor_info. Link: https://lore.kernel.org/r/20201119174906.43862-4-cristian.marussi@arm.com Cc: linux-hwmon@vger.kernel.org Acked-by: Guenter Roeck Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- drivers/hwmon/scmi-hwmon.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/scmi-hwmon.c b/drivers/hwmon/scmi-hwmon.c index 09ce30cba54b..17d064e58938 100644 --- a/drivers/hwmon/scmi-hwmon.c +++ b/drivers/hwmon/scmi-hwmon.c @@ -30,7 +30,7 @@ static inline u64 __pow10(u8 x) static int scmi_hwmon_scale(const struct scmi_sensor_info *sensor, u64 *value) { - s8 scale = sensor->scale; + int scale = sensor->scale; u64 f; switch (sensor->type) { -- cgit v1.2.3 From e2083d36739168f7b612312160cf7bb45b251408 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Thu, 19 Nov 2020 17:49:04 +0000 Subject: firmware: arm_scmi: Add SCMI v3.0 sensors timestamped reads Add new .reading_get_timestamped() method to sensor_ops to support SCMI v3.0 timestamped reads. Link: https://lore.kernel.org/r/20201119174906.43862-5-cristian.marussi@arm.com Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/sensors.c | 127 ++++++++++++++++++++++++++++++++++-- include/linux/scmi_protocol.h | 22 +++++++ 2 files changed, 143 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c index a85827f60a02..2239af5f9e6e 100644 --- a/drivers/firmware/arm_scmi/sensors.c +++ b/drivers/firmware/arm_scmi/sensors.c @@ -155,6 +155,23 @@ struct scmi_msg_sensor_reading_get { #define SENSOR_READ_ASYNC BIT(0) }; +struct scmi_resp_sensor_reading_complete { + __le32 id; + __le64 readings; +}; + +struct scmi_sensor_reading_le { + __le32 sensor_value_low; + __le32 sensor_value_high; + __le32 timestamp_low; + __le32 timestamp_high; +}; + +struct scmi_resp_sensor_reading_complete_v3 { + __le32 id; + struct scmi_sensor_reading_le readings[]; +}; + struct scmi_sensor_trip_notify_payld { __le32 agent_id; __le32 sensor_id; @@ -575,6 +592,21 @@ scmi_sensor_trip_point_config(const struct scmi_handle *handle, u32 sensor_id, return ret; } +/** + * scmi_sensor_reading_get - Read scalar sensor value + * @handle: Platform handle + * @sensor_id: Sensor ID + * @value: The 64bit value sensor reading + * + * This function returns a single 64 bit reading value representing the sensor + * value; if the platform SCMI Protocol implementation and the sensor support + * multiple axis and timestamped-reads, this just returns the first axis while + * dropping the timestamp value. + * Use instead the @scmi_sensor_reading_get_timestamped to retrieve the array of + * timestamped multi-axis values. + * + * Return: 0 on Success + */ static int scmi_sensor_reading_get(const struct scmi_handle *handle, u32 sensor_id, u64 *value) { @@ -585,20 +617,24 @@ static int scmi_sensor_reading_get(const struct scmi_handle *handle, struct scmi_sensor_info *s = si->sensors + sensor_id; ret = scmi_xfer_get_init(handle, SENSOR_READING_GET, - SCMI_PROTOCOL_SENSOR, sizeof(*sensor), - sizeof(u64), &t); + SCMI_PROTOCOL_SENSOR, sizeof(*sensor), 0, &t); if (ret) return ret; sensor = t->tx.buf; sensor->id = cpu_to_le32(sensor_id); - if (s->async) { sensor->flags = cpu_to_le32(SENSOR_READ_ASYNC); ret = scmi_do_xfer_with_response(handle, t); - if (!ret) - *value = get_unaligned_le64((void *) - ((__le32 *)t->rx.buf + 1)); + if (!ret) { + struct scmi_resp_sensor_reading_complete *resp; + + resp = t->rx.buf; + if (le32_to_cpu(resp->id) == sensor_id) + *value = get_unaligned_le64(&resp->readings); + else + ret = -EPROTO; + } } else { sensor->flags = cpu_to_le32(0); ret = scmi_do_xfer(handle, t); @@ -610,6 +646,84 @@ static int scmi_sensor_reading_get(const struct scmi_handle *handle, return ret; } +static inline void +scmi_parse_sensor_readings(struct scmi_sensor_reading *out, + const struct scmi_sensor_reading_le *in) +{ + out->value = get_unaligned_le64((void *)&in->sensor_value_low); + out->timestamp = get_unaligned_le64((void *)&in->timestamp_low); +} + +/** + * scmi_sensor_reading_get_timestamped - Read multiple-axis timestamped values + * @handle: Platform handle + * @sensor_id: Sensor ID + * @count: The length of the provided @readings array + * @readings: An array of elements each representing a timestamped per-axis + * reading of type @struct scmi_sensor_reading. + * Returned readings are ordered as the @axis descriptors array + * included in @struct scmi_sensor_info and the max number of + * returned elements is min(@count, @num_axis); ideally the provided + * array should be of length @count equal to @num_axis. + * + * Return: 0 on Success + */ +static int +scmi_sensor_reading_get_timestamped(const struct scmi_handle *handle, + u32 sensor_id, u8 count, + struct scmi_sensor_reading *readings) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_sensor_reading_get *sensor; + struct sensors_info *si = handle->sensor_priv; + struct scmi_sensor_info *s = si->sensors + sensor_id; + + if (!count || !readings || + (!s->num_axis && count > 1) || (s->num_axis && count > s->num_axis)) + return -EINVAL; + + ret = scmi_xfer_get_init(handle, SENSOR_READING_GET, + SCMI_PROTOCOL_SENSOR, sizeof(*sensor), 0, &t); + if (ret) + return ret; + + sensor = t->tx.buf; + sensor->id = cpu_to_le32(sensor_id); + if (s->async) { + sensor->flags = cpu_to_le32(SENSOR_READ_ASYNC); + ret = scmi_do_xfer_with_response(handle, t); + if (!ret) { + int i; + struct scmi_resp_sensor_reading_complete_v3 *resp; + + resp = t->rx.buf; + /* Retrieve only the number of requested axis anyway */ + if (le32_to_cpu(resp->id) == sensor_id) + for (i = 0; i < count; i++) + scmi_parse_sensor_readings(&readings[i], + &resp->readings[i]); + else + ret = -EPROTO; + } + } else { + sensor->flags = cpu_to_le32(0); + ret = scmi_do_xfer(handle, t); + if (!ret) { + int i; + struct scmi_sensor_reading_le *resp_readings; + + resp_readings = t->rx.buf; + for (i = 0; i < count; i++) + scmi_parse_sensor_readings(&readings[i], + &resp_readings[i]); + } + } + + scmi_xfer_put(handle, t); + return ret; +} + static const struct scmi_sensor_info * scmi_sensor_info_get(const struct scmi_handle *handle, u32 sensor_id) { @@ -630,6 +744,7 @@ static const struct scmi_sensor_ops sensor_ops = { .info_get = scmi_sensor_info_get, .trip_point_config = scmi_sensor_trip_point_config, .reading_get = scmi_sensor_reading_get, + .reading_get_timestamped = scmi_sensor_reading_get_timestamped, }; static int scmi_sensor_set_notify_enabled(const struct scmi_handle *handle, diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 0792b0be25a3..0c52bf0cbee4 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -149,6 +149,20 @@ struct scmi_power_ops { u32 *state); }; +/** + * scmi_sensor_reading - represent a timestamped read + * + * Used by @reading_get_timestamped method. + * + * @value: The signed value sensor read. + * @timestamp: An unsigned timestamp for the sensor read, as provided by + * SCMI platform. Set to zero when not available. + */ +struct scmi_sensor_reading { + long long value; + unsigned long long timestamp; +}; + /** * scmi_range_attrs - specifies a sensor or axis values' range * @min_range: The minimum value which can be represented by the sensor/axis. @@ -390,6 +404,11 @@ enum scmi_sensor_class { * @info_get: get the information of the specified sensor * @trip_point_config: selects and configures a trip-point of interest * @reading_get: gets the current value of the sensor + * @reading_get_timestamped: gets the current value and timestamp, when + * available, of the sensor. (as of v3.0 spec) + * Supports multi-axis sensors for sensors which + * supports it and if the @reading array size of + * @count entry equals the sensor num_axis */ struct scmi_sensor_ops { int (*count_get)(const struct scmi_handle *handle); @@ -399,6 +418,9 @@ struct scmi_sensor_ops { u32 sensor_id, u8 trip_id, u64 trip_value); int (*reading_get)(const struct scmi_handle *handle, u32 sensor_id, u64 *value); + int (*reading_get_timestamped)(const struct scmi_handle *handle, + u32 sensor_id, u8 count, + struct scmi_sensor_reading *readings); }; /** -- cgit v1.2.3 From 7b83c5f41088987d04e24c3af0e1fb9f43b747b5 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Thu, 19 Nov 2020 17:49:05 +0000 Subject: firmware: arm_scmi: Add SCMI v3.0 sensor configuration support Add SCMI v3.0 sensor support for CONFIG_GET/CONFIG_SET commands. Link: https://lore.kernel.org/r/20201119174906.43862-6-cristian.marussi@arm.com Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/sensors.c | 63 +++++++++++++++++++++++++++++++++++++ include/linux/scmi_protocol.h | 37 ++++++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c index 2239af5f9e6e..10c271d430e7 100644 --- a/drivers/firmware/arm_scmi/sensors.c +++ b/drivers/firmware/arm_scmi/sensors.c @@ -23,6 +23,8 @@ enum scmi_sensor_protocol_cmd { SENSOR_READING_GET = 0x6, SENSOR_AXIS_DESCRIPTION_GET = 0x7, SENSOR_LIST_UPDATE_INTERVALS = 0x8, + SENSOR_CONFIG_GET = 0x9, + SENSOR_CONFIG_SET = 0xA, }; struct scmi_msg_resp_sensor_attributes { @@ -149,6 +151,11 @@ struct scmi_msg_set_sensor_trip_point { __le32 value_high; }; +struct scmi_msg_sensor_config_set { + __le32 id; + __le32 sensor_config; +}; + struct scmi_msg_sensor_reading_get { __le32 id; __le32 flags; @@ -592,6 +599,60 @@ scmi_sensor_trip_point_config(const struct scmi_handle *handle, u32 sensor_id, return ret; } +static int scmi_sensor_config_get(const struct scmi_handle *handle, + u32 sensor_id, u32 *sensor_config) +{ + int ret; + struct scmi_xfer *t; + + ret = scmi_xfer_get_init(handle, SENSOR_CONFIG_GET, + SCMI_PROTOCOL_SENSOR, sizeof(__le32), + sizeof(__le32), &t); + if (ret) + return ret; + + put_unaligned_le32(cpu_to_le32(sensor_id), t->tx.buf); + ret = scmi_do_xfer(handle, t); + if (!ret) { + struct sensors_info *si = handle->sensor_priv; + struct scmi_sensor_info *s = si->sensors + sensor_id; + + *sensor_config = get_unaligned_le64(t->rx.buf); + s->sensor_config = *sensor_config; + } + + scmi_xfer_put(handle, t); + return ret; +} + +static int scmi_sensor_config_set(const struct scmi_handle *handle, + u32 sensor_id, u32 sensor_config) +{ + int ret; + struct scmi_xfer *t; + struct scmi_msg_sensor_config_set *msg; + + ret = scmi_xfer_get_init(handle, SENSOR_CONFIG_SET, + SCMI_PROTOCOL_SENSOR, sizeof(*msg), 0, &t); + if (ret) + return ret; + + msg = t->tx.buf; + msg->id = cpu_to_le32(sensor_id); + msg->sensor_config = cpu_to_le32(sensor_config); + + ret = scmi_do_xfer(handle, t); + if (!ret) { + struct sensors_info *si = handle->sensor_priv; + struct scmi_sensor_info *s = si->sensors + sensor_id; + + s->sensor_config = sensor_config; + } + + scmi_xfer_put(handle, t); + return ret; +} + /** * scmi_sensor_reading_get - Read scalar sensor value * @handle: Platform handle @@ -745,6 +806,8 @@ static const struct scmi_sensor_ops sensor_ops = { .trip_point_config = scmi_sensor_trip_point_config, .reading_get = scmi_sensor_reading_get, .reading_get_timestamped = scmi_sensor_reading_get_timestamped, + .config_get = scmi_sensor_config_get, + .config_set = scmi_sensor_config_set, }; static int scmi_sensor_set_notify_enabled(const struct scmi_handle *handle, diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 0c52bf0cbee4..7e9e2cd3d46b 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -286,7 +286,38 @@ struct scmi_sensor_info { unsigned int num_axis; struct scmi_sensor_axis_info *axis; struct scmi_sensor_intervals_info intervals; + unsigned int sensor_config; +#define SCMI_SENS_CFG_UPDATE_SECS_MASK GENMASK(31, 16) +#define SCMI_SENS_CFG_GET_UPDATE_SECS(x) \ + FIELD_GET(SCMI_SENS_CFG_UPDATE_SECS_MASK, (x)) + +#define SCMI_SENS_CFG_UPDATE_EXP_MASK GENMASK(15, 11) +#define SCMI_SENS_CFG_GET_UPDATE_EXP(x) \ + ({ \ + int __signed_exp = \ + FIELD_GET(SCMI_SENS_CFG_UPDATE_EXP_MASK, (x)); \ + \ + if (__signed_exp & BIT(4)) \ + __signed_exp |= GENMASK(31, 5); \ + __signed_exp; \ + }) + +#define SCMI_SENS_CFG_ROUND_MASK GENMASK(10, 9) +#define SCMI_SENS_CFG_ROUND_AUTO 2 +#define SCMI_SENS_CFG_ROUND_UP 1 +#define SCMI_SENS_CFG_ROUND_DOWN 0 + +#define SCMI_SENS_CFG_TSTAMP_ENABLED_MASK BIT(1) +#define SCMI_SENS_CFG_TSTAMP_ENABLE 1 +#define SCMI_SENS_CFG_TSTAMP_DISABLE 0 +#define SCMI_SENS_CFG_IS_TSTAMP_ENABLED(x) \ + FIELD_GET(SCMI_SENS_CFG_TSTAMP_ENABLED_MASK, (x)) + +#define SCMI_SENS_CFG_SENSOR_ENABLED_MASK BIT(0) +#define SCMI_SENS_CFG_SENSOR_ENABLE 1 +#define SCMI_SENS_CFG_SENSOR_DISABLE 0 char name[SCMI_MAX_STR_SIZE]; +#define SCMI_SENS_CFG_IS_ENABLED(x) FIELD_GET(BIT(0), (x)) bool extended_scalar_attrs; unsigned int sensor_power; unsigned int resolution; @@ -409,6 +440,8 @@ enum scmi_sensor_class { * Supports multi-axis sensors for sensors which * supports it and if the @reading array size of * @count entry equals the sensor num_axis + * @config_get: Get sensor current configuration + * @config_set: Set sensor current configuration */ struct scmi_sensor_ops { int (*count_get)(const struct scmi_handle *handle); @@ -421,6 +454,10 @@ struct scmi_sensor_ops { int (*reading_get_timestamped)(const struct scmi_handle *handle, u32 sensor_id, u8 count, struct scmi_sensor_reading *readings); + int (*config_get)(const struct scmi_handle *handle, + u32 sensor_id, u32 *sensor_config); + int (*config_set)(const struct scmi_handle *handle, + u32 sensor_id, u32 sensor_config); }; /** -- cgit v1.2.3 From e3811190acf85c63518fbddaa28bcbfab2baa58d Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Thu, 19 Nov 2020 17:49:06 +0000 Subject: firmware: arm_scmi: Add SCMI v3.0 sensor notifications Add support for new SCMI v3.0 SENSOR_UPDATE notification. Link: https://lore.kernel.org/r/20201119174906.43862-7-cristian.marussi@arm.com Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/sensors.c | 124 ++++++++++++++++++++++++++++++------ include/linux/scmi_protocol.h | 9 +++ 2 files changed, 114 insertions(+), 19 deletions(-) diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c index 10c271d430e7..b3d7c08c09a0 100644 --- a/drivers/firmware/arm_scmi/sensors.c +++ b/drivers/firmware/arm_scmi/sensors.c @@ -25,6 +25,7 @@ enum scmi_sensor_protocol_cmd { SENSOR_LIST_UPDATE_INTERVALS = 0x8, SENSOR_CONFIG_GET = 0x9, SENSOR_CONFIG_SET = 0xA, + SENSOR_CONTINUOUS_UPDATE_NOTIFY = 0xB, }; struct scmi_msg_resp_sensor_attributes { @@ -132,10 +133,10 @@ struct scmi_msg_resp_sensor_list_update_intervals { __le32 intervals[]; }; -struct scmi_msg_sensor_trip_point_notify { +struct scmi_msg_sensor_request_notify { __le32 id; __le32 event_control; -#define SENSOR_TP_NOTIFY_ALL BIT(0) +#define SENSOR_NOTIFY_ALL BIT(0) }; struct scmi_msg_set_sensor_trip_point { @@ -185,6 +186,12 @@ struct scmi_sensor_trip_notify_payld { __le32 trip_point_desc; }; +struct scmi_sensor_update_notify_payld { + __le32 agent_id; + __le32 sensor_id; + struct scmi_sensor_reading_le readings[]; +}; + struct sensors_info { u32 version; int num_sensors; @@ -550,15 +557,16 @@ out: return ret; } -static int scmi_sensor_trip_point_notify(const struct scmi_handle *handle, - u32 sensor_id, bool enable) +static inline int +scmi_sensor_request_notify(const struct scmi_handle *handle, u32 sensor_id, + u8 message_id, bool enable) { int ret; - u32 evt_cntl = enable ? SENSOR_TP_NOTIFY_ALL : 0; + u32 evt_cntl = enable ? SENSOR_NOTIFY_ALL : 0; struct scmi_xfer *t; - struct scmi_msg_sensor_trip_point_notify *cfg; + struct scmi_msg_sensor_request_notify *cfg; - ret = scmi_xfer_get_init(handle, SENSOR_TRIP_POINT_NOTIFY, + ret = scmi_xfer_get_init(handle, message_id, SCMI_PROTOCOL_SENSOR, sizeof(*cfg), 0, &t); if (ret) return ret; @@ -573,6 +581,23 @@ static int scmi_sensor_trip_point_notify(const struct scmi_handle *handle, return ret; } +static int scmi_sensor_trip_point_notify(const struct scmi_handle *handle, + u32 sensor_id, bool enable) +{ + return scmi_sensor_request_notify(handle, sensor_id, + SENSOR_TRIP_POINT_NOTIFY, + enable); +} + +static int +scmi_sensor_continuous_update_notify(const struct scmi_handle *handle, + u32 sensor_id, bool enable) +{ + return scmi_sensor_request_notify(handle, sensor_id, + SENSOR_CONTINUOUS_UPDATE_NOTIFY, + enable); +} + static int scmi_sensor_trip_point_config(const struct scmi_handle *handle, u32 sensor_id, u8 trip_id, u64 trip_value) @@ -815,7 +840,19 @@ static int scmi_sensor_set_notify_enabled(const struct scmi_handle *handle, { int ret; - ret = scmi_sensor_trip_point_notify(handle, src_id, enable); + switch (evt_id) { + case SCMI_EVENT_SENSOR_TRIP_POINT_EVENT: + ret = scmi_sensor_trip_point_notify(handle, src_id, enable); + break; + case SCMI_EVENT_SENSOR_UPDATE: + ret = scmi_sensor_continuous_update_notify(handle, src_id, + enable); + break; + default: + ret = -EINVAL; + break; + } + if (ret) pr_debug("FAIL_ENABLED - evt[%X] dom[%d] - ret:%d\n", evt_id, src_id, ret); @@ -828,20 +865,59 @@ static void *scmi_sensor_fill_custom_report(const struct scmi_handle *handle, const void *payld, size_t payld_sz, void *report, u32 *src_id) { - const struct scmi_sensor_trip_notify_payld *p = payld; - struct scmi_sensor_trip_point_report *r = report; + void *rep = NULL; - if (evt_id != SCMI_EVENT_SENSOR_TRIP_POINT_EVENT || - sizeof(*p) != payld_sz) - return NULL; + switch (evt_id) { + case SCMI_EVENT_SENSOR_TRIP_POINT_EVENT: + { + const struct scmi_sensor_trip_notify_payld *p = payld; + struct scmi_sensor_trip_point_report *r = report; - r->timestamp = timestamp; - r->agent_id = le32_to_cpu(p->agent_id); - r->sensor_id = le32_to_cpu(p->sensor_id); - r->trip_point_desc = le32_to_cpu(p->trip_point_desc); - *src_id = r->sensor_id; + if (sizeof(*p) != payld_sz) + break; - return r; + r->timestamp = timestamp; + r->agent_id = le32_to_cpu(p->agent_id); + r->sensor_id = le32_to_cpu(p->sensor_id); + r->trip_point_desc = le32_to_cpu(p->trip_point_desc); + *src_id = r->sensor_id; + rep = r; + break; + } + case SCMI_EVENT_SENSOR_UPDATE: + { + int i; + struct scmi_sensor_info *s; + const struct scmi_sensor_update_notify_payld *p = payld; + struct scmi_sensor_update_report *r = report; + struct sensors_info *sinfo = handle->sensor_priv; + + /* payld_sz is variable for this event */ + r->sensor_id = le32_to_cpu(p->sensor_id); + if (r->sensor_id >= sinfo->num_sensors) + break; + r->timestamp = timestamp; + r->agent_id = le32_to_cpu(p->agent_id); + s = &sinfo->sensors[r->sensor_id]; + /* + * The generated report r (@struct scmi_sensor_update_report) + * was pre-allocated to contain up to SCMI_MAX_NUM_SENSOR_AXIS + * readings: here it is filled with the effective @num_axis + * readings defined for this sensor or 1 for scalar sensors. + */ + r->readings_count = s->num_axis ?: 1; + for (i = 0; i < r->readings_count; i++) + scmi_parse_sensor_readings(&r->readings[i], + &p->readings[i]); + *src_id = r->sensor_id; + rep = r; + break; + } + default: + break; + } + + return rep; } static const struct scmi_event sensor_events[] = { @@ -850,6 +926,16 @@ static const struct scmi_event sensor_events[] = { .max_payld_sz = sizeof(struct scmi_sensor_trip_notify_payld), .max_report_sz = sizeof(struct scmi_sensor_trip_point_report), }, + { + .id = SCMI_EVENT_SENSOR_UPDATE, + .max_payld_sz = + sizeof(struct scmi_sensor_update_notify_payld) + + SCMI_MAX_NUM_SENSOR_AXIS * + sizeof(struct scmi_sensor_reading_le), + .max_report_sz = sizeof(struct scmi_sensor_update_report) + + SCMI_MAX_NUM_SENSOR_AXIS * + sizeof(struct scmi_sensor_reading), + }, }; static const struct scmi_event_ops sensor_event_ops = { diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h index 7e9e2cd3d46b..be0be5ff7514 100644 --- a/include/linux/scmi_protocol.h +++ b/include/linux/scmi_protocol.h @@ -657,6 +657,7 @@ enum scmi_notification_events { SCMI_EVENT_PERFORMANCE_LIMITS_CHANGED = 0x0, SCMI_EVENT_PERFORMANCE_LEVEL_CHANGED = 0x1, SCMI_EVENT_SENSOR_TRIP_POINT_EVENT = 0x0, + SCMI_EVENT_SENSOR_UPDATE = 0x1, SCMI_EVENT_RESET_ISSUED = 0x0, SCMI_EVENT_BASE_ERROR_EVENT = 0x0, SCMI_EVENT_SYSTEM_POWER_STATE_NOTIFIER = 0x0, @@ -698,6 +699,14 @@ struct scmi_sensor_trip_point_report { unsigned int trip_point_desc; }; +struct scmi_sensor_update_report { + ktime_t timestamp; + unsigned int agent_id; + unsigned int sensor_id; + unsigned int readings_count; + struct scmi_sensor_reading readings[]; +}; + struct scmi_reset_issued_report { ktime_t timestamp; unsigned int agent_id; -- cgit v1.2.3 From 0af104d729614de44c8eb5069353c8985cb17442 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Mon, 23 Nov 2020 00:28:18 +0100 Subject: soc: qcom: pdr: Constify static qmi structs Their only usage is to pass their address to qmi_handle_init() which accepts const pointers to both qmi_ops and qmi_msg_handler. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn Link: https://lore.kernel.org/r/20201122232818.32072-1-rikard.falkeborn@gmail.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pdr_interface.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/pdr_interface.c b/drivers/soc/qcom/pdr_interface.c index f63135c09667..209dcdca923f 100644 --- a/drivers/soc/qcom/pdr_interface.c +++ b/drivers/soc/qcom/pdr_interface.c @@ -110,7 +110,7 @@ static void pdr_locator_del_server(struct qmi_handle *qmi, pdr->locator_addr.sq_port = 0; } -static struct qmi_ops pdr_locator_ops = { +static const struct qmi_ops pdr_locator_ops = { .new_server = pdr_locator_new_server, .del_server = pdr_locator_del_server, }; @@ -238,7 +238,7 @@ static void pdr_notifier_del_server(struct qmi_handle *qmi, mutex_unlock(&pdr->list_lock); } -static struct qmi_ops pdr_notifier_ops = { +static const struct qmi_ops pdr_notifier_ops = { .new_server = pdr_notifier_new_server, .del_server = pdr_notifier_del_server, }; @@ -343,7 +343,7 @@ static void pdr_indication_cb(struct qmi_handle *qmi, queue_work(pdr->indack_wq, &pdr->indack_work); } -static struct qmi_msg_handler qmi_indication_handler[] = { +static const struct qmi_msg_handler qmi_indication_handler[] = { { .type = QMI_INDICATION, .msg_id = SERVREG_STATE_UPDATED_IND_ID, -- cgit v1.2.3 From e945927dc7c2d844b1955b2ec7ace07d2f6a6dcb Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 23 Nov 2020 16:20:08 +0000 Subject: firmware: arm_scmi: Remove residual _le structs naming For sake of consistency, remove any residual naming based on _le suffixes in SCMI sensors protocol, since little endianness is already assumed across all of SCMI implementation and, as such, all currently existent names do not explicitly state their endianness. No functional change. Link: https://lore.kernel.org/r/20201123162008.35814-1-cristian.marussi@arm.com Signed-off-by: Cristian Marussi Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/sensors.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/arm_scmi/sensors.c b/drivers/firmware/arm_scmi/sensors.c index b3d7c08c09a0..4541b891b733 100644 --- a/drivers/firmware/arm_scmi/sensors.c +++ b/drivers/firmware/arm_scmi/sensors.c @@ -168,7 +168,7 @@ struct scmi_resp_sensor_reading_complete { __le64 readings; }; -struct scmi_sensor_reading_le { +struct scmi_sensor_reading_resp { __le32 sensor_value_low; __le32 sensor_value_high; __le32 timestamp_low; @@ -177,7 +177,7 @@ struct scmi_sensor_reading_le { struct scmi_resp_sensor_reading_complete_v3 { __le32 id; - struct scmi_sensor_reading_le readings[]; + struct scmi_sensor_reading_resp readings[]; }; struct scmi_sensor_trip_notify_payld { @@ -189,7 +189,7 @@ struct scmi_sensor_trip_notify_payld { struct scmi_sensor_update_notify_payld { __le32 agent_id; __le32 sensor_id; - struct scmi_sensor_reading_le readings[]; + struct scmi_sensor_reading_resp readings[]; }; struct sensors_info { @@ -734,7 +734,7 @@ static int scmi_sensor_reading_get(const struct scmi_handle *handle, static inline void scmi_parse_sensor_readings(struct scmi_sensor_reading *out, - const struct scmi_sensor_reading_le *in) + const struct scmi_sensor_reading_resp *in) { out->value = get_unaligned_le64((void *)&in->sensor_value_low); out->timestamp = get_unaligned_le64((void *)&in->timestamp_low); @@ -797,7 +797,7 @@ scmi_sensor_reading_get_timestamped(const struct scmi_handle *handle, ret = scmi_do_xfer(handle, t); if (!ret) { int i; - struct scmi_sensor_reading_le *resp_readings; + struct scmi_sensor_reading_resp *resp_readings; resp_readings = t->rx.buf; for (i = 0; i < count; i++) @@ -931,7 +931,7 @@ static const struct scmi_event sensor_events[] = { .max_payld_sz = sizeof(struct scmi_sensor_update_notify_payld) + SCMI_MAX_NUM_SENSOR_AXIS * - sizeof(struct scmi_sensor_reading_le), + sizeof(struct scmi_sensor_reading_resp), .max_report_sz = sizeof(struct scmi_sensor_update_report) + SCMI_MAX_NUM_SENSOR_AXIS * sizeof(struct scmi_sensor_reading), -- cgit v1.2.3 From b636d36e3e0a5072b339b3164da18d6d0934e03e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:17 +0000 Subject: soc: fsl: dpio: qbman-portal: Fix a bunch of kernel-doc misdemeanours Fixes the following W=1 kernel build warning(s): drivers/soc/fsl/dpio/qbman-portal.c:430: warning: Function parameter or member 'inhibit' not described in 'qbman_swp_interrupt_set_inhibit' drivers/soc/fsl/dpio/qbman-portal.c:430: warning: Excess function parameter 'mask' description in 'qbman_swp_interrupt_set_inhibit' drivers/soc/fsl/dpio/qbman-portal.c:518: warning: Function parameter or member 'd' not described in 'qbman_eq_desc_clear' drivers/soc/fsl/dpio/qbman-portal.c:529: warning: Function parameter or member 'respond_success' not described in 'qbman_eq_desc_set_no_orp' drivers/soc/fsl/dpio/qbman-portal.c:529: warning: Excess function parameter 'response_success' description in 'qbman_eq_desc_set_no_orp' drivers/soc/fsl/dpio/qbman-portal.c:941: warning: Function parameter or member 's' not described in 'qbman_swp_push_get' drivers/soc/fsl/dpio/qbman-portal.c:941: warning: Excess function parameter 'p' description in 'qbman_swp_push_get' drivers/soc/fsl/dpio/qbman-portal.c:955: warning: Function parameter or member 's' not described in 'qbman_swp_push_set' drivers/soc/fsl/dpio/qbman-portal.c:955: warning: Excess function parameter 'p' description in 'qbman_swp_push_set' drivers/soc/fsl/dpio/qbman-portal.c:1052: warning: Function parameter or member 'd' not described in 'qbman_pull_desc_set_fq' drivers/soc/fsl/dpio/qbman-portal.c:1065: warning: Function parameter or member 'd' not described in 'qbman_pull_desc_set_wq' drivers/soc/fsl/dpio/qbman-portal.c:1079: warning: Function parameter or member 'd' not described in 'qbman_pull_desc_set_channel' drivers/soc/fsl/dpio/qbman-portal.c:1403: warning: Function parameter or member 'd' not described in 'qbman_release_desc_clear' drivers/soc/fsl/dpio/qbman-portal.c:1412: warning: Function parameter or member 'd' not described in 'qbman_release_desc_set_bpid' drivers/soc/fsl/dpio/qbman-portal.c:1412: warning: Function parameter or member 'bpid' not described in 'qbman_release_desc_set_bpid' drivers/soc/fsl/dpio/qbman-portal.c:1421: warning: Function parameter or member 'd' not described in 'qbman_release_desc_set_rcdi' drivers/soc/fsl/dpio/qbman-portal.c:1421: warning: Function parameter or member 'enable' not described in 'qbman_release_desc_set_rcdi' Cc: Roy Pledge Cc: Li Yang Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Lee Jones Signed-off-by: Li Yang --- drivers/soc/fsl/dpio/qbman-portal.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/soc/fsl/dpio/qbman-portal.c b/drivers/soc/fsl/dpio/qbman-portal.c index 659b4a570d5b..f13da4d7d1c5 100644 --- a/drivers/soc/fsl/dpio/qbman-portal.c +++ b/drivers/soc/fsl/dpio/qbman-portal.c @@ -424,7 +424,7 @@ int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p) /** * qbman_swp_interrupt_set_inhibit() - write interrupt mask register * @p: the given software portal object - * @mask: The mask to set in SWP_IIR register + * @inhibit: whether to inhibit the IRQs */ void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit) { @@ -510,7 +510,7 @@ enum qb_enqueue_commands { #define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4 #define QB_ENQUEUE_CMD_DCA_EN_SHIFT 7 -/** +/* * qbman_eq_desc_clear() - Clear the contents of a descriptor to * default/starting state. */ @@ -522,7 +522,7 @@ void qbman_eq_desc_clear(struct qbman_eq_desc *d) /** * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp * @d: the enqueue descriptor. - * @response_success: 1 = enqueue with response always; 0 = enqueue with + * @respond_success: 1 = enqueue with response always; 0 = enqueue with * rejections returned on a FQ. */ void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success) @@ -932,7 +932,7 @@ int qbman_swp_enqueue_multiple_desc_mem_back(struct qbman_swp *s, /** * qbman_swp_push_get() - Get the push dequeue setup - * @p: the software portal object + * @s: the software portal object * @channel_idx: the channel index to query * @enabled: returned boolean to show whether the push dequeue is enabled * for the given channel @@ -947,7 +947,7 @@ void qbman_swp_push_get(struct qbman_swp *s, u8 channel_idx, int *enabled) /** * qbman_swp_push_set() - Enable or disable push dequeue - * @p: the software portal object + * @s: the software portal object * @channel_idx: the channel index (0 to 15) * @enable: enable or disable push dequeue */ @@ -1046,6 +1046,7 @@ void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes) /** * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues + * @d: the pull dequeue descriptor to be set * @fqid: the frame queue index of the given FQ */ void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid) @@ -1057,6 +1058,7 @@ void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid) /** * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues + * @d: the pull dequeue descriptor to be set * @wqid: composed of channel id and wqid within the channel * @dct: the dequeue command type */ @@ -1071,6 +1073,7 @@ void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid, /** * qbman_pull_desc_set_channel() - Set channelid from which the dequeue command * dequeues + * @d: the pull dequeue descriptor to be set * @chid: the channel id to be dequeued * @dct: the dequeue command type */ @@ -1398,6 +1401,7 @@ int qbman_result_has_new_result(struct qbman_swp *s, const struct dpaa2_dq *dq) /** * qbman_release_desc_clear() - Clear the contents of a descriptor to * default/starting state. + * @d: the pull dequeue descriptor to be cleared */ void qbman_release_desc_clear(struct qbman_release_desc *d) { @@ -1407,6 +1411,8 @@ void qbman_release_desc_clear(struct qbman_release_desc *d) /** * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to + * @d: the pull dequeue descriptor to be set + * @bpid: the bpid value to be set */ void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid) { @@ -1416,6 +1422,8 @@ void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid) /** * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI * interrupt source should be asserted after the release command is completed. + * @d: the pull dequeue descriptor to be set + * @enable: enable (1) or disable (0) value */ void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable) { -- cgit v1.2.3 From 0d0807bc2e05844db9c2fb78d1f36d98ddc8a3fa Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:24 +0000 Subject: soc: fsl: qe: qe_common: Fix misnamed function attribute 'addr' Fixes the following W=1 kernel build warning(s): drivers/soc/fsl/qe/qe_common.c:237: warning: Function parameter or member 'addr' not described in 'cpm_muram_dma' drivers/soc/fsl/qe/qe_common.c:237: warning: Excess function parameter 'offset' description in 'cpm_muram_dma' Cc: Qiang Zhao Cc: Li Yang Cc: Scott Wood Cc: act Cc: Dan Malek Cc: "Software, Inc" Cc: Vitaly Bordug Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Lee Jones Signed-off-by: Li Yang --- drivers/soc/fsl/qe/qe_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/fsl/qe/qe_common.c b/drivers/soc/fsl/qe/qe_common.c index 75075591f630..497a7e0fd027 100644 --- a/drivers/soc/fsl/qe/qe_common.c +++ b/drivers/soc/fsl/qe/qe_common.c @@ -231,7 +231,7 @@ EXPORT_SYMBOL(cpm_muram_offset); /** * cpm_muram_dma - turn a muram virtual address into a DMA address - * @offset: virtual address from cpm_muram_addr() to convert + * @addr: virtual address from cpm_muram_addr() to convert */ dma_addr_t cpm_muram_dma(void __iomem *addr) { -- cgit v1.2.3 From 3d1d8f2943e23bd329b63548cdcc915b3657c4d2 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 3 Nov 2020 15:28:38 +0000 Subject: soc: fsl: qbman: qman: Remove unused variable 'dequeue_wq' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes the following W=1 kernel build warning(s): drivers/soc/fsl/qbman/qman.c: In function ‘qman_shutdown_fq’: drivers/soc/fsl/qbman/qman.c:2700:8: warning: variable ‘dequeue_wq’ set but not used [-Wunused-but-set-variable] Cc: Li Yang Cc: YueHaibing Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: Lee Jones Signed-off-by: Li Yang --- drivers/soc/fsl/qbman/qman.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/soc/fsl/qbman/qman.c b/drivers/soc/fsl/qbman/qman.c index 9888a7061873..62b182c3a8b0 100644 --- a/drivers/soc/fsl/qbman/qman.c +++ b/drivers/soc/fsl/qbman/qman.c @@ -2622,7 +2622,7 @@ int qman_shutdown_fq(u32 fqid) union qm_mc_command *mcc; union qm_mc_result *mcr; int orl_empty, drain = 0, ret = 0; - u32 channel, wq, res; + u32 channel, res; u8 state; p = get_affine_portal(); @@ -2655,7 +2655,7 @@ int qman_shutdown_fq(u32 fqid) DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ); /* Need to store these since the MCR gets reused */ channel = qm_fqd_get_chan(&mcr->queryfq.fqd); - wq = qm_fqd_get_wq(&mcr->queryfq.fqd); + qm_fqd_get_wq(&mcr->queryfq.fqd); if (channel < qm_channel_pool1) { channel_portal = get_portal_for_channel(channel); @@ -2697,7 +2697,6 @@ int qman_shutdown_fq(u32 fqid) * to dequeue from the channel the FQ is scheduled on */ int found_fqrn = 0; - u16 dequeue_wq = 0; /* Flag that we need to drain FQ */ drain = 1; @@ -2705,11 +2704,8 @@ int qman_shutdown_fq(u32 fqid) if (channel >= qm_channel_pool1 && channel < qm_channel_pool1 + 15) { /* Pool channel, enable the bit in the portal */ - dequeue_wq = (channel - - qm_channel_pool1 + 1)<<4 | wq; } else if (channel < qm_channel_pool1) { /* Dedicated channel */ - dequeue_wq = wq; } else { dev_err(dev, "Can't recover FQ 0x%x, ch: 0x%x", fqid, channel); -- cgit v1.2.3 From e95f287deed2454b8cad5b27859271db30130b2b Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 2 Nov 2020 15:26:50 +0800 Subject: soc: fsl: handle RCPM errata A-008646 on SoC LS1021A Hardware issue: - Reading register RCPM_IPPDEXPCR1 always return zero, this causes system firmware could not get correct information and wrongly do clock gating for all wakeup source IP during system suspend. Then those IPs will never get chance to wake system. Workaround: - Copy register RCPM_IPPDEXPCR1's setting to register SCFG_SPARECR8 to allow system firmware's psci method read it and do things accordingly. Signed-off-by: Biwen Li Signed-off-by: Ran Wang Signed-off-by: Li Yang --- drivers/soc/fsl/rcpm.c | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c index a093dbe6d2cb..4ace28cab314 100644 --- a/drivers/soc/fsl/rcpm.c +++ b/drivers/soc/fsl/rcpm.c @@ -2,7 +2,7 @@ // // rcpm.c - Freescale QorIQ RCPM driver // -// Copyright 2019 NXP +// Copyright 2019-2020 NXP // // Author: Ran Wang @@ -22,6 +22,28 @@ struct rcpm { bool little_endian; }; +#define SCFG_SPARECR8 0x051c + +static void copy_ippdexpcr1_setting(u32 val) +{ + struct device_node *np; + void __iomem *regs; + u32 reg_val; + + np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-scfg"); + if (!np) + return; + + regs = of_iomap(np, 0); + if (!regs) + return; + + reg_val = ioread32be(regs + SCFG_SPARECR8); + iowrite32be(val | reg_val, regs + SCFG_SPARECR8); + + iounmap(regs); +} + /** * rcpm_pm_prepare - performs device-level tasks associated with power * management, such as programming related to the wakeup source control. @@ -90,6 +112,17 @@ static int rcpm_pm_prepare(struct device *dev) tmp |= ioread32be(address); iowrite32be(tmp, address); } + /* + * Workaround of errata A-008646 on SoC LS1021A: + * There is a bug of register ippdexpcr1. + * Reading configuration register RCPM_IPPDEXPCR1 + * always return zero. So save ippdexpcr1's value + * to register SCFG_SPARECR8.And the value of + * ippdexpcr1 will be read from SCFG_SPARECR8. + */ + if (dev_of_node(dev) && (i == 1)) + if (of_device_is_compatible(np, "fsl,ls1021a-rcpm")) + copy_ippdexpcr1_setting(tmp); } return 0; -- cgit v1.2.3 From e24f7fac3b973ad24b0fd96f6de47695c90f6528 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Tue, 24 Nov 2020 11:35:46 +0100 Subject: soc: sunxi: Fix compilation of sunxi_mbus dma_direct_set_offset has been moved from dma-mapping.h to dma-map-ops.h, but our driver hasn't been updated resulting in a build breakage. Let's change the header to fix the build. Fixes: 16fee29b0735 ("dma-mapping: remove the dma_direct_set_offset export") Signed-off-by: Maxime Ripard Link: https://lore.kernel.org/r/20201124103546.839711-1-maxime@cerno.tech' Signed-off-by: Arnd Bergmann --- drivers/soc/sunxi/sunxi_mbus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/sunxi/sunxi_mbus.c b/drivers/soc/sunxi/sunxi_mbus.c index a9d077f73c3a..e9925c8487d7 100644 --- a/drivers/soc/sunxi/sunxi_mbus.c +++ b/drivers/soc/sunxi/sunxi_mbus.c @@ -2,7 +2,7 @@ /* Copyright (C) 2020 Maxime Ripard */ #include -#include +#include #include #include #include -- cgit v1.2.3 From bfc1b6597f58040ff9116f5acc84ccd6367e2d59 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Tue, 24 Nov 2020 22:29:54 +0100 Subject: samples: qmi: Constify static qmi ops The only usage of qmi_sample_handlers[] and lookup_ops is to pass their addresses to qmi_handle_init() which accepts const pointers to both qmi_ops and qmi_msg_handler. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn Link: https://lore.kernel.org/r/20201124212954.17750-1-rikard.falkeborn@gmail.com Signed-off-by: Bjorn Andersson --- samples/qmi/qmi_sample_client.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/samples/qmi/qmi_sample_client.c b/samples/qmi/qmi_sample_client.c index c9e7276c3d83..78fcedbd25e2 100644 --- a/samples/qmi/qmi_sample_client.c +++ b/samples/qmi/qmi_sample_client.c @@ -429,7 +429,7 @@ static const struct file_operations data_fops = { .write = data_write, }; -static struct qmi_msg_handler qmi_sample_handlers[] = { +static const struct qmi_msg_handler qmi_sample_handlers[] = { { .type = QMI_RESPONSE, .msg_id = TEST_PING_REQ_MSG_ID_V01, @@ -571,7 +571,7 @@ static void qmi_sample_del_server(struct qmi_handle *qmi, static struct qmi_handle lookup_client; -static struct qmi_ops lookup_ops = { +static const struct qmi_ops lookup_ops = { .new_server = qmi_sample_new_server, .del_server = qmi_sample_del_server, }; -- cgit v1.2.3 From 0924dad5d45882d7946416fd16c754d2a894d326 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Thu, 26 Nov 2020 14:01:30 +0530 Subject: soc: qcom: rpmh: Use __fill_rpmh_msg API during rpmh_write() Use __fill_rpmh_msg API during rpmh_write(). This allows to remove duplication of code in error checking, copying commands and setting message state. Reviewed-by: Bjorn Andersson Signed-off-by: Maulik Shah Link: https://lore.kernel.org/r/1606379490-4052-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmh.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/rpmh.c b/drivers/soc/qcom/rpmh.c index ad1f062620ff..01765ee9cdfb 100644 --- a/drivers/soc/qcom/rpmh.c +++ b/drivers/soc/qcom/rpmh.c @@ -181,8 +181,6 @@ static int __rpmh_write(const struct device *dev, enum rpmh_state state, struct cache_req *req; int i; - rpm_msg->msg.state = state; - /* Cache the request in our store and link the payload */ for (i = 0; i < rpm_msg->msg.num_cmds; i++) { req = cache_rpm_request(ctrlr, state, &rpm_msg->msg.cmds[i]); @@ -190,8 +188,6 @@ static int __rpmh_write(const struct device *dev, enum rpmh_state state, return PTR_ERR(req); } - rpm_msg->msg.state = state; - if (state == RPMH_ACTIVE_ONLY_STATE) { WARN_ON(irqs_disabled()); ret = rpmh_rsc_send_data(ctrlr_to_drv(ctrlr), &rpm_msg->msg); @@ -268,11 +264,9 @@ int rpmh_write(const struct device *dev, enum rpmh_state state, DEFINE_RPMH_MSG_ONSTACK(dev, state, &compl, rpm_msg); int ret; - if (!cmd || !n || n > MAX_RPMH_PAYLOAD) - return -EINVAL; - - memcpy(rpm_msg.cmd, cmd, n * sizeof(*cmd)); - rpm_msg.msg.num_cmds = n; + ret = __fill_rpmh_msg(&rpm_msg, state, cmd, n); + if (ret) + return ret; ret = __rpmh_write(dev, state, &rpm_msg); if (ret) -- cgit v1.2.3 From f365bd3355145891762f32f93f2b388c34ed5115 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 26 Nov 2020 14:57:10 +0530 Subject: dt-bindings: power: Add rpm power domain bindings for sdx55 Add RPM power domain bindings for the SDX55 SoC Acked-by: Manivannan Sadhasivam Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201126092711.1084518-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + include/dt-bindings/power/qcom-rpmpd.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index e07453417f45..64825128ee97 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -25,6 +25,7 @@ properties: - qcom,sdm660-rpmpd - qcom,sc7180-rpmhpd - qcom,sdm845-rpmhpd + - qcom,sdx55-rpmhpd - qcom,sm8150-rpmhpd - qcom,sm8250-rpmhpd diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 973329c62509..7714487ac76b 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -15,6 +15,11 @@ #define SDM845_GFX 7 #define SDM845_MSS 8 +/* SDX55 Power Domain Indexes */ +#define SDX55_MSS 0 +#define SDX55_MX 1 +#define SDX55_CX 2 + /* SM8150 Power Domain Indexes */ #define SM8150_MSS 0 #define SM8150_EBI 1 -- cgit v1.2.3 From 6c6bd2075f01f8c8ae4bc803ba5cd23a3d3db533 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:04 +0300 Subject: memory: tegra: Add and use devm_tegra_memory_controller_get() Multiple Tegra drivers need to retrieve Memory Controller and there is duplication of the retrieval code among the drivers. Add new devm_tegra_memory_controller_get() helper to remove the code's duplication and to fix put_device() which was missed in the duplicated code. Make EMC drivers to use the new helper. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-29-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 48 ++++++++++++++++++++++++++++++++ drivers/memory/tegra/tegra124-emc.c | 18 ++---------- drivers/memory/tegra/tegra210-emc-core.c | 39 +++++++------------------- drivers/memory/tegra/tegra30-emc.c | 18 ++---------- include/soc/tegra/mc.h | 10 +++++++ 5 files changed, 74 insertions(+), 59 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index ec8403557ed4..a72cdcafc933 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -42,6 +42,54 @@ static const struct of_device_id tegra_mc_of_match[] = { }; MODULE_DEVICE_TABLE(of, tegra_mc_of_match); +static void tegra_mc_devm_action_put_device(void *data) +{ + struct tegra_mc *mc = data; + + put_device(mc->dev); +} + +/** + * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle + * @dev: device pointer for the consumer device + * + * This function will search for the Memory Controller node in a device-tree + * and retrieve the Memory Controller handle. + * + * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. + */ +struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) +{ + struct platform_device *pdev; + struct device_node *np; + struct tegra_mc *mc; + int err; + + np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); + if (!np) + return ERR_PTR(-ENOENT); + + pdev = of_find_device_by_node(np); + of_node_put(np); + if (!pdev) + return ERR_PTR(-ENODEV); + + mc = platform_get_drvdata(pdev); + if (!mc) { + put_device(&pdev->dev); + return ERR_PTR(-EPROBE_DEFER); + } + + err = devm_add_action(dev, tegra_mc_devm_action_put_device, mc); + if (err) { + put_device(mc->dev); + return ERR_PTR(err); + } + + return mc; +} +EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); + static int tegra_mc_block_dma_common(struct tegra_mc *mc, const struct tegra_mc_reset *rst) { diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 76ace42a688a..35dbceb7f841 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1177,7 +1177,6 @@ static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { - struct platform_device *mc; struct device_node *np; struct tegra_emc *emc; struct resource *res; @@ -1195,20 +1194,9 @@ static int tegra_emc_probe(struct platform_device *pdev) if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) - return -EPROBE_DEFER; + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); ram_code = tegra_read_ram_code(); diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c index cdd663ba4733..5f224796e32e 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -1828,7 +1828,6 @@ static int tegra210_emc_probe(struct platform_device *pdev) { struct thermal_cooling_device *cd; unsigned long current_rate; - struct platform_device *mc; struct tegra210_emc *emc; struct device_node *np; unsigned int i; @@ -1846,35 +1845,19 @@ static int tegra210_emc_probe(struct platform_device *pdev) spin_lock_init(&emc->lock); emc->dev = &pdev->dev; - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) { - put_device(&mc->dev); - return -EPROBE_DEFER; - } + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); emc->regs = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(emc->regs)) { - err = PTR_ERR(emc->regs); - goto put_mc; - } + if (IS_ERR(emc->regs)) + return PTR_ERR(emc->regs); for (i = 0; i < 2; i++) { emc->channel[i] = devm_platform_ioremap_resource(pdev, 1 + i); - if (IS_ERR(emc->channel[i])) { - err = PTR_ERR(emc->channel[i]); - goto put_mc; - } + if (IS_ERR(emc->channel[i])) + return PTR_ERR(emc->channel[i]); + } tegra210_emc_detect(emc); @@ -1884,7 +1867,7 @@ static int tegra210_emc_probe(struct platform_device *pdev) err = of_reserved_mem_device_init_by_name(emc->dev, np, "nominal"); if (err < 0) { dev_err(emc->dev, "failed to get nominal EMC table: %d\n", err); - goto put_mc; + return err; } err = of_reserved_mem_device_init_by_name(emc->dev, np, "derated"); @@ -2015,8 +1998,7 @@ detach: tegra210_clk_emc_detach(emc->clk); release: of_reserved_mem_device_release(emc->dev); -put_mc: - put_device(emc->mc->dev); + return err; } @@ -2027,7 +2009,6 @@ static int tegra210_emc_remove(struct platform_device *pdev) debugfs_remove_recursive(emc->debugfs.root); tegra210_clk_emc_detach(emc->clk); of_reserved_mem_device_release(emc->dev); - put_device(emc->mc->dev); return 0; } diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 055af0e08a2e..c58cf31cb27b 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1258,7 +1258,6 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) static int tegra_emc_probe(struct platform_device *pdev) { - struct platform_device *mc; struct device_node *np; struct tegra_emc *emc; int err; @@ -1269,17 +1268,6 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENODEV; } - np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0); - if (!np) { - dev_err(&pdev->dev, "could not get memory controller node\n"); - return -ENOENT; - } - - mc = of_find_device_by_node(np); - of_node_put(np); - if (!mc) - return -ENOENT; - np = emc_find_node_by_ram_code(&pdev->dev); if (!np) return -EINVAL; @@ -1290,9 +1278,9 @@ static int tegra_emc_probe(struct platform_device *pdev) return -ENOMEM; } - emc->mc = platform_get_drvdata(mc); - if (!emc->mc) - return -EPROBE_DEFER; + emc->mc = devm_tegra_memory_controller_get(&pdev->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 1238e35653d1..d9395af98143 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -184,4 +184,14 @@ struct tegra_mc { int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc); +#ifdef CONFIG_TEGRA_MC +struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev); +#else +static inline struct tegra_mc * +devm_tegra_memory_controller_get(struct device *dev) +{ + ERR_PTR(-ENODEV); +} +#endif + #endif /* __SOC_TEGRA_MC_H__ */ -- cgit v1.2.3 From 9c45662675b38e80fff48397506cf9fd9936b6f3 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 26 Nov 2020 14:57:11 +0530 Subject: soc: qcom: rpmhpd: Add SDX55 power domains This adds the power domains found in SDX55 SoC. Downstream code tells me that we have 3 power domains so add them Acked-by: Manivannan Sadhasivam Signed-off-by: Vinod Koul Link: https://lore.kernel.org/r/20201126092711.1084518-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmhpd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 6bab57aa6d48..7ce06356d24c 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -135,6 +135,18 @@ static const struct rpmhpd_desc sdm845_desc = { .num_pds = ARRAY_SIZE(sdm845_rpmhpds), }; +/* SDX55 RPMH powerdomains */ +static struct rpmhpd *sdx55_rpmhpds[] = { + [SDX55_MSS] = &sdm845_mss, + [SDX55_MX] = &sdm845_mx, + [SDX55_CX] = &sdm845_cx, +}; + +static const struct rpmhpd_desc sdx55_desc = { + .rpmhpds = sdx55_rpmhpds, + .num_pds = ARRAY_SIZE(sdx55_rpmhpds), +}; + /* SM8150 RPMH powerdomains */ static struct rpmhpd sm8150_mmcx_ao; @@ -208,6 +220,7 @@ static const struct rpmhpd_desc sc7180_desc = { static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sc7180-rpmhpd", .data = &sc7180_desc }, { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, + { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, { } -- cgit v1.2.3 From 4e84d0a6e1206fda47395b5d3af1453e013d7b38 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:05 +0300 Subject: memory: tegra: Use devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-30-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra124-emc.c | 4 +--- drivers/memory/tegra/tegra20-emc.c | 4 +--- 2 files changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c index 35dbceb7f841..ee8ee39e98ed 100644 --- a/drivers/memory/tegra/tegra124-emc.c +++ b/drivers/memory/tegra/tegra124-emc.c @@ -1179,7 +1179,6 @@ static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; struct tegra_emc *emc; - struct resource *res; u32 ram_code; int err; @@ -1189,8 +1188,7 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->dev = &pdev->dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc->regs = devm_ioremap_resource(&pdev->dev, res); + emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 027f46287dbf..5ba4e495bfc3 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -654,7 +654,6 @@ static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; struct tegra_emc *emc; - struct resource *res; int irq, err; /* driver has nothing to do in a case of memory timing absence */ @@ -689,8 +688,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (err) return err; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - emc->regs = devm_ioremap_resource(&pdev->dev, res); + emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) return PTR_ERR(emc->regs); -- cgit v1.2.3 From 162641a6e200e935cd39b26737f3ec0b5ea856fb Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:06 +0300 Subject: memory: tegra: Remove superfluous error messages around platform_get_irq() The platform_get_irq() prints error message telling that interrupt is missing, hence there is no need to duplicated that message in the drivers. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-31-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/mc.c | 4 +--- drivers/memory/tegra/tegra20-emc.c | 1 - drivers/memory/tegra/tegra30-emc.c | 5 ++--- 3 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a72cdcafc933..998f9148ecb8 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -707,10 +707,8 @@ static int tegra_mc_probe(struct platform_device *pdev) } mc->irq = platform_get_irq(pdev, 0); - if (mc->irq < 0) { - dev_err(&pdev->dev, "interrupt not specified\n"); + if (mc->irq < 0) return mc->irq; - } WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 5ba4e495bfc3..c9fe58a724ee 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -665,7 +665,6 @@ static int tegra_emc_probe(struct platform_device *pdev) irq = platform_get_irq(pdev, 0); if (irq < 0) { - dev_err(&pdev->dev, "interrupt not specified\n"); dev_err(&pdev->dev, "please update your device tree\n"); return irq; } diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index c58cf31cb27b..1be28e28ec34 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1299,10 +1299,9 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; err = platform_get_irq(pdev, 0); - if (err < 0) { - dev_err(&pdev->dev, "interrupt not specified: %d\n", err); + if (err < 0) return err; - } + emc->irq = err; err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, -- cgit v1.2.3 From d5ecac0afa30811901eb401067f196e688aeb73e Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:07 +0300 Subject: memory: tegra: Add missing latency allowness entry for Page Table Cache Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-32-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra114.c | 6 ++++++ drivers/memory/tegra/tegra124.c | 6 ++++++ drivers/memory/tegra/tegra30.c | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c index 48ef01c3ff90..ed376ba2d2fe 100644 --- a/drivers/memory/tegra/tegra114.c +++ b/drivers/memory/tegra/tegra114.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra114_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index 0cede24479bf..e2389573d3c0 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -15,6 +15,12 @@ static const struct tegra_mc_client tegra124_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index fcdd812eed80..b1990b4133d8 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -36,6 +36,12 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .id = 0x00, .name = "ptcr", .swgroup = TEGRA_SWGROUP_PTC, + .la = { + .reg = 0x34c, + .shift = 0, + .mask = 0xff, + .def = 0x0, + }, }, { .id = 0x01, .name = "display0a", -- cgit v1.2.3 From 06f079816d4c4e43d4128f394ae249934a32dffd Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:08 +0300 Subject: memory: tegra-mc: Add interconnect framework Add common SoC-agnostic ICC framework which turns Tegra Memory Controller into a memory interconnection provider. This allows us to use interconnect API for tuning of memory configurations. Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Tested-by: Nicolas Chauvet Link: https://lore.kernel.org/r/20201104164923.21238-33-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/mc.c | 100 +++++++++++++++++++++++++++++++++++++++++++ drivers/memory/tegra/mc.h | 22 ++++++++++ include/soc/tegra/mc.h | 17 ++++++++ 4 files changed, 140 insertions(+) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 9f0a96bf9ccc..b38e5255effe 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -3,6 +3,7 @@ config TEGRA_MC bool "NVIDIA Tegra Memory Controller support" default y depends on ARCH_TEGRA + select INTERCONNECT help This driver supports the Memory Controller (MC) hardware found on NVIDIA Tegra SoCs. diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index 998f9148ecb8..a7e6a8e4c95a 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -639,6 +639,101 @@ static __maybe_unused irqreturn_t tegra20_mc_irq(int irq, void *data) return IRQ_HANDLED; } +/* + * Memory Controller (MC) has few Memory Clients that are issuing memory + * bandwidth allocation requests to the MC interconnect provider. The MC + * provider aggregates the requests and then sends the aggregated request + * up to the External Memory Controller (EMC) interconnect provider which + * re-configures hardware interface to External Memory (EMEM) in accordance + * to the required bandwidth. Each MC interconnect node represents an + * individual Memory Client. + * + * Memory interconnect topology: + * + * +----+ + * +--------+ | | + * | TEXSRD +--->+ | + * +--------+ | | + * | | +-----+ +------+ + * ... | MC +--->+ EMC +--->+ EMEM | + * | | +-----+ +------+ + * +--------+ | | + * | DISP.. +--->+ | + * +--------+ | | + * +----+ + */ +static int tegra_mc_interconnect_setup(struct tegra_mc *mc) +{ + struct icc_node *node; + unsigned int i; + int err; + + /* older device-trees don't have interconnect properties */ + if (!device_property_present(mc->dev, "#interconnect-cells") || + !mc->soc->icc_ops) + return 0; + + mc->provider.dev = mc->dev; + mc->provider.data = &mc->provider; + mc->provider.set = mc->soc->icc_ops->set; + mc->provider.aggregate = mc->soc->icc_ops->aggregate; + mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; + + err = icc_provider_add(&mc->provider); + if (err) + return err; + + /* create Memory Controller node */ + node = icc_node_create(TEGRA_ICC_MC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "Memory Controller"; + icc_node_add(node, &mc->provider); + + /* link Memory Controller to External Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_EMC); + if (err) + goto remove_nodes; + + for (i = 0; i < mc->soc->num_clients; i++) { + /* create MC client node */ + node = icc_node_create(mc->soc->clients[i].id); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = mc->soc->clients[i].name; + icc_node_add(node, &mc->provider); + + /* link Memory Client to Memory Controller */ + err = icc_link_create(node, TEGRA_ICC_MC); + if (err) + goto remove_nodes; + } + + /* + * MC driver is registered too early, so early that generic driver + * syncing doesn't work for the MC. But it doesn't really matter + * since syncing works for the EMC drivers, hence we can sync the + * MC driver by ourselves and then EMC will complete syncing of + * the whole ICC state. + */ + icc_sync_state(mc->dev); + + return 0; + +remove_nodes: + icc_nodes_remove(&mc->provider); +del_provider: + icc_provider_del(&mc->provider); + + return err; +} + static int tegra_mc_probe(struct platform_device *pdev) { struct resource *res; @@ -727,6 +822,11 @@ static int tegra_mc_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); + err = tegra_mc_interconnect_setup(mc); + if (err < 0) + dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", + err); + if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); if (IS_ERR(mc->smmu)) { diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index afa3ba45c9e6..33e40d600592 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -78,6 +78,20 @@ #define MC_TIMING_UPDATE BIT(0) +static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) +{ + val = val * percents; + do_div(val, 100); + + return min_t(u64, val, U32_MAX); +} + +static inline struct tegra_mc * +icc_provider_to_tegra_mc(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_mc, provider); +} + static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset) { return readl_relaxed(mc->regs + offset); @@ -115,4 +129,12 @@ extern const struct tegra_mc_soc tegra132_mc_soc; extern const struct tegra_mc_soc tegra210_mc_soc; #endif +/* + * These IDs are for internal use of Tegra ICC drivers. The ID numbers are + * chosen such that they don't conflict with the device-tree ICC node IDs. + */ +#define TEGRA_ICC_MC 1000 +#define TEGRA_ICC_EMC 1001 +#define TEGRA_ICC_EMEM 1002 + #endif /* MEMORY_TEGRA_MC_H */ diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index d9395af98143..43876216de34 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -6,7 +6,9 @@ #ifndef __SOC_TEGRA_MC_H__ #define __SOC_TEGRA_MC_H__ +#include #include +#include #include #include @@ -141,6 +143,17 @@ struct tegra_mc_reset_ops { const struct tegra_mc_reset *rst); }; +#define TEGRA_MC_ICC_TAG_DEFAULT 0 +#define TEGRA_MC_ICC_TAG_ISO BIT(0) + +struct tegra_mc_icc_ops { + int (*set)(struct icc_node *src, struct icc_node *dst); + int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak); + struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec, + void *data); +}; + struct tegra_mc_soc { const struct tegra_mc_client *clients; unsigned int num_clients; @@ -160,6 +173,8 @@ struct tegra_mc_soc { const struct tegra_mc_reset_ops *reset_ops; const struct tegra_mc_reset *resets; unsigned int num_resets; + + const struct tegra_mc_icc_ops *icc_ops; }; struct tegra_mc { @@ -178,6 +193,8 @@ struct tegra_mc { struct reset_controller_dev reset; + struct icc_provider provider; + spinlock_t lock; }; -- cgit v1.2.3 From 0260979b018faaf90ff5a7bb04ac3f38e9dee6e3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:09 +0300 Subject: memory: tegra20-emc: Make driver modular Add modularization support to the Tegra20 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201104164923.21238-34-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/tegra20-emc.c | 17 ++++++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index b38e5255effe..ff426747cd7d 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -9,7 +9,7 @@ config TEGRA_MC NVIDIA Tegra SoCs. config TEGRA20_EMC - bool "NVIDIA Tegra20 External Memory Controller driver" + tristate "NVIDIA Tegra20 External Memory Controller driver" default y depends on ARCH_TEGRA_2x_SOC help diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index c9fe58a724ee..88619e3ec435 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -721,6 +721,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -733,6 +740,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra20-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -742,9 +750,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From fa4794ff8fb4b324ae5b9f089312bcd4ce4ff6ed Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:10 +0300 Subject: memory: tegra20-emc: Continue probing if timings are missing in device-tree EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-35-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 34 ++++++++++++++++------------------ 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 88619e3ec435..a49658d217a7 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -383,6 +383,11 @@ tegra_emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) return of_node_get(dev->of_node); @@ -451,6 +456,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -656,36 +664,26 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int irq, err; - /* driver has nothing to do in a case of memory timing absence */ - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "EMC device tree node doesn't have memory timings\n"); - return 0; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "please update your device tree\n"); return irq; } - np = tegra_emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); - if (!emc) { - of_node_put(np); + if (!emc) return -ENOMEM; - } emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; emc->dev = &pdev->dev; - err = tegra_emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = tegra_emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = tegra_emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) -- cgit v1.2.3 From d5ef16ba5fbe128873a55441d85ccde77f63c129 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 4 Nov 2020 19:49:11 +0300 Subject: memory: tegra20: Support interconnect framework Now Internal and External Memory Controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-36-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 3 +- drivers/memory/tegra/tegra20-emc.c | 310 ++++++++++++++++++++++++++++++++++++- drivers/memory/tegra/tegra20.c | 77 +++++++++ 3 files changed, 386 insertions(+), 4 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index ff426747cd7d..ac3dfe155505 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -11,7 +11,8 @@ config TEGRA_MC config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y - depends on ARCH_TEGRA_2x_SOC + depends on TEGRA_MC && ARCH_TEGRA_2x_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index a49658d217a7..5e10aa97809f 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -9,18 +9,25 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include +#include +#include #include #include +#include #include +#include "mc.h" + #define EMC_INTSTATUS 0x000 #define EMC_INTMASK 0x004 #define EMC_DBG 0x008 @@ -62,6 +69,11 @@ #define EMC_ODT_READ 0x0b4 #define EMC_FBIO_CFG5 0x104 #define EMC_FBIO_CFG6 0x114 +#define EMC_STAT_CONTROL 0x160 +#define EMC_STAT_LLMC_CONTROL 0x178 +#define EMC_STAT_PWR_CLOCK_LIMIT 0x198 +#define EMC_STAT_PWR_CLOCKS 0x19c +#define EMC_STAT_PWR_COUNT 0x1a0 #define EMC_AUTO_CAL_INTERVAL 0x2a8 #define EMC_CFG_2 0x2b8 #define EMC_CFG_DIG_DLL 0x2bc @@ -88,6 +100,8 @@ #define EMC_DBG_READ_DQM_CTRL BIT(9) #define EMC_DBG_CFG_PRIORITY BIT(24) +#define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) + static const u16 emc_timing_registers[] = { EMC_RC, EMC_RFC, @@ -142,11 +156,25 @@ struct emc_timing { u32 data[ARRAY_SIZE(emc_timing_registers)]; }; +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra_emc { struct device *dev; + struct tegra_mc *mc; + struct icc_provider provider; struct notifier_block clk_nb; struct clk *clk; void __iomem *regs; + unsigned int dram_bus_width; struct emc_timing *timings; unsigned int num_timings; @@ -156,6 +184,15 @@ struct tegra_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; static irqreturn_t tegra_emc_isr(int irq, void *data) @@ -413,7 +450,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev) static int emc_setup_hw(struct tegra_emc *emc) { u32 intmask = EMC_REFRESH_OVERFLOW_INT; - u32 emc_cfg, emc_dbg; + u32 emc_cfg, emc_dbg, emc_fbio; emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); @@ -444,6 +481,15 @@ static int emc_setup_hw(struct tegra_emc *emc) emc_dbg &= ~EMC_DBG_FORCE_UPDATE; writel_relaxed(emc_dbg, emc->regs + EMC_DBG); + emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); + + if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16) + emc->dram_bus_width = 16; + else + emc->dram_bus_width = 32; + + dev_info(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); + return 0; } @@ -488,6 +534,83 @@ static long emc_round_rate(unsigned long rate, return timing->rate; } +static void tegra_emc_rate_requests_init(struct tegra_emc *emc) +{ + unsigned int i; + + for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate = 0; + emc->requested_rate[i].max_rate = ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = emc->requested_rate; + unsigned long min_rate = 0, max_rate = ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i == type) { + min_rate = max(new_min_rate, min_rate); + max_rate = min(new_max_rate, max_rate); + } else { + min_rate = max(req->min_rate, min_rate); + max_rate = min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + /* + * EMC rate-changes should go via OPP API because it manages voltage + * changes. + */ + err = dev_pm_opp_set_rate(emc->dev, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate = new_min_rate; + emc->requested_rate[type].max_rate = new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -571,7 +694,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_min_rate(emc->clk, rate); + err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -601,7 +724,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_max_rate(emc->clk, rate); + err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -658,6 +781,177 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + unsigned int dram_data_bus_width_bytes; + int err; + + /* + * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data + * is sampled on both clock edges. This means that EMC clock rate + * equals to the peak data-rate. + */ + dram_data_bus_width_bytes = emc->dram_bus_width / 8; + do_div(rate, dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc; + struct icc_node *node; + int err; + + emc->mc = devm_tegra_memory_controller_get(emc->dev); + if (IS_ERR(emc->mc)) + return PTR_ERR(emc->mc); + + soc = emc->mc->soc; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + struct opp_table *opp_table; + const char *rname = "core"; + int err; + + /* + * Legacy device-trees don't have OPP table and EMC driver isn't + * useful in this case. + */ + if (!device_property_present(emc->dev, "operating-points-v2")) { + dev_err(emc->dev, + "OPP table not found, please update your device tree\n"); + return -ENODEV; + } + + /* voltage scaling is optional */ + if (device_property_present(emc->dev, "core-supply")) + opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + else + opp_table = dev_pm_opp_get_opp_table(emc->dev); + + if (IS_ERR(opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(opp_table), + "failed to prepare OPP table\n"); + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + goto put_table; + } + + dev_info(emc->dev, "current clock rate %lu MHz\n", + clk_get_rate(emc->clk) / 1000000); + + /* first dummy rate-set initializes voltage state */ + err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); + if (err) { + dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_table: + dev_pm_opp_put_regulators(opp_table); + + return err; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -674,6 +968,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (!emc) return -ENOMEM; + mutex_init(&emc->rate_lock); emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; emc->dev = &pdev->dev; @@ -716,8 +1011,14 @@ static int tegra_emc_probe(struct platform_device *pdev) goto unset_cb; } + err = tegra_emc_opp_table_init(emc); + if (err) + goto unreg_notifier; + platform_set_drvdata(pdev, emc); + tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some @@ -728,6 +1029,8 @@ static int tegra_emc_probe(struct platform_device *pdev) return 0; +unreg_notifier: + clk_notifier_unregister(emc->clk, &emc->clk_nb); unset_cb: tegra20_clk_set_emc_round_callback(NULL, NULL); @@ -746,6 +1049,7 @@ static struct platform_driver tegra_emc_driver = { .name = "tegra20-emc", .of_match_table = tegra_emc_of_match, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index a8098bff91d9..29ecf02805a0 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -3,6 +3,10 @@ * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. */ +#include +#include +#include + #include #include "mc.h" @@ -280,6 +284,78 @@ static const struct tegra_mc_reset_ops tegra20_mc_reset_ops = { .reset_status = tegra20_mc_reset_status, }; +static int tegra20_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + /* + * It should be possible to tune arbitration knobs here, but the + * default values are known to work well on all devices. Hence + * nothing to do here so far. + */ + return 0; +} + +static int tegra20_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 300); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra20_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + unsigned int i, idx = spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != idx) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + ndata->node = node; + + /* these clients are isochronous by default */ + if (strstarts(node->name, "display") || + strstarts(node->name, "vi")) + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + else + ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; + + return ndata; + } + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra20_mc_icc_ops = { + .xlate_extended = tegra20_mc_of_icc_xlate_extended, + .aggregate = tegra20_mc_icc_aggreate, + .set = tegra20_mc_icc_set, +}; + const struct tegra_mc_soc tegra20_mc_soc = { .clients = tegra20_mc_clients, .num_clients = ARRAY_SIZE(tegra20_mc_clients), @@ -290,4 +366,5 @@ const struct tegra_mc_soc tegra20_mc_soc = { .reset_ops = &tegra20_mc_reset_ops, .resets = tegra20_mc_resets, .num_resets = ARRAY_SIZE(tegra20_mc_resets), + .icc_ops = &tegra20_mc_icc_ops, }; -- cgit v1.2.3 From 3a0b6b5abfddd0baf0a053aec7e8be59cf33b659 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:31 +0300 Subject: memory: tegra: Correct stub of devm_tegra_memory_controller_get() Correct typo in a stub of devm_tegra_memory_controller_get() to fix a non-ARM kernel compile-testing. Reported-by: Stephen Rothwell Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- include/soc/tegra/mc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h index 43876216de34..d731407e23bb 100644 --- a/include/soc/tegra/mc.h +++ b/include/soc/tegra/mc.h @@ -207,7 +207,7 @@ struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev); static inline struct tegra_mc * devm_tegra_memory_controller_get(struct device *dev) { - ERR_PTR(-ENODEV); + return ERR_PTR(-ENODEV); } #endif -- cgit v1.2.3 From de47653bd4dd3c1bf38c9983cf19556cab4c4211 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:32 +0300 Subject: memory: tegra20-emc: Use dev_pm_opp_set_clkname() The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use dev_pm_opp_set_clkname() instead. Suggested-by: Viresh Kumar Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 5e10aa97809f..bb3f315c9587 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -902,7 +902,7 @@ err_msg: static int tegra_emc_opp_table_init(struct tegra_emc *emc) { - struct opp_table *opp_table; + struct opp_table *reg_opp_table = NULL, *clk_opp_table; const char *rname = "core"; int err; @@ -917,19 +917,24 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) } /* voltage scaling is optional */ - if (device_property_present(emc->dev, "core-supply")) - opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); - else - opp_table = dev_pm_opp_get_opp_table(emc->dev); + if (device_property_present(emc->dev, "core-supply")) { + reg_opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); + if (IS_ERR(reg_opp_table)) + return dev_err_probe(emc->dev, PTR_ERR(reg_opp_table), + "failed to set OPP regulator\n"); + } - if (IS_ERR(opp_table)) - return dev_err_probe(emc->dev, PTR_ERR(opp_table), - "failed to prepare OPP table\n"); + clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL); + err = PTR_ERR_OR_ZERO(clk_opp_table); + if (err) { + dev_err(emc->dev, "failed to set OPP clk: %d\n", err); + goto put_reg_table; + } err = dev_pm_opp_of_add_table(emc->dev); if (err) { dev_err(emc->dev, "failed to add OPP table: %d\n", err); - goto put_table; + goto put_clk_table; } dev_info(emc->dev, "current clock rate %lu MHz\n", @@ -946,8 +951,11 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) remove_table: dev_pm_opp_of_remove_table(emc->dev); -put_table: - dev_pm_opp_put_regulators(opp_table); +put_clk_table: + dev_pm_opp_put_clkname(clk_opp_table); +put_reg_table: + if (reg_opp_table) + dev_pm_opp_put_regulators(reg_opp_table); return err; } -- cgit v1.2.3 From cba3902b0c3df42969231358a5e8b3d40212b7ad Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:33 +0300 Subject: memory: tegra20-emc: Factor out clk initialization Factor out clk initialization and make it resource-managed. This makes easier to follow code and will help to make further changes cleaner. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 70 +++++++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 23 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index bb3f315c9587..d01b556a6d06 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -960,6 +960,49 @@ put_reg_table: return err; } +static void devm_tegra_emc_unset_callback(void *data) +{ + tegra20_clk_set_emc_round_callback(NULL, NULL); +} + +static void devm_tegra_emc_unreg_clk_notifier(void *data) +{ + struct tegra_emc *emc = data; + + clk_notifier_unregister(emc->clk, &emc->clk_nb); +} + +static int tegra_emc_init_clk(struct tegra_emc *emc) +{ + int err; + + tegra20_clk_set_emc_round_callback(emc_round_rate, emc); + + err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, + NULL); + if (err) + return err; + + emc->clk = devm_clk_get(emc->dev, NULL); + if (IS_ERR(emc->clk)) { + dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); + return PTR_ERR(emc->clk); + } + + err = clk_notifier_register(emc->clk, &emc->clk_nb); + if (err) { + dev_err(emc->dev, "failed to register clk notifier: %d\n", err); + return err; + } + + err = devm_add_action_or_reset(emc->dev, + devm_tegra_emc_unreg_clk_notifier, emc); + if (err) + return err; + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1003,25 +1046,13 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; } - tegra20_clk_set_emc_round_callback(emc_round_rate, emc); - - emc->clk = devm_clk_get(&pdev->dev, "emc"); - if (IS_ERR(emc->clk)) { - err = PTR_ERR(emc->clk); - dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); - goto unset_cb; - } - - err = clk_notifier_register(emc->clk, &emc->clk_nb); - if (err) { - dev_err(&pdev->dev, "failed to register clk notifier: %d\n", - err); - goto unset_cb; - } + err = tegra_emc_init_clk(emc); + if (err) + return err; err = tegra_emc_opp_table_init(emc); if (err) - goto unreg_notifier; + return err; platform_set_drvdata(pdev, emc); tegra_emc_rate_requests_init(emc); @@ -1036,13 +1067,6 @@ static int tegra_emc_probe(struct platform_device *pdev) try_module_get(THIS_MODULE); return 0; - -unreg_notifier: - clk_notifier_unregister(emc->clk, &emc->clk_nb); -unset_cb: - tegra20_clk_set_emc_round_callback(NULL, NULL); - - return err; } static const struct of_device_id tegra_emc_of_match[] = { -- cgit v1.2.3 From e09312fec1d48c090bc3a4f13c6a01cb94bd5432 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:35 +0300 Subject: memory: tegra20-emc: Remove IRQ number from error message Remove IRQ number from error message since it doesn't add any useful information, especially because this number is virtual. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-6-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index d01b556a6d06..df758cebbd9d 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -1042,7 +1042,7 @@ static int tegra_emc_probe(struct platform_device *pdev) err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, dev_name(&pdev->dev), emc); if (err) { - dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); + dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); return err; } -- cgit v1.2.3 From dedf62d6f17fc9cf0389602b6d3d7533cc218679 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:34 +0300 Subject: memory: tegra20-emc: Add devfreq support Add devfreq support to the Tegra20 EMC driver. Memory utilization statistics will be periodically polled from the memory controller and appropriate minimum clock rate will be selected by the devfreq governor. Signed-off-by: Dmitry Osipenko Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20201111011456.7875-5-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 3 +- drivers/memory/tegra/tegra20-emc.c | 90 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 92 insertions(+), 1 deletion(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index ac3dfe155505..8cc1ec5be443 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -12,7 +12,8 @@ config TEGRA20_EMC tristate "NVIDIA Tegra20 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_2x_SOC - select PM_OPP + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select PM_DEVFREQ help This driver is for the External Memory Controller (EMC) found on Tegra20 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index df758cebbd9d..0320d9df4a20 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -102,6 +103,10 @@ #define EMC_FBIO_CFG5_DRAM_WIDTH_X16 BIT(4) +#define EMC_PWR_GATHER_CLEAR (1 << 8) +#define EMC_PWR_GATHER_DISABLE (2 << 8) +#define EMC_PWR_GATHER_ENABLE (3 << 8) + static const u16 emc_timing_registers[] = { EMC_RC, EMC_RFC, @@ -157,6 +162,7 @@ struct emc_timing { }; enum emc_rate_request_type { + EMC_RATE_DEVFREQ, EMC_RATE_DEBUG, EMC_RATE_ICC, EMC_RATE_TYPE_MAX, @@ -193,6 +199,8 @@ struct tegra_emc { /* protect shared rate-change code path */ struct mutex rate_lock; + + struct devfreq_simple_ondemand_data ondemand_data; }; static irqreturn_t tegra_emc_isr(int irq, void *data) @@ -1003,6 +1011,87 @@ static int tegra_emc_init_clk(struct tegra_emc *emc) return 0; } +static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct tegra_emc *emc = dev_get_drvdata(dev); + struct dev_pm_opp *opp; + unsigned long rate; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) { + dev_err(dev, "failed to find opp for %lu Hz\n", *freq); + return PTR_ERR(opp); + } + + rate = dev_pm_opp_get_freq(opp); + dev_pm_opp_put(opp); + + return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ); +} + +static int tegra_emc_devfreq_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct tegra_emc *emc = dev_get_drvdata(dev); + + /* freeze counters */ + writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); + + /* + * busy_time: number of clocks EMC request was accepted + * total_time: number of clocks PWR_GATHER control was set to ENABLE + */ + stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); + stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); + stat->current_frequency = clk_get_rate(emc->clk); + + /* clear counters and restart */ + writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); + writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); + + return 0; +} + +static struct devfreq_dev_profile tegra_emc_devfreq_profile = { + .polling_ms = 30, + .target = tegra_emc_devfreq_target, + .get_dev_status = tegra_emc_devfreq_get_dev_status, +}; + +static int tegra_emc_devfreq_init(struct tegra_emc *emc) +{ + struct devfreq *devfreq; + + /* + * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold + * should be less than 50. Secondly, multiple active memory clients + * may cause over 20% of lost clock cycles due to stalls caused by + * competing memory accesses. This means that threshold should be + * set to a less than 30 in order to have a properly working governor. + */ + emc->ondemand_data.upthreshold = 20; + + /* + * Reset statistic gathers state, select global bandwidth for the + * statistics collection mode and set clocks counter saturation + * limit to maximum. + */ + writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); + writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); + writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); + + devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, + DEVFREQ_GOV_SIMPLE_ONDEMAND, + &emc->ondemand_data); + if (IS_ERR(devfreq)) { + dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq); + return PTR_ERR(devfreq); + } + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1058,6 +1147,7 @@ static int tegra_emc_probe(struct platform_device *pdev) tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); tegra_emc_interconnect_init(emc); + tegra_emc_devfreq_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some -- cgit v1.2.3 From 1d1564aabc697d53f19ef40b06d68dc8bde36ad4 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:36 +0300 Subject: memory: tegra30: Add FIFO sizes to memory clients The latency allowness is calculated based on buffering capabilities of memory clients. Add FIFO sizes to the Tegra30 memory clients. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-7-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra30.c | 66 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index b1990b4133d8..d0314f29608d 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -42,6 +42,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0, }, + .fifo_size = 16 * 2, }, { .id = 0x01, .name = "display0a", @@ -56,6 +57,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x02, .name = "display0ab", @@ -70,6 +72,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x03, .name = "display0b", @@ -84,6 +87,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x04, .name = "display0bb", @@ -98,6 +102,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x05, .name = "display0c", @@ -112,6 +117,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x06, .name = "display0cb", @@ -126,6 +132,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 128, }, { .id = 0x07, .name = "display1b", @@ -140,6 +147,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x08, .name = "display1bb", @@ -154,6 +162,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x4e, }, + .fifo_size = 16 * 64, }, { .id = 0x09, .name = "eppup", @@ -168,6 +177,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x17, }, + .fifo_size = 16 * 8, }, { .id = 0x0a, .name = "g2pr", @@ -182,6 +192,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x09, }, + .fifo_size = 16 * 64, }, { .id = 0x0b, .name = "g2sr", @@ -196,6 +207,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x09, }, + .fifo_size = 16 * 64, }, { .id = 0x0c, .name = "mpeunifbr", @@ -210,6 +222,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x50, }, + .fifo_size = 16 * 8, }, { .id = 0x0d, .name = "viruv", @@ -224,6 +237,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2c, }, + .fifo_size = 16 * 8, }, { .id = 0x0e, .name = "afir", @@ -238,6 +252,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 32, }, { .id = 0x0f, .name = "avpcarm7r", @@ -252,6 +267,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 2, }, { .id = 0x10, .name = "displayhc", @@ -266,6 +282,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 2, }, { .id = 0x11, .name = "displayhcb", @@ -280,6 +297,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 2, }, { .id = 0x12, .name = "fdcdrd", @@ -294,6 +312,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x13, .name = "fdcdrd2", @@ -308,6 +327,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x14, .name = "g2dr", @@ -322,6 +342,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x15, .name = "hdar", @@ -336,6 +357,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x16, .name = "host1xdmar", @@ -350,6 +372,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x05, }, + .fifo_size = 16 * 16, }, { .id = 0x17, .name = "host1xr", @@ -364,6 +387,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x50, }, + .fifo_size = 16 * 8, }, { .id = 0x18, .name = "idxsrd", @@ -378,6 +402,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x19, .name = "idxsrd2", @@ -392,6 +417,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x1a, .name = "mpe_ipred", @@ -406,6 +432,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x80, }, + .fifo_size = 16 * 2, }, { .id = 0x1b, .name = "mpeamemrd", @@ -420,6 +447,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x42, }, + .fifo_size = 16 * 64, }, { .id = 0x1c, .name = "mpecsrd", @@ -434,6 +462,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x1d, .name = "ppcsahbdmar", @@ -448,6 +477,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 2, }, { .id = 0x1e, .name = "ppcsahbslvr", @@ -462,6 +492,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 8, }, { .id = 0x1f, .name = "satar", @@ -476,6 +507,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x33, }, + .fifo_size = 16 * 32, }, { .id = 0x20, .name = "texsrd", @@ -490,6 +522,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x21, .name = "texsrd2", @@ -504,6 +537,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 64, }, { .id = 0x22, .name = "vdebsevr", @@ -518,6 +552,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x23, .name = "vdember", @@ -532,6 +567,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xd0, }, + .fifo_size = 16 * 4, }, { .id = 0x24, .name = "vdemcer", @@ -546,6 +582,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2a, }, + .fifo_size = 16 * 16, }, { .id = 0x25, .name = "vdetper", @@ -560,6 +597,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x74, }, + .fifo_size = 16 * 16, }, { .id = 0x26, .name = "mpcorelpr", @@ -570,6 +608,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 14, }, { .id = 0x27, .name = "mpcorer", @@ -580,6 +619,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x04, }, + .fifo_size = 16 * 14, }, { .id = 0x28, .name = "eppu", @@ -594,6 +634,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x29, .name = "eppv", @@ -608,6 +649,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x2a, .name = "eppy", @@ -622,6 +664,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x6c, }, + .fifo_size = 16 * 64, }, { .id = 0x2b, .name = "mpeunifbw", @@ -636,6 +679,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x13, }, + .fifo_size = 16 * 8, }, { .id = 0x2c, .name = "viwsb", @@ -650,6 +694,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 64, }, { .id = 0x2d, .name = "viwu", @@ -664,6 +709,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xb2, }, + .fifo_size = 16 * 64, }, { .id = 0x2e, .name = "viwv", @@ -678,6 +724,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xb2, }, + .fifo_size = 16 * 64, }, { .id = 0x2f, .name = "viwy", @@ -692,6 +739,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x12, }, + .fifo_size = 16 * 64, }, { .id = 0x30, .name = "g2dw", @@ -706,6 +754,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x9, }, + .fifo_size = 16 * 128, }, { .id = 0x31, .name = "afiw", @@ -720,6 +769,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0c, }, + .fifo_size = 16 * 32, }, { .id = 0x32, .name = "avpcarm7w", @@ -734,6 +784,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 2, }, { .id = 0x33, .name = "fdcdwr", @@ -748,6 +799,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x34, .name = "fdcdwr2", @@ -762,6 +814,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0a, }, + .fifo_size = 16 * 48, }, { .id = 0x35, .name = "hdaw", @@ -776,6 +829,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x36, .name = "host1xw", @@ -790,6 +844,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 32, }, { .id = 0x37, .name = "ispw", @@ -804,6 +859,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 64, }, { .id = 0x38, .name = "mpcorelpw", @@ -814,6 +870,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 24, }, { .id = 0x39, .name = "mpcorew", @@ -824,6 +881,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x0e, }, + .fifo_size = 16 * 24, }, { .id = 0x3a, .name = "mpecswr", @@ -838,6 +896,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 8, }, { .id = 0x3b, .name = "ppcsahbdmaw", @@ -852,6 +911,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x10, }, + .fifo_size = 16 * 2, }, { .id = 0x3c, .name = "ppcsahbslvw", @@ -866,6 +926,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x06, }, + .fifo_size = 16 * 4, }, { .id = 0x3d, .name = "sataw", @@ -880,6 +941,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x33, }, + .fifo_size = 16 * 32, }, { .id = 0x3e, .name = "vdebsevw", @@ -894,6 +956,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 4, }, { .id = 0x3f, .name = "vdedbgw", @@ -908,6 +971,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0xff, }, + .fifo_size = 16 * 16, }, { .id = 0x40, .name = "vdembew", @@ -922,6 +986,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x42, }, + .fifo_size = 16 * 2, }, { .id = 0x41, .name = "vdetpmw", @@ -936,6 +1001,7 @@ static const struct tegra_mc_client tegra30_mc_clients[] = { .mask = 0xff, .def = 0x2a, }, + .fifo_size = 16 * 16, }, }; -- cgit v1.2.3 From 0c56eda86f8cad705d7d14e81e0e4efaeeaf4613 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:37 +0300 Subject: memory: tegra30-emc: Make driver modular Add modularization support to the Tegra30 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-8-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 2 +- drivers/memory/tegra/mc.c | 3 +++ drivers/memory/tegra/tegra30-emc.c | 17 ++++++++++++----- 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 8cc1ec5be443..2a4a16bcf91c 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -21,7 +21,7 @@ config TEGRA20_EMC external memory. config TEGRA30_EMC - bool "NVIDIA Tegra30 External Memory Controller driver" + tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC help diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index a7e6a8e4c95a..44064de962c2 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -346,6 +347,7 @@ int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) return 0; } +EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) { @@ -357,6 +359,7 @@ unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) return dram_count; } +EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); static int load_one_timing(struct tegra_mc *mc, struct tegra_mc_timing *timing, diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 1be28e28ec34..d0926088360a 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1330,6 +1330,13 @@ static int tegra_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); tegra_emc_debugfs_init(emc); + /* + * Don't allow the kernel module to be unloaded. Unloading adds some + * extra complexity which doesn't really worth the effort in a case of + * this driver. + */ + try_module_get(THIS_MODULE); + return 0; unset_cb: @@ -1380,6 +1387,7 @@ static const struct of_device_id tegra_emc_of_match[] = { { .compatible = "nvidia,tegra30-emc", }, {}, }; +MODULE_DEVICE_TABLE(of, tegra_emc_of_match); static struct platform_driver tegra_emc_driver = { .probe = tegra_emc_probe, @@ -1390,9 +1398,8 @@ static struct platform_driver tegra_emc_driver = { .suppress_bind_attrs = true, }, }; +module_platform_driver(tegra_emc_driver); -static int __init tegra_emc_init(void) -{ - return platform_driver_register(&tegra_emc_driver); -} -subsys_initcall(tegra_emc_init); +MODULE_AUTHOR("Dmitry Osipenko "); +MODULE_DESCRIPTION("NVIDIA Tegra30 EMC driver"); +MODULE_LICENSE("GPL v2"); -- cgit v1.2.3 From bf25f3fceffa9e4e5b5a59ed51511ec5ba6a6036 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Wed, 11 Nov 2020 04:14:38 +0300 Subject: memory: tegra30-emc: Continue probing if timings are missing in device-tree EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-9-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra30-emc.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index d0926088360a..3488786da03b 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -988,6 +988,11 @@ static struct device_node *emc_find_node_by_ram_code(struct device *dev) u32 value, ram_code; int err; + if (of_get_child_count(dev->of_node) == 0) { + dev_info(dev, "device-tree doesn't have memory timings\n"); + return NULL; + } + ram_code = tegra_read_ram_code(); for_each_child_of_node(dev->of_node, np) { @@ -1057,6 +1062,9 @@ static long emc_round_rate(unsigned long rate, struct tegra_emc *emc = arg; unsigned int i; + if (!emc->num_timings) + return clk_get_rate(emc->clk); + min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); for (i = 0; i < emc->num_timings; i++) { @@ -1262,16 +1270,6 @@ static int tegra_emc_probe(struct platform_device *pdev) struct tegra_emc *emc; int err; - if (of_get_child_count(pdev->dev.of_node) == 0) { - dev_info(&pdev->dev, - "device-tree node doesn't have memory timings\n"); - return -ENODEV; - } - - np = emc_find_node_by_ram_code(&pdev->dev); - if (!np) - return -EINVAL; - emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); if (!emc) { of_node_put(np); @@ -1285,10 +1283,13 @@ static int tegra_emc_probe(struct platform_device *pdev) emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; - err = emc_load_timings_from_dt(emc, np); - of_node_put(np); - if (err) - return err; + np = emc_find_node_by_ram_code(&pdev->dev); + if (np) { + err = emc_load_timings_from_dt(emc, np); + of_node_put(np); + if (err) + return err; + } emc->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(emc->regs)) -- cgit v1.2.3 From 4a91b11c0a100532c466e07a1372d134ab0e753d Mon Sep 17 00:00:00 2001 From: Nicolin Chen Date: Wed, 7 Oct 2020 17:37:46 -0700 Subject: memory: tegra: Complete tegra210_swgroups According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them to the list. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by: Nicolin Chen Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201008003746.25659-6-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra210.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/memory/tegra/tegra210.c b/drivers/memory/tegra/tegra210.c index b400802c9f14..b3bbc5a05ba1 100644 --- a/drivers/memory/tegra/tegra210.c +++ b/drivers/memory/tegra/tegra210.c @@ -1028,6 +1028,8 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = { { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 }, { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 }, { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 }, + { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 }, + { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c }, { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 }, { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 }, { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 }, @@ -1036,19 +1038,27 @@ static const struct tegra_smmu_swgroup tegra210_swgroups[] = { { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c }, { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 }, { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 }, + { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 }, + { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 }, { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 }, { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 }, { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c }, { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 }, { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 }, { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac }, + { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 }, { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 }, { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 }, { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc }, { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 }, + { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 }, + { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 }, { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc }, { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 }, { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 }, + { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 }, + { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc }, + { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 }, }; static const unsigned int tegra210_group_display[] = { -- cgit v1.2.3 From 0e1bcf2c05d0a681c04351fbd60812aea99354b6 Mon Sep 17 00:00:00 2001 From: Nathan Chancellor Date: Thu, 19 Nov 2020 12:52:44 -0700 Subject: memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probe Clang warns: drivers/memory/tegra/tegra30-emc.c:1275:15: warning: variable 'np' is uninitialized when used here [-Wuninitialized] of_node_put(np); ^~ drivers/memory/tegra/tegra30-emc.c:1269:24: note: initialize the variable 'np' to silence this warning There does not need to be an of_node_put call in this error handling block after the shuffling of the np assignment. Remove it so there is no use of uninitialized memory. Fixes: 5e00fd90183a ("memory: tegra30-emc: Continue probing if timings are missing in device-tree") Signed-off-by: Nathan Chancellor Reviewed-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201119195244.1517236-1-natechancellor@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra30-emc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 3488786da03b..93f9002d32ad 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -1271,10 +1271,8 @@ static int tegra_emc_probe(struct platform_device *pdev) int err; emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); - if (!emc) { - of_node_put(np); + if (!emc) return -ENOMEM; - } emc->mc = devm_tegra_memory_controller_get(&pdev->dev); if (IS_ERR(emc->mc)) -- cgit v1.2.3 From 59b644b01cf48d6042f3c5983d464921a4920845 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Fri, 30 Oct 2020 12:36:08 +0100 Subject: soc: mediatek: Add MediaTek SCPSYS power domains The System Control Processor System (SCPSYS) has several power management related tasks in the system. This driver implements support to handle the different power domains supported in order to meet high performance and low power requirements. Co-developed-by: Matthias Brugger Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-3-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/Kconfig | 13 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mt8173-pm-domains.h | 96 +++++++ drivers/soc/mediatek/mtk-pm-domains.c | 456 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.h | 65 +++++ 5 files changed, 631 insertions(+) create mode 100644 drivers/soc/mediatek/mt8173-pm-domains.h create mode 100644 drivers/soc/mediatek/mtk-pm-domains.c create mode 100644 drivers/soc/mediatek/mtk-pm-domains.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 59a56cd790ec..68d800f9e4a5 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -44,6 +44,19 @@ config MTK_SCPSYS Say yes here to add support for the MediaTek SCPSYS power domain driver. +config MTK_SCPSYS_PM_DOMAINS + bool "MediaTek SCPSYS generic power domain" + default ARCH_MEDIATEK + depends on PM + depends on MTK_INFRACFG + select PM_GENERIC_DOMAINS + select REGMAP + help + Say y here to enable power domain support. + In order to meet high performance and low power requirements, the System + Control Processor System (SCPSYS) has several power management related + tasks in the system. + config MTK_MMSYS bool "MediaTek MMSYS Support" default ARCH_MEDIATEK diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 01f9f873634a..1e60fb4f89d4 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o +obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h new file mode 100644 index 000000000000..5f2b5d4ad02b --- /dev/null +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8173_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8173_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8173 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { + [MT8173_POWER_DOMAIN_VDEC] = { + .sta_mask = PWR_STATUS_VDEC, + .ctl_offs = SPM_VDE_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8173_POWER_DOMAIN_VENC] = { + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = SPM_VEN_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT8173_POWER_DOMAIN_ISP] = { + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = SPM_ISP_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + }, + [MT8173_POWER_DOMAIN_MM] = { + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = SPM_DIS_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + .bus_prot_reg_update = true, + .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1, + }, + }, + [MT8173_POWER_DOMAIN_VENC_LT] = { + .sta_mask = PWR_STATUS_VENC_LT, + .ctl_offs = SPM_VEN2_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT8173_POWER_DOMAIN_AUDIO] = { + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = SPM_AUDIO_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT8173_POWER_DOMAIN_USB] = { + .sta_mask = PWR_STATUS_USB, + .ctl_offs = SPM_USB_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8173_POWER_DOMAIN_MFG_ASYNC] = { + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = SPM_MFG_ASYNC_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = 0, + }, + [MT8173_POWER_DOMAIN_MFG_2D] = { + .sta_mask = PWR_STATUS_MFG_2D, + .ctl_offs = SPM_MFG_2D_PWR_CON, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + }, + [MT8173_POWER_DOMAIN_MFG] = { + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = SPM_MFG_PWR_CON, + .sram_pdn_bits = GENMASK(13, 8), + .sram_pdn_ack_bits = GENMASK(21, 16), + .bp_infracfg = { + .bus_prot_reg_update = true, + .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT, + }, + }, +}; + +static const struct scpsys_soc_data mt8173_scpsys_data = { + .domains_data = scpsys_domain_data_mt8173, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173), + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, +}; + +#endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c new file mode 100644 index 000000000000..f8e88308f2e0 --- /dev/null +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -0,0 +1,456 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020 Collabora Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mt8173-pm-domains.h" + +#define MTK_POLL_DELAY_US 10 +#define MTK_POLL_TIMEOUT USEC_PER_SEC + +#define PWR_RST_B_BIT BIT(0) +#define PWR_ISO_BIT BIT(1) +#define PWR_ON_BIT BIT(2) +#define PWR_ON_2ND_BIT BIT(3) +#define PWR_CLK_DIS_BIT BIT(4) + +struct scpsys_domain { + struct generic_pm_domain genpd; + const struct scpsys_domain_data *data; + struct scpsys *scpsys; + int num_clks; + struct clk_bulk_data *clks; + struct regmap *infracfg; +}; + +struct scpsys { + struct device *dev; + struct regmap *base; + const struct scpsys_soc_data *soc_data; + struct genpd_onecell_data pd_data; + struct generic_pm_domain *domains[]; +}; + +#define to_scpsys_domain(gpd) container_of(gpd, struct scpsys_domain, genpd) + +static bool scpsys_domain_is_on(struct scpsys_domain *pd) +{ + struct scpsys *scpsys = pd->scpsys; + u32 status, status2; + + regmap_read(scpsys->base, scpsys->soc_data->pwr_sta_offs, &status); + status &= pd->data->sta_mask; + + regmap_read(scpsys->base, scpsys->soc_data->pwr_sta2nd_offs, &status2); + status2 &= pd->data->sta_mask; + + /* A domain is on when both status bits are set. */ + return status && status2; +} + +static int scpsys_sram_enable(struct scpsys_domain *pd) +{ + u32 pdn_ack = pd->data->sram_pdn_ack_bits; + struct scpsys *scpsys = pd->scpsys; + unsigned int tmp; + + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits); + + /* Either wait until SRAM_PDN_ACK all 1 or 0 */ + return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, + (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); +} + +static int scpsys_sram_disable(struct scpsys_domain *pd) +{ + u32 pdn_ack = pd->data->sram_pdn_ack_bits; + struct scpsys *scpsys = pd->scpsys; + unsigned int tmp; + + regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits); + + /* Either wait until SRAM_PDN_ACK all 1 or 0 */ + return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, + (tmp & pdn_ack) == pdn_ack, MTK_POLL_DELAY_US, + MTK_POLL_TIMEOUT); +} + +static int scpsys_bus_protect_enable(struct scpsys_domain *pd) +{ + const struct scpsys_bus_prot_data *bp_data = &pd->data->bp_infracfg; + + if (!bp_data->bus_prot_mask) + return 0; + + return mtk_infracfg_set_bus_protection(pd->infracfg, bp_data->bus_prot_mask, + bp_data->bus_prot_reg_update); +} + +static int scpsys_bus_protect_disable(struct scpsys_domain *pd) +{ + const struct scpsys_bus_prot_data *bp_data = &pd->data->bp_infracfg; + + if (!bp_data->bus_prot_mask) + return 0; + + return mtk_infracfg_clear_bus_protection(pd->infracfg, bp_data->bus_prot_mask, + bp_data->bus_prot_reg_update); +} + +static int scpsys_power_on(struct generic_pm_domain *genpd) +{ + struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd); + struct scpsys *scpsys = pd->scpsys; + bool tmp; + int ret; + + ret = clk_bulk_enable(pd->num_clks, pd->clks); + if (ret) + return ret; + + /* subsys power on */ + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + + /* wait until PWR_ACK = 1 */ + ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, tmp, MTK_POLL_DELAY_US, + MTK_POLL_TIMEOUT); + if (ret < 0) + goto err_pwr_ack; + + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + + ret = scpsys_sram_enable(pd); + if (ret < 0) + goto err_pwr_ack; + + ret = scpsys_bus_protect_disable(pd); + if (ret < 0) + goto err_disable_sram; + + return 0; + +err_disable_sram: + scpsys_sram_disable(pd); +err_pwr_ack: + clk_bulk_disable(pd->num_clks, pd->clks); + return ret; +} + +static int scpsys_power_off(struct generic_pm_domain *genpd) +{ + struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd); + struct scpsys *scpsys = pd->scpsys; + bool tmp; + int ret; + + ret = scpsys_bus_protect_enable(pd); + if (ret < 0) + return ret; + + ret = scpsys_sram_disable(pd); + if (ret < 0) + return ret; + + /* subsys power off */ + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_CLK_DIS_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_2ND_BIT); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ON_BIT); + + /* wait until PWR_ACK = 0 */ + ret = readx_poll_timeout(scpsys_domain_is_on, pd, tmp, !tmp, MTK_POLL_DELAY_US, + MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + clk_bulk_disable(pd->num_clks, pd->clks); + + return 0; +} + +static struct +generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_node *node) +{ + const struct scpsys_domain_data *domain_data; + struct scpsys_domain *pd; + int i, ret; + u32 id; + + ret = of_property_read_u32(node, "reg", &id); + if (ret) { + dev_err(scpsys->dev, "%pOF: failed to retrieve domain id from reg: %d\n", + node, ret); + return ERR_PTR(-EINVAL); + } + + if (id >= scpsys->soc_data->num_domains) { + dev_err(scpsys->dev, "%pOF: invalid domain id %d\n", node, id); + return ERR_PTR(-EINVAL); + } + + domain_data = &scpsys->soc_data->domains_data[id]; + if (domain_data->sta_mask == 0) { + dev_err(scpsys->dev, "%pOF: undefined domain id %d\n", node, id); + return ERR_PTR(-EINVAL); + } + + pd = devm_kzalloc(scpsys->dev, sizeof(*pd), GFP_KERNEL); + if (!pd) + return ERR_PTR(-ENOMEM); + + pd->data = domain_data; + pd->scpsys = scpsys; + + pd->infracfg = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,infracfg"); + if (IS_ERR(pd->infracfg)) + return ERR_CAST(pd->infracfg); + + pd->num_clks = of_clk_get_parent_count(node); + if (pd->num_clks > 0) { + pd->clks = devm_kcalloc(scpsys->dev, pd->num_clks, sizeof(*pd->clks), GFP_KERNEL); + if (!pd->clks) + return ERR_PTR(-ENOMEM); + } + + for (i = 0; i < pd->num_clks; i++) { + pd->clks[i].clk = of_clk_get(node, i); + if (IS_ERR(pd->clks[i].clk)) { + dev_err(scpsys->dev, "%pOF: failed to get clk at index %d\n", + node, i); + return ERR_PTR(-EINVAL); + } + } + + ret = clk_bulk_prepare(pd->num_clks, pd->clks); + if (ret) + goto err_put_clocks; + + /* + * Initially turn on all domains to make the domains usable + * with !CONFIG_PM and to get the hardware in sync with the + * software. The unused domains will be switched off during + * late_init time. + */ + ret = scpsys_power_on(&pd->genpd); + if (ret < 0) { + dev_err(scpsys->dev, "%pOF: failed to power on domain: %d\n", node, ret); + goto err_unprepare_clocks; + } + + if (scpsys->domains[id]) { + ret = -EINVAL; + dev_err(scpsys->dev, + "power domain with id %d already exists, check your device-tree\n", id); + goto err_unprepare_clocks; + } + + pd->genpd.name = node->name; + pd->genpd.power_off = scpsys_power_off; + pd->genpd.power_on = scpsys_power_on; + + pm_genpd_init(&pd->genpd, NULL, false); + scpsys->domains[id] = &pd->genpd; + + return scpsys->pd_data.domains[id]; + +err_unprepare_clocks: + clk_bulk_unprepare(pd->num_clks, pd->clks); +err_put_clocks: + clk_bulk_put(pd->num_clks, pd->clks); + return ERR_PTR(ret); +} + +static int scpsys_add_subdomain(struct scpsys *scpsys, struct device_node *parent) +{ + struct generic_pm_domain *child_pd, *parent_pd; + struct device_node *child; + int ret; + + for_each_child_of_node(parent, child) { + u32 id; + + ret = of_property_read_u32(parent, "reg", &id); + if (ret) { + dev_err(scpsys->dev, "%pOF: failed to get parent domain id\n", child); + goto err_put_node; + } + + if (!scpsys->pd_data.domains[id]) { + ret = -EINVAL; + dev_err(scpsys->dev, "power domain with id %d does not exist\n", id); + goto err_put_node; + } + + parent_pd = scpsys->pd_data.domains[id]; + + child_pd = scpsys_add_one_domain(scpsys, child); + if (IS_ERR(child_pd)) { + ret = PTR_ERR(child_pd); + dev_err(scpsys->dev, "%pOF: failed to get child domain id\n", child); + goto err_put_node; + } + + ret = pm_genpd_add_subdomain(parent_pd, child_pd); + if (ret) { + dev_err(scpsys->dev, "failed to add %s subdomain to parent %s\n", + child_pd->name, parent_pd->name); + goto err_put_node; + } else { + dev_dbg(scpsys->dev, "%s add subdomain: %s\n", parent_pd->name, + child_pd->name); + } + + /* recursive call to add all subdomains */ + ret = scpsys_add_subdomain(scpsys, child); + if (ret) + goto err_put_node; + } + + return 0; + +err_put_node: + of_node_put(child); + return ret; +} + +static void scpsys_remove_one_domain(struct scpsys_domain *pd) +{ + int ret; + + /* + * We're in the error cleanup already, so we only complain, + * but won't emit another error on top of the original one. + */ + ret = pm_genpd_remove(&pd->genpd); + if (ret < 0) + dev_err(pd->scpsys->dev, + "failed to remove domain '%s' : %d - state may be inconsistent\n", + pd->genpd.name, ret); + + scpsys_power_off(&pd->genpd); + + clk_bulk_unprepare(pd->num_clks, pd->clks); + clk_bulk_put(pd->num_clks, pd->clks); +} + +static void scpsys_domain_cleanup(struct scpsys *scpsys) +{ + struct generic_pm_domain *genpd; + struct scpsys_domain *pd; + int i; + + for (i = scpsys->pd_data.num_domains - 1; i >= 0; i--) { + genpd = scpsys->pd_data.domains[i]; + if (genpd) { + pd = to_scpsys_domain(genpd); + scpsys_remove_one_domain(pd); + } + } +} + +static const struct of_device_id scpsys_of_match[] = { + { + .compatible = "mediatek,mt8173-power-controller", + .data = &mt8173_scpsys_data, + }, + { } +}; + +static int scpsys_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + const struct scpsys_soc_data *soc; + struct device_node *node; + struct device *parent; + struct scpsys *scpsys; + int ret; + + soc = of_device_get_match_data(&pdev->dev); + if (!soc) { + dev_err(&pdev->dev, "no power controller data\n"); + return -EINVAL; + } + + scpsys = devm_kzalloc(dev, struct_size(scpsys, domains, soc->num_domains), GFP_KERNEL); + if (!scpsys) + return -ENOMEM; + + scpsys->dev = dev; + scpsys->soc_data = soc; + + scpsys->pd_data.domains = scpsys->domains; + scpsys->pd_data.num_domains = soc->num_domains; + + parent = dev->parent; + if (!parent) { + dev_err(dev, "no parent for syscon devices\n"); + return -ENODEV; + } + + scpsys->base = syscon_node_to_regmap(parent->of_node); + if (IS_ERR(scpsys->base)) { + dev_err(dev, "no regmap available\n"); + return PTR_ERR(scpsys->base); + } + + ret = -ENODEV; + for_each_available_child_of_node(np, node) { + struct generic_pm_domain *domain; + + domain = scpsys_add_one_domain(scpsys, node); + if (IS_ERR(domain)) { + ret = PTR_ERR(domain); + of_node_put(node); + goto err_cleanup_domains; + } + + ret = scpsys_add_subdomain(scpsys, node); + if (ret) { + of_node_put(node); + goto err_cleanup_domains; + } + } + + if (ret) { + dev_dbg(dev, "no power domains present\n"); + return ret; + } + + ret = of_genpd_add_provider_onecell(np, &scpsys->pd_data); + if (ret) { + dev_err(dev, "failed to add provider: %d\n", ret); + goto err_cleanup_domains; + } + + return 0; + +err_cleanup_domains: + scpsys_domain_cleanup(scpsys); + return ret; +} + +static struct platform_driver scpsys_pm_domain_driver = { + .probe = scpsys_probe, + .driver = { + .name = "mtk-power-controller", + .suppress_bind_attrs = true, + .of_match_table = scpsys_of_match, + }, +}; +builtin_platform_driver(scpsys_pm_domain_driver); diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h new file mode 100644 index 000000000000..7c479021d404 --- /dev/null +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MTK_PM_DOMAINS_H +#define __SOC_MEDIATEK_MTK_PM_DOMAINS_H + +#define MTK_SCPD_ACTIVE_WAKEUP BIT(0) +#define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) + +#define SPM_VDE_PWR_CON 0x0210 +#define SPM_MFG_PWR_CON 0x0214 +#define SPM_VEN_PWR_CON 0x0230 +#define SPM_ISP_PWR_CON 0x0238 +#define SPM_DIS_PWR_CON 0x023c +#define SPM_VEN2_PWR_CON 0x0298 +#define SPM_AUDIO_PWR_CON 0x029c +#define SPM_MFG_2D_PWR_CON 0x02c0 +#define SPM_MFG_ASYNC_PWR_CON 0x02c4 +#define SPM_USB_PWR_CON 0x02cc + +#define SPM_PWR_STATUS 0x060c +#define SPM_PWR_STATUS_2ND 0x0610 + +#define PWR_STATUS_DISP BIT(3) +#define PWR_STATUS_MFG BIT(4) +#define PWR_STATUS_ISP BIT(5) +#define PWR_STATUS_VDEC BIT(7) +#define PWR_STATUS_VENC_LT BIT(20) +#define PWR_STATUS_VENC BIT(21) +#define PWR_STATUS_MFG_2D BIT(22) +#define PWR_STATUS_MFG_ASYNC BIT(23) +#define PWR_STATUS_AUDIO BIT(24) +#define PWR_STATUS_USB BIT(25) + +struct scpsys_bus_prot_data { + u32 bus_prot_mask; + bool bus_prot_reg_update; +}; + +/** + * struct scpsys_domain_data - scp domain data for power on/off flow + * @sta_mask: The mask for power on/off status bit. + * @ctl_offs: The offset for main power control register. + * @sram_pdn_bits: The mask for sram power control bits. + * @sram_pdn_ack_bits: The mask for sram power control acked bits. + * @caps: The flag for active wake-up action. + * @bp_infracfg: bus protection for infracfg subsystem + */ +struct scpsys_domain_data { + u32 sta_mask; + int ctl_offs; + u32 sram_pdn_bits; + u32 sram_pdn_ack_bits; + u8 caps; + const struct scpsys_bus_prot_data bp_infracfg; +}; + +struct scpsys_soc_data { + const struct scpsys_domain_data *domains_data; + int num_domains; + int pwr_sta_offs; + int pwr_sta2nd_offs; +}; + +#endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ -- cgit v1.2.3 From 916d6d71ba56cfc19a0bfd8a0e181443a13cb865 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:10 +0100 Subject: soc: mediatek: pm-domains: Add bus protection protocol Bus protection will need to update more then one register in infracfg. Add support for several operations. Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-5-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8173-pm-domains.h | 4 ++-- drivers/soc/mediatek/mtk-pm-domains.c | 36 +++++++++++++++++++++++--------- drivers/soc/mediatek/mtk-pm-domains.h | 4 +++- 3 files changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h index 5f2b5d4ad02b..72b3acaf74fb 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -34,7 +34,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg = { + .bp_infracfg[0] = { .bus_prot_reg_update = true, .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | MT8173_TOP_AXI_PROT_EN_MM_M1, @@ -76,7 +76,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), - .bp_infracfg = { + .bp_infracfg[0] = { .bus_prot_reg_update = true, .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | MT8173_TOP_AXI_PROT_EN_MFG_M0 | diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index f8e88308f2e0..06a16e45356a 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -88,24 +88,40 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) static int scpsys_bus_protect_enable(struct scpsys_domain *pd) { - const struct scpsys_bus_prot_data *bp_data = &pd->data->bp_infracfg; + const struct scpsys_bus_prot_data *bpd = pd->data->bp_infracfg; + int i, ret; - if (!bp_data->bus_prot_mask) - return 0; + for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { + if (!bpd[i].bus_prot_mask) + break; - return mtk_infracfg_set_bus_protection(pd->infracfg, bp_data->bus_prot_mask, - bp_data->bus_prot_reg_update); + ret = mtk_infracfg_set_bus_protection(pd->infracfg, + bpd[i].bus_prot_mask, + bpd[i].bus_prot_reg_update); + if (ret) + return ret; + } + + return 0; } static int scpsys_bus_protect_disable(struct scpsys_domain *pd) { - const struct scpsys_bus_prot_data *bp_data = &pd->data->bp_infracfg; + const struct scpsys_bus_prot_data *bpd = pd->data->bp_infracfg; + int i, ret; - if (!bp_data->bus_prot_mask) - return 0; + for (i = SPM_MAX_BUS_PROT_DATA; i > 0; i--) { + if (!bpd[i].bus_prot_mask) + continue; - return mtk_infracfg_clear_bus_protection(pd->infracfg, bp_data->bus_prot_mask, - bp_data->bus_prot_reg_update); + ret = mtk_infracfg_clear_bus_protection(pd->infracfg, + bpd[i].bus_prot_mask, + bpd[i].bus_prot_reg_update); + if (ret) + return ret; + } + + return 0; } static int scpsys_power_on(struct generic_pm_domain *genpd) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 7c479021d404..125880a58170 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -32,6 +32,8 @@ #define PWR_STATUS_AUDIO BIT(24) #define PWR_STATUS_USB BIT(25) +#define SPM_MAX_BUS_PROT_DATA 5 + struct scpsys_bus_prot_data { u32 bus_prot_mask; bool bus_prot_reg_update; @@ -52,7 +54,7 @@ struct scpsys_domain_data { u32 sram_pdn_bits; u32 sram_pdn_ack_bits; u8 caps; - const struct scpsys_bus_prot_data bp_infracfg; + const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; }; struct scpsys_soc_data { -- cgit v1.2.3 From 928296ea5da37838d7127de4b10f47cd97401b13 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:11 +0100 Subject: soc: mediatek: pm_domains: Make bus protection generic Bus protection is not exclusively done by calling the infracfg misc driver. Make the calls for setting and clearing the bus protection generic so that we can use other blocks for it as well. Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-6-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/Kconfig | 1 - drivers/soc/mediatek/mtk-infracfg.c | 5 --- drivers/soc/mediatek/mtk-pm-domains.c | 57 +++++++++++++++++++++++++++-------- include/linux/soc/mediatek/infracfg.h | 5 +++ 4 files changed, 49 insertions(+), 19 deletions(-) diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 68d800f9e4a5..67cef12dc585 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -48,7 +48,6 @@ config MTK_SCPSYS_PM_DOMAINS bool "MediaTek SCPSYS generic power domain" default ARCH_MEDIATEK depends on PM - depends on MTK_INFRACFG select PM_GENERIC_DOMAINS select REGMAP help diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c index 4a123796aad3..0590b68e0d78 100644 --- a/drivers/soc/mediatek/mtk-infracfg.c +++ b/drivers/soc/mediatek/mtk-infracfg.c @@ -12,11 +12,6 @@ #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) -#define INFRA_TOPAXI_PROTECTEN 0x0220 -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 - /** * mtk_infracfg_set_bus_protection - enable bus protection * @infracfg: The infracfg regmap diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 06a16e45356a..6122701d018f 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -86,18 +86,24 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) MTK_POLL_TIMEOUT); } -static int scpsys_bus_protect_enable(struct scpsys_domain *pd) +static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, struct regmap *regmap) { - const struct scpsys_bus_prot_data *bpd = pd->data->bp_infracfg; int i, ret; for (i = 0; i < SPM_MAX_BUS_PROT_DATA; i++) { - if (!bpd[i].bus_prot_mask) + u32 val, mask = bpd[i].bus_prot_mask; + + if (!mask) break; - ret = mtk_infracfg_set_bus_protection(pd->infracfg, - bpd[i].bus_prot_mask, - bpd[i].bus_prot_reg_update); + if (bpd[i].bus_prot_reg_update) + regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); + else + regmap_write(regmap, INFRA_TOPAXI_PROTECTEN_SET, mask); + + ret = regmap_read_poll_timeout(regmap, INFRA_TOPAXI_PROTECTSTA1, + val, (val & mask) == mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; } @@ -105,18 +111,34 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) return 0; } -static int scpsys_bus_protect_disable(struct scpsys_domain *pd) +static int scpsys_bus_protect_enable(struct scpsys_domain *pd) +{ + int ret; + + ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); + + return ret; +} + +static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, + struct regmap *regmap) { - const struct scpsys_bus_prot_data *bpd = pd->data->bp_infracfg; int i, ret; - for (i = SPM_MAX_BUS_PROT_DATA; i > 0; i--) { - if (!bpd[i].bus_prot_mask) + for (i = SPM_MAX_BUS_PROT_DATA - 1; i >= 0; i--) { + u32 val, mask = bpd[i].bus_prot_mask; + + if (!mask) continue; - ret = mtk_infracfg_clear_bus_protection(pd->infracfg, - bpd[i].bus_prot_mask, - bpd[i].bus_prot_reg_update); + if (bpd[i].bus_prot_reg_update) + regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); + else + regmap_write(regmap, INFRA_TOPAXI_PROTECTEN_CLR, mask); + + ret = regmap_read_poll_timeout(regmap, INFRA_TOPAXI_PROTECTSTA1, + val, !(val & mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) return ret; } @@ -124,6 +146,15 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd) return 0; } +static int scpsys_bus_protect_disable(struct scpsys_domain *pd) +{ + int ret; + + ret = _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); + + return ret; +} + static int scpsys_power_on(struct generic_pm_domain *genpd) { struct scpsys_domain *pd = container_of(genpd, struct scpsys_domain, genpd); diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 233463d789c6..5bcaab767f6a 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -32,6 +32,11 @@ #define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ BIT(7) | BIT(8)) +#define INFRA_TOPAXI_PROTECTEN 0x0220 +#define INFRA_TOPAXI_PROTECTSTA1 0x0228 +#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 +#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 + #define REG_INFRA_MISC 0xf00 #define F_DDR_4GB_SUPPORT_EN BIT(13) -- cgit v1.2.3 From f414854c884364b8a563760054be615555a62b3a Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:12 +0100 Subject: soc: mediatek: pm-domains: Add SMI block as bus protection block Apart from the infracfg block, the SMI block is used to enable the bus protection for some power domains. Add support for this block. Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-7-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8173-pm-domains.h | 18 ++++++++---------- drivers/soc/mediatek/mtk-pm-domains.c | 23 ++++++++++++++++------- drivers/soc/mediatek/mtk-pm-domains.h | 25 +++++++++++++++++++++++++ 3 files changed, 49 insertions(+), 17 deletions(-) diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h index 72b3acaf74fb..3e8ee5dabb43 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -34,10 +34,9 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .ctl_offs = SPM_DIS_PWR_CON, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), - .bp_infracfg[0] = { - .bus_prot_reg_update = true, - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 | - MT8173_TOP_AXI_PROT_EN_MM_M1, + .bp_infracfg = { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 | + MT8173_TOP_AXI_PROT_EN_MM_M1), }, }, [MT8173_POWER_DOMAIN_VENC_LT] = { @@ -76,12 +75,11 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .ctl_offs = SPM_MFG_PWR_CON, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), - .bp_infracfg[0] = { - .bus_prot_reg_update = true, - .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S | - MT8173_TOP_AXI_PROT_EN_MFG_M0 | - MT8173_TOP_AXI_PROT_EN_MFG_M1 | - MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT, + .bp_infracfg = { + BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S | + MT8173_TOP_AXI_PROT_EN_MFG_M0 | + MT8173_TOP_AXI_PROT_EN_MFG_M1 | + MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT), }, }, }; diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 6122701d018f..8a21847464c2 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -32,6 +32,7 @@ struct scpsys_domain { int num_clks; struct clk_bulk_data *clks; struct regmap *infracfg; + struct regmap *smi; }; struct scpsys { @@ -99,9 +100,9 @@ static int _scpsys_bus_protect_enable(const struct scpsys_bus_prot_data *bpd, st if (bpd[i].bus_prot_reg_update) regmap_set_bits(regmap, bpd[i].bus_prot_set, mask); else - regmap_write(regmap, INFRA_TOPAXI_PROTECTEN_SET, mask); + regmap_write(regmap, bpd[i].bus_prot_set, mask); - ret = regmap_read_poll_timeout(regmap, INFRA_TOPAXI_PROTECTSTA1, + ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, val, (val & mask) == mask, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) @@ -116,8 +117,10 @@ static int scpsys_bus_protect_enable(struct scpsys_domain *pd) int ret; ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); + if (ret) + return ret; - return ret; + return _scpsys_bus_protect_enable(pd->data->bp_smi, pd->smi); } static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, @@ -134,9 +137,9 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, if (bpd[i].bus_prot_reg_update) regmap_clear_bits(regmap, bpd[i].bus_prot_clr, mask); else - regmap_write(regmap, INFRA_TOPAXI_PROTECTEN_CLR, mask); + regmap_write(regmap, bpd[i].bus_prot_clr, mask); - ret = regmap_read_poll_timeout(regmap, INFRA_TOPAXI_PROTECTSTA1, + ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, val, !(val & mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret) @@ -150,9 +153,11 @@ static int scpsys_bus_protect_disable(struct scpsys_domain *pd) { int ret; - ret = _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); + ret = _scpsys_bus_protect_disable(pd->data->bp_smi, pd->smi); + if (ret) + return ret; - return ret; + return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); } static int scpsys_power_on(struct generic_pm_domain *genpd) @@ -267,6 +272,10 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no if (IS_ERR(pd->infracfg)) return ERR_CAST(pd->infracfg); + pd->smi = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,smi"); + if (IS_ERR(pd->smi)) + return ERR_CAST(pd->smi); + pd->num_clks = of_clk_get_parent_count(node); if (pd->num_clks > 0) { pd->clks = devm_kcalloc(scpsys->dev, pd->num_clks, sizeof(*pd->clks), GFP_KERNEL); diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 125880a58170..c2defbdcdf31 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -34,8 +34,31 @@ #define SPM_MAX_BUS_PROT_DATA 5 +#define _BUS_PROT(_mask, _set, _clr, _sta, _update) { \ + .bus_prot_mask = (_mask), \ + .bus_prot_set = _set, \ + .bus_prot_clr = _clr, \ + .bus_prot_sta = _sta, \ + .bus_prot_reg_update = _update, \ + } + +#define BUS_PROT_WR(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _sta, false) + +#define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _sta, true) + +#define BUS_PROT_UPDATE_TOPAXI(_mask) \ + BUS_PROT_UPDATE(_mask, \ + INFRA_TOPAXI_PROTECTEN, \ + INFRA_TOPAXI_PROTECTEN_CLR, \ + INFRA_TOPAXI_PROTECTSTA1) + struct scpsys_bus_prot_data { u32 bus_prot_mask; + u32 bus_prot_set; + u32 bus_prot_clr; + u32 bus_prot_sta; bool bus_prot_reg_update; }; @@ -47,6 +70,7 @@ struct scpsys_bus_prot_data { * @sram_pdn_ack_bits: The mask for sram power control acked bits. * @caps: The flag for active wake-up action. * @bp_infracfg: bus protection for infracfg subsystem + * @bp_smi: bus protection for smi subsystem */ struct scpsys_domain_data { u32 sta_mask; @@ -55,6 +79,7 @@ struct scpsys_domain_data { u32 sram_pdn_ack_bits; u8 caps; const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; + const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; }; struct scpsys_soc_data { -- cgit v1.2.3 From 58a17e310a1c638a71892506f14c1e09b326ed56 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:13 +0100 Subject: soc: mediatek: pm-domains: Add extra sram control For some power domains like vpu_core on MT8183 whose sram need to do clock and internal isolation while power on/off sram. We add a cap "MTK_SCPD_SRAM_ISO" to judge if we need to do the extra sram isolation control or not. Signed-off-by: Weiyi Lu Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-8-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 23 +++++++++++++++++++++-- drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 8a21847464c2..a6f25933dbf0 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -24,6 +24,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) struct scpsys_domain { struct generic_pm_domain genpd; @@ -65,12 +67,23 @@ static int scpsys_sram_enable(struct scpsys_domain *pd) u32 pdn_ack = pd->data->sram_pdn_ack_bits; struct scpsys *scpsys = pd->scpsys; unsigned int tmp; + int ret; regmap_clear_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ - return regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, - (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + ret = regmap_read_poll_timeout(scpsys->base, pd->data->ctl_offs, tmp, + (tmp & pdn_ack) == 0, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) + return ret; + + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT); + udelay(1); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT); + } + + return 0; } static int scpsys_sram_disable(struct scpsys_domain *pd) @@ -79,6 +92,12 @@ static int scpsys_sram_disable(struct scpsys_domain *pd) struct scpsys *scpsys = pd->scpsys; unsigned int tmp; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_SRAM_ISO)) { + regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_CLKISO_BIT); + udelay(1); + regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_SRAM_ISOINT_B_BIT); + } + regmap_set_bits(scpsys->base, pd->data->ctl_offs, pd->data->sram_pdn_bits); /* Either wait until SRAM_PDN_ACK all 1 or 0 */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index c2defbdcdf31..f190a0d9e592 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -5,6 +5,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 -- cgit v1.2.3 From 123e8b4fd0cd9999dd384bef1d7417da68fde962 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:14 +0100 Subject: soc: mediatek: pm-domains: Add subsystem clocks For the bus protection operations, some subsystem clocks need to be enabled before releasing the protection. This patch identifies the subsystem clocks by it's name. Suggested-by: Weiyi Lu [Adapted the patch to the mtk-pm-domains driver] Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-9-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 81 ++++++++++++++++++++++++++++++----- drivers/soc/mediatek/mtk-pm-domains.h | 2 + 2 files changed, 72 insertions(+), 11 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index a6f25933dbf0..88dec58aedd9 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -3,6 +3,7 @@ * Copyright (c) 2020 Collabora Ltd. */ #include +#include #include #include #include @@ -33,6 +34,8 @@ struct scpsys_domain { struct scpsys *scpsys; int num_clks; struct clk_bulk_data *clks; + int num_subsys_clks; + struct clk_bulk_data *subsys_clks; struct regmap *infracfg; struct regmap *smi; }; @@ -204,9 +207,13 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); + ret = clk_bulk_enable(pd->num_subsys_clks, pd->subsys_clks); + if (ret) + goto err_pwr_ack; + ret = scpsys_sram_enable(pd); if (ret < 0) - goto err_pwr_ack; + goto err_disable_subsys_clks; ret = scpsys_bus_protect_disable(pd); if (ret < 0) @@ -216,6 +223,8 @@ static int scpsys_power_on(struct generic_pm_domain *genpd) err_disable_sram: scpsys_sram_disable(pd); +err_disable_subsys_clks: + clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks); err_pwr_ack: clk_bulk_disable(pd->num_clks, pd->clks); return ret; @@ -236,6 +245,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd) if (ret < 0) return ret; + clk_bulk_disable(pd->num_subsys_clks, pd->subsys_clks); + /* subsys power off */ regmap_clear_bits(scpsys->base, pd->data->ctl_offs, PWR_RST_B_BIT); regmap_set_bits(scpsys->base, pd->data->ctl_offs, PWR_ISO_BIT); @@ -259,7 +270,11 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no { const struct scpsys_domain_data *domain_data; struct scpsys_domain *pd; - int i, ret; + struct property *prop; + const char *clk_name; + int i, ret, num_clks; + struct clk *clk; + int clk_ind = 0; u32 id; ret = of_property_read_u32(node, "reg", &id); @@ -295,25 +310,62 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no if (IS_ERR(pd->smi)) return ERR_CAST(pd->smi); - pd->num_clks = of_clk_get_parent_count(node); - if (pd->num_clks > 0) { + num_clks = of_clk_get_parent_count(node); + if (num_clks > 0) { + /* Calculate number of subsys_clks */ + of_property_for_each_string(node, "clock-names", prop, clk_name) { + char *subsys; + + subsys = strchr(clk_name, '-'); + if (subsys) + pd->num_subsys_clks++; + else + pd->num_clks++; + } + pd->clks = devm_kcalloc(scpsys->dev, pd->num_clks, sizeof(*pd->clks), GFP_KERNEL); if (!pd->clks) return ERR_PTR(-ENOMEM); + + pd->subsys_clks = devm_kcalloc(scpsys->dev, pd->num_subsys_clks, + sizeof(*pd->subsys_clks), GFP_KERNEL); + if (!pd->subsys_clks) + return ERR_PTR(-ENOMEM); + } for (i = 0; i < pd->num_clks; i++) { - pd->clks[i].clk = of_clk_get(node, i); - if (IS_ERR(pd->clks[i].clk)) { - dev_err(scpsys->dev, "%pOF: failed to get clk at index %d\n", - node, i); - return ERR_PTR(-EINVAL); + clk = of_clk_get(node, i); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err_probe(scpsys->dev, ret, + "%pOF: failed to get clk at index %d: %d\n", node, i, ret); + goto err_put_clocks; } + + pd->clks[clk_ind++].clk = clk; + } + + for (i = 0; i < pd->num_subsys_clks; i++) { + clk = of_clk_get(node, i + clk_ind); + if (IS_ERR(clk)) { + ret = PTR_ERR(clk); + dev_err_probe(scpsys->dev, ret, + "%pOF: failed to get clk at index %d: %d\n", node, + i + clk_ind, ret); + goto err_put_subsys_clocks; + } + + pd->subsys_clks[i].clk = clk; } ret = clk_bulk_prepare(pd->num_clks, pd->clks); if (ret) - goto err_put_clocks; + goto err_put_subsys_clocks; + + ret = clk_bulk_prepare(pd->num_subsys_clks, pd->subsys_clks); + if (ret) + goto err_unprepare_clocks; /* * Initially turn on all domains to make the domains usable @@ -331,7 +383,7 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no ret = -EINVAL; dev_err(scpsys->dev, "power domain with id %d already exists, check your device-tree\n", id); - goto err_unprepare_clocks; + goto err_unprepare_subsys_clocks; } pd->genpd.name = node->name; @@ -343,8 +395,12 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no return scpsys->pd_data.domains[id]; +err_unprepare_subsys_clocks: + clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks); err_unprepare_clocks: clk_bulk_unprepare(pd->num_clks, pd->clks); +err_put_subsys_clocks: + clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks); err_put_clocks: clk_bulk_put(pd->num_clks, pd->clks); return ERR_PTR(ret); @@ -421,6 +477,9 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd) clk_bulk_unprepare(pd->num_clks, pd->clks); clk_bulk_put(pd->num_clks, pd->clks); + + clk_bulk_unprepare(pd->num_subsys_clks, pd->subsys_clks); + clk_bulk_put(pd->num_subsys_clks, pd->subsys_clks); } static void scpsys_domain_cleanup(struct scpsys *scpsys) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index f190a0d9e592..20df5689739b 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -63,6 +63,8 @@ struct scpsys_bus_prot_data { bool bus_prot_reg_update; }; +#define MAX_SUBSYS_CLKS 10 + /** * struct scpsys_domain_data - scp domain data for power on/off flow * @sta_mask: The mask for power on/off status bit. -- cgit v1.2.3 From 1d4597fa18b2e5d38deebdaa8121734a166a6c73 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:15 +0100 Subject: soc: mediatek: pm-domains: Allow bus protection to ignore clear ack In some cases the hardware does not create an acknowledgment of the bus protection clearing. Add a flag to the bus protection indicating that a clear event will be ignored. Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-10-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 3 +++ drivers/soc/mediatek/mtk-pm-domains.h | 23 ++++++++++++++--------- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 88dec58aedd9..03279a999dfc 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -161,6 +161,9 @@ static int _scpsys_bus_protect_disable(const struct scpsys_bus_prot_data *bpd, else regmap_write(regmap, bpd[i].bus_prot_clr, mask); + if (bpd[i].ignore_clr_ack) + continue; + ret = regmap_read_poll_timeout(regmap, bpd[i].bus_prot_sta, val, !(val & mask), MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 20df5689739b..809d2d43f01d 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -35,19 +35,23 @@ #define SPM_MAX_BUS_PROT_DATA 5 -#define _BUS_PROT(_mask, _set, _clr, _sta, _update) { \ - .bus_prot_mask = (_mask), \ - .bus_prot_set = _set, \ - .bus_prot_clr = _clr, \ - .bus_prot_sta = _sta, \ - .bus_prot_reg_update = _update, \ +#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ + .bus_prot_mask = (_mask), \ + .bus_prot_set = _set, \ + .bus_prot_clr = _clr, \ + .bus_prot_sta = _sta, \ + .bus_prot_reg_update = _update, \ + .ignore_clr_ack = _ignore, \ } -#define BUS_PROT_WR(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, false) +#define BUS_PROT_WR(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _sta, false, false) + +#define BUS_PROT_WR_IGN(_mask, _set, _clr, _sta) \ + _BUS_PROT(_mask, _set, _clr, _sta, false, true) #define BUS_PROT_UPDATE(_mask, _set, _clr, _sta) \ - _BUS_PROT(_mask, _set, _clr, _sta, true) + _BUS_PROT(_mask, _set, _clr, _sta, true, false) #define BUS_PROT_UPDATE_TOPAXI(_mask) \ BUS_PROT_UPDATE(_mask, \ @@ -61,6 +65,7 @@ struct scpsys_bus_prot_data { u32 bus_prot_clr; u32 bus_prot_sta; bool bus_prot_reg_update; + bool ignore_clr_ack; }; #define MAX_SUBSYS_CLKS 10 -- cgit v1.2.3 From eb9fa767fbe19d3db7d303e9fde7f3056221ffe1 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Fri, 30 Oct 2020 12:36:17 +0100 Subject: soc: mediatek: pm-domains: Add support for mt8183 Add the needed board data to support mt8183 SoC. Signed-off-by: Matthias Brugger Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-12-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8183-pm-domains.h | 221 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + drivers/soc/mediatek/mtk-pm-domains.h | 1 + include/linux/soc/mediatek/infracfg.h | 46 +++++++ 4 files changed, 273 insertions(+) create mode 100644 drivers/soc/mediatek/mt8183-pm-domains.h diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediatek/mt8183-pm-domains.h new file mode 100644 index 000000000000..8d996c5d2682 --- /dev/null +++ b/drivers/soc/mediatek/mt8183-pm-domains.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8183 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { + [MT8183_POWER_DOMAIN_AUDIO] = { + .sta_mask = PWR_STATUS_AUDIO, + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + }, + [MT8183_POWER_DOMAIN_CONN] = { + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x032c, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + }, + }, + [MT8183_POWER_DOMAIN_MFG_ASYNC] = { + .sta_mask = PWR_STATUS_MFG_ASYNC, + .ctl_offs = 0x0334, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + }, + [MT8183_POWER_DOMAIN_MFG] = { + .sta_mask = PWR_STATUS_MFG, + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE0] = { + .sta_mask = BIT(7), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_CORE1] = { + .sta_mask = BIT(20), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8183_POWER_DOMAIN_MFG_2D] = { + .sta_mask = PWR_STATUS_MFG_2D, + .ctl_offs = 0x0348, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + }, + }, + [MT8183_POWER_DOMAIN_DISP] = { + .sta_mask = PWR_STATUS_DISP, + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET, + MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1), + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + }, + .bp_smi = { + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), + }, + }, + [MT8183_POWER_DOMAIN_CAM] = { + .sta_mask = BIT(25), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + }, + .bp_smi = { + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), + }, + }, + [MT8183_POWER_DOMAIN_ISP] = { + .sta_mask = PWR_STATUS_ISP, + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(9, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + }, + .bp_smi = { + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), + }, + }, + [MT8183_POWER_DOMAIN_VDEC] = { + .sta_mask = BIT(31), + .ctl_offs = 0x0300, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_smi = { + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), + }, + }, + [MT8183_POWER_DOMAIN_VENC] = { + .sta_mask = PWR_STATUS_VENC, + .ctl_offs = 0x0304, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(15, 12), + .bp_smi = { + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), + }, + }, + [MT8183_POWER_DOMAIN_VPU_TOP] = { + .sta_mask = BIT(26), + .ctl_offs = 0x0324, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP, + MT8183_TOP_AXI_PROT_EN_SET, + MT8183_TOP_AXI_PROT_EN_CLR, + MT8183_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND, + MT8183_TOP_AXI_PROT_EN_MM_SET, + MT8183_TOP_AXI_PROT_EN_MM_CLR, + MT8183_TOP_AXI_PROT_EN_MM_STA1), + }, + .bp_smi = { + BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP, + MT8183_SMI_COMMON_CLAMP_EN_SET, + MT8183_SMI_COMMON_CLAMP_EN_CLR, + MT8183_SMI_COMMON_CLAMP_EN), + }, + }, + [MT8183_POWER_DOMAIN_VPU_CORE0] = { + .sta_mask = BIT(27), + .ctl_offs = 0x33c, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), + }, + .caps = MTK_SCPD_SRAM_ISO, + }, + [MT8183_POWER_DOMAIN_VPU_CORE1] = { + .sta_mask = BIT(28), + .ctl_offs = 0x0340, + .sram_pdn_bits = GENMASK(11, 8), + .sram_pdn_ack_bits = GENMASK(13, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), + BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND, + MT8183_TOP_AXI_PROT_EN_MCU_SET, + MT8183_TOP_AXI_PROT_EN_MCU_CLR, + MT8183_TOP_AXI_PROT_EN_MCU_STA1), + }, + .caps = MTK_SCPD_SRAM_ISO, + }, +}; + +static const struct scpsys_soc_data mt8183_scpsys_data = { + .domains_data = scpsys_domain_data_mt8183, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184 +}; + +#endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 03279a999dfc..8703d50cd2b7 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -16,6 +16,7 @@ #include #include "mt8173-pm-domains.h" +#include "mt8183-pm-domains.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -505,6 +506,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8173-power-controller", .data = &mt8173_scpsys_data, }, + { + .compatible = "mediatek,mt8183-power-controller", + .data = &mt8183_scpsys_data, + }, { } }; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 809d2d43f01d..2c745f11b422 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -22,6 +22,7 @@ #define SPM_PWR_STATUS 0x060c #define SPM_PWR_STATUS_2ND 0x0610 +#define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) #define PWR_STATUS_MFG BIT(4) #define PWR_STATUS_ISP BIT(5) diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 5bcaab767f6a..9d01e32e19bc 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,52 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H +#define MT8183_TOP_AXI_PROT_EN_STA1 0x228 +#define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258 +#define MT8183_TOP_AXI_PROT_EN_SET 0x2a0 +#define MT8183_TOP_AXI_PROT_EN_CLR 0x2a4 +#define MT8183_TOP_AXI_PROT_EN_1_SET 0x2a8 +#define MT8183_TOP_AXI_PROT_EN_1_CLR 0x2ac +#define MT8183_TOP_AXI_PROT_EN_MCU_SET 0x2c4 +#define MT8183_TOP_AXI_PROT_EN_MCU_CLR 0x2c8 +#define MT8183_TOP_AXI_PROT_EN_MCU_STA1 0x2e4 +#define MT8183_TOP_AXI_PROT_EN_MM_SET 0x2d4 +#define MT8183_TOP_AXI_PROT_EN_MM_CLR 0x2d8 +#define MT8183_TOP_AXI_PROT_EN_MM_STA1 0x2ec + +#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11)) +#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14)) +#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22)) +#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28) +#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27) +#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17)) +#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19) +#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8)) +#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10) +#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \ + BIT(9) | BIT(13)) +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \ + BIT(12)) +#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11)) +#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \ + BIT(4)) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \ + BIT(5)) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6) +#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7) + +#define MT8183_SMI_COMMON_CLAMP_EN 0x3c0 +#define MT8183_SMI_COMMON_CLAMP_EN_SET 0x3c4 +#define MT8183_SMI_COMMON_CLAMP_EN_CLR 0x3c8 + +#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0) +#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1) +#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2) +#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4)) +#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6)) +#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7) + #define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) #define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) #define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) -- cgit v1.2.3 From c1f3163d8ff36f5b75d467bf95581b8f2319cd64 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Fri, 30 Oct 2020 12:36:21 +0100 Subject: soc: mediatek: pm-domains: Add default power off flag For some power domain, like conn on MT8192, it should be default OFF. Because the power on/off control relies the function of connectivity chip and its firmware. And if project choose other chip vendor solution, those necessary connectivity functions will not provided. Signed-off-by: Weiyi Lu Signed-off-by: Enric Balletbo i Serra Link: https://lore.kernel.org/r/20201030113622.201188-16-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-pm-domains.c | 25 ++++++++++++++++++------- drivers/soc/mediatek/mtk-pm-domains.h | 1 + 2 files changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 8703d50cd2b7..c3b85b69f2f7 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -377,10 +377,16 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no * software. The unused domains will be switched off during * late_init time. */ - ret = scpsys_power_on(&pd->genpd); - if (ret < 0) { - dev_err(scpsys->dev, "%pOF: failed to power on domain: %d\n", node, ret); - goto err_unprepare_clocks; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) { + if (scpsys_domain_is_on(pd)) + dev_warn(scpsys->dev, + "%pOF: A default off power domain has been ON\n", node); + } else { + ret = scpsys_power_on(&pd->genpd); + if (ret < 0) { + dev_err(scpsys->dev, "%pOF: failed to power on domain: %d\n", node, ret); + goto err_unprepare_clocks; + } } if (scpsys->domains[id]) { @@ -394,7 +400,11 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no pd->genpd.power_off = scpsys_power_off; pd->genpd.power_on = scpsys_power_on; - pm_genpd_init(&pd->genpd, NULL, false); + if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) + pm_genpd_init(&pd->genpd, NULL, true); + else + pm_genpd_init(&pd->genpd, NULL, false); + scpsys->domains[id] = &pd->genpd; return scpsys->pd_data.domains[id]; @@ -467,6 +477,9 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd) { int ret; + if (scpsys_domain_is_on(pd)) + scpsys_power_off(&pd->genpd); + /* * We're in the error cleanup already, so we only complain, * but won't emit another error on top of the original one. @@ -477,8 +490,6 @@ static void scpsys_remove_one_domain(struct scpsys_domain *pd) "failed to remove domain '%s' : %d - state may be inconsistent\n", pd->genpd.name, ret); - scpsys_power_off(&pd->genpd); - clk_bulk_unprepare(pd->num_clks, pd->clks); clk_bulk_put(pd->num_clks, pd->clks); diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 2c745f11b422..a2f4d8f97e05 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -6,6 +6,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) #define MTK_SCPD_SRAM_ISO BIT(2) +#define MTK_SCPD_KEEP_DEFAULT_OFF BIT(3) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) #define SPM_VDE_PWR_CON 0x0210 -- cgit v1.2.3 From a49d5e7a89d644a5c0ddc851be4bbf08614e6015 Mon Sep 17 00:00:00 2001 From: Weiyi Lu Date: Fri, 30 Oct 2020 12:36:22 +0100 Subject: soc: mediatek: pm-domains: Add support for mt8192 Add the needed board data to support mt8192 SoC. Signed-off-by: Weiyi Lu Signed-off-by: Enric Balletbo i Serra Tested-by: Weiyi Lu Link: https://lore.kernel.org/r/20201030113622.201188-17-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mt8192-pm-domains.h | 292 +++++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 5 + include/linux/soc/mediatek/infracfg.h | 56 ++++++ 3 files changed, 353 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-pm-domains.h diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h new file mode 100644 index 000000000000..0fdf6dc6231f --- /dev/null +++ b/drivers/soc/mediatek/mt8192-pm-domains.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include + +/* + * MT8192 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { + [MT8192_POWER_DOMAIN_AUDIO] = { + .sta_mask = BIT(21), + .ctl_offs = 0x0354, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + }, + }, + [MT8192_POWER_DOMAIN_CONN] = { + .sta_mask = PWR_STATUS_CONN, + .ctl_offs = 0x0304, + .sram_pdn_bits = 0, + .sram_pdn_ack_bits = 0, + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8192_POWER_DOMAIN_MFG0] = { + .sta_mask = BIT(2), + .ctl_offs = 0x0308, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG1] = { + .sta_mask = BIT(3), + .ctl_offs = 0x030c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + }, + }, + [MT8192_POWER_DOMAIN_MFG2] = { + .sta_mask = BIT(4), + .ctl_offs = 0x0310, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG3] = { + .sta_mask = BIT(5), + .ctl_offs = 0x0314, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG4] = { + .sta_mask = BIT(6), + .ctl_offs = 0x0318, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG5] = { + .sta_mask = BIT(7), + .ctl_offs = 0x031c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_MFG6] = { + .sta_mask = BIT(8), + .ctl_offs = 0x0320, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_DISP] = { + .sta_mask = BIT(20), + .ctl_offs = 0x0350, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP, + MT8192_TOP_AXI_PROT_EN_SET, + MT8192_TOP_AXI_PROT_EN_CLR, + MT8192_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8192_POWER_DOMAIN_IPE] = { + .sta_mask = BIT(14), + .ctl_offs = 0x0338, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT8192_POWER_DOMAIN_ISP] = { + .sta_mask = BIT(12), + .ctl_offs = 0x0330, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8192_POWER_DOMAIN_ISP2] = { + .sta_mask = BIT(13), + .ctl_offs = 0x0334, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT8192_POWER_DOMAIN_MDP] = { + .sta_mask = BIT(19), + .ctl_offs = 0x034c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND, + MT8192_TOP_AXI_PROT_EN_MM_2_SET, + MT8192_TOP_AXI_PROT_EN_MM_2_CLR, + MT8192_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8192_POWER_DOMAIN_VENC] = { + .sta_mask = BIT(17), + .ctl_offs = 0x0344, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT8192_POWER_DOMAIN_VDEC] = { + .sta_mask = BIT(15), + .ctl_offs = 0x033c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + }, + }, + [MT8192_POWER_DOMAIN_VDEC2] = { + .sta_mask = BIT(16), + .ctl_offs = 0x0340, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_CAM] = { + .sta_mask = BIT(23), + .ctl_offs = 0x035c, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM, + MT8192_TOP_AXI_PROT_EN_2_SET, + MT8192_TOP_AXI_PROT_EN_2_CLR, + MT8192_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM, + MT8192_TOP_AXI_PROT_EN_1_SET, + MT8192_TOP_AXI_PROT_EN_1_CLR, + MT8192_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND, + MT8192_TOP_AXI_PROT_EN_MM_SET, + MT8192_TOP_AXI_PROT_EN_MM_CLR, + MT8192_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM, + MT8192_TOP_AXI_PROT_EN_VDNR_SET, + MT8192_TOP_AXI_PROT_EN_VDNR_CLR, + MT8192_TOP_AXI_PROT_EN_VDNR_STA1), + }, + }, + [MT8192_POWER_DOMAIN_CAM_RAWA] = { + .sta_mask = BIT(24), + .ctl_offs = 0x0360, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_CAM_RAWB] = { + .sta_mask = BIT(25), + .ctl_offs = 0x0364, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, + [MT8192_POWER_DOMAIN_CAM_RAWC] = { + .sta_mask = BIT(26), + .ctl_offs = 0x0368, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + }, +}; + +static const struct scpsys_soc_data mt8192_scpsys_data = { + .domains_data = scpsys_domain_data_mt8192, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192), + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, +}; + +#endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index c3b85b69f2f7..fb70cb3b07b3 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -17,6 +17,7 @@ #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" +#include "mt8192-pm-domains.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -521,6 +522,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8183-power-controller", .data = &mt8183_scpsys_data, }, + { + .compatible = "mediatek,mt8192-power-controller", + .data = &mt8192_scpsys_data, + }, { } }; diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 9d01e32e19bc..e7842debc05d 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,62 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H +#define MT8192_TOP_AXI_PROT_EN_STA1 0x228 +#define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 +#define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 +#define MT8192_TOP_AXI_PROT_EN_CLR 0x2a4 +#define MT8192_TOP_AXI_PROT_EN_1_SET 0x2a8 +#define MT8192_TOP_AXI_PROT_EN_1_CLR 0x2ac +#define MT8192_TOP_AXI_PROT_EN_MM_SET 0x2d4 +#define MT8192_TOP_AXI_PROT_EN_MM_CLR 0x2d8 +#define MT8192_TOP_AXI_PROT_EN_MM_STA1 0x2ec +#define MT8192_TOP_AXI_PROT_EN_2_SET 0x714 +#define MT8192_TOP_AXI_PROT_EN_2_CLR 0x718 +#define MT8192_TOP_AXI_PROT_EN_2_STA1 0x724 +#define MT8192_TOP_AXI_PROT_EN_VDNR_SET 0xb84 +#define MT8192_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 +#define MT8192_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 +#define MT8192_TOP_AXI_PROT_EN_MM_2_SET 0xdcc +#define MT8192_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 +#define MT8192_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 + +#define MT8192_TOP_AXI_PROT_EN_DISP (BIT(6) | BIT(23)) +#define MT8192_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(18)) +#define MT8192_TOP_AXI_PROT_EN_CONN_2ND BIT(14) +#define MT8192_TOP_AXI_PROT_EN_MFG1 GENMASK(22, 21) +#define MT8192_TOP_AXI_PROT_EN_1_CONN BIT(10) +#define MT8192_TOP_AXI_PROT_EN_1_MFG1 BIT(21) +#define MT8192_TOP_AXI_PROT_EN_1_CAM BIT(22) +#define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0) +#define MT8192_TOP_AXI_PROT_EN_2_ADSP BIT(3) +#define MT8192_TOP_AXI_PROT_EN_2_AUDIO BIT(4) +#define MT8192_TOP_AXI_PROT_EN_2_MFG1 GENMASK(6, 5) +#define MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND BIT(7) +#define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2)) +#define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \ + BIT(10) | BIT(12) | \ + BIT(14) | BIT(16) | \ + BIT(24) | BIT(26)) +#define MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND (BIT(1) | BIT(3)) +#define MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND (BIT(1) | BIT(3) | \ + BIT(15) | BIT(17) | \ + BIT(25) | BIT(27)) +#define MT8192_TOP_AXI_PROT_EN_MM_ISP2 BIT(14) +#define MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND BIT(15) +#define MT8192_TOP_AXI_PROT_EN_MM_IPE BIT(16) +#define MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND BIT(17) +#define MT8192_TOP_AXI_PROT_EN_MM_VDEC BIT(24) +#define MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND BIT(25) +#define MT8192_TOP_AXI_PROT_EN_MM_VENC BIT(26) +#define MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(27) +#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP BIT(8) +#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP (BIT(8) | BIT(12)) +#define MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND BIT(9) +#define MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND (BIT(9) | BIT(13)) +#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP BIT(12) +#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13) +#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21) + #define MT8183_TOP_AXI_PROT_EN_STA1 0x228 #define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258 #define MT8183_TOP_AXI_PROT_EN_SET 0x2a0 -- cgit v1.2.3 From 8b6bed678428b6df66741cb0956e076d579e3891 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 19 Nov 2020 13:52:14 +0100 Subject: soc: renesas: rmobile-sysc: Stop using __raw_*() I/O accessors There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM driver code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by: Arnd Bergmann Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20201119125214.4065925-1-geert+renesas@glider.be --- drivers/soc/renesas/rmobile-sysc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/soc/renesas/rmobile-sysc.c b/drivers/soc/renesas/rmobile-sysc.c index beb1c7211c3d..9046b8c933cb 100644 --- a/drivers/soc/renesas/rmobile-sysc.c +++ b/drivers/soc/renesas/rmobile-sysc.c @@ -57,19 +57,19 @@ static int rmobile_pd_power_down(struct generic_pm_domain *genpd) return ret; } - if (__raw_readl(rmobile_pd->base + PSTR) & mask) { + if (readl(rmobile_pd->base + PSTR) & mask) { unsigned int retry_count; - __raw_writel(mask, rmobile_pd->base + SPDCR); + writel(mask, rmobile_pd->base + SPDCR); for (retry_count = PSTR_RETRIES; retry_count; retry_count--) { - if (!(__raw_readl(rmobile_pd->base + SPDCR) & mask)) + if (!(readl(rmobile_pd->base + SPDCR) & mask)) break; cpu_relax(); } } pr_debug("%s: Power off, 0x%08x -> PSTR = 0x%08x\n", genpd->name, mask, - __raw_readl(rmobile_pd->base + PSTR)); + readl(rmobile_pd->base + PSTR)); return 0; } @@ -80,13 +80,13 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd) unsigned int retry_count; int ret = 0; - if (__raw_readl(rmobile_pd->base + PSTR) & mask) + if (readl(rmobile_pd->base + PSTR) & mask) return ret; - __raw_writel(mask, rmobile_pd->base + SWUCR); + writel(mask, rmobile_pd->base + SWUCR); for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) { - if (!(__raw_readl(rmobile_pd->base + SWUCR) & mask)) + if (!(readl(rmobile_pd->base + SWUCR) & mask)) break; if (retry_count > PSTR_RETRIES) udelay(PSTR_DELAY_US); @@ -98,7 +98,7 @@ static int __rmobile_pd_power_up(struct rmobile_pm_domain *rmobile_pd) pr_debug("%s: Power on, 0x%08x -> PSTR = 0x%08x\n", rmobile_pd->genpd.name, mask, - __raw_readl(rmobile_pd->base + PSTR)); + readl(rmobile_pd->base + PSTR)); return ret; } -- cgit v1.2.3 From 24c8a743336a1fdf42c0c768b4435633069c6a39 Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 30 Sep 2020 20:48:02 +0200 Subject: pcmcia: at91_cf: move definitions locally struct at91_cf_data is only used in the driver since all the platforms moved to device tree, move its definition locally. Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20200930184804.3127757-1-alexandre.belloni@bootlin.com --- drivers/pcmcia/at91_cf.c | 12 +++++++++++- include/linux/platform_data/atmel.h | 12 ------------ 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c index 7db0e9c74dfc..ed60c4dffecb 100644 --- a/drivers/pcmcia/at91_cf.c +++ b/drivers/pcmcia/at91_cf.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -35,6 +34,17 @@ #define CF_IO_PHYS (1 << 23) #define CF_MEM_PHYS (0x017ff800) +struct at91_cf_data { + int irq_pin; /* I/O IRQ */ + int det_pin; /* Card detect */ + int vcc_pin; /* power switching */ + int rst_pin; /* card reset */ + u8 chipselect; /* EBI Chip Select number */ + u8 flags; +#define AT91_CF_TRUE_IDE 0x01 +#define AT91_IDE_SWAP_A0_A2 0x02 +}; + struct regmap *mc; /*--------------------------------------------------------------------------*/ diff --git a/include/linux/platform_data/atmel.h b/include/linux/platform_data/atmel.h index 99e6069c5fd8..73f63be509c4 100644 --- a/include/linux/platform_data/atmel.h +++ b/include/linux/platform_data/atmel.h @@ -6,18 +6,6 @@ #ifndef __ATMEL_H__ #define __ATMEL_H__ - /* Compact Flash */ -struct at91_cf_data { - int irq_pin; /* I/O IRQ */ - int det_pin; /* Card detect */ - int vcc_pin; /* power switching */ - int rst_pin; /* card reset */ - u8 chipselect; /* EBI Chip Select number */ - u8 flags; -#define AT91_CF_TRUE_IDE 0x01 -#define AT91_IDE_SWAP_A0_A2 0x02 -}; - /* FIXME: this needs a better location, but gets stuff building again */ #ifdef CONFIG_ATMEL_PM extern int at91_suspend_entering_slow_clock(void); -- cgit v1.2.3 From 264788c8f23703d0d3e967fb5aea83eb64d2cb2b Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Wed, 30 Sep 2020 20:48:03 +0200 Subject: pcmcia: at91_cf: remove platform data support Board file support has been removed for at91rm9200 back in 2014, make the CF driver DT only. Signed-off-by: Alexandre Belloni Link: https://lore.kernel.org/r/20200930184804.3127757-2-alexandre.belloni@bootlin.com --- drivers/pcmcia/Kconfig | 1 + drivers/pcmcia/at91_cf.c | 38 ++++++++------------------------------ 2 files changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 82d10b6661c7..884023e88345 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -258,6 +258,7 @@ config OMAP_CF config AT91_CF tristate "AT91 CompactFlash Controller" depends on PCI + depends on OF depends on PCMCIA && ARCH_AT91 help Say Y here to support the CompactFlash controller on AT91 chips. diff --git a/drivers/pcmcia/at91_cf.c b/drivers/pcmcia/at91_cf.c index ed60c4dffecb..6b1edfc890a3 100644 --- a/drivers/pcmcia/at91_cf.c +++ b/drivers/pcmcia/at91_cf.c @@ -219,16 +219,18 @@ static struct pccard_operations at91_cf_ops = { /*--------------------------------------------------------------------------*/ -#if defined(CONFIG_OF) static const struct of_device_id at91_cf_dt_ids[] = { { .compatible = "atmel,at91rm9200-cf" }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, at91_cf_dt_ids); -static int at91_cf_dt_init(struct platform_device *pdev) +static int at91_cf_probe(struct platform_device *pdev) { - struct at91_cf_data *board; + struct at91_cf_socket *cf; + struct at91_cf_data *board; + struct resource *io; + int status; board = devm_kzalloc(&pdev->dev, sizeof(*board), GFP_KERNEL); if (!board) @@ -239,33 +241,9 @@ static int at91_cf_dt_init(struct platform_device *pdev) board->vcc_pin = of_get_gpio(pdev->dev.of_node, 2); board->rst_pin = of_get_gpio(pdev->dev.of_node, 3); - pdev->dev.platform_data = board; - mc = syscon_regmap_lookup_by_compatible("atmel,at91rm9200-sdramc"); - - return PTR_ERR_OR_ZERO(mc); -} -#else -static int at91_cf_dt_init(struct platform_device *pdev) -{ - return -ENODEV; -} -#endif - -static int at91_cf_probe(struct platform_device *pdev) -{ - struct at91_cf_socket *cf; - struct at91_cf_data *board = pdev->dev.platform_data; - struct resource *io; - int status; - - if (!board) { - status = at91_cf_dt_init(pdev); - if (status) - return status; - - board = pdev->dev.platform_data; - } + if (IS_ERR(mc)) + return PTR_ERR(mc); if (!gpio_is_valid(board->det_pin) || !gpio_is_valid(board->rst_pin)) return -ENODEV; @@ -409,7 +387,7 @@ static int at91_cf_resume(struct platform_device *pdev) static struct platform_driver at91_cf_driver = { .driver = { .name = "at91_cf", - .of_match_table = of_match_ptr(at91_cf_dt_ids), + .of_match_table = at91_cf_dt_ids, }, .probe = at91_cf_probe, .remove = at91_cf_remove, -- cgit v1.2.3 From a69dcdfc2dd21f86cb1f79f98fc94c52f96cff64 Mon Sep 17 00:00:00 2001 From: Chun-Kuang Hu Date: Mon, 2 Nov 2020 08:04:38 +0800 Subject: soc / drm: mediatek: cmdq: Remove timeout handler in helper function For each client driver, its timeout handler need to dump hardware register or its state machine information, and their way to detect timeout are also different, so remove timeout handler in helper function and let client driver implement its own timeout handler. Signed-off-by: Chun-Kuang Hu Acked-by: Matthias Brugger Link: https://lore.kernel.org/r/20201102000438.29225-1-chunkuang.hu@kernel.org Signed-off-by: Matthias Brugger --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 3 +-- drivers/soc/mediatek/mtk-cmdq-helper.c | 41 +-------------------------------- include/linux/soc/mediatek/mtk-cmdq.h | 10 +------- 3 files changed, 3 insertions(+), 51 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index ac038572164d..4be5d1fccf2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -824,8 +824,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, #if IS_REACHABLE(CONFIG_MTK_CMDQ) mtk_crtc->cmdq_client = cmdq_mbox_create(mtk_crtc->mmsys_dev, - drm_crtc_index(&mtk_crtc->base), - 2000); + drm_crtc_index(&mtk_crtc->base)); if (IS_ERR(mtk_crtc->cmdq_client)) { dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n", drm_crtc_index(&mtk_crtc->base)); diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c index 505651b0d715..280d3bd9f675 100644 --- a/drivers/soc/mediatek/mtk-cmdq-helper.c +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c @@ -70,14 +70,7 @@ int cmdq_dev_get_client_reg(struct device *dev, } EXPORT_SYMBOL(cmdq_dev_get_client_reg); -static void cmdq_client_timeout(struct timer_list *t) -{ - struct cmdq_client *client = from_timer(client, t, timer); - - dev_err(client->client.dev, "cmdq timeout!\n"); -} - -struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, u32 timeout) +struct cmdq_client *cmdq_mbox_create(struct device *dev, int index) { struct cmdq_client *client; @@ -85,12 +78,6 @@ struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, u32 timeout) if (!client) return (struct cmdq_client *)-ENOMEM; - client->timeout_ms = timeout; - if (timeout != CMDQ_NO_TIMEOUT) { - spin_lock_init(&client->lock); - timer_setup(&client->timer, cmdq_client_timeout, 0); - } - client->pkt_cnt = 0; client->client.dev = dev; client->client.tx_block = false; client->client.knows_txdone = true; @@ -112,11 +99,6 @@ EXPORT_SYMBOL(cmdq_mbox_create); void cmdq_mbox_destroy(struct cmdq_client *client) { - if (client->timeout_ms != CMDQ_NO_TIMEOUT) { - spin_lock(&client->lock); - del_timer_sync(&client->timer); - spin_unlock(&client->lock); - } mbox_free_channel(client->chan); kfree(client); } @@ -449,18 +431,6 @@ static void cmdq_pkt_flush_async_cb(struct cmdq_cb_data data) struct cmdq_task_cb *cb = &pkt->cb; struct cmdq_client *client = (struct cmdq_client *)pkt->cl; - if (client->timeout_ms != CMDQ_NO_TIMEOUT) { - unsigned long flags = 0; - - spin_lock_irqsave(&client->lock, flags); - if (--client->pkt_cnt == 0) - del_timer(&client->timer); - else - mod_timer(&client->timer, jiffies + - msecs_to_jiffies(client->timeout_ms)); - spin_unlock_irqrestore(&client->lock, flags); - } - dma_sync_single_for_cpu(client->chan->mbox->dev, pkt->pa_base, pkt->cmd_buf_size, DMA_TO_DEVICE); if (cb->cb) { @@ -473,7 +443,6 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, void *data) { int err; - unsigned long flags = 0; struct cmdq_client *client = (struct cmdq_client *)pkt->cl; pkt->cb.cb = cb; @@ -484,14 +453,6 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, dma_sync_single_for_device(client->chan->mbox->dev, pkt->pa_base, pkt->cmd_buf_size, DMA_TO_DEVICE); - if (client->timeout_ms != CMDQ_NO_TIMEOUT) { - spin_lock_irqsave(&client->lock, flags); - if (client->pkt_cnt++ == 0) - mod_timer(&client->timer, jiffies + - msecs_to_jiffies(client->timeout_ms)); - spin_unlock_irqrestore(&client->lock, flags); - } - err = mbox_send_message(client->chan, pkt); if (err < 0) return err; diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h index 960704d75994..8e9996610978 100644 --- a/include/linux/soc/mediatek/mtk-cmdq.h +++ b/include/linux/soc/mediatek/mtk-cmdq.h @@ -11,7 +11,6 @@ #include #include -#define CMDQ_NO_TIMEOUT 0xffffffffu #define CMDQ_ADDR_HIGH(addr) ((u32)(((addr) >> 16) & GENMASK(31, 0))) #define CMDQ_ADDR_LOW(addr) ((u16)(addr) | BIT(1)) @@ -24,12 +23,8 @@ struct cmdq_client_reg { }; struct cmdq_client { - spinlock_t lock; - u32 pkt_cnt; struct mbox_client client; struct mbox_chan *chan; - struct timer_list timer; - u32 timeout_ms; /* in unit of microsecond */ }; /** @@ -51,13 +46,10 @@ int cmdq_dev_get_client_reg(struct device *dev, * cmdq_mbox_create() - create CMDQ mailbox client and channel * @dev: device of CMDQ mailbox client * @index: index of CMDQ mailbox channel - * @timeout: timeout of a pkt execution by GCE, in unit of microsecond, set - * CMDQ_NO_TIMEOUT if a timer is not used. * * Return: CMDQ mailbox client pointer */ -struct cmdq_client *cmdq_mbox_create(struct device *dev, int index, - u32 timeout); +struct cmdq_client *cmdq_mbox_create(struct device *dev, int index); /** * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel -- cgit v1.2.3 From aaf162d4a5dfdf623a48b3bd6af2af4c237c38f3 Mon Sep 17 00:00:00 2001 From: Neal Liu Date: Thu, 15 Oct 2020 11:20:38 +0800 Subject: dt-bindings: devapc: add bindings for mtk-devapc Add bindings for mtk-devapc. Signed-off-by: Neal Liu Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1602732039-12179-2-git-send-email-neal.liu@mediatek.com Signed-off-by: Matthias Brugger --- .../devicetree/bindings/soc/mediatek/devapc.yaml | 58 ++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/devapc.yaml diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml new file mode 100644 index 000000000000..6c763f873a63 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# # Copyright 2020 MediaTek Inc. +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/mediatek/devapc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek Device Access Permission Control driver + +description: | + MediaTek bus fabric provides TrustZone security support and data + protection to prevent slaves from being accessed by unexpected masters. + The security violation is logged and sent to the processor for further + analysis and countermeasures. + +maintainers: + - Neal Liu + +properties: + compatible: + enum: + - mediatek,mt6779-devapc + + reg: + description: The base address of devapc register bank + maxItems: 1 + + interrupts: + description: A single interrupt specifier + maxItems: 1 + + clocks: + description: Contains module clock source and clock names + maxItems: 1 + + clock-names: + description: Names of the clocks list in clocks property + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +examples: + - | + #include + #include + + devapc: devapc@10207000 { + compatible = "mediatek,mt6779-devapc"; + reg = <0x10207000 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>; + clock-names = "devapc-infra-clock"; + }; -- cgit v1.2.3 From 0890beb22618c0359f1e2652fc1e49bb5c5e876d Mon Sep 17 00:00:00 2001 From: Neal Liu Date: Thu, 15 Oct 2020 11:20:39 +0800 Subject: soc: mediatek: add mt6779 devapc driver MediaTek bus fabric provides TrustZone security support and data protection to prevent slaves from being accessed by unexpected masters. The security violation is logged and sent to the processor for further analysis or countermeasures. Any occurrence of security violation would raise an interrupt, and it will be handled by mtk-devapc driver. The violation information is printed in order to find the murderer. Signed-off-by: Neal Liu Link: https://lore.kernel.org/r/1602732039-12179-3-git-send-email-neal.liu@mediatek.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/Kconfig | 9 ++ drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-devapc.c | 308 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 318 insertions(+) create mode 100644 drivers/soc/mediatek/mtk-devapc.c diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 67cef12dc585..851121d83f14 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -17,6 +17,15 @@ config MTK_CMDQ time limitation, such as updating display configuration during the vblank. +config MTK_DEVAPC + tristate "Mediatek Device APC Support" + help + Say yes here to enable support for Mediatek Device APC driver. + This driver is mainly used to handle the violation which catches + unexpected transaction. + The violation information is logged for further analysis or + countermeasures. + config MTK_INFRACFG bool "MediaTek INFRACFG Support" select REGMAP diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index 1e60fb4f89d4..b6908db534c2 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o +obj-$(CONFIG_MTK_DEVAPC) += mtk-devapc.o obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-devapc.c new file mode 100644 index 000000000000..f1cea041dc5a --- /dev/null +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define VIO_MOD_TO_REG_IND(m) ((m) / 32) +#define VIO_MOD_TO_REG_OFF(m) ((m) % 32) + +struct mtk_devapc_vio_dbgs { + union { + u32 vio_dbg0; + struct { + u32 mstid:16; + u32 dmnid:6; + u32 vio_w:1; + u32 vio_r:1; + u32 addr_h:4; + u32 resv:4; + } dbg0_bits; + }; + + u32 vio_dbg1; +}; + +struct mtk_devapc_data { + /* numbers of violation index */ + u32 vio_idx_num; + + /* reg offset */ + u32 vio_mask_offset; + u32 vio_sta_offset; + u32 vio_dbg0_offset; + u32 vio_dbg1_offset; + u32 apc_con_offset; + u32 vio_shift_sta_offset; + u32 vio_shift_sel_offset; + u32 vio_shift_con_offset; +}; + +struct mtk_devapc_context { + struct device *dev; + void __iomem *infra_base; + struct clk *infra_clk; + const struct mtk_devapc_data *data; +}; + +static void clear_vio_status(struct mtk_devapc_context *ctx) +{ + void __iomem *reg; + int i; + + reg = ctx->infra_base + ctx->data->vio_sta_offset; + + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) + writel(GENMASK(31, 0), reg + 4 * i); + + writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0), + reg + 4 * i); +} + +static void mask_module_irq(struct mtk_devapc_context *ctx, bool mask) +{ + void __iomem *reg; + u32 val; + int i; + + reg = ctx->infra_base + ctx->data->vio_mask_offset; + + if (mask) + val = GENMASK(31, 0); + else + val = 0; + + for (i = 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) + writel(val, reg + 4 * i); + + val = readl(reg + 4 * i); + if (mask) + val |= GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, + 0); + else + val &= ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, + 0); + + writel(val, reg + 4 * i); +} + +#define PHY_DEVAPC_TIMEOUT 0x10000 + +/* + * devapc_sync_vio_dbg - do "shift" mechansim" to get full violation information. + * shift mechanism is depends on devapc hardware design. + * Mediatek devapc set multiple slaves as a group. + * When violation is triggered, violation info is kept + * inside devapc hardware. + * Driver should do shift mechansim to sync full violation + * info to VIO_DBGs registers. + * + */ +static int devapc_sync_vio_dbg(struct mtk_devapc_context *ctx) +{ + void __iomem *pd_vio_shift_sta_reg; + void __iomem *pd_vio_shift_sel_reg; + void __iomem *pd_vio_shift_con_reg; + int min_shift_group; + int ret; + u32 val; + + pd_vio_shift_sta_reg = ctx->infra_base + + ctx->data->vio_shift_sta_offset; + pd_vio_shift_sel_reg = ctx->infra_base + + ctx->data->vio_shift_sel_offset; + pd_vio_shift_con_reg = ctx->infra_base + + ctx->data->vio_shift_con_offset; + + /* Find the minimum shift group which has violation */ + val = readl(pd_vio_shift_sta_reg); + if (!val) + return false; + + min_shift_group = __ffs(val); + + /* Assign the group to sync */ + writel(0x1 << min_shift_group, pd_vio_shift_sel_reg); + + /* Start syncing */ + writel(0x1, pd_vio_shift_con_reg); + + ret = readl_poll_timeout(pd_vio_shift_con_reg, val, val == 0x3, 0, + PHY_DEVAPC_TIMEOUT); + if (ret) { + dev_err(ctx->dev, "%s: Shift violation info failed\n", __func__); + return false; + } + + /* Stop syncing */ + writel(0x0, pd_vio_shift_con_reg); + + /* Write clear */ + writel(0x1 << min_shift_group, pd_vio_shift_sta_reg); + + return true; +} + +/* + * devapc_extract_vio_dbg - extract full violation information after doing + * shift mechanism. + */ +static void devapc_extract_vio_dbg(struct mtk_devapc_context *ctx) +{ + struct mtk_devapc_vio_dbgs vio_dbgs; + void __iomem *vio_dbg0_reg; + void __iomem *vio_dbg1_reg; + + vio_dbg0_reg = ctx->infra_base + ctx->data->vio_dbg0_offset; + vio_dbg1_reg = ctx->infra_base + ctx->data->vio_dbg1_offset; + + vio_dbgs.vio_dbg0 = readl(vio_dbg0_reg); + vio_dbgs.vio_dbg1 = readl(vio_dbg1_reg); + + /* Print violation information */ + if (vio_dbgs.dbg0_bits.vio_w) + dev_info(ctx->dev, "Write Violation\n"); + else if (vio_dbgs.dbg0_bits.vio_r) + dev_info(ctx->dev, "Read Violation\n"); + + dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n", + vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid, + vio_dbgs.vio_dbg1); +} + +/* + * devapc_violation_irq - the devapc Interrupt Service Routine (ISR) will dump + * violation information including which master violates + * access slave. + */ +static irqreturn_t devapc_violation_irq(int irq_number, void *data) +{ + struct mtk_devapc_context *ctx = data; + + while (devapc_sync_vio_dbg(ctx)) + devapc_extract_vio_dbg(ctx); + + clear_vio_status(ctx); + + return IRQ_HANDLED; +} + +/* + * start_devapc - unmask slave's irq to start receiving devapc violation. + */ +static void start_devapc(struct mtk_devapc_context *ctx) +{ + writel(BIT(31), ctx->infra_base + ctx->data->apc_con_offset); + + mask_module_irq(ctx, false); +} + +/* + * stop_devapc - mask slave's irq to stop service. + */ +static void stop_devapc(struct mtk_devapc_context *ctx) +{ + mask_module_irq(ctx, true); + + writel(BIT(2), ctx->infra_base + ctx->data->apc_con_offset); +} + +static const struct mtk_devapc_data devapc_mt6779 = { + .vio_idx_num = 511, + .vio_mask_offset = 0x0, + .vio_sta_offset = 0x400, + .vio_dbg0_offset = 0x900, + .vio_dbg1_offset = 0x904, + .apc_con_offset = 0xF00, + .vio_shift_sta_offset = 0xF10, + .vio_shift_sel_offset = 0xF14, + .vio_shift_con_offset = 0xF20, +}; + +static const struct of_device_id mtk_devapc_dt_match[] = { + { + .compatible = "mediatek,mt6779-devapc", + .data = &devapc_mt6779, + }, { + }, +}; + +static int mtk_devapc_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; + struct mtk_devapc_context *ctx; + u32 devapc_irq; + int ret; + + if (IS_ERR(node)) + return -ENODEV; + + ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->data = of_device_get_match_data(&pdev->dev); + ctx->dev = &pdev->dev; + + ctx->infra_base = of_iomap(node, 0); + if (!ctx->infra_base) + return -EINVAL; + + devapc_irq = irq_of_parse_and_map(node, 0); + if (!devapc_irq) + return -EINVAL; + + ctx->infra_clk = devm_clk_get(&pdev->dev, "devapc-infra-clock"); + if (IS_ERR(ctx->infra_clk)) + return -EINVAL; + + if (clk_prepare_enable(ctx->infra_clk)) + return -EINVAL; + + ret = devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq, + IRQF_TRIGGER_NONE, "devapc", ctx); + if (ret) { + clk_disable_unprepare(ctx->infra_clk); + return ret; + } + + platform_set_drvdata(pdev, ctx); + + start_devapc(ctx); + + return 0; +} + +static int mtk_devapc_remove(struct platform_device *pdev) +{ + struct mtk_devapc_context *ctx = platform_get_drvdata(pdev); + + stop_devapc(ctx); + + clk_disable_unprepare(ctx->infra_clk); + + return 0; +} + +static struct platform_driver mtk_devapc_driver = { + .probe = mtk_devapc_probe, + .remove = mtk_devapc_remove, + .driver = { + .name = "mtk-devapc", + .of_match_table = mtk_devapc_dt_match, + }, +}; + +module_platform_driver(mtk_devapc_driver); + +MODULE_DESCRIPTION("Mediatek Device APC Driver"); +MODULE_AUTHOR("Neal Liu "); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 51c0e618b219c025ddaaf14baea8942cb7e2105b Mon Sep 17 00:00:00 2001 From: Yongqiang Niu Date: Tue, 6 Oct 2020 21:33:17 +0200 Subject: soc / drm: mediatek: Move DDP component defines into mtk-mmsys.h MMSYS is the driver which controls the routing of these DDP components, so the definition of the mtk_ddp_comp_id enum should be placed in mtk-mmsys.h Signed-off-by: Yongqiang Niu Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20201006193320.405529-2-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 34 +---------------------------- drivers/soc/mediatek/mtk-mmsys.c | 4 +--- include/linux/soc/mediatek/mtk-mmsys.h | 33 ++++++++++++++++++++++++++++ 3 files changed, 35 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index 1d9e00b69462..5aa52b7afeec 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -7,6 +7,7 @@ #define MTK_DRM_DDP_COMP_H #include +#include struct device; struct device_node; @@ -35,39 +36,6 @@ enum mtk_ddp_comp_type { MTK_DDP_COMP_TYPE_MAX, }; -enum mtk_ddp_comp_id { - DDP_COMPONENT_AAL0, - DDP_COMPONENT_AAL1, - DDP_COMPONENT_BLS, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_COLOR1, - DDP_COMPONENT_DITHER, - DDP_COMPONENT_DPI0, - DDP_COMPONENT_DPI1, - DDP_COMPONENT_DSI0, - DDP_COMPONENT_DSI1, - DDP_COMPONENT_DSI2, - DDP_COMPONENT_DSI3, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_OD0, - DDP_COMPONENT_OD1, - DDP_COMPONENT_OVL0, - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_OVL_2L1, - DDP_COMPONENT_OVL1, - DDP_COMPONENT_PWM0, - DDP_COMPONENT_PWM1, - DDP_COMPONENT_PWM2, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_RDMA2, - DDP_COMPONENT_UFOE, - DDP_COMPONENT_WDMA0, - DDP_COMPONENT_WDMA1, - DDP_COMPONENT_ID_MAX, -}; - struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a55f25511173..36ad66bb221b 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -5,13 +5,11 @@ */ #include +#include #include #include #include -#include "../../gpu/drm/mediatek/mtk_drm_ddp.h" -#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h" - #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 7bab5d9a3d31..2228bf6133da 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -9,6 +9,39 @@ enum mtk_ddp_comp_id; struct device; +enum mtk_ddp_comp_id { + DDP_COMPONENT_AAL0, + DDP_COMPONENT_AAL1, + DDP_COMPONENT_BLS, + DDP_COMPONENT_CCORR, + DDP_COMPONENT_COLOR0, + DDP_COMPONENT_COLOR1, + DDP_COMPONENT_DITHER, + DDP_COMPONENT_DPI0, + DDP_COMPONENT_DPI1, + DDP_COMPONENT_DSI0, + DDP_COMPONENT_DSI1, + DDP_COMPONENT_DSI2, + DDP_COMPONENT_DSI3, + DDP_COMPONENT_GAMMA, + DDP_COMPONENT_OD0, + DDP_COMPONENT_OD1, + DDP_COMPONENT_OVL0, + DDP_COMPONENT_OVL_2L0, + DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL1, + DDP_COMPONENT_PWM0, + DDP_COMPONENT_PWM1, + DDP_COMPONENT_PWM2, + DDP_COMPONENT_RDMA0, + DDP_COMPONENT_RDMA1, + DDP_COMPONENT_RDMA2, + DDP_COMPONENT_UFOE, + DDP_COMPONENT_WDMA0, + DDP_COMPONENT_WDMA1, + DDP_COMPONENT_ID_MAX, +}; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); -- cgit v1.2.3 From cc6576029aedc79ce87b9fcb22cbd396d47f2852 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Tue, 6 Oct 2020 21:33:18 +0200 Subject: soc: mediatek: mmsys: Use devm_platform_ioremap_resource() For the common platform_get_resource()+devm_platform_ioremap() combination, there is a helper, so use it and make the code a bit more compact. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Chun-Kuang Hu Link: https://lore.kernel.org/r/20201006193320.405529-3-enric.balletbo@collabora.com Signed-off-by: Matthias Brugger --- drivers/soc/mediatek/mtk-mmsys.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index 36ad66bb221b..18f93979e14a 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -306,15 +306,12 @@ static int mtk_mmsys_probe(struct platform_device *pdev) struct platform_device *clks; struct platform_device *drm; void __iomem *config_regs; - struct resource *mem; int ret; - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - config_regs = devm_ioremap_resource(dev, mem); + config_regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(config_regs)) { ret = PTR_ERR(config_regs); - dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", - ret); + dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret); return ret; } -- cgit v1.2.3 From a0453f4ed066cae651b3119ed11f52d31dae1eca Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 26 Nov 2020 19:11:42 +0000 Subject: memory: renesas-rpc-if: Return correct value to the caller of rpcif_manual_xfer() In the error path of rpcif_manual_xfer() the value of ret is overwritten by value returned by reset_control_reset() function and thus returning incorrect value to the caller. This patch makes sure the correct value is returned to the caller of rpcif_manual_xfer() by dropping the overwrite of ret in error path. Also now we ignore the value returned by reset_control_reset() in the error path and instead print a error message when it fails. Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver") Reported-by: Pavel Machek Signed-off-by: Lad Prabhakar Reviewed-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Reviewed-by: Pavel Machek (CIP) Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201126191146.8753-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index f2a33a1af836..69f2e2b4cd50 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -508,7 +508,8 @@ exit: return ret; err_out: - ret = reset_control_reset(rpc->rstc); + if (reset_control_reset(rpc->rstc)) + dev_err(rpc->dev, "Failed to reset HW\n"); rpcif_hw_init(rpc, rpc->bus_size == 2); goto exit; } -- cgit v1.2.3 From 61a6d854b9555b420fbfae62ef26baa8b9493b32 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 26 Nov 2020 19:11:43 +0000 Subject: memory: renesas-rpc-if: Fix unbalanced pm_runtime_enable in rpcif_{enable,disable}_rpm rpcif_enable_rpm calls pm_runtime_enable, so rpcif_disable_rpm needs to call pm_runtime_disable and not pm_runtime_put_sync. Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver") Reported-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar Reviewed-by: Sergei Shtylyov Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201126191146.8753-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 69f2e2b4cd50..a8d0ba368625 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -212,7 +212,7 @@ EXPORT_SYMBOL(rpcif_enable_rpm); void rpcif_disable_rpm(struct rpcif *rpc) { - pm_runtime_put_sync(rpc->dev); + pm_runtime_disable(rpc->dev); } EXPORT_SYMBOL(rpcif_disable_rpm); -- cgit v1.2.3 From 4e6b86b409f9fc63fedb39d6e3a0202c4b0244ce Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 26 Nov 2020 19:11:44 +0000 Subject: memory: renesas-rpc-if: Fix a node reference leak in rpcif_probe() Release the node reference by calling of_node_put(flash) in the probe. Fixes: ca7d8b980b67f ("memory: add Renesas RPC-IF driver") Reported-by: Pavel Machek Signed-off-by: Lad Prabhakar Reviewed-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Reviewed-by: Pavel Machek (CIP) Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20201126191146.8753-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index a8d0ba368625..da0fdb4c7595 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -561,9 +561,11 @@ static int rpcif_probe(struct platform_device *pdev) } else if (of_device_is_compatible(flash, "cfi-flash")) { name = "rpc-if-hyperflash"; } else { + of_node_put(flash); dev_warn(&pdev->dev, "unknown flash type\n"); return -ENODEV; } + of_node_put(flash); vdev = platform_device_alloc(name, pdev->id); if (!vdev) -- cgit v1.2.3 From 7889a7da59e0131ac60b858c73a3604ef88b1d96 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 26 Nov 2020 19:11:45 +0000 Subject: memory: renesas-rpc-if: Make rpcif_enable/disable_rpm() as static inline Define rpcif_enable_rpm() and rpcif_disable_rpm() as static inline in the header instead of exporting them. Suggested-by: Pavel Machek Signed-off-by: Lad Prabhakar Reviewed-by: Pavel Machek (CIP) Link: https://lore.kernel.org/r/20201126191146.8753-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/renesas-rpc-if.c | 13 ------------- include/memory/renesas-rpc-if.h | 13 +++++++++++-- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index da0fdb4c7595..8d36e221def1 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include @@ -204,18 +203,6 @@ int rpcif_sw_init(struct rpcif *rpc, struct device *dev) } EXPORT_SYMBOL(rpcif_sw_init); -void rpcif_enable_rpm(struct rpcif *rpc) -{ - pm_runtime_enable(rpc->dev); -} -EXPORT_SYMBOL(rpcif_enable_rpm); - -void rpcif_disable_rpm(struct rpcif *rpc) -{ - pm_runtime_disable(rpc->dev); -} -EXPORT_SYMBOL(rpcif_disable_rpm); - void rpcif_hw_init(struct rpcif *rpc, bool hyperflash) { u32 dummy; diff --git a/include/memory/renesas-rpc-if.h b/include/memory/renesas-rpc-if.h index 9ad136682c47..14cfd036268a 100644 --- a/include/memory/renesas-rpc-if.h +++ b/include/memory/renesas-rpc-if.h @@ -10,6 +10,7 @@ #ifndef __RENESAS_RPC_IF_H #define __RENESAS_RPC_IF_H +#include #include enum rpcif_data_dir { @@ -77,11 +78,19 @@ struct rpcif { int rpcif_sw_init(struct rpcif *rpc, struct device *dev); void rpcif_hw_init(struct rpcif *rpc, bool hyperflash); -void rpcif_enable_rpm(struct rpcif *rpc); -void rpcif_disable_rpm(struct rpcif *rpc); void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs, size_t *len); int rpcif_manual_xfer(struct rpcif *rpc); ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf); +static inline void rpcif_enable_rpm(struct rpcif *rpc) +{ + pm_runtime_enable(rpc->dev); +} + +static inline void rpcif_disable_rpm(struct rpcif *rpc) +{ + pm_runtime_disable(rpc->dev); +} + #endif // __RENESAS_RPC_IF_H -- cgit v1.2.3 From 90ad8e0acd0d4e874a84ffca3ab58cbafcc2dd42 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 18 Nov 2020 15:31:21 +0800 Subject: firmware: imx: scu-pd: Add video0/1 power domains support for i.MX8qxp DC0 subsystem This patch adds video0/1 power domains support for i.MX8qxp DC0 subsystem. Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Signed-off-by: Liu Ying Signed-off-by: Shawn Guo --- drivers/firmware/imx/scu-pd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index a614d8dd868e..bb2518091030 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -166,6 +166,7 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, { "dc0-pll", IMX_SC_R_DC_0_PLL_0, 2, true, 0 }, + { "dc0-video", IMX_SC_R_DC_0_VIDEO0, 2, true, 0 }, /* CM40 SS */ { "cm40-i2c", IMX_SC_R_M4_0_I2C, 1, false, 0 }, -- cgit v1.2.3 From f57afc6f77dae77d52eba32d4c4c7d2252021646 Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 18 Nov 2020 15:31:22 +0800 Subject: firmware: imx: scu-pd: Add main power domain support for i.MX8qxp LVDS1 subsystem This patch adds the main power domain support for i.MX8qxp LVDS1 subsystem. Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Signed-off-by: Liu Ying Signed-off-by: Shawn Guo --- drivers/firmware/imx/scu-pd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index bb2518091030..5f9c4211e397 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -162,6 +162,7 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { /* LVDS SS */ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, + { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, /* DC SS */ { "dc0", IMX_SC_R_DC_0, 1, false, 0 }, -- cgit v1.2.3 From e00e70a4dae4cae026d43f2f05ba46a19c4ef22d Mon Sep 17 00:00:00 2001 From: Liu Ying Date: Wed, 18 Nov 2020 15:31:23 +0800 Subject: firmware: imx: scu-pd: Add some power domains support for i.MX8qxp MIPI1 subsystem This patch adds the main power domain, pwm0 power domain and i2c0/1 power domains support for i.MX8qxp MIPI1 subsystem. Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Signed-off-by: Liu Ying Signed-off-by: Shawn Guo --- drivers/firmware/imx/scu-pd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c index 5f9c4211e397..08533ee67626 100644 --- a/drivers/firmware/imx/scu-pd.c +++ b/drivers/firmware/imx/scu-pd.c @@ -160,6 +160,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = { { "mipi0-pwm0", IMX_SC_R_MIPI_0_PWM_0, 1, false, 0 }, { "mipi0-i2c", IMX_SC_R_MIPI_0_I2C_0, 2, true, 0 }, + { "mipi1", IMX_SC_R_MIPI_1, 1, false, 0 }, + { "mipi1-pwm0", IMX_SC_R_MIPI_1_PWM_0, 1, false, 0 }, + { "mipi1-i2c", IMX_SC_R_MIPI_1_I2C_0, 2, true, 0 }, + /* LVDS SS */ { "lvds0", IMX_SC_R_LVDS_0, 1, false, 0 }, { "lvds1", IMX_SC_R_LVDS_1, 1, false, 0 }, -- cgit v1.2.3 From 28f851e6afa858f182802e23ac60c3ed7d1c04a1 Mon Sep 17 00:00:00 2001 From: Yu Kuai Date: Tue, 17 Nov 2020 09:13:22 +0800 Subject: soc: amlogic: canvas: add missing put_device() call in meson_canvas_get() if of_find_device_by_node() succeed, meson_canvas_get() doesn't have a corresponding put_device(). Thus add put_device() to fix the exception handling for this function implementation. Fixes: 382f8be04551 ("soc: amlogic: canvas: Fix meson_canvas_get when probe failed") Signed-off-by: Yu Kuai Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/20201117011322.522477-1-yukuai3@huawei.com --- drivers/soc/amlogic/meson-canvas.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/soc/amlogic/meson-canvas.c b/drivers/soc/amlogic/meson-canvas.c index c655f5f92b12..d0329ad170d1 100644 --- a/drivers/soc/amlogic/meson-canvas.c +++ b/drivers/soc/amlogic/meson-canvas.c @@ -72,8 +72,10 @@ struct meson_canvas *meson_canvas_get(struct device *dev) * current state, this driver probe cannot return -EPROBE_DEFER */ canvas = dev_get_drvdata(&canvas_pdev->dev); - if (!canvas) + if (!canvas) { + put_device(&canvas_pdev->dev); return ERR_PTR(-EINVAL); + } return canvas; } -- cgit v1.2.3 From 1116e43e7e4be7c7d76578ffac1d3a73f4ebcafe Mon Sep 17 00:00:00 2001 From: Yejune Deng Date: Wed, 18 Nov 2020 10:48:20 +0800 Subject: soc: amlogic: replace devm_reset_control_array_get() devm_reset_control_array_get_exclusive() looks more readable Signed-off-by: Yejune Deng Reviewed-by: Philipp Zabel Reviewed-by: Martin Blumenstingl Signed-off-by: Kevin Hilman Link: https://lore.kernel.org/r/1605667700-16681-1-git-send-email-yejune.deng@gmail.com --- drivers/soc/amlogic/meson-ee-pwrc.c | 3 +-- drivers/soc/amlogic/meson-gx-pwrc-vpu.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c index ed7d2fbb47f2..50bf5d2b828b 100644 --- a/drivers/soc/amlogic/meson-ee-pwrc.c +++ b/drivers/soc/amlogic/meson-ee-pwrc.c @@ -413,8 +413,7 @@ static int meson_ee_pwrc_init_domain(struct platform_device *pdev, dev_warn(&pdev->dev, "Invalid resets count %d for domain %s\n", count, dom->desc.name); - dom->rstc = devm_reset_control_array_get(&pdev->dev, false, - false); + dom->rstc = devm_reset_control_array_get_exclusive(&pdev->dev); if (IS_ERR(dom->rstc)) return PTR_ERR(dom->rstc); } diff --git a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c index 8790627e3098..b4615b288625 100644 --- a/drivers/soc/amlogic/meson-gx-pwrc-vpu.c +++ b/drivers/soc/amlogic/meson-gx-pwrc-vpu.c @@ -304,7 +304,7 @@ static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev) return PTR_ERR(regmap_hhi); } - rstc = devm_reset_control_array_get(&pdev->dev, false, false); + rstc = devm_reset_control_array_get_exclusive(&pdev->dev); if (IS_ERR(rstc)) { if (PTR_ERR(rstc) != -EPROBE_DEFER) dev_err(&pdev->dev, "failed to get reset lines\n"); -- cgit v1.2.3 From 0d625a167b169f0bfdfd2e4dc05b9c89b81efe98 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 9 Nov 2020 13:21:41 -0600 Subject: reset: socfpga: add error handling and release mem-region In case of an error, call release_mem_region when an error happens during allocation of resources. Also add error handling for the case that reset_controller_register fails. Reported-by: kernel test robot Reported-by: Dan Carpenter Signed-off-by: Dinh Nguyen Signed-off-by: Philipp Zabel --- drivers/reset/reset-socfpga.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index bdd984296196..2a72f861f798 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -44,7 +44,7 @@ static int a10_reset_init(struct device_node *np) data->membase = ioremap(res.start, size); if (!data->membase) { ret = -ENOMEM; - goto err_alloc; + goto release_region; } if (of_property_read_u32(np, "altr,modrst-offset", ®_offset)) @@ -59,7 +59,14 @@ static int a10_reset_init(struct device_node *np) data->rcdev.of_node = np; data->status_active_low = true; - return reset_controller_register(&data->rcdev); + ret = reset_controller_register(&data->rcdev); + if (ret) + pr_err("unable to register device\n"); + + return ret; + +release_region: + release_mem_region(res.start, size); err_alloc: kfree(data); -- cgit v1.2.3 From d06c4dec98b655e2808d2a59681ec24197c59c9d Mon Sep 17 00:00:00 2001 From: Crystal Guo Date: Wed, 30 Sep 2020 10:21:59 +0800 Subject: reset-controller: ti: force the write operation when assert or deassert Force the write operation in case the read already happens to return the correct value. Signed-off-by: Crystal Guo Signed-off-by: Philipp Zabel --- drivers/reset/reset-ti-syscon.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index ef97c4dbbb4e..218370faf37b 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -89,7 +89,7 @@ static int ti_syscon_reset_assert(struct reset_controller_dev *rcdev, mask = BIT(control->assert_bit); value = (control->flags & ASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->assert_offset, mask, value); + return regmap_write_bits(data->regmap, control->assert_offset, mask, value); } /** @@ -120,7 +120,7 @@ static int ti_syscon_reset_deassert(struct reset_controller_dev *rcdev, mask = BIT(control->deassert_bit); value = (control->flags & DEASSERT_SET) ? mask : 0x0; - return regmap_update_bits(data->regmap, control->deassert_offset, mask, value); + return regmap_write_bits(data->regmap, control->deassert_offset, mask, value); } /** -- cgit v1.2.3 From c2867b2e710fc85bb39c6f6e5948450c48e8a33e Mon Sep 17 00:00:00 2001 From: Zhang Changzhong Date: Fri, 4 Dec 2020 16:33:25 +0800 Subject: soc: rockchip: io-domain: Fix error return code in rockchip_iodomain_probe() Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: e943c43b32ce ("PM: AVS: rockchip-io: Move the driver to the rockchip specific drivers") Reported-by: Hulk Robot Signed-off-by: Zhang Changzhong Link: https://lore.kernel.org/r/1607070805-33038-1-git-send-email-zhangchangzhong@huawei.com Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/io-domain.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/rockchip/io-domain.c b/drivers/soc/rockchip/io-domain.c index d13d2d497720..cf8182fc3642 100644 --- a/drivers/soc/rockchip/io-domain.c +++ b/drivers/soc/rockchip/io-domain.c @@ -544,6 +544,7 @@ static int rockchip_iodomain_probe(struct platform_device *pdev) if (uV < 0) { dev_err(iod->dev, "Can't determine voltage: %s\n", supply_name); + ret = uV; goto unreg_notify; } -- cgit v1.2.3 From 9bd5773e02d174dfab3c336fc43d18ec15afc5a3 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 3 Dec 2020 22:24:30 +0300 Subject: dt-bindings: memory: tegra20-emc: Document opp-supported-hw property Document opp-supported-hw property, which is not strictly necessary to have on Tegra20, but it's very convenient to have because all other SoC core devices will use hardware versioning, and thus, it's good to maintain the consistency. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201203192439.16177-2-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt index 67ac8d1297da..cc443fcf4bec 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt @@ -16,6 +16,12 @@ Properties: - #interconnect-cells : Should be 0. - operating-points-v2: See ../bindings/opp/opp.txt for details. +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: One bitfield indicating SoC process ID mask + + A bitwise AND is performed against this value and if any bit + matches, the OPP gets enabled. + Optional properties: - core-supply: Phandle of voltage regulator of the SoC "core" power domain. -- cgit v1.2.3 From 7e04ce2a9d3071f791a8147b5d3c8ddbb8e38989 Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 3 Dec 2020 22:24:31 +0300 Subject: memory: tegra20: Support hardware versioning and clean up OPP table initialization Support hardware versioning, which is now required for Tegra20 EMC OPP. Clean up OPP table initialization by using a error code returned by OPP API for judging about the OPP table presence in a device-tree and remove OPP regulator initialization because we're now going to use power domain instead of a raw regulator. This puts Tegra20 EMC OPP preparation on par with the Tegra30/124 EMC drivers. Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201203192439.16177-3-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra20-emc.c | 48 ++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 28 deletions(-) diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c index 0320d9df4a20..686aaf477d8a 100644 --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c @@ -910,43 +910,36 @@ err_msg: static int tegra_emc_opp_table_init(struct tegra_emc *emc) { - struct opp_table *reg_opp_table = NULL, *clk_opp_table; - const char *rname = "core"; + u32 hw_version = BIT(tegra_sku_info.soc_process_id); + struct opp_table *clk_opp_table, *hw_opp_table; int err; - /* - * Legacy device-trees don't have OPP table and EMC driver isn't - * useful in this case. - */ - if (!device_property_present(emc->dev, "operating-points-v2")) { - dev_err(emc->dev, - "OPP table not found, please update your device tree\n"); - return -ENODEV; - } - - /* voltage scaling is optional */ - if (device_property_present(emc->dev, "core-supply")) { - reg_opp_table = dev_pm_opp_set_regulators(emc->dev, &rname, 1); - if (IS_ERR(reg_opp_table)) - return dev_err_probe(emc->dev, PTR_ERR(reg_opp_table), - "failed to set OPP regulator\n"); - } - clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL); err = PTR_ERR_OR_ZERO(clk_opp_table); if (err) { dev_err(emc->dev, "failed to set OPP clk: %d\n", err); - goto put_reg_table; + return err; } - err = dev_pm_opp_of_add_table(emc->dev); + hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); if (err) { - dev_err(emc->dev, "failed to add OPP table: %d\n", err); + dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); goto put_clk_table; } - dev_info(emc->dev, "current clock rate %lu MHz\n", - clk_get_rate(emc->clk) / 1000000); + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + if (err == -ENODEV) + dev_err(emc->dev, "OPP table not found, please update your device tree\n"); + else + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + + goto put_hw_table; + } + + dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); /* first dummy rate-set initializes voltage state */ err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); @@ -959,11 +952,10 @@ static int tegra_emc_opp_table_init(struct tegra_emc *emc) remove_table: dev_pm_opp_of_remove_table(emc->dev); +put_hw_table: + dev_pm_opp_put_supported_hw(hw_opp_table); put_clk_table: dev_pm_opp_put_clkname(clk_opp_table); -put_reg_table: - if (reg_opp_table) - dev_pm_opp_put_regulators(reg_opp_table); return err; } -- cgit v1.2.3 From d76fa3f2c252421faf326afd5f445bed5d34075f Mon Sep 17 00:00:00 2001 From: Dmitry Osipenko Date: Thu, 3 Dec 2020 22:24:32 +0300 Subject: memory: tegra30: Support interconnect framework Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supports tuning of memory arbitration latency, which needs to be done for ISO memory clients, like a Display client for example. Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Acked-by: Georgi Djakov Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201203192439.16177-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/Kconfig | 1 + drivers/memory/tegra/tegra30-emc.c | 344 ++++++++++++++++++++++++++++++++++--- drivers/memory/tegra/tegra30.c | 173 ++++++++++++++++++- 3 files changed, 496 insertions(+), 22 deletions(-) diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig index 2a4a16bcf91c..ca7077a06f4c 100644 --- a/drivers/memory/tegra/Kconfig +++ b/drivers/memory/tegra/Kconfig @@ -24,6 +24,7 @@ config TEGRA30_EMC tristate "NVIDIA Tegra30 External Memory Controller driver" default y depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + select PM_OPP help This driver is for the External Memory Controller (EMC) found on Tegra30 chips. The EMC controls the external DRAM on the board. diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index 93f9002d32ad..44ac155936aa 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -14,16 +14,21 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include +#include +#include #include #include +#include #include #include "mc.h" @@ -323,9 +328,21 @@ struct emc_timing { bool emc_cfg_dyn_self_ref; }; +enum emc_rate_request_type { + EMC_RATE_DEBUG, + EMC_RATE_ICC, + EMC_RATE_TYPE_MAX, +}; + +struct emc_rate_request { + unsigned long min_rate; + unsigned long max_rate; +}; + struct tegra_emc { struct device *dev; struct tegra_mc *mc; + struct icc_provider provider; struct notifier_block clk_nb; struct clk *clk; void __iomem *regs; @@ -352,6 +369,15 @@ struct tegra_emc { unsigned long min_rate; unsigned long max_rate; } debugfs; + + /* + * There are multiple sources in the EMC driver which could request + * a min/max clock rate, these rates are contained in this array. + */ + struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX]; + + /* protect shared rate-change code path */ + struct mutex rate_lock; }; static int emc_seq_update_timing(struct tegra_emc *emc) @@ -1094,6 +1120,83 @@ static long emc_round_rate(unsigned long rate, return timing->rate; } +static void tegra_emc_rate_requests_init(struct tegra_emc *emc) +{ + unsigned int i; + + for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { + emc->requested_rate[i].min_rate = 0; + emc->requested_rate[i].max_rate = ULONG_MAX; + } +} + +static int emc_request_rate(struct tegra_emc *emc, + unsigned long new_min_rate, + unsigned long new_max_rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = emc->requested_rate; + unsigned long min_rate = 0, max_rate = ULONG_MAX; + unsigned int i; + int err; + + /* select minimum and maximum rates among the requested rates */ + for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { + if (i == type) { + min_rate = max(new_min_rate, min_rate); + max_rate = min(new_max_rate, max_rate); + } else { + min_rate = max(req->min_rate, min_rate); + max_rate = min(req->max_rate, max_rate); + } + } + + if (min_rate > max_rate) { + dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", + __func__, type, min_rate, max_rate); + return -ERANGE; + } + + /* + * EMC rate-changes should go via OPP API because it manages voltage + * changes. + */ + err = dev_pm_opp_set_rate(emc->dev, min_rate); + if (err) + return err; + + emc->requested_rate[type].min_rate = new_min_rate; + emc->requested_rate[type].max_rate = new_max_rate; + + return 0; +} + +static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, rate, req->max_rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + +static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, + enum emc_rate_request_type type) +{ + struct emc_rate_request *req = &emc->requested_rate[type]; + int ret; + + mutex_lock(&emc->rate_lock); + ret = emc_request_rate(emc, req->min_rate, rate, type); + mutex_unlock(&emc->rate_lock); + + return ret; +} + /* * debugfs interface * @@ -1177,7 +1280,7 @@ static int tegra_emc_debug_min_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_min_rate(emc->clk, rate); + err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -1207,7 +1310,7 @@ static int tegra_emc_debug_max_rate_set(void *data, u64 rate) if (!tegra_emc_validate_rate(emc, rate)) return -EINVAL; - err = clk_set_max_rate(emc->clk, rate); + err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); if (err < 0) return err; @@ -1264,6 +1367,214 @@ static void tegra_emc_debugfs_init(struct tegra_emc *emc) emc, &tegra_emc_debug_max_rate_fops); } +static inline struct tegra_emc * +to_tegra_emc_provider(struct icc_provider *provider) +{ + return container_of(provider, struct tegra_emc, provider); +} + +static struct icc_node_data * +emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct icc_provider *provider = data; + struct icc_node_data *ndata; + struct icc_node *node; + + /* External Memory is the only possible ICC route */ + list_for_each_entry(node, &provider->nodes, node_list) { + if (node->id != TEGRA_ICC_EMEM) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + /* + * SRC and DST nodes should have matching TAG in order to have + * it set by default for a requested path. + */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + ndata->node = node; + + return ndata; + } + + return ERR_PTR(-EPROBE_DEFER); +} + +static int emc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); + unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); + unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); + unsigned long long rate = max(avg_bw, peak_bw); + const unsigned int dram_data_bus_width_bytes = 4; + const unsigned int ddr = 2; + int err; + + /* + * Tegra30 EMC runs on a clock rate of SDRAM bus. This means that + * EMC clock rate is twice smaller than the peak data rate because + * data is sampled on both EMC clock edges. + */ + do_div(rate, ddr * dram_data_bus_width_bytes); + rate = min_t(u64, rate, U32_MAX); + + err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); + if (err) + return err; + + return 0; +} + +static int tegra_emc_interconnect_init(struct tegra_emc *emc) +{ + const struct tegra_mc_soc *soc = emc->mc->soc; + struct icc_node *node; + int err; + + emc->provider.dev = emc->dev; + emc->provider.set = emc_icc_set; + emc->provider.data = &emc->provider; + emc->provider.aggregate = soc->icc_ops->aggregate; + emc->provider.xlate_extended = emc_of_icc_xlate_extended; + + err = icc_provider_add(&emc->provider); + if (err) + goto err_msg; + + /* create External Memory Controller node */ + node = icc_node_create(TEGRA_ICC_EMC); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto del_provider; + } + + node->name = "External Memory Controller"; + icc_node_add(node, &emc->provider); + + /* link External Memory Controller to External Memory (DRAM) */ + err = icc_link_create(node, TEGRA_ICC_EMEM); + if (err) + goto remove_nodes; + + /* create External Memory node */ + node = icc_node_create(TEGRA_ICC_EMEM); + if (IS_ERR(node)) { + err = PTR_ERR(node); + goto remove_nodes; + } + + node->name = "External Memory (DRAM)"; + icc_node_add(node, &emc->provider); + + return 0; + +remove_nodes: + icc_nodes_remove(&emc->provider); +del_provider: + icc_provider_del(&emc->provider); +err_msg: + dev_err(emc->dev, "failed to initialize ICC: %d\n", err); + + return err; +} + +static int tegra_emc_opp_table_init(struct tegra_emc *emc) +{ + u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); + struct opp_table *clk_opp_table, *hw_opp_table; + int err; + + clk_opp_table = dev_pm_opp_set_clkname(emc->dev, NULL); + err = PTR_ERR_OR_ZERO(clk_opp_table); + if (err) { + dev_err(emc->dev, "failed to set OPP clk: %d\n", err); + return err; + } + + hw_opp_table = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); + err = PTR_ERR_OR_ZERO(hw_opp_table); + if (err) { + dev_err(emc->dev, "failed to set OPP supported HW: %d\n", err); + goto put_clk_table; + } + + err = dev_pm_opp_of_add_table(emc->dev); + if (err) { + if (err == -ENODEV) + dev_err(emc->dev, "OPP table not found, please update your device tree\n"); + else + dev_err(emc->dev, "failed to add OPP table: %d\n", err); + + goto put_hw_table; + } + + dev_info(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", + hw_version, clk_get_rate(emc->clk) / 1000000); + + /* first dummy rate-set initializes voltage state */ + err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); + if (err) { + dev_err(emc->dev, "failed to initialize OPP clock: %d\n", err); + goto remove_table; + } + + return 0; + +remove_table: + dev_pm_opp_of_remove_table(emc->dev); +put_hw_table: + dev_pm_opp_put_supported_hw(hw_opp_table); +put_clk_table: + dev_pm_opp_put_clkname(clk_opp_table); + + return err; +} + +static void devm_tegra_emc_unset_callback(void *data) +{ + tegra20_clk_set_emc_round_callback(NULL, NULL); +} + +static void devm_tegra_emc_unreg_clk_notifier(void *data) +{ + struct tegra_emc *emc = data; + + clk_notifier_unregister(emc->clk, &emc->clk_nb); +} + +static int tegra_emc_init_clk(struct tegra_emc *emc) +{ + int err; + + tegra20_clk_set_emc_round_callback(emc_round_rate, emc); + + err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, + NULL); + if (err) + return err; + + emc->clk = devm_clk_get(emc->dev, NULL); + if (IS_ERR(emc->clk)) { + dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); + return PTR_ERR(emc->clk); + } + + err = clk_notifier_register(emc->clk, &emc->clk_nb); + if (err) { + dev_err(emc->dev, "failed to register clk notifier: %d\n", err); + return err; + } + + err = devm_add_action_or_reset(emc->dev, + devm_tegra_emc_unreg_clk_notifier, emc); + if (err) + return err; + + return 0; +} + static int tegra_emc_probe(struct platform_device *pdev) { struct device_node *np; @@ -1278,6 +1589,7 @@ static int tegra_emc_probe(struct platform_device *pdev) if (IS_ERR(emc->mc)) return PTR_ERR(emc->mc); + mutex_init(&emc->rate_lock); emc->clk_nb.notifier_call = emc_clk_change_notify; emc->dev = &pdev->dev; @@ -1310,24 +1622,18 @@ static int tegra_emc_probe(struct platform_device *pdev) return err; } - tegra20_clk_set_emc_round_callback(emc_round_rate, emc); - - emc->clk = devm_clk_get(&pdev->dev, "emc"); - if (IS_ERR(emc->clk)) { - err = PTR_ERR(emc->clk); - dev_err(&pdev->dev, "failed to get emc clock: %d\n", err); - goto unset_cb; - } + err = tegra_emc_init_clk(emc); + if (err) + return err; - err = clk_notifier_register(emc->clk, &emc->clk_nb); - if (err) { - dev_err(&pdev->dev, "failed to register clk notifier: %d\n", - err); - goto unset_cb; - } + err = tegra_emc_opp_table_init(emc); + if (err) + return err; platform_set_drvdata(pdev, emc); + tegra_emc_rate_requests_init(emc); tegra_emc_debugfs_init(emc); + tegra_emc_interconnect_init(emc); /* * Don't allow the kernel module to be unloaded. Unloading adds some @@ -1337,11 +1643,6 @@ static int tegra_emc_probe(struct platform_device *pdev) try_module_get(THIS_MODULE); return 0; - -unset_cb: - tegra20_clk_set_emc_round_callback(NULL, NULL); - - return err; } static int tegra_emc_suspend(struct device *dev) @@ -1395,6 +1696,7 @@ static struct platform_driver tegra_emc_driver = { .of_match_table = tegra_emc_of_match, .pm = &tegra_emc_pm_ops, .suppress_bind_attrs = true, + .sync_state = icc_sync_state, }, }; module_platform_driver(tegra_emc_driver); diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index d0314f29608d..ea849003014b 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -4,7 +4,8 @@ */ #include -#include +#include +#include #include @@ -1083,6 +1084,175 @@ static const struct tegra_mc_reset tegra30_mc_resets[] = { TEGRA30_MC_RESET(VI, 0x200, 0x204, 17), }; +static void tegra30_mc_tune_client_latency(struct tegra_mc *mc, + const struct tegra_mc_client *client, + unsigned int bandwidth_mbytes_sec) +{ + u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div; + const struct tegra_mc_la *la = &client->la; + unsigned int fifo_size = client->fifo_size; + u32 arb_nsec, la_ticks, value; + + /* see 18.4.1 Client Configuration in Tegra3 TRM v03p */ + if (bandwidth_mbytes_sec) + arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec; + else + arb_nsec = U32_MAX; + + /* + * Latency allowness should be set with consideration for the module's + * latency tolerance and internal buffering capabilities. + * + * Display memory clients use isochronous transfers and have very low + * tolerance to a belated transfers. Hence we need to compensate the + * memory arbitration imperfection for them in order to prevent FIFO + * underflow condition when memory bus is busy. + * + * VI clients also need a stronger compensation. + */ + switch (client->swgroup) { + case TEGRA_SWGROUP_MPCORE: + case TEGRA_SWGROUP_PTC: + /* + * We always want lower latency for these clients, hence + * don't touch them. + */ + return; + + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 2; + break; + + case TEGRA_SWGROUP_VI: + arb_tolerance_compensation_nsec = 1050; + arb_tolerance_compensation_div = 1; + break; + + default: + arb_tolerance_compensation_nsec = 150; + arb_tolerance_compensation_div = 1; + break; + } + + if (arb_nsec > arb_tolerance_compensation_nsec) + arb_nsec -= arb_tolerance_compensation_nsec; + else + arb_nsec = 0; + + arb_nsec /= arb_tolerance_compensation_div; + + /* + * Latency allowance is a number of ticks a request from a particular + * client may wait in the EMEM arbiter before it becomes a high-priority + * request. + */ + la_ticks = arb_nsec / mc->tick; + la_ticks = min(la_ticks, la->mask); + + value = mc_readl(mc, la->reg); + value &= ~(la->mask << la->shift); + value |= la_ticks << la->shift; + mc_writel(mc, value, la->reg); +} + +static int tegra30_mc_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider); + const struct tegra_mc_client *client = &mc->soc->clients[src->id]; + u64 peak_bandwidth = icc_units_to_bps(src->peak_bw); + + /* + * Skip pre-initialization that is done by icc_node_add(), which sets + * bandwidth to maximum for all clients before drivers are loaded. + * + * This doesn't make sense for us because we don't have drivers for all + * clients and it's okay to keep configuration left from bootloader + * during boot, at least for today. + */ + if (src == dst) + return 0; + + /* convert bytes/sec to megabytes/sec */ + do_div(peak_bandwidth, 1000000); + + tegra30_mc_tune_client_latency(mc, client, peak_bandwidth); + + return 0; +} + +static int tegra30_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw, + u32 peak_bw, u32 *agg_avg, u32 *agg_peak) +{ + /* + * ISO clients need to reserve extra bandwidth up-front because + * there could be high bandwidth pressure during initial filling + * of the client's FIFO buffers. Secondly, we need to take into + * account impurities of the memory subsystem. + */ + if (tag & TEGRA_MC_ICC_TAG_ISO) + peak_bw = tegra_mc_scale_percents(peak_bw, 400); + + *agg_avg += avg_bw; + *agg_peak = max(*agg_peak, peak_bw); + + return 0; +} + +static struct icc_node_data * +tegra30_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data) +{ + struct tegra_mc *mc = icc_provider_to_tegra_mc(data); + const struct tegra_mc_client *client; + unsigned int i, idx = spec->args[0]; + struct icc_node_data *ndata; + struct icc_node *node; + + list_for_each_entry(node, &mc->provider.nodes, node_list) { + if (node->id != idx) + continue; + + ndata = kzalloc(sizeof(*ndata), GFP_KERNEL); + if (!ndata) + return ERR_PTR(-ENOMEM); + + client = &mc->soc->clients[idx]; + ndata->node = node; + + switch (client->swgroup) { + case TEGRA_SWGROUP_DC: + case TEGRA_SWGROUP_DCB: + case TEGRA_SWGROUP_PTC: + case TEGRA_SWGROUP_VI: + /* these clients are isochronous by default */ + ndata->tag = TEGRA_MC_ICC_TAG_ISO; + break; + + default: + ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT; + break; + } + + return ndata; + } + + for (i = 0; i < mc->soc->num_clients; i++) { + if (mc->soc->clients[i].id == idx) + return ERR_PTR(-EPROBE_DEFER); + } + + dev_err(mc->dev, "invalid ICC client ID %u\n", idx); + + return ERR_PTR(-EINVAL); +} + +static const struct tegra_mc_icc_ops tegra30_mc_icc_ops = { + .xlate_extended = tegra30_mc_of_icc_xlate_extended, + .aggregate = tegra30_mc_icc_aggreate, + .set = tegra30_mc_icc_set, +}; + const struct tegra_mc_soc tegra30_mc_soc = { .clients = tegra30_mc_clients, .num_clients = ARRAY_SIZE(tegra30_mc_clients), @@ -1097,4 +1267,5 @@ const struct tegra_mc_soc tegra30_mc_soc = { .reset_ops = &tegra_mc_reset_ops_common, .resets = tegra30_mc_resets, .num_resets = ARRAY_SIZE(tegra30_mc_resets), + .icc_ops = &tegra30_mc_icc_ops, }; -- cgit v1.2.3 From d77d22d701b0471584abe1871570bb43deb6e3c4 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 4 Dec 2020 00:08:14 +0100 Subject: memory: ti-emif-sram: only build for ARMv7 The driver can be compile-tested on all ARM machines, but causes a failure when built for ARMv7-M: arm-linux-gnueabi-ld: error: drivers/memory/ti-emif-sram-pm.o: conflicting architecture profiles A/M Limit the target machines to configurations that have ARMv7 enabled. Fixes: ea0c0ad6b6eb ("memory: Enable compile testing for most of the drivers") Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20201203230832.1481767-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski --- drivers/memory/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index eebd2ddcd860..3ea6913df176 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -128,7 +128,7 @@ config OMAP_GPMC_DEBUG config TI_EMIF_SRAM tristate "Texas Instruments EMIF SRAM driver" - depends on SOC_AM33XX || SOC_AM43XX || (ARM && COMPILE_TEST) + depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST) depends on SRAM help This driver is for the EMIF module available on Texas Instruments -- cgit v1.2.3 From 4bfa07300b9334b487ed4f3d4901c35ebb31b7ca Mon Sep 17 00:00:00 2001 From: Zhang Changzhong Date: Fri, 4 Dec 2020 16:31:57 +0800 Subject: memory: jz4780_nemc: Fix potential NULL dereference in jz4780_nemc_probe() platform_get_resource() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. This is detected by Coccinelle semantic patch. Fixes: 911a88829725 ("memory: jz4780-nemc: driver for the NEMC on JZ4780 SoCs") Signed-off-by: Zhang Changzhong Acked-by: Paul Cercueil Link: https://lore.kernel.org/r/1607070717-32880-1-git-send-email-zhangchangzhong@huawei.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/jz4780-nemc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c index 608ae925e641..555f7ac3b7dd 100644 --- a/drivers/memory/jz4780-nemc.c +++ b/drivers/memory/jz4780-nemc.c @@ -291,6 +291,8 @@ static int jz4780_nemc_probe(struct platform_device *pdev) nemc->dev = dev; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; /* * The driver currently only uses the registers up to offset -- cgit v1.2.3 From 7136d6a92aed6b4a1bfa5b2fe62b0ec27883b3f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Dec 2020 21:59:54 +0200 Subject: soc: samsung: exynos-chipid: order list of SoCs by name Bring some order to the list of SoCs. No functional change. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201202195955.128633-1-krzk@kernel.org --- drivers/soc/samsung/exynos-chipid.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 8d4d05086906..b4cd0cc00f45 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -20,6 +20,7 @@ static const struct exynos_soc_id { const char *name; unsigned int id; } soc_ids[] = { + /* List ordered by SoC name */ { "EXYNOS3250", 0xE3472000 }, { "EXYNOS4210", 0x43200000 }, /* EVT0 revision */ { "EXYNOS4210", 0x43210000 }, @@ -29,10 +30,10 @@ static const struct exynos_soc_id { { "EXYNOS5260", 0xE5260000 }, { "EXYNOS5410", 0xE5410000 }, { "EXYNOS5420", 0xE5420000 }, + { "EXYNOS5433", 0xE5433000 }, { "EXYNOS5440", 0xE5440000 }, { "EXYNOS5800", 0xE5422000 }, { "EXYNOS7420", 0xE7420000 }, - { "EXYNOS5433", 0xE5433000 }, }; static const char * __init product_id_to_soc_id(unsigned int product_id) -- cgit v1.2.3 From 3b4c362e5ef102ca2d70d33f4e8cf0780053a7db Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 2 Dec 2020 21:59:55 +0200 Subject: soc: samsung: exynos-chipid: initialize later - with arch_initcall The Exynos ChipID driver on Exynos SoCs has only informational purpose - to expose the SoC device in sysfs. No other drivers depend on it so there is really no benefit of initializing it early. Instead, initialize everything with arch_initcall which: 1. Allows to use dev_info() as the SoC bus is present (since core_initcall), 2. Could speed things up because of execution in a SMP environment (after bringing up secondary CPUs, unlike early_initcall), 3. Reduces the amount of work to be done early, when the kernel has to bring up critical devices. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20201202195955.128633-2-krzk@kernel.org --- drivers/soc/samsung/exynos-chipid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index b4cd0cc00f45..1a76eade2ed6 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -99,9 +99,9 @@ static int __init exynos_chipid_early_init(void) goto err; } - /* it is too early to use dev_info() here (soc_dev is NULL) */ - pr_info("soc soc0: Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n", - soc_dev_attr->soc_id, product_id, revision); + dev_info(soc_device_to_device(soc_dev), + "Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n", + soc_dev_attr->soc_id, product_id, revision); return 0; @@ -111,4 +111,4 @@ err: return ret; } -early_initcall(exynos_chipid_early_init); +arch_initcall(exynos_chipid_early_init); -- cgit v1.2.3 From 4c44274ee457e3f7012dc532c8c9cc8964a82612 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 4 Dec 2020 10:16:11 +0100 Subject: clk: samsung: mark PM functions as __maybe_unused The use of SIMPLE_DEV_PM_OPS() means that the suspend/resume functions are now unused when CONFIG_PM is disabled: drivers/clk/samsung/clk-exynos-clkout.c:219:12: error: 'exynos_clkout_resume' defined but not used [-Werror=unused-function] 219 | static int exynos_clkout_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ drivers/clk/samsung/clk-exynos-clkout.c:210:12: error: 'exynos_clkout_suspend' defined but not used [-Werror=unused-function] 210 | static int exynos_clkout_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ Mark them as __maybe_unused to shut up the otherwise harmless warning. Fixes: 9484f2cb8332 ("clk: samsung: exynos-clkout: convert to module driver") Signed-off-by: Arnd Bergmann Acked-by: Chanwoo Choi Acked-by: Sylwester Nawrocki Link: https://lore.kernel.org/r/20201204091616.4128366-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos-clkout.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index 9ec2f40cc400..e6d6cbf8c4e6 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -207,7 +207,7 @@ static int exynos_clkout_remove(struct platform_device *pdev) return 0; } -static int exynos_clkout_suspend(struct device *dev) +static int __maybe_unused exynos_clkout_suspend(struct device *dev) { struct exynos_clkout *clkout = dev_get_drvdata(dev); @@ -216,7 +216,7 @@ static int exynos_clkout_suspend(struct device *dev) return 0; } -static int exynos_clkout_resume(struct device *dev) +static int __maybe_unused exynos_clkout_resume(struct device *dev) { struct exynos_clkout *clkout = dev_get_drvdata(dev); -- cgit v1.2.3 From 853e69d6c87c463563eb33e060d0ab6566b1452b Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Mon, 9 Nov 2020 14:48:15 +0100 Subject: soc: xilinx: vcu: drop useless success message The message that the driver was successfully probed only adds useless noise. Drop the message. Signed-off-by: Michael Tretter Reviewed-by: Hyun Kwon Link: https://lore.kernel.org/r/20201109134818.4159342-2-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- drivers/soc/xilinx/xlnx_vcu.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index a3aa40996f13..dcd8e7824b06 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -571,8 +571,6 @@ static int xvcu_probe(struct platform_device *pdev) dev_set_drvdata(&pdev->dev, xvcu); - dev_info(&pdev->dev, "%s: Probed successfully\n", __func__); - return 0; error_pll_ref: -- cgit v1.2.3 From a3857f89ddb05097d4cffeb3884d6e26da8a34e2 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Mon, 9 Nov 2020 14:48:16 +0100 Subject: dt-bindings: soc: xlnx: extract xlnx, vcu-settings to separate binding The xlnx,vcu binding comprises two adjacent register banks: The first register bank ("vcu_slcr") contains registers for setting the clocks of the vcu and controlling the performance monitors. The second bank ("logicoreip") contains the configuration settings of the video codec unit, which are set before synthesizing the bitstream. Drivers that drive the actual video codec unit need to read the registers from the logicoreip register bank for configuring the vcu firmware. As logicoreip is a too generic name for this register bank, use "vcu-settings" as a binding name, because the register bank basically provides the configuration settings of the VCU. Therefore, add the vcu-settings binding to provide a syscon interface for other drivers to read these registers. The alternative would have been to merge the two register banks of the xlnx,vcu binding into one register bank and make xlnx,vcu provide a syscon interface, but that would lead to more incompatibility than making second register bank of xlnx,vcu optional. Signed-off-by: Michael Tretter Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201109134818.4159342-3-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- .../bindings/soc/xilinx/xlnx,vcu-settings.yaml | 34 ++++++++++++++++++++++ .../devicetree/bindings/soc/xilinx/xlnx,vcu.txt | 9 ++---- 2 files changed, 36 insertions(+), 7 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu-settings.yaml diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu-settings.yaml b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu-settings.yaml new file mode 100644 index 000000000000..378d0ced43c8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu-settings.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/xilinx/xlnx,vcu-settings.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx VCU Settings + +maintainers: + - Michael Tretter + +description: | + The Xilinx VCU Settings provides information about the configuration of the + video codec unit. + +properties: + compatible: + items: + - const: xlnx,vcu-settings + - const: syscon + + reg: + maxItems: 1 + +required: + - compatible + - reg + +examples: + - | + xlnx_vcu: vcu@a0041000 { + compatible = "xlnx,vcu-settings", "syscon"; + reg = <0x0 0xa0041000 0x0 0x1000>; + }; diff --git a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt index 6786d6715df0..2417b13ba468 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt +++ b/Documentation/devicetree/bindings/soc/xilinx/xlnx,vcu.txt @@ -12,10 +12,7 @@ Required properties: - compatible: shall be one of: "xlnx,vcu" "xlnx,vcu-logicoreip-1.0" -- reg, reg-names: There are two sets of registers need to provide. - 1. vcu slcr - 2. Logicore - reg-names should contain name for the each register sequence. +- reg : The base offset and size of the VCU_PL_SLCR register space. - clocks: phandle for aclk and pll_ref clocksource - clock-names: The identification string, "aclk", is always required for the axi clock. "pll_ref" is required for pll. @@ -23,9 +20,7 @@ Example: xlnx_vcu: vcu@a0040000 { compatible = "xlnx,vcu-logicoreip-1.0"; - reg = <0x0 0xa0040000 0x0 0x1000>, - <0x0 0xa0041000 0x0 0x1000>; - reg-names = "vcu_slcr", "logicore"; + reg = <0x0 0xa0040000 0x0 0x1000>; clocks = <&si570_1>, <&clkc 71>; clock-names = "pll_ref", "aclk"; }; -- cgit v1.2.3 From 30b79eb1f92ed5974885d374a4107c94e2dd3e03 Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Mon, 9 Nov 2020 14:48:17 +0100 Subject: soc: xilinx: vcu: use vcu-settings syscon registers Switch the "logicoreip" registers to the new xlnx,vcu-settings binding to be able to read the settings if the settings are specified in a separate device tree node that is shared with other drivers. If the driver is not able to find a node with the new binding, fall back to check for the logicore register bank to be backwards compatible. Signed-off-by: Michael Tretter Reviewed-by: Hyun Kwon Link: https://lore.kernel.org/r/20201109134818.4159342-4-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- drivers/soc/xilinx/Kconfig | 1 + drivers/soc/xilinx/xlnx_vcu.c | 94 ++++++++++++++++++------------------- include/linux/mfd/syscon/xlnx-vcu.h | 38 +++++++++++++++ 3 files changed, 86 insertions(+), 47 deletions(-) create mode 100644 include/linux/mfd/syscon/xlnx-vcu.h diff --git a/drivers/soc/xilinx/Kconfig b/drivers/soc/xilinx/Kconfig index 646512d7276f..0b1708dae361 100644 --- a/drivers/soc/xilinx/Kconfig +++ b/drivers/soc/xilinx/Kconfig @@ -4,6 +4,7 @@ menu "Xilinx SoC drivers" config XILINX_VCU tristate "Xilinx VCU logicoreIP Init" depends on HAS_IOMEM + select REGMAP_MMIO help Provides the driver to enable and disable the isolation between the processing system and programmable logic part by using the logicoreIP diff --git a/drivers/soc/xilinx/xlnx_vcu.c b/drivers/soc/xilinx/xlnx_vcu.c index dcd8e7824b06..14daad4efc58 100644 --- a/drivers/soc/xilinx/xlnx_vcu.c +++ b/drivers/soc/xilinx/xlnx_vcu.c @@ -10,39 +10,12 @@ #include #include #include +#include +#include #include #include #include - -/* Address map for different registers implemented in the VCU LogiCORE IP. */ -#define VCU_ECODER_ENABLE 0x00 -#define VCU_DECODER_ENABLE 0x04 -#define VCU_MEMORY_DEPTH 0x08 -#define VCU_ENC_COLOR_DEPTH 0x0c -#define VCU_ENC_VERTICAL_RANGE 0x10 -#define VCU_ENC_FRAME_SIZE_X 0x14 -#define VCU_ENC_FRAME_SIZE_Y 0x18 -#define VCU_ENC_COLOR_FORMAT 0x1c -#define VCU_ENC_FPS 0x20 -#define VCU_MCU_CLK 0x24 -#define VCU_CORE_CLK 0x28 -#define VCU_PLL_BYPASS 0x2c -#define VCU_ENC_CLK 0x30 -#define VCU_PLL_CLK 0x34 -#define VCU_ENC_VIDEO_STANDARD 0x38 -#define VCU_STATUS 0x3c -#define VCU_AXI_ENC_CLK 0x40 -#define VCU_AXI_DEC_CLK 0x44 -#define VCU_AXI_MCU_CLK 0x48 -#define VCU_DEC_VIDEO_STANDARD 0x4c -#define VCU_DEC_FRAME_SIZE_X 0x50 -#define VCU_DEC_FRAME_SIZE_Y 0x54 -#define VCU_DEC_FPS 0x58 -#define VCU_BUFFER_B_FRAME 0x5c -#define VCU_WPP_EN 0x60 -#define VCU_PLL_CLK_DEC 0x64 -#define VCU_GASKET_INIT 0x74 -#define VCU_GASKET_VALUE 0x03 +#include /* vcu slcr registers, bitmask and shift */ #define VCU_PLL_CTRL 0x24 @@ -106,11 +79,20 @@ struct xvcu_device { struct device *dev; struct clk *pll_ref; struct clk *aclk; - void __iomem *logicore_reg_ba; + struct regmap *logicore_reg_ba; void __iomem *vcu_slcr_ba; u32 coreclk; }; +static struct regmap_config vcu_settings_regmap_config = { + .name = "regmap", + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0xfff, + .cache_type = REGCACHE_NONE, +}; + /** * struct xvcu_pll_cfg - Helper data * @fbdiv: The integer portion of the feedback divider to the PLL @@ -300,10 +282,12 @@ static int xvcu_set_vcu_pll_info(struct xvcu_device *xvcu) int ret, i; const struct xvcu_pll_cfg *found = NULL; - inte = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK); - deci = xvcu_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC); - coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; - mcuclk = xvcu_read(xvcu->logicore_reg_ba, VCU_MCU_CLK) * MHZ; + regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK, &inte); + regmap_read(xvcu->logicore_reg_ba, VCU_PLL_CLK_DEC, &deci); + regmap_read(xvcu->logicore_reg_ba, VCU_CORE_CLK, &coreclk); + coreclk *= MHZ; + regmap_read(xvcu->logicore_reg_ba, VCU_MCU_CLK, &mcuclk); + mcuclk *= MHZ; if (!mcuclk || !coreclk) { dev_err(xvcu->dev, "Invalid mcu and core clock data\n"); return -EINVAL; @@ -498,6 +482,7 @@ static int xvcu_probe(struct platform_device *pdev) { struct resource *res; struct xvcu_device *xvcu; + void __iomem *regs; int ret; xvcu = devm_kzalloc(&pdev->dev, sizeof(*xvcu), GFP_KERNEL); @@ -518,17 +503,32 @@ static int xvcu_probe(struct platform_device *pdev) return -ENOMEM; } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "logicore"); - if (!res) { - dev_err(&pdev->dev, "get logicore memory resource failed.\n"); - return -ENODEV; - } + xvcu->logicore_reg_ba = + syscon_regmap_lookup_by_compatible("xlnx,vcu-settings"); + if (IS_ERR(xvcu->logicore_reg_ba)) { + dev_info(&pdev->dev, + "could not find xlnx,vcu-settings: trying direct register access\n"); + + res = platform_get_resource_byname(pdev, + IORESOURCE_MEM, "logicore"); + if (!res) { + dev_err(&pdev->dev, "get logicore memory resource failed.\n"); + return -ENODEV; + } - xvcu->logicore_reg_ba = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (!xvcu->logicore_reg_ba) { - dev_err(&pdev->dev, "logicore register mapping failed.\n"); - return -ENOMEM; + regs = devm_ioremap(&pdev->dev, res->start, resource_size(res)); + if (!regs) { + dev_err(&pdev->dev, "logicore register mapping failed.\n"); + return -ENOMEM; + } + + xvcu->logicore_reg_ba = + devm_regmap_init_mmio(&pdev->dev, regs, + &vcu_settings_regmap_config); + if (IS_ERR(xvcu->logicore_reg_ba)) { + dev_err(&pdev->dev, "failed to init regmap\n"); + return PTR_ERR(xvcu->logicore_reg_ba); + } } xvcu->aclk = devm_clk_get(&pdev->dev, "aclk"); @@ -560,7 +560,7 @@ static int xvcu_probe(struct platform_device *pdev) * Bit 0 : Gasket isolation * Bit 1 : put VCU out of reset */ - xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE); + regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, VCU_GASKET_VALUE); /* Do the PLL Settings based on the ref clk,core and mcu clk freq */ ret = xvcu_set_pll(xvcu); @@ -597,7 +597,7 @@ static int xvcu_remove(struct platform_device *pdev) return -ENODEV; /* Add the the Gasket isolation and put the VCU in reset. */ - xvcu_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); + regmap_write(xvcu->logicore_reg_ba, VCU_GASKET_INIT, 0); clk_disable_unprepare(xvcu->pll_ref); clk_disable_unprepare(xvcu->aclk); diff --git a/include/linux/mfd/syscon/xlnx-vcu.h b/include/linux/mfd/syscon/xlnx-vcu.h new file mode 100644 index 000000000000..d3edec4b7b1d --- /dev/null +++ b/include/linux/mfd/syscon/xlnx-vcu.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2020 Pengutronix, Michael Tretter + */ + +#ifndef __XLNX_VCU_H +#define __XLNX_VCU_H + +#define VCU_ECODER_ENABLE 0x00 +#define VCU_DECODER_ENABLE 0x04 +#define VCU_MEMORY_DEPTH 0x08 +#define VCU_ENC_COLOR_DEPTH 0x0c +#define VCU_ENC_VERTICAL_RANGE 0x10 +#define VCU_ENC_FRAME_SIZE_X 0x14 +#define VCU_ENC_FRAME_SIZE_Y 0x18 +#define VCU_ENC_COLOR_FORMAT 0x1c +#define VCU_ENC_FPS 0x20 +#define VCU_MCU_CLK 0x24 +#define VCU_CORE_CLK 0x28 +#define VCU_PLL_BYPASS 0x2c +#define VCU_ENC_CLK 0x30 +#define VCU_PLL_CLK 0x34 +#define VCU_ENC_VIDEO_STANDARD 0x38 +#define VCU_STATUS 0x3c +#define VCU_AXI_ENC_CLK 0x40 +#define VCU_AXI_DEC_CLK 0x44 +#define VCU_AXI_MCU_CLK 0x48 +#define VCU_DEC_VIDEO_STANDARD 0x4c +#define VCU_DEC_FRAME_SIZE_X 0x50 +#define VCU_DEC_FRAME_SIZE_Y 0x54 +#define VCU_DEC_FPS 0x58 +#define VCU_BUFFER_B_FRAME 0x5c +#define VCU_WPP_EN 0x60 +#define VCU_PLL_CLK_DEC 0x64 +#define VCU_GASKET_INIT 0x74 +#define VCU_GASKET_VALUE 0x03 + +#endif /* __XLNX_VCU_H */ -- cgit v1.2.3 From 7b1c9b8441aa94a549a90fa3d42687ccbad3eade Mon Sep 17 00:00:00 2001 From: Michael Tretter Date: Mon, 9 Nov 2020 14:48:18 +0100 Subject: soc: xilinx: vcu: add missing register NUM_CORE The H.264/H.265 Video Codec Unit v1.2 documentation describes this register as follows: Number of encoders core used for the provided configuration This is required for configuring the VCU encoder buffer. Signed-off-by: Michael Tretter Reviewed-by: Hyun Kwon Link: https://lore.kernel.org/r/20201109134818.4159342-5-m.tretter@pengutronix.de Signed-off-by: Michal Simek --- include/linux/mfd/syscon/xlnx-vcu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/mfd/syscon/xlnx-vcu.h b/include/linux/mfd/syscon/xlnx-vcu.h index d3edec4b7b1d..ff7bc3656f6e 100644 --- a/include/linux/mfd/syscon/xlnx-vcu.h +++ b/include/linux/mfd/syscon/xlnx-vcu.h @@ -32,6 +32,7 @@ #define VCU_BUFFER_B_FRAME 0x5c #define VCU_WPP_EN 0x60 #define VCU_PLL_CLK_DEC 0x64 +#define VCU_NUM_CORE 0x6c #define VCU_GASKET_INIT 0x74 #define VCU_GASKET_VALUE 0x03 -- cgit v1.2.3 From 463edf5a59fd8f0fe0135101d67bfca81d1e3771 Mon Sep 17 00:00:00 2001 From: Wendy Liang Date: Tue, 24 Nov 2020 00:18:18 -0800 Subject: firmware: xlnx-zynqmp: fix compilation warning Fix compilation warning when ZYNQMP_FIRMWARE is not defined. include/linux/firmware/xlnx-zynqmp.h: In function 'zynqmp_pm_get_eemi_ops': include/linux/firmware/xlnx-zynqmp.h:363:9: error: implicit declaration of function 'ERR_PTR' [-Werror=implicit-function-declaration] 363 | return ERR_PTR(-ENODEV); include/linux/firmware/xlnx-zynqmp.h:363:18: note: each undeclared identifier is reported only once for each function it appears in include/linux/firmware/xlnx-zynqmp.h: In function 'zynqmp_pm_get_api_version': include/linux/firmware/xlnx-zynqmp.h:367:10: error: 'ENODEV' undeclared (first use in this function) 367 | return -ENODEV; | ^~~~~~ Signed-off-by: Wendy Liang Link: https://lore.kernel.org/r/1606205898-12642-1-git-send-email-wendy.liang@xilinx.com Signed-off-by: Michal Simek --- include/linux/firmware/xlnx-zynqmp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 5968df82b991..f84244ea633b 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -13,6 +13,8 @@ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ +#include + #define ZYNQMP_PM_VERSION_MAJOR 1 #define ZYNQMP_PM_VERSION_MINOR 0 -- cgit v1.2.3 From 332bee16406675b7383e52c8f775dab1585e957c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 1 Dec 2020 15:29:59 +0100 Subject: firmware: xilinx: Fix kernel-doc warnings kernel-doc is reporting some style issues. The patch is fixing them. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/e606233d15bfdc594535dd34eb85472b42f61830.1606832997.git.michal.simek@xilinx.com --- drivers/firmware/xilinx/zynqmp.c | 46 ++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 8d1ff2454e2e..e5ac3008a1d7 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -585,13 +585,13 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_get_pll_frac_data); /** * zynqmp_pm_set_sd_tapdelay() - Set tap delay for the SD device * - * @node_id Node ID of the device - * @type Type of tap delay to set (input/output) - * @value Value to set fot the tap delay + * @node_id: Node ID of the device + * @type: Type of tap delay to set (input/output) + * @value: Value to set fot the tap delay * * This function sets input/output tap delay for the SD device. * - * @return Returns status, either success or error+reason + * Return: Returns status, either success or error+reason */ int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) { @@ -603,12 +603,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_set_sd_tapdelay); /** * zynqmp_pm_sd_dll_reset() - Reset DLL logic * - * @node_id Node ID of the device - * @type Reset type + * @node_id: Node ID of the device + * @type: Reset type * * This function resets DLL logic for the SD device. * - * @return Returns status, either success or error+reason + * Return: Returns status, either success or error+reason */ int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) { @@ -619,12 +619,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_sd_dll_reset); /** * zynqmp_pm_write_ggs() - PM API for writing global general storage (ggs) - * @index GGS register index - * @value Register value to be written + * @index: GGS register index + * @value: Register value to be written * * This function writes value to GGS register. * - * @return Returns status, either success or error+reason + * Return: Returns status, either success or error+reason */ int zynqmp_pm_write_ggs(u32 index, u32 value) { @@ -635,12 +635,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_write_ggs); /** * zynqmp_pm_write_ggs() - PM API for reading global general storage (ggs) - * @index GGS register index - * @value Register value to be written + * @index: GGS register index + * @value: Register value to be written * * This function returns GGS register value. * - * @return Returns status, either success or error+reason + * Return: Returns status, either success or error+reason */ int zynqmp_pm_read_ggs(u32 index, u32 *value) { @@ -652,12 +652,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_read_ggs); /** * zynqmp_pm_write_pggs() - PM API for writing persistent global general * storage (pggs) - * @index PGGS register index - * @value Register value to be written + * @index: PGGS register index + * @value: Register value to be written * * This function writes value to PGGS register. * - * @return Returns status, either success or error+reason + * Return: Returns status, either success or error+reason */ int zynqmp_pm_write_pggs(u32 index, u32 value) { @@ -669,12 +669,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_write_pggs); /** * zynqmp_pm_write_pggs() - PM API for reading persistent global general * storage (pggs) - * @index PGGS register index - * @value Register value to be written + * @index: PGGS register index + * @value: Register value to be written * * This function returns PGGS register value. * - * @return Returns status, either success or error+reason + * Return: Returns status, either success or error+reason */ int zynqmp_pm_read_pggs(u32 index, u32 *value) { @@ -685,12 +685,12 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_read_pggs); /** * zynqmp_pm_set_boot_health_status() - PM API for setting healthy boot status - * @value Status value to be written + * @value: Status value to be written * * This function sets healthy bit value to indicate boot health status * to firmware. * - * @return Returns status, either success or error+reason + * Return: Returns status, either success or error+reason */ int zynqmp_pm_set_boot_health_status(u32 value) { @@ -785,10 +785,10 @@ EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status); * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller * master has initialized its own power management * + * Return: Returns status, either success or error+reason + * * This API function is to be used for notify the power management controller * about the completed power management initialization. - * - * Return: Returns status, either success or error+reason */ int zynqmp_pm_init_finalize(void) { -- cgit v1.2.3 From 1f6a11a01059f9c65f8461987cc0bab4c0b58338 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 2 Dec 2020 08:38:48 +0100 Subject: firmware: xilinx: Remove additional newline This additional newline is useless and also reported by checkpatch --strict. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/d927f3f2c97910958dd77a22828cd0bf8d89c9de.1606894725.git.michal.simek@xilinx.com --- include/linux/firmware/xlnx-zynqmp.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index f84244ea633b..0db9005782d6 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -316,7 +316,6 @@ struct zynqmp_pm_query_data { u32 arg3; }; - int zynqmp_pm_invoke_fn(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); -- cgit v1.2.3 From a80cefec2c2783166727324bde724c39aa8a12df Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 2 Dec 2020 08:38:49 +0100 Subject: firmware: xilinx: Add a blank line after function declaration Fix all these issues which are also reported by checkpatch --strict. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7b6007e05f6c01214861a37f198cd5bee62a4d3e.1606894725.git.michal.simek@xilinx.com --- include/linux/firmware/xlnx-zynqmp.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 0db9005782d6..0e7e72650ed3 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -363,107 +363,132 @@ static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { return ERR_PTR(-ENODEV); } + static inline int zynqmp_pm_get_api_version(u32 *version) { return -ENODEV; } + static inline int zynqmp_pm_get_chipid(u32 *idcode, u32 *version) { return -ENODEV; } + static inline int zynqmp_pm_query_data(struct zynqmp_pm_query_data qdata, u32 *out) { return -ENODEV; } + static inline int zynqmp_pm_clock_enable(u32 clock_id) { return -ENODEV; } + static inline int zynqmp_pm_clock_disable(u32 clock_id) { return -ENODEV; } + static inline int zynqmp_pm_clock_getstate(u32 clock_id, u32 *state) { return -ENODEV; } + static inline int zynqmp_pm_clock_setdivider(u32 clock_id, u32 divider) { return -ENODEV; } + static inline int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) { return -ENODEV; } + static inline int zynqmp_pm_clock_setrate(u32 clock_id, u64 rate) { return -ENODEV; } + static inline int zynqmp_pm_clock_getrate(u32 clock_id, u64 *rate) { return -ENODEV; } + static inline int zynqmp_pm_clock_setparent(u32 clock_id, u32 parent_id) { return -ENODEV; } + static inline int zynqmp_pm_clock_getparent(u32 clock_id, u32 *parent_id) { return -ENODEV; } + static inline int zynqmp_pm_set_pll_frac_mode(u32 clk_id, u32 mode) { return -ENODEV; } + static inline int zynqmp_pm_get_pll_frac_mode(u32 clk_id, u32 *mode) { return -ENODEV; } + static inline int zynqmp_pm_set_pll_frac_data(u32 clk_id, u32 data) { return -ENODEV; } + static inline int zynqmp_pm_get_pll_frac_data(u32 clk_id, u32 *data) { return -ENODEV; } + static inline int zynqmp_pm_set_sd_tapdelay(u32 node_id, u32 type, u32 value) { return -ENODEV; } + static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) { return -ENODEV; } + static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, const enum zynqmp_pm_reset_action assert_flag) { return -ENODEV; } + static inline int zynqmp_pm_reset_get_status(const enum zynqmp_pm_reset reset, u32 *status) { return -ENODEV; } + static inline int zynqmp_pm_init_finalize(void) { return -ENODEV; } + static inline int zynqmp_pm_set_suspend_mode(u32 mode) { return -ENODEV; } + static inline int zynqmp_pm_request_node(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack) { return -ENODEV; } + static inline int zynqmp_pm_release_node(const u32 node) { return -ENODEV; } + static inline int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const u32 qos, @@ -471,39 +496,48 @@ static inline int zynqmp_pm_set_requirement(const u32 node, { return -ENODEV; } + static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) { return -ENODEV; } + static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) { return -ENODEV; } + static inline int zynqmp_pm_fpga_get_status(u32 *value) { return -ENODEV; } + static inline int zynqmp_pm_write_ggs(u32 index, u32 value) { return -ENODEV; } + static inline int zynqmp_pm_read_ggs(u32 index, u32 *value) { return -ENODEV; } + static inline int zynqmp_pm_write_pggs(u32 index, u32 value) { return -ENODEV; } + static inline int zynqmp_pm_read_pggs(u32 index, u32 *value) { return -ENODEV; } + static inline int zynqmp_pm_system_shutdown(const u32 type, const u32 subtype) { return -ENODEV; } + static inline int zynqmp_pm_set_boot_health_status(u32 value) { return -ENODEV; -- cgit v1.2.3 From 311c2520de21cb2f44291ad3d984b42191126628 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 2 Dec 2020 08:38:50 +0100 Subject: firmware: xilinx: Properly align function parameter Fix parameters alignment reported by checkpatch --strict. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/00ed9fcb94a6c22eff1fe8afdea46b2764a8687d.1606894725.git.michal.simek@xilinx.com --- include/linux/firmware/xlnx-zynqmp.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 0e7e72650ed3..edc2977b26d9 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -456,7 +456,7 @@ static inline int zynqmp_pm_sd_dll_reset(u32 node_id, u32 type) } static inline int zynqmp_pm_reset_assert(const enum zynqmp_pm_reset reset, - const enum zynqmp_pm_reset_action assert_flag) + const enum zynqmp_pm_reset_action assert_flag) { return -ENODEV; } @@ -490,9 +490,9 @@ static inline int zynqmp_pm_release_node(const u32 node) } static inline int zynqmp_pm_set_requirement(const u32 node, - const u32 capabilities, - const u32 qos, - const enum zynqmp_pm_request_ack ack) + const u32 capabilities, + const u32 qos, + const enum zynqmp_pm_request_ack ack) { return -ENODEV; } -- cgit v1.2.3 From 1dcdee6ee8f8fdfef5932699129d442d2f1a064d Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 10 Dec 2020 12:51:24 +0100 Subject: soc: mediatek: mmsys: Specify HAS_IOMEM dependency for MTK_MMSYS Because mtk-mmsys uses the 'devm_platform_ioremap_resource' function, it should depend on HAS_IOMEM. Fixes: cc6576029aed ("soc: mediatek: mmsys: Use devm_platform_ioremap_resource()") Reported-by: kernel test robot Signed-off-by: Enric Balletbo i Serra Signed-off-by: Matthias Brugger Link: https://lore.kernel.org/r/20201203121447.3366406-1-enric.balletbo@collabora.com Signed-off-by: Arnd Bergmann --- drivers/soc/mediatek/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 851121d83f14..fdd8bc08569e 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -68,6 +68,7 @@ config MTK_SCPSYS_PM_DOMAINS config MTK_MMSYS bool "MediaTek MMSYS Support" default ARCH_MEDIATEK + depends on HAS_IOMEM help Say yes here to add support for the MediaTek Multimedia Subsystem (MMSYS). -- cgit v1.2.3