From 2cee31cd49733e89dfedf4f68a56839fc2e42040 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:00 +0200 Subject: pinctrl: renesas: r8a7796: Add missing bias for PRESET# pin MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit R-Car Gen3 Hardware Manual Errata for Rev. 0.52 of Nov 30, 2016, added the configuration bit for bias pull-down control for the PRESET# pin on R-Car M3-W. Add driver support for controlling pull-down on this pin. Fixes: 2d40bd24274d2577 ("pinctrl: sh-pfc: r8a7796: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/c479de5b3f235c2f7d5faea9e7e08e6fccb135df.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7796.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index 44e9d2eea484..bbb1b436ded3 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -67,6 +67,7 @@ PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \ PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \ PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \ + PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\ PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \ PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \ PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \ @@ -6218,7 +6219,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ [ 5] = RCAR_GP_PIN(6, 30), /* GP6_30 */ [ 6] = RCAR_GP_PIN(6, 31), /* GP6_31 */ - [ 7] = SH_PFC_PIN_NONE, + [ 7] = PIN_PRESET_N, /* PRESET# */ [ 8] = SH_PFC_PIN_NONE, [ 9] = SH_PFC_PIN_NONE, [10] = SH_PFC_PIN_NONE, -- cgit v1.2.3 From 702a5fa2fe4d7e7f28fed92a170b540acfff9d34 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:01 +0200 Subject: pinctrl: renesas: r8a77990: JTAG pins do not have pull-down capabilities MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hence remove the SH_PFC_PIN_CFG_PULL_DOWN flags from their pin descriptions. Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/da4b2d69955840a506412f1e8099607a0da97ecc.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77990.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index d040eb3e305d..eeebbab4dd81 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -53,10 +53,10 @@ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \ PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \ PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TCK, "TCK", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TDI, "TDI", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \ - PIN_NOGP_CFG(TRST_N, "TRST_N", fn, CFG_FLAGS) + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP) /* * F_() : just information -- cgit v1.2.3 From d82b92410359e57c16455322fa9baf36cb72bc80 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:02 +0200 Subject: pinctrl: renesas: r8a77990: Drop bogus PUEN_ prefixes in comments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The "PUEN_" prefixes are part of the bit names of the PUEN registers, while the comments should refer to the actual pin names. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/9ea85ae8973f6d9b3d10f02f0d9b4ab6a086ec63.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77990.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c index eeebbab4dd81..f44c7da3ec16 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -5197,8 +5197,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = RCAR_GP_PIN(1, 0), /* A0 */ [28] = SH_PFC_PIN_NONE, [29] = SH_PFC_PIN_NONE, - [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */ - [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */ + [30] = RCAR_GP_PIN(2, 25), /* EX_WAIT0 */ + [31] = RCAR_GP_PIN(2, 24), /* RD/WR# */ } }, { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ @@ -5333,8 +5333,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { [27] = SH_PFC_PIN_NONE, [28] = SH_PFC_PIN_NONE, [29] = SH_PFC_PIN_NONE, - [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */ - [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */ + [30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */ + [31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */ } }, { /* sentinel */ }, }; -- cgit v1.2.3 From cf04bbe5ed29cb7b3205bebfd8f4e747359d2cd9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:03 +0200 Subject: pinctrl: renesas: r8a7778: Remove unused PORT_GP_PUP_1() macro MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The last user was removed in commit dd1f760bffcee2c5 ("pinctrl: sh-pfc: r8a7778: Use common PORT_GP_CFG_27() macro"). Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/129147ac57f5e931cc7108db0a6483b803a1b8f4.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7778.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c index 6185af9c4990..d641e408f1bd 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7778.c +++ b/drivers/pinctrl/renesas/pfc-r8a7778.c @@ -18,9 +18,6 @@ #include "sh_pfc.h" -#define PORT_GP_PUP_1(bank, pin, fn, sfx) \ - PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) - #define CPU_ALL_GP(fn, sfx) \ PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ -- cgit v1.2.3 From 904ec4bebc1df908a943bf3178f6c633672ce47b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:04 +0200 Subject: pinctrl: renesas: r8a779{51,6,65}: Reduce non-functional differences MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change whitespace in the pin control drivers for R-Car H3 ES2.0+, R-Car M3-W/M3-W+, and R-Car M3-N, to reduce the differences among these very similar drivers. These changes have no functional impact. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/527b45ebfc664a80e41cb0136677db7260e11437.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77951.c | 4 +- drivers/pinctrl/renesas/pfc-r8a7796.c | 7 +-- drivers/pinctrl/renesas/pfc-r8a77965.c | 79 +++++++++++++++++----------------- 3 files changed, 46 insertions(+), 44 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c index be4eee070842..84c0ea5d59c1 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77951.c +++ b/drivers/pinctrl/renesas/pfc-r8a77951.c @@ -241,7 +241,7 @@ #define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0) #define GPSR6_2 F_(SSI_SDATA0, IP14_31_28) #define GPSR6_1 F_(SSI_WS01239, IP14_27_24) -#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) +#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20) /* GPSR7 */ #define GPSR7_3 FM(GP7_03) @@ -668,7 +668,7 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), - PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), + PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), PINMUX_IPSR_GPSR(IP0_27_24, QPOLB), diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c index bbb1b436ded3..a4d74df3d201 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -1549,7 +1549,7 @@ static const u16 pinmux_data[] = { * core will do the right thing and skip trying to mux the pin * while still applying configuration to it. */ -#define FM(x) PINMUX_DATA(x##_MARK, 0), +#define FM(x) PINMUX_DATA(x##_MARK, 0), PINMUX_STATIC #undef FM }; @@ -4234,7 +4234,7 @@ static const struct { SH_PFC_PIN_GROUP(avb_link), SH_PFC_PIN_GROUP(avb_magic), SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ + SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */ SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_avtp_pps), @@ -5991,7 +5991,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, + unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c index e69210cc6148..a7607a679886 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -666,14 +666,14 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0), PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), - PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), - PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2), + PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0), PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1), PINMUX_IPSR_GPSR(IP0_27_24, IRQ0), @@ -727,16 +727,16 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1), PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), - PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1), + PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), - PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), - PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3), + PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1), + PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1), PINMUX_IPSR_GPSR(IP1_31_28, A0), PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16), @@ -1171,13 +1171,13 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1), PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), - PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1), PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0), - PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), - PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A, I2C_SEL_0_0, SEL_NDF_0), + PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1), PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1), PINMUX_IPSR_GPSR(IP11_27_24, SCK0), @@ -1553,7 +1553,7 @@ static const u16 pinmux_data[] = { * core will do the right thing and skip trying to mux the pin * while still applying configuration to it. */ -#define FM(x) PINMUX_DATA(x##_MARK, 0), +#define FM(x) PINMUX_DATA(x##_MARK, 0), PINMUX_STATIC #undef FM }; @@ -4224,24 +4224,24 @@ static const unsigned int vin4_data18_a_pins[] = { RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), - RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), - RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), - RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), - RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), - RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), - RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), + RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3), + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), + RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), + RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), + RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), + RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), }; static const unsigned int vin4_data18_a_mux[] = { VI4_DATA2_A_MARK, VI4_DATA3_A_MARK, VI4_DATA4_A_MARK, VI4_DATA5_A_MARK, VI4_DATA6_A_MARK, VI4_DATA7_A_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const union vin_data vin4_data_a_pins = { @@ -4294,12 +4294,12 @@ static const unsigned int vin4_data18_b_mux[] = { VI4_DATA2_B_MARK, VI4_DATA3_B_MARK, VI4_DATA4_B_MARK, VI4_DATA5_B_MARK, VI4_DATA6_B_MARK, VI4_DATA7_B_MARK, - VI4_DATA10_MARK, VI4_DATA11_MARK, - VI4_DATA12_MARK, VI4_DATA13_MARK, - VI4_DATA14_MARK, VI4_DATA15_MARK, - VI4_DATA18_MARK, VI4_DATA19_MARK, - VI4_DATA20_MARK, VI4_DATA21_MARK, - VI4_DATA22_MARK, VI4_DATA23_MARK, + VI4_DATA10_MARK, VI4_DATA11_MARK, + VI4_DATA12_MARK, VI4_DATA13_MARK, + VI4_DATA14_MARK, VI4_DATA15_MARK, + VI4_DATA18_MARK, VI4_DATA19_MARK, + VI4_DATA20_MARK, VI4_DATA21_MARK, + VI4_DATA22_MARK, VI4_DATA23_MARK, }; static const union vin_data vin4_data_b_pins = { @@ -6248,7 +6248,8 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { { /* sentinel */ }, }; -static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl) +static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, + unsigned int pin, u32 *pocctrl) { int bit = -EINVAL; -- cgit v1.2.3 From ac5f8197d15cf37d7ae37ff5b6438abe6c8509a6 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Wed, 21 Apr 2021 20:20:41 +0200 Subject: dt-bindings: pinctrl: convert Broadcom Northstar to the json-schema MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Important: this change converts the binding as it is. It includes dependency on undocumented CRU that must be refactored. CRU must get documented and offset property has to be reworked. Above can (and will be) be handled once every CRU MFD subdevice gets documented properly (including the pinmux). Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20210421182041.22636-1-zajec5@gmail.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/brcm,bcm4708-pinmux.txt | 55 ------------- .../bindings/pinctrl/brcm,ns-pinmux.yaml | 94 ++++++++++++++++++++++ 2 files changed, 94 insertions(+), 55 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt deleted file mode 100644 index 8ab2d468dbdb..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt +++ /dev/null @@ -1,55 +0,0 @@ -Broadcom Northstar pins mux controller - -Some of Northstar SoCs's pins can be used for various purposes thanks to the mux -controller. This binding allows describing mux controller and listing available -functions. They can be referenced later by other bindings to let system -configure controller correctly. - -A list of pins varies across chipsets so few bindings are available. - -Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" -noce. - -Required properties: -- compatible: must be one of: - "brcm,bcm4708-pinmux" - "brcm,bcm4709-pinmux" - "brcm,bcm53012-pinmux" -- offset: offset of pin registers in the CRU block - -Functions and their groups available for all chipsets: -- "spi": "spi_grp" -- "i2c": "i2c_grp" -- "pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp" -- "uart1": "uart1_grp" - -Additionally available on BCM4709 and BCM53012: -- "mdio": "mdio_grp" -- "uart2": "uart2_grp" -- "sdio": "sdio_pwr_grp", "sdio_1p8v_grp" - -For documentation of subnodes see: -Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt - -Example: - dmu@1800c000 { - compatible = "simple-bus"; - ranges = <0 0x1800c000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - cru@100 { - compatible = "syscon", "simple-mfd"; - reg = <0x100 0x1a4>; - - pinctrl { - compatible = "brcm,bcm4708-pinmux"; - offset = <0xc0>; - - spi-pins { - function = "spi"; - groups = "spi_grp"; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml new file mode 100644 index 000000000000..470aff599c27 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,ns-pinmux.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,ns-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Northstar pins mux controller + +maintainers: + - Rafał Miłecki + +description: + Some of Northstar SoCs's pins can be used for various purposes thanks to the + mux controller. This binding allows describing mux controller and listing + available functions. They can be referenced later by other bindings to let + system configure controller correctly. + + A list of pins varies across chipsets so few bindings are available. + + Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon" + node. + +properties: + compatible: + enum: + - brcm,bcm4708-pinmux + - brcm,bcm4709-pinmux + - brcm,bcm53012-pinmux + + offset: + description: offset of pin registers in the CRU block + maxItems: 1 + $ref: /schemas/types.yaml#/definitions/uint32-array + +patternProperties: + '-pins$': + type: object + description: pin node + $ref: pinmux-node.yaml# + + properties: + function: + enum: [ spi, i2c, pwm, uart1, mdio, uart2, sdio ] + groups: + minItems: 1 + maxItems: 4 + items: + enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, + uart1_grp, mdio_grp, uart2_grp, sdio_pwr_grp, sdio_1p8v_grp ] + + required: + - function + - groups + + additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + const: brcm,bcm4708-pinmux + then: + patternProperties: + '-pins$': + properties: + function: + enum: [ spi, i2c, pwm, uart1 ] + groups: + items: + enum: [ spi_grp, i2c_grp, pwm0_grp, pwm1_grp, pwm2_grp, pwm3_grp, + uart1_grp ] + +required: + - offset + +additionalProperties: false + +examples: + - | + cru@1800c100 { + compatible = "syscon", "simple-mfd"; + reg = <0x1800c100 0x1a4>; + + pinctrl { + compatible = "brcm,bcm4708-pinmux"; + offset = <0xc0>; + + spi-pins { + function = "spi"; + groups = "spi_grp"; + }; + }; + }; -- cgit v1.2.3 From d62bd5ce12d79bcd6a6c3e4381daa7375dc21158 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Thu, 29 Apr 2021 16:34:24 -0600 Subject: pinctrl: amd: Implement irq_set_wake This allows the OS to control which devices produce wake events. $ grep enabled /sys/kernel/irq/*/wakeup /sys/kernel/irq/24/wakeup:enabled Signed-off-by: Raul E Rangel Link: https://lore.kernel.org/r/20210429163341.1.I7631534622233689dd81410525e0dd617b9b2012@changeid Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 2d4acf21117c..03c0cf15df4a 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -438,6 +438,29 @@ static void amd_gpio_irq_unmask(struct irq_data *d) raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } +static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) +{ + u32 pin_reg; + unsigned long flags; + struct gpio_chip *gc = irq_data_get_irq_chip_data(d); + struct amd_gpio *gpio_dev = gpiochip_get_data(gc); + u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | + BIT(WAKE_CNTRL_OFF_S4); + + raw_spin_lock_irqsave(&gpio_dev->lock, flags); + pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + + if (on) + pin_reg |= wake_mask; + else + pin_reg &= ~wake_mask; + + writel(pin_reg, gpio_dev->base + (d->hwirq)*4); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); + + return 0; +} + static void amd_gpio_irq_eoi(struct irq_data *d) { u32 reg; @@ -552,9 +575,16 @@ static struct irq_chip amd_gpio_irqchip = { .irq_disable = amd_gpio_irq_disable, .irq_mask = amd_gpio_irq_mask, .irq_unmask = amd_gpio_irq_unmask, + .irq_set_wake = amd_gpio_irq_set_wake, .irq_eoi = amd_gpio_irq_eoi, .irq_set_type = amd_gpio_irq_set_type, - .flags = IRQCHIP_SKIP_SET_WAKE, + /* + * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event + * also generates an IRQ. We need the IRQ so the irq_handler can clear + * the wake event. Otherwise the wake event will never clear and + * prevent the system from suspending. + */ + .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, }; #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) -- cgit v1.2.3 From 969ef42b1ae094da99b8acbf14864f94d37f6e58 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Wed, 28 Apr 2021 17:37:51 -0700 Subject: pinctrl: qcom: spmi-mpp: Add compatible for pmi8994 The PMI8994 has 4 multi-purpose-pins, add a compatible for this hardware block to the MPP driver. Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210429003751.224232-1-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt | 1 + drivers/pinctrl/qcom/pinctrl-spmi-mpp.c | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt index 0ba07bc96c55..5363d44cbb74 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-mpp.txt @@ -21,6 +21,7 @@ of PMIC's from Qualcomm. "qcom,pmi8950-mpp", "qcom,pm8994-mpp", "qcom,pma8084-mpp", + "qcom,pmi8994-mpp", And must contain either "qcom,spmi-mpp" or "qcom,ssbi-mpp" if the device is on an spmi bus or an ssbi bus respectively. diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c index 3c213f799feb..2da9b5f68f3f 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c @@ -920,6 +920,7 @@ static const struct of_device_id pmic_mpp_of_match[] = { { .compatible = "qcom,pmi8950-mpp" }, /* 4 MPP's */ { .compatible = "qcom,pm8994-mpp" }, /* 8 MPP's */ { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ + { .compatible = "qcom,pmi8994-mpp" }, /* 4 MPP's */ { .compatible = "qcom,spmi-mpp" }, /* Generic */ { }, }; -- cgit v1.2.3 From d7f444499d6faf9a6ae3b27ec094109528d2b9a7 Mon Sep 17 00:00:00 2001 From: Bixuan Cui Date: Sat, 8 May 2021 11:15:02 +0800 Subject: pinctrl: equilibrium: Add missing MODULE_DEVICE_TABLE This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Reported-by: Hulk Robot Signed-off-by: Bixuan Cui Link: https://lore.kernel.org/r/20210508031502.53637-1-cuibixuan@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-equilibrium.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-equilibrium.c b/drivers/pinctrl/pinctrl-equilibrium.c index a194d8089b6f..38cc20fa9d5a 100644 --- a/drivers/pinctrl/pinctrl-equilibrium.c +++ b/drivers/pinctrl/pinctrl-equilibrium.c @@ -939,6 +939,7 @@ static const struct of_device_id eqbr_pinctrl_dt_match[] = { { .compatible = "intel,lgm-io" }, {} }; +MODULE_DEVICE_TABLE(of, eqbr_pinctrl_dt_match); static struct platform_driver eqbr_pinctrl_driver = { .probe = eqbr_pinctrl_probe, -- cgit v1.2.3 From 57b55eeb755201832c2fc2df58818f64fc023fdb Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 10 May 2021 22:47:17 +0300 Subject: pinctrl: Keep enum pin_config_param ordered by name (part 2) It seems the ordering is by name. Keep it that way. Here updating the entire list (there were two more options not in order). Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210510194717.12255-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- include/linux/pinctrl/pinconf-generic.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index e18ab3d5908f..98ed5959ca9a 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -81,28 +81,28 @@ struct pinctrl_map; * passed in the argument on a custom form, else just use argument 1 * to indicate low power mode, argument 0 turns low power mode off. * @PIN_CONFIG_MODE_PWM: this will configure the pin for PWM + * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a + * value on the line. Use argument 1 to indicate high level, argument 0 to + * indicate low level. (Please see Documentation/driver-api/pinctl.rst, + * section "GPIO mode pitfalls" for a discussion around this parameter.) * @PIN_CONFIG_OUTPUT_ENABLE: this will enable the pin's output mode * without driving a value there. For most platforms this reduces to * enable the output buffers and then let the pin controller current * configuration (eg. the currently selected mux function) drive values on * the line. Use argument 1 to enable output mode, argument 0 to disable * it. - * @PIN_CONFIG_OUTPUT: this will configure the pin as an output and drive a - * value on the line. Use argument 1 to indicate high level, argument 0 to - * indicate low level. (Please see Documentation/driver-api/pinctl.rst, - * section "GPIO mode pitfalls" for a discussion around this parameter.) * @PIN_CONFIG_PERSIST_STATE: retain pin state across sleep or controller reset * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power * supplies, the argument to this parameter (on a custom format) tells * the driver which alternative power source to use. - * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state. - * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to - * this parameter (on a custom format) tells the driver which alternative - * slew rate to use. * @PIN_CONFIG_SKEW_DELAY: if the pin has programmable skew rate (on inputs) * or latch delay (on outputs) this parameter (in a custom format) * specifies the clock skew or latch delay. It typically controls how * many double inverters are put in front of the line. + * @PIN_CONFIG_SLEEP_HARDWARE_STATE: indicate this is sleep related state. + * @PIN_CONFIG_SLEW_RATE: if the pin can select slew rate, the argument to + * this parameter (on a custom format) tells the driver which alternative + * slew rate to use. * @PIN_CONFIG_END: this is the last enumerator for pin configurations, if * you need to pass in custom configurations to the pin controller, use * PIN_CONFIG_END+1 as the base offset. @@ -127,13 +127,13 @@ enum pin_config_param { PIN_CONFIG_INPUT_SCHMITT_ENABLE, PIN_CONFIG_MODE_LOW_POWER, PIN_CONFIG_MODE_PWM, - PIN_CONFIG_OUTPUT_ENABLE, PIN_CONFIG_OUTPUT, + PIN_CONFIG_OUTPUT_ENABLE, PIN_CONFIG_PERSIST_STATE, PIN_CONFIG_POWER_SOURCE, + PIN_CONFIG_SKEW_DELAY, PIN_CONFIG_SLEEP_HARDWARE_STATE, PIN_CONFIG_SLEW_RATE, - PIN_CONFIG_SKEW_DELAY, PIN_CONFIG_END = 0x7F, PIN_CONFIG_MAX = 0xFF, }; -- cgit v1.2.3 From 0f9facdbd9d432442e5655425e8702ed8e28f1b8 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Tue, 11 May 2021 17:09:36 +0800 Subject: pinctrl: ocelot: Remove redundant error printing in ocelot_pinctrl_probe() When devm_ioremap_resource() fails, a clear enough error message will be printed by its subfunction __devm_ioremap_resource(). The error information contains the device name, failure cause, and possibly resource information. Therefore, remove the error printing here to simplify code and reduce the binary size. Reported-by: Hulk Robot Signed-off-by: Zhen Lei Link: https://lore.kernel.org/r/20210511090936.4452-1-thunder.leizhen@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 2fd18e356d0c..e470c16718de 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1362,10 +1362,8 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) base = devm_ioremap_resource(dev, platform_get_resource(pdev, IORESOURCE_MEM, 0)); - if (IS_ERR(base)) { - dev_err(dev, "Failed to ioremap registers\n"); + if (IS_ERR(base)) return PTR_ERR(base); - } info->stride = 1 + (info->desc->npins - 1) / 32; -- cgit v1.2.3 From ef9385fbf30e9484e4291db76e000b8961419782 Mon Sep 17 00:00:00 2001 From: Zhen Lei Date: Tue, 11 May 2021 16:51:26 +0800 Subject: pinctrl: iproc-gpio: Remove redundant error printing in iproc_gpio_probe() When devm_ioremap_resource() fails, a clear enough error message will be printed by its subfunction __devm_ioremap_resource(). The error information contains the device name, failure cause, and possibly resource information. Therefore, remove the error printing here to simplify code and reduce the binary size. Reported-by: Hulk Robot Signed-off-by: Zhen Lei Acked-by: Ray Jui Link: https://lore.kernel.org/r/20210511085126.4287-1-thunder.leizhen@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-iproc-gpio.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index e2bd2dce6bb4..dc511b9a6b43 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -813,10 +813,8 @@ static int iproc_gpio_probe(struct platform_device *pdev) res = platform_get_resource(pdev, IORESOURCE_MEM, 1); if (res) { chip->io_ctrl = devm_ioremap_resource(dev, res); - if (IS_ERR(chip->io_ctrl)) { - dev_err(dev, "unable to map I/O memory\n"); + if (IS_ERR(chip->io_ctrl)) return PTR_ERR(chip->io_ctrl); - } if (of_device_is_compatible(dev->of_node, "brcm,cygnus-ccm-gpio")) io_ctrl_type = IOCTRL_TYPE_CDRU; -- cgit v1.2.3 From 676e2d075040990bdfec7500df7fac6887611ed1 Mon Sep 17 00:00:00 2001 From: satya priya Date: Wed, 12 May 2021 16:43:06 +0530 Subject: pinctrl: qcom: spmi-gpio: Add support for pm7325 Add compatible string for PM7325 pmic GPIO support to the Qualcomm PMIC GPIO driver. Signed-off-by: satya priya Acked-by: Bjorn Andersson Link: https://lore.kernel.org/r/1620817988-18809-2-git-send-email-skakit@codeaurora.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-spmi-gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 00870da0c94e..a89d24a040af 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -1131,6 +1131,7 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 }, { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 }, { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 }, + { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 }, { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 }, { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 }, { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 }, -- cgit v1.2.3 From f9fb145b27cd7700399075c0897e6918a4d5dabe Mon Sep 17 00:00:00 2001 From: satya priya Date: Wed, 12 May 2021 16:43:07 +0530 Subject: dt-bindings: pinctrl: qcom-pmic-gpio: Add pm7325 support Add compatible string for PM7325 pmic GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: satya priya Acked-by: Rob Herring Link: https://lore.kernel.org/r/1620817988-18809-3-git-send-email-skakit@codeaurora.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index f6a9760558a6..161216daf463 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -31,6 +31,7 @@ PMIC's from Qualcomm. "qcom,pm8350b-gpio" "qcom,pm8350c-gpio" "qcom,pmk8350-gpio" + "qcom,pm7325-gpio" "qcom,pmr735a-gpio" "qcom,pmr735b-gpio" "qcom,pm6150-gpio" @@ -120,6 +121,7 @@ to specify in a pin configuration subnode: gpio1-gpio8 for pm8350b gpio1-gpio9 for pm8350c gpio1-gpio4 for pmk8350 + gpio1-gpio10 for pm7325 gpio1-gpio4 for pmr735a gpio1-gpio4 for pmr735b gpio1-gpio10 for pm6150 -- cgit v1.2.3 From 258435a1c8187f559549e515d2f77fa0b57bcd27 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 25 May 2021 11:50:50 +0300 Subject: pinctrl: tigerlake: Add Alder Lake-M ACPI ID Intel Alder Lake-M PCH has the same GPIO hardware than Tiger Lake-LP PCH but the ACPI ID is different. Add this new ACPI ID to the list of supported devices. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 75b6d66955bf..3e4ef2b87526 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -749,6 +749,7 @@ static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { { "INT34C5", (kernel_ulong_t)&tgllp_soc_data }, { "INT34C6", (kernel_ulong_t)&tglh_soc_data }, { "INTC1055", (kernel_ulong_t)&tgllp_soc_data }, + { "INTC1057", (kernel_ulong_t)&tgllp_soc_data }, { } }; MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); -- cgit v1.2.3 From 1ca46d3e43569186bd1decfb02a6b4c4ddb4304b Mon Sep 17 00:00:00 2001 From: Maximilian Luz Date: Wed, 12 May 2021 23:03:16 +0200 Subject: pinctrl/amd: Add device HID for new AMD GPIO controller Add device HID AMDI0031 to the AMD GPIO controller driver match table. This controller can be found on Microsoft Surface Laptop 4 devices and seems similar enough that we can just copy the existing AMDI0030 entry. Cc: # 5.10+ Tested-by: Sachi King Signed-off-by: Maximilian Luz Link: https://lore.kernel.org/r/20210512210316.1982416-1-luzmaximilian@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 03c0cf15df4a..a76be6cc26ee 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -1021,6 +1021,7 @@ static int amd_gpio_remove(struct platform_device *pdev) static const struct acpi_device_id amd_gpio_acpi_match[] = { { "AMD0030", 0 }, { "AMDI0030", 0}, + { "AMDI0031", 0}, { }, }; MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); -- cgit v1.2.3 From 9b882b73d37932a5ba20d7fdcbe6e3191d9582cd Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Thu, 13 May 2021 18:09:47 +0200 Subject: pinctrl: npcm: Align a few entries in the pin function table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The entries for GPIO 33 and 34 are not properly aligned. Fix the alignment. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20210513160947.1716185-1-j.neuschaefer@gmx.net Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 2535ca720668..bb1ea47ec4c6 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -958,8 +958,8 @@ static const struct npcm7xx_pincfg pincfg[] = { NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0), NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0), - NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), - NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), + NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), -- cgit v1.2.3 From f56b273cd845a1139f8e37437367bca314e67b1c Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Wed, 12 May 2021 20:01:40 +0200 Subject: pinctrl: at91: Constify struct at91_pinctrl_mux_ops The at91_pinctrl_mux_ops struct is never modified by the driver. Make it const wherever it is possible to allow the compiler to put the static variables in read-only memory. Note that sam9x60_ops was already const, but the const was cast away when the return value of of_match_device() was cast to a pointer to a non-const struct at91_pinctrl_mux_ops. Signed-off-by: Rikard Falkeborn Link: https://lore.kernel.org/r/20210512180140.33293-1-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c index fc61aaec34cc..72e6df7abe8c 100644 --- a/drivers/pinctrl/pinctrl-at91.c +++ b/drivers/pinctrl/pinctrl-at91.c @@ -42,7 +42,7 @@ struct at91_gpio_chip { int pioc_idx; /* PIO bank index */ void __iomem *regbase; /* PIO bank virtual address */ struct clk *clock; /* associated clock */ - struct at91_pinctrl_mux_ops *ops; /* ops */ + const struct at91_pinctrl_mux_ops *ops; /* ops */ }; static struct at91_gpio_chip *gpio_chips[MAX_GPIO_BANKS]; @@ -210,7 +210,7 @@ struct at91_pinctrl { struct at91_pin_group *groups; int ngroups; - struct at91_pinctrl_mux_ops *ops; + const struct at91_pinctrl_mux_ops *ops; }; static inline const struct at91_pin_group *at91_pinctrl_find_group_by_name( @@ -688,7 +688,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR); } -static struct at91_pinctrl_mux_ops at91rm9200_ops = { +static const struct at91_pinctrl_mux_ops at91rm9200_ops = { .get_periph = at91_mux_get_periph, .mux_A_periph = at91_mux_set_A_periph, .mux_B_periph = at91_mux_set_B_periph, @@ -697,7 +697,7 @@ static struct at91_pinctrl_mux_ops at91rm9200_ops = { .irq_type = gpio_irq_type, }; -static struct at91_pinctrl_mux_ops at91sam9x5_ops = { +static const struct at91_pinctrl_mux_ops at91sam9x5_ops = { .get_periph = at91_mux_pio3_get_periph, .mux_A_periph = at91_mux_pio3_set_A_periph, .mux_B_periph = at91_mux_pio3_set_B_periph, @@ -737,7 +737,7 @@ static const struct at91_pinctrl_mux_ops sam9x60_ops = { .irq_type = alt_gpio_irq_type, }; -static struct at91_pinctrl_mux_ops sama5d3_ops = { +static const struct at91_pinctrl_mux_ops sama5d3_ops = { .get_periph = at91_mux_pio3_get_periph, .mux_A_periph = at91_mux_pio3_set_A_periph, .mux_B_periph = at91_mux_pio3_set_B_periph, @@ -1284,7 +1284,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev, return -ENODEV; info->dev = &pdev->dev; - info->ops = (struct at91_pinctrl_mux_ops *) + info->ops = (const struct at91_pinctrl_mux_ops *) of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; at91_pinctrl_child_count(info, np); @@ -1849,7 +1849,7 @@ static int at91_gpio_probe(struct platform_device *pdev) goto err; } - at91_chip->ops = (struct at91_pinctrl_mux_ops *) + at91_chip->ops = (const struct at91_pinctrl_mux_ops *) of_match_device(at91_gpio_of_match, &pdev->dev)->data; at91_chip->pioc_virq = irq; at91_chip->pioc_idx = alias_idx; -- cgit v1.2.3 From 710071479cf8c6127791427561a6ba4ee916c07f Mon Sep 17 00:00:00 2001 From: Mark Kettenis Date: Thu, 20 May 2021 19:13:06 +0200 Subject: dt-bindings: pinctrl: Add DT bindings for apple, pinctrl The Apple GPIO controller is a simple combined pin and GPIO conroller present on Apple ARM SoC platforms, including various iPhone and iPad devices and the "Apple Silicon" Macs. Signed-off-by: Mark Kettenis Link: https://lore.kernel.org/r/20210520171310.772-2-mark.kettenis@xs4all.nl Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/apple,pinctrl.yaml | 106 +++++++++++++++++++++ MAINTAINERS | 2 + include/dt-bindings/pinctrl/apple.h | 13 +++ 3 files changed, 121 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml create mode 100644 include/dt-bindings/pinctrl/apple.h diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml new file mode 100644 index 000000000000..d50571affd1f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/apple,pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple GPIO controller + +maintainers: + - Mark Kettenis + +description: | + The Apple GPIO controller is a simple combined pin and GPIO + controller present on Apple ARM SoC platforms, including various + iPhone and iPad devices and the "Apple Silicon" Macs. + +properties: + compatible: + items: + - const: apple,t8103-pinctrl + - const: apple,pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + interrupts: + description: One interrupt for each of the (up to 7) interrupt + groups supported by the controller sorted by interrupt group + number in ascending order. + minItems: 1 + maxItems: 7 + + interrupt-controller: true + +patternProperties: + '-pins$': + type: object + $ref: pinmux-node.yaml# + + properties: + pinmux: + description: + Values are constructed from pin number and alternate function + configuration number using the APPLE_PINMUX() helper macro + defined in include/dt-bindings/pinctrl/apple.h. + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl: pinctrl@23c100000 { + compatible = "apple,t8103-pinctrl", "apple,pinctrl"; + reg = <0x2 0x3c100000 0x0 0x100000>; + clocks = <&gpio_clk>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 212>; + + interrupt-controller; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + + pcie_pins: pcie-pins { + pinmux = , + , + ; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index bd7aff0c120f..59e1e03c6096 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1655,9 +1655,11 @@ C: irc://chat.freenode.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml +F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ F: drivers/irqchip/irq-apple-aic.c F: include/dt-bindings/interrupt-controller/apple-aic.h +F: include/dt-bindings/pinctrl/apple.h ARM/ARTPEC MACHINE SUPPORT M: Jesper Nilsson diff --git a/include/dt-bindings/pinctrl/apple.h b/include/dt-bindings/pinctrl/apple.h new file mode 100644 index 000000000000..ea0a6f466592 --- /dev/null +++ b/include/dt-bindings/pinctrl/apple.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ +/* + * This header provides constants for Apple pinctrl bindings. + */ + +#ifndef _DT_BINDINGS_PINCTRL_APPLE_H +#define _DT_BINDINGS_PINCTRL_APPLE_H + +#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16)) +#define APPLE_PIN(pinmux) ((pinmux) & 0xffff) +#define APPLE_FUNC(pinmux) ((pinmux) >> 16) + +#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */ -- cgit v1.2.3 From 8b4c397d88d97d4fd9c3f3527aa66688b1a3387a Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 19 May 2021 18:24:06 +0200 Subject: dt-bindings: pinctrl: mt65xx: add mt8365 SoC binding Add binding documentation for MT8365 Pin controller. Signed-off-by: Fabien Parent Acked-by: Rob Herring Link: https://lore.kernel.org/r/20210519162409.3755679-1-fparent@baylibre.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 + include/dt-bindings/pinctrl/mt8365-pinfunc.h | 858 +++++++++++++++++++++ 2 files changed, 859 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt8365-pinfunc.h diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 360e59c9301a..5fe2c26c28bf 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl. "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. + "mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl. "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to specify pins. diff --git a/include/dt-bindings/pinctrl/mt8365-pinfunc.h b/include/dt-bindings/pinctrl/mt8365-pinfunc.h new file mode 100644 index 000000000000..e2ec8af57dcf --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8365-pinfunc.h @@ -0,0 +1,858 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2021 MediaTek Inc. + */ +#ifndef __MT8365_PINFUNC_H +#define __MT8365_PINFUNC_H + +#include + +#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1) +#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2) +#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) +#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) +#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5) +#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) + +#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1) +#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2) +#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3) +#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) +#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5) +#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) + +#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1) +#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2) +#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3) +#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) +#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5) +#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) + +#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1) +#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2) +#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) +#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5) +#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6) +#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) + +#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1) +#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2) +#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3) +#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) +#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5) +#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6) +#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) + +#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1) +#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2) +#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3) +#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) +#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5) +#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6) +#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) + +#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1) +#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2) +#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) +#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5) +#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6) +#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) + +#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1) +#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3) +#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) +#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5) +#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) + +#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1) +#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2) +#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3) +#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) +#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5) +#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) + +#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1) +#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2) +#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3) +#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) +#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5) +#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) + +#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1) +#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2) +#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3) +#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) +#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5) +#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) + +#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1) +#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2) +#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3) +#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4) +#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5) +#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) + +#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1) +#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2) +#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3) +#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4) +#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5) +#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7) + +#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1) +#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2) +#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3) +#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4) +#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5) +#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7) + +#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1) +#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2) +#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3) +#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4) +#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5) +#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6) +#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7) + +#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1) +#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2) +#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4) +#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5) +#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6) +#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7) + +#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1) +#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2) +#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3) +#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4) +#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5) +#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6) +#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7) + +#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1) +#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2) +#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3) +#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4) +#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5) +#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6) +#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7) + +#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1) +#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2) +#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3) +#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4) +#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5) +#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6) +#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7) + +#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1) +#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2) +#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7) + +#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1) +#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2) +#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7) + +#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1) +#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2) +#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3) +#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4) +#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7) + +#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1) +#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7) + +#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1) +#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2) +#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3) +#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4) +#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5) +#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6) +#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7) + +#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1) +#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7) + +#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1) +#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2) +#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3) +#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4) +#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5) +#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6) +#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7) + +#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1) +#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3) +#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4) +#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5) +#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6) +#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7) + +#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3) +#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4) +#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5) +#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6) +#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7) + +#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1) +#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2) +#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3) +#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4) +#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5) +#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6) +#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7) + +#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1) +#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2) +#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3) +#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4) +#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5) +#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6) +#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7) + +#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1) +#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2) +#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3) +#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5) +#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) + +#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1) +#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2) +#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3) +#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5) +#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6) + +#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1) +#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2) +#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3) +#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4) +#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5) + +#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1) +#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2) +#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3) +#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4) +#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5) + +#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1) +#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2) +#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3) +#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4) +#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) + +#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1) +#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2) +#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7) + +#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1) +#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2) +#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7) + +#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1) +#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2) +#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3) +#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4) +#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5) +#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6) +#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7) + +#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1) +#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2) +#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3) +#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4) +#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5) +#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6) +#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7) + +#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1) +#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2) +#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3) +#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4) +#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5) +#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6) +#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7) + +#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1) +#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2) +#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3) +#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4) +#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5) +#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6) +#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7) + +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1) +#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2) + +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) +#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) + +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1) + +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1) + +#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1) + +#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1) + +#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1) +#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2) + +#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1) + +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2) +#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3) + +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2) +#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3) + +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2) +#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3) + +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2) +#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3) + +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2) +#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3) + +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2) +#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3) + +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2) +#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3) + +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2) +#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3) + +#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1) + +#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1) + +#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1) +#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6) +#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7) + +#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1) +#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6) +#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7) + +#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1) + +#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1) + +#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1) + +#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1) + +#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1) +#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2) +#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7) + +#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1) +#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2) +#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7) + +#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1) +#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2) +#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4) +#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5) +#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7) + +#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1) +#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2) +#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4) +#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5) +#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7) + +#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1) +#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2) +#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3) +#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4) +#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5) +#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7) + +#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1) +#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2) +#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4) +#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5) +#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7) + +#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1) +#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2) +#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7) + +#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1) +#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2) +#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5) +#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7) + +#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1) +#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2) +#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5) +#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7) + +#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1) +#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2) +#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5) +#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7) + +#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1) +#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5) +#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7) + +#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1) +#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5) +#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7) + +#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1) +#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5) +#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7) + +#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1) +#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5) +#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7) + +#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1) +#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5) +#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7) + +#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5) +#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6) + +#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5) +#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6) + +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5) +#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6) + +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5) +#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6) + +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5) +#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6) + +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3) +#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5) + +#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2) +#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3) + +#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6) +#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7) + +#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6) +#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7) + +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6) +#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7) + +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6) +#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7) + +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6) +#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7) + +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2) +#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3) + +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1) +#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2) + +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1) +#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2) + +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1) +#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2) + +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1) +#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2) + +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1) +#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2) + +#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1) +#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2) + +#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1) +#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2) + +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1) +#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2) + +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1) +#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2) + +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1) +#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2) + +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1) +#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2) + +#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1) + +#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1) +#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2) +#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7) + +#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1) +#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2) +#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7) + +#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1) +#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2) +#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7) + +#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1) +#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2) +#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7) + +#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1) +#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2) +#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7) + +#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2) +#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3) +#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4) +#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5) + +#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2) +#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3) +#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4) +#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5) + +#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3) +#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4) +#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5) + +#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2) +#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3) +#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4) +#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5) + +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6) +#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7) + +#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3) +#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4) +#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5) +#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6) +#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7) + +#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3) +#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4) +#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5) +#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6) +#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7) + +#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2) +#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7) + +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2) +#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7) + +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2) +#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7) + +#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2) +#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7) + +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2) +#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7) + +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2) +#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7) + +#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2) +#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7) + +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2) +#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7) + +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2) +#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7) + +#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1) +#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2) + +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1) +#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2) + +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2) +#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3) + +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2) +#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3) + +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2) +#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3) + +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2) +#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3) + +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3) +#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7) + +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1) +#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7) + +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1) +#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7) + +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1) +#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7) + +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1) + +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1) + +#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1) + +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1) + +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1) + +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1) + +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1) + +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1) + +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1) + +#endif /* __MT8365_PINFUNC_H */ -- cgit v1.2.3 From 9f940d8ecf921d2638b05da60eec0d25459be170 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 19 May 2021 18:24:07 +0200 Subject: pinctrl: mediatek: don't hardcode mode encoding in common code MT8365 encode the pins mode differently than other MTK pinctrl drivers that use the PINCTRL_MTK common code. Add 3 new fields in mtk_pinctrl_devdata in order to store how pin modes are encoded into the register. At the same time update all the pinctrl driver that depends on CONFIG_PINCTRL_MTK. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210519162409.3755679-2-fparent@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt2701.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mt2712.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mt6397.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mt8127.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mt8135.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mt8167.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mt8173.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mt8516.c | 3 +++ drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 19 +++++++++---------- drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 3 +++ 10 files changed, 36 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2701.c b/drivers/pinctrl/mediatek/pinctrl-mt2701.c index df8c6fb12955..37228dd5103e 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2701.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2701.c @@ -523,6 +523,9 @@ static const struct mtk_pinctrl_devdata mt2701_pinctrl_data = { .port_shf = 4, .port_mask = 0x1f, .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, .eint_hw = { .port_mask = 6, .ports = 6, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt2712.c b/drivers/pinctrl/mediatek/pinctrl-mt2712.c index 8398d55c01cb..ba35fc6cc138 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt2712.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt2712.c @@ -576,6 +576,9 @@ static const struct mtk_pinctrl_devdata mt2712_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, .eint_hw = { .port_mask = 0xf, .ports = 8, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c index a1914e0e49c7..bc5c3dfcdc76 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6397.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c @@ -33,6 +33,9 @@ static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = { .port_shf = 3, .port_mask = 0x3, .port_align = 2, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, }; static int mt6397_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c index 5f05be056309..eaf5c76b14c7 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8127.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c @@ -292,6 +292,9 @@ static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, .eint_hw = { .port_mask = 7, .ports = 6, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c index 9ac784c48873..b8f4080aab45 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c @@ -305,6 +305,9 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, .eint_hw = { .port_mask = 7, .ports = 6, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c index 7b68886bad16..ba12ef795e52 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8167.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -324,6 +324,9 @@ static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, .eint_hw = { .port_mask = 7, .ports = 6, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c index 75e7c0978337..fc99df8a11c6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c @@ -332,6 +332,9 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, .eint_hw = { .port_mask = 7, .ports = 6, diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c index b375426aa61e..219fb4bc341f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c @@ -324,6 +324,9 @@ static const struct mtk_pinctrl_devdata mt8516_pinctrl_data = { .port_shf = 4, .port_mask = 0xf, .port_align = 4, + .mode_mask = 0xf, + .mode_per_reg = 5, + .mode_shf = 4, .eint_hw = { .port_mask = 7, .ports = 6, diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index a02ad10ec6fa..9fe91e11a877 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -33,7 +33,6 @@ #include "mtk-eint.h" #include "pinctrl-mtk-common.h" -#define MAX_GPIO_MODE_PER_REG 5 #define GPIO_MODE_BITS 3 #define GPIO_MODE_PREFIX "GPIO" @@ -61,7 +60,7 @@ static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl, static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin) { /* Different SoC has different mask and port shift. */ - return ((pin >> 4) & pctl->devdata->port_mask) + return ((pin >> pctl->devdata->mode_shf) & pctl->devdata->port_mask) << pctl->devdata->port_shf; } @@ -74,7 +73,7 @@ static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; - bit = BIT(offset & 0xf); + bit = BIT(offset & pctl->devdata->mode_mask); if (pctl->devdata->spec_dir_set) pctl->devdata->spec_dir_set(®_addr, offset); @@ -96,7 +95,7 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value) struct mtk_pinctrl *pctl = gpiochip_get_data(chip); reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset; - bit = BIT(offset & 0xf); + bit = BIT(offset & pctl->devdata->mode_mask); if (value) reg_addr = SET_ADDR(reg_addr, pctl); @@ -135,7 +134,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, pin, pctl->devdata->port_align, value, arg); } - bit = BIT(pin & 0xf); + bit = BIT(offset & pctl->devdata->mode_mask); if (arg == PIN_CONFIG_INPUT_ENABLE) offset = pctl->devdata->ies_offset; @@ -311,7 +310,7 @@ static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, return -EINVAL; } - bit = BIT(pin & 0xf); + bit = BIT(pin & pctl->devdata->mode_mask); if (enable) reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) + pctl->devdata->pullen_offset, pctl); @@ -683,11 +682,11 @@ static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev, pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin), pin, mode); - reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf) + reg_addr = ((pin / pctl->devdata->mode_per_reg) << pctl->devdata->port_shf) + pctl->devdata->pinmux_offset; mode &= mask; - bit = pin % MAX_GPIO_MODE_PER_REG; + bit = pin % pctl->devdata->mode_per_reg; mask <<= (GPIO_MODE_BITS * bit); val = (mode << (GPIO_MODE_BITS * bit)); return regmap_update_bits(mtk_get_regmap(pctl, pin), @@ -798,7 +797,7 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset) struct mtk_pinctrl *pctl = gpiochip_get_data(chip); reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset; - bit = BIT(offset & 0xf); + bit = BIT(offset & pctl->devdata->mode_mask); if (pctl->devdata->spec_dir_set) pctl->devdata->spec_dir_set(®_addr, offset); @@ -820,7 +819,7 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset) reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->din_offset; - bit = BIT(offset & 0xf); + bit = BIT(offset & pctl->devdata->mode_mask); regmap_read(pctl->regmap1, reg_addr, &read_val); return !!(read_val & bit); } diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h index 69364b56803f..98f27cdc609a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h @@ -254,6 +254,9 @@ struct mtk_pinctrl_devdata { unsigned char port_align; struct mtk_eint_hw eint_hw; struct mtk_eint_regs *eint_regs; + unsigned int mode_mask; + unsigned int mode_per_reg; + unsigned int mode_shf; }; struct mtk_pinctrl { -- cgit v1.2.3 From e94d8b6fb83a81fa8c6595fadcada7b349e7694a Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Wed, 19 May 2021 18:24:08 +0200 Subject: pinctrl: mediatek: add support for mt8365 SoC Add pinctrl driver for MT8365 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210519162409.3755679-3-fparent@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 6 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8365.c | 502 ++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h | 1511 +++++++++++++++++++++++++ 4 files changed, 2020 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8365.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 90f0c8255eaf..b27c2070559a 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -153,6 +153,12 @@ config PINCTRL_MT8195 depends on ARM64 || COMPILE_TEST select PINCTRL_MTK_PARIS +config PINCTRL_MT8365 + bool "Mediatek MT8365 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + config PINCTRL_MT8516 bool "Mediatek MT8516 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 06fde993ace2..1bb7f9c65bc2 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -22,5 +22,6 @@ obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o obj-$(CONFIG_PINCTRL_MT8195) += pinctrl-mt8195.o +obj-$(CONFIG_PINCTRL_MT8365) += pinctrl-mt8365.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8365.c b/drivers/pinctrl/mediatek/pinctrl-mt8365.c new file mode 100644 index 000000000000..22c33c3cb581 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8365.c @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Zhiyong Tao + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8365.h" + +static const struct mtk_drv_group_desc mt8365_drv_grp[] = { + /* 0E4E8SR 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* 0E2E4SR 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2) +}; + +static const struct mtk_pin_drv_grp mt8365_pin_drv[] = { + + MTK_PIN_DRV_GRP(0, 0x710, 0, 2), + MTK_PIN_DRV_GRP(1, 0x710, 0, 2), + MTK_PIN_DRV_GRP(2, 0x710, 0, 2), + MTK_PIN_DRV_GRP(3, 0x710, 0, 2), + MTK_PIN_DRV_GRP(4, 0x710, 4, 2), + MTK_PIN_DRV_GRP(5, 0x710, 4, 2), + MTK_PIN_DRV_GRP(6, 0x710, 4, 2), + MTK_PIN_DRV_GRP(7, 0x710, 4, 2), + MTK_PIN_DRV_GRP(8, 0x710, 8, 2), + MTK_PIN_DRV_GRP(9, 0x710, 8, 2), + MTK_PIN_DRV_GRP(10, 0x710, 8, 2), + MTK_PIN_DRV_GRP(11, 0x710, 8, 2), + MTK_PIN_DRV_GRP(12, 0x710, 12, 2), + MTK_PIN_DRV_GRP(13, 0x710, 12, 2), + MTK_PIN_DRV_GRP(14, 0x710, 12, 2), + MTK_PIN_DRV_GRP(15, 0x710, 12, 2), + MTK_PIN_DRV_GRP(16, 0x710, 16, 2), + MTK_PIN_DRV_GRP(17, 0x710, 16, 2), + MTK_PIN_DRV_GRP(18, 0x710, 16, 2), + MTK_PIN_DRV_GRP(19, 0x710, 20, 2), + MTK_PIN_DRV_GRP(20, 0x710, 24, 2), + MTK_PIN_DRV_GRP(21, 0x710, 24, 2), + MTK_PIN_DRV_GRP(22, 0x710, 28, 2), + MTK_PIN_DRV_GRP(23, 0x720, 0, 2), + MTK_PIN_DRV_GRP(24, 0x720, 0, 2), + MTK_PIN_DRV_GRP(25, 0x720, 0, 2), + MTK_PIN_DRV_GRP(26, 0x720, 4, 2), + MTK_PIN_DRV_GRP(27, 0x720, 4, 2), + MTK_PIN_DRV_GRP(28, 0x720, 4, 2), + MTK_PIN_DRV_GRP(29, 0x720, 4, 2), + MTK_PIN_DRV_GRP(30, 0x720, 8, 2), + MTK_PIN_DRV_GRP(31, 0x720, 8, 2), + MTK_PIN_DRV_GRP(32, 0x720, 8, 2), + MTK_PIN_DRV_GRP(33, 0x720, 8, 2), + MTK_PIN_DRV_GRP(34, 0x720, 8, 2), + MTK_PIN_DRV_GRP(35, 0x720, 12, 2), + MTK_PIN_DRV_GRP(36, 0x720, 12, 2), + MTK_PIN_DRV_GRP(37, 0x720, 12, 2), + MTK_PIN_DRV_GRP(38, 0x720, 12, 2), + MTK_PIN_DRV_GRP(39, 0x720, 12, 2), + MTK_PIN_DRV_GRP(40, 0x720, 12, 2), + MTK_PIN_DRV_GRP(41, 0x720, 16, 2), + MTK_PIN_DRV_GRP(42, 0x720, 16, 2), + MTK_PIN_DRV_GRP(43, 0x720, 16, 2), + MTK_PIN_DRV_GRP(44, 0x720, 16, 2), + MTK_PIN_DRV_GRP(45, 0x720, 20, 2), + MTK_PIN_DRV_GRP(46, 0x720, 20, 2), + MTK_PIN_DRV_GRP(47, 0x720, 20, 2), + MTK_PIN_DRV_GRP(48, 0x720, 20, 2), + MTK_PIN_DRV_GRP(49, 0x720, 24, 2), + MTK_PIN_DRV_GRP(50, 0x720, 24, 2), + MTK_PIN_DRV_GRP(51, 0x720, 24, 2), + MTK_PIN_DRV_GRP(52, 0x720, 24, 2), + MTK_PIN_DRV_GRP(53, 0x720, 24, 2), + MTK_PIN_DRV_GRP(54, 0x720, 24, 2), + MTK_PIN_DRV_GRP(55, 0x720, 24, 2), + MTK_PIN_DRV_GRP(56, 0x720, 24, 2), + MTK_PIN_DRV_GRP(57, 0x720, 28, 2), + MTK_PIN_DRV_GRP(58, 0x720, 28, 2), + MTK_PIN_DRV_GRP(59, 0x730, 0, 2), + MTK_PIN_DRV_GRP(60, 0x730, 0, 2), + MTK_PIN_DRV_GRP(61, 0x730, 4, 2), + MTK_PIN_DRV_GRP(62, 0x730, 4, 2), + MTK_PIN_DRV_GRP(63, 0x730, 8, 2), + MTK_PIN_DRV_GRP(64, 0x730, 8, 2), + MTK_PIN_DRV_GRP(65, 0x730, 12, 2), + MTK_PIN_DRV_GRP(66, 0x730, 12, 2), + MTK_PIN_DRV_GRP(67, 0x730, 12, 2), + MTK_PIN_DRV_GRP(68, 0x730, 12, 2), + MTK_PIN_DRV_GRP(69, 0x730, 12, 2), + MTK_PIN_DRV_GRP(70, 0x730, 12, 2), + MTK_PIN_DRV_GRP(71, 0x730, 16, 2), + MTK_PIN_DRV_GRP(72, 0x730, 16, 2), + MTK_PIN_DRV_GRP(73, 0x730, 16, 2), + MTK_PIN_DRV_GRP(74, 0x730, 16, 2), + MTK_PIN_DRV_GRP(75, 0x730, 16, 2), + MTK_PIN_DRV_GRP(76, 0x730, 16, 2), + MTK_PIN_DRV_GRP(77, 0x730, 16, 2), + MTK_PIN_DRV_GRP(78, 0x730, 16, 2), + MTK_PIN_DRV_GRP(79, 0x730, 16, 2), + MTK_PIN_DRV_GRP(80, 0x730, 20, 2), + MTK_PIN_DRV_GRP(81, 0x730, 24, 2), + MTK_PIN_DRV_GRP(82, 0x730, 28, 2), + MTK_PIN_DRV_GRP(83, 0x730, 28, 2), + MTK_PIN_DRV_GRP(84, 0x730, 28, 2), + MTK_PIN_DRV_GRP(85, 0x730, 28, 2), + MTK_PIN_DRV_GRP(86, 0x740, 12, 2), + MTK_PIN_DRV_GRP(87, 0x740, 16, 2), + MTK_PIN_DRV_GRP(88, 0x740, 20, 2), + MTK_PIN_DRV_GRP(89, 0x740, 24, 2), + MTK_PIN_DRV_GRP(90, 0x740, 24, 2), + MTK_PIN_DRV_GRP(91, 0x740, 24, 2), + MTK_PIN_DRV_GRP(92, 0x740, 24, 2), + MTK_PIN_DRV_GRP(93, 0x750, 8, 2), + MTK_PIN_DRV_GRP(94, 0x750, 8, 2), + MTK_PIN_DRV_GRP(95, 0x750, 8, 2), + MTK_PIN_DRV_GRP(96, 0x750, 8, 2), + MTK_PIN_DRV_GRP(97, 0x750, 24, 2), + MTK_PIN_DRV_GRP(98, 0x750, 28, 2), + MTK_PIN_DRV_GRP(99, 0x760, 0, 2), + MTK_PIN_DRV_GRP(100, 0x750, 8, 2), + MTK_PIN_DRV_GRP(101, 0x750, 8, 2), + MTK_PIN_DRV_GRP(102, 0x750, 8, 2), + MTK_PIN_DRV_GRP(103, 0x750, 8, 2), + MTK_PIN_DRV_GRP(104, 0x760, 20, 2), + MTK_PIN_DRV_GRP(105, 0x760, 24, 2), + MTK_PIN_DRV_GRP(106, 0x760, 24, 2), + MTK_PIN_DRV_GRP(107, 0x760, 24, 2), + MTK_PIN_DRV_GRP(108, 0x760, 24, 2), + MTK_PIN_DRV_GRP(109, 0x760, 24, 2), + MTK_PIN_DRV_GRP(110, 0x760, 28, 2), + MTK_PIN_DRV_GRP(111, 0x760, 28, 2), + MTK_PIN_DRV_GRP(112, 0x760, 28, 2), + MTK_PIN_DRV_GRP(113, 0x760, 28, 2), + MTK_PIN_DRV_GRP(114, 0x770, 0, 2), + MTK_PIN_DRV_GRP(115, 0x770, 0, 2), + MTK_PIN_DRV_GRP(116, 0x770, 0, 2), + MTK_PIN_DRV_GRP(117, 0x770, 4, 2), + MTK_PIN_DRV_GRP(118, 0x770, 4, 2), + MTK_PIN_DRV_GRP(119, 0x770, 4, 2), + MTK_PIN_DRV_GRP(120, 0x770, 8, 2), + MTK_PIN_DRV_GRP(121, 0x770, 8, 2), + MTK_PIN_DRV_GRP(122, 0x770, 8, 2), + MTK_PIN_DRV_GRP(123, 0x770, 12, 2), + MTK_PIN_DRV_GRP(124, 0x770, 12, 2), + MTK_PIN_DRV_GRP(125, 0x770, 12, 2), + MTK_PIN_DRV_GRP(126, 0x770, 16, 2), + MTK_PIN_DRV_GRP(127, 0x770, 16, 2), + MTK_PIN_DRV_GRP(128, 0x770, 16, 2), + MTK_PIN_DRV_GRP(129, 0x770, 20, 2), + MTK_PIN_DRV_GRP(130, 0x770, 20, 2), + MTK_PIN_DRV_GRP(131, 0x770, 20, 2), + MTK_PIN_DRV_GRP(132, 0x770, 20, 2), + MTK_PIN_DRV_GRP(133, 0x770, 20, 2), + MTK_PIN_DRV_GRP(134, 0x770, 20, 2), + MTK_PIN_DRV_GRP(135, 0x770, 20, 2), + MTK_PIN_DRV_GRP(136, 0x770, 24, 2), + MTK_PIN_DRV_GRP(137, 0x770, 24, 2), + MTK_PIN_DRV_GRP(138, 0x770, 24, 2), + MTK_PIN_DRV_GRP(139, 0x770, 24, 2), + MTK_PIN_DRV_GRP(140, 0x770, 24, 2), + MTK_PIN_DRV_GRP(141, 0x770, 24, 2), + MTK_PIN_DRV_GRP(142, 0x770, 24, 2), + MTK_PIN_DRV_GRP(143, 0x770, 24, 2), + MTK_PIN_DRV_GRP(144, 0x770, 24, 2), +}; + +static const struct mtk_pin_spec_pupd_set_samereg mt8365_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(22, 0x070, 0, 2, 1), + MTK_PIN_PUPD_SPEC_SR(23, 0x070, 3, 5, 4), + MTK_PIN_PUPD_SPEC_SR(24, 0x070, 6, 8, 7), + MTK_PIN_PUPD_SPEC_SR(25, 0x070, 9, 11, 10), + MTK_PIN_PUPD_SPEC_SR(80, 0x070, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(81, 0x070, 17, 16, 15), + MTK_PIN_PUPD_SPEC_SR(82, 0x070, 20, 19, 18), + MTK_PIN_PUPD_SPEC_SR(83, 0x070, 23, 22, 21), + MTK_PIN_PUPD_SPEC_SR(84, 0x070, 26, 25, 24), + MTK_PIN_PUPD_SPEC_SR(85, 0x070, 29, 28, 27), + MTK_PIN_PUPD_SPEC_SR(86, 0x080, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(87, 0x080, 5, 4, 3), + MTK_PIN_PUPD_SPEC_SR(88, 0x080, 8, 7, 6), + MTK_PIN_PUPD_SPEC_SR(89, 0x080, 11, 10, 9), + MTK_PIN_PUPD_SPEC_SR(90, 0x080, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(91, 0x080, 17, 16, 15), + MTK_PIN_PUPD_SPEC_SR(92, 0x080, 20, 19, 18), + MTK_PIN_PUPD_SPEC_SR(93, 0x080, 23, 22, 21), + MTK_PIN_PUPD_SPEC_SR(94, 0x080, 26, 25, 24), + MTK_PIN_PUPD_SPEC_SR(95, 0x080, 29, 28, 27), + MTK_PIN_PUPD_SPEC_SR(96, 0x090, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(97, 0x090, 5, 4, 3), + MTK_PIN_PUPD_SPEC_SR(98, 0x090, 8, 7, 6), + MTK_PIN_PUPD_SPEC_SR(99, 0x090, 11, 10, 9), + MTK_PIN_PUPD_SPEC_SR(100, 0x090, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(101, 0x090, 17, 16, 15), + MTK_PIN_PUPD_SPEC_SR(102, 0x090, 20, 19, 18), + MTK_PIN_PUPD_SPEC_SR(103, 0x090, 23, 22, 21), + MTK_PIN_PUPD_SPEC_SR(104, 0x090, 26, 25, 24), + MTK_PIN_PUPD_SPEC_SR(105, 0x090, 29, 28, 27), + MTK_PIN_PUPD_SPEC_SR(106, 0x0F0, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(107, 0x0F0, 5, 4, 3), + MTK_PIN_PUPD_SPEC_SR(108, 0x0F0, 8, 7, 6), + MTK_PIN_PUPD_SPEC_SR(109, 0x0F0, 11, 10, 9), +}; + +static const struct mtk_pin_ies_smt_set mt8365_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 3, 0x410, 0), + MTK_PIN_IES_SMT_SPEC(4, 7, 0x410, 1), + MTK_PIN_IES_SMT_SPEC(8, 11, 0x410, 2), + MTK_PIN_IES_SMT_SPEC(12, 15, 0x410, 3), + MTK_PIN_IES_SMT_SPEC(16, 18, 0x410, 4), + MTK_PIN_IES_SMT_SPEC(19, 19, 0x410, 5), + MTK_PIN_IES_SMT_SPEC(20, 21, 0x410, 6), + MTK_PIN_IES_SMT_SPEC(22, 22, 0x410, 7), + MTK_PIN_IES_SMT_SPEC(23, 25, 0x410, 8), + MTK_PIN_IES_SMT_SPEC(26, 29, 0x410, 9), + MTK_PIN_IES_SMT_SPEC(30, 34, 0x410, 10), + MTK_PIN_IES_SMT_SPEC(35, 40, 0x410, 11), + MTK_PIN_IES_SMT_SPEC(41, 44, 0x410, 12), + MTK_PIN_IES_SMT_SPEC(45, 48, 0x410, 13), + MTK_PIN_IES_SMT_SPEC(49, 56, 0x410, 14), + MTK_PIN_IES_SMT_SPEC(57, 58, 0x410, 15), + MTK_PIN_IES_SMT_SPEC(59, 60, 0x410, 16), + MTK_PIN_IES_SMT_SPEC(61, 62, 0x410, 17), + MTK_PIN_IES_SMT_SPEC(63, 64, 0x410, 18), + MTK_PIN_IES_SMT_SPEC(65, 70, 0x410, 19), + MTK_PIN_IES_SMT_SPEC(71, 79, 0x410, 20), + MTK_PIN_IES_SMT_SPEC(80, 80, 0x410, 21), + MTK_PIN_IES_SMT_SPEC(81, 81, 0x410, 22), + MTK_PIN_IES_SMT_SPEC(82, 82, 0x410, 23), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x410, 24), + MTK_PIN_IES_SMT_SPEC(84, 84, 0x410, 25), + MTK_PIN_IES_SMT_SPEC(85, 85, 0x410, 26), + MTK_PIN_IES_SMT_SPEC(86, 86, 0x410, 27), + MTK_PIN_IES_SMT_SPEC(87, 87, 0x410, 28), + MTK_PIN_IES_SMT_SPEC(88, 88, 0x410, 29), + MTK_PIN_IES_SMT_SPEC(89, 89, 0x410, 30), + MTK_PIN_IES_SMT_SPEC(90, 90, 0x410, 31), + MTK_PIN_IES_SMT_SPEC(91, 91, 0x420, 0), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x420, 1), + MTK_PIN_IES_SMT_SPEC(93, 93, 0x420, 2), + MTK_PIN_IES_SMT_SPEC(94, 94, 0x420, 3), + MTK_PIN_IES_SMT_SPEC(95, 95, 0x420, 4), + MTK_PIN_IES_SMT_SPEC(96, 96, 0x420, 5), + MTK_PIN_IES_SMT_SPEC(97, 97, 0x420, 6), + MTK_PIN_IES_SMT_SPEC(98, 98, 0x420, 7), + MTK_PIN_IES_SMT_SPEC(99, 99, 0x420, 8), + MTK_PIN_IES_SMT_SPEC(100, 100, 0x420, 9), + MTK_PIN_IES_SMT_SPEC(101, 101, 0x420, 10), + MTK_PIN_IES_SMT_SPEC(102, 102, 0x420, 11), + MTK_PIN_IES_SMT_SPEC(103, 103, 0x420, 12), + MTK_PIN_IES_SMT_SPEC(104, 104, 0x420, 13), + MTK_PIN_IES_SMT_SPEC(105, 109, 0x420, 14), + MTK_PIN_IES_SMT_SPEC(110, 113, 0x420, 15), + MTK_PIN_IES_SMT_SPEC(114, 112, 0x420, 16), + MTK_PIN_IES_SMT_SPEC(117, 119, 0x420, 17), + MTK_PIN_IES_SMT_SPEC(120, 122, 0x420, 18), + MTK_PIN_IES_SMT_SPEC(123, 125, 0x420, 19), + MTK_PIN_IES_SMT_SPEC(126, 128, 0x420, 20), + MTK_PIN_IES_SMT_SPEC(129, 135, 0x420, 21), + MTK_PIN_IES_SMT_SPEC(136, 144, 0x420, 22), +}; + +static const struct mtk_pin_ies_smt_set mt8365_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 0, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(1, 1, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(2, 2, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(3, 3, 0x470, 0), + MTK_PIN_IES_SMT_SPEC(4, 4, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(5, 5, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(6, 6, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(7, 7, 0x470, 1), + MTK_PIN_IES_SMT_SPEC(8, 8, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(9, 9, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(10, 10, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(11, 11, 0x470, 2), + MTK_PIN_IES_SMT_SPEC(12, 12, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(13, 13, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(14, 14, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(15, 15, 0x470, 3), + MTK_PIN_IES_SMT_SPEC(16, 16, 0x470, 4), + MTK_PIN_IES_SMT_SPEC(17, 17, 0x470, 4), + MTK_PIN_IES_SMT_SPEC(18, 18, 0x470, 4), + MTK_PIN_IES_SMT_SPEC(19, 19, 0x470, 5), + MTK_PIN_IES_SMT_SPEC(20, 20, 0x470, 6), + MTK_PIN_IES_SMT_SPEC(21, 21, 0x470, 6), + MTK_PIN_IES_SMT_SPEC(22, 22, 0x470, 7), + MTK_PIN_IES_SMT_SPEC(23, 23, 0x470, 8), + MTK_PIN_IES_SMT_SPEC(24, 24, 0x470, 8), + MTK_PIN_IES_SMT_SPEC(25, 25, 0x470, 8), + MTK_PIN_IES_SMT_SPEC(26, 26, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(27, 27, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(28, 28, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(29, 29, 0x470, 9), + MTK_PIN_IES_SMT_SPEC(30, 30, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(31, 31, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(32, 32, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(33, 33, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(34, 34, 0x470, 10), + MTK_PIN_IES_SMT_SPEC(35, 35, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(36, 36, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(37, 37, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(38, 38, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(39, 39, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(40, 40, 0x470, 11), + MTK_PIN_IES_SMT_SPEC(41, 41, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(42, 42, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(43, 43, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(44, 44, 0x470, 12), + MTK_PIN_IES_SMT_SPEC(45, 45, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(46, 46, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(47, 47, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(48, 48, 0x470, 13), + MTK_PIN_IES_SMT_SPEC(49, 49, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(50, 50, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(51, 51, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(52, 52, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(53, 53, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(54, 54, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(55, 55, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(56, 56, 0x470, 14), + MTK_PIN_IES_SMT_SPEC(57, 57, 0x470, 15), + MTK_PIN_IES_SMT_SPEC(58, 58, 0x470, 15), + MTK_PIN_IES_SMT_SPEC(59, 59, 0x470, 16), + MTK_PIN_IES_SMT_SPEC(60, 60, 0x470, 16), + MTK_PIN_IES_SMT_SPEC(61, 61, 0x470, 17), + MTK_PIN_IES_SMT_SPEC(62, 62, 0x470, 17), + MTK_PIN_IES_SMT_SPEC(63, 63, 0x470, 18), + MTK_PIN_IES_SMT_SPEC(64, 64, 0x470, 18), + MTK_PIN_IES_SMT_SPEC(65, 65, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(66, 66, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(67, 67, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(68, 68, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(69, 69, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(70, 70, 0x470, 19), + MTK_PIN_IES_SMT_SPEC(71, 71, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(72, 72, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(73, 73, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(74, 74, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(75, 75, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(76, 76, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(77, 77, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(78, 78, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(79, 79, 0x470, 20), + MTK_PIN_IES_SMT_SPEC(80, 80, 0x470, 21), + MTK_PIN_IES_SMT_SPEC(81, 81, 0x470, 22), + MTK_PIN_IES_SMT_SPEC(82, 82, 0x470, 23), + MTK_PIN_IES_SMT_SPEC(83, 83, 0x470, 24), + MTK_PIN_IES_SMT_SPEC(84, 84, 0x470, 25), + MTK_PIN_IES_SMT_SPEC(85, 85, 0x470, 26), + MTK_PIN_IES_SMT_SPEC(86, 86, 0x470, 27), + MTK_PIN_IES_SMT_SPEC(87, 87, 0x470, 28), + MTK_PIN_IES_SMT_SPEC(88, 88, 0x470, 29), + MTK_PIN_IES_SMT_SPEC(89, 89, 0x470, 30), + MTK_PIN_IES_SMT_SPEC(90, 90, 0x470, 31), + MTK_PIN_IES_SMT_SPEC(91, 91, 0x480, 0), + MTK_PIN_IES_SMT_SPEC(92, 92, 0x480, 1), + MTK_PIN_IES_SMT_SPEC(93, 93, 0x480, 2), + MTK_PIN_IES_SMT_SPEC(94, 94, 0x480, 3), + MTK_PIN_IES_SMT_SPEC(95, 95, 0x480, 4), + MTK_PIN_IES_SMT_SPEC(96, 96, 0x480, 5), + MTK_PIN_IES_SMT_SPEC(97, 97, 0x480, 6), + MTK_PIN_IES_SMT_SPEC(98, 98, 0x480, 7), + MTK_PIN_IES_SMT_SPEC(99, 99, 0x480, 8), + MTK_PIN_IES_SMT_SPEC(100, 100, 0x480, 9), + MTK_PIN_IES_SMT_SPEC(101, 101, 0x480, 10), + MTK_PIN_IES_SMT_SPEC(102, 102, 0x480, 11), + MTK_PIN_IES_SMT_SPEC(103, 103, 0x480, 12), + MTK_PIN_IES_SMT_SPEC(104, 104, 0x480, 13), + MTK_PIN_IES_SMT_SPEC(105, 105, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(106, 106, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(107, 107, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(108, 108, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(109, 109, 0x480, 14), + MTK_PIN_IES_SMT_SPEC(110, 110, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(111, 111, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(112, 112, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(113, 113, 0x480, 15), + MTK_PIN_IES_SMT_SPEC(114, 114, 0x480, 16), + MTK_PIN_IES_SMT_SPEC(115, 115, 0x480, 16), + MTK_PIN_IES_SMT_SPEC(116, 116, 0x480, 16), + MTK_PIN_IES_SMT_SPEC(117, 117, 0x480, 17), + MTK_PIN_IES_SMT_SPEC(118, 118, 0x480, 17), + MTK_PIN_IES_SMT_SPEC(119, 119, 0x480, 17), + MTK_PIN_IES_SMT_SPEC(120, 120, 0x480, 18), + MTK_PIN_IES_SMT_SPEC(121, 121, 0x480, 18), + MTK_PIN_IES_SMT_SPEC(122, 122, 0x480, 18), + MTK_PIN_IES_SMT_SPEC(123, 123, 0x480, 19), + MTK_PIN_IES_SMT_SPEC(124, 124, 0x480, 19), + MTK_PIN_IES_SMT_SPEC(125, 125, 0x480, 19), + MTK_PIN_IES_SMT_SPEC(126, 126, 0x480, 20), + MTK_PIN_IES_SMT_SPEC(127, 127, 0x480, 20), + MTK_PIN_IES_SMT_SPEC(128, 128, 0x480, 20), + MTK_PIN_IES_SMT_SPEC(129, 129, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(130, 130, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(131, 131, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(132, 132, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(133, 133, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(134, 134, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(135, 135, 0x480, 21), + MTK_PIN_IES_SMT_SPEC(136, 136, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(137, 137, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(138, 138, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(139, 139, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(140, 140, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(141, 141, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(142, 142, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(143, 143, 0x480, 22), + MTK_PIN_IES_SMT_SPEC(144, 144, 0x480, 22), +}; + +static int mt8365_spec_pull_set(struct regmap *regmap, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + return mtk_pctrl_spec_pull_set_samereg(regmap, mt8365_spec_pupd, + ARRAY_SIZE(mt8365_spec_pupd), pin, align, isup, r1r0); +} + +static int mt8365_ies_smt_set(struct regmap *regmap, unsigned int pin, + unsigned char align, int value, enum pin_config_param arg) +{ + if (arg == PIN_CONFIG_INPUT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_ies_set, + ARRAY_SIZE(mt8365_ies_set), pin, align, value); + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8365_smt_set, + ARRAY_SIZE(mt8365_smt_set), pin, align, value); + return -EINVAL; +} + +static const struct mtk_pinctrl_devdata mt8365_pinctrl_data = { + .pins = mtk_pins_mt8365, + .npins = ARRAY_SIZE(mtk_pins_mt8365), + .grp_desc = mt8365_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8365_drv_grp), + .pin_drv_grp = mt8365_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8365_pin_drv), + .spec_pull_set = mt8365_spec_pull_set, + .spec_ies_smt_set = mt8365_ies_smt_set, + .dir_offset = 0x0140, + .dout_offset = 0x00A0, + .din_offset = 0x0000, + .pinmux_offset = 0x01E0, + .ies_offset = 0x0410, + .smt_offset = 0x0470, + .pullen_offset = 0x0860, + .pullsel_offset = 0x0900, + .drv_offset = 0x0710, + .type1_start = 145, + .type1_end = 145, + .port_shf = 4, + .port_mask = 0x1f, + .port_align = 4, + .mode_mask = 0x1f, + .mode_per_reg = 10, + .mode_shf = 5, + .eint_hw = { + .port_mask = 7, + .ports = 5, + .ap_num = 160, + .db_cnt = 160, + }, +}; + +static int mtk_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_pctrl_init(pdev, &mt8365_pinctrl_data, NULL); +} + +static const struct of_device_id mt8365_pctrl_match[] = { + { + .compatible = "mediatek,mt8365-pinctrl", + }, + {} +}; + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mtk_pinctrl_probe, + .driver = { + .name = "mediatek-mt8365-pinctrl", + .owner = THIS_MODULE, + .of_match_table = mt8365_pctrl_match, + .pm = &mtk_eint_pm_ops, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} +arch_initcall(mtk_pinctrl_init); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("MediaTek MT8365 Pinctrl Driver"); +MODULE_AUTHOR("Zhiyong Tao "); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h new file mode 100644 index 000000000000..39e17532c460 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8365.h @@ -0,0 +1,1511 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 MediaTek Inc. + * Author: Zhiyong Tao + * + */ + +#ifndef __PINCTRL_MTK_MT8365_H +#define __PINCTRL_MTK_MT8365_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt8365[] = { + MTK_PIN( + PINCTRL_PIN(0, "GPIO0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 0), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "DPI_D0"), + MTK_FUNCTION(2, "PWM_A"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "EXT_TXD0"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + PINCTRL_PIN(1, "GPIO1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 1), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "DPI_D1"), + MTK_FUNCTION(2, "PWM_B"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "EXT_TXD1"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + PINCTRL_PIN(2, "GPIO2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 2), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "DPI_D2"), + MTK_FUNCTION(2, "PWM_C"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "EXT_TXD2"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + PINCTRL_PIN(3, "GPIO3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 3), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "DPI_D3"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "EXT_TXD3"), + MTK_FUNCTION(5, "CONN_MCU_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + PINCTRL_PIN(4, "GPIO4"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 4), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "DPI_D4"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "EXT_TXC"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "VDEC_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + PINCTRL_PIN(5, "GPIO5"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 5), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "DPI_D5"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "EXT_RXER"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "MM_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + PINCTRL_PIN(6, "GPIO6"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 6), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "DPI_D6"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "EXT_RXC"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + PINCTRL_PIN(7, "GPIO7"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 7), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "DPI_D7"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "EXT_RXDV"), + MTK_FUNCTION(5, "CONN_DSP_JCK"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + PINCTRL_PIN(8, "GPIO8"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 8), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "DPI_D8"), + MTK_FUNCTION(2, "SPI_CLK"), + MTK_FUNCTION(3, "I2S0_BCK"), + MTK_FUNCTION(4, "EXT_RXD0"), + MTK_FUNCTION(5, "CONN_DSP_JINTP"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + PINCTRL_PIN(9, "GPIO9"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 9), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "DPI_D9"), + MTK_FUNCTION(2, "SPI_CSB"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "EXT_RXD1"), + MTK_FUNCTION(5, "CONN_DSP_JDI"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + PINCTRL_PIN(10, "GPIO10"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 10), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "DPI_D10"), + MTK_FUNCTION(2, "SPI_MI"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "EXT_RXD2"), + MTK_FUNCTION(5, "CONN_DSP_JMS"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + PINCTRL_PIN(11, "GPIO11"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 11), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "DPI_D11"), + MTK_FUNCTION(2, "SPI_MO"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "EXT_RXD3"), + MTK_FUNCTION(5, "CONN_DSP_JDO"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + PINCTRL_PIN(12, "GPIO12"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 12), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "DPI_DE"), + MTK_FUNCTION(2, "UCTS1"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "EXT_TXEN"), + MTK_FUNCTION(5, "O_WIFI_TXD"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + PINCTRL_PIN(13, "GPIO13"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 13), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "DPI_VSYNC"), + MTK_FUNCTION(2, "URTS1"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "EXT_COL"), + MTK_FUNCTION(5, "SPDIF_IN"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + PINCTRL_PIN(14, "GPIO14"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 14), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "DPI_CK"), + MTK_FUNCTION(2, "UCTS2"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(4, "EXT_MDIO"), + MTK_FUNCTION(5, "SPDIF_OUT"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + PINCTRL_PIN(15, "GPIO15"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 15), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "DPI_HSYNC"), + MTK_FUNCTION(2, "URTS2"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "EXT_MDC"), + MTK_FUNCTION(5, "IRRX"), + MTK_FUNCTION(6, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + PINCTRL_PIN(16, "GPIO16"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 16), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "DPI_D12"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(4, "CLKM0"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "TSF_IN"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + PINCTRL_PIN(17, "GPIO17"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 17), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "DPI_D13"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + PINCTRL_PIN(18, "GPIO18"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 18), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "DPI_D14"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "PWM_C"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "MFG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + PINCTRL_PIN(19, "DISP_PWM"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 19), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_A"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + PINCTRL_PIN(20, "LCM_RST"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 20), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(2, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + PINCTRL_PIN(21, "DSI_TE"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 21), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(2, "PWM_C"), + MTK_FUNCTION(3, "ANT_SEL0"), + MTK_FUNCTION(4, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + PINCTRL_PIN(22, "KPROW0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 22), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + PINCTRL_PIN(23, "KPROW1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 23), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "WIFI_TXD"), + MTK_FUNCTION(4, "CLKM3"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "EXT_FRAME_SYNC"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + PINCTRL_PIN(24, "KPCOL0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 24), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + PINCTRL_PIN(25, "KPCOL1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 25), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "APU_JTAG_TRST"), + MTK_FUNCTION(4, "UDI_NTRST_XI"), + MTK_FUNCTION(5, "DFD_NTRST_XI"), + MTK_FUNCTION(6, "CONN_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + PINCTRL_PIN(26, "SPI_CS"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 26), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "SPI_CSB"), + MTK_FUNCTION(3, "APU_JTAG_TMS"), + MTK_FUNCTION(4, "UDI_TMS_XI"), + MTK_FUNCTION(5, "DFD_TMS_XI"), + MTK_FUNCTION(6, "CONN_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + PINCTRL_PIN(27, "SPI_CK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 27), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "SPI_CLK"), + MTK_FUNCTION(3, "APU_JTAG_TCK"), + MTK_FUNCTION(4, "UDI_TCK_XI"), + MTK_FUNCTION(5, "DFD_TCK_XI"), + MTK_FUNCTION(6, "APU_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + PINCTRL_PIN(28, "SPI_MI"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 28), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "SPI_MI"), + MTK_FUNCTION(2, "SPI_MO"), + MTK_FUNCTION(3, "APU_JTAG_TDI"), + MTK_FUNCTION(4, "UDI_TDI_XI"), + MTK_FUNCTION(5, "DFD_TDI_XI"), + MTK_FUNCTION(6, "DSP_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + PINCTRL_PIN(29, "SPI_MO"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 29), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "SPI_MO"), + MTK_FUNCTION(2, "SPI_MI"), + MTK_FUNCTION(3, "APU_JTAG_TDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "DFD_TDO"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + PINCTRL_PIN(30, "JTMS"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 30), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "DFD_TMS_XI"), + MTK_FUNCTION(3, "UDI_TMS_XI"), + MTK_FUNCTION(4, "MCU_SPM_TMS"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + PINCTRL_PIN(31, "JTCK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 31), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "DFD_TCK_XI"), + MTK_FUNCTION(3, "UDI_TCK_XI"), + MTK_FUNCTION(4, "MCU_SPM_TCK"), + MTK_FUNCTION(5, "CONN_MCU_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_TCKC") + ), + MTK_PIN( + PINCTRL_PIN(32, "JTDI"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 32), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "DFD_TDI_XI"), + MTK_FUNCTION(3, "UDI_TDI_XI"), + MTK_FUNCTION(4, "MCU_SPM_TDI"), + MTK_FUNCTION(5, "CONN_MCU_TDI") + ), + MTK_PIN( + PINCTRL_PIN(33, "JTDO"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 33), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "DFD_TDO"), + MTK_FUNCTION(3, "UDI_TDO"), + MTK_FUNCTION(4, "MCU_SPM_TDO"), + MTK_FUNCTION(5, "CONN_MCU_TDO") + ), + MTK_PIN( + PINCTRL_PIN(34, "JTRST"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 34), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "JTRST"), + MTK_FUNCTION(2, "DFD_NTRST_XI"), + MTK_FUNCTION(3, "UDI_NTRST_XI"), + MTK_FUNCTION(4, "MCU_SPM_NTRST"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B") + ), + MTK_PIN( + PINCTRL_PIN(35, "URXD0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 35), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0"), + MTK_FUNCTION(7, "DSP_URXD0") + ), + MTK_PIN( + PINCTRL_PIN(36, "UTXD0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 36), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0"), + MTK_FUNCTION(7, "DSP_UTXD0") + ), + MTK_PIN( + PINCTRL_PIN(37, "URXD1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 37), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(3, "UCTS2"), + MTK_FUNCTION(4, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(5, "CONN_UART0_RXD"), + MTK_FUNCTION(6, "I2S0_MCK"), + MTK_FUNCTION(7, "DSP_URXD0") + ), + MTK_PIN( + PINCTRL_PIN(38, "UTXD1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 38), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(3, "URTS2"), + MTK_FUNCTION(4, "ANT_SEL2"), + MTK_FUNCTION(5, "CONN_UART0_TXD"), + MTK_FUNCTION(6, "I2S1_MCK"), + MTK_FUNCTION(7, "DSP_UTXD0") + ), + MTK_PIN( + PINCTRL_PIN(39, "URXD2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 39), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "UTXD2"), + MTK_FUNCTION(3, "UCTS1"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "DSP_URXD0") + ), + MTK_PIN( + PINCTRL_PIN(40, "UTXD2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 40), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "URXD2"), + MTK_FUNCTION(3, "URTS1"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "I2S3_MCK"), + MTK_FUNCTION(7, "DSP_UTXD0") + ), + MTK_PIN( + PINCTRL_PIN(41, "PWRAP_SPI0_MI"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 41), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + PINCTRL_PIN(42, "PWRAP_SPI0_MO"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 42), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + PINCTRL_PIN(43, "PWRAP_SPI0_CK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 43), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + PINCTRL_PIN(44, "PWRAP_SPI0_CSN"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 44), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + PINCTRL_PIN(45, "RTC32K_CK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 45), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + PINCTRL_PIN(46, "WATCHDOG"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 46), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + PINCTRL_PIN(47, "SRCLKENA0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 47), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "SRCLKENA0"), + MTK_FUNCTION(2, "SRCLKENA1") + ), + MTK_PIN( + PINCTRL_PIN(48, "SRCLKENA1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 48), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + PINCTRL_PIN(49, "AUD_CLK_MOSI"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 49), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "I2S1_MCK") + ), + MTK_PIN( + PINCTRL_PIN(50, "AUD_SYNC_MOSI"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 50), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(3, "I2S1_BCK") + ), + MTK_PIN( + PINCTRL_PIN(51, "AUD_DAT_MOSI0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 51), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(2, "AUD_DAT_MISO0"), + MTK_FUNCTION(3, "I2S1_LRCK") + ), + MTK_PIN( + PINCTRL_PIN(52, "AUD_DAT_MOSI1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 52), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(2, "AUD_DAT_MISO1"), + MTK_FUNCTION(3, "I2S1_DO") + ), + MTK_PIN( + PINCTRL_PIN(53, "AUD_CLK_MISO"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 53), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "AUD_CLK_MISO"), + MTK_FUNCTION(2, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "I2S2_MCK") + ), + MTK_PIN( + PINCTRL_PIN(54, "AUD_SYNC_MISO"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 54), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "AUD_SYNC_MISO"), + MTK_FUNCTION(2, "AUD_SYNC_MOSI"), + MTK_FUNCTION(3, "I2S2_BCK") + ), + MTK_PIN( + PINCTRL_PIN(55, "AUD_DAT_MISO0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 55), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "I2S2_LRCK") + ), + MTK_PIN( + PINCTRL_PIN(56, "AUD_DAT_MISO1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 56), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "I2S2_DI") + ), + MTK_PIN( + PINCTRL_PIN(57, "SDA0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 57), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "SDA0_0") + ), + MTK_PIN( + PINCTRL_PIN(58, "SCL0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 58), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SCL0_0") + ), + MTK_PIN( + PINCTRL_PIN(59, "SDA1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 59), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SDA1_0"), + MTK_FUNCTION(6, "USB_SDA"), + MTK_FUNCTION(7, "DBG_SDA") + ), + MTK_PIN( + PINCTRL_PIN(60, "SCL1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 60), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SCL1_0"), + MTK_FUNCTION(6, "USB_SCL"), + MTK_FUNCTION(7, "DBG_SCL") + ), + MTK_PIN( + PINCTRL_PIN(61, "SDA2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 61), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "SDA2_0") + ), + MTK_PIN( + PINCTRL_PIN(62, "SCL2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 62), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "SCL2_0") + ), + MTK_PIN( + PINCTRL_PIN(63, "SDA3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 63), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "SDA3_0") + ), + MTK_PIN( + PINCTRL_PIN(64, "SCL3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 64), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "SCL3_0") + ), + MTK_PIN( + PINCTRL_PIN(65, "CMMCLK0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 65), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CMMCLK1"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + PINCTRL_PIN(66, "CMMCLK1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 66), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CMMCLK0"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + PINCTRL_PIN(67, "CMPCLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 67), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(4, "TDM_RX_BCK"), + MTK_FUNCTION(5, "I2S0_BCK"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + PINCTRL_PIN(68, "CMDAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 68), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "ANT_SEL1"), + MTK_FUNCTION(4, "TDM_RX_LRCK"), + MTK_FUNCTION(5, "I2S0_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + PINCTRL_PIN(69, "CMDAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 69), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "ANT_SEL2"), + MTK_FUNCTION(3, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(4, "TDM_RX_MCK"), + MTK_FUNCTION(5, "I2S0_MCK"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + PINCTRL_PIN(70, "CMDAT2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 70), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "CMDAT2"), + MTK_FUNCTION(2, "ANT_SEL3"), + MTK_FUNCTION(4, "TDM_RX_DI"), + MTK_FUNCTION(5, "I2S0_DI"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + PINCTRL_PIN(71, "CMDAT3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 71), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "CMDAT3"), + MTK_FUNCTION(2, "ANT_SEL4"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + PINCTRL_PIN(72, "CMDAT4"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 72), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "CMDAT4"), + MTK_FUNCTION(2, "ANT_SEL5"), + MTK_FUNCTION(5, "I2S3_BCK"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + PINCTRL_PIN(73, "CMDAT5"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 73), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "CMDAT5"), + MTK_FUNCTION(2, "ANT_SEL6"), + MTK_FUNCTION(5, "I2S3_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + PINCTRL_PIN(74, "CMDAT6"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 74), + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "CMDAT6"), + MTK_FUNCTION(2, "ANT_SEL7"), + MTK_FUNCTION(5, "I2S3_MCK"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + PINCTRL_PIN(75, "CMDAT7"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 75), + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "CMDAT7"), + MTK_FUNCTION(5, "I2S3_DO"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + PINCTRL_PIN(76, "CMDAT8"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 76), + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "CMDAT8"), + MTK_FUNCTION(5, "PCM_CLK"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + PINCTRL_PIN(77, "CMDAT9"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 77), + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "CMDAT9"), + MTK_FUNCTION(5, "PCM_SYNC"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + PINCTRL_PIN(78, "CMHSYNC"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 78), + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "CMHSYNC"), + MTK_FUNCTION(5, "PCM_RX"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + PINCTRL_PIN(79, "CMVSYNC"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 79), + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "CMVSYNC"), + MTK_FUNCTION(5, "PCM_TX"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + PINCTRL_PIN(80, "MSDC2_CMD"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 80), + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "TDM_TX_LRCK"), + MTK_FUNCTION(3, "UTXD1"), + MTK_FUNCTION(4, "DPI_D19"), + MTK_FUNCTION(5, "UDI_TMS_XI"), + MTK_FUNCTION(6, "ADSP_JTAG_TMS") + ), + MTK_PIN( + PINCTRL_PIN(81, "MSDC2_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 81), + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "TDM_TX_BCK"), + MTK_FUNCTION(3, "URXD1"), + MTK_FUNCTION(4, "DPI_D20"), + MTK_FUNCTION(5, "UDI_TCK_XI"), + MTK_FUNCTION(6, "ADSP_JTAG_TCK") + ), + MTK_PIN( + PINCTRL_PIN(82, "MSDC2_DAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 82), + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "TDM_TX_DATA0"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "DPI_D21"), + MTK_FUNCTION(5, "UDI_TDI_XI"), + MTK_FUNCTION(6, "ADSP_JTAG_TDI") + ), + MTK_PIN( + PINCTRL_PIN(83, "MSDC2_DAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 83), + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "TDM_TX_DATA1"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "DPI_D22"), + MTK_FUNCTION(5, "UDI_TDO"), + MTK_FUNCTION(6, "ADSP_JTAG_TDO") + ), + MTK_PIN( + PINCTRL_PIN(84, "MSDC2_DAT2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 84), + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "TDM_TX_DATA2"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(4, "DPI_D23"), + MTK_FUNCTION(5, "UDI_NTRST_XI"), + MTK_FUNCTION(6, "ADSP_JTAG_TRST") + ), + MTK_PIN( + PINCTRL_PIN(85, "MSDC2_DAT3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 85), + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "TDM_TX_DATA3"), + MTK_FUNCTION(3, "PWM_B"), + MTK_FUNCTION(5, "EXT_FRAME_SYNC") + ), + MTK_PIN( + PINCTRL_PIN(86, "MSDC2_DSL"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 86), + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MSDC2_DSL"), + MTK_FUNCTION(2, "TDM_TX_MCK"), + MTK_FUNCTION(3, "PWM_C") + ), + MTK_PIN( + PINCTRL_PIN(87, "MSDC1_CMD"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 87), + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "CONN_MCU_AICE_TMSC"), + MTK_FUNCTION(3, "DFD_TMS_XI"), + MTK_FUNCTION(4, "APU_JTAG_TMS"), + MTK_FUNCTION(5, "MCU_SPM_TMS"), + MTK_FUNCTION(6, "CONN_DSP_JMS"), + MTK_FUNCTION(7, "ADSP_JTAG_TMS") + ), + MTK_PIN( + PINCTRL_PIN(88, "MSDC1_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 88), + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(4, "APU_JTAG_TCK"), + MTK_FUNCTION(5, "MCU_SPM_TCK"), + MTK_FUNCTION(6, "CONN_DSP_JCK"), + MTK_FUNCTION(7, "ADSP_JTAG_TCK") + ), + MTK_PIN( + PINCTRL_PIN(89, "MSDC1_DAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 89), + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "PWM_C"), + MTK_FUNCTION(3, "DFD_TDI_XI"), + MTK_FUNCTION(4, "APU_JTAG_TDI"), + MTK_FUNCTION(5, "MCU_SPM_TDI"), + MTK_FUNCTION(6, "CONN_DSP_JDI"), + MTK_FUNCTION(7, "ADSP_JTAG_TDI") + ), + MTK_PIN( + PINCTRL_PIN(90, "MSDC1_DAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 90), + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "SPDIF_IN"), + MTK_FUNCTION(3, "DFD_TDO"), + MTK_FUNCTION(4, "APU_JTAG_TDO"), + MTK_FUNCTION(5, "MCU_SPM_TDO"), + MTK_FUNCTION(6, "CONN_DSP_JDO"), + MTK_FUNCTION(7, "ADSP_JTAG_TDO") + ), + MTK_PIN( + PINCTRL_PIN(91, "MSDC1_DAT2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 91), + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "SPDIF_OUT"), + MTK_FUNCTION(3, "DFD_NTRST_XI"), + MTK_FUNCTION(4, "APU_JTAG_TRST"), + MTK_FUNCTION(5, "MCU_SPM_NTRST"), + MTK_FUNCTION(6, "CONN_DSP_JINTP"), + MTK_FUNCTION(7, "ADSP_JTAG_TRST") + ), + MTK_PIN( + PINCTRL_PIN(92, "MSDC1_DAT3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 92), + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "IRRX"), + MTK_FUNCTION(3, "PWM_A") + ), + MTK_PIN( + PINCTRL_PIN(93, "MSDC0_DAT7"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 93), + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(2, "NLD7") + ), + MTK_PIN( + PINCTRL_PIN(94, "MSDC0_DAT6"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 94), + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(2, "NLD6") + ), + MTK_PIN( + PINCTRL_PIN(95, "MSDC0_DAT5"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 95), + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(2, "NLD4") + ), + MTK_PIN( + PINCTRL_PIN(96, "MSDC0_DAT4"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 96), + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(2, "NLD3") + ), + MTK_PIN( + PINCTRL_PIN(97, "MSDC0_RSTB"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 97), + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(2, "NLD0") + ), + MTK_PIN( + PINCTRL_PIN(98, "MSDC0_CMD"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 98), + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(2, "NALE") + ), + MTK_PIN( + PINCTRL_PIN(99, "MSDC0_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 99), + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(2, "NWEB") + ), + MTK_PIN( + PINCTRL_PIN(100, "MSDC0_DAT3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 100), + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(2, "NLD1") + ), + MTK_PIN( + PINCTRL_PIN(101, "MSDC0_DAT2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 101), + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(2, "NLD5") + ), + MTK_PIN( + PINCTRL_PIN(102, "MSDC0_DAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 102), + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(2, "NDQS") + ), + MTK_PIN( + PINCTRL_PIN(103, "MSDC0_DAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 103), + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(2, "NLD2") + ), + MTK_PIN( + PINCTRL_PIN(104, "MSDC0_DSL"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 104), + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "MSDC0_DSL") + ), + MTK_PIN( + PINCTRL_PIN(105, "NCLE"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 105), + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "NCLE"), + MTK_FUNCTION(2, "TDM_RX_MCK"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + PINCTRL_PIN(106, "NCEB1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 106), + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "NCEB1"), + MTK_FUNCTION(2, "TDM_RX_BCK"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + PINCTRL_PIN(107, "NCEB0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 107), + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "NCEB0"), + MTK_FUNCTION(2, "TDM_RX_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + PINCTRL_PIN(108, "NREB"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 108), + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "NREB"), + MTK_FUNCTION(2, "TDM_RX_DI"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + PINCTRL_PIN(109, "NRNB"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 109), + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "NRNB"), + MTK_FUNCTION(2, "TSF_IN"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + PINCTRL_PIN(110, "PCM_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 110), + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "PCM_CLK"), + MTK_FUNCTION(2, "I2S0_BCK"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "SPDIF_IN"), + MTK_FUNCTION(5, "DPI_D15") + ), + MTK_PIN( + PINCTRL_PIN(111, "PCM_SYNC"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 111), + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "PCM_SYNC"), + MTK_FUNCTION(2, "I2S0_LRCK"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "SPDIF_OUT"), + MTK_FUNCTION(5, "DPI_D16") + ), + MTK_PIN( + PINCTRL_PIN(112, "PCM_RX"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 112), + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "PCM_RX"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S3_MCK"), + MTK_FUNCTION(4, "IRRX"), + MTK_FUNCTION(5, "DPI_D17") + ), + MTK_PIN( + PINCTRL_PIN(113, "PCM_TX"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 113), + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "PCM_TX"), + MTK_FUNCTION(2, "I2S0_MCK"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "PWM_B"), + MTK_FUNCTION(5, "DPI_D18") + ), + MTK_PIN( + PINCTRL_PIN(114, "I2S_DATA_IN"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 114), + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(6, "SPDIF_IN"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + PINCTRL_PIN(115, "I2S_LRCK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 115), + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(6, "SPDIF_OUT"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + PINCTRL_PIN(116, "I2S_BCK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 116), + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "PWM_C"), + MTK_FUNCTION(6, "IRRX"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + PINCTRL_PIN(117, "DMIC0_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 117), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "DMIC0_CLK"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + PINCTRL_PIN(118, "DMIC0_DAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 118), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "DMIC0_DAT0"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + PINCTRL_PIN(119, "DMIC0_DAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 119), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "DMIC0_DAT1"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + PINCTRL_PIN(120, "DMIC1_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 120), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "DMIC1_CLK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + PINCTRL_PIN(121, "DMIC1_DAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 121), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "DMIC1_DAT0"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + PINCTRL_PIN(122, "DMIC1_DAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 122), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "DMIC1_DAT1"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + PINCTRL_PIN(123, "DMIC2_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 123), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "DMIC2_CLK"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + PINCTRL_PIN(124, "DMIC2_DAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 124), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "DMIC2_DAT0"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + PINCTRL_PIN(125, "DMIC2_DAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 125), + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "DMIC2_DAT1"), + MTK_FUNCTION(2, "TDM_RX_BCK"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + PINCTRL_PIN(126, "DMIC3_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 126), + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "DMIC3_CLK"), + MTK_FUNCTION(2, "TDM_RX_LRCK") + ), + MTK_PIN( + PINCTRL_PIN(127, "DMIC3_DAT0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 127), + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "DMIC3_DAT0"), + MTK_FUNCTION(2, "TDM_RX_DI") + ), + MTK_PIN( + PINCTRL_PIN(128, "DMIC3_DAT1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 128), + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "DMIC3_DAT1"), + MTK_FUNCTION(2, "TDM_RX_MCK"), + MTK_FUNCTION(3, "VAD_CLK") + ), + MTK_PIN( + PINCTRL_PIN(129, "TDM_TX_BCK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 129), + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "TDM_TX_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(3, "ckmon1_ck") + ), + MTK_PIN( + PINCTRL_PIN(130, "TDM_TX_LRCK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 130), + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "TDM_TX_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(3, "ckmon2_ck") + ), + MTK_PIN( + PINCTRL_PIN(131, "TDM_TX_MCK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 131), + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "TDM_TX_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(3, "ckmon3_ck") + ), + MTK_PIN( + PINCTRL_PIN(132, "TDM_TX_DATA0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 132), + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "TDM_TX_DATA0"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "ckmon4_ck"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + PINCTRL_PIN(133, "TDM_TX_DATA1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 133), + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "TDM_TX_DATA1"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + PINCTRL_PIN(134, "TDM_TX_DATA2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 134), + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "TDM_TX_DATA2"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + PINCTRL_PIN(135, "TDM_TX_DATA3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 135), + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "TDM_TX_DATA3"), + MTK_FUNCTION(7, "DBG_MON_B32") + ), + MTK_PIN( + PINCTRL_PIN(136, "CONN_TOP_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 136), + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "CONN_TOP_CLK") + ), + MTK_PIN( + PINCTRL_PIN(137, "CONN_TOP_DATA"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 137), + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "CONN_TOP_DATA") + ), + MTK_PIN( + PINCTRL_PIN(138, "CONN_HRST_B"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 138), + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "CONN_HRST_B") + ), + MTK_PIN( + PINCTRL_PIN(139, "CONN_WB_PTA"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 139), + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "CONN_WB_PTA") + ), + MTK_PIN( + PINCTRL_PIN(140, "CONN_BT_CLK"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 140), + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "CONN_BT_CLK") + ), + MTK_PIN( + PINCTRL_PIN(141, "CONN_BT_DATA"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 141), + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "CONN_BT_DATA") + ), + MTK_PIN( + PINCTRL_PIN(142, "CONN_WF_CTRL0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 142), + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "CONN_WF_CTRL0") + ), + MTK_PIN( + PINCTRL_PIN(143, "CONN_WF_CTRL1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 143), + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "CONN_WF_CTRL1") + ), + MTK_PIN( + PINCTRL_PIN(144, "CONN_WF_CTRL2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 144), + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "CONN_WF_CTRL2") + ), + MTK_PIN( + PINCTRL_PIN(145, "TESTMODE"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 145), + MTK_FUNCTION(0, "GPIO145") + ), + MTK_PIN( + PINCTRL_PIN(146, "SYSRSTB"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 146), + MTK_FUNCTION(0, "GPIO146") + ), + MTK_PIN( + PINCTRL_PIN(147, "BIAS_MSDC0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 147), + MTK_FUNCTION(0, "GPIO147") + ), + MTK_PIN( + PINCTRL_PIN(148, "BIAS_IO0"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 148), + MTK_FUNCTION(0, "GPIO148") + ), + MTK_PIN( + PINCTRL_PIN(149, "BIAS1_IO1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 149), + MTK_FUNCTION(0, "GPIO149") + ), + MTK_PIN( + PINCTRL_PIN(150, "BIAS2_IO1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 150), + MTK_FUNCTION(0, "GPIO150") + ), + MTK_PIN( + PINCTRL_PIN(151, "BIAS_DPI"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 151), + MTK_FUNCTION(0, "GPIO151") + ), + MTK_PIN( + PINCTRL_PIN(152, "BIAS_MSDC2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 152), + MTK_FUNCTION(0, "GPIO152") + ), + MTK_PIN( + PINCTRL_PIN(153, "BIAS_IO2"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 153), + MTK_FUNCTION(0, "GPIO153") + ), + MTK_PIN( + PINCTRL_PIN(154, "BIAS_IO3"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 154), + MTK_FUNCTION(0, "GPIO154") + ), + MTK_PIN( + PINCTRL_PIN(155, "BIAS1_MSDC1"), + NULL, "mt8365", + MTK_EINT_FUNCTION(0, 155), + MTK_FUNCTION(0, "GPIO155") + ), +}; + +#endif /* __PINCTRL_MTK_MT8365_H */ -- cgit v1.2.3 From 89be5957e7ec300cae7af4059db69a0e1f45662d Mon Sep 17 00:00:00 2001 From: Steven Lee Date: Tue, 25 May 2021 13:53:05 +0800 Subject: dt-bindings: pinctrl: Update enum for adding SGPM2 and SGPS2 AST2600 has 2 SGPIO master interfaces one with 128 pins and another one has 80 pins. It also supports 2 SGPIO slave interfaces. In the current bindings, there are only SGPM1 and SGPS1 defined in enum, SGPM2 and SGPS2 should also be added in the bindings. Signed-off-by: Steven Lee Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210525055308.31069-2-steven_lee@aspeedtech.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml index ad91c0bc54da..ad2866c99738 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -46,8 +46,8 @@ patternProperties: PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, - SALT9, SD1, SD2, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, - SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, + SALT9, SD1, SD2, SGPM1, SGPM2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12, @@ -74,9 +74,9 @@ patternProperties: RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1, SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1, SALT2, SALT3, SALT4, SALT5, SALT6, - SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPS1, SIOONCTRL, - SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, - SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, + SALT7, SALT8, SALT9G0, SALT9G1, SD1, SD2, SD3, SGPM1, SGPM2, SGPS1, SGPS2, + SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, + SPI1ABR, SPI1CS1, SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, -- cgit v1.2.3 From 0b9714845935aeab6dfcfbbb796f484aa33058f9 Mon Sep 17 00:00:00 2001 From: Steven Lee Date: Tue, 25 May 2021 13:53:07 +0800 Subject: pinctrl: pinctrl-aspeed-g6: Add sgpio pinctrl settings AST2600 supports 2 SGPIO master interfaces and 2 SGPIO slave interfaces. Current pinctrl driver only define the first sgpio master and slave interfaces. The second SGPIO master and slave interfaces should be added in pinctrl driver as well. Signed-off-by: Steven Lee Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20210525055308.31069-4-steven_lee@aspeedtech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 24 ++++++++++++++++++++---- drivers/pinctrl/aspeed/pinmux-aspeed.h | 9 +++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 5c1a109842a7..36688793b3a0 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -46,8 +46,10 @@ #define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ #define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ #define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ +#define SCU690 0x690 /* Multi-function Pin Control #24 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ #define SCU69C 0x69C /* Multi-function Pin Control #27 */ +#define SCU6D0 0x6D0 /* Multi-function Pin Control #29 */ #define SCUC20 0xC20 /* PCIE configuration Setting Control */ #define ASPEED_G6_NR_PINS 256 @@ -81,13 +83,17 @@ FUNC_GROUP_DECL(I2C12, L26, K24); #define K26 4 SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4)); SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4)); -PIN_DECL_2(K26, GPIOA4, MACLINK1, SCL13); +SIG_EXPR_LIST_DECL_SESG(K26, SGPS2CK, SGPS2, SIG_DESC_SET(SCU690, 4)); +SIG_EXPR_LIST_DECL_SESG(K26, SGPM2CLK, SGPM2, SIG_DESC_SET(SCU6D0, 4)); +PIN_DECL_4(K26, GPIOA4, MACLINK1, SCL13, SGPS2CK, SGPM2CLK); FUNC_GROUP_DECL(MACLINK1, K26); #define L24 5 SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5)); SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5)); -PIN_DECL_2(L24, GPIOA5, MACLINK2, SDA13); +SIG_EXPR_LIST_DECL_SESG(L24, SGPS2LD, SGPS2, SIG_DESC_SET(SCU690, 5)); +SIG_EXPR_LIST_DECL_SESG(L24, SGPM2LD, SGPM2, SIG_DESC_SET(SCU6D0, 5)); +PIN_DECL_4(L24, GPIOA5, MACLINK2, SDA13, SGPS2LD, SGPM2LD); FUNC_GROUP_DECL(MACLINK2, L24); FUNC_GROUP_DECL(I2C13, K26, L24); @@ -95,16 +101,22 @@ FUNC_GROUP_DECL(I2C13, K26, L24); #define L23 6 SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6)); SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6)); -PIN_DECL_2(L23, GPIOA6, MACLINK3, SCL14); +SIG_EXPR_LIST_DECL_SESG(L23, SGPS2O, SGPS2, SIG_DESC_SET(SCU690, 6)); +SIG_EXPR_LIST_DECL_SESG(L23, SGPM2O, SGPM2, SIG_DESC_SET(SCU6D0, 6)); +PIN_DECL_4(L23, GPIOA6, MACLINK3, SCL14, SGPS2O, SGPM2O); FUNC_GROUP_DECL(MACLINK3, L23); #define K25 7 SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7)); -PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); +SIG_EXPR_LIST_DECL_SESG(K25, SGPS2I, SGPS2, SIG_DESC_SET(SCU690, 7)); +SIG_EXPR_LIST_DECL_SESG(K25, SGPM2I, SGPM2, SIG_DESC_SET(SCU6D0, 7)); +PIN_DECL_4(K25, GPIOA7, MACLINK4, SDA14, SGPS2I, SGPM2I); FUNC_GROUP_DECL(MACLINK4, K25); FUNC_GROUP_DECL(I2C14, L23, K25); +FUNC_GROUP_DECL(SGPM2, K26, L24, L23, K25); +FUNC_GROUP_DECL(SGPS2, K26, L24, L23, K25); #define J26 8 SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8)); @@ -2060,7 +2072,9 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(EMMCG4), ASPEED_PINCTRL_GROUP(EMMCG8), ASPEED_PINCTRL_GROUP(SGPM1), + ASPEED_PINCTRL_GROUP(SGPM2), ASPEED_PINCTRL_GROUP(SGPS1), + ASPEED_PINCTRL_GROUP(SGPS2), ASPEED_PINCTRL_GROUP(SIOONCTRL), ASPEED_PINCTRL_GROUP(SIOPBI), ASPEED_PINCTRL_GROUP(SIOPBO), @@ -2276,7 +2290,9 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(SD1), ASPEED_PINCTRL_FUNC(SD2), ASPEED_PINCTRL_FUNC(SGPM1), + ASPEED_PINCTRL_FUNC(SGPM2), ASPEED_PINCTRL_FUNC(SGPS1), + ASPEED_PINCTRL_FUNC(SGPS2), ASPEED_PINCTRL_FUNC(SIOONCTRL), ASPEED_PINCTRL_FUNC(SIOPBI), ASPEED_PINCTRL_FUNC(SIOPBO), diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index dba5875ff276..b69ba6b360a2 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -730,6 +730,15 @@ struct aspeed_pin_desc { SIG_EXPR_LIST_PTR(pin, low), \ SIG_EXPR_LIST_PTR(pin, other)) +#define PIN_DECL_4(pin, other, prio1, prio2, prio3, prio4) \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, \ + SIG_EXPR_LIST_PTR(pin, prio1), \ + SIG_EXPR_LIST_PTR(pin, prio2), \ + SIG_EXPR_LIST_PTR(pin, prio3), \ + SIG_EXPR_LIST_PTR(pin, prio4), \ + SIG_EXPR_LIST_PTR(pin, other)) + #define GROUP_SYM(group) group_pins_ ## group #define GROUP_DECL(group, ...) \ static const int GROUP_SYM(group)[] = { __VA_ARGS__ } -- cgit v1.2.3 From b9045af9fb26f2d81acb32a6d6f5bbfe6fb6c670 Mon Sep 17 00:00:00 2001 From: Yang Li Date: Wed, 26 May 2021 11:07:44 +0800 Subject: pinctrl: Fix kernel-doc Fix function name in pinctrl-single.c kernel-doc comment to remove a warning found by clang_w1. drivers/pinctrl/pinctrl-single.c:1523: warning: expecting prototype for pcs_irq_handle(). Prototype was for pcs_irq_chain_handler() instead. Reported-by: Abaci Robot Signed-off-by: Yang Li Link: https://lore.kernel.org/r/1621998464-10918-1-git-send-email-yang.lee@linux.alibaba.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 2c9c9835f375..7834d5d23224 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1513,7 +1513,7 @@ static irqreturn_t pcs_irq_handler(int irq, void *d) } /** - * pcs_irq_handle() - handler for the dedicated chained interrupt case + * pcs_irq_chain_handler() - handler for the dedicated chained interrupt case * @desc: interrupt descriptor * * Use this if you have a separate interrupt for each -- cgit v1.2.3 From 4bc80da53317edd1c31c183203aa7d8809c42667 Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Fri, 21 May 2021 12:01:58 +0300 Subject: pinctrl: bcm2835: Accept fewer than expected IRQs The downstream .dts files only request two GPIO IRQs. Truncate the array of parent IRQs when irq_of_parse_and_map returns 0. Signed-off-by: Phil Elwell Signed-off-by: Ivan T. Ivanov Reviewed-by: Florian Fainelli Link: https://lore.kernel.org/r/20210521090158.26932-1-iivanov@suse.de Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 1d21129f7751..2c87af1180c4 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1274,9 +1274,13 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) char *name; girq->parents[i] = irq_of_parse_and_map(np, i); - if (!is_7211) + if (!is_7211) { + if (!girq->parents[i]) { + girq->num_parents = i; + break; + } continue; - + } /* Skip over the all banks interrupts */ pc->wake_irq[i] = irq_of_parse_and_map(np, i + BCM2835_NUM_IRQS + 1); -- cgit v1.2.3 From 07d5136f9bf1fa6abe70a1f88b04c1216fbf87a2 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 27 May 2021 22:13:09 +0200 Subject: docs/pinctrl: fix the reference to the u300 platform With commit ce1380c9f4bc ("ARM: remove u300 platform") it is wrong to use arch/arm/mach-u300/Kconfig file as example. Since the u300 platform has been replaced by the u8500, let's use its Kconfig as example. Signed-off-by: Dario Binacchi Link: https://lore.kernel.org/r/20210527201309.13308-1-dariobin@libero.it Signed-off-by: Linus Walleij --- Documentation/driver-api/pin-control.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index e2474425fb0c..71eefe5a023f 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -95,7 +95,7 @@ this in our driver:: To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and selected drivers, you need to select them from your machine's Kconfig entry, since these are so tightly integrated with the machines they are used on. -See for example arch/arm/mach-u300/Kconfig for an example. +See for example arch/arm/mach-ux500/Kconfig for an example. Pins usually have fancier names than this. You can find these in the datasheet for your chip. Notice that the core pinctrl.h file provides a fancy macro -- cgit v1.2.3 From 696beef77521d3e418a2780859d1522c3c39d9b5 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 28 May 2021 11:13:11 +0200 Subject: pinctrl: mediatek: move bit assignment The bit needs offset to be defined which happens some lines below. Looks like a bug. The kernel test robot complains: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:137:12: warning: variable 'offset' is uninitialized when used here [-Wuninitialized] bit = BIT(offset & pctl->devdata->mode_mask); ^~~~~~ Fix it up by reverting to what was done before. Cc: Fabien Parent Cc: Sean Wang Cc: Matthias Brugger Cc: Mattijs Korpershoek Cc: linux-mediatek@lists.infradead.org Fixes: 9f940d8ecf92 ("pinctrl: mediatek: don't hardcode mode encoding in common code") Reported-by: kernel test robot Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 9fe91e11a877..525b1aa7f7a6 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -134,7 +134,7 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, pin, pctl->devdata->port_align, value, arg); } - bit = BIT(offset & pctl->devdata->mode_mask); + bit = BIT(pin & 0xf); if (arg == PIN_CONFIG_INPUT_ENABLE) offset = pctl->devdata->ies_offset; -- cgit v1.2.3 From fd6850132f61d6a784905f1c35a41b726e639c7b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:05 +0200 Subject: pinctrl: renesas: r8a77470: Add bias pinconf support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for the RZ/G1C SoC, using the common R-Car bias handling. Note that on RZ/G1C, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/18c8ebf9fa9e239253a723857e9dffeec775db7e.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77470.c | 346 +++++++++++++++++++++++++++++---- 1 file changed, 306 insertions(+), 40 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c index b3b116da1bb0..e6e5487691c1 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77470.c +++ b/drivers/pinctrl/renesas/pfc-r8a77470.c @@ -11,46 +11,56 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_4(0, fn, sfx), \ - PORT_GP_1(0, 4, fn, sfx), \ - PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(0, 11, fn, sfx), \ - PORT_GP_1(0, 12, fn, sfx), \ - PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_23(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_17(3, fn, sfx), \ - PORT_GP_1(3, 27, fn, sfx), \ - PORT_GP_1(3, 28, fn, sfx), \ - PORT_GP_1(3, 29, fn, sfx), \ - PORT_GP_14(4, fn, sfx), \ - PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(4, 20, fn, sfx), \ - PORT_GP_1(4, 21, fn, sfx), \ - PORT_GP_1(4, 22, fn, sfx), \ - PORT_GP_1(4, 23, fn, sfx), \ - PORT_GP_1(4, 24, fn, sfx), \ - PORT_GP_1(4, 25, fn, sfx), \ - PORT_GP_32(5, fn, sfx) + PORT_GP_CFG_4(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(3, 27, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(3, 28, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(3, 29, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_14(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(4, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(NMI, "NMI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -1121,8 +1131,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AVB -------------------------------------------------------------------- */ @@ -3420,8 +3439,254 @@ static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, return bit; } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + /* PUPR0 pull-up pins */ + [ 0] = RCAR_GP_PIN(1, 0), /* D0 */ + [ 1] = RCAR_GP_PIN(0, 22), /* MMC0_D7 */ + [ 2] = RCAR_GP_PIN(0, 21), /* MMC0_D6 */ + [ 3] = RCAR_GP_PIN(0, 20), /* MMC0_D5 */ + [ 4] = RCAR_GP_PIN(0, 19), /* MMC0_D4 */ + [ 5] = RCAR_GP_PIN(0, 18), /* MMC0_D3 */ + [ 6] = RCAR_GP_PIN(0, 17), /* MMC0_D2 */ + [ 7] = RCAR_GP_PIN(0, 16), /* MMC0_D1 */ + [ 8] = RCAR_GP_PIN(0, 15), /* MMC0_D0 */ + [ 9] = RCAR_GP_PIN(0, 14), /* MMC0_CMD */ + [10] = RCAR_GP_PIN(0, 13), /* MMC0_CLK */ + [11] = RCAR_GP_PIN(0, 12), /* SD0_WP */ + [12] = RCAR_GP_PIN(0, 11), /* SD0_CD */ + [13] = RCAR_GP_PIN(0, 10), /* SD0_DAT3 */ + [14] = RCAR_GP_PIN(0, 9), /* SD0_DAT2 */ + [15] = RCAR_GP_PIN(0, 8), /* SD0_DAT1 */ + [16] = RCAR_GP_PIN(0, 7), /* SD0_DAT0 */ + [17] = RCAR_GP_PIN(0, 6), /* SD0_CMD */ + [18] = RCAR_GP_PIN(0, 5), /* SD0_CLK */ + [19] = RCAR_GP_PIN(0, 4), /* CLKOUT */ + [20] = PIN_NMI, /* NMI */ + [21] = RCAR_GP_PIN(0, 3), /* USB1_OVC */ + [22] = RCAR_GP_PIN(0, 2), /* USB1_PWEN */ + [23] = RCAR_GP_PIN(0, 1), /* USB0_OVC */ + [24] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */ + [25] = SH_PFC_PIN_NONE, + [26] = PIN_TDO, /* TDO */ + [27] = PIN_TDI, /* TDI */ + [28] = PIN_TMS, /* TMS */ + [29] = PIN_TCK, /* TCK */ + [30] = PIN_TRST_N, /* TRST# */ + [31] = PIN_PRESETOUT_N, /* PRESETOUT# */ + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR0", 0xe6060100) { + /* PUPR0 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */ + [ 1] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */ + [ 2] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */ + [ 3] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */ + [ 4] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */ + [ 5] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */ + [ 6] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */ + [ 7] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */ + [ 8] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */ + [ 9] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */ + [10] = RCAR_GP_PIN(1, 22), /* EX_WAIT0 */ + [11] = RCAR_GP_PIN(1, 21), /* QSPI0_SSL */ + [12] = RCAR_GP_PIN(1, 20), /* QSPI0_IO3 */ + [13] = RCAR_GP_PIN(1, 19), /* QSPI0_IO2 */ + [14] = RCAR_GP_PIN(1, 18), /* QSPI0_MISO/QSPI0_IO1 */ + [15] = RCAR_GP_PIN(1, 17), /* QSPI0_MOSI/QSPI0_IO0 */ + [16] = RCAR_GP_PIN(1, 16), /* QSPI0_SPCLK */ + [17] = RCAR_GP_PIN(1, 15), /* D15 */ + [18] = RCAR_GP_PIN(1, 14), /* D14 */ + [19] = RCAR_GP_PIN(1, 13), /* D13 */ + [20] = RCAR_GP_PIN(1, 12), /* D12 */ + [21] = RCAR_GP_PIN(1, 11), /* D11 */ + [22] = RCAR_GP_PIN(1, 10), /* D10 */ + [23] = RCAR_GP_PIN(1, 9), /* D9 */ + [24] = RCAR_GP_PIN(1, 8), /* D8 */ + [25] = RCAR_GP_PIN(1, 7), /* D7 */ + [26] = RCAR_GP_PIN(1, 6), /* D6 */ + [27] = RCAR_GP_PIN(1, 5), /* D5 */ + [28] = RCAR_GP_PIN(1, 4), /* D4 */ + [29] = RCAR_GP_PIN(1, 3), /* D3 */ + [30] = RCAR_GP_PIN(1, 2), /* D2 */ + [31] = RCAR_GP_PIN(1, 1), /* D1 */ + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 9), /* VI1_CLKENB */ + [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA7 */ + [ 2] = RCAR_GP_PIN(3, 7), /* VI1_DATA6 */ + [ 3] = RCAR_GP_PIN(3, 6), /* VI1_DATA5 */ + [ 4] = RCAR_GP_PIN(3, 5), /* VI1_DATA4 */ + [ 5] = RCAR_GP_PIN(3, 4), /* VI1_DATA3 */ + [ 6] = RCAR_GP_PIN(3, 3), /* VI1_DATA2 */ + [ 7] = RCAR_GP_PIN(3, 2), /* VI1_DATA1 */ + [ 8] = RCAR_GP_PIN(3, 1), /* VI1_DATA0 */ + [ 9] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ + [10] = RCAR_GP_PIN(2, 31), /* DU0_CDE */ + [11] = RCAR_GP_PIN(2, 30), /* DU0_DISP */ + [12] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */ + [13] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */ + [14] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */ + [15] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */ + [16] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */ + [17] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */ + [18] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */ + [19] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */ + [20] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */ + [21] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */ + [22] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */ + [23] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */ + [24] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */ + [25] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */ + [26] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */ + [27] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */ + [28] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */ + [29] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */ + [30] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */ + [31] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 21), /* SD2_WP */ + [ 1] = RCAR_GP_PIN(4, 20), /* SD2_CD */ + [ 2] = RCAR_GP_PIN(4, 19), /* SD2_DAT3 */ + [ 3] = RCAR_GP_PIN(4, 18), /* SD2_DAT2 */ + [ 4] = RCAR_GP_PIN(4, 17), /* SD2_DAT1 */ + [ 5] = RCAR_GP_PIN(4, 16), /* SD2_DAT0 */ + [ 6] = RCAR_GP_PIN(4, 15), /* SD2_CMD */ + [ 7] = RCAR_GP_PIN(4, 14), /* SD2_CLK */ + [ 8] = RCAR_GP_PIN(4, 13), /* HRTS1#_A */ + [ 9] = RCAR_GP_PIN(4, 12), /* HCTS1#_A */ + [10] = RCAR_GP_PIN(4, 11), /* HTX1_A */ + [11] = RCAR_GP_PIN(4, 10), /* HRX1_A */ + [12] = RCAR_GP_PIN(4, 9), /* MSIOF0_SS2_A */ + [13] = RCAR_GP_PIN(4, 8), /* MSIOF0_SS1_A */ + [14] = RCAR_GP_PIN(4, 7), /* MSIOF0_SYNC_A */ + [15] = RCAR_GP_PIN(4, 6), /* MSIOF0_SCK_A */ + [16] = RCAR_GP_PIN(4, 5), /* MSIOF0_TXD_A */ + [17] = RCAR_GP_PIN(4, 4), /* MSIOF0_RXD_A */ + [18] = RCAR_GP_PIN(4, 3), /* SDA1_A */ + [19] = RCAR_GP_PIN(4, 2), /* SCL1_A */ + [20] = RCAR_GP_PIN(4, 1), /* SDA0_A */ + [21] = RCAR_GP_PIN(4, 0), /* SCL0_A */ + [22] = RCAR_GP_PIN(3, 29), /* AVB_TXD5 */ + [23] = RCAR_GP_PIN(3, 28), /* AVB_TXD4 */ + [24] = RCAR_GP_PIN(3, 27), /* AVB_TXD3 */ + [25] = RCAR_GP_PIN(3, 16), /* VI1_DATA11 */ + [26] = RCAR_GP_PIN(3, 15), /* VI1_DATA10 */ + [27] = RCAR_GP_PIN(3, 14), /* VI1_DATA9 */ + [28] = RCAR_GP_PIN(3, 13), /* VI1_DATA8 */ + [29] = RCAR_GP_PIN(3, 12), /* VI1_VSYNC# */ + [30] = RCAR_GP_PIN(3, 11), /* VI1_HSYNC# */ + [31] = RCAR_GP_PIN(3, 10), /* VI1_FIELD */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 27), /* SSI_SDATA9_A */ + [ 1] = RCAR_GP_PIN(5, 26), /* SSI_WS9_A */ + [ 2] = RCAR_GP_PIN(5, 25), /* SSI_SCK9_A */ + [ 3] = RCAR_GP_PIN(5, 24), /* SSI_SDATA2_A */ + [ 4] = RCAR_GP_PIN(5, 23), /* SSI_WS2_A */ + [ 5] = RCAR_GP_PIN(5, 22), /* SSI_SCK2_A */ + [ 6] = RCAR_GP_PIN(5, 21), /* SSI_SDATA1_A */ + [ 7] = RCAR_GP_PIN(5, 20), /* SSI_WS1_A */ + [ 8] = RCAR_GP_PIN(5, 19), /* SSI_SDATA8_A */ + [ 9] = RCAR_GP_PIN(5, 18), /* SSI_SCK1_A */ + [10] = RCAR_GP_PIN(5, 17), /* SSI_SDATA4_A */ + [11] = RCAR_GP_PIN(5, 16), /* SSI_WS4_A */ + [12] = RCAR_GP_PIN(5, 15), /* SSI_SCK4_A */ + [13] = RCAR_GP_PIN(5, 14), /* SSI_SDATA3 */ + [14] = RCAR_GP_PIN(5, 13), /* SSI_WS34 */ + [15] = RCAR_GP_PIN(5, 12), /* SSI_SCK34 */ + [16] = RCAR_GP_PIN(5, 11), /* SSI_SDATA0_A */ + [17] = RCAR_GP_PIN(5, 10), /* SSI_WS0129_A */ + [18] = RCAR_GP_PIN(5, 9), /* SSI_SCK0129_A */ + [19] = RCAR_GP_PIN(5, 8), /* SSI_SDATA7_A */ + [20] = RCAR_GP_PIN(5, 7), /* SSI_WS78_A */ + [21] = RCAR_GP_PIN(5, 6), /* SSI_SCK78_A */ + [22] = RCAR_GP_PIN(5, 5), /* SSI_SDATA6_A */ + [23] = RCAR_GP_PIN(5, 4), /* SSI_WS6_A */ + [24] = RCAR_GP_PIN(5, 3), /* SSI_SCK6_A */ + [25] = RCAR_GP_PIN(5, 2), /* SSI_SDATA5_A */ + [26] = RCAR_GP_PIN(5, 1), /* SSI_WS5_A */ + [27] = RCAR_GP_PIN(5, 0), /* SSI_SCK5_A */ + [28] = RCAR_GP_PIN(4, 25), /* SDA2_A */ + [29] = RCAR_GP_PIN(4, 24), /* SCL2_A */ + [30] = RCAR_GP_PIN(4, 23), /* TX3_A */ + [31] = RCAR_GP_PIN(4, 22), /* RX3_A */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = RCAR_GP_PIN(5, 31), /* AUDIO_CLKOUT_A */ + [29] = RCAR_GP_PIN(5, 30), /* AUDIO_CLKC_A */ + [30] = RCAR_GP_PIN(5, 29), /* AUDIO_CLKB_A */ + [31] = RCAR_GP_PIN(5, 28), /* AUDIO_CLKA_A */ + } }, + { /* sentinel */ } +}; + static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = { .pin_to_pocctrl = r8a77470_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A77470 @@ -3440,6 +3705,7 @@ const struct sh_pfc_soc_info r8a77470_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), -- cgit v1.2.3 From 2be3d6024234011217273ceb0437a2be312f82fa Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:06 +0200 Subject: pinctrl: renesas: r8a7790: Add bias pinconf support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car H2 and RZ/G1H SoCs, using the common R-Car bias handling. Note that on RZ/G1H, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Tested-by: Wolfram Sang Link: https://lore.kernel.org/r/dde6e0b36a4e4494039a3466df208b5ec5c594ee.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7790.c | 301 +++++++++++++++++++++++++++++++++- 1 file changed, 294 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index e9a64e0e2734..08c0a23edf68 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -21,18 +21,23 @@ * which case they support both 3.3V and 1.8V signalling. */ #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_30(1, fn, sfx), \ - PORT_GP_30(2, fn, sfx), \ - PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_32(5, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) #define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ PIN_NOGP(IIC0_SDA, "AF15", fn), \ PIN_NOGP(IIC0_SCL, "AG15", fn), \ PIN_NOGP(IIC3_SDA, "AH15", fn), \ - PIN_NOGP(IIC3_SCL, "AJ15", fn) + PIN_NOGP(IIC3_SCL, "AJ15", fn), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -5992,6 +5997,284 @@ static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return 31 - (pin & 0x1f); } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 16), /* A0 */ + [ 1] = RCAR_GP_PIN(0, 17), /* A1 */ + [ 2] = RCAR_GP_PIN(0, 18), /* A2 */ + [ 3] = RCAR_GP_PIN(0, 19), /* A3 */ + [ 4] = RCAR_GP_PIN(0, 20), /* A4 */ + [ 5] = RCAR_GP_PIN(0, 21), /* A5 */ + [ 6] = RCAR_GP_PIN(0, 22), /* A6 */ + [ 7] = RCAR_GP_PIN(0, 23), /* A7 */ + [ 8] = RCAR_GP_PIN(0, 24), /* A8 */ + [ 9] = RCAR_GP_PIN(0, 25), /* A9 */ + [10] = RCAR_GP_PIN(0, 26), /* A10 */ + [11] = RCAR_GP_PIN(0, 27), /* A11 */ + [12] = RCAR_GP_PIN(0, 28), /* A12 */ + [13] = RCAR_GP_PIN(0, 29), /* A13 */ + [14] = RCAR_GP_PIN(0, 30), /* A14 */ + [15] = RCAR_GP_PIN(0, 31), /* A15 */ + [16] = RCAR_GP_PIN(1, 0), /* A16 */ + [17] = RCAR_GP_PIN(1, 1), /* A17 */ + [18] = RCAR_GP_PIN(1, 2), /* A18 */ + [19] = RCAR_GP_PIN(1, 3), /* A19 */ + [20] = RCAR_GP_PIN(1, 4), /* A20 */ + [21] = RCAR_GP_PIN(1, 5), /* A21 */ + [22] = RCAR_GP_PIN(1, 6), /* A22 */ + [23] = RCAR_GP_PIN(1, 7), /* A23 */ + [24] = RCAR_GP_PIN(1, 8), /* A24 */ + [25] = RCAR_GP_PIN(1, 9), /* A25 */ + [26] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ + [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ + [28] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ + [29] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ + [30] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ + [31] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + /* PUPR1 pull-up pins */ + [ 0] = RCAR_GP_PIN(1, 18), /* BS# */ + [ 1] = RCAR_GP_PIN(1, 19), /* RD# */ + [ 2] = RCAR_GP_PIN(1, 20), /* RD/WR# */ + [ 3] = RCAR_GP_PIN(1, 21), /* WE0# */ + [ 4] = RCAR_GP_PIN(1, 22), /* WE1# */ + [ 5] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ + [ 6] = RCAR_GP_PIN(5, 24), /* AVS1 */ + [ 7] = RCAR_GP_PIN(5, 25), /* AVS2 */ + [ 8] = RCAR_GP_PIN(1, 10), /* CS0# */ + [ 9] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ + [10] = PIN_TRST_N, /* TRST# */ + [11] = PIN_TCK, /* TCK */ + [12] = PIN_TMS, /* TMS */ + [13] = PIN_TDI, /* TDI */ + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = RCAR_GP_PIN(0, 0), /* D0 */ + [17] = RCAR_GP_PIN(0, 1), /* D1 */ + [18] = RCAR_GP_PIN(0, 2), /* D2 */ + [19] = RCAR_GP_PIN(0, 3), /* D3 */ + [20] = RCAR_GP_PIN(0, 4), /* D4 */ + [21] = RCAR_GP_PIN(0, 5), /* D5 */ + [22] = RCAR_GP_PIN(0, 6), /* D6 */ + [23] = RCAR_GP_PIN(0, 7), /* D7 */ + [24] = RCAR_GP_PIN(0, 8), /* D8 */ + [25] = RCAR_GP_PIN(0, 9), /* D9 */ + [26] = RCAR_GP_PIN(0, 10), /* D10 */ + [27] = RCAR_GP_PIN(0, 11), /* D11 */ + [28] = RCAR_GP_PIN(0, 12), /* D12 */ + [29] = RCAR_GP_PIN(0, 13), /* D13 */ + [30] = RCAR_GP_PIN(0, 14), /* D14 */ + [31] = RCAR_GP_PIN(0, 15), /* D15 */ + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) { + /* PUPR1 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 28), /* DU_DOTCLKIN2 */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ + [ 6] = RCAR_GP_PIN(2, 1), /* VI0_DATA0_VI0_B0 */ + [ 7] = RCAR_GP_PIN(2, 2), /* VI0_DATA1_VI0_B1 */ + [ 8] = RCAR_GP_PIN(2, 3), /* VI0_DATA2_VI0_B2 */ + [ 9] = RCAR_GP_PIN(2, 4), /* VI0_DATA3_VI0_B3 */ + [10] = RCAR_GP_PIN(2, 5), /* VI0_DATA4_VI0_B4 */ + [11] = RCAR_GP_PIN(2, 6), /* VI0_DATA5_VI0_B5 */ + [12] = RCAR_GP_PIN(2, 7), /* VI0_DATA6_VI0_B6 */ + [13] = RCAR_GP_PIN(2, 8), /* VI0_DATA7_VI0_B7 */ + [14] = RCAR_GP_PIN(2, 9), /* VI1_CLK */ + [15] = RCAR_GP_PIN(2, 10), /* VI1_DATA0_VI1_B0 */ + [16] = RCAR_GP_PIN(2, 11), /* VI1_DATA1_VI1_B1 */ + [17] = RCAR_GP_PIN(2, 12), /* VI1_DATA2_VI1_B2 */ + [18] = RCAR_GP_PIN(2, 13), /* VI1_DATA3_VI1_B3 */ + [19] = RCAR_GP_PIN(2, 14), /* VI1_DATA4_VI1_B4 */ + [20] = RCAR_GP_PIN(2, 15), /* VI1_DATA5_VI1_B5 */ + [21] = RCAR_GP_PIN(2, 16), /* VI1_DATA6_VI1_B6 */ + [22] = RCAR_GP_PIN(2, 17), /* VI1_DATA7_VI1_B7 */ + [23] = RCAR_GP_PIN(5, 27), /* DU_DOTCLKIN1 */ + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = RCAR_GP_PIN(4, 0), /* MLB_CLK */ + [28] = RCAR_GP_PIN(4, 1), /* MLB_SIG */ + [29] = RCAR_GP_PIN(4, 2), /* MLB_DAT */ + [30] = SH_PFC_PIN_NONE, + [31] = RCAR_GP_PIN(5, 26), /* DU_DOTCLKIN0 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ + [ 1] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ + [ 2] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ + [ 3] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ + [ 4] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ + [ 5] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ + [ 6] = RCAR_GP_PIN(3, 6), /* SD0_CD */ + [ 7] = RCAR_GP_PIN(3, 7), /* SD0_WP */ + [ 8] = RCAR_GP_PIN(3, 8), /* SD1_CLK */ + [ 9] = RCAR_GP_PIN(3, 9), /* SD1_CMD */ + [10] = RCAR_GP_PIN(3, 10), /* SD1_DAT0 */ + [11] = RCAR_GP_PIN(3, 11), /* SD1_DAT1 */ + [12] = RCAR_GP_PIN(3, 12), /* SD1_DAT2 */ + [13] = RCAR_GP_PIN(3, 13), /* SD1_DAT3 */ + [14] = RCAR_GP_PIN(3, 14), /* SD1_CD */ + [15] = RCAR_GP_PIN(3, 15), /* SD1_WP */ + [16] = RCAR_GP_PIN(3, 16), /* SD2_CLK */ + [17] = RCAR_GP_PIN(3, 17), /* SD2_CMD */ + [18] = RCAR_GP_PIN(3, 18), /* SD2_DAT0 */ + [19] = RCAR_GP_PIN(3, 19), /* SD2_DAT1 */ + [20] = RCAR_GP_PIN(3, 20), /* SD2_DAT2 */ + [21] = RCAR_GP_PIN(3, 21), /* SD2_DAT3 */ + [22] = RCAR_GP_PIN(3, 22), /* SD2_CD */ + [23] = RCAR_GP_PIN(3, 23), /* SD2_WP */ + [24] = RCAR_GP_PIN(3, 24), /* SD3_CLK */ + [25] = RCAR_GP_PIN(3, 25), /* SD3_CMD */ + [26] = RCAR_GP_PIN(3, 26), /* SD3_DAT0 */ + [27] = RCAR_GP_PIN(3, 27), /* SD3_DAT1 */ + [28] = RCAR_GP_PIN(3, 28), /* SD3_DAT2 */ + [29] = RCAR_GP_PIN(3, 29), /* SD3_DAT3 */ + [30] = RCAR_GP_PIN(3, 30), /* SD3_CD */ + [31] = RCAR_GP_PIN(3, 31), /* SD3_WP */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 3), /* SSI_SCK0129 */ + [ 1] = RCAR_GP_PIN(4, 4), /* SSI_WS0129 */ + [ 2] = RCAR_GP_PIN(4, 5), /* SSI_SDATA0 */ + [ 3] = RCAR_GP_PIN(4, 6), /* SSI_SDATA1 */ + [ 4] = RCAR_GP_PIN(4, 7), /* SSI_SDATA2 */ + [ 5] = RCAR_GP_PIN(4, 8), /* SSI_SCK34 */ + [ 6] = RCAR_GP_PIN(4, 9), /* SSI_WS34 */ + [ 7] = RCAR_GP_PIN(4, 10), /* SSI_SDATA3 */ + [ 8] = RCAR_GP_PIN(4, 11), /* SSI_SCK4 */ + [ 9] = RCAR_GP_PIN(4, 12), /* SSI_WS4 */ + [10] = RCAR_GP_PIN(4, 13), /* SSI_SDATA4 */ + [11] = RCAR_GP_PIN(4, 14), /* SSI_SCK5 */ + [12] = RCAR_GP_PIN(4, 15), /* SSI_WS5 */ + [13] = RCAR_GP_PIN(4, 16), /* SSI_SDATA5 */ + [14] = RCAR_GP_PIN(4, 17), /* SSI_SCK6 */ + [15] = RCAR_GP_PIN(4, 18), /* SSI_WS6 */ + [16] = RCAR_GP_PIN(4, 19), /* SSI_SDATA6 */ + [17] = RCAR_GP_PIN(4, 20), /* SSI_SCK78 */ + [18] = RCAR_GP_PIN(4, 21), /* SSI_WS78 */ + [19] = RCAR_GP_PIN(4, 22), /* SSI_SDATA7 */ + [20] = RCAR_GP_PIN(4, 23), /* SSI_SDATA8 */ + [21] = RCAR_GP_PIN(4, 24), /* SSI_SDATA9 */ + [22] = RCAR_GP_PIN(4, 25), /* AUDIO_CLKA */ + [23] = RCAR_GP_PIN(4, 26), /* AUDIO_CLKB */ + [24] = RCAR_GP_PIN(1, 24), /* DREQ0 */ + [25] = RCAR_GP_PIN(1, 25), /* DACK0 */ + [26] = RCAR_GP_PIN(1, 26), /* DREQ1 */ + [27] = RCAR_GP_PIN(1, 27), /* DACK1 */ + [28] = RCAR_GP_PIN(1, 28), /* DREQ2 */ + [29] = RCAR_GP_PIN(1, 29), /* DACK2 */ + [30] = RCAR_GP_PIN(2, 18), /* ETH_CRS_DV */ + [31] = RCAR_GP_PIN(2, 19), /* ETH_RX_ER */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 27), /* SCIFA0_SCK */ + [ 1] = RCAR_GP_PIN(4, 28), /* SCIFA0_RXD */ + [ 2] = RCAR_GP_PIN(4, 29), /* SCIFA0_TXD */ + [ 3] = RCAR_GP_PIN(4, 30), /* SCIFA0_CTS# */ + [ 4] = RCAR_GP_PIN(4, 31), /* SCIFA0_RTS# */ + [ 5] = RCAR_GP_PIN(5, 0), /* SCIFA1_RXD */ + [ 6] = RCAR_GP_PIN(5, 1), /* SCIFA1_TXD */ + [ 7] = RCAR_GP_PIN(5, 2), /* SCIFA1_CTS# */ + [ 8] = RCAR_GP_PIN(5, 3), /* SCIFA1_RTS# */ + [ 9] = RCAR_GP_PIN(5, 4), /* SCIFA2_SCK */ + [10] = RCAR_GP_PIN(5, 5), /* SCIFA2_RXD */ + [11] = RCAR_GP_PIN(5, 6), /* SCIFA2_TXD */ + [12] = RCAR_GP_PIN(5, 7), /* HSCK0 */ + [13] = RCAR_GP_PIN(5, 8), /* HRX0 */ + [14] = RCAR_GP_PIN(5, 9), /* HTX0 */ + [15] = RCAR_GP_PIN(5, 10), /* HCTS0# */ + [16] = RCAR_GP_PIN(5, 11), /* HRTS0# */ + [17] = RCAR_GP_PIN(5, 12), /* MSIOF0_SCK */ + [18] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */ + [19] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */ + [20] = RCAR_GP_PIN(5, 15), /* MSIOF0_TXD */ + [21] = RCAR_GP_PIN(5, 16), /* MSIOF0_SS2 */ + [22] = RCAR_GP_PIN(5, 17), /* MSIOF0_RXD */ + [23] = RCAR_GP_PIN(5, 18), /* USB0_PWEN */ + [24] = RCAR_GP_PIN(5, 19), /* USB0_OVC_VBUS */ + [25] = RCAR_GP_PIN(5, 20), /* USB1_PWEN */ + [26] = RCAR_GP_PIN(5, 21), /* USB1_OVC */ + [27] = RCAR_GP_PIN(5, 22), /* USB2_PWEN */ + [28] = RCAR_GP_PIN(5, 23), /* USB2_OVC */ + [29] = RCAR_GP_PIN(2, 20), /* ETH_RXD0 */ + [30] = RCAR_GP_PIN(2, 21), /* ETH_RXD1 */ + [31] = RCAR_GP_PIN(2, 22), /* ETH_LINK */ + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 23), /* ETH_REF_CLK */ + [ 1] = RCAR_GP_PIN(2, 24), /* ETH_MDIO */ + [ 2] = RCAR_GP_PIN(2, 25), /* ETH_TXD1 */ + [ 3] = RCAR_GP_PIN(2, 26), /* ETH_TX_EN */ + [ 4] = RCAR_GP_PIN(2, 27), /* ETH_MAGIC */ + [ 5] = RCAR_GP_PIN(2, 28), /* ETH_TXD0 */ + [ 6] = RCAR_GP_PIN(2, 29), /* ETH_MDC */ + [ 7] = RCAR_GP_PIN(5, 29), /* PWM0 */ + [ 8] = RCAR_GP_PIN(5, 30), /* PWM1 */ + [ 9] = RCAR_GP_PIN(5, 31), /* PWM2 */ + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + static const struct soc_device_attribute r8a7790_tdsel[] = { { .soc_id = "r8a7790", .revision = "ES1.0" }, { /* sentinel */ } @@ -6009,6 +6292,8 @@ static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { .init = r8a7790_pinmux_soc_init, .pin_to_pocctrl = r8a7790_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A7742 @@ -6027,6 +6312,7 @@ const struct sh_pfc_soc_info r8a7742_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions.common), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -6051,6 +6337,7 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), -- cgit v1.2.3 From 35477d7e90a1aabf863f89c45a1e1fc15dacc305 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:07 +0200 Subject: pinctrl: renesas: r8a7792: Add bias pinconf support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for pull-up (most pins) and pull-down (EDBGREQ) handling for the R-Car V2H SoC, using the common R-Car bias handling. Note that the R-Car V2H Hardware User's Manual Rev. 1.00 says that the LSI Pin Pull-Up Control Register 11 (PUPR11) controls pull-ups for the {SCK,WS,SDATA}[01] pins. These are assumed to be typos, as R-Car V2H has only Serial Sound Interface channels 3 and 4. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/48d2abdd63ee43ed99cb32ed4a5f4d76ba563162.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7792.c | 533 +++++++++++++++++++++++++++++++++- 1 file changed, 521 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c index f54a7c81005d..3ab56dc768de 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7792.c +++ b/drivers/pinctrl/renesas/pfc-r8a7792.c @@ -11,18 +11,29 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_29(0, fn, sfx), \ - PORT_GP_23(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_28(3, fn, sfx), \ - PORT_GP_17(4, fn, sfx), \ - PORT_GP_17(5, fn, sfx), \ - PORT_GP_17(6, fn, sfx), \ - PORT_GP_17(7, fn, sfx), \ - PORT_GP_17(8, fn, sfx), \ - PORT_GP_17(9, fn, sfx), \ - PORT_GP_32(10, fn, sfx), \ - PORT_GP_30(11, fn, sfx) + PORT_GP_CFG_29(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_23(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_28(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(7, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(8, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_17(9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_30(11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DU0_DOTCLKIN, "DU0_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(DU0_DOTCLKOUT, "DU0_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(DU1_DOTCLKIN, "DU1_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(DU1_DOTCLKOUT, "DU1_DOTCLKOUT", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(EDBGREQ, "EDBGREQ", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -723,8 +734,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AVB -------------------------------------------------------------------- */ @@ -2779,8 +2799,496 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = { { }, }; +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 0), /* DU0_DR0_DATA0 */ + [ 1] = RCAR_GP_PIN(0, 1), /* DU0_DR1_DATA1 */ + [ 2] = RCAR_GP_PIN(0, 2), /* DU0_DR2_Y4_DATA2 */ + [ 3] = RCAR_GP_PIN(0, 3), /* DU0_DR3_Y5_DATA3 */ + [ 4] = RCAR_GP_PIN(0, 4), /* DU0_DR4_Y6_DATA4 */ + [ 5] = RCAR_GP_PIN(0, 5), /* DU0_DR5_Y7_DATA5 */ + [ 6] = RCAR_GP_PIN(0, 6), /* DU0_DR6_Y8_DATA6 */ + [ 7] = RCAR_GP_PIN(0, 7), /* DU0_DR7_Y9_DATA7 */ + [ 8] = RCAR_GP_PIN(0, 8), /* DU0_DG0_DATA8 */ + [ 9] = RCAR_GP_PIN(0, 9), /* DU0_DG1_DATA9 */ + [10] = RCAR_GP_PIN(0, 10), /* DU0_DG2_C6_DATA10 */ + [11] = RCAR_GP_PIN(0, 11), /* DU0_DG3_C7_DATA11 */ + [12] = RCAR_GP_PIN(0, 12), /* DU0_DG4_Y0_DATA12 */ + [13] = RCAR_GP_PIN(0, 13), /* DU0_DG5_Y1_DATA13 */ + [14] = RCAR_GP_PIN(0, 14), /* DU0_DG6_Y2_DATA14 */ + [15] = RCAR_GP_PIN(0, 15), /* DU0_DG7_Y3_DATA15 */ + [16] = RCAR_GP_PIN(0, 16), /* DU0_DB0 */ + [17] = RCAR_GP_PIN(0, 17), /* DU0_DB1 */ + [18] = RCAR_GP_PIN(0, 18), /* DU0_DB2_C0 */ + [19] = RCAR_GP_PIN(0, 19), /* DU0_DB3_C1 */ + [20] = RCAR_GP_PIN(0, 20), /* DU0_DB4_C2 */ + [21] = RCAR_GP_PIN(0, 21), /* DU0_DB5_C3 */ + [22] = RCAR_GP_PIN(0, 22), /* DU0_DB6_C4 */ + [23] = RCAR_GP_PIN(0, 23), /* DU0_DB7_C5 */ + [24] = RCAR_GP_PIN(0, 24), /* DU0_EXHSYNC/DU0_HSYNC */ + [25] = RCAR_GP_PIN(0, 25), /* DU0_EXVSYNC/DU0_VSYNC */ + [26] = RCAR_GP_PIN(0, 26), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */ + [27] = RCAR_GP_PIN(0, 27), /* DU0_DISP */ + [28] = RCAR_GP_PIN(0, 28), /* DU0_CDE */ + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + [ 0] = RCAR_GP_PIN(1, 0), /* DU1_DR2_Y4_DATA0 */ + [ 1] = RCAR_GP_PIN(1, 1), /* DU1_DR3_Y5_DATA1 */ + [ 2] = RCAR_GP_PIN(1, 2), /* DU1_DR4_Y6_DATA2 */ + [ 3] = RCAR_GP_PIN(1, 3), /* DU1_DR5_Y7_DATA3 */ + [ 4] = RCAR_GP_PIN(1, 4), /* DU1_DR6_DATA4 */ + [ 5] = RCAR_GP_PIN(1, 5), /* DU1_DR7_DATA5 */ + [ 6] = RCAR_GP_PIN(1, 6), /* DU1_DG2_C6_DATA6 */ + [ 7] = RCAR_GP_PIN(1, 7), /* DU1_DG3_C7_DATA7 */ + [ 8] = RCAR_GP_PIN(1, 8), /* DU1_DG4_Y0_DATA8 */ + [ 9] = RCAR_GP_PIN(1, 9), /* DU1_DG5_Y1_DATA9 */ + [10] = RCAR_GP_PIN(1, 10), /* DU1_DG6_Y2_DATA10 */ + [11] = RCAR_GP_PIN(1, 11), /* DU1_DG7_Y3_DATA11 */ + [12] = RCAR_GP_PIN(1, 12), /* DU1_DB2_C0_DATA12 */ + [13] = RCAR_GP_PIN(1, 13), /* DU1_DB3_C1_DATA13 */ + [14] = RCAR_GP_PIN(1, 14), /* DU1_DB4_C2_DATA14 */ + [15] = RCAR_GP_PIN(1, 15), /* DU1_DB5_C3_DATA15 */ + [16] = RCAR_GP_PIN(1, 16), /* DU1_DB6_C4 */ + [17] = RCAR_GP_PIN(1, 17), /* DU1_DB7_C5 */ + [18] = RCAR_GP_PIN(1, 18), /* DU1_EXHSYNC/DU1_HSYNC */ + [19] = RCAR_GP_PIN(1, 19), /* DU1_EXVSYNC/DU1_VSYNC */ + [20] = RCAR_GP_PIN(1, 20), /* DU1_EXODDF/DU1_ODDF_DISP_CDE */ + [21] = RCAR_GP_PIN(1, 21), /* DU1_DISP */ + [22] = RCAR_GP_PIN(1, 22), /* DU1_CDE */ + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 0), /* D0 */ + [ 1] = RCAR_GP_PIN(2, 1), /* D1 */ + [ 2] = RCAR_GP_PIN(2, 2), /* D2 */ + [ 3] = RCAR_GP_PIN(2, 3), /* D3 */ + [ 4] = RCAR_GP_PIN(2, 4), /* D4 */ + [ 5] = RCAR_GP_PIN(2, 5), /* D5 */ + [ 6] = RCAR_GP_PIN(2, 6), /* D6 */ + [ 7] = RCAR_GP_PIN(2, 7), /* D7 */ + [ 8] = RCAR_GP_PIN(2, 8), /* D8 */ + [ 9] = RCAR_GP_PIN(2, 9), /* D9 */ + [10] = RCAR_GP_PIN(2, 10), /* D10 */ + [11] = RCAR_GP_PIN(2, 11), /* D11 */ + [12] = RCAR_GP_PIN(2, 12), /* D12 */ + [13] = RCAR_GP_PIN(2, 13), /* D13 */ + [14] = RCAR_GP_PIN(2, 14), /* D14 */ + [15] = RCAR_GP_PIN(2, 15), /* D15 */ + [16] = RCAR_GP_PIN(2, 16), /* A0 */ + [17] = RCAR_GP_PIN(2, 17), /* A1 */ + [18] = RCAR_GP_PIN(2, 18), /* A2 */ + [19] = RCAR_GP_PIN(2, 19), /* A3 */ + [20] = RCAR_GP_PIN(2, 20), /* A4 */ + [21] = RCAR_GP_PIN(2, 21), /* A5 */ + [22] = RCAR_GP_PIN(2, 22), /* A6 */ + [23] = RCAR_GP_PIN(2, 23), /* A7 */ + [24] = RCAR_GP_PIN(2, 24), /* A8 */ + [25] = RCAR_GP_PIN(2, 25), /* A9 */ + [26] = RCAR_GP_PIN(2, 26), /* A10 */ + [27] = RCAR_GP_PIN(2, 27), /* A11 */ + [28] = RCAR_GP_PIN(2, 28), /* A12 */ + [29] = RCAR_GP_PIN(2, 29), /* A13 */ + [30] = RCAR_GP_PIN(2, 30), /* A14 */ + [31] = RCAR_GP_PIN(2, 31), /* A15 */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 0), /* A16 */ + [ 1] = RCAR_GP_PIN(3, 1), /* A17 */ + [ 2] = RCAR_GP_PIN(3, 2), /* A18 */ + [ 3] = RCAR_GP_PIN(3, 3), /* A19 */ + [ 4] = RCAR_GP_PIN(3, 4), /* A20 */ + [ 5] = RCAR_GP_PIN(3, 5), /* A21 */ + [ 6] = RCAR_GP_PIN(3, 6), /* CS1#/A26 */ + [ 7] = RCAR_GP_PIN(3, 7), /* EX_CS0# */ + [ 8] = RCAR_GP_PIN(3, 8), /* EX_CS1# */ + [ 9] = RCAR_GP_PIN(3, 9), /* EX_CS2# */ + [10] = RCAR_GP_PIN(3, 10), /* EX_CS3# */ + [11] = RCAR_GP_PIN(3, 11), /* EX_CS4# */ + [12] = RCAR_GP_PIN(3, 12), /* EX_CS5# */ + [13] = RCAR_GP_PIN(3, 13), /* BS# */ + [14] = RCAR_GP_PIN(3, 14), /* RD# */ + [15] = RCAR_GP_PIN(3, 15), /* RD/WR# */ + [16] = RCAR_GP_PIN(3, 16), /* WE0# */ + [17] = RCAR_GP_PIN(3, 17), /* WE1# */ + [18] = RCAR_GP_PIN(3, 18), /* EX_WAIT0 */ + [19] = RCAR_GP_PIN(3, 19), /* IRQ0 */ + [20] = RCAR_GP_PIN(3, 20), /* IRQ1 */ + [21] = RCAR_GP_PIN(3, 21), /* IRQ2 */ + [22] = RCAR_GP_PIN(3, 22), /* IRQ3 */ + [23] = RCAR_GP_PIN(3, 23), /* A22 */ + [24] = RCAR_GP_PIN(3, 24), /* A23 */ + [25] = RCAR_GP_PIN(3, 25), /* A24 */ + [26] = RCAR_GP_PIN(3, 26), /* A25 */ + [27] = RCAR_GP_PIN(3, 27), /* CS0# */ + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 0), /* VI0_CLK */ + [ 1] = RCAR_GP_PIN(4, 1), /* VI0_CLKENB */ + [ 2] = RCAR_GP_PIN(4, 2), /* VI0_HSYNC# */ + [ 3] = RCAR_GP_PIN(4, 3), /* VI0_VSYNC# */ + [ 4] = RCAR_GP_PIN(4, 4), /* VI0_D0_B0_C0 */ + [ 5] = RCAR_GP_PIN(4, 5), /* VI0_D1_B1_C1 */ + [ 6] = RCAR_GP_PIN(4, 6), /* VI0_D2_B2_C2 */ + [ 7] = RCAR_GP_PIN(4, 7), /* VI0_D3_B3_C3 */ + [ 8] = RCAR_GP_PIN(4, 8), /* VI0_D4_B4_C4 */ + [ 9] = RCAR_GP_PIN(4, 9), /* VI0_D5_B5_C5 */ + [10] = RCAR_GP_PIN(4, 10), /* VI0_D6_B6_C6 */ + [11] = RCAR_GP_PIN(4, 11), /* VI0_D7_B7_C7 */ + [12] = RCAR_GP_PIN(4, 12), /* VI0_D8_G0_Y0 */ + [13] = RCAR_GP_PIN(4, 13), /* VI0_D9_G1_Y1 */ + [14] = RCAR_GP_PIN(4, 14), /* VI0_D10_G2_Y2 */ + [15] = RCAR_GP_PIN(4, 15), /* VI0_D11_G3_Y3 */ + [16] = RCAR_GP_PIN(4, 16), /* VI0_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 0), /* VI1_CLK */ + [ 1] = RCAR_GP_PIN(5, 1), /* VI1_CLKENB */ + [ 2] = RCAR_GP_PIN(5, 2), /* VI1_HSYNC# */ + [ 3] = RCAR_GP_PIN(5, 3), /* VI1_VSYNC# */ + [ 4] = RCAR_GP_PIN(5, 4), /* VI1_D0_B0_C0 */ + [ 5] = RCAR_GP_PIN(5, 5), /* VI1_D1_B1_C1 */ + [ 6] = RCAR_GP_PIN(5, 6), /* VI1_D2_B2_C2 */ + [ 7] = RCAR_GP_PIN(5, 7), /* VI1_D3_B3_C3 */ + [ 8] = RCAR_GP_PIN(5, 8), /* VI1_D4_B4_C4 */ + [ 9] = RCAR_GP_PIN(5, 9), /* VI1_D5_B5_C5 */ + [10] = RCAR_GP_PIN(5, 10), /* VI1_D6_B6_C6 */ + [11] = RCAR_GP_PIN(5, 11), /* VI1_D7_B7_C7 */ + [12] = RCAR_GP_PIN(5, 12), /* VI1_D8_G0_Y0 */ + [13] = RCAR_GP_PIN(5, 13), /* VI1_D9_G1_Y1 */ + [14] = RCAR_GP_PIN(5, 14), /* VI1_D10_G2_Y2 */ + [15] = RCAR_GP_PIN(5, 15), /* VI1_D11_G3_Y3 */ + [16] = RCAR_GP_PIN(5, 16), /* VI1_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(6, 0), /* VI2_CLK */ + [ 1] = RCAR_GP_PIN(6, 1), /* VI2_CLKENB */ + [ 2] = RCAR_GP_PIN(6, 2), /* VI2_HSYNC# */ + [ 3] = RCAR_GP_PIN(6, 3), /* VI2_VSYNC# */ + [ 4] = RCAR_GP_PIN(6, 4), /* VI2_D0_C0 */ + [ 5] = RCAR_GP_PIN(6, 5), /* VI2_D1_C1 */ + [ 6] = RCAR_GP_PIN(6, 6), /* VI2_D2_C2 */ + [ 7] = RCAR_GP_PIN(6, 7), /* VI2_D3_C3 */ + [ 8] = RCAR_GP_PIN(6, 8), /* VI2_D4_C4 */ + [ 9] = RCAR_GP_PIN(6, 9), /* VI2_D5_C5 */ + [10] = RCAR_GP_PIN(6, 10), /* VI2_D6_C6 */ + [11] = RCAR_GP_PIN(6, 11), /* VI2_D7_C7 */ + [12] = RCAR_GP_PIN(6, 12), /* VI2_D8_Y0 */ + [13] = RCAR_GP_PIN(6, 13), /* VI2_D9_Y1 */ + [14] = RCAR_GP_PIN(6, 14), /* VI2_D10_Y2 */ + [15] = RCAR_GP_PIN(6, 15), /* VI2_D11_Y3 */ + [16] = RCAR_GP_PIN(6, 16), /* VI2_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR7", 0xe606011c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(7, 0), /* VI3_CLK */ + [ 1] = RCAR_GP_PIN(7, 1), /* VI3_CLKENB */ + [ 2] = RCAR_GP_PIN(7, 2), /* VI3_HSYNC# */ + [ 3] = RCAR_GP_PIN(7, 3), /* VI3_VSYNC# */ + [ 4] = RCAR_GP_PIN(7, 4), /* VI3_D0_C0 */ + [ 5] = RCAR_GP_PIN(7, 5), /* VI3_D1_C1 */ + [ 6] = RCAR_GP_PIN(7, 6), /* VI3_D2_C2 */ + [ 7] = RCAR_GP_PIN(7, 7), /* VI3_D3_C3 */ + [ 8] = RCAR_GP_PIN(7, 8), /* VI3_D4_C4 */ + [ 9] = RCAR_GP_PIN(7, 9), /* VI3_D5_C5 */ + [10] = RCAR_GP_PIN(7, 10), /* VI3_D6_C6 */ + [11] = RCAR_GP_PIN(7, 11), /* VI3_D7_C7 */ + [12] = RCAR_GP_PIN(7, 12), /* VI3_D8_Y0 */ + [13] = RCAR_GP_PIN(7, 13), /* VI3_D9_Y1 */ + [14] = RCAR_GP_PIN(7, 14), /* VI3_D10_Y2 */ + [15] = RCAR_GP_PIN(7, 15), /* VI3_D11_Y3 */ + [16] = RCAR_GP_PIN(7, 16), /* VI3_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR8", 0xe6060120, "N/A", 0) { + [ 0] = RCAR_GP_PIN(8, 0), /* VI4_CLK */ + [ 1] = RCAR_GP_PIN(8, 1), /* VI4_CLKENB */ + [ 2] = RCAR_GP_PIN(8, 2), /* VI4_HSYNC# */ + [ 3] = RCAR_GP_PIN(8, 3), /* VI4_VSYNC# */ + [ 4] = RCAR_GP_PIN(8, 4), /* VI4_D0_C0 */ + [ 5] = RCAR_GP_PIN(8, 5), /* VI4_D1_C1 */ + [ 6] = RCAR_GP_PIN(8, 6), /* VI4_D2_C2 */ + [ 7] = RCAR_GP_PIN(8, 7), /* VI4_D3_C3 */ + [ 8] = RCAR_GP_PIN(8, 8), /* VI4_D4_C4 */ + [ 9] = RCAR_GP_PIN(8, 9), /* VI4_D5_C5 */ + [10] = RCAR_GP_PIN(8, 10), /* VI4_D6_C6 */ + [11] = RCAR_GP_PIN(8, 11), /* VI4_D7_C7 */ + [12] = RCAR_GP_PIN(8, 12), /* VI4_D8_Y0 */ + [13] = RCAR_GP_PIN(8, 13), /* VI4_D9_Y1 */ + [14] = RCAR_GP_PIN(8, 14), /* VI4_D10_Y2 */ + [15] = RCAR_GP_PIN(8, 15), /* VI4_D11_Y3 */ + [16] = RCAR_GP_PIN(8, 16), /* VI4_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR9", 0xe6060124, "N/A", 0) { + [ 0] = RCAR_GP_PIN(9, 0), /* VI5_CLK */ + [ 1] = RCAR_GP_PIN(9, 1), /* VI5_CLKENB */ + [ 2] = RCAR_GP_PIN(9, 2), /* VI5_HSYNC# */ + [ 3] = RCAR_GP_PIN(9, 3), /* VI5_VSYNC# */ + [ 4] = RCAR_GP_PIN(9, 4), /* VI5_D0_C0 */ + [ 5] = RCAR_GP_PIN(9, 5), /* VI5_D1_C1 */ + [ 6] = RCAR_GP_PIN(9, 6), /* VI5_D2_C2 */ + [ 7] = RCAR_GP_PIN(9, 7), /* VI5_D3_C3 */ + [ 8] = RCAR_GP_PIN(9, 8), /* VI5_D4_C4 */ + [ 9] = RCAR_GP_PIN(9, 9), /* VI5_D5_C5 */ + [10] = RCAR_GP_PIN(9, 10), /* VI5_D6_C6 */ + [11] = RCAR_GP_PIN(9, 11), /* VI5_D7_C7 */ + [12] = RCAR_GP_PIN(9, 12), /* VI5_D8_Y0 */ + [13] = RCAR_GP_PIN(9, 13), /* VI5_D9_Y1 */ + [14] = RCAR_GP_PIN(9, 14), /* VI5_D10_Y2 */ + [15] = RCAR_GP_PIN(9, 15), /* VI5_D11_Y3 */ + [16] = RCAR_GP_PIN(9, 16), /* VI5_FIELD */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR10", 0xe6060128, "N/A", 0) { + [ 0] = RCAR_GP_PIN(10, 0), /* HSCK0 */ + [ 1] = RCAR_GP_PIN(10, 1), /* HCTS0# */ + [ 2] = RCAR_GP_PIN(10, 2), /* HRTS0# */ + [ 3] = RCAR_GP_PIN(10, 3), /* HTX0 */ + [ 4] = RCAR_GP_PIN(10, 4), /* HRX0 */ + [ 5] = RCAR_GP_PIN(10, 5), /* HSCK1 */ + [ 6] = RCAR_GP_PIN(10, 6), /* HRTS1# */ + [ 7] = RCAR_GP_PIN(10, 7), /* HCTS1# */ + [ 8] = RCAR_GP_PIN(10, 8), /* HTX1 */ + [ 9] = RCAR_GP_PIN(10, 9), /* HRX1 */ + [10] = RCAR_GP_PIN(10, 10), /* SCK0 */ + [11] = RCAR_GP_PIN(10, 11), /* CTS0# */ + [12] = RCAR_GP_PIN(10, 12), /* RTS0# */ + [13] = RCAR_GP_PIN(10, 13), /* TX0 */ + [14] = RCAR_GP_PIN(10, 14), /* RX0 */ + [15] = RCAR_GP_PIN(10, 15), /* SCK1 */ + [16] = RCAR_GP_PIN(10, 16), /* CTS1# */ + [17] = RCAR_GP_PIN(10, 17), /* RTS1# */ + [18] = RCAR_GP_PIN(10, 18), /* TX1 */ + [19] = RCAR_GP_PIN(10, 19), /* RX1 */ + [20] = RCAR_GP_PIN(10, 20), /* SCK2 */ + [21] = RCAR_GP_PIN(10, 21), /* TX2 */ + [22] = RCAR_GP_PIN(10, 22), /* RX2 */ + [23] = RCAR_GP_PIN(10, 23), /* SCK3 */ + [24] = RCAR_GP_PIN(10, 24), /* TX3 */ + [25] = RCAR_GP_PIN(10, 25), /* RX3 */ + [26] = RCAR_GP_PIN(10, 26), /* SCIF_CLK */ + [27] = RCAR_GP_PIN(10, 27), /* CAN0_TX */ + [28] = RCAR_GP_PIN(10, 28), /* CAN0_RX */ + [29] = RCAR_GP_PIN(10, 29), /* CAN_CLK */ + [30] = RCAR_GP_PIN(10, 30), /* CAN1_TX */ + [31] = RCAR_GP_PIN(10, 31), /* CAN1_RX */ + } }, + { PINMUX_BIAS_REG("PUPR11", 0xe606012c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(11, 0), /* PWM0 */ + [ 1] = RCAR_GP_PIN(11, 1), /* PWM1 */ + [ 2] = RCAR_GP_PIN(11, 2), /* PWM2 */ + [ 3] = RCAR_GP_PIN(11, 3), /* PWM3 */ + [ 4] = RCAR_GP_PIN(11, 4), /* PWM4 */ + [ 5] = RCAR_GP_PIN(11, 5), /* SD0_CLK */ + [ 6] = RCAR_GP_PIN(11, 6), /* SD0_CMD */ + [ 7] = RCAR_GP_PIN(11, 7), /* SD0_DAT0 */ + [ 8] = RCAR_GP_PIN(11, 8), /* SD0_DAT1 */ + [ 9] = RCAR_GP_PIN(11, 9), /* SD0_DAT2 */ + [10] = RCAR_GP_PIN(11, 10), /* SD0_DAT3 */ + [11] = RCAR_GP_PIN(11, 11), /* SD0_CD */ + [12] = RCAR_GP_PIN(11, 12), /* SD0_WP */ + [13] = RCAR_GP_PIN(11, 13), /* SSI_SCK3 */ + [14] = RCAR_GP_PIN(11, 14), /* SSI_WS3 */ + [15] = RCAR_GP_PIN(11, 15), /* SSI_SDATA3 */ + [16] = RCAR_GP_PIN(11, 16), /* SSI_SCK4 */ + [17] = RCAR_GP_PIN(11, 17), /* SSI_WS4 */ + [18] = RCAR_GP_PIN(11, 18), /* SSI_SDATA4 */ + [19] = RCAR_GP_PIN(11, 19), /* AUDIO_CLKOUT */ + [20] = RCAR_GP_PIN(11, 20), /* AUDIO_CLKA */ + [21] = RCAR_GP_PIN(11, 21), /* AUDIO_CLKB */ + [22] = RCAR_GP_PIN(11, 22), /* ADICLK */ + [23] = RCAR_GP_PIN(11, 23), /* ADICS_SAMP */ + [24] = RCAR_GP_PIN(11, 24), /* ADIDATA */ + [25] = RCAR_GP_PIN(11, 25), /* ADICHS0 */ + [26] = RCAR_GP_PIN(11, 26), /* ADICHS1 */ + [27] = RCAR_GP_PIN(11, 27), /* ADICHS2 */ + [28] = RCAR_GP_PIN(11, 28), /* AVS1 */ + [29] = RCAR_GP_PIN(11, 29), /* AVS2 */ + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR12", 0xe6060130, "N/A", 0) { + /* PUPR12 pull-up pins */ + [ 0] = PIN_DU0_DOTCLKIN, /* DU0_DOTCLKIN */ + [ 1] = PIN_DU0_DOTCLKOUT, /* DU0_DOTCLKOUT */ + [ 2] = PIN_DU1_DOTCLKIN, /* DU1_DOTCLKIN */ + [ 3] = PIN_DU1_DOTCLKOUT, /* DU1_DOTCLKOUT */ + [ 4] = PIN_TRST_N, /* TRST# */ + [ 5] = PIN_TCK, /* TCK */ + [ 6] = PIN_TMS, /* TMS */ + [ 7] = PIN_TDI, /* TDI */ + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR12", 0xe6060130) { + /* PUPR12 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = PIN_EDBGREQ, /* EDBGREQ */ + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + +static const struct sh_pfc_soc_operations r8a7792_pinmux_ops = { + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, +}; + const struct sh_pfc_soc_info r8a7792_pinmux_info = { .name = "r8a77920_pfc", + .ops = &r8a7792_pinmux_ops, .unlock_reg = 0xe6060000, /* PMMR */ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, @@ -2793,6 +3301,7 @@ const struct sh_pfc_soc_info r8a7792_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), -- cgit v1.2.3 From 009f502238a8464933595a128f812a3841830710 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:08 +0200 Subject: pinctrl: renesas: r8a7794: Add bias pinconf support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for pull-up (most pins) and pull-down (ASEBRK#/ACK) handling for R-Car E2 and RZ/G1E SoCs, using the common R-Car bias handling. Note that on RZ/G1E, the "ASEBRK#/ACK" pin is called "ACK", but the code doesn't handle that naming difference. Hence users should use the R-Car naming in DTS files. Signed-off-by: Geert Uytterhoeven Tested-by: Wolfram Sang Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/f78da2ba937ce98ae9196f4ee54149a5214fd545.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a7794.c | 360 +++++++++++++++++++++++++++++++++- 1 file changed, 351 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 34481b6c4328..fbb5b3b68f34 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -15,15 +15,66 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_32(0, fn, sfx), \ - PORT_GP_26(1, fn, sfx), \ - PORT_GP_32(2, fn, sfx), \ - PORT_GP_32(3, fn, sfx), \ - PORT_GP_32(4, fn, sfx), \ - PORT_GP_28(5, fn, sfx), \ - PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_1(6, 24, fn, sfx), \ - PORT_GP_1(6, 25, fn, sfx) + PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_26(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_7(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(5, 7, fn, sfx), \ + PORT_GP_1(5, 8, fn, sfx), \ + PORT_GP_1(5, 9, fn, sfx), \ + PORT_GP_CFG_1(5, 10, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 11, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 12, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 13, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 14, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 15, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 16, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 17, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 18, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 19, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 20, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 21, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 22, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(5, 23, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_1(5, 24, fn, sfx), \ + PORT_GP_1(5, 25, fn, sfx), \ + PORT_GP_1(5, 26, fn, sfx), \ + PORT_GP_1(5, 27, fn, sfx), \ + PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ + PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(ASEBRK_N_ACK, "ASEBRK#/ACK", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) enum { PINMUX_RESERVED = 0, @@ -1436,8 +1487,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - Audio Clock ------------------------------------------------------------ */ @@ -5580,6 +5640,284 @@ static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *poc return -EINVAL; } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUPR0", 0xe6060100, "N/A", 0) { + [ 0] = RCAR_GP_PIN(0, 0), /* D0 */ + [ 1] = RCAR_GP_PIN(0, 1), /* D1 */ + [ 2] = RCAR_GP_PIN(0, 2), /* D2 */ + [ 3] = RCAR_GP_PIN(0, 3), /* D3 */ + [ 4] = RCAR_GP_PIN(0, 4), /* D4 */ + [ 5] = RCAR_GP_PIN(0, 5), /* D5 */ + [ 6] = RCAR_GP_PIN(0, 6), /* D6 */ + [ 7] = RCAR_GP_PIN(0, 7), /* D7 */ + [ 8] = RCAR_GP_PIN(0, 8), /* D8 */ + [ 9] = RCAR_GP_PIN(0, 9), /* D9 */ + [10] = RCAR_GP_PIN(0, 10), /* D10 */ + [11] = RCAR_GP_PIN(0, 11), /* D11 */ + [12] = RCAR_GP_PIN(0, 12), /* D12 */ + [13] = RCAR_GP_PIN(0, 13), /* D13 */ + [14] = RCAR_GP_PIN(0, 14), /* D14 */ + [15] = RCAR_GP_PIN(0, 15), /* D15 */ + [16] = RCAR_GP_PIN(0, 16), /* A0 */ + [17] = RCAR_GP_PIN(0, 17), /* A1 */ + [18] = RCAR_GP_PIN(0, 18), /* A2 */ + [19] = RCAR_GP_PIN(0, 19), /* A3 */ + [20] = RCAR_GP_PIN(0, 20), /* A4 */ + [21] = RCAR_GP_PIN(0, 21), /* A5 */ + [22] = RCAR_GP_PIN(0, 22), /* A6 */ + [23] = RCAR_GP_PIN(0, 23), /* A7 */ + [24] = RCAR_GP_PIN(0, 24), /* A8 */ + [25] = RCAR_GP_PIN(0, 25), /* A9 */ + [26] = RCAR_GP_PIN(0, 26), /* A10 */ + [27] = RCAR_GP_PIN(0, 27), /* A11 */ + [28] = RCAR_GP_PIN(0, 28), /* A12 */ + [29] = RCAR_GP_PIN(0, 29), /* A13 */ + [30] = RCAR_GP_PIN(0, 30), /* A14 */ + [31] = RCAR_GP_PIN(0, 31), /* A15 */ + } }, + { PINMUX_BIAS_REG("PUPR1", 0xe6060104, "N/A", 0) { + /* PUPR1 pull-up pins */ + [ 0] = RCAR_GP_PIN(1, 0), /* A16 */ + [ 1] = RCAR_GP_PIN(1, 1), /* A17 */ + [ 2] = RCAR_GP_PIN(1, 2), /* A18 */ + [ 3] = RCAR_GP_PIN(1, 3), /* A19 */ + [ 4] = RCAR_GP_PIN(1, 4), /* A20 */ + [ 5] = RCAR_GP_PIN(1, 5), /* A21 */ + [ 6] = RCAR_GP_PIN(1, 6), /* A22 */ + [ 7] = RCAR_GP_PIN(1, 7), /* A23 */ + [ 8] = RCAR_GP_PIN(1, 8), /* A24 */ + [ 9] = RCAR_GP_PIN(1, 9), /* A25 */ + [10] = RCAR_GP_PIN(1, 10), /* CS0# */ + [11] = RCAR_GP_PIN(1, 12), /* EX_CS0# */ + [12] = RCAR_GP_PIN(1, 14), /* EX_CS2# */ + [13] = RCAR_GP_PIN(1, 16), /* EX_CS4# */ + [14] = RCAR_GP_PIN(1, 18), /* BS# */ + [15] = RCAR_GP_PIN(1, 19), /* RD# */ + [16] = RCAR_GP_PIN(1, 20), /* RD/WR# */ + [17] = RCAR_GP_PIN(1, 21), /* WE0# */ + [18] = RCAR_GP_PIN(1, 22), /* WE1# */ + [19] = RCAR_GP_PIN(1, 23), /* EX_WAIT0 */ + [20] = RCAR_GP_PIN(1, 24), /* DREQ0# */ + [21] = RCAR_GP_PIN(1, 25), /* DACK0 */ + [22] = PIN_TRST_N, /* TRST# */ + [23] = PIN_TCK, /* TCK */ + [24] = PIN_TMS, /* TMS */ + [25] = PIN_TDI, /* TDI */ + [26] = RCAR_GP_PIN(1, 11), /* CS1#/A26 */ + [27] = RCAR_GP_PIN(1, 13), /* EX_CS1# */ + [28] = RCAR_GP_PIN(1, 15), /* EX_CS3# */ + [29] = RCAR_GP_PIN(1, 17), /* EX_CS5# */ + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("N/A", 0, "PUPR1", 0xe6060104) { + /* PUPR1 pull-down pins */ + [ 0] = SH_PFC_PIN_NONE, + [ 1] = SH_PFC_PIN_NONE, + [ 2] = SH_PFC_PIN_NONE, + [ 3] = SH_PFC_PIN_NONE, + [ 4] = SH_PFC_PIN_NONE, + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = SH_PFC_PIN_NONE, + [ 9] = SH_PFC_PIN_NONE, + [10] = SH_PFC_PIN_NONE, + [11] = SH_PFC_PIN_NONE, + [12] = SH_PFC_PIN_NONE, + [13] = SH_PFC_PIN_NONE, + [14] = SH_PFC_PIN_NONE, + [15] = SH_PFC_PIN_NONE, + [16] = SH_PFC_PIN_NONE, + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = PIN_ASEBRK_N_ACK, /* ASEBRK#/ACK */ + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR2", 0xe6060108, "N/A", 0) { + [ 0] = RCAR_GP_PIN(2, 0), /* DU0_DR0 */ + [ 1] = RCAR_GP_PIN(2, 1), /* DU0_DR1 */ + [ 2] = RCAR_GP_PIN(2, 2), /* DU0_DR2 */ + [ 3] = RCAR_GP_PIN(2, 3), /* DU0_DR3 */ + [ 4] = RCAR_GP_PIN(2, 4), /* DU0_DR4 */ + [ 5] = RCAR_GP_PIN(2, 5), /* DU0_DR5 */ + [ 6] = RCAR_GP_PIN(2, 6), /* DU0_DR6 */ + [ 7] = RCAR_GP_PIN(2, 7), /* DU0_DR7 */ + [ 8] = RCAR_GP_PIN(2, 8), /* DU0_DG0 */ + [ 9] = RCAR_GP_PIN(2, 9), /* DU0_DG1 */ + [10] = RCAR_GP_PIN(2, 10), /* DU0_DG2 */ + [11] = RCAR_GP_PIN(2, 11), /* DU0_DG3 */ + [12] = RCAR_GP_PIN(2, 12), /* DU0_DG4 */ + [13] = RCAR_GP_PIN(2, 13), /* DU0_DG5 */ + [14] = RCAR_GP_PIN(2, 14), /* DU0_DG6 */ + [15] = RCAR_GP_PIN(2, 15), /* DU0_DG7 */ + [16] = RCAR_GP_PIN(2, 16), /* DU0_DB0 */ + [17] = RCAR_GP_PIN(2, 17), /* DU0_DB1 */ + [18] = RCAR_GP_PIN(2, 18), /* DU0_DB2 */ + [19] = RCAR_GP_PIN(2, 19), /* DU0_DB3 */ + [20] = RCAR_GP_PIN(2, 20), /* DU0_DB4 */ + [21] = RCAR_GP_PIN(2, 21), /* DU0_DB5 */ + [22] = RCAR_GP_PIN(2, 22), /* DU0_DB6 */ + [23] = RCAR_GP_PIN(2, 23), /* DU0_DB7 */ + [24] = RCAR_GP_PIN(2, 24), /* DU0_DOTCLKIN */ + [25] = RCAR_GP_PIN(2, 25), /* DU0_DOTCLKOUT0 */ + [26] = RCAR_GP_PIN(2, 26), /* DU0_DOTCLKOUT1 */ + [27] = RCAR_GP_PIN(2, 27), /* DU0_EXHSYNC/DU0_HSYNC */ + [28] = RCAR_GP_PIN(2, 28), /* DU0_EXVSYNC/DU0_VSYNC */ + [29] = RCAR_GP_PIN(2, 29), /* DU0_EXODDF/DU0_ODDF_DISP_CDE */ + [30] = RCAR_GP_PIN(2, 30), /* DU0_DISP */ + [31] = RCAR_GP_PIN(2, 31), /* DU0_CDE */ + } }, + { PINMUX_BIAS_REG("PUPR3", 0xe606010c, "N/A", 0) { + [ 0] = RCAR_GP_PIN(3, 2), /* VI0_DATA1_VI0_B1 */ + [ 1] = RCAR_GP_PIN(3, 3), /* VI0_DATA2_VI0_B2 */ + [ 2] = RCAR_GP_PIN(3, 4), /* VI0_DATA3_VI0_B3 */ + [ 3] = RCAR_GP_PIN(3, 5), /* VI0_DATA4_VI0_B4 */ + [ 4] = RCAR_GP_PIN(3, 6), /* VI0_DATA5_VI0_B5 */ + [ 5] = RCAR_GP_PIN(3, 7), /* VI0_DATA6_VI0_B6 */ + [ 6] = RCAR_GP_PIN(3, 8), /* VI0_DATA7_VI0_B7 */ + [ 7] = RCAR_GP_PIN(3, 9), /* VI0_CLKENB */ + [ 8] = RCAR_GP_PIN(3, 10), /* VI0_FIELD */ + [ 9] = RCAR_GP_PIN(3, 11), /* VI0_HSYNC# */ + [10] = RCAR_GP_PIN(3, 12), /* VI0_VSYNC# */ + [11] = RCAR_GP_PIN(3, 13), /* ETH_MDIO */ + [12] = RCAR_GP_PIN(3, 14), /* ETH_CRS_DV */ + [13] = RCAR_GP_PIN(3, 15), /* ETH_RX_ER */ + [14] = RCAR_GP_PIN(3, 16), /* ETH_RXD0 */ + [15] = RCAR_GP_PIN(3, 17), /* ETH_RXD1 */ + [16] = RCAR_GP_PIN(3, 18), /* ETH_LINK */ + [17] = RCAR_GP_PIN(3, 19), /* ETH_REF_CLK */ + [18] = RCAR_GP_PIN(3, 20), /* ETH_TXD1 */ + [19] = RCAR_GP_PIN(3, 21), /* ETH_TX_EN */ + [20] = RCAR_GP_PIN(3, 22), /* ETH_MAGIC */ + [21] = RCAR_GP_PIN(3, 23), /* ETH_TXD0 */ + [22] = RCAR_GP_PIN(3, 24), /* ETH_MDC */ + [23] = RCAR_GP_PIN(3, 25), /* HSCIF0_HRX */ + [24] = RCAR_GP_PIN(3, 26), /* HSCIF0_HTX */ + [25] = RCAR_GP_PIN(3, 27), /* HSCIF0_HCTS# */ + [26] = RCAR_GP_PIN(3, 28), /* HSCIF0_HRTS# */ + [27] = RCAR_GP_PIN(3, 29), /* HSCIF0_HSCK */ + [28] = RCAR_GP_PIN(3, 30), /* I2C0_SCL */ + [29] = RCAR_GP_PIN(3, 31), /* I2C0_SDA */ + [30] = RCAR_GP_PIN(4, 0), /* I2C1_SCL */ + [31] = RCAR_GP_PIN(4, 1), /* I2C1_SDA */ + } }, + { PINMUX_BIAS_REG("PUPR4", 0xe6060110, "N/A", 0) { + [ 0] = RCAR_GP_PIN(4, 2), /* MSIOF0_RXD */ + [ 1] = RCAR_GP_PIN(4, 3), /* MSIOF0_TXD */ + [ 2] = RCAR_GP_PIN(4, 4), /* MSIOF0_SCK */ + [ 3] = RCAR_GP_PIN(4, 5), /* MSIOF0_SYNC */ + [ 4] = RCAR_GP_PIN(4, 6), /* MSIOF0_SS1 */ + [ 5] = RCAR_GP_PIN(4, 7), /* MSIOF0_SS2 */ + [ 6] = RCAR_GP_PIN(4, 8), /* HSCIF1_HRX */ + [ 7] = RCAR_GP_PIN(4, 9), /* HSCIF1_HTX */ + [ 8] = RCAR_GP_PIN(4, 10), /* HSCIF1_HSCK */ + [ 9] = RCAR_GP_PIN(4, 11), /* HSCIF1_HCTS# */ + [10] = RCAR_GP_PIN(4, 12), /* HSCIF1_HRTS# */ + [11] = RCAR_GP_PIN(4, 13), /* SCIF1_SCK */ + [12] = RCAR_GP_PIN(4, 14), /* SCIF1_RXD */ + [13] = RCAR_GP_PIN(4, 15), /* SCIF1_TXD */ + [14] = RCAR_GP_PIN(4, 16), /* SCIF2_RXD */ + [15] = RCAR_GP_PIN(4, 17), /* SCIF2_TXD */ + [16] = RCAR_GP_PIN(4, 18), /* SCIF2_SCK */ + [17] = RCAR_GP_PIN(4, 19), /* SCIF3_SCK */ + [18] = RCAR_GP_PIN(4, 20), /* SCIF3_RXD */ + [19] = RCAR_GP_PIN(4, 21), /* SCIF3_TXD */ + [20] = RCAR_GP_PIN(4, 22), /* I2C2_SCL */ + [21] = RCAR_GP_PIN(4, 23), /* I2C2_SDA */ + [22] = RCAR_GP_PIN(4, 24), /* SSI_SCK5 */ + [23] = RCAR_GP_PIN(4, 25), /* SSI_WS5 */ + [24] = RCAR_GP_PIN(4, 26), /* SSI_SDATA5 */ + [25] = RCAR_GP_PIN(4, 27), /* SSI_SCK6 */ + [26] = RCAR_GP_PIN(4, 28), /* SSI_WS6 */ + [27] = RCAR_GP_PIN(4, 29), /* SSI_SDATA6 */ + [28] = RCAR_GP_PIN(4, 30), /* SSI_SCK78 */ + [29] = RCAR_GP_PIN(4, 31), /* SSI_WS78 */ + [30] = RCAR_GP_PIN(5, 0), /* SSI_SDATA7 */ + [31] = RCAR_GP_PIN(5, 1), /* SSI_SCK0129 */ + } }, + { PINMUX_BIAS_REG("PUPR5", 0xe6060114, "N/A", 0) { + [ 0] = RCAR_GP_PIN(5, 2), /* SSI_WS0129 */ + [ 1] = RCAR_GP_PIN(5, 3), /* SSI_SDATA0 */ + [ 2] = RCAR_GP_PIN(5, 4), /* SSI_SCK34 */ + [ 3] = RCAR_GP_PIN(5, 5), /* SSI_WS34 */ + [ 4] = RCAR_GP_PIN(5, 6), /* SSI_SDATA3 */ + [ 5] = SH_PFC_PIN_NONE, + [ 6] = SH_PFC_PIN_NONE, + [ 7] = SH_PFC_PIN_NONE, + [ 8] = RCAR_GP_PIN(5, 10), /* SSI_SDATA8 */ + [ 9] = RCAR_GP_PIN(5, 11), /* SSI_SCK1 */ + [10] = RCAR_GP_PIN(5, 12), /* SSI_WS1 */ + [11] = RCAR_GP_PIN(5, 13), /* SSI_SDATA1 */ + [12] = RCAR_GP_PIN(5, 14), /* SSI_SCK2 */ + [13] = RCAR_GP_PIN(5, 15), /* SSI_WS2 */ + [14] = RCAR_GP_PIN(5, 16), /* SSI_SDATA2 */ + [15] = RCAR_GP_PIN(5, 17), /* SSI_SCK9 */ + [16] = RCAR_GP_PIN(5, 18), /* SSI_WS9 */ + [17] = RCAR_GP_PIN(5, 19), /* SSI_SDATA9 */ + [18] = RCAR_GP_PIN(5, 20), /* AUDIO_CLKA */ + [19] = RCAR_GP_PIN(5, 21), /* AUDIO_CLKB */ + [20] = RCAR_GP_PIN(5, 22), /* AUDIO_CLKC */ + [21] = RCAR_GP_PIN(5, 23), /* AUDIO_CLKOUT */ + [22] = RCAR_GP_PIN(3, 0), /* VI0_CLK */ + [23] = RCAR_GP_PIN(3, 1), /* VI0_DATA0_VI0_B0 */ + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { PINMUX_BIAS_REG("PUPR6", 0xe6060118, "N/A", 0) { + [ 0] = RCAR_GP_PIN(6, 1), /* SD0_CMD */ + [ 1] = RCAR_GP_PIN(6, 2), /* SD0_DATA0 */ + [ 2] = RCAR_GP_PIN(6, 3), /* SD0_DATA1 */ + [ 3] = RCAR_GP_PIN(6, 4), /* SD0_DATA2 */ + [ 4] = RCAR_GP_PIN(6, 5), /* SD0_DATA3 */ + [ 5] = RCAR_GP_PIN(6, 6), /* SD0_CD */ + [ 6] = RCAR_GP_PIN(6, 7), /* SD0_WP */ + [ 7] = RCAR_GP_PIN(6, 9), /* SD1_CMD */ + [ 8] = RCAR_GP_PIN(6, 10), /* SD1_DATA0 */ + [ 9] = RCAR_GP_PIN(6, 11), /* SD1_DATA1 */ + [10] = RCAR_GP_PIN(6, 12), /* SD1_DATA2 */ + [11] = RCAR_GP_PIN(6, 13), /* SD1_DATA3 */ + [12] = RCAR_GP_PIN(6, 14), /* SD1_CD */ + [13] = RCAR_GP_PIN(6, 15), /* SD1_WP */ + [14] = SH_PFC_PIN_NONE, + [15] = RCAR_GP_PIN(6, 17), /* MMC_CMD */ + [16] = RCAR_GP_PIN(6, 18), /* MMC_D0 */ + [17] = RCAR_GP_PIN(6, 19), /* MMC_D1 */ + [18] = RCAR_GP_PIN(6, 20), /* MMC_D2 */ + [19] = RCAR_GP_PIN(6, 21), /* MMC_D3 */ + [20] = RCAR_GP_PIN(6, 22), /* MMC_D4 */ + [21] = RCAR_GP_PIN(6, 23), /* MMC_D5 */ + [22] = RCAR_GP_PIN(6, 24), /* MMC_D6 */ + [23] = RCAR_GP_PIN(6, 25), /* MMC_D7 */ + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + static const struct soc_device_attribute r8a7794_tdsel[] = { { .soc_id = "r8a7794", .revision = "ES1.0" }, { /* sentinel */ } @@ -5597,6 +5935,8 @@ static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = { .init = r8a7794_pinmux_soc_init, .pin_to_pocctrl = r8a7794_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; #ifdef CONFIG_PINCTRL_PFC_R8A7745 @@ -5615,6 +5955,7 @@ const struct sh_pfc_soc_info r8a7745_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), @@ -5637,6 +5978,7 @@ const struct sh_pfc_soc_info r8a7794_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), -- cgit v1.2.3 From b764833e36337cb2b574db75c1d31fde7dd6e6e5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:09 +0200 Subject: pinctrl: renesas: r8a77970: Add bias pinconf support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for pull-up (most pins, excl. DU_DOTCLKIN and EXTALR) and pull-down (most pins, excl. JTAG) handling for the R-Car V3M SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/bcfad447624d874258a45a92554574b8fe9f712f.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77970.c | 175 +++++++++++++++++++++++++++++++-- 1 file changed, 169 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c index 7935826cfae7..45b0b235c5cc 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -19,12 +19,23 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_28(1, fn, sfx), \ - PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_6(4, fn, sfx), \ - PORT_GP_15(5, fn, sfx) + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ + PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP) + /* * F_() : just information * FM() : macro for FN_xxx / xxx_MARK @@ -718,8 +729,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AVB0 ------------------------------------------------------------------- */ @@ -2496,8 +2516,150 @@ static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, return -EINVAL; } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */ + [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */ + [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */ + [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */ + [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */ + [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */ + [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */ + [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */ + [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */ + [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */ + [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */ + [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */ + [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */ + [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */ + [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */ + [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */ + [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */ + [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */ + [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */ + [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */ + [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */ + [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */ + [22] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */ + [23] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [24] = PIN_EXTALR, /* EXTALR */ + [25] = PIN_FSCLKST_N, /* FSCLKST# */ + [26] = RCAR_GP_PIN(1, 0), /* IRQ0 */ + [27] = PIN_TRST_N, /* TRST# */ + [28] = PIN_TCK, /* TCK */ + [29] = PIN_TMS, /* TMS */ + [30] = PIN_TDI, /* TDI */ + [31] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */ + [ 1] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */ + [ 2] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */ + [ 3] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */ + [ 4] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */ + [ 5] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */ + [ 6] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */ + [ 7] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */ + [ 8] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */ + [ 9] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */ + [10] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */ + [11] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */ + [12] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */ + [13] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */ + [14] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */ + [15] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */ + [16] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ + [17] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */ + [18] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */ + [19] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */ + [20] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */ + [21] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */ + [22] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */ + [23] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */ + [24] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */ + [25] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */ + [26] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */ + [27] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */ + [28] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */ + [29] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */ + [30] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */ + [31] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */ + [ 1] = RCAR_GP_PIN(4, 0), /* SCL0 */ + [ 2] = RCAR_GP_PIN(4, 1), /* SDA0 */ + [ 3] = RCAR_GP_PIN(4, 2), /* SCL1 */ + [ 4] = RCAR_GP_PIN(4, 3), /* SDA1 */ + [ 5] = RCAR_GP_PIN(4, 4), /* SCL2 */ + [ 6] = RCAR_GP_PIN(4, 5), /* SDA2 */ + [ 7] = RCAR_GP_PIN(1, 1), /* AVB0_RX_CTL */ + [ 8] = RCAR_GP_PIN(1, 2), /* AVB0_RXC */ + [ 9] = RCAR_GP_PIN(1, 3), /* AVB0_RD0 */ + [10] = RCAR_GP_PIN(1, 4), /* AVB0_RD1 */ + [11] = RCAR_GP_PIN(1, 5), /* AVB0_RD2 */ + [12] = RCAR_GP_PIN(1, 6), /* AVB0_RD3 */ + [13] = RCAR_GP_PIN(1, 7), /* AVB0_TX_CTL */ + [14] = RCAR_GP_PIN(1, 8), /* AVB0_TXC */ + [15] = RCAR_GP_PIN(1, 9), /* AVB0_TD0 */ + [16] = RCAR_GP_PIN(1, 10), /* AVB0_TD1 */ + [17] = RCAR_GP_PIN(1, 11), /* AVB0_TD2 */ + [18] = RCAR_GP_PIN(1, 12), /* AVB0_TD3 */ + [19] = RCAR_GP_PIN(1, 13), /* AVB0_TXCREFCLK */ + [20] = RCAR_GP_PIN(1, 14), /* AVB0_MDIO */ + [21] = RCAR_GP_PIN(1, 15), /* AVB0_MDC */ + [22] = RCAR_GP_PIN(1, 16), /* AVB0_MAGIC */ + [23] = RCAR_GP_PIN(1, 17), /* AVB0_PHY_INT */ + [24] = RCAR_GP_PIN(1, 18), /* AVB0_LINK */ + [25] = RCAR_GP_PIN(1, 19), /* AVB0_AVTP_MATCH */ + [26] = RCAR_GP_PIN(1, 20), /* AVB0_AVTP_CAPTURE */ + [27] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */ + [28] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */ + [29] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */ + [30] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */ + [31] = RCAR_GP_PIN(1, 25), /* CANFD_CLK */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */ + [ 1] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */ + [ 2] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */ + [ 3] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */ + [ 4] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */ + [ 5] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */ + [ 6] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */ + [ 7] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */ + [ 8] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */ + [ 9] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */ + [10] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */ + [11] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */ + [12] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */ + [13] = RCAR_GP_PIN(5, 13), /* RPC_WP# */ + [14] = RCAR_GP_PIN(5, 14), /* RPC_INT# */ + [15] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */ + [16] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */ + [17] = SH_PFC_PIN_NONE, + [18] = SH_PFC_PIN_NONE, + [19] = SH_PFC_PIN_NONE, + [20] = SH_PFC_PIN_NONE, + [21] = SH_PFC_PIN_NONE, + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = SH_PFC_PIN_NONE, + [25] = SH_PFC_PIN_NONE, + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + static const struct sh_pfc_soc_operations pinmux_ops = { .pin_to_pocctrl = r8a77970_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77970_pinmux_info = { @@ -2515,6 +2677,7 @@ const struct sh_pfc_soc_info r8a77970_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, -- cgit v1.2.3 From c3975a73ca9410519cf62531f640b68d69b0d798 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 30 Apr 2021 14:31:10 +0200 Subject: pinctrl: renesas: r8a77980: Add bias pinconf support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement support for pull-up and pull-down handling for the R-Car V3H SoC, using the common R-Car bias handling. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/448f47ccd89d9bc8621c7fda8c81508deb05cb82.1619785375.git.geert+renesas@glider.be --- drivers/pinctrl/renesas/pfc-r8a77980.c | 209 ++++++++++++++++++++++++++++++++- 1 file changed, 203 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 20cff93a2a13..c4825b01449e 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -19,12 +19,23 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx) \ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_28(1, fn, sfx), \ - PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_25(4, fn, sfx), \ - PORT_GP_15(5, fn, sfx) + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) + +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) /* * F_() : just information @@ -830,8 +841,17 @@ static const u16 pinmux_data[] = { PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N), }; +/* + * Pins not associated with a GPIO port. + */ +enum { + GP_ASSIGN_LAST(), + NOGP_ALL(), +}; + static const struct sh_pfc_pin pinmux_pins[] = { PINMUX_GPIO_GP_ALL(), + PINMUX_NOGP_ALL(), }; /* - AVB -------------------------------------------------------------------- */ @@ -2945,8 +2965,184 @@ static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, return -EINVAL; } +static const struct pinmux_bias_reg pinmux_bias_regs[] = { + { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { + [ 0] = RCAR_GP_PIN(0, 0), /* DU_DR2 */ + [ 1] = RCAR_GP_PIN(0, 1), /* DU_DR3 */ + [ 2] = RCAR_GP_PIN(0, 2), /* DU_DR4 */ + [ 3] = RCAR_GP_PIN(0, 3), /* DU_DR5 */ + [ 4] = RCAR_GP_PIN(0, 4), /* DU_DR6 */ + [ 5] = RCAR_GP_PIN(0, 5), /* DU_DR7 */ + [ 6] = RCAR_GP_PIN(0, 6), /* DU_DG2 */ + [ 7] = RCAR_GP_PIN(0, 7), /* DU_DG3 */ + [ 8] = RCAR_GP_PIN(0, 8), /* DU_DG4 */ + [ 9] = RCAR_GP_PIN(0, 9), /* DU_DG5 */ + [10] = RCAR_GP_PIN(0, 10), /* DU_DG6 */ + [11] = RCAR_GP_PIN(0, 11), /* DU_DG7 */ + [12] = RCAR_GP_PIN(0, 12), /* DU_DB2 */ + [13] = RCAR_GP_PIN(0, 13), /* DU_DB3 */ + [14] = RCAR_GP_PIN(0, 14), /* DU_DB4 */ + [15] = RCAR_GP_PIN(0, 15), /* DU_DB5 */ + [16] = RCAR_GP_PIN(0, 16), /* DU_DB6 */ + [17] = RCAR_GP_PIN(0, 17), /* DU_DB7 */ + [18] = RCAR_GP_PIN(0, 18), /* DU_DOTCLKOUT */ + [19] = RCAR_GP_PIN(0, 19), /* DU_EXHSYNC/DU_HSYNC */ + [20] = RCAR_GP_PIN(0, 20), /* DU_EXVSYNC/DU_VSYNC */ + [21] = RCAR_GP_PIN(0, 21), /* DU_EXODDF/DU_ODDF/DISP/CDE */ + [22] = SH_PFC_PIN_NONE, + [23] = SH_PFC_PIN_NONE, + [24] = PIN_DU_DOTCLKIN, /* DU_DOTCLKIN */ + [25] = SH_PFC_PIN_NONE, + [26] = PIN_PRESETOUT_N, /* PRESETOUT# */ + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = PIN_EXTALR, /* EXTALR */ + [31] = PIN_FSCLKST_N, /* FSCLKST# */ + } }, + { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { + [ 0] = PIN_FSCLKST, /* FSCLKST */ + [ 1] = SH_PFC_PIN_NONE, + [ 2] = RCAR_GP_PIN(1, 0), /* IRQ0 */ + [ 3] = PIN_DCUTRST_N, /* DCUTRST# */ + [ 4] = PIN_DCUTCK_LPDCLK, /* DCUTCK_LPDCLK */ + [ 5] = PIN_DCUTMS, /* DCUTMS */ + [ 6] = PIN_DCUTDI_LPDI, /* DCUTDI_LPDI */ + [ 7] = SH_PFC_PIN_NONE, + [ 8] = RCAR_GP_PIN(2, 0), /* VI0_CLK */ + [ 9] = RCAR_GP_PIN(2, 1), /* VI0_CLKENB */ + [10] = RCAR_GP_PIN(2, 2), /* VI0_HSYNC# */ + [11] = RCAR_GP_PIN(2, 3), /* VI0_VSYNC# */ + [12] = RCAR_GP_PIN(2, 4), /* VI0_DATA0 */ + [13] = RCAR_GP_PIN(2, 5), /* VI0_DATA1 */ + [14] = RCAR_GP_PIN(2, 6), /* VI0_DATA2 */ + [15] = RCAR_GP_PIN(2, 7), /* VI0_DATA3 */ + [16] = RCAR_GP_PIN(2, 8), /* VI0_DATA4 */ + [17] = RCAR_GP_PIN(2, 9), /* VI0_DATA5 */ + [18] = RCAR_GP_PIN(2, 10), /* VI0_DATA6 */ + [19] = RCAR_GP_PIN(2, 11), /* VI0_DATA7 */ + [20] = RCAR_GP_PIN(2, 12), /* VI0_DATA8 */ + [21] = RCAR_GP_PIN(2, 13), /* VI0_DATA9 */ + [22] = RCAR_GP_PIN(2, 14), /* VI0_DATA10 */ + [23] = RCAR_GP_PIN(2, 15), /* VI0_DATA11 */ + [24] = RCAR_GP_PIN(2, 16), /* VI0_FIELD */ + [25] = RCAR_GP_PIN(3, 0), /* VI1_CLK */ + [26] = RCAR_GP_PIN(3, 1), /* VI1_CLKENB */ + [27] = RCAR_GP_PIN(3, 2), /* VI1_HSYNC# */ + [28] = RCAR_GP_PIN(3, 3), /* VI1_VSYNC# */ + [29] = RCAR_GP_PIN(3, 4), /* VI1_DATA0 */ + [30] = RCAR_GP_PIN(3, 5), /* VI1_DATA1 */ + [31] = RCAR_GP_PIN(3, 6), /* VI1_DATA2 */ + } }, + { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { + [ 0] = RCAR_GP_PIN(3, 7), /* VI1_DATA3 */ + [ 1] = RCAR_GP_PIN(3, 8), /* VI1_DATA4 */ + [ 2] = RCAR_GP_PIN(3, 9), /* VI1_DATA5 */ + [ 3] = RCAR_GP_PIN(3, 10), /* VI1_DATA6 */ + [ 4] = RCAR_GP_PIN(3, 11), /* VI1_DATA7 */ + [ 5] = RCAR_GP_PIN(3, 12), /* VI1_DATA8 */ + [ 6] = RCAR_GP_PIN(3, 13), /* VI1_DATA9 */ + [ 7] = RCAR_GP_PIN(3, 14), /* VI1_DATA10 */ + [ 8] = RCAR_GP_PIN(3, 15), /* VI1_DATA11 */ + [ 9] = RCAR_GP_PIN(3, 16), /* VI1_FIELD */ + [10] = RCAR_GP_PIN(4, 0), /* SCL0 */ + [11] = RCAR_GP_PIN(4, 1), /* SDA0 */ + [12] = RCAR_GP_PIN(4, 2), /* SCL1 */ + [13] = RCAR_GP_PIN(4, 3), /* SDA1 */ + [14] = RCAR_GP_PIN(4, 4), /* SCL2 */ + [15] = RCAR_GP_PIN(4, 5), /* SDA2 */ + [16] = RCAR_GP_PIN(1, 1), /* AVB_RX_CTL */ + [17] = RCAR_GP_PIN(1, 2), /* AVB_RXC */ + [18] = RCAR_GP_PIN(1, 3), /* AVB_RD0 */ + [19] = RCAR_GP_PIN(1, 4), /* AVB_RD1 */ + [20] = RCAR_GP_PIN(1, 5), /* AVB_RD2 */ + [21] = RCAR_GP_PIN(1, 6), /* AVB_RD3 */ + [22] = RCAR_GP_PIN(1, 7), /* AVB_TX_CTL */ + [23] = RCAR_GP_PIN(1, 8), /* AVB_TXC */ + [24] = RCAR_GP_PIN(1, 9), /* AVB_TD0 */ + [25] = RCAR_GP_PIN(1, 10), /* AVB_TD1 */ + [26] = RCAR_GP_PIN(1, 11), /* AVB_TD2 */ + [27] = RCAR_GP_PIN(1, 12), /* AVB_TD3 */ + [28] = RCAR_GP_PIN(1, 13), /* AVB_TXCREFCLK */ + [29] = RCAR_GP_PIN(1, 14), /* AVB_MDIO */ + [30] = RCAR_GP_PIN(1, 15), /* AVB_MDC */ + [31] = RCAR_GP_PIN(1, 16), /* AVB_MAGIC */ + } }, + { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { + [ 0] = RCAR_GP_PIN(1, 17), /* AVB_PHY_INT */ + [ 1] = RCAR_GP_PIN(1, 18), /* AVB_LINK */ + [ 2] = RCAR_GP_PIN(1, 19), /* AVB_AVTP_MATCH */ + [ 3] = RCAR_GP_PIN(1, 20), /* AVTP_CAPTURE */ + [ 4] = RCAR_GP_PIN(4, 6), /* GETHER_RX_CTL */ + [ 5] = RCAR_GP_PIN(4, 7), /* GETHER_RXC */ + [ 6] = RCAR_GP_PIN(4, 8), /* GETHER_RD0 */ + [ 7] = RCAR_GP_PIN(4, 9), /* GETHER_RD1 */ + [ 8] = RCAR_GP_PIN(4, 10), /* GETHER_RD2 */ + [ 9] = RCAR_GP_PIN(4, 11), /* GETHER_RD3 */ + [10] = RCAR_GP_PIN(4, 12), /* GETHER_TX_CTL */ + [11] = RCAR_GP_PIN(4, 13), /* GETHER_TXC */ + [12] = RCAR_GP_PIN(4, 14), /* GETHER_TD0 */ + [13] = RCAR_GP_PIN(4, 15), /* GETHER_TD1 */ + [14] = RCAR_GP_PIN(4, 16), /* GETHER_TD2 */ + [15] = RCAR_GP_PIN(4, 17), /* GETHER_TD3 */ + [16] = RCAR_GP_PIN(4, 18), /* GETHER_TXCREFCLK */ + [17] = RCAR_GP_PIN(4, 19), /* GETHER_TXCREFCLK_MEGA */ + [18] = RCAR_GP_PIN(4, 20), /* GETHER_MDIO_A */ + [19] = RCAR_GP_PIN(4, 21), /* GETHER_MDC_A */ + [20] = RCAR_GP_PIN(4, 22), /* GETHER_MAGIC */ + [21] = RCAR_GP_PIN(4, 23), /* GETHER_PHY_INT_A */ + [22] = RCAR_GP_PIN(4, 24), /* GETHER_LINK_A */ + [23] = RCAR_GP_PIN(1, 21), /* CANFD0_TX_A */ + [24] = RCAR_GP_PIN(1, 22), /* CANFD0_RX_A */ + [25] = RCAR_GP_PIN(1, 23), /* CANFD1_TX */ + [26] = RCAR_GP_PIN(1, 24), /* CANFD1_RX */ + [27] = RCAR_GP_PIN(1, 25), /* CAN_CLK_A */ + [28] = RCAR_GP_PIN(5, 0), /* QSPI0_SPCLK */ + [29] = RCAR_GP_PIN(5, 1), /* QSPI0_MOSI_IO0 */ + [30] = RCAR_GP_PIN(5, 2), /* QSPI0_MISO_IO1 */ + [31] = RCAR_GP_PIN(5, 3), /* QSPI0_IO2 */ + } }, + { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { + [ 0] = RCAR_GP_PIN(5, 4), /* QSPI0_IO3 */ + [ 1] = RCAR_GP_PIN(5, 5), /* QSPI0_SSL */ + [ 2] = RCAR_GP_PIN(5, 6), /* QSPI1_SPCLK */ + [ 3] = RCAR_GP_PIN(5, 7), /* QSPI1_MOSI_IO0 */ + [ 4] = RCAR_GP_PIN(5, 8), /* QSPI1_MISO_IO1 */ + [ 5] = RCAR_GP_PIN(5, 9), /* QSPI1_IO2 */ + [ 6] = RCAR_GP_PIN(5, 10), /* QSPI1_IO3 */ + [ 7] = RCAR_GP_PIN(5, 11), /* QSPI1_SSL */ + [ 8] = RCAR_GP_PIN(5, 12), /* RPC_RESET# */ + [ 9] = RCAR_GP_PIN(5, 13), /* RPC_WP# */ + [10] = RCAR_GP_PIN(5, 14), /* RPC_INT# */ + [11] = RCAR_GP_PIN(1, 26), /* DIGRF_CLKIN */ + [12] = RCAR_GP_PIN(1, 27), /* DIGRF_CLKOUT */ + [13] = RCAR_GP_PIN(2, 17), /* IRQ4 */ + [14] = RCAR_GP_PIN(2, 18), /* IRQ5 */ + [15] = RCAR_GP_PIN(2, 25), /* SCL3 */ + [16] = RCAR_GP_PIN(2, 26), /* SDA3 */ + [17] = RCAR_GP_PIN(2, 19), /* MSIOF0_RXD */ + [18] = RCAR_GP_PIN(2, 20), /* MSIOF0_TXD */ + [19] = RCAR_GP_PIN(2, 21), /* MSIOF0_SCK */ + [20] = RCAR_GP_PIN(2, 22), /* MSIOF0_SYNC */ + [21] = RCAR_GP_PIN(2, 23), /* MSIOF0_SS1 */ + [22] = RCAR_GP_PIN(2, 24), /* MSIOF0_SS2 */ + [23] = RCAR_GP_PIN(2, 27), /* FSO_CFE_0# */ + [24] = RCAR_GP_PIN(2, 28), /* FSO_CFE_1# */ + [25] = RCAR_GP_PIN(2, 29), /* FSO_TOE# */ + [26] = SH_PFC_PIN_NONE, + [27] = SH_PFC_PIN_NONE, + [28] = SH_PFC_PIN_NONE, + [29] = SH_PFC_PIN_NONE, + [30] = SH_PFC_PIN_NONE, + [31] = SH_PFC_PIN_NONE, + } }, + { /* sentinel */ } +}; + static const struct sh_pfc_soc_operations pinmux_ops = { .pin_to_pocctrl = r8a77980_pin_to_pocctrl, + .get_bias = rcar_pinmux_get_bias, + .set_bias = rcar_pinmux_set_bias, }; const struct sh_pfc_soc_info r8a77980_pinmux_info = { @@ -2964,6 +3160,7 @@ const struct sh_pfc_soc_info r8a77980_pinmux_info = { .nr_functions = ARRAY_SIZE(pinmux_functions), .cfg_regs = pinmux_config_regs, + .bias_regs = pinmux_bias_regs, .ioctrl_regs = pinmux_ioctrl_regs, .pinmux_data = pinmux_data, -- cgit v1.2.3 From 897120d41e7afd9da435cb00041a142aeeb53c07 Mon Sep 17 00:00:00 2001 From: Radim Pavlik Date: Tue, 1 Jun 2021 10:48:18 +0000 Subject: pinctrl: mcp23s08: fix race condition in irq handler Checking value of MCP_INTF in mcp23s08_irq suggests that the handler may be called even when there is no interrupt pending. But the actual interrupt could happened between reading MCP_INTF and MCP_GPIO. In this situation we got nothing from MCP_INTF, but the event gets acknowledged on the expander by reading MCP_GPIO. This leads to losing events. Fix the problem by not reading any register until we see something in MCP_INTF. The error was reproduced and fix tested on MCP23017. Signed-off-by: Radim Pavlik Link: https://lore.kernel.org/r/AM7PR06MB6769E1183F68DEBB252F665ABA3E9@AM7PR06MB6769.eurprd06.prod.outlook.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index ce2d8014b7e0..799d596a1a4b 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -351,6 +351,11 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) if (mcp_read(mcp, MCP_INTF, &intf)) goto unlock; + if (intf == 0) { + /* There is no interrupt pending */ + return IRQ_HANDLED; + } + if (mcp_read(mcp, MCP_INTCAP, &intcap)) goto unlock; @@ -368,11 +373,6 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) mcp->cached_gpio = gpio; mutex_unlock(&mcp->lock); - if (intf == 0) { - /* There is no interrupt pending */ - return IRQ_HANDLED; - } - dev_dbg(mcp->chip.parent, "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n", intcap, intf, gpio_orig, gpio); -- cgit v1.2.3 From 375eede3e37797667850f10342d8ace6fb327553 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Mon, 7 Jun 2021 08:56:20 +0200 Subject: pinctrl: mtk: Fix mt8365 Kconfig dependency This SoC needs to select PINCTRL_MTK or we can end up in kernel compiles that miss some symbols. Cc: Fabien Parent Reported-by: kernel test robot Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC") Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index b27c2070559a..7040a7a7bd5d 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -158,6 +158,7 @@ config PINCTRL_MT8365 depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK config PINCTRL_MT8516 bool "Mediatek MT8516 pin control" -- cgit v1.2.3 From 8c987eb15aa6e397e2dba63246c4d8785f5c9f41 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Wed, 2 Jun 2021 17:04:20 +0200 Subject: pinctrl: single: config: enable the pin's input It enables / disables the input buffer. As explained in the description of 'enum pin_config_param' this does not affect the pin's ability to drive output. Signed-off-by: Dario Binacchi Acked-by: Tony Lindgren Link: https://lore.kernel.org/r/20210602150420.18202-1-dariobin@libero.it Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 7834d5d23224..e3aa64798f7d 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -534,6 +534,7 @@ static int pcs_pinconf_get(struct pinctrl_dev *pctldev, case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: case PIN_CONFIG_MODE_LOW_POWER: + case PIN_CONFIG_INPUT_ENABLE: default: *config = data; break; @@ -572,6 +573,7 @@ static int pcs_pinconf_set(struct pinctrl_dev *pctldev, case PIN_CONFIG_DRIVE_STRENGTH: case PIN_CONFIG_SLEW_RATE: case PIN_CONFIG_MODE_LOW_POWER: + case PIN_CONFIG_INPUT_ENABLE: shift = ffs(func->conf[i].mask) - 1; data &= ~func->conf[i].mask; data |= (arg << shift) & func->conf[i].mask; @@ -918,6 +920,7 @@ static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, static const struct pcs_conf_type prop2[] = { { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, + { "pinctrl-single,input-enable", PIN_CONFIG_INPUT_ENABLE, }, { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, { "pinctrl-single,low-power-mode", PIN_CONFIG_MODE_LOW_POWER, }, }; -- cgit v1.2.3 From 276e552e081c2db115319130511b55397d9695bd Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Fri, 4 Jun 2021 13:51:54 +0200 Subject: pinctrl: ralink: move ralink architecture pinmux header into the driver Ralink architecture is making use of the header located in 'arch/mips/include/asm/mach-ralink/pinmux.h' to stablish the mechanisms to make derived SoCs to set its pin functions and groups. In order to move all architecture pinmux into a more accurate place which is 'drivers/pinctrl/ralink' we have to first of all move this file also there with a small modification which creates 'rt2880_pinmux_init' function to allow SoCs pinctrl drivers to pass its configuration to the common code located in 'pinctrl-rt2880.c' file. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210604115159.8834-2-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij --- arch/mips/include/asm/mach-ralink/pinmux.h | 52 ----------------------------- arch/mips/ralink/prom.c | 1 - drivers/pinctrl/ralink/pinctrl-rt2880.c | 30 +++-------------- drivers/pinctrl/ralink/pinmux.h | 53 ++++++++++++++++++++++++++++++ 4 files changed, 58 insertions(+), 78 deletions(-) delete mode 100644 arch/mips/include/asm/mach-ralink/pinmux.h create mode 100644 drivers/pinctrl/ralink/pinmux.h diff --git a/arch/mips/include/asm/mach-ralink/pinmux.h b/arch/mips/include/asm/mach-ralink/pinmux.h deleted file mode 100644 index 048309348be0..000000000000 --- a/arch/mips/include/asm/mach-ralink/pinmux.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2012 John Crispin - */ - -#ifndef _RT288X_PINMUX_H__ -#define _RT288X_PINMUX_H__ - -#define FUNC(name, value, pin_first, pin_count) \ - { name, value, pin_first, pin_count } - -#define GRP(_name, _func, _mask, _shift) \ - { .name = _name, .mask = _mask, .shift = _shift, \ - .func = _func, .gpio = _mask, \ - .func_count = ARRAY_SIZE(_func) } - -#define GRP_G(_name, _func, _mask, _gpio, _shift) \ - { .name = _name, .mask = _mask, .shift = _shift, \ - .func = _func, .gpio = _gpio, \ - .func_count = ARRAY_SIZE(_func) } - -struct rt2880_pmx_group; - -struct rt2880_pmx_func { - const char *name; - const char value; - - int pin_first; - int pin_count; - int *pins; - - int *groups; - int group_count; - - int enabled; -}; - -struct rt2880_pmx_group { - const char *name; - int enabled; - - const u32 shift; - const char mask; - const char gpio; - - struct rt2880_pmx_func *func; - int func_count; -}; - -extern struct rt2880_pmx_group *rt2880_pinmux_data; - -#endif diff --git a/arch/mips/ralink/prom.c b/arch/mips/ralink/prom.c index 25728def3503..aaac1e6ec7d9 100644 --- a/arch/mips/ralink/prom.c +++ b/arch/mips/ralink/prom.c @@ -18,7 +18,6 @@ #include "common.h" struct ralink_soc_info soc_info; -struct rt2880_pmx_group *rt2880_pinmux_data = NULL; enum ralink_soc_type ralink_soc; EXPORT_SYMBOL_GPL(ralink_soc); diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/ralink/pinctrl-rt2880.c index 1f4bca854add..abe31d4d448e 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt2880.c +++ b/drivers/pinctrl/ralink/pinctrl-rt2880.c @@ -17,9 +17,9 @@ #include #include -#include #include +#include "pinmux.h" #include "../core.h" #include "../pinctrl-utils.h" @@ -311,13 +311,14 @@ static int rt2880_pinmux_pins(struct rt2880_priv *p) return 0; } -static int rt2880_pinmux_probe(struct platform_device *pdev) +int rt2880_pinmux_init(struct platform_device *pdev, + struct rt2880_pmx_group *data) { struct rt2880_priv *p; struct pinctrl_dev *dev; int err; - if (!rt2880_pinmux_data) + if (!data) return -ENOTSUPP; /* setup the private data */ @@ -327,7 +328,7 @@ static int rt2880_pinmux_probe(struct platform_device *pdev) p->dev = &pdev->dev; p->desc = &rt2880_pctrl_desc; - p->groups = rt2880_pinmux_data; + p->groups = data; platform_set_drvdata(pdev, p); /* init the device */ @@ -346,24 +347,3 @@ static int rt2880_pinmux_probe(struct platform_device *pdev) return PTR_ERR_OR_ZERO(dev); } - -static const struct of_device_id rt2880_pinmux_match[] = { - { .compatible = "ralink,rt2880-pinmux" }, - {}, -}; -MODULE_DEVICE_TABLE(of, rt2880_pinmux_match); - -static struct platform_driver rt2880_pinmux_driver = { - .probe = rt2880_pinmux_probe, - .driver = { - .name = "rt2880-pinmux", - .of_match_table = rt2880_pinmux_match, - }, -}; - -static int __init rt2880_pinmux_init(void) -{ - return platform_driver_register(&rt2880_pinmux_driver); -} - -core_initcall_sync(rt2880_pinmux_init); diff --git a/drivers/pinctrl/ralink/pinmux.h b/drivers/pinctrl/ralink/pinmux.h new file mode 100644 index 000000000000..0046abe3bcc7 --- /dev/null +++ b/drivers/pinctrl/ralink/pinmux.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2012 John Crispin + */ + +#ifndef _RT288X_PINMUX_H__ +#define _RT288X_PINMUX_H__ + +#define FUNC(name, value, pin_first, pin_count) \ + { name, value, pin_first, pin_count } + +#define GRP(_name, _func, _mask, _shift) \ + { .name = _name, .mask = _mask, .shift = _shift, \ + .func = _func, .gpio = _mask, \ + .func_count = ARRAY_SIZE(_func) } + +#define GRP_G(_name, _func, _mask, _gpio, _shift) \ + { .name = _name, .mask = _mask, .shift = _shift, \ + .func = _func, .gpio = _gpio, \ + .func_count = ARRAY_SIZE(_func) } + +struct rt2880_pmx_group; + +struct rt2880_pmx_func { + const char *name; + const char value; + + int pin_first; + int pin_count; + int *pins; + + int *groups; + int group_count; + + int enabled; +}; + +struct rt2880_pmx_group { + const char *name; + int enabled; + + const u32 shift; + const char mask; + const char gpio; + + struct rt2880_pmx_func *func; + int func_count; +}; + +int rt2880_pinmux_init(struct platform_device *pdev, + struct rt2880_pmx_group *data); + +#endif -- cgit v1.2.3 From e98dd3db96f710b5545f313c9f364a306bb35c86 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Fri, 4 Jun 2021 13:51:55 +0200 Subject: pinctrl: ralink: move MT7621 SoC pinmux config into a new 'pinctrl-mt7621.c' file Move all related code for SoC MT7621 into a new driver located in 'pinctrl-mt7621.c' source file. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210604115159.8834-3-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij --- arch/mips/ralink/mt7621.c | 88 ------------------------ drivers/pinctrl/ralink/Kconfig | 5 ++ drivers/pinctrl/ralink/Makefile | 2 + drivers/pinctrl/ralink/pinctrl-mt7621.c | 116 ++++++++++++++++++++++++++++++++ 4 files changed, 123 insertions(+), 88 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-mt7621.c diff --git a/arch/mips/ralink/mt7621.c b/arch/mips/ralink/mt7621.c index f82ad2a621f6..bd71f5b14238 100644 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c @@ -18,97 +18,10 @@ #include #include -#include - #include "common.h" -#define MT7621_GPIO_MODE_UART1 1 -#define MT7621_GPIO_MODE_I2C 2 -#define MT7621_GPIO_MODE_UART3_MASK 0x3 -#define MT7621_GPIO_MODE_UART3_SHIFT 3 -#define MT7621_GPIO_MODE_UART3_GPIO 1 -#define MT7621_GPIO_MODE_UART2_MASK 0x3 -#define MT7621_GPIO_MODE_UART2_SHIFT 5 -#define MT7621_GPIO_MODE_UART2_GPIO 1 -#define MT7621_GPIO_MODE_JTAG 7 -#define MT7621_GPIO_MODE_WDT_MASK 0x3 -#define MT7621_GPIO_MODE_WDT_SHIFT 8 -#define MT7621_GPIO_MODE_WDT_GPIO 1 -#define MT7621_GPIO_MODE_PCIE_RST 0 -#define MT7621_GPIO_MODE_PCIE_REF 2 -#define MT7621_GPIO_MODE_PCIE_MASK 0x3 -#define MT7621_GPIO_MODE_PCIE_SHIFT 10 -#define MT7621_GPIO_MODE_PCIE_GPIO 1 -#define MT7621_GPIO_MODE_MDIO_MASK 0x3 -#define MT7621_GPIO_MODE_MDIO_SHIFT 12 -#define MT7621_GPIO_MODE_MDIO_GPIO 1 -#define MT7621_GPIO_MODE_RGMII1 14 -#define MT7621_GPIO_MODE_RGMII2 15 -#define MT7621_GPIO_MODE_SPI_MASK 0x3 -#define MT7621_GPIO_MODE_SPI_SHIFT 16 -#define MT7621_GPIO_MODE_SPI_GPIO 1 -#define MT7621_GPIO_MODE_SDHCI_MASK 0x3 -#define MT7621_GPIO_MODE_SDHCI_SHIFT 18 -#define MT7621_GPIO_MODE_SDHCI_GPIO 1 - static void *detect_magic __initdata = detect_memory_region; -static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; -static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; -static struct rt2880_pmx_func uart3_grp[] = { - FUNC("uart3", 0, 5, 4), - FUNC("i2s", 2, 5, 4), - FUNC("spdif3", 3, 5, 4), -}; -static struct rt2880_pmx_func uart2_grp[] = { - FUNC("uart2", 0, 9, 4), - FUNC("pcm", 2, 9, 4), - FUNC("spdif2", 3, 9, 4), -}; -static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; -static struct rt2880_pmx_func wdt_grp[] = { - FUNC("wdt rst", 0, 18, 1), - FUNC("wdt refclk", 2, 18, 1), -}; -static struct rt2880_pmx_func pcie_rst_grp[] = { - FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), - FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) -}; -static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; -static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; -static struct rt2880_pmx_func spi_grp[] = { - FUNC("spi", 0, 34, 7), - FUNC("nand1", 2, 34, 7), -}; -static struct rt2880_pmx_func sdhci_grp[] = { - FUNC("sdhci", 0, 41, 8), - FUNC("nand2", 2, 41, 8), -}; -static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; - -static struct rt2880_pmx_group mt7621_pinmux_data[] = { - GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), - GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), - GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, - MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), - GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, - MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), - GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), - GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, - MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), - GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, - MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), - GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, - MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), - GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, - MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), - GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, - MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), - GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), - { 0 } -}; - phys_addr_t mips_cpc_default_phys_base(void) { panic("Cannot detect cpc address"); @@ -219,7 +132,6 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) (rev & CHIP_REV_ECO_MASK)); soc_info->mem_detect = mt7621_memory_detect; - rt2880_pinmux_data = mt7621_pinmux_data; soc_dev_init(soc_info, rev); diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 8c5f6341477f..ef8990a4c1eb 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -11,4 +11,9 @@ config PINCTRL_RT2880 select PINMUX select GENERIC_PINCONF +config PINCTRL_MT7621 + bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs" + depends on RALINK && SOC_MT7621 + select PINCTRL_RT2880 + endmenu diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 242554298d07..470855290ff6 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -1,2 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o + +obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7621.c b/drivers/pinctrl/ralink/pinctrl-mt7621.c new file mode 100644 index 000000000000..7d96144c474e --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-mt7621.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include "pinmux.h" + +#define MT7621_GPIO_MODE_UART1 1 +#define MT7621_GPIO_MODE_I2C 2 +#define MT7621_GPIO_MODE_UART3_MASK 0x3 +#define MT7621_GPIO_MODE_UART3_SHIFT 3 +#define MT7621_GPIO_MODE_UART3_GPIO 1 +#define MT7621_GPIO_MODE_UART2_MASK 0x3 +#define MT7621_GPIO_MODE_UART2_SHIFT 5 +#define MT7621_GPIO_MODE_UART2_GPIO 1 +#define MT7621_GPIO_MODE_JTAG 7 +#define MT7621_GPIO_MODE_WDT_MASK 0x3 +#define MT7621_GPIO_MODE_WDT_SHIFT 8 +#define MT7621_GPIO_MODE_WDT_GPIO 1 +#define MT7621_GPIO_MODE_PCIE_RST 0 +#define MT7621_GPIO_MODE_PCIE_REF 2 +#define MT7621_GPIO_MODE_PCIE_MASK 0x3 +#define MT7621_GPIO_MODE_PCIE_SHIFT 10 +#define MT7621_GPIO_MODE_PCIE_GPIO 1 +#define MT7621_GPIO_MODE_MDIO_MASK 0x3 +#define MT7621_GPIO_MODE_MDIO_SHIFT 12 +#define MT7621_GPIO_MODE_MDIO_GPIO 1 +#define MT7621_GPIO_MODE_RGMII1 14 +#define MT7621_GPIO_MODE_RGMII2 15 +#define MT7621_GPIO_MODE_SPI_MASK 0x3 +#define MT7621_GPIO_MODE_SPI_SHIFT 16 +#define MT7621_GPIO_MODE_SPI_GPIO 1 +#define MT7621_GPIO_MODE_SDHCI_MASK 0x3 +#define MT7621_GPIO_MODE_SDHCI_SHIFT 18 +#define MT7621_GPIO_MODE_SDHCI_GPIO 1 + +static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; +static struct rt2880_pmx_func uart3_grp[] = { + FUNC("uart3", 0, 5, 4), + FUNC("i2s", 2, 5, 4), + FUNC("spdif3", 3, 5, 4), +}; +static struct rt2880_pmx_func uart2_grp[] = { + FUNC("uart2", 0, 9, 4), + FUNC("pcm", 2, 9, 4), + FUNC("spdif2", 3, 9, 4), +}; +static struct rt2880_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) }; +static struct rt2880_pmx_func wdt_grp[] = { + FUNC("wdt rst", 0, 18, 1), + FUNC("wdt refclk", 2, 18, 1), +}; +static struct rt2880_pmx_func pcie_rst_grp[] = { + FUNC("pcie rst", MT7621_GPIO_MODE_PCIE_RST, 19, 1), + FUNC("pcie refclk", MT7621_GPIO_MODE_PCIE_REF, 19, 1) +}; +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 20, 2) }; +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 22, 12) }; +static struct rt2880_pmx_func spi_grp[] = { + FUNC("spi", 0, 34, 7), + FUNC("nand1", 2, 34, 7), +}; +static struct rt2880_pmx_func sdhci_grp[] = { + FUNC("sdhci", 0, 41, 8), + FUNC("nand2", 2, 41, 8), +}; +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 49, 12) }; + +static struct rt2880_pmx_group mt7621_pinmux_data[] = { + GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1), + GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C), + GRP_G("uart3", uart3_grp, MT7621_GPIO_MODE_UART3_MASK, + MT7621_GPIO_MODE_UART3_GPIO, MT7621_GPIO_MODE_UART3_SHIFT), + GRP_G("uart2", uart2_grp, MT7621_GPIO_MODE_UART2_MASK, + MT7621_GPIO_MODE_UART2_GPIO, MT7621_GPIO_MODE_UART2_SHIFT), + GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG), + GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK, + MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT), + GRP_G("pcie", pcie_rst_grp, MT7621_GPIO_MODE_PCIE_MASK, + MT7621_GPIO_MODE_PCIE_GPIO, MT7621_GPIO_MODE_PCIE_SHIFT), + GRP_G("mdio", mdio_grp, MT7621_GPIO_MODE_MDIO_MASK, + MT7621_GPIO_MODE_MDIO_GPIO, MT7621_GPIO_MODE_MDIO_SHIFT), + GRP("rgmii2", rgmii2_grp, 1, MT7621_GPIO_MODE_RGMII2), + GRP_G("spi", spi_grp, MT7621_GPIO_MODE_SPI_MASK, + MT7621_GPIO_MODE_SPI_GPIO, MT7621_GPIO_MODE_SPI_SHIFT), + GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK, + MT7621_GPIO_MODE_SDHCI_GPIO, MT7621_GPIO_MODE_SDHCI_SHIFT), + GRP("rgmii1", rgmii1_grp, 1, MT7621_GPIO_MODE_RGMII1), + { 0 } +}; + +static int mt7621_pinmux_probe(struct platform_device *pdev) +{ + return rt2880_pinmux_init(pdev, mt7621_pinmux_data); +} + +static const struct of_device_id mt7621_pinmux_match[] = { + { .compatible = "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, mt7621_pinmux_match); + +static struct platform_driver mt7621_pinmux_driver = { + .probe = mt7621_pinmux_probe, + .driver = { + .name = "rt2880-pinmux", + .of_match_table = mt7621_pinmux_match, + }, +}; + +static int __init mt7621_pinmux_init(void) +{ + return platform_driver_register(&mt7621_pinmux_driver); +} +core_initcall_sync(mt7621_pinmux_init); -- cgit v1.2.3 From 8b8b0fa21dfa9e0222199b32e9c684d1aa2649af Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Fri, 4 Jun 2021 13:51:56 +0200 Subject: pinctrl: ralink: move RT3883 SoC pinmux config into a new 'pinctrl-rt3883.c' file Move all related code for SoC RT3883 into a new driver located in 'pinctrl-rt3883.c' source file Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210604115159.8834-4-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij --- arch/mips/include/asm/mach-ralink/rt3883.h | 34 --------- arch/mips/ralink/rt3883.c | 45 ------------ drivers/pinctrl/ralink/Kconfig | 5 ++ drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-rt3883.c | 107 +++++++++++++++++++++++++++++ 5 files changed, 113 insertions(+), 79 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-rt3883.c diff --git a/arch/mips/include/asm/mach-ralink/rt3883.h b/arch/mips/include/asm/mach-ralink/rt3883.h index 565f2548496a..f250de9c055b 100644 --- a/arch/mips/include/asm/mach-ralink/rt3883.h +++ b/arch/mips/include/asm/mach-ralink/rt3883.h @@ -109,40 +109,6 @@ #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19) #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18) -#define RT3883_GPIO_MODE_UART0_SHIFT 2 -#define RT3883_GPIO_MODE_UART0_MASK 0x7 -#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) -#define RT3883_GPIO_MODE_UARTF 0x0 -#define RT3883_GPIO_MODE_PCM_UARTF 0x1 -#define RT3883_GPIO_MODE_PCM_I2S 0x2 -#define RT3883_GPIO_MODE_I2S_UARTF 0x3 -#define RT3883_GPIO_MODE_PCM_GPIO 0x4 -#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 -#define RT3883_GPIO_MODE_GPIO_I2S 0x6 -#define RT3883_GPIO_MODE_GPIO 0x7 - -#define RT3883_GPIO_MODE_I2C 0 -#define RT3883_GPIO_MODE_SPI 1 -#define RT3883_GPIO_MODE_UART1 5 -#define RT3883_GPIO_MODE_JTAG 6 -#define RT3883_GPIO_MODE_MDIO 7 -#define RT3883_GPIO_MODE_GE1 9 -#define RT3883_GPIO_MODE_GE2 10 - -#define RT3883_GPIO_MODE_PCI_SHIFT 11 -#define RT3883_GPIO_MODE_PCI_MASK 0x7 -#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT) -#define RT3883_GPIO_MODE_LNA_A_SHIFT 16 -#define RT3883_GPIO_MODE_LNA_A_MASK 0x3 -#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT) -#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3 -#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK) -#define RT3883_GPIO_MODE_LNA_G_SHIFT 18 -#define RT3883_GPIO_MODE_LNA_G_MASK 0x3 -#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT) -#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 -#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) - #define RT3883_GPIO_I2C_SD 1 #define RT3883_GPIO_I2C_SCLK 2 #define RT3883_GPIO_SPI_CS0 3 diff --git a/arch/mips/ralink/rt3883.c b/arch/mips/ralink/rt3883.c index ff91f3531ad0..d9875f146d66 100644 --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c @@ -14,52 +14,9 @@ #include #include #include -#include #include "common.h" -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartf_func[] = { - FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), - FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), - FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), - FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8), - FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4), - FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), - FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), -}; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) }; -static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) }; -static struct rt2880_pmx_func pci_func[] = { - FUNC("pci-dev", 0, 40, 32), - FUNC("pci-host2", 1, 40, 32), - FUNC("pci-host1", 2, 40, 32), - FUNC("pci-fnc", 3, 40, 32) -}; -static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) }; -static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) }; - -static struct rt2880_pmx_group rt3883_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK, - RT3883_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO), - GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A), - GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G), - GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK, - RT3883_GPIO_MODE_PCI_SHIFT), - GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1), - GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2), - { 0 } -}; - void __init ralink_clk_init(void) { unsigned long cpu_rate, sys_rate; @@ -142,7 +99,5 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_min = RT3883_MEM_SIZE_MIN; soc_info->mem_size_max = RT3883_MEM_SIZE_MAX; - rt2880_pinmux_data = rt3883_pinmux_data; - ralink_soc = RT3883_SOC; } diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index ef8990a4c1eb..6f5fb3dc0a41 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -16,4 +16,9 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RT2880 +config PINCTRL_RT3883 + bool "RT3883 pinctrl driver for RALINK/Mediatek SOCs" + depends on RALINK && SOC_RT3883 + select PINCTRL_RT2880 + endmenu diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 470855290ff6..86d6f8253afa 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-rt3883.c b/drivers/pinctrl/ralink/pinctrl-rt3883.c new file mode 100644 index 000000000000..3e0e1b4caa64 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-rt3883.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include "pinmux.h" + +#define RT3883_GPIO_MODE_UART0_SHIFT 2 +#define RT3883_GPIO_MODE_UART0_MASK 0x7 +#define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT) +#define RT3883_GPIO_MODE_UARTF 0x0 +#define RT3883_GPIO_MODE_PCM_UARTF 0x1 +#define RT3883_GPIO_MODE_PCM_I2S 0x2 +#define RT3883_GPIO_MODE_I2S_UARTF 0x3 +#define RT3883_GPIO_MODE_PCM_GPIO 0x4 +#define RT3883_GPIO_MODE_GPIO_UARTF 0x5 +#define RT3883_GPIO_MODE_GPIO_I2S 0x6 +#define RT3883_GPIO_MODE_GPIO 0x7 + +#define RT3883_GPIO_MODE_I2C 0 +#define RT3883_GPIO_MODE_SPI 1 +#define RT3883_GPIO_MODE_UART1 5 +#define RT3883_GPIO_MODE_JTAG 6 +#define RT3883_GPIO_MODE_MDIO 7 +#define RT3883_GPIO_MODE_GE1 9 +#define RT3883_GPIO_MODE_GE2 10 + +#define RT3883_GPIO_MODE_PCI_SHIFT 11 +#define RT3883_GPIO_MODE_PCI_MASK 0x7 +#define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT) +#define RT3883_GPIO_MODE_LNA_A_SHIFT 16 +#define RT3883_GPIO_MODE_LNA_A_MASK 0x3 +#define _RT3883_GPIO_MODE_LNA_A(_x) ((_x) << RT3883_GPIO_MODE_LNA_A_SHIFT) +#define RT3883_GPIO_MODE_LNA_A_GPIO 0x3 +#define RT3883_GPIO_MODE_LNA_A _RT3883_GPIO_MODE_LNA_A(RT3883_GPIO_MODE_LNA_A_MASK) +#define RT3883_GPIO_MODE_LNA_G_SHIFT 18 +#define RT3883_GPIO_MODE_LNA_G_MASK 0x3 +#define _RT3883_GPIO_MODE_LNA_G(_x) ((_x) << RT3883_GPIO_MODE_LNA_G_SHIFT) +#define RT3883_GPIO_MODE_LNA_G_GPIO 0x3 +#define RT3883_GPIO_MODE_LNA_G _RT3883_GPIO_MODE_LNA_G(RT3883_GPIO_MODE_LNA_G_MASK) + +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; +static struct rt2880_pmx_func uartf_func[] = { + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8), + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8), + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8), + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8), + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4), + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4), + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4), +}; +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) }; +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna g", 0, 35, 3) }; +static struct rt2880_pmx_func pci_func[] = { + FUNC("pci-dev", 0, 40, 32), + FUNC("pci-host2", 1, 40, 32), + FUNC("pci-host1", 2, 40, 32), + FUNC("pci-fnc", 3, 40, 32) +}; +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) }; +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge2", 0, 84, 12) }; + +static struct rt2880_pmx_group rt3883_pinmux_data[] = { + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C), + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI), + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK, + RT3883_GPIO_MODE_UART0_SHIFT), + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1), + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG), + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO), + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A), + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G), + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK, + RT3883_GPIO_MODE_PCI_SHIFT), + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1), + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2), + { 0 } +}; + +static int rt3883_pinmux_probe(struct platform_device *pdev) +{ + return rt2880_pinmux_init(pdev, rt3883_pinmux_data); +} + +static const struct of_device_id rt3883_pinmux_match[] = { + { .compatible = "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, rt3883_pinmux_match); + +static struct platform_driver rt3883_pinmux_driver = { + .probe = rt3883_pinmux_probe, + .driver = { + .name = "rt2880-pinmux", + .of_match_table = rt3883_pinmux_match, + }, +}; + +static int __init rt3883_pinmux_init(void) +{ + return platform_driver_register(&rt3883_pinmux_driver); +} +core_initcall_sync(rt3883_pinmux_init); -- cgit v1.2.3 From 3a1b0ca5a83b69f95ab9641ae0e77526a6fee384 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Fri, 4 Jun 2021 13:51:57 +0200 Subject: pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file Move all related code for SoC RT305X into a new driver located in 'pinctrl-rt305x.c' source file. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210604115159.8834-5-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij --- arch/mips/include/asm/mach-ralink/rt305x.h | 24 ----- arch/mips/ralink/rt305x.c | 77 ---------------- drivers/pinctrl/ralink/Kconfig | 5 ++ drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-rt305x.c | 136 +++++++++++++++++++++++++++++ 5 files changed, 142 insertions(+), 101 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-rt305x.c diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h index b54619dc4b88..4d8e8c8d83ce 100644 --- a/arch/mips/include/asm/mach-ralink/rt305x.h +++ b/arch/mips/include/asm/mach-ralink/rt305x.h @@ -114,30 +114,6 @@ static inline int soc_is_rt5350(void) #define RT305X_GPIO_GE0_TXD0 40 #define RT305X_GPIO_GE0_RXCLK 51 -#define RT305X_GPIO_MODE_UART0_SHIFT 2 -#define RT305X_GPIO_MODE_UART0_MASK 0x7 -#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) -#define RT305X_GPIO_MODE_UARTF 0 -#define RT305X_GPIO_MODE_PCM_UARTF 1 -#define RT305X_GPIO_MODE_PCM_I2S 2 -#define RT305X_GPIO_MODE_I2S_UARTF 3 -#define RT305X_GPIO_MODE_PCM_GPIO 4 -#define RT305X_GPIO_MODE_GPIO_UARTF 5 -#define RT305X_GPIO_MODE_GPIO_I2S 6 -#define RT305X_GPIO_MODE_GPIO 7 - -#define RT305X_GPIO_MODE_I2C 0 -#define RT305X_GPIO_MODE_SPI 1 -#define RT305X_GPIO_MODE_UART1 5 -#define RT305X_GPIO_MODE_JTAG 6 -#define RT305X_GPIO_MODE_MDIO 7 -#define RT305X_GPIO_MODE_SDRAM 8 -#define RT305X_GPIO_MODE_RGMII 9 -#define RT5350_GPIO_MODE_PHY_LED 14 -#define RT5350_GPIO_MODE_SPI_CS1 21 -#define RT3352_GPIO_MODE_LNA 18 -#define RT3352_GPIO_MODE_PA 20 - #define RT3352_SYSC_REG_SYSCFG0 0x010 #define RT3352_SYSC_REG_SYSCFG1 0x014 #define RT3352_SYSC_REG_CLKCFG1 0x030 diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c index c5b63c142705..8b095a9dcb15 100644 --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c @@ -16,83 +16,9 @@ #include #include #include -#include #include "common.h" -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartf_func[] = { - FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), - FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), - FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), - FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8), - FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4), - FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), - FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), -}; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; -static struct rt2880_pmx_func rt5350_cs1_func[] = { - FUNC("spi_cs1", 0, 27, 1), - FUNC("wdg_cs1", 1, 27, 1), -}; -static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct rt2880_pmx_func rt3352_rgmii_func[] = { - FUNC("rgmii", 0, 24, 12) -}; -static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; -static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; -static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; -static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; -static struct rt2880_pmx_func rt3352_cs1_func[] = { - FUNC("spi_cs1", 0, 45, 1), - FUNC("wdg_cs1", 1, 45, 1), -}; - -static struct rt2880_pmx_group rt3050_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, - RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), - GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), - GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM), - { 0 } -}; - -static struct rt2880_pmx_group rt3352_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, - RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), - GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), - GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), - GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), - GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), - GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), - { 0 } -}; - -static struct rt2880_pmx_group rt5350_pinmux_data[] = { - GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), - GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, - RT305X_GPIO_MODE_UART0_SHIFT), - GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), - GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), - GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED), - GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), - { 0 } -}; - static unsigned long rt5350_get_mem_size(void) { void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE); @@ -265,14 +191,11 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_base = RT305X_SDRAM_BASE; if (soc_is_rt5350()) { soc_info->mem_size = rt5350_get_mem_size(); - rt2880_pinmux_data = rt5350_pinmux_data; } else if (soc_is_rt305x() || soc_is_rt3350()) { soc_info->mem_size_min = RT305X_MEM_SIZE_MIN; soc_info->mem_size_max = RT305X_MEM_SIZE_MAX; - rt2880_pinmux_data = rt3050_pinmux_data; } else if (soc_is_rt3352()) { soc_info->mem_size_min = RT3352_MEM_SIZE_MIN; soc_info->mem_size_max = RT3352_MEM_SIZE_MAX; - rt2880_pinmux_data = rt3352_pinmux_data; } } diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 6f5fb3dc0a41..705a63d34d3c 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -16,6 +16,11 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RT2880 +config PINCTRL_RT305X + bool "RT305X pinctrl driver for RALINK/Mediatek SOCs" + depends on RALINK && SOC_RT305X + select PINCTRL_RT2880 + config PINCTRL_RT3883 bool "RT3883 pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_RT3883 diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 86d6f8253afa..119d30ecea98 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -2,4 +2,5 @@ obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c new file mode 100644 index 000000000000..699fe18e7000 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include "pinmux.h" + +#define RT305X_GPIO_MODE_UART0_SHIFT 2 +#define RT305X_GPIO_MODE_UART0_MASK 0x7 +#define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT) +#define RT305X_GPIO_MODE_UARTF 0 +#define RT305X_GPIO_MODE_PCM_UARTF 1 +#define RT305X_GPIO_MODE_PCM_I2S 2 +#define RT305X_GPIO_MODE_I2S_UARTF 3 +#define RT305X_GPIO_MODE_PCM_GPIO 4 +#define RT305X_GPIO_MODE_GPIO_UARTF 5 +#define RT305X_GPIO_MODE_GPIO_I2S 6 +#define RT305X_GPIO_MODE_GPIO 7 + +#define RT305X_GPIO_MODE_I2C 0 +#define RT305X_GPIO_MODE_SPI 1 +#define RT305X_GPIO_MODE_UART1 5 +#define RT305X_GPIO_MODE_JTAG 6 +#define RT305X_GPIO_MODE_MDIO 7 +#define RT305X_GPIO_MODE_SDRAM 8 +#define RT305X_GPIO_MODE_RGMII 9 +#define RT5350_GPIO_MODE_PHY_LED 14 +#define RT5350_GPIO_MODE_SPI_CS1 21 +#define RT3352_GPIO_MODE_LNA 18 +#define RT3352_GPIO_MODE_PA 20 + +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; +static struct rt2880_pmx_func uartf_func[] = { + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8), + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8), + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8), + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8), + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4), + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4), + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4), +}; +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) }; +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) }; +static struct rt2880_pmx_func rt5350_cs1_func[] = { + FUNC("spi_cs1", 0, 27, 1), + FUNC("wdg_cs1", 1, 27, 1), +}; +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; +static struct rt2880_pmx_func rt3352_rgmii_func[] = { + FUNC("rgmii", 0, 24, 12) +}; +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) }; +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) }; +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) }; +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) }; +static struct rt2880_pmx_func rt3352_cs1_func[] = { + FUNC("spi_cs1", 0, 45, 1), + FUNC("wdg_cs1", 1, 45, 1), +}; + +static struct rt2880_pmx_group rt3050_pinmux_data[] = { + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, + RT305X_GPIO_MODE_UART0_SHIFT), + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII), + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM), + { 0 } +}; + +static struct rt2880_pmx_group rt3352_pinmux_data[] = { + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, + RT305X_GPIO_MODE_UART0_SHIFT), + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO), + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII), + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA), + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA), + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED), + GRP("spi_cs1", rt3352_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), + { 0 } +}; + +static struct rt2880_pmx_group rt5350_pinmux_data[] = { + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C), + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI), + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK, + RT305X_GPIO_MODE_UART0_SHIFT), + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1), + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG), + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED), + GRP("spi_cs1", rt5350_cs1_func, 2, RT5350_GPIO_MODE_SPI_CS1), + { 0 } +}; + +static int rt305x_pinmux_probe(struct platform_device *pdev) +{ + if (soc_is_rt5350()) + return rt2880_pinmux_init(pdev, rt5350_pinmux_data); + else if (soc_is_rt305x() || soc_is_rt3350()) + return rt2880_pinmux_init(pdev, rt3050_pinmux_data); + else if (soc_is_rt3352()) + return rt2880_pinmux_init(pdev, rt3352_pinmux_data); + else + return -EINVAL; +} + +static const struct of_device_id rt305x_pinmux_match[] = { + { .compatible = "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, rt305x_pinmux_match); + +static struct platform_driver rt305x_pinmux_driver = { + .probe = rt305x_pinmux_probe, + .driver = { + .name = "rt2880-pinmux", + .of_match_table = rt305x_pinmux_match, + }, +}; + +static int __init rt305x_pinmux_init(void) +{ + return platform_driver_register(&rt305x_pinmux_driver); +} +core_initcall_sync(rt305x_pinmux_init); -- cgit v1.2.3 From 745ec436de7223fbe086be5123fe3014c4220611 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Fri, 4 Jun 2021 13:51:58 +0200 Subject: pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file Move all related code for SoC MT7620 into a new driver located in 'pinctrl-mt7620.c' source file. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210604115159.8834-6-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij --- arch/mips/include/asm/mach-ralink/mt7620.h | 53 +--- arch/mips/ralink/mt7620.c | 320 ----------------------- drivers/pinctrl/ralink/Kconfig | 5 + drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-mt7620.c | 390 +++++++++++++++++++++++++++++ 5 files changed, 403 insertions(+), 366 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-mt7620.c diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h index 757ce53d00e6..d51dfad8f543 100644 --- a/arch/mips/include/asm/mach-ralink/mt7620.h +++ b/arch/mips/include/asm/mach-ralink/mt7620.h @@ -83,52 +83,13 @@ #define MT7620_DDR2_SIZE_MIN 32 #define MT7620_DDR2_SIZE_MAX 256 -#define MT7620_GPIO_MODE_UART0_SHIFT 2 -#define MT7620_GPIO_MODE_UART0_MASK 0x7 -#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) -#define MT7620_GPIO_MODE_UARTF 0x0 -#define MT7620_GPIO_MODE_PCM_UARTF 0x1 -#define MT7620_GPIO_MODE_PCM_I2S 0x2 -#define MT7620_GPIO_MODE_I2S_UARTF 0x3 -#define MT7620_GPIO_MODE_PCM_GPIO 0x4 -#define MT7620_GPIO_MODE_GPIO_UARTF 0x5 -#define MT7620_GPIO_MODE_GPIO_I2S 0x6 -#define MT7620_GPIO_MODE_GPIO 0x7 - -#define MT7620_GPIO_MODE_NAND 0 -#define MT7620_GPIO_MODE_SD 1 -#define MT7620_GPIO_MODE_ND_SD_GPIO 2 -#define MT7620_GPIO_MODE_ND_SD_MASK 0x3 -#define MT7620_GPIO_MODE_ND_SD_SHIFT 18 - -#define MT7620_GPIO_MODE_PCIE_RST 0 -#define MT7620_GPIO_MODE_PCIE_REF 1 -#define MT7620_GPIO_MODE_PCIE_GPIO 2 -#define MT7620_GPIO_MODE_PCIE_MASK 0x3 -#define MT7620_GPIO_MODE_PCIE_SHIFT 16 - -#define MT7620_GPIO_MODE_WDT_RST 0 -#define MT7620_GPIO_MODE_WDT_REF 1 -#define MT7620_GPIO_MODE_WDT_GPIO 2 -#define MT7620_GPIO_MODE_WDT_MASK 0x3 -#define MT7620_GPIO_MODE_WDT_SHIFT 21 - -#define MT7620_GPIO_MODE_MDIO 0 -#define MT7620_GPIO_MODE_MDIO_REFCLK 1 -#define MT7620_GPIO_MODE_MDIO_GPIO 2 -#define MT7620_GPIO_MODE_MDIO_MASK 0x3 -#define MT7620_GPIO_MODE_MDIO_SHIFT 7 - -#define MT7620_GPIO_MODE_I2C 0 -#define MT7620_GPIO_MODE_UART1 5 -#define MT7620_GPIO_MODE_RGMII1 9 -#define MT7620_GPIO_MODE_RGMII2 10 -#define MT7620_GPIO_MODE_SPI 11 -#define MT7620_GPIO_MODE_SPI_REF_CLK 12 -#define MT7620_GPIO_MODE_WLED 13 -#define MT7620_GPIO_MODE_JTAG 15 -#define MT7620_GPIO_MODE_EPHY 15 -#define MT7620_GPIO_MODE_PA 20 +extern enum ralink_soc_type ralink_soc; + +static inline int is_mt76x8(void) +{ + return ralink_soc == MT762X_SOC_MT7628AN || + ralink_soc == MT762X_SOC_MT7688; +} static inline int mt7620_get_eco(void) { diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 53a5969e61af..ae1fa0391c88 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "common.h" @@ -50,320 +49,6 @@ /* does the board have sdram or ddram */ static int dram_type; -static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; -static struct rt2880_pmx_func mdio_grp[] = { - FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), - FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), -}; -static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; -static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; -static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; -static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; -static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; -static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; -static struct rt2880_pmx_func uartf_grp[] = { - FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), - FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), - FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), - FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), - FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), - FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), - FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), -}; -static struct rt2880_pmx_func wdt_grp[] = { - FUNC("wdt rst", 0, 17, 1), - FUNC("wdt refclk", 0, 17, 1), - }; -static struct rt2880_pmx_func pcie_rst_grp[] = { - FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), - FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) -}; -static struct rt2880_pmx_func nd_sd_grp[] = { - FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), - FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) -}; - -static struct rt2880_pmx_group mt7620a_pinmux_data[] = { - GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), - GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, - MT7620_GPIO_MODE_UART0_SHIFT), - GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), - GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), - GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, - MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), - GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, - MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), - GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), - GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), - GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, - MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), - GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, - MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), - GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), - GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), - GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), - GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), - { 0 } -}; - -static struct rt2880_pmx_func pwm1_grp_mt7628[] = { - FUNC("sdxc d6", 3, 19, 1), - FUNC("utif", 2, 19, 1), - FUNC("gpio", 1, 19, 1), - FUNC("pwm1", 0, 19, 1), -}; - -static struct rt2880_pmx_func pwm0_grp_mt7628[] = { - FUNC("sdxc d7", 3, 18, 1), - FUNC("utif", 2, 18, 1), - FUNC("gpio", 1, 18, 1), - FUNC("pwm0", 0, 18, 1), -}; - -static struct rt2880_pmx_func uart2_grp_mt7628[] = { - FUNC("sdxc d5 d4", 3, 20, 2), - FUNC("pwm", 2, 20, 2), - FUNC("gpio", 1, 20, 2), - FUNC("uart2", 0, 20, 2), -}; - -static struct rt2880_pmx_func uart1_grp_mt7628[] = { - FUNC("sw_r", 3, 45, 2), - FUNC("pwm", 2, 45, 2), - FUNC("gpio", 1, 45, 2), - FUNC("uart1", 0, 45, 2), -}; - -static struct rt2880_pmx_func i2c_grp_mt7628[] = { - FUNC("-", 3, 4, 2), - FUNC("debug", 2, 4, 2), - FUNC("gpio", 1, 4, 2), - FUNC("i2c", 0, 4, 2), -}; - -static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) }; -static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) }; -static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; -static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; - -static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { - FUNC("jtag", 3, 22, 8), - FUNC("utif", 2, 22, 8), - FUNC("gpio", 1, 22, 8), - FUNC("sdxc", 0, 22, 8), -}; - -static struct rt2880_pmx_func uart0_grp_mt7628[] = { - FUNC("-", 3, 12, 2), - FUNC("-", 2, 12, 2), - FUNC("gpio", 1, 12, 2), - FUNC("uart0", 0, 12, 2), -}; - -static struct rt2880_pmx_func i2s_grp_mt7628[] = { - FUNC("antenna", 3, 0, 4), - FUNC("pcm", 2, 0, 4), - FUNC("gpio", 1, 0, 4), - FUNC("i2s", 0, 0, 4), -}; - -static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { - FUNC("-", 3, 6, 1), - FUNC("refclk", 2, 6, 1), - FUNC("gpio", 1, 6, 1), - FUNC("spi cs1", 0, 6, 1), -}; - -static struct rt2880_pmx_func spis_grp_mt7628[] = { - FUNC("pwm_uart2", 3, 14, 4), - FUNC("utif", 2, 14, 4), - FUNC("gpio", 1, 14, 4), - FUNC("spis", 0, 14, 4), -}; - -static struct rt2880_pmx_func gpio_grp_mt7628[] = { - FUNC("pcie", 3, 11, 1), - FUNC("refclk", 2, 11, 1), - FUNC("gpio", 1, 11, 1), - FUNC("gpio", 0, 11, 1), -}; - -static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 30, 1), - FUNC("utif", 2, 30, 1), - FUNC("gpio", 1, 30, 1), - FUNC("p4led_kn", 0, 30, 1), -}; - -static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 31, 1), - FUNC("utif", 2, 31, 1), - FUNC("gpio", 1, 31, 1), - FUNC("p3led_kn", 0, 31, 1), -}; - -static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 32, 1), - FUNC("utif", 2, 32, 1), - FUNC("gpio", 1, 32, 1), - FUNC("p2led_kn", 0, 32, 1), -}; - -static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 33, 1), - FUNC("utif", 2, 33, 1), - FUNC("gpio", 1, 33, 1), - FUNC("p1led_kn", 0, 33, 1), -}; - -static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = { - FUNC("jtag", 3, 34, 1), - FUNC("rsvd", 2, 34, 1), - FUNC("gpio", 1, 34, 1), - FUNC("p0led_kn", 0, 34, 1), -}; - -static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { - FUNC("rsvd", 3, 35, 1), - FUNC("rsvd", 2, 35, 1), - FUNC("gpio", 1, 35, 1), - FUNC("wled_kn", 0, 35, 1), -}; - -static struct rt2880_pmx_func p4led_an_grp_mt7628[] = { - FUNC("jtag", 3, 39, 1), - FUNC("utif", 2, 39, 1), - FUNC("gpio", 1, 39, 1), - FUNC("p4led_an", 0, 39, 1), -}; - -static struct rt2880_pmx_func p3led_an_grp_mt7628[] = { - FUNC("jtag", 3, 40, 1), - FUNC("utif", 2, 40, 1), - FUNC("gpio", 1, 40, 1), - FUNC("p3led_an", 0, 40, 1), -}; - -static struct rt2880_pmx_func p2led_an_grp_mt7628[] = { - FUNC("jtag", 3, 41, 1), - FUNC("utif", 2, 41, 1), - FUNC("gpio", 1, 41, 1), - FUNC("p2led_an", 0, 41, 1), -}; - -static struct rt2880_pmx_func p1led_an_grp_mt7628[] = { - FUNC("jtag", 3, 42, 1), - FUNC("utif", 2, 42, 1), - FUNC("gpio", 1, 42, 1), - FUNC("p1led_an", 0, 42, 1), -}; - -static struct rt2880_pmx_func p0led_an_grp_mt7628[] = { - FUNC("jtag", 3, 43, 1), - FUNC("rsvd", 2, 43, 1), - FUNC("gpio", 1, 43, 1), - FUNC("p0led_an", 0, 43, 1), -}; - -static struct rt2880_pmx_func wled_an_grp_mt7628[] = { - FUNC("rsvd", 3, 44, 1), - FUNC("rsvd", 2, 44, 1), - FUNC("gpio", 1, 44, 1), - FUNC("wled_an", 0, 44, 1), -}; - -#define MT7628_GPIO_MODE_MASK 0x3 - -#define MT7628_GPIO_MODE_P4LED_KN 58 -#define MT7628_GPIO_MODE_P3LED_KN 56 -#define MT7628_GPIO_MODE_P2LED_KN 54 -#define MT7628_GPIO_MODE_P1LED_KN 52 -#define MT7628_GPIO_MODE_P0LED_KN 50 -#define MT7628_GPIO_MODE_WLED_KN 48 -#define MT7628_GPIO_MODE_P4LED_AN 42 -#define MT7628_GPIO_MODE_P3LED_AN 40 -#define MT7628_GPIO_MODE_P2LED_AN 38 -#define MT7628_GPIO_MODE_P1LED_AN 36 -#define MT7628_GPIO_MODE_P0LED_AN 34 -#define MT7628_GPIO_MODE_WLED_AN 32 -#define MT7628_GPIO_MODE_PWM1 30 -#define MT7628_GPIO_MODE_PWM0 28 -#define MT7628_GPIO_MODE_UART2 26 -#define MT7628_GPIO_MODE_UART1 24 -#define MT7628_GPIO_MODE_I2C 20 -#define MT7628_GPIO_MODE_REFCLK 18 -#define MT7628_GPIO_MODE_PERST 16 -#define MT7628_GPIO_MODE_WDT 14 -#define MT7628_GPIO_MODE_SPI 12 -#define MT7628_GPIO_MODE_SDMODE 10 -#define MT7628_GPIO_MODE_UART0 8 -#define MT7628_GPIO_MODE_I2S 6 -#define MT7628_GPIO_MODE_CS1 4 -#define MT7628_GPIO_MODE_SPIS 2 -#define MT7628_GPIO_MODE_GPIO 0 - -static struct rt2880_pmx_group mt7628an_pinmux_data[] = { - GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_PWM1), - GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_PWM0), - GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART2), - GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART1), - GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_I2C), - GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), - GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), - GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), - GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), - GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_SDMODE), - GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_UART0), - GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_I2S), - GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_CS1), - GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_SPIS), - GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_GPIO), - GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_WLED_AN), - GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P0LED_AN), - GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P1LED_AN), - GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P2LED_AN), - GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P3LED_AN), - GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P4LED_AN), - GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_WLED_KN), - GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P0LED_KN), - GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P1LED_KN), - GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P2LED_KN), - GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P3LED_KN), - GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, - 1, MT7628_GPIO_MODE_P4LED_KN), - { 0 } -}; - -static inline int is_mt76x8(void) -{ - return ralink_soc == MT762X_SOC_MT7628AN || - ralink_soc == MT762X_SOC_MT7688; -} - static __init u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div) { @@ -710,9 +395,4 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) (pmu0 & PMU_SW_SET) ? ("sw") : ("hw")); pr_info("Digital PMU set to %s control\n", (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw")); - - if (is_mt76x8()) - rt2880_pinmux_data = mt7628an_pinmux_data; - else - rt2880_pinmux_data = mt7620a_pinmux_data; } diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 705a63d34d3c..6edf0589cf0a 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -11,6 +11,11 @@ config PINCTRL_RT2880 select PINMUX select GENERIC_PINCONF +config PINCTRL_MT7620 + bool "mt7620 pinctrl driver for RALINK/Mediatek SOCs" + depends on RALINK && SOC_MT7620 + select PINCTRL_RT2880 + config PINCTRL_MT7621 bool "mt7621 pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_MT7621 diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 119d30ecea98..9b99b20e51e6 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o +obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-mt7620.c b/drivers/pinctrl/ralink/pinctrl-mt7620.c new file mode 100644 index 000000000000..425d55a2ee19 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-mt7620.c @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include "pinmux.h" + +#define MT7620_GPIO_MODE_UART0_SHIFT 2 +#define MT7620_GPIO_MODE_UART0_MASK 0x7 +#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT) +#define MT7620_GPIO_MODE_UARTF 0x0 +#define MT7620_GPIO_MODE_PCM_UARTF 0x1 +#define MT7620_GPIO_MODE_PCM_I2S 0x2 +#define MT7620_GPIO_MODE_I2S_UARTF 0x3 +#define MT7620_GPIO_MODE_PCM_GPIO 0x4 +#define MT7620_GPIO_MODE_GPIO_UARTF 0x5 +#define MT7620_GPIO_MODE_GPIO_I2S 0x6 +#define MT7620_GPIO_MODE_GPIO 0x7 + +#define MT7620_GPIO_MODE_NAND 0 +#define MT7620_GPIO_MODE_SD 1 +#define MT7620_GPIO_MODE_ND_SD_GPIO 2 +#define MT7620_GPIO_MODE_ND_SD_MASK 0x3 +#define MT7620_GPIO_MODE_ND_SD_SHIFT 18 + +#define MT7620_GPIO_MODE_PCIE_RST 0 +#define MT7620_GPIO_MODE_PCIE_REF 1 +#define MT7620_GPIO_MODE_PCIE_GPIO 2 +#define MT7620_GPIO_MODE_PCIE_MASK 0x3 +#define MT7620_GPIO_MODE_PCIE_SHIFT 16 + +#define MT7620_GPIO_MODE_WDT_RST 0 +#define MT7620_GPIO_MODE_WDT_REF 1 +#define MT7620_GPIO_MODE_WDT_GPIO 2 +#define MT7620_GPIO_MODE_WDT_MASK 0x3 +#define MT7620_GPIO_MODE_WDT_SHIFT 21 + +#define MT7620_GPIO_MODE_MDIO 0 +#define MT7620_GPIO_MODE_MDIO_REFCLK 1 +#define MT7620_GPIO_MODE_MDIO_GPIO 2 +#define MT7620_GPIO_MODE_MDIO_MASK 0x3 +#define MT7620_GPIO_MODE_MDIO_SHIFT 7 + +#define MT7620_GPIO_MODE_I2C 0 +#define MT7620_GPIO_MODE_UART1 5 +#define MT7620_GPIO_MODE_RGMII1 9 +#define MT7620_GPIO_MODE_RGMII2 10 +#define MT7620_GPIO_MODE_SPI 11 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12 +#define MT7620_GPIO_MODE_WLED 13 +#define MT7620_GPIO_MODE_JTAG 15 +#define MT7620_GPIO_MODE_EPHY 15 +#define MT7620_GPIO_MODE_PA 20 + +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) }; +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) }; +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) }; +static struct rt2880_pmx_func mdio_grp[] = { + FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2), + FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2), +}; +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) }; +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) }; +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) }; +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) }; +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) }; +static struct rt2880_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) }; +static struct rt2880_pmx_func uartf_grp[] = { + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8), + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8), + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8), + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8), + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4), + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4), + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4), +}; +static struct rt2880_pmx_func wdt_grp[] = { + FUNC("wdt rst", 0, 17, 1), + FUNC("wdt refclk", 0, 17, 1), + }; +static struct rt2880_pmx_func pcie_rst_grp[] = { + FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1), + FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1) +}; +static struct rt2880_pmx_func nd_sd_grp[] = { + FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15), + FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13) +}; + +static struct rt2880_pmx_group mt7620a_pinmux_data[] = { + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C), + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK, + MT7620_GPIO_MODE_UART0_SHIFT), + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI), + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1), + GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK, + MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT), + GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK, + MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT), + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1), + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK), + GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK, + MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT), + GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK, + MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT), + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2), + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED), + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY), + GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA), + { 0 } +}; + +static struct rt2880_pmx_func pwm1_grp_mt7628[] = { + FUNC("sdxc d6", 3, 19, 1), + FUNC("utif", 2, 19, 1), + FUNC("gpio", 1, 19, 1), + FUNC("pwm1", 0, 19, 1), +}; + +static struct rt2880_pmx_func pwm0_grp_mt7628[] = { + FUNC("sdxc d7", 3, 18, 1), + FUNC("utif", 2, 18, 1), + FUNC("gpio", 1, 18, 1), + FUNC("pwm0", 0, 18, 1), +}; + +static struct rt2880_pmx_func uart2_grp_mt7628[] = { + FUNC("sdxc d5 d4", 3, 20, 2), + FUNC("pwm", 2, 20, 2), + FUNC("gpio", 1, 20, 2), + FUNC("uart2", 0, 20, 2), +}; + +static struct rt2880_pmx_func uart1_grp_mt7628[] = { + FUNC("sw_r", 3, 45, 2), + FUNC("pwm", 2, 45, 2), + FUNC("gpio", 1, 45, 2), + FUNC("uart1", 0, 45, 2), +}; + +static struct rt2880_pmx_func i2c_grp_mt7628[] = { + FUNC("-", 3, 4, 2), + FUNC("debug", 2, 4, 2), + FUNC("gpio", 1, 4, 2), + FUNC("i2c", 0, 4, 2), +}; + +static struct rt2880_pmx_func refclk_grp_mt7628[] = { FUNC("refclk", 0, 37, 1) }; +static struct rt2880_pmx_func perst_grp_mt7628[] = { FUNC("perst", 0, 36, 1) }; +static struct rt2880_pmx_func wdt_grp_mt7628[] = { FUNC("wdt", 0, 38, 1) }; +static struct rt2880_pmx_func spi_grp_mt7628[] = { FUNC("spi", 0, 7, 4) }; + +static struct rt2880_pmx_func sd_mode_grp_mt7628[] = { + FUNC("jtag", 3, 22, 8), + FUNC("utif", 2, 22, 8), + FUNC("gpio", 1, 22, 8), + FUNC("sdxc", 0, 22, 8), +}; + +static struct rt2880_pmx_func uart0_grp_mt7628[] = { + FUNC("-", 3, 12, 2), + FUNC("-", 2, 12, 2), + FUNC("gpio", 1, 12, 2), + FUNC("uart0", 0, 12, 2), +}; + +static struct rt2880_pmx_func i2s_grp_mt7628[] = { + FUNC("antenna", 3, 0, 4), + FUNC("pcm", 2, 0, 4), + FUNC("gpio", 1, 0, 4), + FUNC("i2s", 0, 0, 4), +}; + +static struct rt2880_pmx_func spi_cs1_grp_mt7628[] = { + FUNC("-", 3, 6, 1), + FUNC("refclk", 2, 6, 1), + FUNC("gpio", 1, 6, 1), + FUNC("spi cs1", 0, 6, 1), +}; + +static struct rt2880_pmx_func spis_grp_mt7628[] = { + FUNC("pwm_uart2", 3, 14, 4), + FUNC("utif", 2, 14, 4), + FUNC("gpio", 1, 14, 4), + FUNC("spis", 0, 14, 4), +}; + +static struct rt2880_pmx_func gpio_grp_mt7628[] = { + FUNC("pcie", 3, 11, 1), + FUNC("refclk", 2, 11, 1), + FUNC("gpio", 1, 11, 1), + FUNC("gpio", 0, 11, 1), +}; + +static struct rt2880_pmx_func p4led_kn_grp_mt7628[] = { + FUNC("jtag", 3, 30, 1), + FUNC("utif", 2, 30, 1), + FUNC("gpio", 1, 30, 1), + FUNC("p4led_kn", 0, 30, 1), +}; + +static struct rt2880_pmx_func p3led_kn_grp_mt7628[] = { + FUNC("jtag", 3, 31, 1), + FUNC("utif", 2, 31, 1), + FUNC("gpio", 1, 31, 1), + FUNC("p3led_kn", 0, 31, 1), +}; + +static struct rt2880_pmx_func p2led_kn_grp_mt7628[] = { + FUNC("jtag", 3, 32, 1), + FUNC("utif", 2, 32, 1), + FUNC("gpio", 1, 32, 1), + FUNC("p2led_kn", 0, 32, 1), +}; + +static struct rt2880_pmx_func p1led_kn_grp_mt7628[] = { + FUNC("jtag", 3, 33, 1), + FUNC("utif", 2, 33, 1), + FUNC("gpio", 1, 33, 1), + FUNC("p1led_kn", 0, 33, 1), +}; + +static struct rt2880_pmx_func p0led_kn_grp_mt7628[] = { + FUNC("jtag", 3, 34, 1), + FUNC("rsvd", 2, 34, 1), + FUNC("gpio", 1, 34, 1), + FUNC("p0led_kn", 0, 34, 1), +}; + +static struct rt2880_pmx_func wled_kn_grp_mt7628[] = { + FUNC("rsvd", 3, 35, 1), + FUNC("rsvd", 2, 35, 1), + FUNC("gpio", 1, 35, 1), + FUNC("wled_kn", 0, 35, 1), +}; + +static struct rt2880_pmx_func p4led_an_grp_mt7628[] = { + FUNC("jtag", 3, 39, 1), + FUNC("utif", 2, 39, 1), + FUNC("gpio", 1, 39, 1), + FUNC("p4led_an", 0, 39, 1), +}; + +static struct rt2880_pmx_func p3led_an_grp_mt7628[] = { + FUNC("jtag", 3, 40, 1), + FUNC("utif", 2, 40, 1), + FUNC("gpio", 1, 40, 1), + FUNC("p3led_an", 0, 40, 1), +}; + +static struct rt2880_pmx_func p2led_an_grp_mt7628[] = { + FUNC("jtag", 3, 41, 1), + FUNC("utif", 2, 41, 1), + FUNC("gpio", 1, 41, 1), + FUNC("p2led_an", 0, 41, 1), +}; + +static struct rt2880_pmx_func p1led_an_grp_mt7628[] = { + FUNC("jtag", 3, 42, 1), + FUNC("utif", 2, 42, 1), + FUNC("gpio", 1, 42, 1), + FUNC("p1led_an", 0, 42, 1), +}; + +static struct rt2880_pmx_func p0led_an_grp_mt7628[] = { + FUNC("jtag", 3, 43, 1), + FUNC("rsvd", 2, 43, 1), + FUNC("gpio", 1, 43, 1), + FUNC("p0led_an", 0, 43, 1), +}; + +static struct rt2880_pmx_func wled_an_grp_mt7628[] = { + FUNC("rsvd", 3, 44, 1), + FUNC("rsvd", 2, 44, 1), + FUNC("gpio", 1, 44, 1), + FUNC("wled_an", 0, 44, 1), +}; + +#define MT7628_GPIO_MODE_MASK 0x3 + +#define MT7628_GPIO_MODE_P4LED_KN 58 +#define MT7628_GPIO_MODE_P3LED_KN 56 +#define MT7628_GPIO_MODE_P2LED_KN 54 +#define MT7628_GPIO_MODE_P1LED_KN 52 +#define MT7628_GPIO_MODE_P0LED_KN 50 +#define MT7628_GPIO_MODE_WLED_KN 48 +#define MT7628_GPIO_MODE_P4LED_AN 42 +#define MT7628_GPIO_MODE_P3LED_AN 40 +#define MT7628_GPIO_MODE_P2LED_AN 38 +#define MT7628_GPIO_MODE_P1LED_AN 36 +#define MT7628_GPIO_MODE_P0LED_AN 34 +#define MT7628_GPIO_MODE_WLED_AN 32 +#define MT7628_GPIO_MODE_PWM1 30 +#define MT7628_GPIO_MODE_PWM0 28 +#define MT7628_GPIO_MODE_UART2 26 +#define MT7628_GPIO_MODE_UART1 24 +#define MT7628_GPIO_MODE_I2C 20 +#define MT7628_GPIO_MODE_REFCLK 18 +#define MT7628_GPIO_MODE_PERST 16 +#define MT7628_GPIO_MODE_WDT 14 +#define MT7628_GPIO_MODE_SPI 12 +#define MT7628_GPIO_MODE_SDMODE 10 +#define MT7628_GPIO_MODE_UART0 8 +#define MT7628_GPIO_MODE_I2S 6 +#define MT7628_GPIO_MODE_CS1 4 +#define MT7628_GPIO_MODE_SPIS 2 +#define MT7628_GPIO_MODE_GPIO 0 + +static struct rt2880_pmx_group mt7628an_pinmux_data[] = { + GRP_G("pwm1", pwm1_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_PWM1), + GRP_G("pwm0", pwm0_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_PWM0), + GRP_G("uart2", uart2_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_UART2), + GRP_G("uart1", uart1_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_UART1), + GRP_G("i2c", i2c_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_I2C), + GRP("refclk", refclk_grp_mt7628, 1, MT7628_GPIO_MODE_REFCLK), + GRP("perst", perst_grp_mt7628, 1, MT7628_GPIO_MODE_PERST), + GRP("wdt", wdt_grp_mt7628, 1, MT7628_GPIO_MODE_WDT), + GRP("spi", spi_grp_mt7628, 1, MT7628_GPIO_MODE_SPI), + GRP_G("sdmode", sd_mode_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_SDMODE), + GRP_G("uart0", uart0_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_UART0), + GRP_G("i2s", i2s_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_I2S), + GRP_G("spi cs1", spi_cs1_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_CS1), + GRP_G("spis", spis_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_SPIS), + GRP_G("gpio", gpio_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_GPIO), + GRP_G("wled_an", wled_an_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_WLED_AN), + GRP_G("p0led_an", p0led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P0LED_AN), + GRP_G("p1led_an", p1led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P1LED_AN), + GRP_G("p2led_an", p2led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P2LED_AN), + GRP_G("p3led_an", p3led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P3LED_AN), + GRP_G("p4led_an", p4led_an_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P4LED_AN), + GRP_G("wled_kn", wled_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_WLED_KN), + GRP_G("p0led_kn", p0led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P0LED_KN), + GRP_G("p1led_kn", p1led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P1LED_KN), + GRP_G("p2led_kn", p2led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P2LED_KN), + GRP_G("p3led_kn", p3led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P3LED_KN), + GRP_G("p4led_kn", p4led_kn_grp_mt7628, MT7628_GPIO_MODE_MASK, + 1, MT7628_GPIO_MODE_P4LED_KN), + { 0 } +}; + +static int mt7620_pinmux_probe(struct platform_device *pdev) +{ + if (is_mt76x8()) + return rt2880_pinmux_init(pdev, mt7628an_pinmux_data); + else + return rt2880_pinmux_init(pdev, mt7620a_pinmux_data); +} + +static const struct of_device_id mt7620_pinmux_match[] = { + { .compatible = "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, mt7620_pinmux_match); + +static struct platform_driver mt7620_pinmux_driver = { + .probe = mt7620_pinmux_probe, + .driver = { + .name = "rt2880-pinmux", + .of_match_table = mt7620_pinmux_match, + }, +}; + +static int __init mt7620_pinmux_init(void) +{ + return platform_driver_register(&mt7620_pinmux_driver); +} +core_initcall_sync(mt7620_pinmux_init); -- cgit v1.2.3 From a49a8717d8693b339fb2b62e5846286d6126de7d Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Fri, 4 Jun 2021 13:51:59 +0200 Subject: pinctrl: ralink: move RT288X SoC pinmux config into a new 'pinctrl-rt288x.c' file Move all related code for SoC RT288X into a new driver located in 'pinctrl-rt288x.c' source file. Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210604115159.8834-7-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij --- arch/mips/include/asm/mach-ralink/rt288x.h | 9 ----- arch/mips/ralink/rt288x.c | 21 ----------- drivers/pinctrl/ralink/Kconfig | 5 +++ drivers/pinctrl/ralink/Makefile | 1 + drivers/pinctrl/ralink/pinctrl-rt288x.c | 60 ++++++++++++++++++++++++++++++ 5 files changed, 66 insertions(+), 30 deletions(-) create mode 100644 drivers/pinctrl/ralink/pinctrl-rt288x.c diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h index 5d10178f26af..5f213534f0f5 100644 --- a/arch/mips/include/asm/mach-ralink/rt288x.h +++ b/arch/mips/include/asm/mach-ralink/rt288x.h @@ -33,15 +33,6 @@ #define SYSTEM_CONFIG_CPUCLK_280 0x2 #define SYSTEM_CONFIG_CPUCLK_300 0x3 -#define RT2880_GPIO_MODE_I2C BIT(0) -#define RT2880_GPIO_MODE_UART0 BIT(1) -#define RT2880_GPIO_MODE_SPI BIT(2) -#define RT2880_GPIO_MODE_UART1 BIT(3) -#define RT2880_GPIO_MODE_JTAG BIT(4) -#define RT2880_GPIO_MODE_MDIO BIT(5) -#define RT2880_GPIO_MODE_SDRAM BIT(6) -#define RT2880_GPIO_MODE_PCI BIT(7) - #define CLKCFG_SRAM_CS_N_WDT BIT(9) #define RT2880_SDRAM_BASE 0x08000000 diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c index 34083c70ec68..493335db2fe1 100644 --- a/arch/mips/ralink/rt288x.c +++ b/arch/mips/ralink/rt288x.c @@ -14,29 +14,9 @@ #include #include #include -#include #include "common.h" -static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; -static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; -static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) }; -static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; -static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; -static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; -static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) }; - -static struct rt2880_pmx_group rt2880_pinmux_data_act[] = { - GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C), - GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI), - GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0), - GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG), - GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO), - GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM), - GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI), - { 0 } -}; - void __init ralink_clk_init(void) { unsigned long cpu_rate, wmac_rate = 40000000; @@ -106,6 +86,5 @@ void __init prom_soc_init(struct ralink_soc_info *soc_info) soc_info->mem_size_min = RT2880_MEM_SIZE_MIN; soc_info->mem_size_max = RT2880_MEM_SIZE_MAX; - rt2880_pinmux_data = rt2880_pinmux_data_act; ralink_soc = RT2880_SOC; } diff --git a/drivers/pinctrl/ralink/Kconfig b/drivers/pinctrl/ralink/Kconfig index 6edf0589cf0a..a76ee3deb8c3 100644 --- a/drivers/pinctrl/ralink/Kconfig +++ b/drivers/pinctrl/ralink/Kconfig @@ -21,6 +21,11 @@ config PINCTRL_MT7621 depends on RALINK && SOC_MT7621 select PINCTRL_RT2880 +config PINCTRL_RT288X + bool "RT288X pinctrl driver for RALINK/Mediatek SOCs" + depends on RALINK && SOC_RT288X + select PINCTRL_RT2880 + config PINCTRL_RT305X bool "RT305X pinctrl driver for RALINK/Mediatek SOCs" depends on RALINK && SOC_RT305X diff --git a/drivers/pinctrl/ralink/Makefile b/drivers/pinctrl/ralink/Makefile index 9b99b20e51e6..a15610206ced 100644 --- a/drivers/pinctrl/ralink/Makefile +++ b/drivers/pinctrl/ralink/Makefile @@ -3,5 +3,6 @@ obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o +obj-$(CONFIG_PINCTRL_RT288X) += pinctrl-rt288x.o obj-$(CONFIG_PINCTRL_RT305X) += pinctrl-rt305x.o obj-$(CONFIG_PINCTRL_RT3883) += pinctrl-rt3883.o diff --git a/drivers/pinctrl/ralink/pinctrl-rt288x.c b/drivers/pinctrl/ralink/pinctrl-rt288x.c new file mode 100644 index 000000000000..0744aebbace5 --- /dev/null +++ b/drivers/pinctrl/ralink/pinctrl-rt288x.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include "pinmux.h" + +#define RT2880_GPIO_MODE_I2C BIT(0) +#define RT2880_GPIO_MODE_UART0 BIT(1) +#define RT2880_GPIO_MODE_SPI BIT(2) +#define RT2880_GPIO_MODE_UART1 BIT(3) +#define RT2880_GPIO_MODE_JTAG BIT(4) +#define RT2880_GPIO_MODE_MDIO BIT(5) +#define RT2880_GPIO_MODE_SDRAM BIT(6) +#define RT2880_GPIO_MODE_PCI BIT(7) + +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) }; +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) }; +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 8) }; +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 5) }; +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) }; +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) }; +static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 32) }; + +static struct rt2880_pmx_group rt2880_pinmux_data_act[] = { + GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C), + GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI), + GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0), + GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG), + GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO), + GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM), + GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI), + { 0 } +}; + +static int rt288x_pinmux_probe(struct platform_device *pdev) +{ + return rt2880_pinmux_init(pdev, rt2880_pinmux_data_act); +} + +static const struct of_device_id rt288x_pinmux_match[] = { + { .compatible = "ralink,rt2880-pinmux" }, + {} +}; +MODULE_DEVICE_TABLE(of, rt288x_pinmux_match); + +static struct platform_driver rt288x_pinmux_driver = { + .probe = rt288x_pinmux_probe, + .driver = { + .name = "rt2880-pinmux", + .of_match_table = rt288x_pinmux_match, + }, +}; + +static int __init rt288x_pinmux_init(void) +{ + return platform_driver_register(&rt288x_pinmux_driver); +} +core_initcall_sync(rt288x_pinmux_init); -- cgit v1.2.3 From d9779093676bd8743ba2e1cd971f4eabb15c060d Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Sat, 5 Jun 2021 20:59:07 +0200 Subject: pinctrl: bcm: Constify static pinctrl_ops These are only assigned, either directly or via the bcm63xx_pinctrl_soc struct, to the pctlops field in the pinctrl_desc struct and never modified, so make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn Acked-by: Florian Fainelli Link: https://lore.kernel.org/r/20210605185908.39982-2-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm6318.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm63268.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6328.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6358.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6362.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6368.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm63xx.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6318.c b/drivers/pinctrl/bcm/pinctrl-bcm6318.c index 77fd9b58067d..4f96a285c307 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6318.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6318.c @@ -452,7 +452,7 @@ static int bcm6318_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops bcm6318_pctl_ops = { +static const struct pinctrl_ops bcm6318_pctl_ops = { .dt_free_map = pinctrl_utils_free_map, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .get_group_name = bcm6318_pinctrl_get_group_name, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63268.c b/drivers/pinctrl/bcm/pinctrl-bcm63268.c index d4c5fad7fb7d..f1dea4e1c63e 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm63268.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm63268.c @@ -597,7 +597,7 @@ static int bcm63268_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops bcm63268_pctl_ops = { +static const struct pinctrl_ops bcm63268_pctl_ops = { .dt_free_map = pinctrl_utils_free_map, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .get_group_name = bcm63268_pinctrl_get_group_name, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6328.c b/drivers/pinctrl/bcm/pinctrl-bcm6328.c index c9efce600550..fc090a1609d1 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6328.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6328.c @@ -358,7 +358,7 @@ static int bcm6328_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops bcm6328_pctl_ops = { +static const struct pinctrl_ops bcm6328_pctl_ops = { .dt_free_map = pinctrl_utils_free_map, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .get_group_name = bcm6328_pinctrl_get_group_name, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6358.c b/drivers/pinctrl/bcm/pinctrl-bcm6358.c index d638578727f3..7b316305eada 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6358.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6358.c @@ -303,7 +303,7 @@ static int bcm6358_gpio_request_enable(struct pinctrl_dev *pctldev, return regmap_field_update_bits(priv->overlays, mask, 0); } -static struct pinctrl_ops bcm6358_pctl_ops = { +static const struct pinctrl_ops bcm6358_pctl_ops = { .dt_free_map = pinctrl_utils_free_map, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .get_group_name = bcm6358_pinctrl_get_group_name, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6362.c b/drivers/pinctrl/bcm/pinctrl-bcm6362.c index 40ef495b6301..a9e8178268ed 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6362.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6362.c @@ -571,7 +571,7 @@ static int bcm6362_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops bcm6362_pctl_ops = { +static const struct pinctrl_ops bcm6362_pctl_ops = { .dt_free_map = pinctrl_utils_free_map, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .get_group_name = bcm6362_pinctrl_get_group_name, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6368.c b/drivers/pinctrl/bcm/pinctrl-bcm6368.c index 838095f9e890..e3739e921f5c 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6368.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6368.c @@ -457,7 +457,7 @@ static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev, return 0; } -static struct pinctrl_ops bcm6368_pctl_ops = { +static const struct pinctrl_ops bcm6368_pctl_ops = { .dt_free_map = pinctrl_utils_free_map, .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, .get_group_name = bcm6368_pinctrl_get_group_name, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.h b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h index 3bdb50021f1b..c135477ec768 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm63xx.h +++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h @@ -12,7 +12,7 @@ #define BCM63XX_BANK_GPIOS 32 struct bcm63xx_pinctrl_soc { - struct pinctrl_ops *pctl_ops; + const struct pinctrl_ops *pctl_ops; struct pinmux_ops *pmx_ops; const struct pinctrl_pin_desc *pins; -- cgit v1.2.3 From 0c6838767236c9348e05b3f54361a89ec03adc84 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Sat, 5 Jun 2021 20:59:08 +0200 Subject: pinctrl: bcm: Constify static pinmux_ops These are only assigned, either directly or via the bcm63xx_pinctrl_soc struct, to the pmxops field in the pinctrl_desc struct and never modified, so make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn Acked-by: Florian Fainelli Link: https://lore.kernel.org/r/20210605185908.39982-3-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm6318.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm63268.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6328.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6358.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6362.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm6368.c | 2 +- drivers/pinctrl/bcm/pinctrl-bcm63xx.h | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6318.c b/drivers/pinctrl/bcm/pinctrl-bcm6318.c index 4f96a285c307..9311220fb6cb 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6318.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6318.c @@ -460,7 +460,7 @@ static const struct pinctrl_ops bcm6318_pctl_ops = { .get_groups_count = bcm6318_pinctrl_get_group_count, }; -static struct pinmux_ops bcm6318_pmx_ops = { +static const struct pinmux_ops bcm6318_pmx_ops = { .get_function_groups = bcm6318_pinctrl_get_groups, .get_function_name = bcm6318_pinctrl_get_func_name, .get_functions_count = bcm6318_pinctrl_get_func_count, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63268.c b/drivers/pinctrl/bcm/pinctrl-bcm63268.c index f1dea4e1c63e..1c1060a39597 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm63268.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm63268.c @@ -605,7 +605,7 @@ static const struct pinctrl_ops bcm63268_pctl_ops = { .get_groups_count = bcm63268_pinctrl_get_group_count, }; -static struct pinmux_ops bcm63268_pmx_ops = { +static const struct pinmux_ops bcm63268_pmx_ops = { .get_function_groups = bcm63268_pinctrl_get_groups, .get_function_name = bcm63268_pinctrl_get_func_name, .get_functions_count = bcm63268_pinctrl_get_func_count, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6328.c b/drivers/pinctrl/bcm/pinctrl-bcm6328.c index fc090a1609d1..ffa8864abab6 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6328.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6328.c @@ -366,7 +366,7 @@ static const struct pinctrl_ops bcm6328_pctl_ops = { .get_groups_count = bcm6328_pinctrl_get_group_count, }; -static struct pinmux_ops bcm6328_pmx_ops = { +static const struct pinmux_ops bcm6328_pmx_ops = { .get_function_groups = bcm6328_pinctrl_get_groups, .get_function_name = bcm6328_pinctrl_get_func_name, .get_functions_count = bcm6328_pinctrl_get_func_count, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6358.c b/drivers/pinctrl/bcm/pinctrl-bcm6358.c index 7b316305eada..9f6cd7447887 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6358.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6358.c @@ -311,7 +311,7 @@ static const struct pinctrl_ops bcm6358_pctl_ops = { .get_groups_count = bcm6358_pinctrl_get_group_count, }; -static struct pinmux_ops bcm6358_pmx_ops = { +static const struct pinmux_ops bcm6358_pmx_ops = { .get_function_groups = bcm6358_pinctrl_get_groups, .get_function_name = bcm6358_pinctrl_get_func_name, .get_functions_count = bcm6358_pinctrl_get_func_count, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6362.c b/drivers/pinctrl/bcm/pinctrl-bcm6362.c index a9e8178268ed..13c7230949b2 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6362.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6362.c @@ -579,7 +579,7 @@ static const struct pinctrl_ops bcm6362_pctl_ops = { .get_groups_count = bcm6362_pinctrl_get_group_count, }; -static struct pinmux_ops bcm6362_pmx_ops = { +static const struct pinmux_ops bcm6362_pmx_ops = { .get_function_groups = bcm6362_pinctrl_get_groups, .get_function_name = bcm6362_pinctrl_get_func_name, .get_functions_count = bcm6362_pinctrl_get_func_count, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm6368.c b/drivers/pinctrl/bcm/pinctrl-bcm6368.c index e3739e921f5c..b33a74aec82b 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm6368.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm6368.c @@ -465,7 +465,7 @@ static const struct pinctrl_ops bcm6368_pctl_ops = { .get_groups_count = bcm6368_pinctrl_get_group_count, }; -static struct pinmux_ops bcm6368_pmx_ops = { +static const struct pinmux_ops bcm6368_pmx_ops = { .get_function_groups = bcm6368_pinctrl_get_groups, .get_function_name = bcm6368_pinctrl_get_func_name, .get_functions_count = bcm6368_pinctrl_get_func_count, diff --git a/drivers/pinctrl/bcm/pinctrl-bcm63xx.h b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h index c135477ec768..d58c8cd5b6b8 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm63xx.h +++ b/drivers/pinctrl/bcm/pinctrl-bcm63xx.h @@ -13,7 +13,7 @@ struct bcm63xx_pinctrl_soc { const struct pinctrl_ops *pctl_ops; - struct pinmux_ops *pmx_ops; + const struct pinmux_ops *pmx_ops; const struct pinctrl_pin_desc *pins; unsigned npins; -- cgit v1.2.3 From 884af72c90016cfccd5717439c86b48702cbf184 Mon Sep 17 00:00:00 2001 From: Zou Wei Date: Tue, 8 Jun 2021 14:34:08 +0800 Subject: pinctrl: mcp23s08: Fix missing unlock on error in mcp23s08_irq() Add the missing unlock before return from function mcp23s08_irq() in the error handling case. v1-->v2: remove the "return IRQ_HANDLED" line Fixes: 897120d41e7a ("pinctrl: mcp23s08: fix race condition in irq handler") Reported-by: Hulk Robot Signed-off-by: Zou Wei Link: https://lore.kernel.org/r/1623134048-56051-1-git-send-email-zou_wei@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 799d596a1a4b..d0259577934e 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -353,7 +353,7 @@ static irqreturn_t mcp23s08_irq(int irq, void *data) if (intf == 0) { /* There is no interrupt pending */ - return IRQ_HANDLED; + goto unlock; } if (mcp_read(mcp, MCP_INTCAP, &intcap)) -- cgit v1.2.3 From 21c423a6511f5a0639501a3100513666c8344372 Mon Sep 17 00:00:00 2001 From: Matthias Brugger Date: Tue, 8 Jun 2021 17:06:56 +0200 Subject: pinctrl: mediatek: fix mode encoding Pin modes are encoded in the SoC data structure. Use that value to set IES SMT. Cc: Fabien Parent Cc: Sean Wang Cc: Mattijs Korpershoek Cc: linux-mediatek@lists.infradead.org Fixes: 696beef77521 ("pinctrl: mediatek: move bit assignment") Signed-off-by: Matthias Brugger Signed-off-by: Matthias Brugger Link: https://lore.kernel.org/r/20210608150656.29007-1-matthias.bgg@kernel.org Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c index 525b1aa7f7a6..5f7c421ab6e7 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c @@ -134,13 +134,13 @@ static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, pin, pctl->devdata->port_align, value, arg); } - bit = BIT(pin & 0xf); - if (arg == PIN_CONFIG_INPUT_ENABLE) offset = pctl->devdata->ies_offset; else offset = pctl->devdata->smt_offset; + bit = BIT(offset & pctl->devdata->mode_mask); + if (value) reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl); else -- cgit v1.2.3 From 4e73bfa3ee37277e3f3e636786fd52d89273bd79 Mon Sep 17 00:00:00 2001 From: Andreas Kaessens Date: Thu, 10 Jun 2021 15:24:37 +0200 Subject: pinctrl: mcp23s08: Add optional reset GPIO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MCP23x port expander RESET# line can be connected to a host GPIO. The optional reset-gpio must be set to LOW if the reset is asserted at probing time. On page 5 in the datasheet [0] the "Device Active After Reset high" time is specified at 0 µs. Therefore no waiting is needed after the reset transition. [0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf Signed-off-by: Andreas Kaessens Signed-off-by: Darian Biastoch Link: https://lore.kernel.org/r/20210610132438.3085841-1-akaessens@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 3 +++ drivers/pinctrl/pinctrl-mcp23s08.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index d0259577934e..bccebe43dd6a 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -558,6 +559,8 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->chip.parent = dev; mcp->chip.owner = THIS_MODULE; + mcp->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + /* verify MCP_IOCON.SEQOP = 0, so sequential reads work, * and MCP_IOCON.HAEN = 1, so we work with all chips. */ diff --git a/drivers/pinctrl/pinctrl-mcp23s08.h b/drivers/pinctrl/pinctrl-mcp23s08.h index 90dc27081a3c..b8d15939e0c2 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.h +++ b/drivers/pinctrl/pinctrl-mcp23s08.h @@ -43,6 +43,7 @@ struct mcp23s08 { struct pinctrl_dev *pctldev; struct pinctrl_desc pinctrl_desc; + struct gpio_desc *reset_gpio; }; extern const struct regmap_config mcp23x08_regmap; -- cgit v1.2.3 From ee9889dfa969544ea4bbc3a406f2135a2bcaea69 Mon Sep 17 00:00:00 2001 From: Andreas Kaessens Date: Thu, 10 Jun 2021 15:24:38 +0200 Subject: dt-bindings: pinctrl: mcp23s08: add documentation for reset-gpios The reset-gpios property is added to the optional dt-bindings and also an example for it's usage. Signed-off-by: Andreas Kaessens Signed-off-by: Darian Biastoch Link: https://lore.kernel.org/r/20210610132438.3085841-2-akaessens@gmail.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt index 6ec3c8d79f49..2fa5edac7a35 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt @@ -49,6 +49,7 @@ Optional properties: - interrupt-controller: Marks the device node as a interrupt controller. - drive-open-drain: Sets the ODR flag in the IOCON register. This configures the IRQ output as open drain active low. +- reset-gpios: Corresponds to the active-low RESET# pin for the chip Optional device specific properties: - microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices @@ -135,6 +136,7 @@ gpio21: gpio@21 { microchip,irq-mirror; pinctrl-names = "default"; pinctrl-0 = <&i2cgpio0irq>, <&gpio21pullups>; + reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; gpio21pullups: pinmux { pins = "gpio0", "gpio1", "gpio2", "gpio3", -- cgit v1.2.3 From d3decc70d0793c2e2126bcced9e99877ea27a96d Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Mon, 14 Jun 2021 19:27:09 +0200 Subject: dt-bindings: pinctrl: qcom: sm6125: Document SM6125 pinctrl driver Document the newly added SM6125 pinctrl driver Signed-off-by: Martin Botka Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210614172713.558192-1-martin.botka@somainline.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm6125-pinctrl.yaml | 132 +++++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml new file mode 100644 index 000000000000..5f7adaa81f83 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6125-pinctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6125-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: Qualcomm Technologies, Inc. SM6125 TLMM block + +maintainers: + - Martin Botka + +description: | + This binding describes the Top Level Mode Multiplexer (TLMM) block found + in the SM6125 platform. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,sm6125-tlmm + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: "west" + - const: "south" + - const: "east" + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + gpio-reserved-ranges: true + '#gpio-cells': true + gpio-ranges: true + wakeup-parent: true + +required: + - compatible + - reg + - reg-names + +additionalProperties: false + +patternProperties: + '-state$': + oneOf: + - $ref: "#/$defs/qcom-sm6125-tlmm-state" + - patternProperties: + ".*": + $ref: "#/$defs/qcom-sm6125-tlmm-state" + +$defs: + qcom-sm6125-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio[0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-2]$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ adsp_ext, agera_pll, atest_char, atest_char0, atest_char1, + atest_char2, atest_char3, atest_tsens, atest_tsens2, atest_usb1, + atest_usb10, atest_usb11, atest_usb12, atest_usb13, atest_usb2, + atest_usb20, atest_usb21, atest_usb22, atest_usb23, aud_sb, + audio_ref, cam_mclk, cci_async, cci_i2c, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, copy_gp, copy_phase, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, debug_hot, dmic0_clk, dmic0_data, dmic1_clk, + dmic1_data, dp_hot, edp_hot, edp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, + gp_pdm0, gp_pdm1, gp_pdm2, gpio, gps_tx, jitter_bist, ldo_en, + ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0, mdp_vsync1, + mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, mpm_pwr, mss_lte, + nav_pps, pa_indicator, phase_flag, pll_bist, pll_bypassnl, pll_reset, + pri_mi2s, pri_mi2s_ws, prng_rosc, qca_sb, qdss_cti, qdss, qlink_enable, + qlink_request, qua_mi2s, qui_mi2s, qup00, qup01, qup02, qup03, qup04, + qup10, qup11, qup12, qup13, qup14, sd_write, sec_mi2s, sp_cmu, swr_rx, + swr_tx, ter_mi2s, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, + uim2_present, uim2_reset, unused1, unused2, usb_phy, vfr_1, vsense_trigger, + wlan1_adc0, wlan1_adc1, wlan2_adc0, wlan2_adc1, wsa_clk, wsa_data ] + + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + pinctrl@500000 { + compatible = "qcom,sm6125-tlmm"; + reg = <0x00500000 0x400000>, + <0x00900000 0x400000>, + <0x00d00000 0x400000>; + reg-names = "west", "south", "east"; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 134>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; -- cgit v1.2.3 From 0c3ae641a27a41e4998663b34c133d6ff3131df7 Mon Sep 17 00:00:00 2001 From: Martin Botka Date: Mon, 14 Jun 2021 19:27:10 +0200 Subject: drivers: qcom: pinctrl: Add pinctrl driver for sm6125 This patch adds pinctrl driver for sm6125. Signed-off-by: Martin Botka Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210614172713.558192-2-martin.botka@somainline.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm6125.c | 1277 +++++++++++++++++++++++++++++++++ 3 files changed, 1287 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm6125.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 25d2f7f7f3b6..ec1192b459f2 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -256,6 +256,15 @@ config PINCTRL_SDX55 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SDX55 platform. +config PINCTRL_SM6125 + tristate "Qualcomm Technologies Inc SM6125 pin controller driver" + depends on GPIOLIB && OF + depends on PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM6125 platform. + config PINCTRL_SM8150 tristate "Qualcomm Technologies Inc SM8150 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index d4301fbb7274..d696fe2789bb 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PINCTRL_SC8180X) += pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) += pinctrl-sdx55.o +obj-$(CONFIG_PINCTRL_SM6125) += pinctrl-sm6125.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o obj-$(CONFIG_PINCTRL_SM8350) += pinctrl-sm8350.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm6125.c b/drivers/pinctrl/qcom/pinctrl-sm6125.c new file mode 100644 index 000000000000..724fa5a34465 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm6125.c @@ -0,0 +1,1277 @@ +//SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const char * const sm6125_tiles[] = { + "south", + "east", + "west" +}; + +enum { + SOUTH, + EAST, + WEST +}; + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x4 + 0x1000 * id, \ + .intr_cfg_reg = 0x8 + 0x1000 * id, \ + .intr_status_reg = 0xc + 0x1000 * id, \ + .intr_target_reg = 0x8 + 0x1000 * id, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = _tile, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = WEST, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sm6125_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "UFS_RESET"), + PINCTRL_PIN(134, "SDC1_RCLK"), + PINCTRL_PIN(135, "SDC1_CLK"), + PINCTRL_PIN(136, "SDC1_CMD"), + PINCTRL_PIN(137, "SDC1_DATA"), + PINCTRL_PIN(138, "SDC2_CLK"), + PINCTRL_PIN(139, "SDC2_CMD"), + PINCTRL_PIN(140, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); + +static const unsigned int ufs_reset_pins[] = { 133 }; +static const unsigned int sdc1_rclk_pins[] = { 134 }; +static const unsigned int sdc1_clk_pins[] = { 135 }; +static const unsigned int sdc1_cmd_pins[] = { 136 }; +static const unsigned int sdc1_data_pins[] = { 137 }; +static const unsigned int sdc2_clk_pins[] = { 138 }; +static const unsigned int sdc2_cmd_pins[] = { 139 }; +static const unsigned int sdc2_data_pins[] = { 140 }; + + +enum sm6125_functions { + msm_mux_qup00, + msm_mux_gpio, + msm_mux_qdss, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_ddr_pxi0, + msm_mux_ddr_bist, + msm_mux_atest_tsens2, + msm_mux_vsense_trigger, + msm_mux_atest_usb1, + msm_mux_gp_pdm1, + msm_mux_phase_flag, + msm_mux_dbg_out, + msm_mux_qup14, + msm_mux_atest_usb11, + msm_mux_ddr_pxi2, + msm_mux_atest_usb10, + msm_mux_jitter_bist, + msm_mux_ddr_pxi3, + msm_mux_pll_bypassnl, + msm_mux_pll_bist, + msm_mux_qup03, + msm_mux_pll_reset, + msm_mux_agera_pll, + msm_mux_qdss_cti, + msm_mux_qup04, + msm_mux_wlan2_adc1, + msm_mux_wlan2_adc0, + msm_mux_wsa_clk, + msm_mux_qup13, + msm_mux_ter_mi2s, + msm_mux_wsa_data, + msm_mux_qup10, + msm_mux_gcc_gp3, + msm_mux_qup12, + msm_mux_sd_write, + msm_mux_qup11, + msm_mux_cam_mclk, + msm_mux_atest_tsens, + msm_mux_cci_i2c, + msm_mux_cci_timer2, + msm_mux_cci_timer1, + msm_mux_gcc_gp2, + msm_mux_cci_async, + msm_mux_cci_timer4, + msm_mux_cci_timer0, + msm_mux_gcc_gp1, + msm_mux_cci_timer3, + msm_mux_wlan1_adc1, + msm_mux_wlan1_adc0, + msm_mux_qlink_request, + msm_mux_qlink_enable, + msm_mux_pa_indicator, + msm_mux_nav_pps, + msm_mux_gps_tx, + msm_mux_gp_pdm0, + msm_mux_atest_usb13, + msm_mux_ddr_pxi1, + msm_mux_atest_usb12, + msm_mux_cri_trng0, + msm_mux_cri_trng, + msm_mux_cri_trng1, + msm_mux_gp_pdm2, + msm_mux_sp_cmu, + msm_mux_atest_usb2, + msm_mux_atest_usb23, + msm_mux_uim2_data, + msm_mux_uim2_clk, + msm_mux_uim2_reset, + msm_mux_atest_usb22, + msm_mux_uim2_present, + msm_mux_atest_usb21, + msm_mux_uim1_data, + msm_mux_atest_usb20, + msm_mux_uim1_clk, + msm_mux_uim1_reset, + msm_mux_uim1_present, + msm_mux_mdp_vsync, + msm_mux_copy_gp, + msm_mux_tsense_pwm, + msm_mux_mpm_pwr, + msm_mux_tgu_ch3, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mdp_vsync4, + msm_mux_mdp_vsync5, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_atest_char1, + msm_mux_vfr_1, + msm_mux_tgu_ch2, + msm_mux_atest_char0, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_prng_rosc, + msm_mux_dp_hot, + msm_mux_debug_hot, + msm_mux_copy_phase, + msm_mux_usb_phy, + msm_mux_atest_char, + msm_mux_unused1, + msm_mux_qua_mi2s, + msm_mux_mss_lte, + msm_mux_swr_tx, + msm_mux_aud_sb, + msm_mux_unused2, + msm_mux_swr_rx, + msm_mux_edp_hot, + msm_mux_audio_ref, + msm_mux_pri_mi2s, + msm_mux_pri_mi2s_ws, + msm_mux_adsp_ext, + msm_mux_edp_lcd, + msm_mux_mclk2, + msm_mux_m_voc, + msm_mux_mclk1, + msm_mux_qca_sb, + msm_mux_qui_mi2s, + msm_mux_dmic0_clk, + msm_mux_sec_mi2s, + msm_mux_dmic0_data, + msm_mux_dmic1_clk, + msm_mux_dmic1_data, + msm_mux__, +}; + +static const char * const qup00_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", +}; +static const char * const qdss_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio20", "gpio21", "gpio34", "gpio35", + "gpio36", "gpio42", "gpio41", "gpio43", "gpio44", "gpio45", "gpio46", + "gpio47", "gpio48", "gpio49", "gpio80", "gpio81", "gpio82", "gpio83", + "gpio84", "gpio85", "gpio86", "gpio91", "gpio92", "gpio94", "gpio96", + "gpio100", "gpio102", "gpio114", "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const qup01_groups[] = { + "gpio4", "gpio5", +}; +static const char * const qup02_groups[] = { + "gpio6", "gpio7", "gpio8", "gpio9", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const atest_tsens2_groups[] = { + "gpio7", +}; +static const char * const vsense_trigger_groups[] = { + "gpio7", +}; +static const char * const atest_usb1_groups[] = { + "gpio7", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio65", +}; +static const char * const phase_flag_groups[] = { + "gpio8", "gpio9", "gpio23", "gpio24", "gpio25", "gpio26", "gpio28", + "gpio29", "gpio30", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", + "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio80", "gpio81", + "gpio82", "gpio83", "gpio84", "gpio88", "gpio89", "gpio91", "gpio93", + "gpio98", "gpio129", "gpio130", "gpio131", +}; +static const char * const dbg_out_groups[] = { + "gpio9", +}; +static const char * const qup14_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio13", +}; +static const char * const atest_usb11_groups[] = { + "gpio10", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio10", "gpio11", +}; +static const char * const atest_usb10_groups[] = { + "gpio11", +}; +static const char * const jitter_bist_groups[] = { + "gpio12", "gpio31", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio13", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const pll_bist_groups[] = { + "gpio13", "gpio32", +}; +static const char * const qup03_groups[] = { + "gpio14", "gpio15", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const agera_pll_groups[] = { + "gpio14", "gpio33", +}; +static const char * const qdss_cti_groups[] = { + "gpio14", "gpio15", "gpio95", "gpio101", "gpio106", "gpio107", + "gpio110", "gpio111", +}; +static const char * const qup04_groups[] = { + "gpio16", "gpio17", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio16", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio17", +}; +static const char * const wsa_clk_groups[] = { + "gpio18", +}; +static const char * const qup13_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const ter_mi2s_groups[] = { + "gpio18", "gpio19", "gpio20", "gpio21", +}; +static const char * const wsa_data_groups[] = { + "gpio19", +}; +static const char * const qup10_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", "gpio58", +}; +static const char * const qup12_groups[] = { + "gpio28", "gpio29", +}; +static const char * const sd_write_groups[] = { + "gpio29", +}; +static const char * const qup11_groups[] = { + "gpio30", "gpio31", "gpio32", "gpio33", +}; +static const char * const cam_mclk_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio44", +}; +static const char * const atest_tsens_groups[] = { + "gpio34", +}; +static const char * const cci_i2c_groups[] = { + "gpio37", "gpio38", "gpio39", "gpio40", +}; +static const char * const cci_timer2_groups[] = { + "gpio42", +}; +static const char * const cci_timer1_groups[] = { + "gpio43", +}; +static const char * const gcc_gp2_groups[] = { + "gpio43", "gpio44", +}; +static const char * const cci_async_groups[] = { + "gpio44", "gpio47", "gpio48", +}; +static const char * const cci_timer4_groups[] = { + "gpio44", +}; +static const char * const cci_timer0_groups[] = { + "gpio45", +}; +static const char * const gcc_gp1_groups[] = { + "gpio45", "gpio46", +}; +static const char * const cci_timer3_groups[] = { + "gpio46", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio47", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio48", +}; +static const char * const qlink_request_groups[] = { + "gpio50", +}; +static const char * const qlink_enable_groups[] = { + "gpio51", +}; +static const char * const pa_indicator_groups[] = { + "gpio52", +}; +static const char * const nav_pps_groups[] = { + "gpio52", "gpio55", "gpio56", "gpio58", + "gpio59", +}; +static const char * const gps_tx_groups[] = { + "gpio52", "gpio53", "gpio55", "gpio56", "gpio58", "gpio59", +}; +static const char * const gp_pdm0_groups[] = { + "gpio53", "gpio94", +}; +static const char * const atest_usb13_groups[] = { + "gpio53", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio53", "gpio54", +}; +static const char * const atest_usb12_groups[] = { + "gpio54", +}; +static const char * const cri_trng0_groups[] = { + "gpio59", +}; +static const char * const cri_trng_groups[] = { + "gpio60", +}; +static const char * const cri_trng1_groups[] = { + "gpio61", +}; +static const char * const gp_pdm2_groups[] = { + "gpio62", "gpio78", +}; +static const char * const sp_cmu_groups[] = { + "gpio63", +}; +static const char * const atest_usb2_groups[] = { + "gpio66", +}; +static const char * const atest_usb23_groups[] = { + "gpio67", +}; +static const char * const uim2_data_groups[] = { + "gpio72", +}; +static const char * const uim2_clk_groups[] = { + "gpio73", +}; +static const char * const uim2_reset_groups[] = { + "gpio74", +}; +static const char * const atest_usb22_groups[] = { + "gpio74", +}; +static const char * const uim2_present_groups[] = { + "gpio75", +}; +static const char * const atest_usb21_groups[] = { + "gpio75", +}; +static const char * const uim1_data_groups[] = { + "gpio76", +}; +static const char * const atest_usb20_groups[] = { + "gpio76", +}; +static const char * const uim1_clk_groups[] = { + "gpio77", +}; +static const char * const uim1_reset_groups[] = { + "gpio78", +}; +static const char * const uim1_present_groups[] = { + "gpio79", +}; +static const char * const mdp_vsync_groups[] = { + "gpio80", "gpio81", "gpio82", "gpio89", "gpio96", "gpio97", +}; +static const char * const copy_gp_groups[] = { + "gpio85", +}; +static const char * const tsense_pwm_groups[] = { + "gpio87", +}; +static const char * const mpm_pwr_groups[] = { + "gpio88", +}; +static const char * const tgu_ch3_groups[] = { + "gpio88", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync4_groups[] = { + "gpio89", +}; +static const char * const mdp_vsync5_groups[] = { + "gpio89", +}; +static const char * const tgu_ch0_groups[] = { + "gpio89", +}; +static const char * const tgu_ch1_groups[] = { + "gpio90", +}; +static const char * const atest_char1_groups[] = { + "gpio90", +}; +static const char * const vfr_1_groups[] = { + "gpio91", +}; +static const char * const tgu_ch2_groups[] = { + "gpio91", +}; +static const char * const atest_char0_groups[] = { + "gpio92", +}; +static const char * const atest_char2_groups[] = { + "gpio93", +}; +static const char * const atest_char3_groups[] = { + "gpio94", +}; +static const char * const ldo_en_groups[] = { + "gpio96", +}; +static const char * const ldo_update_groups[] = { + "gpio97", +}; +static const char * const prng_rosc_groups[] = { + "gpio98", "gpio100", +}; +static const char * const dp_hot_groups[] = { + "gpio100", +}; +static const char * const debug_hot_groups[] = { + "gpio101", +}; +static const char * const copy_phase_groups[] = { + "gpio101", +}; +static const char * const usb_phy_groups[] = { + "gpio102", +}; +static const char * const atest_char_groups[] = { + "gpio102", +}; +static const char * const unused1_groups[] = { + "gpio104", +}; +static const char * const qua_mi2s_groups[] = { + "gpio104", "gpio106", "gpio107", "gpio108", "gpio110", "gpio111", +}; +static const char * const mss_lte_groups[] = { + "gpio105", "gpio109", +}; +static const char * const swr_tx_groups[] = { + "gpio106", "gpio107", "gpio108", "gpio109", +}; +static const char * const aud_sb_groups[] = { + "gpio106", "gpio107", "gpio108", "gpio109", +}; +static const char * const unused2_groups[] = { + "gpio109", +}; +static const char * const swr_rx_groups[] = { + "gpio110", "gpio111", "gpio112", +}; +static const char * const edp_hot_groups[] = { + "gpio111", +}; +static const char * const audio_ref_groups[] = { + "gpio112", +}; +static const char * const pri_mi2s_groups[] = { + "gpio113", "gpio115", "gpio116", +}; +static const char * const pri_mi2s_ws_groups[] = { + "gpio114", +}; +static const char * const adsp_ext_groups[] = { + "gpio116", +}; +static const char * const edp_lcd_groups[] = { + "gpio117", +}; +static const char * const mclk2_groups[] = { + "gpio118", +}; +static const char * const m_voc_groups[] = { + "gpio118", +}; +static const char * const mclk1_groups[] = { + "gpio119", +}; +static const char * const qca_sb_groups[] = { + "gpio121", "gpio122", +}; +static const char * const qui_mi2s_groups[] = { + "gpio121", "gpio122", "gpio123", "gpio124", +}; +static const char * const dmic0_clk_groups[] = { + "gpio125", +}; +static const char * const sec_mi2s_groups[] = { + "gpio125", "gpio126", "gpio127", "gpio128", +}; +static const char * const dmic0_data_groups[] = { + "gpio126", +}; +static const char * const dmic1_clk_groups[] = { + "gpio127", +}; +static const char * const dmic1_data_groups[] = { + "gpio128", +}; + +static const struct msm_function sm6125_functions[] = { + FUNCTION(qup00), + FUNCTION(gpio), + FUNCTION(qdss), + FUNCTION(qup01), + FUNCTION(qup02), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_bist), + FUNCTION(atest_tsens2), + FUNCTION(vsense_trigger), + FUNCTION(atest_usb1), + FUNCTION(gp_pdm1), + FUNCTION(phase_flag), + FUNCTION(dbg_out), + FUNCTION(qup14), + FUNCTION(atest_usb11), + FUNCTION(ddr_pxi2), + FUNCTION(atest_usb10), + FUNCTION(jitter_bist), + FUNCTION(ddr_pxi3), + FUNCTION(pll_bypassnl), + FUNCTION(pll_bist), + FUNCTION(qup03), + FUNCTION(pll_reset), + FUNCTION(agera_pll), + FUNCTION(qdss_cti), + FUNCTION(qup04), + FUNCTION(wlan2_adc1), + FUNCTION(wlan2_adc0), + FUNCTION(wsa_clk), + FUNCTION(qup13), + FUNCTION(ter_mi2s), + FUNCTION(wsa_data), + FUNCTION(qup10), + FUNCTION(gcc_gp3), + FUNCTION(qup12), + FUNCTION(sd_write), + FUNCTION(qup11), + FUNCTION(cam_mclk), + FUNCTION(atest_tsens), + FUNCTION(cci_i2c), + FUNCTION(cci_timer2), + FUNCTION(cci_timer1), + FUNCTION(gcc_gp2), + FUNCTION(cci_async), + FUNCTION(cci_timer4), + FUNCTION(cci_timer0), + FUNCTION(gcc_gp1), + FUNCTION(cci_timer3), + FUNCTION(wlan1_adc1), + FUNCTION(wlan1_adc0), + FUNCTION(qlink_request), + FUNCTION(qlink_enable), + FUNCTION(pa_indicator), + FUNCTION(nav_pps), + FUNCTION(gps_tx), + FUNCTION(gp_pdm0), + FUNCTION(atest_usb13), + FUNCTION(ddr_pxi1), + FUNCTION(atest_usb12), + FUNCTION(cri_trng0), + FUNCTION(cri_trng), + FUNCTION(cri_trng1), + FUNCTION(gp_pdm2), + FUNCTION(sp_cmu), + FUNCTION(atest_usb2), + FUNCTION(atest_usb23), + FUNCTION(uim2_data), + FUNCTION(uim2_clk), + FUNCTION(uim2_reset), + FUNCTION(atest_usb22), + FUNCTION(uim2_present), + FUNCTION(atest_usb21), + FUNCTION(uim1_data), + FUNCTION(atest_usb20), + FUNCTION(uim1_clk), + FUNCTION(uim1_reset), + FUNCTION(uim1_present), + FUNCTION(mdp_vsync), + FUNCTION(copy_gp), + FUNCTION(tsense_pwm), + FUNCTION(mpm_pwr), + FUNCTION(tgu_ch3), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mdp_vsync4), + FUNCTION(mdp_vsync5), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(atest_char1), + FUNCTION(vfr_1), + FUNCTION(tgu_ch2), + FUNCTION(atest_char0), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(prng_rosc), + FUNCTION(dp_hot), + FUNCTION(debug_hot), + FUNCTION(copy_phase), + FUNCTION(usb_phy), + FUNCTION(atest_char), + FUNCTION(unused1), + FUNCTION(qua_mi2s), + FUNCTION(mss_lte), + FUNCTION(swr_tx), + FUNCTION(aud_sb), + FUNCTION(unused2), + FUNCTION(swr_rx), + FUNCTION(edp_hot), + FUNCTION(audio_ref), + FUNCTION(pri_mi2s), + FUNCTION(pri_mi2s_ws), + FUNCTION(adsp_ext), + FUNCTION(edp_lcd), + FUNCTION(mclk2), + FUNCTION(m_voc), + FUNCTION(mclk1), + FUNCTION(qca_sb), + FUNCTION(qui_mi2s), + FUNCTION(dmic0_clk), + FUNCTION(sec_mi2s), + FUNCTION(dmic0_data), + FUNCTION(dmic1_clk), + FUNCTION(dmic1_data), +}; + + /* + * Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm6125_groups[] = { + [0] = PINGROUP(0, WEST, qup00, _, qdss, _, _, _, _, _, _), + [1] = PINGROUP(1, WEST, qup00, _, qdss, _, _, _, _, _, _), + [2] = PINGROUP(2, WEST, qup00, _, qdss, _, _, _, _, _, _), + [3] = PINGROUP(3, WEST, qup00, _, qdss, _, _, _, _, _, _), + [4] = PINGROUP(4, WEST, qup01, _, _, _, _, _, _, _, _), + [5] = PINGROUP(5, WEST, qup01, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, WEST, qup02, ddr_pxi0, _, _, _, _, _, _, _), + [7] = PINGROUP(7, WEST, qup02, ddr_bist, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _), + [8] = PINGROUP(8, WEST, qup02, gp_pdm1, ddr_bist, _, phase_flag, _, _, _, _), + [9] = PINGROUP(9, WEST, qup02, ddr_bist, dbg_out, phase_flag, _, _, _, _, _), + [10] = PINGROUP(10, EAST, qup14, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _, _), + [11] = PINGROUP(11, EAST, qup14, atest_usb10, ddr_pxi2, _, _, _, _, _, _), + [12] = PINGROUP(12, EAST, qup14, jitter_bist, ddr_pxi3, _, _, _, _, _, _), + [13] = PINGROUP(13, EAST, qup14, pll_bypassnl, pll_bist, _, ddr_pxi3, _, _, _, _), + [14] = PINGROUP(14, WEST, qup03, qup03, pll_reset, agera_pll, _, qdss_cti, _, _, _), + [15] = PINGROUP(15, WEST, qup03, qup03, qdss_cti, _, _, _, _, _, _), + [16] = PINGROUP(16, WEST, qup04, qup04, _, wlan2_adc1, _, _, _, _, _), + [17] = PINGROUP(17, WEST, qup04, qup04, _, wlan2_adc0, _, _, _, _, _), + [18] = PINGROUP(18, EAST, wsa_clk, qup13, ter_mi2s, _, _, _, _, _, _), + [19] = PINGROUP(19, EAST, wsa_data, qup13, ter_mi2s, _, _, _, _, _, _), + [20] = PINGROUP(20, EAST, qup13, ter_mi2s, qdss, _, _, _, _, _, _), + [21] = PINGROUP(21, EAST, qup13, ter_mi2s, _, qdss, _, _, _, _, _), + [22] = PINGROUP(22, WEST, qup10, gcc_gp3, _, _, _, _, _, _, _), + [23] = PINGROUP(23, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [24] = PINGROUP(24, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [25] = PINGROUP(25, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [26] = PINGROUP(26, WEST, qup10, _, phase_flag, _, _, _, _, _, _), + [27] = PINGROUP(27, WEST, qup10, _, _, _, _, _, _, _, _), + [28] = PINGROUP(28, WEST, qup12, _, phase_flag, _, _, _, _, _, _), + [29] = PINGROUP(29, WEST, qup12, sd_write, _, phase_flag, _, _, _, _, _), + [30] = PINGROUP(30, WEST, qup11, _, phase_flag, _, _, _, _, _, _), + [31] = PINGROUP(31, WEST, qup11, jitter_bist, _, _, _, _, _, _, _), + [32] = PINGROUP(32, WEST, qup11, pll_bist, _, _, _, _, _, _, _), + [33] = PINGROUP(33, WEST, qup11, agera_pll, _, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, cam_mclk, _, qdss, atest_tsens, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, cam_mclk, _, qdss, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, cci_i2c, _, _, _, _, _, _, _, _), + [38] = PINGROUP(38, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, EAST, cci_i2c, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, EAST, _, qdss, _, _, _, _, _, _, _), + [42] = PINGROUP(42, EAST, cci_timer2, _, qdss, _, _, _, _, _, _), + [43] = PINGROUP(43, EAST, cci_timer1, _, gcc_gp2, _, qdss, _, _, _, _), + [44] = PINGROUP(44, SOUTH, cci_async, cci_timer4, _, gcc_gp2, _, qdss, cam_mclk, _, _), + [45] = PINGROUP(45, SOUTH, cci_timer0, _, gcc_gp1, qdss, _, _, _, _, _), + [46] = PINGROUP(46, SOUTH, cci_timer3, _, gcc_gp1, _, qdss, _, _, _, _), + [47] = PINGROUP(47, SOUTH, cci_async, _, qdss, wlan1_adc1, _, _, _, _, _), + [48] = PINGROUP(48, SOUTH, cci_async, _, qdss, wlan1_adc0, _, _, _, _, _), + [49] = PINGROUP(49, SOUTH, qdss, _, _, _, _, _, _, _, _), + [50] = PINGROUP(50, SOUTH, qlink_request, _, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qlink_enable, _, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, pa_indicator, nav_pps, nav_pps, gps_tx, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, _, gps_tx, gp_pdm0, _, phase_flag, atest_usb13, ddr_pxi1, _, _), + [54] = PINGROUP(54, SOUTH, _, _, phase_flag, atest_usb12, ddr_pxi1, _, _, _, _), + [55] = PINGROUP(55, SOUTH, _, nav_pps, nav_pps, gps_tx, _, phase_flag, _, _, _), + [56] = PINGROUP(56, SOUTH, _, nav_pps, gps_tx, nav_pps, phase_flag, _, _, _, _), + [57] = PINGROUP(57, SOUTH, _, phase_flag, _, _, _, _, _, _, _), + [58] = PINGROUP(58, SOUTH, _, nav_pps, nav_pps, gps_tx, gcc_gp3, _, phase_flag, _, _), + [59] = PINGROUP(59, SOUTH, _, nav_pps, nav_pps, gps_tx, cri_trng0, _, phase_flag, _, _), + [60] = PINGROUP(60, SOUTH, _, cri_trng, _, phase_flag, _, _, _, _, _), + [61] = PINGROUP(61, SOUTH, _, cri_trng1, _, phase_flag, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, _, _, gp_pdm2, _, phase_flag, _, _, _, _), + [63] = PINGROUP(63, SOUTH, _, sp_cmu, _, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, _, _, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, _, gp_pdm1, _, _, _, _, _, _, _), + [66] = PINGROUP(66, SOUTH, _, _, atest_usb2, _, _, _, _, _, _), + [67] = PINGROUP(67, SOUTH, _, _, atest_usb23, _, _, _, _, _, _), + [68] = PINGROUP(68, SOUTH, _, _, _, _, _, _, _, _, _), + [69] = PINGROUP(69, SOUTH, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, _, _, _, _, _, _, _, _, _), + [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, uim2_data, _, _, _, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, uim2_clk, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, uim2_reset, _, atest_usb22, _, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, uim2_present, _, atest_usb21, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, uim1_data, _, atest_usb20, _, _, _, _, _, _), + [77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, SOUTH, uim1_reset, gp_pdm2, _, _, _, _, _, _, _), + [79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _), + [81] = PINGROUP(81, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _), + [82] = PINGROUP(82, SOUTH, mdp_vsync, _, phase_flag, qdss, _, _, _, _, _), + [83] = PINGROUP(83, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), + [84] = PINGROUP(84, SOUTH, _, phase_flag, qdss, _, _, _, _, _, _), + [85] = PINGROUP(85, SOUTH, copy_gp, _, qdss, _, _, _, _, _, _), + [86] = PINGROUP(86, SOUTH, _, qdss, _, _, _, _, _, _, _), + [87] = PINGROUP(87, WEST, tsense_pwm, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, WEST, mpm_pwr, tgu_ch3, _, phase_flag, _, _, _, _, _), + [89] = PINGROUP(89, WEST, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mdp_vsync4, mdp_vsync5, tgu_ch0, _), + [90] = PINGROUP(90, WEST, tgu_ch1, atest_char1, _, _, _, _, _, _, _), + [91] = PINGROUP(91, WEST, vfr_1, tgu_ch2, _, phase_flag, qdss, _, _, _, _), + [92] = PINGROUP(92, WEST, qdss, atest_char0, _, _, _, _, _, _, _), + [93] = PINGROUP(93, WEST, _, phase_flag, atest_char2, _, _, _, _, _, _), + [94] = PINGROUP(94, SOUTH, gp_pdm0, _, qdss, atest_char3, _, _, _, _, _), + [95] = PINGROUP(95, SOUTH, qdss_cti, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, SOUTH, mdp_vsync, ldo_en, qdss, _, _, _, _, _, _), + [97] = PINGROUP(97, SOUTH, mdp_vsync, ldo_update, _, _, _, _, _, _, _), + [98] = PINGROUP(98, SOUTH, _, phase_flag, prng_rosc, _, _, _, _, _, _), + [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _), + [100] = PINGROUP(100, SOUTH, dp_hot, prng_rosc, qdss, _, _, _, _, _, _), + [101] = PINGROUP(101, SOUTH, debug_hot, copy_phase, qdss_cti, _, _, _, _, _, _), + [102] = PINGROUP(102, SOUTH, usb_phy, _, qdss, atest_char, _, _, _, _, _), + [103] = PINGROUP(103, SOUTH, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, EAST, unused1, _, qua_mi2s, _, _, _, _, _, _), + [105] = PINGROUP(105, EAST, mss_lte, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _), + [107] = PINGROUP(107, EAST, swr_tx, aud_sb, qua_mi2s, _, qdss_cti, _, _, _, _), + [108] = PINGROUP(108, EAST, swr_tx, aud_sb, qua_mi2s, _, _, _, _, _, _), + [109] = PINGROUP(109, EAST, swr_tx, aud_sb, unused2, _, mss_lte, _, _, _, _), + [110] = PINGROUP(110, EAST, swr_rx, qua_mi2s, _, qdss_cti, _, _, _, _, _), + [111] = PINGROUP(111, EAST, swr_rx, qua_mi2s, edp_hot, _, qdss_cti, _, _, _, _), + [112] = PINGROUP(112, EAST, swr_rx, audio_ref, _, _, _, _, _, _, _), + [113] = PINGROUP(113, EAST, pri_mi2s, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, EAST, pri_mi2s_ws, qdss, _, _, _, _, _, _, _), + [115] = PINGROUP(115, EAST, pri_mi2s, qdss, _, _, _, _, _, _, _), + [116] = PINGROUP(116, EAST, pri_mi2s, adsp_ext, qdss, _, _, _, _, _, _), + [117] = PINGROUP(117, SOUTH, edp_lcd, qdss, _, _, _, _, _, _, _), + [118] = PINGROUP(118, SOUTH, mclk2, m_voc, qdss, _, _, _, _, _, _), + [119] = PINGROUP(119, SOUTH, mclk1, _, _, _, _, _, _, _, _), + [120] = PINGROUP(120, SOUTH, _, _, _, _, _, _, _, _, _), + [121] = PINGROUP(121, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _), + [122] = PINGROUP(122, EAST, qca_sb, qui_mi2s, _, _, _, _, _, _, _), + [123] = PINGROUP(123, EAST, qui_mi2s, _, _, _, _, _, _, _, _), + [124] = PINGROUP(124, EAST, qui_mi2s, _, _, _, _, _, _, _, _), + [125] = PINGROUP(125, EAST, dmic0_clk, sec_mi2s, _, _, _, _, _, _, _), + [126] = PINGROUP(126, EAST, dmic0_data, sec_mi2s, _, _, _, _, _, _, _), + [127] = PINGROUP(127, EAST, dmic1_clk, sec_mi2s, _, _, _, _, _, _, _), + [128] = PINGROUP(128, EAST, dmic1_data, sec_mi2s, _, _, _, _, _, _, _), + [129] = PINGROUP(129, SOUTH, _, phase_flag, _, _, _, _, _, _, _), + [130] = PINGROUP(130, SOUTH, phase_flag, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, SOUTH, phase_flag, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, SOUTH, _, _, _, _, _, _, _, _, _), + [133] = UFS_RESET(ufs_reset, 0x190000), + [134] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x18d000, 15, 0), + [135] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x18d000, 13, 6), + [136] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x18d000, 11, 3), + [137] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x18d000, 9, 0), + [138] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x58b000, 14, 6), + [139] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x58b000, 11, 3), + [140] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x58b000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm6125_tlmm = { + .pins = sm6125_pins, + .npins = ARRAY_SIZE(sm6125_pins), + .functions = sm6125_functions, + .nfunctions = ARRAY_SIZE(sm6125_functions), + .groups = sm6125_groups, + .ngroups = ARRAY_SIZE(sm6125_groups), + .ngpios = 134, + .tiles = sm6125_tiles, + .ntiles = ARRAY_SIZE(sm6125_tiles), +}; + +static int sm6125_tlmm_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm6125_tlmm); +} + +static const struct of_device_id sm6125_tlmm_of_match[] = { + { .compatible = "qcom,sm6125-tlmm", }, + { }, +}; + +static struct platform_driver sm6125_tlmm_driver = { + .driver = { + .name = "sm6125-tlmm", + .of_match_table = sm6125_tlmm_of_match, + }, + .probe = sm6125_tlmm_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm6125_tlmm_init(void) +{ + return platform_driver_register(&sm6125_tlmm_driver); +} +arch_initcall(sm6125_tlmm_init); + +static void __exit sm6125_tlmm_exit(void) +{ + platform_driver_unregister(&sm6125_tlmm_driver); +} +module_exit(sm6125_tlmm_exit); + +MODULE_DESCRIPTION("QTI sm6125 TLMM driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm6125_tlmm_of_match); -- cgit v1.2.3 From fa99e7013827858b9cfe43ebe539b9060a7861e8 Mon Sep 17 00:00:00 2001 From: Sai Krishna Potthuri Date: Mon, 21 Jun 2021 16:30:14 +0530 Subject: pinctrl: zynqmp: some code cleanups Some minor code cleanups and updates which includes - Mention module name under help in Kconfig. - Remove extra lines and duplicate Pin range checks. - Replace 'return ret' with 'return 0' in success path. - Copyright year update. - use devm_pinctrl_register() instead pinctrl_register() in probe. Signed-off-by: Sai Krishna Potthuri Link: https://lore.kernel.org/r/1624273214-66849-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 ++ drivers/pinctrl/pinctrl-zynqmp.c | 50 ++++++++++++++++------------------------ 2 files changed, 22 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index c2c7e7963ed0..f38f12801f18 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -336,6 +336,8 @@ config PINCTRL_ZYNQMP Configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters such as pull-up, slew rate, etc. + This driver can also be built as a module. If so, the module + will be called pinctrl-zynqmp. config PINCTRL_INGENIC bool "Pinctrl driver for the Ingenic JZ47xx SoCs" diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index d5497003ce71..bbde676b7313 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -2,7 +2,7 @@ /* * ZynqMP pin controller * - * Copyright (C) 2020 Xilinx, Inc. + * Copyright (C) 2020, 2021 Xilinx, Inc. * * Sai Krishna Potthuri * Rajan Vaja @@ -252,9 +252,6 @@ static int zynqmp_pinconf_cfg_get(struct pinctrl_dev *pctldev, unsigned int arg, param = pinconf_to_config_param(*config); int ret; - if (pin >= zynqmp_desc.npins) - return -EOPNOTSUPP; - switch (param) { case PIN_CONFIG_SLEW_RATE: param = PM_PINCTRL_CONFIG_SLEW_RATE; @@ -317,7 +314,7 @@ static int zynqmp_pinconf_cfg_get(struct pinctrl_dev *pctldev, } break; default: - ret = -EOPNOTSUPP; + ret = -ENOTSUPP; break; } @@ -348,9 +345,6 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, { int i, ret; - if (pin >= zynqmp_desc.npins) - return -EOPNOTSUPP; - for (i = 0; i < num_configs; i++) { unsigned int param = pinconf_to_config_param(configs[i]); unsigned int arg = pinconf_to_config_argument(configs[i]); @@ -428,7 +422,7 @@ static int zynqmp_pinconf_cfg_set(struct pinctrl_dev *pctldev, dev_warn(pctldev->dev, "unsupported configuration parameter '%u'\n", param); - ret = -EOPNOTSUPP; + ret = -ENOTSUPP; break; } @@ -504,7 +498,7 @@ static int zynqmp_pinctrl_get_function_groups(u32 fid, u32 index, u16 *groups) memcpy(groups, &payload[1], PINCTRL_GET_FUNC_GROUPS_RESP_LEN); - return ret; + return 0; } static int zynqmp_pinctrl_get_func_num_groups(u32 fid, unsigned int *ngroups) @@ -522,7 +516,7 @@ static int zynqmp_pinctrl_get_func_num_groups(u32 fid, unsigned int *ngroups) *ngroups = payload[1]; - return ret; + return 0; } /** @@ -533,16 +527,16 @@ static int zynqmp_pinctrl_get_func_num_groups(u32 fid, unsigned int *ngroups) * @groups: Groups data. * * Query firmware to get group IDs for each function. Firmware returns - * group IDs. Based on group index for the function, group names in + * group IDs. Based on the group index for the function, group names in * the function are stored. For example, the first group in "eth0" function - * is named as "eth0_0" and second group as "eth0_1" and so on. + * is named as "eth0_0" and the second group as "eth0_1" and so on. * * Based on the group ID received from the firmware, function stores name of * the group for that group ID. For example, if "eth0" first group ID * is x, groups[x] name will be stored as "eth0_0". * * Once done for each function, each function would have its group names - * and each groups would also have their names. + * and each group would also have their names. * * Return: 0 on success else error code. */ @@ -552,7 +546,7 @@ static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid, { u16 resp[NUM_GROUPS_PER_RESP] = {0}; const char **fgroups; - int ret = 0, index, i; + int ret, index, i; fgroups = devm_kzalloc(dev, sizeof(*fgroups) * func->ngroups, GFP_KERNEL); if (!fgroups) @@ -588,7 +582,7 @@ static int zynqmp_pinctrl_prepare_func_groups(struct device *dev, u32 fid, done: func->groups = fgroups; - return ret; + return 0; } static void zynqmp_pinctrl_get_function_name(u32 fid, char *name) @@ -622,7 +616,7 @@ static int zynqmp_pinctrl_get_num_functions(unsigned int *nfuncs) *nfuncs = payload[1]; - return ret; + return 0; } static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups) @@ -641,7 +635,7 @@ static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups) memcpy(groups, &payload[1], PINCTRL_GET_PIN_GROUPS_RESP_LEN); - return ret; + return 0; } static void zynqmp_pinctrl_group_add_pin(struct zynqmp_pctrl_group *group, @@ -660,7 +654,7 @@ static void zynqmp_pinctrl_group_add_pin(struct zynqmp_pctrl_group *group, * Based on the firmware response(group IDs for the pin), add * pin number to the respective group's pin array. * - * Once all pins are queries, each groups would have its number + * Once all pins are queries, each group would have its number * of pins and pin numbers data. * * Return: 0 on success else error code. @@ -689,7 +683,7 @@ static int zynqmp_pinctrl_create_pin_groups(struct device *dev, index += NUM_GROUPS_PER_RESP; } while (index <= MAX_PIN_GROUPS); - return ret; + return 0; } /** @@ -727,7 +721,7 @@ static int zynqmp_pinctrl_prepare_group_pins(struct device *dev, * prepare pin control driver data. * * Query number of functions and number of function groups (number - * of groups in given function) to allocate required memory buffers + * of groups in the given function) to allocate required memory buffers * for functions and groups. Once buffers are allocated to store * functions and groups data, query and store required information * (number of groups and group names for each function, number of @@ -778,7 +772,7 @@ static int zynqmp_pinctrl_prepare_function_info(struct device *dev, pctrl->funcs = funcs; pctrl->groups = groups; - return ret; + return 0; } static int zynqmp_pinctrl_get_num_pins(unsigned int *npins) @@ -795,7 +789,7 @@ static int zynqmp_pinctrl_get_num_pins(unsigned int *npins) *npins = payload[1]; - return ret; + return 0; } /** @@ -853,19 +847,17 @@ static int zynqmp_pinctrl_probe(struct platform_device *pdev) &zynqmp_desc.pins, &zynqmp_desc.npins); if (ret) { - dev_err(&pdev->dev, "pin desc prepare fail with %d\n", - ret); + dev_err(&pdev->dev, "pin desc prepare fail with %d\n", ret); return ret; } ret = zynqmp_pinctrl_prepare_function_info(&pdev->dev, pctrl); if (ret) { - dev_err(&pdev->dev, "function info prepare fail with %d\n", - ret); + dev_err(&pdev->dev, "function info prepare fail with %d\n", ret); return ret; } - pctrl->pctrl = pinctrl_register(&zynqmp_desc, &pdev->dev, pctrl); + pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynqmp_desc, pctrl); if (IS_ERR(pctrl->pctrl)) return PTR_ERR(pctrl->pctrl); @@ -887,7 +879,6 @@ static const struct of_device_id zynqmp_pinctrl_of_match[] = { { .compatible = "xlnx,zynqmp-pinctrl" }, { } }; - MODULE_DEVICE_TABLE(of, zynqmp_pinctrl_of_match); static struct platform_driver zynqmp_pinctrl_driver = { @@ -898,7 +889,6 @@ static struct platform_driver zynqmp_pinctrl_driver = { .probe = zynqmp_pinctrl_probe, .remove = zynqmp_pinctrl_remove, }; - module_platform_driver(zynqmp_pinctrl_driver); MODULE_AUTHOR("Sai Krishna Potthuri "); -- cgit v1.2.3 From db0f032512443678d30aa26c247099220e3e5aee Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Thu, 17 Jun 2021 16:46:02 +0200 Subject: pinctrl: stm32: check for IRQ MUX validity during alloc() Considering the following irq_domain_ops call chain: - .alloc() is called when a clients calls platform_get_irq() or gpiod_to_irq() - .activate() is called next, when the clients calls request_threaded_irq() Check for the IRQ MUX conflict during the first stage (alloc instead of activate). This avoids to provide the client with an IRQ that can't be used. Signed-off-by: Fabien Dessenne Link: https://lore.kernel.org/r/20210617144602.2557619-1-fabien.dessenne@foss.st.com Signed-off-by: Linus Walleij --- drivers/pinctrl/stm32/pinctrl-stm32.c | 79 ++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index ad9eb5ed8e81..63e0c78d4a7e 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -414,57 +414,25 @@ static int stm32_gpio_domain_activate(struct irq_domain *d, { struct stm32_gpio_bank *bank = d->host_data; struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); - unsigned long flags; int ret = 0; - /* - * gpio irq mux is shared between several banks, a lock has to be done - * to avoid overriding. - */ - spin_lock_irqsave(&pctl->irqmux_lock, flags); - if (pctl->hwlock) { ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, HWSPNLCK_TIMEOUT); if (ret) { dev_err(pctl->dev, "Can't get hwspinlock\n"); - goto unlock; + return ret; } } - if (pctl->irqmux_map & BIT(irq_data->hwirq)) { - dev_err(pctl->dev, "irq line %ld already requested.\n", - irq_data->hwirq); - ret = -EBUSY; - if (pctl->hwlock) - hwspin_unlock_in_atomic(pctl->hwlock); - goto unlock; - } else { - pctl->irqmux_map |= BIT(irq_data->hwirq); - } - regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); if (pctl->hwlock) hwspin_unlock_in_atomic(pctl->hwlock); -unlock: - spin_unlock_irqrestore(&pctl->irqmux_lock, flags); return ret; } -static void stm32_gpio_domain_deactivate(struct irq_domain *d, - struct irq_data *irq_data) -{ - struct stm32_gpio_bank *bank = d->host_data; - struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); - unsigned long flags; - - spin_lock_irqsave(&pctl->irqmux_lock, flags); - pctl->irqmux_map &= ~BIT(irq_data->hwirq); - spin_unlock_irqrestore(&pctl->irqmux_lock, flags); -} - static int stm32_gpio_domain_alloc(struct irq_domain *d, unsigned int virq, unsigned int nr_irqs, void *data) @@ -472,9 +440,28 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d, struct stm32_gpio_bank *bank = d->host_data; struct irq_fwspec *fwspec = data; struct irq_fwspec parent_fwspec; - irq_hw_number_t hwirq; + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + irq_hw_number_t hwirq = fwspec->param[0]; + unsigned long flags; + int ret = 0; + + /* + * Check first that the IRQ MUX of that line is free. + * gpio irq mux is shared between several banks, protect with a lock + */ + spin_lock_irqsave(&pctl->irqmux_lock, flags); + + if (pctl->irqmux_map & BIT(hwirq)) { + dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq); + ret = -EBUSY; + } else { + pctl->irqmux_map |= BIT(hwirq); + } + + spin_unlock_irqrestore(&pctl->irqmux_lock, flags); + if (ret) + return ret; - hwirq = fwspec->param[0]; parent_fwspec.fwnode = d->parent->fwnode; parent_fwspec.param_count = 2; parent_fwspec.param[0] = fwspec->param[0]; @@ -486,12 +473,26 @@ static int stm32_gpio_domain_alloc(struct irq_domain *d, return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); } +static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq, + unsigned int nr_irqs) +{ + struct stm32_gpio_bank *bank = d->host_data; + struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); + struct irq_data *irq_data = irq_domain_get_irq_data(d, virq); + unsigned long flags, hwirq = irq_data->hwirq; + + irq_domain_free_irqs_common(d, virq, nr_irqs); + + spin_lock_irqsave(&pctl->irqmux_lock, flags); + pctl->irqmux_map &= ~BIT(hwirq); + spin_unlock_irqrestore(&pctl->irqmux_lock, flags); +} + static const struct irq_domain_ops stm32_gpio_domain_ops = { - .translate = stm32_gpio_domain_translate, - .alloc = stm32_gpio_domain_alloc, - .free = irq_domain_free_irqs_common, + .translate = stm32_gpio_domain_translate, + .alloc = stm32_gpio_domain_alloc, + .free = stm32_gpio_domain_free, .activate = stm32_gpio_domain_activate, - .deactivate = stm32_gpio_domain_deactivate, }; /* Pinctrl functions */ -- cgit v1.2.3 From bfa50166cd9d5d190b20dc33d1ec7ae19ced7022 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Tue, 29 Jun 2021 16:34:07 +0200 Subject: pinctrl: ralink: rt305x: add missing include Header 'rt305x.h' is ralink architecture dependent file where other general definitions which are in 'ralink_regs.h' are being used. This 'rt305x.h' is only being included in two different files: 'rt305x.c' and 'pinctrl-rt305x.c'. When file 'pinctrl-rt305x.c' is being compiled definitions in 'ralink_regs.h' are need to build it properly. Hence, add missing include 'ralink_regs.h' in 'pinctrl-rt305x.c' source to avoid compilation problems. Fixes: 3a1b0ca5a83b ("pinctrl: ralink: move RT305X SoC pinmux config into a new 'pinctrl-rt305x.c' file") Reported-by: kernel test robot Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20210629143407.14703-1-sergio.paracuellos@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/ralink/pinctrl-rt305x.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/ralink/pinctrl-rt305x.c b/drivers/pinctrl/ralink/pinctrl-rt305x.c index 699fe18e7000..5d8fa156c003 100644 --- a/drivers/pinctrl/ralink/pinctrl-rt305x.c +++ b/drivers/pinctrl/ralink/pinctrl-rt305x.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only +#include #include #include #include -- cgit v1.2.3