From f8bd3c82bf7d7d602f7ee219b8e68ac4dac0a3c5 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 19 Jul 2021 16:24:55 -0500 Subject: arm64: dts: qcom: sc7280: add IPA information Add IPA-related nodes and definitions to "sc7280.dtsi", including the reserved memory area used for AP-based IPA firmware loading. Signed-off-by: Alex Elder Signed-off-by: David S. Miller --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a8c274ad74c4..5eb2b58ea23b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -63,6 +64,11 @@ no-map; reg = <0x0 0x80b00000 0x0 0x100000>; }; + + ipa_fw_mem: memory@8b700000 { + reg = <0 0x8b700000 0 0x10000>; + no-map; + }; }; cpus { @@ -508,6 +514,43 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + ipa: ipa@1e40000 { + compatible = "qcom,sc7280-ipa"; + + iommus = <&apps_smmu 0x480 0x0>, + <&apps_smmu 0x482 0x0>; + reg = <0 0x1e40000 0 0x8000>, + <0 0x1e50000 0 0x4ad0>, + <0 0x1e04000 0 0x23000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, + <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; + interconnect-names = "memory", + "config"; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex", "syscon"; reg = <0 0x01f40000 0 0x40000>; -- cgit v1.2.3 From fd0f72c34bd96a1138b89585ce6bfcd9617ea81e Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 19 Jul 2021 16:24:56 -0500 Subject: arm64: dts: qcom: sc7180: define ipa_fw_mem node Define the reserved memory space used for IPA firmware for the Qualcomm SC7180 SoC. Signed-off-by: Alex Elder Signed-off-by: David S. Miller --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a5d58eb92896..7af551a1fd90 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -110,6 +110,11 @@ no-map; }; + ipa_fw_mem: memory@8b700000 { + reg = <0 0x8b700000 0 0x10000>; + no-map; + }; + rmtfs_mem: memory@94600000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x94600000 0x0 0x200000>; -- cgit v1.2.3 From 41667a933c8ad141d0ba79d98e5f6458e7e66864 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Mon, 19 Jul 2021 15:18:21 +0800 Subject: arm64: dts: imx8mp: change interrupt order per dt-binding This patch changs interrupt order which found by dtbs_check. $ make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/net/nxp,dwmac-imx.yaml arch/arm64/boot/dts/freescale/imx8mp-evk.dt.yaml: ethernet@30bf0000: interrupt-names:0: 'macirq' was expected arch/arm64/boot/dts/freescale/imx8mp-evk.dt.yaml: ethernet@30bf0000: interrupt-names:1: 'eth_wake_irq' was expected According to Documentation/devicetree/bindings/net/snps,dwmac.yaml, we should list interrupt in it's order. Signed-off-by: Joakim Zhang Signed-off-by: David S. Miller --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9f7c7f587d38..ca38d0d6c3c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -821,9 +821,9 @@ eqos: ethernet@30bf0000 { compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; reg = <0x30bf0000 0x10000>; - interrupts = , - ; - interrupt-names = "eth_wake_irq", "macirq"; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, <&clk IMX8MP_CLK_QOS_ENET_ROOT>, <&clk IMX8MP_CLK_ENET_QOS_TIMER>, -- cgit v1.2.3 From a758dee8ac50cdabc1229ca82bc7472752a51e1d Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Wed, 28 Jul 2021 19:52:02 +0800 Subject: arm64: dts: imx8m: add "fsl,imx8mq-fec" compatible string for FEC Add "fsl,imx8mq-fec" compatible string for FEC to support new feature (IEEE 802.3az EEE standard). Signed-off-by: Joakim Zhang Signed-off-by: David S. Miller --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index e7648c3b8390..1608a48495b6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -920,7 +920,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index d4231e061403..e6de293865b0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -923,7 +923,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , -- cgit v1.2.3 From 987e1b96d056d81e6253ba1b1e80a4fd7b7b68a1 Mon Sep 17 00:00:00 2001 From: Joakim Zhang Date: Wed, 28 Jul 2021 19:52:03 +0800 Subject: arm64: dts: imx8qxp: add "fsl,imx8qm-fec" compatible string for FEC Add "fsl,imx8qm-fec" compatible string for FEC to support new feature (RGMII delayed clock). Signed-off-by: Joakim Zhang Signed-off-by: David S. Miller --- arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi index f5f58959f65c..46da21af3702 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi @@ -17,9 +17,9 @@ }; &fec1 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec"; }; &fec2 { - compatible = "fsl,imx8qxp-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8qxp-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec"; }; -- cgit v1.2.3 From a0221a0f9ba5820c4a5c0625f965684c6fe76ad7 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 2 Aug 2021 18:30:19 -0500 Subject: Revert "Merge branch 'qcom-dts-updates'" This reverts commit b79c6fba6cd7c49a7dbea9999e182f74cca63e19, reversing these changes made to 0ac26271344478ff718329fa9d4ef81d4bcbc43b: commit 6a0eb6c9d934 ("dt-bindings: net: qcom,ipa: make imem interconnect optional") commit f8bd3c82bf7d ("arm64: dts: qcom: sc7280: add IPA information") commit fd0f72c34bd9 ("arm64: dts: qcom: sc7180: define ipa_fw_mem node") I intend for these commits to go through the Qualcomm repository, to avoid conflicting with other activity being merged there. Signed-off-by: Alex Elder Link: https://lore.kernel.org/r/20210802233019.800250-1-elder@linaro.org Signed-off-by: Jakub Kicinski --- .../devicetree/bindings/net/qcom,ipa.yaml | 18 ++++----- arch/arm64/boot/dts/qcom/sc7180.dtsi | 5 --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ---------------------- 3 files changed, 8 insertions(+), 58 deletions(-) (limited to 'arch/arm64/boot') diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index 4853ab7017bd..ed88ba4b94df 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -87,18 +87,16 @@ properties: - const: ipa-setup-ready interconnects: - minItems: 2 items: - - description: Path leading to system memory - - description: Path between the AP and IPA config space - - description: Path leading to internal memory + - description: Interconnect path between IPA and main memory + - description: Interconnect path between IPA and internal memory + - description: Interconnect path between IPA and the AP subsystem interconnect-names: - minItems: 2 items: - const: memory - - const: config - const: imem + - const: config qcom,smem-states: $ref: /schemas/types.yaml#/definitions/phandle-array @@ -209,11 +207,11 @@ examples: interconnects = <&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_EBI1>, - <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_IPA_CFG>, - <&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_IMEM>; + <&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_IMEM>, + <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_IPA_CFG>; interconnect-names = "memory", - "config", - "imem"; + "imem", + "config"; qcom,smem-states = <&ipa_smp2p_out 0>, <&ipa_smp2p_out 1>; diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 7e0ff917e548..a9a052f8c63c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -110,11 +110,6 @@ no-map; }; - ipa_fw_mem: memory@8b700000 { - reg = <0 0x8b700000 0 0x10000>; - no-map; - }; - rmtfs_mem: memory@94600000 { compatible = "qcom,rmtfs-mem"; reg = <0x0 0x94600000 0x0 0x200000>; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5eb2b58ea23b..a8c274ad74c4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -64,11 +63,6 @@ no-map; reg = <0x0 0x80b00000 0x0 0x100000>; }; - - ipa_fw_mem: memory@8b700000 { - reg = <0 0x8b700000 0 0x10000>; - no-map; - }; }; cpus { @@ -514,43 +508,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa: ipa@1e40000 { - compatible = "qcom,sc7280-ipa"; - - iommus = <&apps_smmu 0x480 0x0>, - <&apps_smmu 0x482 0x0>; - reg = <0 0x1e40000 0 0x8000>, - <0 0x1e50000 0 0x4ad0>, - <0 0x1e04000 0 0x23000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; - interconnect-names = "memory", - "config"; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; - - status = "disabled"; - }; - tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex", "syscon"; reg = <0 0x01f40000 0 0x40000>; -- cgit v1.2.3 From 920c293af8d01942caa10300ad97eabf778e8598 Mon Sep 17 00:00:00 2001 From: Steen Hegelund Date: Thu, 19 Aug 2021 09:39:40 +0200 Subject: arm64: dts: sparx5: Add the Sparx5 switch frame DMA support This adds the interrupt for the Sparx5 Frame DMA. If this configuration is present the Sparx5 SwitchDev driver will use the Frame DMA feature, and if not it will use register based injection and extraction for sending and receiving frames to the CPU. Signed-off-by: Steen Hegelund Signed-off-by: David S. Miller --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm64/boot') diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index ad07fff40544..787ebcec121d 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -471,8 +471,9 @@ <0x6 0x10004000 0x7fc000>, <0x6 0x11010000 0xaf0000>; reg-names = "cpu", "dev", "gcb"; - interrupt-names = "xtr"; - interrupts = ; + interrupt-names = "xtr", "fdma"; + interrupts = , + ; resets = <&reset 0>; reset-names = "switch"; }; -- cgit v1.2.3